| stats.txt (11456:c0fb4435b80f) | stats.txt (11502:e273e86a873d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 47.468752 # Number of seconds simulated 4sim_ticks 47468751978000 # Number of ticks simulated 5final_tick 47468751978000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 47.384315 # Number of seconds simulated 4sim_ticks 47384315163000 # Number of ticks simulated 5final_tick 47384315163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 133266 # Simulator instruction rate (inst/s) 8host_op_rate 156717 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6699893970 # Simulator tick rate (ticks/s) 10host_mem_usage 769956 # Number of bytes of host memory used 11host_seconds 7085.00 # Real time elapsed on the host 12sim_insts 944191442 # Number of instructions simulated 13sim_ops 1110340105 # Number of ops (including micro ops) simulated | 7host_inst_rate 172390 # Simulator instruction rate (inst/s) 8host_op_rate 202727 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9043218476 # Simulator tick rate (ticks/s) 10host_mem_usage 765852 # Number of bytes of host memory used 11host_seconds 5239.76 # Real time elapsed on the host 12sim_insts 903281747 # Number of instructions simulated 13sim_ops 1062243320 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu0.dtb.walker 171136 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 120960 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 3861216 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 14070216 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 17654336 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 218240 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 209216 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 3621984 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 13693456 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 20748864 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 405504 # Number of bytes read from this memory 27system.physmem.bytes_read::total 74775128 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 3861216 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 3621984 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 7483200 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 90808384 # Number of bytes written to this memory | 16system.physmem.bytes_read::cpu0.dtb.walker 88320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 58304 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 4233376 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 12825352 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 13896960 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 201536 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 189312 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 2647264 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 11439440 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 16431296 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 444928 # Number of bytes read from this memory 27system.physmem.bytes_read::total 62456088 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 4233376 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 2647264 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 6880640 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 79489088 # Number of bytes written to this memory |
| 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory | 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory |
| 34system.physmem.bytes_written::total 90828968 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 2674 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1890 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 76284 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 219860 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 275849 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 3410 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 3269 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 56637 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 213973 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 324201 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6336 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 1184383 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1418881 # Number of write requests responded to by this memory | 34system.physmem.bytes_written::total 79509672 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 1380 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 911 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 82099 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 200409 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 217140 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 3149 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 2958 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 41407 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 178754 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 256739 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6952 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 991898 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1242017 # Number of write requests responded to by this memory |
| 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory | 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory |
| 50system.physmem.num_writes::total 1421455 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 3605 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 2548 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 81342 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 296410 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 371915 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 4598 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 4407 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 76302 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 288473 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 437106 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 8543 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1575250 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 81342 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 76302 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 157645 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1913014 # Write bandwidth from this memory (bytes/s) | 50system.physmem.num_writes::total 1244591 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 1864 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 1230 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 89341 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 270667 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 293282 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 4253 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 3995 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 55868 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 241418 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 346767 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9390 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1318075 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 89341 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 55868 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 145209 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1677540 # Write bandwidth from this memory (bytes/s) |
| 67system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) | 67system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) |
| 69system.physmem.bw_write::total 1913448 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1913014 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 3605 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 2548 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 81342 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 296844 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 371915 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 4598 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 4407 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 76302 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 288473 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 437106 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 8543 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 3488697 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 1184383 # Number of read requests accepted 84system.physmem.writeReqs 1421455 # Number of write requests accepted 85system.physmem.readBursts 1184383 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1421455 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 75776512 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 24000 # Total number of bytes read from write queue 89system.physmem.bytesWritten 90827456 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 74775128 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 90828968 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 375 # Number of DRAM read bursts serviced by the write queue | 69system.physmem.bw_write::total 1677974 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1677540 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 1864 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 1230 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 89341 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 271101 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 293282 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 4253 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 3995 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 55868 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 241418 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 346767 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9390 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 2996050 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 991898 # Number of read requests accepted 84system.physmem.writeReqs 1244591 # Number of write requests accepted 85system.physmem.readBursts 991898 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1244591 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 63457600 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 23872 # Total number of bytes read from write queue 89system.physmem.bytesWritten 79508544 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 62456088 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 79509672 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 373 # Number of DRAM read bursts serviced by the write queue |
| 93system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 93system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 95system.physmem.perBankRdBursts::0 72103 # Per bank write bursts 96system.physmem.perBankRdBursts::1 78803 # Per bank write bursts 97system.physmem.perBankRdBursts::2 72464 # Per bank write bursts 98system.physmem.perBankRdBursts::3 70552 # Per bank write bursts 99system.physmem.perBankRdBursts::4 69846 # Per bank write bursts 100system.physmem.perBankRdBursts::5 79143 # Per bank write bursts 101system.physmem.perBankRdBursts::6 69266 # Per bank write bursts 102system.physmem.perBankRdBursts::7 70722 # Per bank write bursts 103system.physmem.perBankRdBursts::8 68903 # Per bank write bursts 104system.physmem.perBankRdBursts::9 99020 # Per bank write bursts 105system.physmem.perBankRdBursts::10 71711 # Per bank write bursts 106system.physmem.perBankRdBursts::11 73604 # Per bank write bursts 107system.physmem.perBankRdBursts::12 71852 # Per bank write bursts 108system.physmem.perBankRdBursts::13 74765 # Per bank write bursts 109system.physmem.perBankRdBursts::14 70123 # Per bank write bursts 110system.physmem.perBankRdBursts::15 71131 # Per bank write bursts 111system.physmem.perBankWrBursts::0 89065 # Per bank write bursts 112system.physmem.perBankWrBursts::1 93300 # Per bank write bursts 113system.physmem.perBankWrBursts::2 85781 # Per bank write bursts 114system.physmem.perBankWrBursts::3 86502 # Per bank write bursts 115system.physmem.perBankWrBursts::4 86907 # Per bank write bursts 116system.physmem.perBankWrBursts::5 92159 # Per bank write bursts 117system.physmem.perBankWrBursts::6 86239 # Per bank write bursts 118system.physmem.perBankWrBursts::7 88123 # Per bank write bursts 119system.physmem.perBankWrBursts::8 85047 # Per bank write bursts 120system.physmem.perBankWrBursts::9 93098 # Per bank write bursts 121system.physmem.perBankWrBursts::10 87729 # Per bank write bursts 122system.physmem.perBankWrBursts::11 90867 # Per bank write bursts 123system.physmem.perBankWrBursts::12 86341 # Per bank write bursts 124system.physmem.perBankWrBursts::13 90891 # Per bank write bursts 125system.physmem.perBankWrBursts::14 88902 # Per bank write bursts 126system.physmem.perBankWrBursts::15 88228 # Per bank write bursts | 95system.physmem.perBankRdBursts::0 57534 # Per bank write bursts 96system.physmem.perBankRdBursts::1 67322 # Per bank write bursts 97system.physmem.perBankRdBursts::2 57239 # Per bank write bursts 98system.physmem.perBankRdBursts::3 59640 # Per bank write bursts 99system.physmem.perBankRdBursts::4 58543 # Per bank write bursts 100system.physmem.perBankRdBursts::5 68655 # Per bank write bursts 101system.physmem.perBankRdBursts::6 57471 # Per bank write bursts 102system.physmem.perBankRdBursts::7 60839 # Per bank write bursts 103system.physmem.perBankRdBursts::8 60208 # Per bank write bursts 104system.physmem.perBankRdBursts::9 81942 # Per bank write bursts 105system.physmem.perBankRdBursts::10 59318 # Per bank write bursts 106system.physmem.perBankRdBursts::11 61436 # Per bank write bursts 107system.physmem.perBankRdBursts::12 60309 # Per bank write bursts 108system.physmem.perBankRdBursts::13 62906 # Per bank write bursts 109system.physmem.perBankRdBursts::14 58748 # Per bank write bursts 110system.physmem.perBankRdBursts::15 59415 # Per bank write bursts 111system.physmem.perBankWrBursts::0 74024 # Per bank write bursts 112system.physmem.perBankWrBursts::1 81724 # Per bank write bursts 113system.physmem.perBankWrBursts::2 74878 # Per bank write bursts 114system.physmem.perBankWrBursts::3 76858 # Per bank write bursts 115system.physmem.perBankWrBursts::4 76593 # Per bank write bursts 116system.physmem.perBankWrBursts::5 82864 # Per bank write bursts 117system.physmem.perBankWrBursts::6 74278 # Per bank write bursts 118system.physmem.perBankWrBursts::7 78173 # Per bank write bursts 119system.physmem.perBankWrBursts::8 76626 # Per bank write bursts 120system.physmem.perBankWrBursts::9 80136 # Per bank write bursts 121system.physmem.perBankWrBursts::10 77163 # Per bank write bursts 122system.physmem.perBankWrBursts::11 80655 # Per bank write bursts 123system.physmem.perBankWrBursts::12 76245 # Per bank write bursts 124system.physmem.perBankWrBursts::13 79687 # Per bank write bursts 125system.physmem.perBankWrBursts::14 75064 # Per bank write bursts 126system.physmem.perBankWrBursts::15 77353 # Per bank write bursts |
| 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 128system.physmem.numWrRetry 43 # Number of times write queue was full causing retry 129system.physmem.totGap 47468750370500 # Total gap between requests | 128system.physmem.numWrRetry 51477 # Number of times write queue was full causing retry 129system.physmem.totGap 47384313590500 # Total gap between requests |
| 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 21333 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) | 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 21333 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 136system.physmem.readPktSize::6 1163025 # Read request sizes (log2) | 136system.physmem.readPktSize::6 970540 # Read request sizes (log2) |
| 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) | 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 143system.physmem.writePktSize::6 1418881 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 512770 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 308725 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 87137 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 63943 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 45149 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 40149 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 37001 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 34987 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 30693 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 8585 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 4718 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 2994 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 2073 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 1609 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 1005 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 881 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 765 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 567 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 148 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 96 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 9 # What read queue length does an incoming req see | 143system.physmem.writePktSize::6 1242017 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 445378 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 243433 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 76996 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 56880 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 37150 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 31949 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 29173 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 27068 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 25124 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 6848 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 3836 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 2454 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 1543 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 1198 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 708 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 591 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 507 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 398 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 167 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 104 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see |
| 165system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see --- 10 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 165system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see --- 10 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 191system.physmem.wrQLenPdf::15 26847 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 31854 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 44695 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 49676 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 56919 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 61698 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 67754 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 74407 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 81101 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 85167 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 89920 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 95633 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 94983 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 99480 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 111361 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 98562 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 89368 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 83432 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 13050 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 9803 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 8425 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 6741 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 5561 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 4626 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 3942 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 3261 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 2837 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 2381 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 2058 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 1909 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 1685 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 1499 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 1391 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 1145 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 1040 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 919 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 710 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 666 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 524 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 403 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 368 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 321 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 250 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 182 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 161 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 165 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 132 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 77 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 105 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 1159540 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 143.680535 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 97.586865 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 190.741453 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 783407 67.56% 67.56% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 222260 19.17% 86.73% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 55727 4.81% 91.54% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 24890 2.15% 93.68% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 21192 1.83% 95.51% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 11987 1.03% 96.54% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 8178 0.71% 97.25% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 4967 0.43% 97.68% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 26932 2.32% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 1159540 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 67946 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 17.425117 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 68.584486 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-511 67943 100.00% 100.00% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::512-1023 1 0.00% 100.00% # Reads before turning the bus around for writes | 191system.physmem.wrQLenPdf::15 23188 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 27066 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 36083 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 41131 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 44808 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 48159 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 53054 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 57269 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 61997 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 63720 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 68707 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 72599 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 69938 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 72538 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 82492 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 73770 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 67397 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 63055 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 4615 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 3320 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 2487 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 2032 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 1667 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 1537 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 1438 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 1351 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 1216 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 1258 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 1384 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 1422 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 1370 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 1543 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 1563 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 1451 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 1716 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 1865 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 2021 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 2168 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 2359 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 2664 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 2841 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 3106 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 3376 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 3630 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 3943 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 4563 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 6136 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 24445 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 120872 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 982131 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 145.566960 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 98.657532 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 193.069606 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 654413 66.63% 66.63% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 194527 19.81% 86.44% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 50477 5.14% 91.58% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 21176 2.16% 93.73% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 16419 1.67% 95.41% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 9395 0.96% 96.36% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 6596 0.67% 97.03% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 5289 0.54% 97.57% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 23839 2.43% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 982131 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 56922 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 17.418608 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 74.895923 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-511 56917 99.99% 99.99% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::512-1023 2 0.00% 99.99% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes |
| 259system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes | 260system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes |
| 261system.physmem.rdPerTurnAround::total 67946 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 67946 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 20.886866 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 17.982744 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 74.693624 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::0-127 67692 99.63% 99.63% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::128-255 167 0.25% 99.87% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::256-383 12 0.02% 99.89% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::384-511 13 0.02% 99.91% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::512-639 10 0.01% 99.92% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::640-767 5 0.01% 99.93% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::768-895 6 0.01% 99.94% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::896-1023 2 0.00% 99.94% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::1024-1151 3 0.00% 99.95% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::1152-1279 3 0.00% 99.95% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::1280-1407 1 0.00% 99.95% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::1408-1535 3 0.00% 99.96% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::1536-1663 1 0.00% 99.96% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::1664-1791 2 0.00% 99.96% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::1792-1919 3 0.00% 99.97% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::1920-2047 1 0.00% 99.97% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::2048-2175 1 0.00% 99.97% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::2176-2303 2 0.00% 99.97% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::2432-2559 1 0.00% 99.97% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::2560-2687 2 0.00% 99.98% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::2688-2815 1 0.00% 99.98% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::2944-3071 1 0.00% 99.98% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::3072-3199 1 0.00% 99.98% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::3200-3327 1 0.00% 99.98% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::3584-3711 1 0.00% 99.98% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::3840-3967 2 0.00% 99.99% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::3968-4095 3 0.00% 99.99% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::4224-4351 3 0.00% 100.00% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::4736-4863 1 0.00% 100.00% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::5760-5887 1 0.00% 100.00% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::6528-6655 1 0.00% 100.00% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::total 67946 # Writes before turning the bus around for reads 298system.physmem.totQLat 53444908202 # Total ticks spent queuing 299system.physmem.totMemAccLat 75645058202 # Total ticks spent from burst creation until serviced by the DRAM 300system.physmem.totBusLat 5920040000 # Total ticks spent in databus transfers 301system.physmem.avgQLat 45138.98 # Average queueing delay per DRAM burst | 262system.physmem.rdPerTurnAround::total 56922 # Reads before turning the bus around for writes 263system.physmem.wrPerTurnAround::samples 56922 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::mean 21.824971 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::gmean 17.750218 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::stdev 638.100533 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::0-4095 56920 100.00% 100.00% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::45056-49151 1 0.00% 100.00% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::143360-147455 1 0.00% 100.00% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::total 56922 # Writes before turning the bus around for reads 271system.physmem.totQLat 43578574020 # Total ticks spent queuing 272system.physmem.totMemAccLat 62169667770 # Total ticks spent from burst creation until serviced by the DRAM 273system.physmem.totBusLat 4957625000 # Total ticks spent in databus transfers 274system.physmem.avgQLat 43951.06 # Average queueing delay per DRAM burst |
| 302system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 275system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 303system.physmem.avgMemAccLat 63888.98 # Average memory access latency per DRAM burst 304system.physmem.avgRdBW 1.60 # Average DRAM read bandwidth in MiByte/s 305system.physmem.avgWrBW 1.91 # Average achieved write bandwidth in MiByte/s 306system.physmem.avgRdBWSys 1.58 # Average system read bandwidth in MiByte/s 307system.physmem.avgWrBWSys 1.91 # Average system write bandwidth in MiByte/s | 276system.physmem.avgMemAccLat 62701.06 # Average memory access latency per DRAM burst 277system.physmem.avgRdBW 1.34 # Average DRAM read bandwidth in MiByte/s 278system.physmem.avgWrBW 1.68 # Average achieved write bandwidth in MiByte/s 279system.physmem.avgRdBWSys 1.32 # Average system read bandwidth in MiByte/s 280system.physmem.avgWrBWSys 1.68 # Average system write bandwidth in MiByte/s |
| 308system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 281system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 309system.physmem.busUtil 0.03 # Data bus utilization in percentage | 282system.physmem.busUtil 0.02 # Data bus utilization in percentage |
| 310system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 311system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes | 283system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 284system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes |
| 312system.physmem.avgRdQLen 2.06 # Average read queue length when enqueuing 313system.physmem.avgWrQLen 23.70 # Average write queue length when enqueuing 314system.physmem.readRowHits 894156 # Number of row buffer hits during reads 315system.physmem.writeRowHits 549489 # Number of row buffer hits during writes 316system.physmem.readRowHitRate 75.52 # Row buffer hit rate for reads 317system.physmem.writeRowHitRate 38.72 # Row buffer hit rate for writes 318system.physmem.avgGap 18216309.06 # Average gap between requests 319system.physmem.pageHitRate 55.46 # Row buffer hit rate, read and write combined 320system.physmem_0.actEnergy 4374828360 # Energy for activate commands per rank (pJ) 321system.physmem_0.preEnergy 2387059125 # Energy for precharge commands per rank (pJ) 322system.physmem_0.readEnergy 4546612200 # Energy for read commands per rank (pJ) 323system.physmem_0.writeEnergy 4588332480 # Energy for write commands per rank (pJ) 324system.physmem_0.refreshEnergy 3100427903040 # Energy for refresh commands per rank (pJ) 325system.physmem_0.actBackEnergy 1181604436515 # Energy for active background per rank (pJ) 326system.physmem_0.preBackEnergy 27444754155000 # Energy for precharge background per rank (pJ) 327system.physmem_0.totalEnergy 31742683326720 # Total energy per rank (pJ) 328system.physmem_0.averagePower 668.706973 # Core power per rank (mW) 329system.physmem_0.memoryStateTime::IDLE 45656629611476 # Time in different power states 330system.physmem_0.memoryStateTime::REF 1585085840000 # Time in different power states | 285system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing 286system.physmem.avgWrQLen 23.75 # Average write queue length when enqueuing 287system.physmem.readRowHits 750886 # Number of row buffer hits during reads 288system.physmem.writeRowHits 500828 # Number of row buffer hits during writes 289system.physmem.readRowHitRate 75.73 # Row buffer hit rate for reads 290system.physmem.writeRowHitRate 40.31 # Row buffer hit rate for writes 291system.physmem.avgGap 21186920.03 # Average gap between requests 292system.physmem.pageHitRate 56.03 # Row buffer hit rate, read and write combined 293system.physmem_0.actEnergy 3717395640 # Energy for activate commands per rank (pJ) 294system.physmem_0.preEnergy 2028340875 # Energy for precharge commands per rank (pJ) 295system.physmem_0.readEnergy 3800456400 # Energy for read commands per rank (pJ) 296system.physmem_0.writeEnergy 4013660160 # Energy for write commands per rank (pJ) 297system.physmem_0.refreshEnergy 3094913078400 # Energy for refresh commands per rank (pJ) 298system.physmem_0.actBackEnergy 1158326321940 # Energy for active background per rank (pJ) 299system.physmem_0.preBackEnergy 27414513105000 # Energy for precharge background per rank (pJ) 300system.physmem_0.totalEnergy 31681312358415 # Total energy per rank (pJ) 301system.physmem_0.averagePower 668.603367 # Core power per rank (mW) 302system.physmem_0.memoryStateTime::IDLE 45606511009457 # Time in different power states 303system.physmem_0.memoryStateTime::REF 1582266400000 # Time in different power states |
| 331system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 304system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 332system.physmem_0.memoryStateTime::ACT 227033353524 # Time in different power states | 305system.physmem_0.memoryStateTime::ACT 195537314293 # Time in different power states |
| 333system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 306system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 334system.physmem_1.actEnergy 4391294040 # Energy for activate commands per rank (pJ) 335system.physmem_1.preEnergy 2396043375 # Energy for precharge commands per rank (pJ) 336system.physmem_1.readEnergy 4688572200 # Energy for read commands per rank (pJ) 337system.physmem_1.writeEnergy 4607947440 # Energy for write commands per rank (pJ) 338system.physmem_1.refreshEnergy 3100427903040 # Energy for refresh commands per rank (pJ) 339system.physmem_1.actBackEnergy 1183305976290 # Energy for active background per rank (pJ) 340system.physmem_1.preBackEnergy 27443261584500 # Energy for precharge background per rank (pJ) 341system.physmem_1.totalEnergy 31743079320885 # Total energy per rank (pJ) 342system.physmem_1.averagePower 668.715315 # Core power per rank (mW) 343system.physmem_1.memoryStateTime::IDLE 45654123959514 # Time in different power states 344system.physmem_1.memoryStateTime::REF 1585085840000 # Time in different power states | 307system.physmem_1.actEnergy 3707514720 # Energy for activate commands per rank (pJ) 308system.physmem_1.preEnergy 2022949500 # Energy for precharge commands per rank (pJ) 309system.physmem_1.readEnergy 3933399600 # Energy for read commands per rank (pJ) 310system.physmem_1.writeEnergy 4036579920 # Energy for write commands per rank (pJ) 311system.physmem_1.refreshEnergy 3094913078400 # Energy for refresh commands per rank (pJ) 312system.physmem_1.actBackEnergy 1156667621085 # Energy for active background per rank (pJ) 313system.physmem_1.preBackEnergy 27415968105750 # Energy for precharge background per rank (pJ) 314system.physmem_1.totalEnergy 31681249248975 # Total energy per rank (pJ) 315system.physmem_1.averagePower 668.602035 # Core power per rank (mW) 316system.physmem_1.memoryStateTime::IDLE 45608919765384 # Time in different power states 317system.physmem_1.memoryStateTime::REF 1582266400000 # Time in different power states |
| 345system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 318system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 346system.physmem_1.memoryStateTime::ACT 229539287986 # Time in different power states | 319system.physmem_1.memoryStateTime::ACT 193128558366 # Time in different power states |
| 347system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 348system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory 349system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 350system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory 351system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 352system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory 353system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory 354system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory --- 17 unchanged lines hidden (view full) --- 372system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 373system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) 374system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 375system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 376system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 377system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 378system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 379system.cf0.dma_write_txs 1670 # Number of DMA write transactions. | 320system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 321system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory 322system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 323system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory 324system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 325system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory 326system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory 327system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory --- 17 unchanged lines hidden (view full) --- 345system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 346system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) 347system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 348system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 349system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 350system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 351system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 352system.cf0.dma_write_txs 1670 # Number of DMA write transactions. |
| 380system.cpu0.branchPred.lookups 132444225 # Number of BP lookups 381system.cpu0.branchPred.condPredicted 87787955 # Number of conditional branches predicted 382system.cpu0.branchPred.condIncorrect 6400754 # Number of conditional branches incorrect 383system.cpu0.branchPred.BTBLookups 93524644 # Number of BTB lookups 384system.cpu0.branchPred.BTBHits 57612051 # Number of BTB hits | 353system.cpu0.branchPred.lookups 138091637 # Number of BP lookups 354system.cpu0.branchPred.condPredicted 91311717 # Number of conditional branches predicted 355system.cpu0.branchPred.condIncorrect 6789940 # Number of conditional branches incorrect 356system.cpu0.branchPred.BTBLookups 97223509 # Number of BTB lookups 357system.cpu0.branchPred.BTBHits 59866310 # Number of BTB hits |
| 385system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 358system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 386system.cpu0.branchPred.BTBHitPct 61.600931 # BTB Hit Percentage 387system.cpu0.branchPred.usedRAS 17778768 # Number of times the RAS was used to get a target. 388system.cpu0.branchPred.RASInCorrect 168825 # Number of incorrect RAS predictions. 389system.cpu0.branchPred.indirectLookups 4144770 # Number of indirect predictor lookups. 390system.cpu0.branchPred.indirectHits 2586947 # Number of indirect target hits. 391system.cpu0.branchPred.indirectMisses 1557823 # Number of indirect misses. 392system.cpu0.branchPredindirectMispredicted 392899 # Number of mispredicted indirect branches. | 359system.cpu0.branchPred.BTBHitPct 61.575961 # BTB Hit Percentage 360system.cpu0.branchPred.usedRAS 18644167 # Number of times the RAS was used to get a target. 361system.cpu0.branchPred.RASInCorrect 188685 # Number of incorrect RAS predictions. 362system.cpu0.branchPred.indirectLookups 4389066 # Number of indirect predictor lookups. 363system.cpu0.branchPred.indirectHits 2747803 # Number of indirect target hits. 364system.cpu0.branchPred.indirectMisses 1641263 # Number of indirect misses. 365system.cpu0.branchPredindirectMispredicted 409141 # Number of mispredicted indirect branches. |
| 393system.cpu_clk_domain.clock 500 # Clock period in ticks 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 415system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 416system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 417system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 418system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 419system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 420system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 421system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 422system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 366system.cpu_clk_domain.clock 500 # Clock period in ticks 367system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 368system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 369system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 370system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 371system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 372system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 373system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 388system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 389system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 390system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 391system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 392system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 393system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 394system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 395system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 423system.cpu0.dtb.walker.walks 539802 # Table walker walks requested 424system.cpu0.dtb.walker.walksLong 539802 # Table walker walks initiated with long descriptors 425system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11294 # Level at which table walker walks with long descriptors terminate 426system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84152 # Level at which table walker walks with long descriptors terminate 427system.cpu0.dtb.walker.walksSquashedBefore 248635 # Table walks squashed before starting 428system.cpu0.dtb.walker.walkWaitTime::samples 291167 # Table walker wait (enqueue to first request) latency 429system.cpu0.dtb.walker.walkWaitTime::mean 2569.659336 # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkWaitTime::stdev 15605.583986 # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkWaitTime::0-65535 288567 99.11% 99.11% # Table walker wait (enqueue to first request) latency 432system.cpu0.dtb.walker.walkWaitTime::65536-131071 1409 0.48% 99.59% # Table walker wait (enqueue to first request) latency 433system.cpu0.dtb.walker.walkWaitTime::131072-196607 865 0.30% 99.89% # Table walker wait (enqueue to first request) latency 434system.cpu0.dtb.walker.walkWaitTime::196608-262143 174 0.06% 99.95% # Table walker wait (enqueue to first request) latency 435system.cpu0.dtb.walker.walkWaitTime::262144-327679 52 0.02% 99.97% # Table walker wait (enqueue to first request) latency 436system.cpu0.dtb.walker.walkWaitTime::327680-393215 75 0.03% 99.99% # Table walker wait (enqueue to first request) latency 437system.cpu0.dtb.walker.walkWaitTime::393216-458751 18 0.01% 100.00% # Table walker wait (enqueue to first request) latency 438system.cpu0.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency 439system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 440system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 441system.cpu0.dtb.walker.walkWaitTime::total 291167 # Table walker wait (enqueue to first request) latency 442system.cpu0.dtb.walker.walkCompletionTime::samples 273980 # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::mean 20501.036572 # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::gmean 17496.757374 # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::stdev 20192.590719 # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::0-65535 271123 98.96% 98.96% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::65536-131071 705 0.26% 99.21% # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1540 0.56% 99.78% # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walkCompletionTime::196608-262143 149 0.05% 99.83% # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::262144-327679 269 0.10% 99.93% # Table walker service (enqueue to completion) latency 451system.cpu0.dtb.walker.walkCompletionTime::327680-393215 86 0.03% 99.96% # Table walker service (enqueue to completion) latency 452system.cpu0.dtb.walker.walkCompletionTime::393216-458751 62 0.02% 99.98% # Table walker service (enqueue to completion) latency 453system.cpu0.dtb.walker.walkCompletionTime::458752-524287 25 0.01% 99.99% # Table walker service (enqueue to completion) latency 454system.cpu0.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 99.99% # Table walker service (enqueue to completion) latency 455system.cpu0.dtb.walker.walkCompletionTime::589824-655359 8 0.00% 100.00% # Table walker service (enqueue to completion) latency 456system.cpu0.dtb.walker.walkCompletionTime::655360-720895 7 0.00% 100.00% # Table walker service (enqueue to completion) latency 457system.cpu0.dtb.walker.walkCompletionTime::total 273980 # Table walker service (enqueue to completion) latency 458system.cpu0.dtb.walker.walksPending::samples 529053057016 # Table walker pending requests distribution 459system.cpu0.dtb.walker.walksPending::mean 0.549473 # Table walker pending requests distribution 460system.cpu0.dtb.walker.walksPending::stdev 0.550536 # Table walker pending requests distribution 461system.cpu0.dtb.walker.walksPending::0-1 527876290016 99.78% 99.78% # Table walker pending requests distribution 462system.cpu0.dtb.walker.walksPending::2-3 603631000 0.11% 99.89% # Table walker pending requests distribution 463system.cpu0.dtb.walker.walksPending::4-5 259797000 0.05% 99.94% # Table walker pending requests distribution 464system.cpu0.dtb.walker.walksPending::6-7 123836500 0.02% 99.96% # Table walker pending requests distribution 465system.cpu0.dtb.walker.walksPending::8-9 92525500 0.02% 99.98% # Table walker pending requests distribution 466system.cpu0.dtb.walker.walksPending::10-11 56948500 0.01% 99.99% # Table walker pending requests distribution 467system.cpu0.dtb.walker.walksPending::12-13 16655000 0.00% 100.00% # Table walker pending requests distribution 468system.cpu0.dtb.walker.walksPending::14-15 23145000 0.00% 100.00% # Table walker pending requests distribution 469system.cpu0.dtb.walker.walksPending::16-17 228500 0.00% 100.00% # Table walker pending requests distribution 470system.cpu0.dtb.walker.walksPending::total 529053057016 # Table walker pending requests distribution 471system.cpu0.dtb.walker.walkPageSizes::4K 84152 88.17% 88.17% # Table walker page sizes translated 472system.cpu0.dtb.walker.walkPageSizes::2M 11294 11.83% 100.00% # Table walker page sizes translated 473system.cpu0.dtb.walker.walkPageSizes::total 95446 # Table walker page sizes translated 474system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 539802 # Table walker requests started/completed, data/inst | 396system.cpu0.dtb.walker.walks 530338 # Table walker walks requested 397system.cpu0.dtb.walker.walksLong 530338 # Table walker walks initiated with long descriptors 398system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10426 # Level at which table walker walks with long descriptors terminate 399system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79784 # Level at which table walker walks with long descriptors terminate 400system.cpu0.dtb.walker.walksSquashedBefore 241995 # Table walks squashed before starting 401system.cpu0.dtb.walker.walkWaitTime::samples 288343 # Table walker wait (enqueue to first request) latency 402system.cpu0.dtb.walker.walkWaitTime::mean 2099.123266 # Table walker wait (enqueue to first request) latency 403system.cpu0.dtb.walker.walkWaitTime::stdev 12230.418976 # Table walker wait (enqueue to first request) latency 404system.cpu0.dtb.walker.walkWaitTime::0-65535 286535 99.37% 99.37% # Table walker wait (enqueue to first request) latency 405system.cpu0.dtb.walker.walkWaitTime::65536-131071 1269 0.44% 99.81% # Table walker wait (enqueue to first request) latency 406system.cpu0.dtb.walker.walkWaitTime::131072-196607 337 0.12% 99.93% # Table walker wait (enqueue to first request) latency 407system.cpu0.dtb.walker.walkWaitTime::196608-262143 138 0.05% 99.98% # Table walker wait (enqueue to first request) latency 408system.cpu0.dtb.walker.walkWaitTime::262144-327679 37 0.01% 99.99% # Table walker wait (enqueue to first request) latency 409system.cpu0.dtb.walker.walkWaitTime::327680-393215 22 0.01% 100.00% # Table walker wait (enqueue to first request) latency 410system.cpu0.dtb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 411system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 412system.cpu0.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 413system.cpu0.dtb.walker.walkWaitTime::total 288343 # Table walker wait (enqueue to first request) latency 414system.cpu0.dtb.walker.walkCompletionTime::samples 261783 # Table walker service (enqueue to completion) latency 415system.cpu0.dtb.walker.walkCompletionTime::mean 19021.382214 # Table walker service (enqueue to completion) latency 416system.cpu0.dtb.walker.walkCompletionTime::gmean 16878.246550 # Table walker service (enqueue to completion) latency 417system.cpu0.dtb.walker.walkCompletionTime::stdev 10891.763559 # Table walker service (enqueue to completion) latency 418system.cpu0.dtb.walker.walkCompletionTime::0-32767 246122 94.02% 94.02% # Table walker service (enqueue to completion) latency 419system.cpu0.dtb.walker.walkCompletionTime::32768-65535 14409 5.50% 99.52% # Table walker service (enqueue to completion) latency 420system.cpu0.dtb.walker.walkCompletionTime::65536-98303 656 0.25% 99.77% # Table walker service (enqueue to completion) latency 421system.cpu0.dtb.walker.walkCompletionTime::98304-131071 427 0.16% 99.94% # Table walker service (enqueue to completion) latency 422system.cpu0.dtb.walker.walkCompletionTime::131072-163839 44 0.02% 99.95% # Table walker service (enqueue to completion) latency 423system.cpu0.dtb.walker.walkCompletionTime::163840-196607 15 0.01% 99.96% # Table walker service (enqueue to completion) latency 424system.cpu0.dtb.walker.walkCompletionTime::196608-229375 47 0.02% 99.98% # Table walker service (enqueue to completion) latency 425system.cpu0.dtb.walker.walkCompletionTime::229376-262143 25 0.01% 99.99% # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walkCompletionTime::262144-294911 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::294912-327679 22 0.01% 99.99% # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walkCompletionTime::327680-360447 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::360448-393215 5 0.00% 100.00% # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::393216-425983 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::total 261783 # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walksPending::samples 513336492752 # Table walker pending requests distribution 434system.cpu0.dtb.walker.walksPending::mean 0.609866 # Table walker pending requests distribution 435system.cpu0.dtb.walker.walksPending::stdev 0.537961 # Table walker pending requests distribution 436system.cpu0.dtb.walker.walksPending::0-1 512309669252 99.80% 99.80% # Table walker pending requests distribution 437system.cpu0.dtb.walker.walksPending::2-3 522001000 0.10% 99.90% # Table walker pending requests distribution 438system.cpu0.dtb.walker.walksPending::4-5 221126000 0.04% 99.94% # Table walker pending requests distribution 439system.cpu0.dtb.walker.walksPending::6-7 109873500 0.02% 99.97% # Table walker pending requests distribution 440system.cpu0.dtb.walker.walksPending::8-9 86703000 0.02% 99.98% # Table walker pending requests distribution 441system.cpu0.dtb.walker.walksPending::10-11 51185000 0.01% 99.99% # Table walker pending requests distribution 442system.cpu0.dtb.walker.walksPending::12-13 14405500 0.00% 100.00% # Table walker pending requests distribution 443system.cpu0.dtb.walker.walksPending::14-15 21121500 0.00% 100.00% # Table walker pending requests distribution 444system.cpu0.dtb.walker.walksPending::16-17 397500 0.00% 100.00% # Table walker pending requests distribution 445system.cpu0.dtb.walker.walksPending::18-19 10500 0.00% 100.00% # Table walker pending requests distribution 446system.cpu0.dtb.walker.walksPending::total 513336492752 # Table walker pending requests distribution 447system.cpu0.dtb.walker.walkPageSizes::4K 79785 88.44% 88.44% # Table walker page sizes translated 448system.cpu0.dtb.walker.walkPageSizes::2M 10426 11.56% 100.00% # Table walker page sizes translated 449system.cpu0.dtb.walker.walkPageSizes::total 90211 # Table walker page sizes translated 450system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 530338 # Table walker requests started/completed, data/inst |
| 475system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 451system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 476system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 539802 # Table walker requests started/completed, data/inst 477system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 95446 # Table walker requests started/completed, data/inst | 452system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 530338 # Table walker requests started/completed, data/inst 453system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 90211 # Table walker requests started/completed, data/inst |
| 478system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 454system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 479system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 95446 # Table walker requests started/completed, data/inst 480system.cpu0.dtb.walker.walkRequestOrigin::total 635248 # Table walker requests started/completed, data/inst | 455system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 90211 # Table walker requests started/completed, data/inst 456system.cpu0.dtb.walker.walkRequestOrigin::total 620549 # Table walker requests started/completed, data/inst |
| 481system.cpu0.dtb.inst_hits 0 # ITB inst hits 482system.cpu0.dtb.inst_misses 0 # ITB inst misses | 457system.cpu0.dtb.inst_hits 0 # ITB inst hits 458system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 483system.cpu0.dtb.read_hits 96092667 # DTB read hits 484system.cpu0.dtb.read_misses 371231 # DTB read misses 485system.cpu0.dtb.write_hits 80108557 # DTB write hits 486system.cpu0.dtb.write_misses 168571 # DTB write misses 487system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed | 459system.cpu0.dtb.read_hits 99690232 # DTB read hits 460system.cpu0.dtb.read_misses 367422 # DTB read misses 461system.cpu0.dtb.write_hits 83046551 # DTB write hits 462system.cpu0.dtb.write_misses 162916 # DTB write misses 463system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed |
| 488system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 464system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 489system.cpu0.dtb.flush_tlb_mva_asid 46091 # Number of times TLB was flushed by MVA & ASID 490system.cpu0.dtb.flush_tlb_asid 1084 # Number of times TLB was flushed by ASID 491system.cpu0.dtb.flush_entries 35125 # Number of entries that have been flushed from TLB 492system.cpu0.dtb.align_faults 346 # Number of TLB faults due to alignment restrictions 493system.cpu0.dtb.prefetch_faults 6813 # Number of TLB faults due to prefetch | 465system.cpu0.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID 466system.cpu0.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID 467system.cpu0.dtb.flush_entries 35541 # Number of entries that have been flushed from TLB 468system.cpu0.dtb.align_faults 482 # Number of TLB faults due to alignment restrictions 469system.cpu0.dtb.prefetch_faults 6442 # Number of TLB faults due to prefetch |
| 494system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 470system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 495system.cpu0.dtb.perms_faults 38936 # Number of TLB faults due to permissions restrictions 496system.cpu0.dtb.read_accesses 96463898 # DTB read accesses 497system.cpu0.dtb.write_accesses 80277128 # DTB write accesses | 471system.cpu0.dtb.perms_faults 39704 # Number of TLB faults due to permissions restrictions 472system.cpu0.dtb.read_accesses 100057654 # DTB read accesses 473system.cpu0.dtb.write_accesses 83209467 # DTB write accesses |
| 498system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 474system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 499system.cpu0.dtb.hits 176201224 # DTB hits 500system.cpu0.dtb.misses 539802 # DTB misses 501system.cpu0.dtb.accesses 176741026 # DTB accesses | 475system.cpu0.dtb.hits 182736783 # DTB hits 476system.cpu0.dtb.misses 530338 # DTB misses 477system.cpu0.dtb.accesses 183267121 # DTB accesses |
| 502system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 503system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 504system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 505system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 506system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 507system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 508system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 509system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 523system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 524system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 525system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 526system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 527system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 528system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 529system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 530system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 478system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 479system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 480system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 481system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 499system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 500system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 501system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 502system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 503system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 504system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 505system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 506system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 531system.cpu0.itb.walker.walks 79903 # Table walker walks requested 532system.cpu0.itb.walker.walksLong 79903 # Table walker walks initiated with long descriptors 533system.cpu0.itb.walker.walksLongTerminationLevel::Level2 950 # Level at which table walker walks with long descriptors terminate 534system.cpu0.itb.walker.walksLongTerminationLevel::Level3 57315 # Level at which table walker walks with long descriptors terminate 535system.cpu0.itb.walker.walksSquashedBefore 9653 # Table walks squashed before starting 536system.cpu0.itb.walker.walkWaitTime::samples 70250 # Table walker wait (enqueue to first request) latency 537system.cpu0.itb.walker.walkWaitTime::mean 1248.284698 # Table walker wait (enqueue to first request) latency 538system.cpu0.itb.walker.walkWaitTime::stdev 10855.060811 # Table walker wait (enqueue to first request) latency 539system.cpu0.itb.walker.walkWaitTime::0-65535 69985 99.62% 99.62% # Table walker wait (enqueue to first request) latency 540system.cpu0.itb.walker.walkWaitTime::65536-131071 65 0.09% 99.72% # Table walker wait (enqueue to first request) latency 541system.cpu0.itb.walker.walkWaitTime::131072-196607 177 0.25% 99.97% # Table walker wait (enqueue to first request) latency 542system.cpu0.itb.walker.walkWaitTime::196608-262143 11 0.02% 99.98% # Table walker wait (enqueue to first request) latency 543system.cpu0.itb.walker.walkWaitTime::262144-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency 544system.cpu0.itb.walker.walkWaitTime::327680-393215 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency 545system.cpu0.itb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 546system.cpu0.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 547system.cpu0.itb.walker.walkWaitTime::total 70250 # Table walker wait (enqueue to first request) latency 548system.cpu0.itb.walker.walkCompletionTime::samples 67918 # Table walker service (enqueue to completion) latency 549system.cpu0.itb.walker.walkCompletionTime::mean 26250.242940 # Table walker service (enqueue to completion) latency 550system.cpu0.itb.walker.walkCompletionTime::gmean 22828.736245 # Table walker service (enqueue to completion) latency 551system.cpu0.itb.walker.walkCompletionTime::stdev 25780.781063 # Table walker service (enqueue to completion) latency 552system.cpu0.itb.walker.walkCompletionTime::0-65535 66522 97.94% 97.94% # Table walker service (enqueue to completion) latency 553system.cpu0.itb.walker.walkCompletionTime::65536-131071 103 0.15% 98.10% # Table walker service (enqueue to completion) latency 554system.cpu0.itb.walker.walkCompletionTime::131072-196607 1066 1.57% 99.67% # Table walker service (enqueue to completion) latency 555system.cpu0.itb.walker.walkCompletionTime::196608-262143 71 0.10% 99.77% # Table walker service (enqueue to completion) latency 556system.cpu0.itb.walker.walkCompletionTime::262144-327679 86 0.13% 99.90% # Table walker service (enqueue to completion) latency 557system.cpu0.itb.walker.walkCompletionTime::327680-393215 28 0.04% 99.94% # Table walker service (enqueue to completion) latency 558system.cpu0.itb.walker.walkCompletionTime::393216-458751 25 0.04% 99.97% # Table walker service (enqueue to completion) latency 559system.cpu0.itb.walker.walkCompletionTime::458752-524287 8 0.01% 99.99% # Table walker service (enqueue to completion) latency 560system.cpu0.itb.walker.walkCompletionTime::524288-589823 8 0.01% 100.00% # Table walker service (enqueue to completion) latency 561system.cpu0.itb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 562system.cpu0.itb.walker.walkCompletionTime::total 67918 # Table walker service (enqueue to completion) latency 563system.cpu0.itb.walker.walksPending::samples 408740768228 # Table walker pending requests distribution 564system.cpu0.itb.walker.walksPending::mean 0.873449 # Table walker pending requests distribution 565system.cpu0.itb.walker.walksPending::stdev 0.332683 # Table walker pending requests distribution 566system.cpu0.itb.walker.walksPending::0 51752271292 12.66% 12.66% # Table walker pending requests distribution 567system.cpu0.itb.walker.walksPending::1 356965086936 87.33% 99.99% # Table walker pending requests distribution 568system.cpu0.itb.walker.walksPending::2 21879500 0.01% 100.00% # Table walker pending requests distribution 569system.cpu0.itb.walker.walksPending::3 1303500 0.00% 100.00% # Table walker pending requests distribution 570system.cpu0.itb.walker.walksPending::4 81500 0.00% 100.00% # Table walker pending requests distribution 571system.cpu0.itb.walker.walksPending::5 52500 0.00% 100.00% # Table walker pending requests distribution 572system.cpu0.itb.walker.walksPending::6 29500 0.00% 100.00% # Table walker pending requests distribution 573system.cpu0.itb.walker.walksPending::7 1000 0.00% 100.00% # Table walker pending requests distribution 574system.cpu0.itb.walker.walksPending::8 62500 0.00% 100.00% # Table walker pending requests distribution 575system.cpu0.itb.walker.walksPending::total 408740768228 # Table walker pending requests distribution 576system.cpu0.itb.walker.walkPageSizes::4K 57315 98.37% 98.37% # Table walker page sizes translated 577system.cpu0.itb.walker.walkPageSizes::2M 950 1.63% 100.00% # Table walker page sizes translated 578system.cpu0.itb.walker.walkPageSizes::total 58265 # Table walker page sizes translated | 507system.cpu0.itb.walker.walks 81834 # Table walker walks requested 508system.cpu0.itb.walker.walksLong 81834 # Table walker walks initiated with long descriptors 509system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1030 # Level at which table walker walks with long descriptors terminate 510system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58824 # Level at which table walker walks with long descriptors terminate 511system.cpu0.itb.walker.walksSquashedBefore 9805 # Table walks squashed before starting 512system.cpu0.itb.walker.walkWaitTime::samples 72029 # Table walker wait (enqueue to first request) latency 513system.cpu0.itb.walker.walkWaitTime::mean 864.033931 # Table walker wait (enqueue to first request) latency 514system.cpu0.itb.walker.walkWaitTime::stdev 6165.525550 # Table walker wait (enqueue to first request) latency 515system.cpu0.itb.walker.walkWaitTime::0-32767 71606 99.41% 99.41% # Table walker wait (enqueue to first request) latency 516system.cpu0.itb.walker.walkWaitTime::32768-65535 296 0.41% 99.82% # Table walker wait (enqueue to first request) latency 517system.cpu0.itb.walker.walkWaitTime::65536-98303 49 0.07% 99.89% # Table walker wait (enqueue to first request) latency 518system.cpu0.itb.walker.walkWaitTime::98304-131071 70 0.10% 99.99% # Table walker wait (enqueue to first request) latency 519system.cpu0.itb.walker.walkWaitTime::131072-163839 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 520system.cpu0.itb.walker.walkWaitTime::163840-196607 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency 521system.cpu0.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 522system.cpu0.itb.walker.walkWaitTime::229376-262143 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 523system.cpu0.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 524system.cpu0.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 525system.cpu0.itb.walker.walkWaitTime::total 72029 # Table walker wait (enqueue to first request) latency 526system.cpu0.itb.walker.walkCompletionTime::samples 69659 # Table walker service (enqueue to completion) latency 527system.cpu0.itb.walker.walkCompletionTime::mean 23684.893553 # Table walker service (enqueue to completion) latency 528system.cpu0.itb.walker.walkCompletionTime::gmean 21955.996989 # Table walker service (enqueue to completion) latency 529system.cpu0.itb.walker.walkCompletionTime::stdev 12765.700584 # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walkCompletionTime::0-32767 63811 91.60% 91.60% # Table walker service (enqueue to completion) latency 531system.cpu0.itb.walker.walkCompletionTime::32768-65535 5242 7.53% 99.13% # Table walker service (enqueue to completion) latency 532system.cpu0.itb.walker.walkCompletionTime::65536-98303 100 0.14% 99.27% # Table walker service (enqueue to completion) latency 533system.cpu0.itb.walker.walkCompletionTime::98304-131071 402 0.58% 99.85% # Table walker service (enqueue to completion) latency 534system.cpu0.itb.walker.walkCompletionTime::131072-163839 39 0.06% 99.91% # Table walker service (enqueue to completion) latency 535system.cpu0.itb.walker.walkCompletionTime::163840-196607 17 0.02% 99.93% # Table walker service (enqueue to completion) latency 536system.cpu0.itb.walker.walkCompletionTime::196608-229375 16 0.02% 99.95% # Table walker service (enqueue to completion) latency 537system.cpu0.itb.walker.walkCompletionTime::229376-262143 8 0.01% 99.97% # Table walker service (enqueue to completion) latency 538system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency 539system.cpu0.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.98% # Table walker service (enqueue to completion) latency 540system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 541system.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency 542system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 543system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 544system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 545system.cpu0.itb.walker.walkCompletionTime::total 69659 # Table walker service (enqueue to completion) latency 546system.cpu0.itb.walker.walksPending::samples 375894589280 # Table walker pending requests distribution 547system.cpu0.itb.walker.walksPending::mean 0.860066 # Table walker pending requests distribution 548system.cpu0.itb.walker.walksPending::stdev 0.347066 # Table walker pending requests distribution 549system.cpu0.itb.walker.walksPending::0 52618427692 14.00% 14.00% # Table walker pending requests distribution 550system.cpu0.itb.walker.walksPending::1 323259257588 86.00% 100.00% # Table walker pending requests distribution 551system.cpu0.itb.walker.walksPending::2 15893500 0.00% 100.00% # Table walker pending requests distribution 552system.cpu0.itb.walker.walksPending::3 943500 0.00% 100.00% # Table walker pending requests distribution 553system.cpu0.itb.walker.walksPending::4 54500 0.00% 100.00% # Table walker pending requests distribution 554system.cpu0.itb.walker.walksPending::5 12500 0.00% 100.00% # Table walker pending requests distribution 555system.cpu0.itb.walker.walksPending::total 375894589280 # Table walker pending requests distribution 556system.cpu0.itb.walker.walkPageSizes::4K 58824 98.28% 98.28% # Table walker page sizes translated 557system.cpu0.itb.walker.walkPageSizes::2M 1030 1.72% 100.00% # Table walker page sizes translated 558system.cpu0.itb.walker.walkPageSizes::total 59854 # Table walker page sizes translated |
| 579system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 559system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 580system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 79903 # Table walker requests started/completed, data/inst 581system.cpu0.itb.walker.walkRequestOrigin_Requested::total 79903 # Table walker requests started/completed, data/inst | 560system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 81834 # Table walker requests started/completed, data/inst 561system.cpu0.itb.walker.walkRequestOrigin_Requested::total 81834 # Table walker requests started/completed, data/inst |
| 582system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 562system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 583system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 58265 # Table walker requests started/completed, data/inst 584system.cpu0.itb.walker.walkRequestOrigin_Completed::total 58265 # Table walker requests started/completed, data/inst 585system.cpu0.itb.walker.walkRequestOrigin::total 138168 # Table walker requests started/completed, data/inst 586system.cpu0.itb.inst_hits 207793696 # ITB inst hits 587system.cpu0.itb.inst_misses 79903 # ITB inst misses | 563system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59854 # Table walker requests started/completed, data/inst 564system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59854 # Table walker requests started/completed, data/inst 565system.cpu0.itb.walker.walkRequestOrigin::total 141688 # Table walker requests started/completed, data/inst 566system.cpu0.itb.inst_hits 216521473 # ITB inst hits 567system.cpu0.itb.inst_misses 81834 # ITB inst misses |
| 588system.cpu0.itb.read_hits 0 # DTB read hits 589system.cpu0.itb.read_misses 0 # DTB read misses 590system.cpu0.itb.write_hits 0 # DTB write hits 591system.cpu0.itb.write_misses 0 # DTB write misses | 568system.cpu0.itb.read_hits 0 # DTB read hits 569system.cpu0.itb.read_misses 0 # DTB read misses 570system.cpu0.itb.write_hits 0 # DTB write hits 571system.cpu0.itb.write_misses 0 # DTB write misses |
| 592system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed | 572system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed |
| 593system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 573system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 594system.cpu0.itb.flush_tlb_mva_asid 46091 # Number of times TLB was flushed by MVA & ASID 595system.cpu0.itb.flush_tlb_asid 1084 # Number of times TLB was flushed by ASID 596system.cpu0.itb.flush_entries 24840 # Number of entries that have been flushed from TLB | 574system.cpu0.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID 575system.cpu0.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID 576system.cpu0.itb.flush_entries 25342 # Number of entries that have been flushed from TLB |
| 597system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 598system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 599system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 577system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 578system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 579system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 600system.cpu0.itb.perms_faults 191050 # Number of TLB faults due to permissions restrictions | 580system.cpu0.itb.perms_faults 198402 # Number of TLB faults due to permissions restrictions |
| 601system.cpu0.itb.read_accesses 0 # DTB read accesses 602system.cpu0.itb.write_accesses 0 # DTB write accesses | 581system.cpu0.itb.read_accesses 0 # DTB read accesses 582system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 603system.cpu0.itb.inst_accesses 207873599 # ITB inst accesses 604system.cpu0.itb.hits 207793696 # DTB hits 605system.cpu0.itb.misses 79903 # DTB misses 606system.cpu0.itb.accesses 207873599 # DTB accesses 607system.cpu0.numCycles 761315266 # number of cpu cycles simulated | 583system.cpu0.itb.inst_accesses 216603307 # ITB inst accesses 584system.cpu0.itb.hits 216521473 # DTB hits 585system.cpu0.itb.misses 81834 # DTB misses 586system.cpu0.itb.accesses 216603307 # DTB accesses 587system.cpu0.numCycles 746014900 # number of cpu cycles simulated |
| 608system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 609system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 588system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 589system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 610system.cpu0.fetch.icacheStallCycles 84074114 # Number of cycles fetch is stalled on an Icache miss 611system.cpu0.fetch.Insts 585063894 # Number of instructions fetch has processed 612system.cpu0.fetch.Branches 132444225 # Number of branches that fetch encountered 613system.cpu0.fetch.predictedBranches 77977766 # Number of branches that fetch has predicted taken 614system.cpu0.fetch.Cycles 631770796 # Number of cycles fetch has run and was not squashing or blocked 615system.cpu0.fetch.SquashCycles 13765762 # Number of cycles fetch has spent squashing 616system.cpu0.fetch.TlbCycles 1785587 # Number of cycles fetch has spent waiting for tlb 617system.cpu0.fetch.MiscStallCycles 318737 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 618system.cpu0.fetch.PendingTrapStallCycles 5559321 # Number of stall cycles due to pending traps 619system.cpu0.fetch.PendingQuiesceStallCycles 752999 # Number of stall cycles due to pending quiesce instructions 620system.cpu0.fetch.IcacheWaitRetryStallCycles 796339 # Number of stall cycles due to full MSHR 621system.cpu0.fetch.CacheLines 207603742 # Number of cache lines fetched 622system.cpu0.fetch.IcacheSquashes 1586738 # Number of outstanding Icache misses that were squashed 623system.cpu0.fetch.ItlbSquashes 26136 # Number of outstanding ITLB misses that were squashed 624system.cpu0.fetch.rateDist::samples 731940774 # Number of instructions fetched each cycle (Total) 625system.cpu0.fetch.rateDist::mean 0.936268 # Number of instructions fetched each cycle (Total) 626system.cpu0.fetch.rateDist::stdev 1.209570 # Number of instructions fetched each cycle (Total) | 590system.cpu0.fetch.icacheStallCycles 90433879 # Number of cycles fetch is stalled on an Icache miss 591system.cpu0.fetch.Insts 610172736 # Number of instructions fetch has processed 592system.cpu0.fetch.Branches 138091637 # Number of branches that fetch encountered 593system.cpu0.fetch.predictedBranches 81258280 # Number of branches that fetch has predicted taken 594system.cpu0.fetch.Cycles 615398287 # Number of cycles fetch has run and was not squashing or blocked 595system.cpu0.fetch.SquashCycles 14620490 # Number of cycles fetch has spent squashing 596system.cpu0.fetch.TlbCycles 1715297 # Number of cycles fetch has spent waiting for tlb 597system.cpu0.fetch.MiscStallCycles 295776 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 598system.cpu0.fetch.PendingTrapStallCycles 5589619 # Number of stall cycles due to pending traps 599system.cpu0.fetch.PendingQuiesceStallCycles 711520 # Number of stall cycles due to pending quiesce instructions 600system.cpu0.fetch.IcacheWaitRetryStallCycles 813110 # Number of stall cycles due to full MSHR 601system.cpu0.fetch.CacheLines 216323861 # Number of cache lines fetched 602system.cpu0.fetch.IcacheSquashes 1696724 # Number of outstanding Icache misses that were squashed 603system.cpu0.fetch.ItlbSquashes 26704 # Number of outstanding ITLB misses that were squashed 604system.cpu0.fetch.rateDist::samples 722267733 # Number of instructions fetched each cycle (Total) 605system.cpu0.fetch.rateDist::mean 0.989116 # Number of instructions fetched each cycle (Total) 606system.cpu0.fetch.rateDist::stdev 1.222569 # Number of instructions fetched each cycle (Total) |
| 627system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 607system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 628system.cpu0.fetch.rateDist::0 403543312 55.13% 55.13% # Number of instructions fetched each cycle (Total) 629system.cpu0.fetch.rateDist::1 128205713 17.52% 72.65% # Number of instructions fetched each cycle (Total) 630system.cpu0.fetch.rateDist::2 43488128 5.94% 78.59% # Number of instructions fetched each cycle (Total) 631system.cpu0.fetch.rateDist::3 156703621 21.41% 100.00% # Number of instructions fetched each cycle (Total) | 608system.cpu0.fetch.rateDist::0 380266002 52.65% 52.65% # Number of instructions fetched each cycle (Total) 609system.cpu0.fetch.rateDist::1 133082578 18.43% 71.07% # Number of instructions fetched each cycle (Total) 610system.cpu0.fetch.rateDist::2 45433566 6.29% 77.36% # Number of instructions fetched each cycle (Total) 611system.cpu0.fetch.rateDist::3 163485587 22.64% 100.00% # Number of instructions fetched each cycle (Total) |
| 632system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 633system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 634system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 612system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 613system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 614system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 635system.cpu0.fetch.rateDist::total 731940774 # Number of instructions fetched each cycle (Total) 636system.cpu0.fetch.branchRate 0.173968 # Number of branch fetches per cycle 637system.cpu0.fetch.rate 0.768491 # Number of inst fetches per cycle 638system.cpu0.decode.IdleCycles 100319911 # Number of cycles decode is idle 639system.cpu0.decode.BlockedCycles 372509653 # Number of cycles decode is blocked 640system.cpu0.decode.RunCycles 217857253 # Number of cycles decode is running 641system.cpu0.decode.UnblockCycles 36338079 # Number of cycles decode is unblocking 642system.cpu0.decode.SquashCycles 4915878 # Number of cycles decode is squashing 643system.cpu0.decode.BranchResolved 18873695 # Number of times decode resolved a branch 644system.cpu0.decode.BranchMispred 2004301 # Number of times decode detected a branch misprediction 645system.cpu0.decode.DecodedInsts 606758178 # Number of instructions handled by decode 646system.cpu0.decode.SquashedInsts 22350639 # Number of squashed instructions handled by decode 647system.cpu0.rename.SquashCycles 4915878 # Number of cycles rename is squashing 648system.cpu0.rename.IdleCycles 134368949 # Number of cycles rename is idle 649system.cpu0.rename.BlockCycles 57393762 # Number of cycles rename is blocking 650system.cpu0.rename.serializeStallCycles 239367965 # count of cycles rename stalled for serializing inst 651system.cpu0.rename.RunCycles 219640614 # Number of cycles rename is running 652system.cpu0.rename.UnblockCycles 76253606 # Number of cycles rename is unblocking 653system.cpu0.rename.RenamedInsts 590337881 # Number of instructions processed by rename 654system.cpu0.rename.SquashedInsts 5891778 # Number of squashed instructions processed by rename 655system.cpu0.rename.ROBFullEvents 10879657 # Number of times rename has blocked due to ROB full 656system.cpu0.rename.IQFullEvents 272900 # Number of times rename has blocked due to IQ full 657system.cpu0.rename.LQFullEvents 275104 # Number of times rename has blocked due to LQ full 658system.cpu0.rename.SQFullEvents 42478331 # Number of times rename has blocked due to SQ full 659system.cpu0.rename.FullRegisterEvents 10735 # Number of times there has been no free registers 660system.cpu0.rename.RenamedOperands 562575259 # Number of destination operands rename has renamed 661system.cpu0.rename.RenameLookups 912365987 # Number of register rename lookups that rename has made 662system.cpu0.rename.int_rename_lookups 697390419 # Number of integer rename lookups 663system.cpu0.rename.fp_rename_lookups 694396 # Number of floating rename lookups 664system.cpu0.rename.CommittedMaps 507972674 # Number of HB maps that are committed 665system.cpu0.rename.UndoneMaps 54602579 # Number of HB maps that are undone due to squashing 666system.cpu0.rename.serializingInsts 15164295 # count of serializing insts renamed 667system.cpu0.rename.tempSerializingInsts 13334098 # count of temporary serializing insts renamed 668system.cpu0.rename.skidInsts 72899123 # count of insts added to the skid buffer 669system.cpu0.memDep0.insertedLoads 96066209 # Number of loads inserted to the mem dependence unit. 670system.cpu0.memDep0.insertedStores 83257958 # Number of stores inserted to the mem dependence unit. 671system.cpu0.memDep0.conflictingLoads 8637114 # Number of conflicting loads. 672system.cpu0.memDep0.conflictingStores 7533431 # Number of conflicting stores. 673system.cpu0.iq.iqInstsAdded 568637659 # Number of instructions added to the IQ (excludes non-spec) 674system.cpu0.iq.iqNonSpecInstsAdded 15304177 # Number of non-speculative instructions added to the IQ 675system.cpu0.iq.iqInstsIssued 573527019 # Number of instructions issued 676system.cpu0.iq.iqSquashedInstsIssued 2573483 # Number of squashed instructions issued 677system.cpu0.iq.iqSquashedInstsExamined 51469570 # Number of squashed instructions iterated over during squash; mainly for profiling 678system.cpu0.iq.iqSquashedOperandsExamined 33194366 # Number of squashed operands that are examined and possibly removed from graph 679system.cpu0.iq.iqSquashedNonSpecRemoved 252301 # Number of squashed non-spec instructions that were removed 680system.cpu0.iq.issued_per_cycle::samples 731940774 # Number of insts issued each cycle 681system.cpu0.iq.issued_per_cycle::mean 0.783570 # Number of insts issued each cycle 682system.cpu0.iq.issued_per_cycle::stdev 1.057506 # Number of insts issued each cycle | 615system.cpu0.fetch.rateDist::total 722267733 # Number of instructions fetched each cycle (Total) 616system.cpu0.fetch.branchRate 0.185106 # Number of branch fetches per cycle 617system.cpu0.fetch.rate 0.817910 # Number of inst fetches per cycle 618system.cpu0.decode.IdleCycles 106050198 # Number of cycles decode is idle 619system.cpu0.decode.BlockedCycles 344087060 # Number of cycles decode is blocked 620system.cpu0.decode.RunCycles 231125881 # Number of cycles decode is running 621system.cpu0.decode.UnblockCycles 35774912 # Number of cycles decode is unblocking 622system.cpu0.decode.SquashCycles 5229682 # Number of cycles decode is squashing 623system.cpu0.decode.BranchResolved 19752919 # Number of times decode resolved a branch 624system.cpu0.decode.BranchMispred 2120005 # Number of times decode detected a branch misprediction 625system.cpu0.decode.DecodedInsts 632519077 # Number of instructions handled by decode 626system.cpu0.decode.SquashedInsts 23747295 # Number of squashed instructions handled by decode 627system.cpu0.rename.SquashCycles 5229682 # Number of cycles rename is squashing 628system.cpu0.rename.IdleCycles 140879480 # Number of cycles rename is idle 629system.cpu0.rename.BlockCycles 46445701 # Number of cycles rename is blocking 630system.cpu0.rename.serializeStallCycles 235545365 # count of cycles rename stalled for serializing inst 631system.cpu0.rename.RunCycles 231642525 # Number of cycles rename is running 632system.cpu0.rename.UnblockCycles 62524980 # Number of cycles rename is unblocking 633system.cpu0.rename.RenamedInsts 614970268 # Number of instructions processed by rename 634system.cpu0.rename.SquashedInsts 6274841 # Number of squashed instructions processed by rename 635system.cpu0.rename.ROBFullEvents 9683853 # Number of times rename has blocked due to ROB full 636system.cpu0.rename.IQFullEvents 239254 # Number of times rename has blocked due to IQ full 637system.cpu0.rename.LQFullEvents 254272 # Number of times rename has blocked due to LQ full 638system.cpu0.rename.SQFullEvents 29219197 # Number of times rename has blocked due to SQ full 639system.cpu0.rename.FullRegisterEvents 11058 # Number of times there has been no free registers 640system.cpu0.rename.RenamedOperands 585821211 # Number of destination operands rename has renamed 641system.cpu0.rename.RenameLookups 944611426 # Number of register rename lookups that rename has made 642system.cpu0.rename.int_rename_lookups 725501320 # Number of integer rename lookups 643system.cpu0.rename.fp_rename_lookups 860588 # Number of floating rename lookups 644system.cpu0.rename.CommittedMaps 527918401 # Number of HB maps that are committed 645system.cpu0.rename.UndoneMaps 57902804 # Number of HB maps that are undone due to squashing 646system.cpu0.rename.serializingInsts 14873386 # count of serializing insts renamed 647system.cpu0.rename.tempSerializingInsts 12932012 # count of temporary serializing insts renamed 648system.cpu0.rename.skidInsts 72326353 # count of insts added to the skid buffer 649system.cpu0.memDep0.insertedLoads 100125445 # Number of loads inserted to the mem dependence unit. 650system.cpu0.memDep0.insertedStores 86327833 # Number of stores inserted to the mem dependence unit. 651system.cpu0.memDep0.conflictingLoads 8833111 # Number of conflicting loads. 652system.cpu0.memDep0.conflictingStores 7713299 # Number of conflicting stores. 653system.cpu0.iq.iqInstsAdded 593239093 # Number of instructions added to the IQ (excludes non-spec) 654system.cpu0.iq.iqNonSpecInstsAdded 14925406 # Number of non-speculative instructions added to the IQ 655system.cpu0.iq.iqInstsIssued 596650262 # Number of instructions issued 656system.cpu0.iq.iqSquashedInstsIssued 2740149 # Number of squashed instructions issued 657system.cpu0.iq.iqSquashedInstsExamined 54305512 # Number of squashed instructions iterated over during squash; mainly for profiling 658system.cpu0.iq.iqSquashedOperandsExamined 35087941 # Number of squashed operands that are examined and possibly removed from graph 659system.cpu0.iq.iqSquashedNonSpecRemoved 259840 # Number of squashed non-spec instructions that were removed 660system.cpu0.iq.issued_per_cycle::samples 722267733 # Number of insts issued each cycle 661system.cpu0.iq.issued_per_cycle::mean 0.826079 # Number of insts issued each cycle 662system.cpu0.iq.issued_per_cycle::stdev 1.071801 # Number of insts issued each cycle |
| 683system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 663system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 684system.cpu0.iq.issued_per_cycle::0 419086912 57.26% 57.26% # Number of insts issued each cycle 685system.cpu0.iq.issued_per_cycle::1 131041268 17.90% 75.16% # Number of insts issued each cycle 686system.cpu0.iq.issued_per_cycle::2 110621862 15.11% 90.27% # Number of insts issued each cycle 687system.cpu0.iq.issued_per_cycle::3 63525040 8.68% 98.95% # Number of insts issued each cycle 688system.cpu0.iq.issued_per_cycle::4 7661553 1.05% 100.00% # Number of insts issued each cycle 689system.cpu0.iq.issued_per_cycle::5 4139 0.00% 100.00% # Number of insts issued each cycle | 664system.cpu0.iq.issued_per_cycle::0 398653423 55.19% 55.19% # Number of insts issued each cycle 665system.cpu0.iq.issued_per_cycle::1 132668388 18.37% 73.56% # Number of insts issued each cycle 666system.cpu0.iq.issued_per_cycle::2 116695962 16.16% 89.72% # Number of insts issued each cycle 667system.cpu0.iq.issued_per_cycle::3 66414173 9.20% 98.92% # Number of insts issued each cycle 668system.cpu0.iq.issued_per_cycle::4 7831504 1.08% 100.00% # Number of insts issued each cycle 669system.cpu0.iq.issued_per_cycle::5 4283 0.00% 100.00% # Number of insts issued each cycle |
| 690system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 691system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 692system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 693system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 694system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 695system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 670system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 671system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 672system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 673system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 674system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 675system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 696system.cpu0.iq.issued_per_cycle::total 731940774 # Number of insts issued each cycle | 676system.cpu0.iq.issued_per_cycle::total 722267733 # Number of insts issued each cycle |
| 697system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 677system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 698system.cpu0.iq.fu_full::IntAlu 59257381 45.13% 45.13% # attempts to use FU when none available 699system.cpu0.iq.fu_full::IntMult 46667 0.04% 45.16% # attempts to use FU when none available 700system.cpu0.iq.fu_full::IntDiv 17941 0.01% 45.18% # attempts to use FU when none available 701system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.18% # attempts to use FU when none available 702system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.18% # attempts to use FU when none available 703system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.18% # attempts to use FU when none available 704system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.18% # attempts to use FU when none available 705system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.18% # attempts to use FU when none available 706system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.18% # attempts to use FU when none available 707system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.18% # attempts to use FU when none available 708system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.18% # attempts to use FU when none available 709system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.18% # attempts to use FU when none available 710system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.18% # attempts to use FU when none available 711system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.18% # attempts to use FU when none available 712system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.18% # attempts to use FU when none available 713system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.18% # attempts to use FU when none available 714system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.18% # attempts to use FU when none available 715system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.18% # attempts to use FU when none available 716system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.18% # attempts to use FU when none available 717system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.18% # attempts to use FU when none available 718system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.18% # attempts to use FU when none available 719system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.18% # attempts to use FU when none available 720system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.18% # attempts to use FU when none available 721system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.18% # attempts to use FU when none available 722system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.18% # attempts to use FU when none available 723system.cpu0.iq.fu_full::SimdFloatMisc 17 0.00% 45.18% # attempts to use FU when none available 724system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.18% # attempts to use FU when none available 725system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.18% # attempts to use FU when none available 726system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.18% # attempts to use FU when none available 727system.cpu0.iq.fu_full::MemRead 34285997 26.11% 71.29% # attempts to use FU when none available 728system.cpu0.iq.fu_full::MemWrite 37701656 28.71% 100.00% # attempts to use FU when none available | 678system.cpu0.iq.fu_full::IntAlu 62572261 45.86% 45.86% # attempts to use FU when none available 679system.cpu0.iq.fu_full::IntMult 47637 0.03% 45.89% # attempts to use FU when none available 680system.cpu0.iq.fu_full::IntDiv 27538 0.02% 45.91% # attempts to use FU when none available 681system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.91% # attempts to use FU when none available 682system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.91% # attempts to use FU when none available 683system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.91% # attempts to use FU when none available 684system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.91% # attempts to use FU when none available 685system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.91% # attempts to use FU when none available 686system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.91% # attempts to use FU when none available 687system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.91% # attempts to use FU when none available 688system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.91% # attempts to use FU when none available 689system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.91% # attempts to use FU when none available 690system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.91% # attempts to use FU when none available 691system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.91% # attempts to use FU when none available 692system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.91% # attempts to use FU when none available 693system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.91% # attempts to use FU when none available 694system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.91% # attempts to use FU when none available 695system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.91% # attempts to use FU when none available 696system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.91% # attempts to use FU when none available 697system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.91% # attempts to use FU when none available 698system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.91% # attempts to use FU when none available 699system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.91% # attempts to use FU when none available 700system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.91% # attempts to use FU when none available 701system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.91% # attempts to use FU when none available 702system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.91% # attempts to use FU when none available 703system.cpu0.iq.fu_full::SimdFloatMisc 12 0.00% 45.91% # attempts to use FU when none available 704system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.91% # attempts to use FU when none available 705system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.91% # attempts to use FU when none available 706system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.91% # attempts to use FU when none available 707system.cpu0.iq.fu_full::MemRead 35025206 25.67% 71.58% # attempts to use FU when none available 708system.cpu0.iq.fu_full::MemWrite 38780691 28.42% 100.00% # attempts to use FU when none available |
| 729system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 730system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 709system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 710system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 731system.cpu0.iq.FU_type_0::No_OpClass 17 0.00% 0.00% # Type of FU issued 732system.cpu0.iq.FU_type_0::IntAlu 391712029 68.30% 68.30% # Type of FU issued 733system.cpu0.iq.FU_type_0::IntMult 1330798 0.23% 68.53% # Type of FU issued 734system.cpu0.iq.FU_type_0::IntDiv 69152 0.01% 68.54% # Type of FU issued 735system.cpu0.iq.FU_type_0::FloatAdd 6 0.00% 68.54% # Type of FU issued 736system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.54% # Type of FU issued 737system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.54% # Type of FU issued 738system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.54% # Type of FU issued 739system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.54% # Type of FU issued 740system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.54% # Type of FU issued 741system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.54% # Type of FU issued 742system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.54% # Type of FU issued 743system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 68.54% # Type of FU issued 744system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.54% # Type of FU issued 745system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.54% # Type of FU issued 746system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.54% # Type of FU issued 747system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.54% # Type of FU issued 748system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.54% # Type of FU issued 749system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.54% # Type of FU issued 750system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.54% # Type of FU issued 751system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.54% # Type of FU issued 752system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.54% # Type of FU issued 753system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.54% # Type of FU issued 754system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.54% # Type of FU issued 755system.cpu0.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.54% # Type of FU issued 756system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.54% # Type of FU issued 757system.cpu0.iq.FU_type_0::SimdFloatMisc 42956 0.01% 68.55% # Type of FU issued 758system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.55% # Type of FU issued 759system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.55% # Type of FU issued 760system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.55% # Type of FU issued 761system.cpu0.iq.FU_type_0::MemRead 99049842 17.27% 85.82% # Type of FU issued 762system.cpu0.iq.FU_type_0::MemWrite 81322170 14.18% 100.00% # Type of FU issued | 711system.cpu0.iq.FU_type_0::No_OpClass 37 0.00% 0.00% # Type of FU issued 712system.cpu0.iq.FU_type_0::IntAlu 408003074 68.38% 68.38% # Type of FU issued 713system.cpu0.iq.FU_type_0::IntMult 1391206 0.23% 68.62% # Type of FU issued 714system.cpu0.iq.FU_type_0::IntDiv 75246 0.01% 68.63% # Type of FU issued 715system.cpu0.iq.FU_type_0::FloatAdd 5 0.00% 68.63% # Type of FU issued 716system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.63% # Type of FU issued 717system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.63% # Type of FU issued 718system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.63% # Type of FU issued 719system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.63% # Type of FU issued 720system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.63% # Type of FU issued 721system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.63% # Type of FU issued 722system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.63% # Type of FU issued 723system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.63% # Type of FU issued 724system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.63% # Type of FU issued 725system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.63% # Type of FU issued 726system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.63% # Type of FU issued 727system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.63% # Type of FU issued 728system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.63% # Type of FU issued 729system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.63% # Type of FU issued 730system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.63% # Type of FU issued 731system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.63% # Type of FU issued 732system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.63% # Type of FU issued 733system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.63% # Type of FU issued 734system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.63% # Type of FU issued 735system.cpu0.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.63% # Type of FU issued 736system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.63% # Type of FU issued 737system.cpu0.iq.FU_type_0::SimdFloatMisc 75513 0.01% 68.64% # Type of FU issued 738system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.64% # Type of FU issued 739system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.64% # Type of FU issued 740system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.64% # Type of FU issued 741system.cpu0.iq.FU_type_0::MemRead 102801955 17.23% 85.87% # Type of FU issued 742system.cpu0.iq.FU_type_0::MemWrite 84303178 14.13% 100.00% # Type of FU issued |
| 763system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 764system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 743system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 744system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 765system.cpu0.iq.FU_type_0::total 573527019 # Type of FU issued 766system.cpu0.iq.rate 0.753337 # Inst issue rate 767system.cpu0.iq.fu_busy_cnt 131309659 # FU busy when requested 768system.cpu0.iq.fu_busy_rate 0.228951 # FU busy rate (busy events/executed inst) 769system.cpu0.iq.int_inst_queue_reads 2011763518 # Number of integer instruction queue reads 770system.cpu0.iq.int_inst_queue_writes 635110276 # Number of integer instruction queue writes 771system.cpu0.iq.int_inst_queue_wakeup_accesses 556950573 # Number of integer instruction queue wakeup accesses 772system.cpu0.iq.fp_inst_queue_reads 1114436 # Number of floating instruction queue reads 773system.cpu0.iq.fp_inst_queue_writes 438215 # Number of floating instruction queue writes 774system.cpu0.iq.fp_inst_queue_wakeup_accesses 411063 # Number of floating instruction queue wakeup accesses 775system.cpu0.iq.int_alu_accesses 704141671 # Number of integer alu accesses 776system.cpu0.iq.fp_alu_accesses 694990 # Number of floating point alu accesses 777system.cpu0.iew.lsq.thread0.forwLoads 2575949 # Number of loads that had data forwarded from stores | 745system.cpu0.iq.FU_type_0::total 596650262 # Type of FU issued 746system.cpu0.iq.rate 0.799783 # Inst issue rate 747system.cpu0.iq.fu_busy_cnt 136453345 # FU busy when requested 748system.cpu0.iq.fu_busy_rate 0.228699 # FU busy rate (busy events/executed inst) 749system.cpu0.iq.int_inst_queue_reads 2053360508 # Number of integer instruction queue reads 750system.cpu0.iq.int_inst_queue_writes 662051351 # Number of integer instruction queue writes 751system.cpu0.iq.int_inst_queue_wakeup_accesses 579495604 # Number of integer instruction queue wakeup accesses 752system.cpu0.iq.fp_inst_queue_reads 1401241 # Number of floating instruction queue reads 753system.cpu0.iq.fp_inst_queue_writes 556367 # Number of floating instruction queue writes 754system.cpu0.iq.fp_inst_queue_wakeup_accesses 521179 # Number of floating instruction queue wakeup accesses 755system.cpu0.iq.int_alu_accesses 732235238 # Number of integer alu accesses 756system.cpu0.iq.fp_alu_accesses 868332 # Number of floating point alu accesses 757system.cpu0.iew.lsq.thread0.forwLoads 2674563 # Number of loads that had data forwarded from stores |
| 778system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 758system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 779system.cpu0.iew.lsq.thread0.squashedLoads 11750995 # Number of loads squashed 780system.cpu0.iew.lsq.thread0.ignoredResponses 17228 # Number of memory responses ignored because the instruction is squashed 781system.cpu0.iew.lsq.thread0.memOrderViolation 138196 # Number of memory ordering violations 782system.cpu0.iew.lsq.thread0.squashedStores 5318019 # Number of stores squashed | 759system.cpu0.iew.lsq.thread0.squashedLoads 12322480 # Number of loads squashed 760system.cpu0.iew.lsq.thread0.ignoredResponses 16225 # Number of memory responses ignored because the instruction is squashed 761system.cpu0.iew.lsq.thread0.memOrderViolation 138716 # Number of memory ordering violations 762system.cpu0.iew.lsq.thread0.squashedStores 5498195 # Number of stores squashed |
| 783system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 784system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 763system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 764system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 785system.cpu0.iew.lsq.thread0.rescheduledLoads 2553185 # Number of loads that were rescheduled 786system.cpu0.iew.lsq.thread0.cacheBlocked 4584143 # Number of times an access to memory failed due to the cache being blocked | 765system.cpu0.iew.lsq.thread0.rescheduledLoads 2627025 # Number of loads that were rescheduled 766system.cpu0.iew.lsq.thread0.cacheBlocked 4349073 # Number of times an access to memory failed due to the cache being blocked |
| 787system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 767system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 788system.cpu0.iew.iewSquashCycles 4915878 # Number of cycles IEW is squashing 789system.cpu0.iew.iewBlockCycles 6708218 # Number of cycles IEW is blocking 790system.cpu0.iew.iewUnblockCycles 2698388 # Number of cycles IEW is unblocking 791system.cpu0.iew.iewDispatchedInsts 584066483 # Number of instructions dispatched to IQ | 768system.cpu0.iew.iewSquashCycles 5229682 # Number of cycles IEW is squashing 769system.cpu0.iew.iewBlockCycles 6015766 # Number of cycles IEW is blocking 770system.cpu0.iew.iewUnblockCycles 1577054 # Number of cycles IEW is unblocking 771system.cpu0.iew.iewDispatchedInsts 608291813 # Number of instructions dispatched to IQ |
| 792system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 772system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 793system.cpu0.iew.iewDispLoadInsts 96066209 # Number of dispatched load instructions 794system.cpu0.iew.iewDispStoreInsts 83257958 # Number of dispatched store instructions 795system.cpu0.iew.iewDispNonSpecInsts 13102761 # Number of dispatched non-speculative instructions 796system.cpu0.iew.iewIQFullEvents 64235 # Number of times the IQ has become full, causing a stall 797system.cpu0.iew.iewLSQFullEvents 2566402 # Number of times the LSQ has become full, causing a stall 798system.cpu0.iew.memOrderViolationEvents 138196 # Number of memory order violations 799system.cpu0.iew.predictedTakenIncorrect 1807441 # Number of branches that were predicted taken incorrectly 800system.cpu0.iew.predictedNotTakenIncorrect 2958148 # Number of branches that were predicted not taken incorrectly 801system.cpu0.iew.branchMispredicts 4765589 # Number of branch mispredicts detected at execute 802system.cpu0.iew.iewExecutedInsts 565930325 # Number of executed instructions 803system.cpu0.iew.iewExecLoadInsts 96085763 # Number of load instructions executed 804system.cpu0.iew.iewExecSquashedInsts 7069222 # Number of squashed instructions skipped in execute | 773system.cpu0.iew.iewDispLoadInsts 100125445 # Number of dispatched load instructions 774system.cpu0.iew.iewDispStoreInsts 86327833 # Number of dispatched store instructions 775system.cpu0.iew.iewDispNonSpecInsts 12661031 # Number of dispatched non-speculative instructions 776system.cpu0.iew.iewIQFullEvents 57348 # Number of times the IQ has become full, causing a stall 777system.cpu0.iew.iewLSQFullEvents 1462300 # Number of times the LSQ has become full, causing a stall 778system.cpu0.iew.memOrderViolationEvents 138716 # Number of memory order violations 779system.cpu0.iew.predictedTakenIncorrect 1920652 # Number of branches that were predicted taken incorrectly 780system.cpu0.iew.predictedNotTakenIncorrect 3139987 # Number of branches that were predicted not taken incorrectly 781system.cpu0.iew.branchMispredicts 5060639 # Number of branch mispredicts detected at execute 782system.cpu0.iew.iewExecutedInsts 588583301 # Number of executed instructions 783system.cpu0.iew.iewExecLoadInsts 99681195 # Number of load instructions executed 784system.cpu0.iew.iewExecSquashedInsts 7546532 # Number of squashed instructions skipped in execute |
| 805system.cpu0.iew.exec_swp 0 # number of swp insts executed | 785system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 806system.cpu0.iew.exec_nop 124647 # number of nop insts executed 807system.cpu0.iew.exec_refs 176196325 # number of memory reference insts executed 808system.cpu0.iew.exec_branches 106580080 # Number of branches executed 809system.cpu0.iew.exec_stores 80110562 # Number of stores executed 810system.cpu0.iew.exec_rate 0.743359 # Inst execution rate 811system.cpu0.iew.wb_sent 558072531 # cumulative count of insts sent to commit 812system.cpu0.iew.wb_count 557361636 # cumulative count of insts written-back 813system.cpu0.iew.wb_producers 269759058 # num instructions producing a value 814system.cpu0.iew.wb_consumers 442874225 # num instructions consuming a value 815system.cpu0.iew.wb_rate 0.732104 # insts written-back per cycle 816system.cpu0.iew.wb_fanout 0.609110 # average fanout of values written-back 817system.cpu0.commit.commitSquashedInsts 44855365 # The number of squashed insts skipped by commit 818system.cpu0.commit.commitNonSpecStalls 15051876 # The number of times commit has been forced to stall to communicate backwards 819system.cpu0.commit.branchMispredicts 4433751 # The number of times a branch was mispredicted 820system.cpu0.commit.committed_per_cycle::samples 723417587 # Number of insts commited each cycle 821system.cpu0.commit.committed_per_cycle::mean 0.736051 # Number of insts commited each cycle 822system.cpu0.commit.committed_per_cycle::stdev 1.544488 # Number of insts commited each cycle | 786system.cpu0.iew.exec_nop 127314 # number of nop insts executed 787system.cpu0.iew.exec_refs 182727665 # number of memory reference insts executed 788system.cpu0.iew.exec_branches 110905985 # Number of branches executed 789system.cpu0.iew.exec_stores 83046470 # Number of stores executed 790system.cpu0.iew.exec_rate 0.788970 # Inst execution rate 791system.cpu0.iew.wb_sent 580785082 # cumulative count of insts sent to commit 792system.cpu0.iew.wb_count 580016783 # cumulative count of insts written-back 793system.cpu0.iew.wb_producers 281571835 # num instructions producing a value 794system.cpu0.iew.wb_consumers 462036259 # num instructions consuming a value 795system.cpu0.iew.wb_rate 0.777487 # insts written-back per cycle 796system.cpu0.iew.wb_fanout 0.609415 # average fanout of values written-back 797system.cpu0.commit.commitSquashedInsts 47239068 # The number of squashed insts skipped by commit 798system.cpu0.commit.commitNonSpecStalls 14665566 # The number of times commit has been forced to stall to communicate backwards 799system.cpu0.commit.branchMispredicts 4709377 # The number of times a branch was mispredicted 800system.cpu0.commit.committed_per_cycle::samples 713265593 # Number of insts commited each cycle 801system.cpu0.commit.committed_per_cycle::mean 0.776512 # Number of insts commited each cycle 802system.cpu0.commit.committed_per_cycle::stdev 1.575400 # Number of insts commited each cycle |
| 823system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 803system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 824system.cpu0.commit.committed_per_cycle::0 490442876 67.80% 67.80% # Number of insts commited each cycle 825system.cpu0.commit.committed_per_cycle::1 120876307 16.71% 84.50% # Number of insts commited each cycle 826system.cpu0.commit.committed_per_cycle::2 51465837 7.11% 91.62% # Number of insts commited each cycle 827system.cpu0.commit.committed_per_cycle::3 17138323 2.37% 93.99% # Number of insts commited each cycle 828system.cpu0.commit.committed_per_cycle::4 12635808 1.75% 95.73% # Number of insts commited each cycle 829system.cpu0.commit.committed_per_cycle::5 8409902 1.16% 96.90% # Number of insts commited each cycle 830system.cpu0.commit.committed_per_cycle::6 5731195 0.79% 97.69% # Number of insts commited each cycle 831system.cpu0.commit.committed_per_cycle::7 3469312 0.48% 98.17% # Number of insts commited each cycle 832system.cpu0.commit.committed_per_cycle::8 13248027 1.83% 100.00% # Number of insts commited each cycle | 804system.cpu0.commit.committed_per_cycle::0 472345396 66.22% 66.22% # Number of insts commited each cycle 805system.cpu0.commit.committed_per_cycle::1 122854697 17.22% 83.45% # Number of insts commited each cycle 806system.cpu0.commit.committed_per_cycle::2 54352038 7.62% 91.07% # Number of insts commited each cycle 807system.cpu0.commit.committed_per_cycle::3 18530727 2.60% 93.67% # Number of insts commited each cycle 808system.cpu0.commit.committed_per_cycle::4 13156863 1.84% 95.51% # Number of insts commited each cycle 809system.cpu0.commit.committed_per_cycle::5 8843989 1.24% 96.75% # Number of insts commited each cycle 810system.cpu0.commit.committed_per_cycle::6 5973723 0.84% 97.59% # Number of insts commited each cycle 811system.cpu0.commit.committed_per_cycle::7 3646989 0.51% 98.10% # Number of insts commited each cycle 812system.cpu0.commit.committed_per_cycle::8 13561171 1.90% 100.00% # Number of insts commited each cycle |
| 833system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 834system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 835system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 813system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 814system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 815system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 836system.cpu0.commit.committed_per_cycle::total 723417587 # Number of insts commited each cycle 837system.cpu0.commit.committedInsts 452974919 # Number of instructions committed 838system.cpu0.commit.committedOps 532472262 # Number of ops (including micro ops) committed | 816system.cpu0.commit.committed_per_cycle::total 713265593 # Number of insts commited each cycle 817system.cpu0.commit.committedInsts 471410910 # Number of instructions committed 818system.cpu0.commit.committedOps 553858980 # Number of ops (including micro ops) committed |
| 839system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 819system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 840system.cpu0.commit.refs 162255152 # Number of memory references committed 841system.cpu0.commit.loads 84315213 # Number of loads committed 842system.cpu0.commit.membars 3606698 # Number of memory barriers committed 843system.cpu0.commit.branches 101352780 # Number of branches committed 844system.cpu0.commit.fp_insts 403239 # Number of committed floating point instructions. 845system.cpu0.commit.int_insts 488332622 # Number of committed integer instructions. 846system.cpu0.commit.function_calls 13274605 # Number of function calls committed. | 820system.cpu0.commit.refs 168632602 # Number of memory references committed 821system.cpu0.commit.loads 87802964 # Number of loads committed 822system.cpu0.commit.membars 3653468 # Number of memory barriers committed 823system.cpu0.commit.branches 105429162 # Number of branches committed 824system.cpu0.commit.fp_insts 512997 # Number of committed floating point instructions. 825system.cpu0.commit.int_insts 508174699 # Number of committed integer instructions. 826system.cpu0.commit.function_calls 13889214 # Number of function calls committed. |
| 847system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 827system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 848system.cpu0.commit.op_class_0::IntAlu 369012489 69.30% 69.30% # Class of committed instruction 849system.cpu0.commit.op_class_0::IntMult 1112277 0.21% 69.51% # Class of committed instruction 850system.cpu0.commit.op_class_0::IntDiv 54460 0.01% 69.52% # Class of committed instruction 851system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction 852system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction 853system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction 854system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction 855system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction 856system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction 857system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction 858system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction 859system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction 860system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction 861system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction 862system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction 863system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction 864system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction 865system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction 866system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction 867system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction 868system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.52% # Class of committed instruction 869system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction 870system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.52% # Class of committed instruction 871system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.52% # Class of committed instruction 872system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction 873system.cpu0.commit.op_class_0::SimdFloatMisc 37842 0.01% 69.53% # Class of committed instruction 874system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction 875system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction 876system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction 877system.cpu0.commit.op_class_0::MemRead 84315213 15.83% 85.36% # Class of committed instruction 878system.cpu0.commit.op_class_0::MemWrite 77939939 14.64% 100.00% # Class of committed instruction | 828system.cpu0.commit.op_class_0::IntAlu 383941234 69.32% 69.32% # Class of committed instruction 829system.cpu0.commit.op_class_0::IntMult 1156077 0.21% 69.53% # Class of committed instruction 830system.cpu0.commit.op_class_0::IntDiv 59954 0.01% 69.54% # Class of committed instruction 831system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.54% # Class of committed instruction 832system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.54% # Class of committed instruction 833system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.54% # Class of committed instruction 834system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.54% # Class of committed instruction 835system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.54% # Class of committed instruction 836system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.54% # Class of committed instruction 837system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.54% # Class of committed instruction 838system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.54% # Class of committed instruction 839system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.54% # Class of committed instruction 840system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.54% # Class of committed instruction 841system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.54% # Class of committed instruction 842system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.54% # Class of committed instruction 843system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.54% # Class of committed instruction 844system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.54% # Class of committed instruction 845system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.54% # Class of committed instruction 846system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.54% # Class of committed instruction 847system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.54% # Class of committed instruction 848system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.54% # Class of committed instruction 849system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.54% # Class of committed instruction 850system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.54% # Class of committed instruction 851system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.54% # Class of committed instruction 852system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.54% # Class of committed instruction 853system.cpu0.commit.op_class_0::SimdFloatMisc 69071 0.01% 69.55% # Class of committed instruction 854system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.55% # Class of committed instruction 855system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.55% # Class of committed instruction 856system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.55% # Class of committed instruction 857system.cpu0.commit.op_class_0::MemRead 87802964 15.85% 85.41% # Class of committed instruction 858system.cpu0.commit.op_class_0::MemWrite 80829638 14.59% 100.00% # Class of committed instruction |
| 879system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 880system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 859system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 860system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 881system.cpu0.commit.op_class_0::total 532472262 # Class of committed instruction 882system.cpu0.commit.bw_lim_events 13248027 # number cycles where commit BW limit reached 883system.cpu0.rob.rob_reads 1283601950 # The number of ROB reads 884system.cpu0.rob.rob_writes 1163144719 # The number of ROB writes 885system.cpu0.timesIdled 940575 # Number of times that the entire CPU went into an idle state and unscheduled itself 886system.cpu0.idleCycles 29374492 # Total number of cycles that the CPU has spent unscheduled due to idling 887system.cpu0.quiesceCycles 94176188727 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 888system.cpu0.committedInsts 452974919 # Number of Instructions Simulated 889system.cpu0.committedOps 532472262 # Number of Ops (including micro ops) Simulated 890system.cpu0.cpi 1.680701 # CPI: Cycles Per Instruction 891system.cpu0.cpi_total 1.680701 # CPI: Total CPI of All Threads 892system.cpu0.ipc 0.594990 # IPC: Instructions Per Cycle 893system.cpu0.ipc_total 0.594990 # IPC: Total IPC of All Threads 894system.cpu0.int_regfile_reads 668586496 # number of integer regfile reads 895system.cpu0.int_regfile_writes 395947855 # number of integer regfile writes 896system.cpu0.fp_regfile_reads 683579 # number of floating regfile reads 897system.cpu0.fp_regfile_writes 295852 # number of floating regfile writes 898system.cpu0.cc_regfile_reads 123538962 # number of cc regfile reads 899system.cpu0.cc_regfile_writes 124272565 # number of cc regfile writes 900system.cpu0.misc_regfile_reads 1278649841 # number of misc regfile reads 901system.cpu0.misc_regfile_writes 15273032 # number of misc regfile writes 902system.cpu0.dcache.tags.replacements 5802522 # number of replacements 903system.cpu0.dcache.tags.tagsinuse 485.093904 # Cycle average of tags in use 904system.cpu0.dcache.tags.total_refs 150368529 # Total number of references to valid blocks. 905system.cpu0.dcache.tags.sampled_refs 5803033 # Sample count of references to valid blocks. 906system.cpu0.dcache.tags.avg_refs 25.912058 # Average number of references to valid blocks. 907system.cpu0.dcache.tags.warmup_cycle 2962390000 # Cycle when the warmup percentage was hit. 908system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.093904 # Average occupied blocks per requestor 909system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947449 # Average percentage of cache occupancy 910system.cpu0.dcache.tags.occ_percent::total 0.947449 # Average percentage of cache occupancy | 861system.cpu0.commit.op_class_0::total 553858980 # Class of committed instruction 862system.cpu0.commit.bw_lim_events 13561171 # number cycles where commit BW limit reached 863system.cpu0.rob.rob_reads 1296549352 # The number of ROB reads 864system.cpu0.rob.rob_writes 1211163120 # The number of ROB writes 865system.cpu0.timesIdled 982435 # Number of times that the entire CPU went into an idle state and unscheduled itself 866system.cpu0.idleCycles 23747167 # Total number of cycles that the CPU has spent unscheduled due to idling 867system.cpu0.quiesceCycles 94022615466 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 868system.cpu0.committedInsts 471410910 # Number of Instructions Simulated 869system.cpu0.committedOps 553858980 # Number of Ops (including micro ops) Simulated 870system.cpu0.cpi 1.582515 # CPI: Cycles Per Instruction 871system.cpu0.cpi_total 1.582515 # CPI: Total CPI of All Threads 872system.cpu0.ipc 0.631905 # IPC: Instructions Per Cycle 873system.cpu0.ipc_total 0.631905 # IPC: Total IPC of All Threads 874system.cpu0.int_regfile_reads 694459704 # number of integer regfile reads 875system.cpu0.int_regfile_writes 413089219 # number of integer regfile writes 876system.cpu0.fp_regfile_reads 846069 # number of floating regfile reads 877system.cpu0.fp_regfile_writes 429660 # number of floating regfile writes 878system.cpu0.cc_regfile_reads 127998327 # number of cc regfile reads 879system.cpu0.cc_regfile_writes 128742208 # number of cc regfile writes 880system.cpu0.misc_regfile_reads 1288788249 # number of misc regfile reads 881system.cpu0.misc_regfile_writes 14832406 # number of misc regfile writes 882system.cpu0.dcache.tags.replacements 5793916 # number of replacements 883system.cpu0.dcache.tags.tagsinuse 505.305765 # Cycle average of tags in use 884system.cpu0.dcache.tags.total_refs 157106373 # Total number of references to valid blocks. 885system.cpu0.dcache.tags.sampled_refs 5794427 # Sample count of references to valid blocks. 886system.cpu0.dcache.tags.avg_refs 27.113358 # Average number of references to valid blocks. 887system.cpu0.dcache.tags.warmup_cycle 1908955000 # Cycle when the warmup percentage was hit. 888system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.305765 # Average occupied blocks per requestor 889system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986925 # Average percentage of cache occupancy 890system.cpu0.dcache.tags.occ_percent::total 0.986925 # Average percentage of cache occupancy |
| 911system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id | 891system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id |
| 912system.cpu0.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 913system.cpu0.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id 914system.cpu0.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id | 892system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 893system.cpu0.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id 894system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id |
| 915system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id | 895system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id |
| 916system.cpu0.dcache.tags.tag_accesses 336490622 # Number of tag accesses 917system.cpu0.dcache.tags.data_accesses 336490622 # Number of data accesses 918system.cpu0.dcache.ReadReq_hits::cpu0.data 77978502 # number of ReadReq hits 919system.cpu0.dcache.ReadReq_hits::total 77978502 # number of ReadReq hits 920system.cpu0.dcache.WriteReq_hits::cpu0.data 67507915 # number of WriteReq hits 921system.cpu0.dcache.WriteReq_hits::total 67507915 # number of WriteReq hits 922system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199394 # number of SoftPFReq hits 923system.cpu0.dcache.SoftPFReq_hits::total 199394 # number of SoftPFReq hits 924system.cpu0.dcache.WriteLineReq_hits::cpu0.data 171803 # number of WriteLineReq hits 925system.cpu0.dcache.WriteLineReq_hits::total 171803 # number of WriteLineReq hits 926system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1821693 # number of LoadLockedReq hits 927system.cpu0.dcache.LoadLockedReq_hits::total 1821693 # number of LoadLockedReq hits 928system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1835435 # number of StoreCondReq hits 929system.cpu0.dcache.StoreCondReq_hits::total 1835435 # number of StoreCondReq hits 930system.cpu0.dcache.demand_hits::cpu0.data 145658220 # number of demand (read+write) hits 931system.cpu0.dcache.demand_hits::total 145658220 # number of demand (read+write) hits 932system.cpu0.dcache.overall_hits::cpu0.data 145857614 # number of overall hits 933system.cpu0.dcache.overall_hits::total 145857614 # number of overall hits 934system.cpu0.dcache.ReadReq_misses::cpu0.data 6410027 # number of ReadReq misses 935system.cpu0.dcache.ReadReq_misses::total 6410027 # number of ReadReq misses 936system.cpu0.dcache.WriteReq_misses::cpu0.data 7429665 # number of WriteReq misses 937system.cpu0.dcache.WriteReq_misses::total 7429665 # number of WriteReq misses 938system.cpu0.dcache.SoftPFReq_misses::cpu0.data 719434 # number of SoftPFReq misses 939system.cpu0.dcache.SoftPFReq_misses::total 719434 # number of SoftPFReq misses 940system.cpu0.dcache.WriteLineReq_misses::cpu0.data 793389 # number of WriteLineReq misses 941system.cpu0.dcache.WriteLineReq_misses::total 793389 # number of WriteLineReq misses 942system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 238145 # number of LoadLockedReq misses 943system.cpu0.dcache.LoadLockedReq_misses::total 238145 # number of LoadLockedReq misses 944system.cpu0.dcache.StoreCondReq_misses::cpu0.data 190782 # number of StoreCondReq misses 945system.cpu0.dcache.StoreCondReq_misses::total 190782 # number of StoreCondReq misses 946system.cpu0.dcache.demand_misses::cpu0.data 14633081 # number of demand (read+write) misses 947system.cpu0.dcache.demand_misses::total 14633081 # number of demand (read+write) misses 948system.cpu0.dcache.overall_misses::cpu0.data 15352515 # number of overall misses 949system.cpu0.dcache.overall_misses::total 15352515 # number of overall misses 950system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 109062490500 # number of ReadReq miss cycles 951system.cpu0.dcache.ReadReq_miss_latency::total 109062490500 # number of ReadReq miss cycles 952system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 171373805000 # number of WriteReq miss cycles 953system.cpu0.dcache.WriteReq_miss_latency::total 171373805000 # number of WriteReq miss cycles 954system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 50210173040 # number of WriteLineReq miss cycles 955system.cpu0.dcache.WriteLineReq_miss_latency::total 50210173040 # number of WriteLineReq miss cycles 956system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3622154000 # number of LoadLockedReq miss cycles 957system.cpu0.dcache.LoadLockedReq_miss_latency::total 3622154000 # number of LoadLockedReq miss cycles 958system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5311494500 # number of StoreCondReq miss cycles 959system.cpu0.dcache.StoreCondReq_miss_latency::total 5311494500 # number of StoreCondReq miss cycles 960system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5825000 # number of StoreCondFailReq miss cycles 961system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5825000 # number of StoreCondFailReq miss cycles 962system.cpu0.dcache.demand_miss_latency::cpu0.data 330646468540 # number of demand (read+write) miss cycles 963system.cpu0.dcache.demand_miss_latency::total 330646468540 # number of demand (read+write) miss cycles 964system.cpu0.dcache.overall_miss_latency::cpu0.data 330646468540 # number of overall miss cycles 965system.cpu0.dcache.overall_miss_latency::total 330646468540 # number of overall miss cycles 966system.cpu0.dcache.ReadReq_accesses::cpu0.data 84388529 # number of ReadReq accesses(hits+misses) 967system.cpu0.dcache.ReadReq_accesses::total 84388529 # number of ReadReq accesses(hits+misses) 968system.cpu0.dcache.WriteReq_accesses::cpu0.data 74937580 # number of WriteReq accesses(hits+misses) 969system.cpu0.dcache.WriteReq_accesses::total 74937580 # number of WriteReq accesses(hits+misses) 970system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 918828 # number of SoftPFReq accesses(hits+misses) 971system.cpu0.dcache.SoftPFReq_accesses::total 918828 # number of SoftPFReq accesses(hits+misses) 972system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 965192 # number of WriteLineReq accesses(hits+misses) 973system.cpu0.dcache.WriteLineReq_accesses::total 965192 # number of WriteLineReq accesses(hits+misses) 974system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2059838 # number of LoadLockedReq accesses(hits+misses) 975system.cpu0.dcache.LoadLockedReq_accesses::total 2059838 # number of LoadLockedReq accesses(hits+misses) 976system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2026217 # number of StoreCondReq accesses(hits+misses) 977system.cpu0.dcache.StoreCondReq_accesses::total 2026217 # number of StoreCondReq accesses(hits+misses) 978system.cpu0.dcache.demand_accesses::cpu0.data 160291301 # number of demand (read+write) accesses 979system.cpu0.dcache.demand_accesses::total 160291301 # number of demand (read+write) accesses 980system.cpu0.dcache.overall_accesses::cpu0.data 161210129 # number of overall (read+write) accesses 981system.cpu0.dcache.overall_accesses::total 161210129 # number of overall (read+write) accesses 982system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075959 # miss rate for ReadReq accesses 983system.cpu0.dcache.ReadReq_miss_rate::total 0.075959 # miss rate for ReadReq accesses 984system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.099145 # miss rate for WriteReq accesses 985system.cpu0.dcache.WriteReq_miss_rate::total 0.099145 # miss rate for WriteReq accesses 986system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.782991 # miss rate for SoftPFReq accesses 987system.cpu0.dcache.SoftPFReq_miss_rate::total 0.782991 # miss rate for SoftPFReq accesses 988system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.822001 # miss rate for WriteLineReq accesses 989system.cpu0.dcache.WriteLineReq_miss_rate::total 0.822001 # miss rate for WriteLineReq accesses 990system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.115613 # miss rate for LoadLockedReq accesses 991system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.115613 # miss rate for LoadLockedReq accesses 992system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.094157 # miss rate for StoreCondReq accesses 993system.cpu0.dcache.StoreCondReq_miss_rate::total 0.094157 # miss rate for StoreCondReq accesses 994system.cpu0.dcache.demand_miss_rate::cpu0.data 0.091291 # miss rate for demand accesses 995system.cpu0.dcache.demand_miss_rate::total 0.091291 # miss rate for demand accesses 996system.cpu0.dcache.overall_miss_rate::cpu0.data 0.095233 # miss rate for overall accesses 997system.cpu0.dcache.overall_miss_rate::total 0.095233 # miss rate for overall accesses 998system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17014.357428 # average ReadReq miss latency 999system.cpu0.dcache.ReadReq_avg_miss_latency::total 17014.357428 # average ReadReq miss latency 1000system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23066.155069 # average WriteReq miss latency 1001system.cpu0.dcache.WriteReq_avg_miss_latency::total 23066.155069 # average WriteReq miss latency 1002system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 63285.693449 # average WriteLineReq miss latency 1003system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 63285.693449 # average WriteLineReq miss latency 1004system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15209.867938 # average LoadLockedReq miss latency 1005system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15209.867938 # average LoadLockedReq miss latency 1006system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27840.647965 # average StoreCondReq miss latency 1007system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27840.647965 # average StoreCondReq miss latency | 896system.cpu0.dcache.tags.tag_accesses 349540400 # Number of tag accesses 897system.cpu0.dcache.tags.data_accesses 349540400 # Number of data accesses 898system.cpu0.dcache.ReadReq_hits::cpu0.data 81616032 # number of ReadReq hits 899system.cpu0.dcache.ReadReq_hits::total 81616032 # number of ReadReq hits 900system.cpu0.dcache.WriteReq_hits::cpu0.data 70522769 # number of WriteReq hits 901system.cpu0.dcache.WriteReq_hits::total 70522769 # number of WriteReq hits 902system.cpu0.dcache.SoftPFReq_hits::cpu0.data 213045 # number of SoftPFReq hits 903system.cpu0.dcache.SoftPFReq_hits::total 213045 # number of SoftPFReq hits 904system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259663 # number of WriteLineReq hits 905system.cpu0.dcache.WriteLineReq_hits::total 259663 # number of WriteLineReq hits 906system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1810689 # number of LoadLockedReq hits 907system.cpu0.dcache.LoadLockedReq_hits::total 1810689 # number of LoadLockedReq hits 908system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1836259 # number of StoreCondReq hits 909system.cpu0.dcache.StoreCondReq_hits::total 1836259 # number of StoreCondReq hits 910system.cpu0.dcache.demand_hits::cpu0.data 152398464 # number of demand (read+write) hits 911system.cpu0.dcache.demand_hits::total 152398464 # number of demand (read+write) hits 912system.cpu0.dcache.overall_hits::cpu0.data 152611509 # number of overall hits 913system.cpu0.dcache.overall_hits::total 152611509 # number of overall hits 914system.cpu0.dcache.ReadReq_misses::cpu0.data 6448823 # number of ReadReq misses 915system.cpu0.dcache.ReadReq_misses::total 6448823 # number of ReadReq misses 916system.cpu0.dcache.WriteReq_misses::cpu0.data 7191873 # number of WriteReq misses 917system.cpu0.dcache.WriteReq_misses::total 7191873 # number of WriteReq misses 918system.cpu0.dcache.SoftPFReq_misses::cpu0.data 676181 # number of SoftPFReq misses 919system.cpu0.dcache.SoftPFReq_misses::total 676181 # number of SoftPFReq misses 920system.cpu0.dcache.WriteLineReq_misses::cpu0.data 810826 # number of WriteLineReq misses 921system.cpu0.dcache.WriteLineReq_misses::total 810826 # number of WriteLineReq misses 922system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 247493 # number of LoadLockedReq misses 923system.cpu0.dcache.LoadLockedReq_misses::total 247493 # number of LoadLockedReq misses 924system.cpu0.dcache.StoreCondReq_misses::cpu0.data 187335 # number of StoreCondReq misses 925system.cpu0.dcache.StoreCondReq_misses::total 187335 # number of StoreCondReq misses 926system.cpu0.dcache.demand_misses::cpu0.data 14451522 # number of demand (read+write) misses 927system.cpu0.dcache.demand_misses::total 14451522 # number of demand (read+write) misses 928system.cpu0.dcache.overall_misses::cpu0.data 15127703 # number of overall misses 929system.cpu0.dcache.overall_misses::total 15127703 # number of overall misses 930system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 92981912000 # number of ReadReq miss cycles 931system.cpu0.dcache.ReadReq_miss_latency::total 92981912000 # number of ReadReq miss cycles 932system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 133998931168 # number of WriteReq miss cycles 933system.cpu0.dcache.WriteReq_miss_latency::total 133998931168 # number of WriteReq miss cycles 934system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 29936196189 # number of WriteLineReq miss cycles 935system.cpu0.dcache.WriteLineReq_miss_latency::total 29936196189 # number of WriteLineReq miss cycles 936system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3415607500 # number of LoadLockedReq miss cycles 937system.cpu0.dcache.LoadLockedReq_miss_latency::total 3415607500 # number of LoadLockedReq miss cycles 938system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4687136000 # number of StoreCondReq miss cycles 939system.cpu0.dcache.StoreCondReq_miss_latency::total 4687136000 # number of StoreCondReq miss cycles 940system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3788500 # number of StoreCondFailReq miss cycles 941system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3788500 # number of StoreCondFailReq miss cycles 942system.cpu0.dcache.demand_miss_latency::cpu0.data 256917039357 # number of demand (read+write) miss cycles 943system.cpu0.dcache.demand_miss_latency::total 256917039357 # number of demand (read+write) miss cycles 944system.cpu0.dcache.overall_miss_latency::cpu0.data 256917039357 # number of overall miss cycles 945system.cpu0.dcache.overall_miss_latency::total 256917039357 # number of overall miss cycles 946system.cpu0.dcache.ReadReq_accesses::cpu0.data 88064855 # number of ReadReq accesses(hits+misses) 947system.cpu0.dcache.ReadReq_accesses::total 88064855 # number of ReadReq accesses(hits+misses) 948system.cpu0.dcache.WriteReq_accesses::cpu0.data 77714642 # number of WriteReq accesses(hits+misses) 949system.cpu0.dcache.WriteReq_accesses::total 77714642 # number of WriteReq accesses(hits+misses) 950system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 889226 # number of SoftPFReq accesses(hits+misses) 951system.cpu0.dcache.SoftPFReq_accesses::total 889226 # number of SoftPFReq accesses(hits+misses) 952system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1070489 # number of WriteLineReq accesses(hits+misses) 953system.cpu0.dcache.WriteLineReq_accesses::total 1070489 # number of WriteLineReq accesses(hits+misses) 954system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2058182 # number of LoadLockedReq accesses(hits+misses) 955system.cpu0.dcache.LoadLockedReq_accesses::total 2058182 # number of LoadLockedReq accesses(hits+misses) 956system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2023594 # number of StoreCondReq accesses(hits+misses) 957system.cpu0.dcache.StoreCondReq_accesses::total 2023594 # number of StoreCondReq accesses(hits+misses) 958system.cpu0.dcache.demand_accesses::cpu0.data 166849986 # number of demand (read+write) accesses 959system.cpu0.dcache.demand_accesses::total 166849986 # number of demand (read+write) accesses 960system.cpu0.dcache.overall_accesses::cpu0.data 167739212 # number of overall (read+write) accesses 961system.cpu0.dcache.overall_accesses::total 167739212 # number of overall (read+write) accesses 962system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.073228 # miss rate for ReadReq accesses 963system.cpu0.dcache.ReadReq_miss_rate::total 0.073228 # miss rate for ReadReq accesses 964system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.092542 # miss rate for WriteReq accesses 965system.cpu0.dcache.WriteReq_miss_rate::total 0.092542 # miss rate for WriteReq accesses 966system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760415 # miss rate for SoftPFReq accesses 967system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760415 # miss rate for SoftPFReq accesses 968system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.757435 # miss rate for WriteLineReq accesses 969system.cpu0.dcache.WriteLineReq_miss_rate::total 0.757435 # miss rate for WriteLineReq accesses 970system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.120248 # miss rate for LoadLockedReq accesses 971system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.120248 # miss rate for LoadLockedReq accesses 972system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.092575 # miss rate for StoreCondReq accesses 973system.cpu0.dcache.StoreCondReq_miss_rate::total 0.092575 # miss rate for StoreCondReq accesses 974system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086614 # miss rate for demand accesses 975system.cpu0.dcache.demand_miss_rate::total 0.086614 # miss rate for demand accesses 976system.cpu0.dcache.overall_miss_rate::cpu0.data 0.090186 # miss rate for overall accesses 977system.cpu0.dcache.overall_miss_rate::total 0.090186 # miss rate for overall accesses 978system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14418.431394 # average ReadReq miss latency 979system.cpu0.dcache.ReadReq_avg_miss_latency::total 14418.431394 # average ReadReq miss latency 980system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18631.993525 # average WriteReq miss latency 981system.cpu0.dcache.WriteReq_avg_miss_latency::total 18631.993525 # average WriteReq miss latency 982system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 36920.616987 # average WriteLineReq miss latency 983system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 36920.616987 # average WriteLineReq miss latency 984system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13800.824670 # average LoadLockedReq miss latency 985system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13800.824670 # average LoadLockedReq miss latency 986system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25020.076334 # average StoreCondReq miss latency 987system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25020.076334 # average StoreCondReq miss latency |
| 1008system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1009system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 988system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 989system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 1010system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22595.820288 # average overall miss latency 1011system.cpu0.dcache.demand_avg_miss_latency::total 22595.820288 # average overall miss latency 1012system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21536.957856 # average overall miss latency 1013system.cpu0.dcache.overall_avg_miss_latency::total 21536.957856 # average overall miss latency 1014system.cpu0.dcache.blocked_cycles::no_mshrs 15517119 # number of cycles access was blocked 1015system.cpu0.dcache.blocked_cycles::no_targets 25638833 # number of cycles access was blocked 1016system.cpu0.dcache.blocked::no_mshrs 732854 # number of cycles access was blocked 1017system.cpu0.dcache.blocked::no_targets 730129 # number of cycles access was blocked 1018system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.173548 # average number of cycles each access was blocked 1019system.cpu0.dcache.avg_blocked_cycles::no_targets 35.115484 # average number of cycles each access was blocked 1020system.cpu0.dcache.writebacks::writebacks 5802538 # number of writebacks 1021system.cpu0.dcache.writebacks::total 5802538 # number of writebacks 1022system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3327729 # number of ReadReq MSHR hits 1023system.cpu0.dcache.ReadReq_mshr_hits::total 3327729 # number of ReadReq MSHR hits 1024system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5970882 # number of WriteReq MSHR hits 1025system.cpu0.dcache.WriteReq_mshr_hits::total 5970882 # number of WriteReq MSHR hits 1026system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4398 # number of WriteLineReq MSHR hits 1027system.cpu0.dcache.WriteLineReq_mshr_hits::total 4398 # number of WriteLineReq MSHR hits 1028system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 123286 # number of LoadLockedReq MSHR hits 1029system.cpu0.dcache.LoadLockedReq_mshr_hits::total 123286 # number of LoadLockedReq MSHR hits 1030system.cpu0.dcache.demand_mshr_hits::cpu0.data 9303009 # number of demand (read+write) MSHR hits 1031system.cpu0.dcache.demand_mshr_hits::total 9303009 # number of demand (read+write) MSHR hits 1032system.cpu0.dcache.overall_mshr_hits::cpu0.data 9303009 # number of overall MSHR hits 1033system.cpu0.dcache.overall_mshr_hits::total 9303009 # number of overall MSHR hits 1034system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3082298 # number of ReadReq MSHR misses 1035system.cpu0.dcache.ReadReq_mshr_misses::total 3082298 # number of ReadReq MSHR misses 1036system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1458783 # number of WriteReq MSHR misses 1037system.cpu0.dcache.WriteReq_mshr_misses::total 1458783 # number of WriteReq MSHR misses 1038system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 712505 # number of SoftPFReq MSHR misses 1039system.cpu0.dcache.SoftPFReq_mshr_misses::total 712505 # number of SoftPFReq MSHR misses 1040system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 788991 # number of WriteLineReq MSHR misses 1041system.cpu0.dcache.WriteLineReq_mshr_misses::total 788991 # number of WriteLineReq MSHR misses 1042system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 114859 # number of LoadLockedReq MSHR misses 1043system.cpu0.dcache.LoadLockedReq_mshr_misses::total 114859 # number of LoadLockedReq MSHR misses 1044system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 190777 # number of StoreCondReq MSHR misses 1045system.cpu0.dcache.StoreCondReq_mshr_misses::total 190777 # number of StoreCondReq MSHR misses 1046system.cpu0.dcache.demand_mshr_misses::cpu0.data 5330072 # number of demand (read+write) MSHR misses 1047system.cpu0.dcache.demand_mshr_misses::total 5330072 # number of demand (read+write) MSHR misses 1048system.cpu0.dcache.overall_mshr_misses::cpu0.data 6042577 # number of overall MSHR misses 1049system.cpu0.dcache.overall_mshr_misses::total 6042577 # number of overall MSHR misses 1050system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 19706 # number of ReadReq MSHR uncacheable 1051system.cpu0.dcache.ReadReq_mshr_uncacheable::total 19706 # number of ReadReq MSHR uncacheable 1052system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 21266 # number of WriteReq MSHR uncacheable 1053system.cpu0.dcache.WriteReq_mshr_uncacheable::total 21266 # number of WriteReq MSHR uncacheable 1054system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 40972 # number of overall MSHR uncacheable misses 1055system.cpu0.dcache.overall_mshr_uncacheable_misses::total 40972 # number of overall MSHR uncacheable misses 1056system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 48302897000 # number of ReadReq MSHR miss cycles 1057system.cpu0.dcache.ReadReq_mshr_miss_latency::total 48302897000 # number of ReadReq MSHR miss cycles 1058system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 39166129612 # number of WriteReq MSHR miss cycles 1059system.cpu0.dcache.WriteReq_mshr_miss_latency::total 39166129612 # number of WriteReq MSHR miss cycles 1060system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 19342072500 # number of SoftPFReq MSHR miss cycles 1061system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 19342072500 # number of SoftPFReq MSHR miss cycles 1062system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 49145395540 # number of WriteLineReq MSHR miss cycles 1063system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 49145395540 # number of WriteLineReq MSHR miss cycles 1064system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1672767500 # number of LoadLockedReq MSHR miss cycles 1065system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1672767500 # number of LoadLockedReq MSHR miss cycles 1066system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5120787500 # number of StoreCondReq MSHR miss cycles 1067system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5120787500 # number of StoreCondReq MSHR miss cycles 1068system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5755000 # number of StoreCondFailReq MSHR miss cycles 1069system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5755000 # number of StoreCondFailReq MSHR miss cycles 1070system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 136614422152 # number of demand (read+write) MSHR miss cycles 1071system.cpu0.dcache.demand_mshr_miss_latency::total 136614422152 # number of demand (read+write) MSHR miss cycles 1072system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 155956494652 # number of overall MSHR miss cycles 1073system.cpu0.dcache.overall_mshr_miss_latency::total 155956494652 # number of overall MSHR miss cycles 1074system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3863694500 # number of ReadReq MSHR uncacheable cycles 1075system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3863694500 # number of ReadReq MSHR uncacheable cycles 1076system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3863694500 # number of overall MSHR uncacheable cycles 1077system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3863694500 # number of overall MSHR uncacheable cycles 1078system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036525 # mshr miss rate for ReadReq accesses 1079system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036525 # mshr miss rate for ReadReq accesses 1080system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019467 # mshr miss rate for WriteReq accesses 1081system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019467 # mshr miss rate for WriteReq accesses 1082system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.775450 # mshr miss rate for SoftPFReq accesses 1083system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.775450 # mshr miss rate for SoftPFReq accesses 1084system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.817445 # mshr miss rate for WriteLineReq accesses 1085system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.817445 # mshr miss rate for WriteLineReq accesses 1086system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055761 # mshr miss rate for LoadLockedReq accesses 1087system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055761 # mshr miss rate for LoadLockedReq accesses 1088system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.094154 # mshr miss rate for StoreCondReq accesses 1089system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.094154 # mshr miss rate for StoreCondReq accesses 1090system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033252 # mshr miss rate for demand accesses 1091system.cpu0.dcache.demand_mshr_miss_rate::total 0.033252 # mshr miss rate for demand accesses 1092system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037483 # mshr miss rate for overall accesses 1093system.cpu0.dcache.overall_mshr_miss_rate::total 0.037483 # mshr miss rate for overall accesses 1094system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15671.066522 # average ReadReq mshr miss latency 1095system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15671.066522 # average ReadReq mshr miss latency 1096system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26848.496049 # average WriteReq mshr miss latency 1097system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26848.496049 # average WriteReq mshr miss latency 1098system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 27146.577919 # average SoftPFReq mshr miss latency 1099system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 27146.577919 # average SoftPFReq mshr miss latency 1100system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 62288.917795 # average WriteLineReq mshr miss latency 1101system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 62288.917795 # average WriteLineReq mshr miss latency 1102system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14563.660662 # average LoadLockedReq mshr miss latency 1103system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14563.660662 # average LoadLockedReq mshr miss latency 1104system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26841.744550 # average StoreCondReq mshr miss latency 1105system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26841.744550 # average StoreCondReq mshr miss latency | 990system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17777.853389 # average overall miss latency 991system.cpu0.dcache.demand_avg_miss_latency::total 17777.853389 # average overall miss latency 992system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16983.215453 # average overall miss latency 993system.cpu0.dcache.overall_avg_miss_latency::total 16983.215453 # average overall miss latency 994system.cpu0.dcache.blocked_cycles::no_mshrs 9060649 # number of cycles access was blocked 995system.cpu0.dcache.blocked_cycles::no_targets 19650869 # number of cycles access was blocked 996system.cpu0.dcache.blocked::no_mshrs 747322 # number of cycles access was blocked 997system.cpu0.dcache.blocked::no_targets 698056 # number of cycles access was blocked 998system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.124157 # average number of cycles each access was blocked 999system.cpu0.dcache.avg_blocked_cycles::no_targets 28.150849 # average number of cycles each access was blocked 1000system.cpu0.dcache.writebacks::writebacks 5793928 # number of writebacks 1001system.cpu0.dcache.writebacks::total 5793928 # number of writebacks 1002system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3323367 # number of ReadReq MSHR hits 1003system.cpu0.dcache.ReadReq_mshr_hits::total 3323367 # number of ReadReq MSHR hits 1004system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5758852 # number of WriteReq MSHR hits 1005system.cpu0.dcache.WriteReq_mshr_hits::total 5758852 # number of WriteReq MSHR hits 1006system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4670 # number of WriteLineReq MSHR hits 1007system.cpu0.dcache.WriteLineReq_mshr_hits::total 4670 # number of WriteLineReq MSHR hits 1008system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 128237 # number of LoadLockedReq MSHR hits 1009system.cpu0.dcache.LoadLockedReq_mshr_hits::total 128237 # number of LoadLockedReq MSHR hits 1010system.cpu0.dcache.demand_mshr_hits::cpu0.data 9086889 # number of demand (read+write) MSHR hits 1011system.cpu0.dcache.demand_mshr_hits::total 9086889 # number of demand (read+write) MSHR hits 1012system.cpu0.dcache.overall_mshr_hits::cpu0.data 9086889 # number of overall MSHR hits 1013system.cpu0.dcache.overall_mshr_hits::total 9086889 # number of overall MSHR hits 1014system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3125456 # number of ReadReq MSHR misses 1015system.cpu0.dcache.ReadReq_mshr_misses::total 3125456 # number of ReadReq MSHR misses 1016system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1433021 # number of WriteReq MSHR misses 1017system.cpu0.dcache.WriteReq_mshr_misses::total 1433021 # number of WriteReq MSHR misses 1018system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 669278 # number of SoftPFReq MSHR misses 1019system.cpu0.dcache.SoftPFReq_mshr_misses::total 669278 # number of SoftPFReq MSHR misses 1020system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 806156 # number of WriteLineReq MSHR misses 1021system.cpu0.dcache.WriteLineReq_mshr_misses::total 806156 # number of WriteLineReq MSHR misses 1022system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 119256 # number of LoadLockedReq MSHR misses 1023system.cpu0.dcache.LoadLockedReq_mshr_misses::total 119256 # number of LoadLockedReq MSHR misses 1024system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 187331 # number of StoreCondReq MSHR misses 1025system.cpu0.dcache.StoreCondReq_mshr_misses::total 187331 # number of StoreCondReq MSHR misses 1026system.cpu0.dcache.demand_mshr_misses::cpu0.data 5364633 # number of demand (read+write) MSHR misses 1027system.cpu0.dcache.demand_mshr_misses::total 5364633 # number of demand (read+write) MSHR misses 1028system.cpu0.dcache.overall_mshr_misses::cpu0.data 6033911 # number of overall MSHR misses 1029system.cpu0.dcache.overall_mshr_misses::total 6033911 # number of overall MSHR misses 1030system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32527 # number of ReadReq MSHR uncacheable 1031system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32527 # number of ReadReq MSHR uncacheable 1032system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32351 # number of WriteReq MSHR uncacheable 1033system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32351 # number of WriteReq MSHR uncacheable 1034system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 64878 # number of overall MSHR uncacheable misses 1035system.cpu0.dcache.overall_mshr_uncacheable_misses::total 64878 # number of overall MSHR uncacheable misses 1036system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43142423000 # number of ReadReq MSHR miss cycles 1037system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43142423000 # number of ReadReq MSHR miss cycles 1038system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30169010620 # number of WriteReq MSHR miss cycles 1039system.cpu0.dcache.WriteReq_mshr_miss_latency::total 30169010620 # number of WriteReq MSHR miss cycles 1040system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14964455000 # number of SoftPFReq MSHR miss cycles 1041system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14964455000 # number of SoftPFReq MSHR miss cycles 1042system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28947099689 # number of WriteLineReq MSHR miss cycles 1043system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28947099689 # number of WriteLineReq MSHR miss cycles 1044system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1564593500 # number of LoadLockedReq MSHR miss cycles 1045system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1564593500 # number of LoadLockedReq MSHR miss cycles 1046system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4499876000 # number of StoreCondReq MSHR miss cycles 1047system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4499876000 # number of StoreCondReq MSHR miss cycles 1048system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3717500 # number of StoreCondFailReq MSHR miss cycles 1049system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3717500 # number of StoreCondFailReq MSHR miss cycles 1050system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 102258533309 # number of demand (read+write) MSHR miss cycles 1051system.cpu0.dcache.demand_mshr_miss_latency::total 102258533309 # number of demand (read+write) MSHR miss cycles 1052system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 117222988309 # number of overall MSHR miss cycles 1053system.cpu0.dcache.overall_mshr_miss_latency::total 117222988309 # number of overall MSHR miss cycles 1054system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6208668000 # number of ReadReq MSHR uncacheable cycles 1055system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6208668000 # number of ReadReq MSHR uncacheable cycles 1056system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6208668000 # number of overall MSHR uncacheable cycles 1057system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6208668000 # number of overall MSHR uncacheable cycles 1058system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035490 # mshr miss rate for ReadReq accesses 1059system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035490 # mshr miss rate for ReadReq accesses 1060system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018440 # mshr miss rate for WriteReq accesses 1061system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018440 # mshr miss rate for WriteReq accesses 1062system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.752652 # mshr miss rate for SoftPFReq accesses 1063system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.752652 # mshr miss rate for SoftPFReq accesses 1064system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.753073 # mshr miss rate for WriteLineReq accesses 1065system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.753073 # mshr miss rate for WriteLineReq accesses 1066system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057942 # mshr miss rate for LoadLockedReq accesses 1067system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057942 # mshr miss rate for LoadLockedReq accesses 1068system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092573 # mshr miss rate for StoreCondReq accesses 1069system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092573 # mshr miss rate for StoreCondReq accesses 1070system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032152 # mshr miss rate for demand accesses 1071system.cpu0.dcache.demand_mshr_miss_rate::total 0.032152 # mshr miss rate for demand accesses 1072system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.035972 # mshr miss rate for overall accesses 1073system.cpu0.dcache.overall_mshr_miss_rate::total 0.035972 # mshr miss rate for overall accesses 1074system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13803.561144 # average ReadReq mshr miss latency 1075system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13803.561144 # average ReadReq mshr miss latency 1076system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21052.734482 # average WriteReq mshr miss latency 1077system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21052.734482 # average WriteReq mshr miss latency 1078system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22359.101898 # average SoftPFReq mshr miss latency 1079system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22359.101898 # average SoftPFReq mshr miss latency 1080system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 35907.565892 # average WriteLineReq mshr miss latency 1081system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 35907.565892 # average WriteLineReq mshr miss latency 1082system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13119.620816 # average LoadLockedReq mshr miss latency 1083system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13119.620816 # average LoadLockedReq mshr miss latency 1084system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24020.989585 # average StoreCondReq mshr miss latency 1085system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24020.989585 # average StoreCondReq mshr miss latency |
| 1106system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1107system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1086system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1087system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1108system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25630.877435 # average overall mshr miss latency 1109system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25630.877435 # average overall mshr miss latency 1110system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25809.599886 # average overall mshr miss latency 1111system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25809.599886 # average overall mshr miss latency 1112system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196066.908556 # average ReadReq mshr uncacheable latency 1113system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196066.908556 # average ReadReq mshr uncacheable latency 1114system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 94300.851801 # average overall mshr uncacheable latency 1115system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 94300.851801 # average overall mshr uncacheable latency 1116system.cpu0.icache.tags.replacements 5681079 # number of replacements 1117system.cpu0.icache.tags.tagsinuse 511.944679 # Cycle average of tags in use 1118system.cpu0.icache.tags.total_refs 201561746 # Total number of references to valid blocks. 1119system.cpu0.icache.tags.sampled_refs 5681591 # Sample count of references to valid blocks. 1120system.cpu0.icache.tags.avg_refs 35.476286 # Average number of references to valid blocks. 1121system.cpu0.icache.tags.warmup_cycle 18014203000 # Cycle when the warmup percentage was hit. 1122system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.944679 # Average occupied blocks per requestor 1123system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999892 # Average percentage of cache occupancy 1124system.cpu0.icache.tags.occ_percent::total 0.999892 # Average percentage of cache occupancy | 1088system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19061.608373 # average overall mshr miss latency 1089system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19061.608373 # average overall mshr miss latency 1090system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19427.364492 # average overall mshr miss latency 1091system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19427.364492 # average overall mshr miss latency 1092system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190877.363421 # average ReadReq mshr uncacheable latency 1093system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190877.363421 # average ReadReq mshr uncacheable latency 1094system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95697.586239 # average overall mshr uncacheable latency 1095system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95697.586239 # average overall mshr uncacheable latency 1096system.cpu0.icache.tags.replacements 6136519 # number of replacements 1097system.cpu0.icache.tags.tagsinuse 511.962391 # Cycle average of tags in use 1098system.cpu0.icache.tags.total_refs 209807209 # Total number of references to valid blocks. 1099system.cpu0.icache.tags.sampled_refs 6137031 # Sample count of references to valid blocks. 1100system.cpu0.icache.tags.avg_refs 34.187086 # Average number of references to valid blocks. 1101system.cpu0.icache.tags.warmup_cycle 12886295000 # Cycle when the warmup percentage was hit. 1102system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.962391 # Average occupied blocks per requestor 1103system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999927 # Average percentage of cache occupancy 1104system.cpu0.icache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy |
| 1125system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1105system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1126system.cpu0.icache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 1127system.cpu0.icache.tags.age_task_id_blocks_1024::1 483 # Occupied blocks per task id 1128system.cpu0.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id | 1106system.cpu0.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id 1107system.cpu0.icache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id 1108system.cpu0.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id |
| 1129system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1109system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1130system.cpu0.icache.tags.tag_accesses 420833426 # Number of tag accesses 1131system.cpu0.icache.tags.data_accesses 420833426 # Number of data accesses 1132system.cpu0.icache.ReadReq_hits::cpu0.inst 201561746 # number of ReadReq hits 1133system.cpu0.icache.ReadReq_hits::total 201561746 # number of ReadReq hits 1134system.cpu0.icache.demand_hits::cpu0.inst 201561746 # number of demand (read+write) hits 1135system.cpu0.icache.demand_hits::total 201561746 # number of demand (read+write) hits 1136system.cpu0.icache.overall_hits::cpu0.inst 201561746 # number of overall hits 1137system.cpu0.icache.overall_hits::total 201561746 # number of overall hits 1138system.cpu0.icache.ReadReq_misses::cpu0.inst 6014149 # number of ReadReq misses 1139system.cpu0.icache.ReadReq_misses::total 6014149 # number of ReadReq misses 1140system.cpu0.icache.demand_misses::cpu0.inst 6014149 # number of demand (read+write) misses 1141system.cpu0.icache.demand_misses::total 6014149 # number of demand (read+write) misses 1142system.cpu0.icache.overall_misses::cpu0.inst 6014149 # number of overall misses 1143system.cpu0.icache.overall_misses::total 6014149 # number of overall misses 1144system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 68585469625 # number of ReadReq miss cycles 1145system.cpu0.icache.ReadReq_miss_latency::total 68585469625 # number of ReadReq miss cycles 1146system.cpu0.icache.demand_miss_latency::cpu0.inst 68585469625 # number of demand (read+write) miss cycles 1147system.cpu0.icache.demand_miss_latency::total 68585469625 # number of demand (read+write) miss cycles 1148system.cpu0.icache.overall_miss_latency::cpu0.inst 68585469625 # number of overall miss cycles 1149system.cpu0.icache.overall_miss_latency::total 68585469625 # number of overall miss cycles 1150system.cpu0.icache.ReadReq_accesses::cpu0.inst 207575895 # number of ReadReq accesses(hits+misses) 1151system.cpu0.icache.ReadReq_accesses::total 207575895 # number of ReadReq accesses(hits+misses) 1152system.cpu0.icache.demand_accesses::cpu0.inst 207575895 # number of demand (read+write) accesses 1153system.cpu0.icache.demand_accesses::total 207575895 # number of demand (read+write) accesses 1154system.cpu0.icache.overall_accesses::cpu0.inst 207575895 # number of overall (read+write) accesses 1155system.cpu0.icache.overall_accesses::total 207575895 # number of overall (read+write) accesses 1156system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028973 # miss rate for ReadReq accesses 1157system.cpu0.icache.ReadReq_miss_rate::total 0.028973 # miss rate for ReadReq accesses 1158system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028973 # miss rate for demand accesses 1159system.cpu0.icache.demand_miss_rate::total 0.028973 # miss rate for demand accesses 1160system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028973 # miss rate for overall accesses 1161system.cpu0.icache.overall_miss_rate::total 0.028973 # miss rate for overall accesses 1162system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11404.019027 # average ReadReq miss latency 1163system.cpu0.icache.ReadReq_avg_miss_latency::total 11404.019027 # average ReadReq miss latency 1164system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11404.019027 # average overall miss latency 1165system.cpu0.icache.demand_avg_miss_latency::total 11404.019027 # average overall miss latency 1166system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11404.019027 # average overall miss latency 1167system.cpu0.icache.overall_avg_miss_latency::total 11404.019027 # average overall miss latency 1168system.cpu0.icache.blocked_cycles::no_mshrs 10444384 # number of cycles access was blocked 1169system.cpu0.icache.blocked_cycles::no_targets 1542 # number of cycles access was blocked 1170system.cpu0.icache.blocked::no_mshrs 695799 # number of cycles access was blocked 1171system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked 1172system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.010634 # average number of cycles each access was blocked 1173system.cpu0.icache.avg_blocked_cycles::no_targets 118.615385 # average number of cycles each access was blocked 1174system.cpu0.icache.writebacks::writebacks 5681079 # number of writebacks 1175system.cpu0.icache.writebacks::total 5681079 # number of writebacks 1176system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 332513 # number of ReadReq MSHR hits 1177system.cpu0.icache.ReadReq_mshr_hits::total 332513 # number of ReadReq MSHR hits 1178system.cpu0.icache.demand_mshr_hits::cpu0.inst 332513 # number of demand (read+write) MSHR hits 1179system.cpu0.icache.demand_mshr_hits::total 332513 # number of demand (read+write) MSHR hits 1180system.cpu0.icache.overall_mshr_hits::cpu0.inst 332513 # number of overall MSHR hits 1181system.cpu0.icache.overall_mshr_hits::total 332513 # number of overall MSHR hits 1182system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5681636 # number of ReadReq MSHR misses 1183system.cpu0.icache.ReadReq_mshr_misses::total 5681636 # number of ReadReq MSHR misses 1184system.cpu0.icache.demand_mshr_misses::cpu0.inst 5681636 # number of demand (read+write) MSHR misses 1185system.cpu0.icache.demand_mshr_misses::total 5681636 # number of demand (read+write) MSHR misses 1186system.cpu0.icache.overall_mshr_misses::cpu0.inst 5681636 # number of overall MSHR misses 1187system.cpu0.icache.overall_mshr_misses::total 5681636 # number of overall MSHR misses | 1110system.cpu0.icache.tags.tag_accesses 438728804 # Number of tag accesses 1111system.cpu0.icache.tags.data_accesses 438728804 # Number of data accesses 1112system.cpu0.icache.ReadReq_hits::cpu0.inst 209807209 # number of ReadReq hits 1113system.cpu0.icache.ReadReq_hits::total 209807209 # number of ReadReq hits 1114system.cpu0.icache.demand_hits::cpu0.inst 209807209 # number of demand (read+write) hits 1115system.cpu0.icache.demand_hits::total 209807209 # number of demand (read+write) hits 1116system.cpu0.icache.overall_hits::cpu0.inst 209807209 # number of overall hits 1117system.cpu0.icache.overall_hits::total 209807209 # number of overall hits 1118system.cpu0.icache.ReadReq_misses::cpu0.inst 6488653 # number of ReadReq misses 1119system.cpu0.icache.ReadReq_misses::total 6488653 # number of ReadReq misses 1120system.cpu0.icache.demand_misses::cpu0.inst 6488653 # number of demand (read+write) misses 1121system.cpu0.icache.demand_misses::total 6488653 # number of demand (read+write) misses 1122system.cpu0.icache.overall_misses::cpu0.inst 6488653 # number of overall misses 1123system.cpu0.icache.overall_misses::total 6488653 # number of overall misses 1124system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 69596700450 # number of ReadReq miss cycles 1125system.cpu0.icache.ReadReq_miss_latency::total 69596700450 # number of ReadReq miss cycles 1126system.cpu0.icache.demand_miss_latency::cpu0.inst 69596700450 # number of demand (read+write) miss cycles 1127system.cpu0.icache.demand_miss_latency::total 69596700450 # number of demand (read+write) miss cycles 1128system.cpu0.icache.overall_miss_latency::cpu0.inst 69596700450 # number of overall miss cycles 1129system.cpu0.icache.overall_miss_latency::total 69596700450 # number of overall miss cycles 1130system.cpu0.icache.ReadReq_accesses::cpu0.inst 216295862 # number of ReadReq accesses(hits+misses) 1131system.cpu0.icache.ReadReq_accesses::total 216295862 # number of ReadReq accesses(hits+misses) 1132system.cpu0.icache.demand_accesses::cpu0.inst 216295862 # number of demand (read+write) accesses 1133system.cpu0.icache.demand_accesses::total 216295862 # number of demand (read+write) accesses 1134system.cpu0.icache.overall_accesses::cpu0.inst 216295862 # number of overall (read+write) accesses 1135system.cpu0.icache.overall_accesses::total 216295862 # number of overall (read+write) accesses 1136system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029999 # miss rate for ReadReq accesses 1137system.cpu0.icache.ReadReq_miss_rate::total 0.029999 # miss rate for ReadReq accesses 1138system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029999 # miss rate for demand accesses 1139system.cpu0.icache.demand_miss_rate::total 0.029999 # miss rate for demand accesses 1140system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029999 # miss rate for overall accesses 1141system.cpu0.icache.overall_miss_rate::total 0.029999 # miss rate for overall accesses 1142system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10725.908821 # average ReadReq miss latency 1143system.cpu0.icache.ReadReq_avg_miss_latency::total 10725.908821 # average ReadReq miss latency 1144system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10725.908821 # average overall miss latency 1145system.cpu0.icache.demand_avg_miss_latency::total 10725.908821 # average overall miss latency 1146system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10725.908821 # average overall miss latency 1147system.cpu0.icache.overall_avg_miss_latency::total 10725.908821 # average overall miss latency 1148system.cpu0.icache.blocked_cycles::no_mshrs 10132412 # number of cycles access was blocked 1149system.cpu0.icache.blocked_cycles::no_targets 436 # number of cycles access was blocked 1150system.cpu0.icache.blocked::no_mshrs 737599 # number of cycles access was blocked 1151system.cpu0.icache.blocked::no_targets 9 # number of cycles access was blocked 1152system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.737020 # average number of cycles each access was blocked 1153system.cpu0.icache.avg_blocked_cycles::no_targets 48.444444 # average number of cycles each access was blocked 1154system.cpu0.icache.writebacks::writebacks 6136519 # number of writebacks 1155system.cpu0.icache.writebacks::total 6136519 # number of writebacks 1156system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 351573 # number of ReadReq MSHR hits 1157system.cpu0.icache.ReadReq_mshr_hits::total 351573 # number of ReadReq MSHR hits 1158system.cpu0.icache.demand_mshr_hits::cpu0.inst 351573 # number of demand (read+write) MSHR hits 1159system.cpu0.icache.demand_mshr_hits::total 351573 # number of demand (read+write) MSHR hits 1160system.cpu0.icache.overall_mshr_hits::cpu0.inst 351573 # number of overall MSHR hits 1161system.cpu0.icache.overall_mshr_hits::total 351573 # number of overall MSHR hits 1162system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6137080 # number of ReadReq MSHR misses 1163system.cpu0.icache.ReadReq_mshr_misses::total 6137080 # number of ReadReq MSHR misses 1164system.cpu0.icache.demand_mshr_misses::cpu0.inst 6137080 # number of demand (read+write) MSHR misses 1165system.cpu0.icache.demand_mshr_misses::total 6137080 # number of demand (read+write) MSHR misses 1166system.cpu0.icache.overall_mshr_misses::cpu0.inst 6137080 # number of overall MSHR misses 1167system.cpu0.icache.overall_mshr_misses::total 6137080 # number of overall MSHR misses |
| 1188system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 1189system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable 1190system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 1191system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses | 1168system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 1169system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable 1170system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 1171system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses |
| 1192system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 61685306454 # number of ReadReq MSHR miss cycles 1193system.cpu0.icache.ReadReq_mshr_miss_latency::total 61685306454 # number of ReadReq MSHR miss cycles 1194system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 61685306454 # number of demand (read+write) MSHR miss cycles 1195system.cpu0.icache.demand_mshr_miss_latency::total 61685306454 # number of demand (read+write) MSHR miss cycles 1196system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 61685306454 # number of overall MSHR miss cycles 1197system.cpu0.icache.overall_mshr_miss_latency::total 61685306454 # number of overall MSHR miss cycles 1198system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939780498 # number of ReadReq MSHR uncacheable cycles 1199system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939780498 # number of ReadReq MSHR uncacheable cycles 1200system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939780498 # number of overall MSHR uncacheable cycles 1201system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939780498 # number of overall MSHR uncacheable cycles 1202system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027371 # mshr miss rate for ReadReq accesses 1203system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027371 # mshr miss rate for ReadReq accesses 1204system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027371 # mshr miss rate for demand accesses 1205system.cpu0.icache.demand_mshr_miss_rate::total 0.027371 # mshr miss rate for demand accesses 1206system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027371 # mshr miss rate for overall accesses 1207system.cpu0.icache.overall_mshr_miss_rate::total 0.027371 # mshr miss rate for overall accesses 1208system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10856.962054 # average ReadReq mshr miss latency 1209system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10856.962054 # average ReadReq mshr miss latency 1210system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10856.962054 # average overall mshr miss latency 1211system.cpu0.icache.demand_avg_mshr_miss_latency::total 10856.962054 # average overall mshr miss latency 1212system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10856.962054 # average overall mshr miss latency 1213system.cpu0.icache.overall_avg_mshr_miss_latency::total 10856.962054 # average overall mshr miss latency 1214system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.236651 # average ReadReq mshr uncacheable latency 1215system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.236651 # average ReadReq mshr uncacheable latency 1216system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.236651 # average overall mshr uncacheable latency 1217system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.236651 # average overall mshr uncacheable latency 1218system.cpu0.l2cache.prefetcher.num_hwpf_issued 7915167 # number of hwpf issued 1219system.cpu0.l2cache.prefetcher.pfIdentified 7926437 # number of prefetch candidates identified 1220system.cpu0.l2cache.prefetcher.pfBufferHit 10130 # number of redundant prefetches already in prefetch queue | 1172system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 62984871633 # number of ReadReq MSHR miss cycles 1173system.cpu0.icache.ReadReq_mshr_miss_latency::total 62984871633 # number of ReadReq MSHR miss cycles 1174system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 62984871633 # number of demand (read+write) MSHR miss cycles 1175system.cpu0.icache.demand_mshr_miss_latency::total 62984871633 # number of demand (read+write) MSHR miss cycles 1176system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 62984871633 # number of overall MSHR miss cycles 1177system.cpu0.icache.overall_mshr_miss_latency::total 62984871633 # number of overall MSHR miss cycles 1178system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of ReadReq MSHR uncacheable cycles 1179system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1885677498 # number of ReadReq MSHR uncacheable cycles 1180system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of overall MSHR uncacheable cycles 1181system.cpu0.icache.overall_mshr_uncacheable_latency::total 1885677498 # number of overall MSHR uncacheable cycles 1182system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028374 # mshr miss rate for ReadReq accesses 1183system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028374 # mshr miss rate for ReadReq accesses 1184system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028374 # mshr miss rate for demand accesses 1185system.cpu0.icache.demand_mshr_miss_rate::total 0.028374 # mshr miss rate for demand accesses 1186system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028374 # mshr miss rate for overall accesses 1187system.cpu0.icache.overall_mshr_miss_rate::total 0.028374 # mshr miss rate for overall accesses 1188system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average ReadReq mshr miss latency 1189system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10263.003193 # average ReadReq mshr miss latency 1190system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency 1191system.cpu0.icache.demand_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency 1192system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency 1193system.cpu0.icache.overall_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency 1194system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average ReadReq mshr uncacheable latency 1195system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753 # average ReadReq mshr uncacheable latency 1196system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average overall mshr uncacheable latency 1197system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753 # average overall mshr uncacheable latency 1198system.cpu0.l2cache.prefetcher.num_hwpf_issued 7743703 # number of hwpf issued 1199system.cpu0.l2cache.prefetcher.pfIdentified 7754051 # number of prefetch candidates identified 1200system.cpu0.l2cache.prefetcher.pfBufferHit 9277 # number of redundant prefetches already in prefetch queue |
| 1221system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1222system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 1201system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1202system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 1223system.cpu0.l2cache.prefetcher.pfSpanPage 1009963 # number of prefetches not generated due to page crossing 1224system.cpu0.l2cache.tags.replacements 2664029 # number of replacements 1225system.cpu0.l2cache.tags.tagsinuse 16072.729216 # Cycle average of tags in use 1226system.cpu0.l2cache.tags.total_refs 16415073 # Total number of references to valid blocks. 1227system.cpu0.l2cache.tags.sampled_refs 2680041 # Sample count of references to valid blocks. 1228system.cpu0.l2cache.tags.avg_refs 6.124934 # Average number of references to valid blocks. 1229system.cpu0.l2cache.tags.warmup_cycle 3423391000 # Cycle when the warmup percentage was hit. 1230system.cpu0.l2cache.tags.occ_blocks::writebacks 14987.796585 # Average occupied blocks per requestor 1231system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 47.087094 # Average occupied blocks per requestor 1232system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 49.541309 # Average occupied blocks per requestor 1233system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 988.304228 # Average occupied blocks per requestor 1234system.cpu0.l2cache.tags.occ_percent::writebacks 0.914783 # Average percentage of cache occupancy 1235system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002874 # Average percentage of cache occupancy 1236system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003024 # Average percentage of cache occupancy 1237system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.060321 # Average percentage of cache occupancy 1238system.cpu0.l2cache.tags.occ_percent::total 0.981002 # Average percentage of cache occupancy 1239system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1464 # Occupied blocks per task id 1240system.cpu0.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id 1241system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14480 # Occupied blocks per task id 1242system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 10 # Occupied blocks per task id 1243system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 48 # Occupied blocks per task id 1244system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 590 # Occupied blocks per task id 1245system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 290 # Occupied blocks per task id 1246system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 526 # Occupied blocks per task id 1247system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 1248system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id 1249system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 10 # Occupied blocks per task id 1250system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id 1251system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id 1252system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1208 # Occupied blocks per task id 1253system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5747 # Occupied blocks per task id 1254system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2985 # Occupied blocks per task id 1255system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4461 # Occupied blocks per task id 1256system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.089355 # Percentage of cache occupancy per task id 1257system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id 1258system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.883789 # Percentage of cache occupancy per task id 1259system.cpu0.l2cache.tags.tag_accesses 394147733 # Number of tag accesses 1260system.cpu0.l2cache.tags.data_accesses 394147733 # Number of data accesses 1261system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 551770 # number of ReadReq hits 1262system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 179424 # number of ReadReq hits 1263system.cpu0.l2cache.ReadReq_hits::total 731194 # number of ReadReq hits 1264system.cpu0.l2cache.WritebackDirty_hits::writebacks 3854487 # number of WritebackDirty hits 1265system.cpu0.l2cache.WritebackDirty_hits::total 3854487 # number of WritebackDirty hits 1266system.cpu0.l2cache.WritebackClean_hits::writebacks 7627202 # number of WritebackClean hits 1267system.cpu0.l2cache.WritebackClean_hits::total 7627202 # number of WritebackClean hits 1268system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 654 # number of UpgradeReq hits 1269system.cpu0.l2cache.UpgradeReq_hits::total 654 # number of UpgradeReq hits 1270system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits 1271system.cpu0.l2cache.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits 1272system.cpu0.l2cache.ReadExReq_hits::cpu0.data 878534 # number of ReadExReq hits 1273system.cpu0.l2cache.ReadExReq_hits::total 878534 # number of ReadExReq hits 1274system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5121208 # number of ReadCleanReq hits 1275system.cpu0.l2cache.ReadCleanReq_hits::total 5121208 # number of ReadCleanReq hits 1276system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2880934 # number of ReadSharedReq hits 1277system.cpu0.l2cache.ReadSharedReq_hits::total 2880934 # number of ReadSharedReq hits 1278system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 188453 # number of InvalidateReq hits 1279system.cpu0.l2cache.InvalidateReq_hits::total 188453 # number of InvalidateReq hits 1280system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 551770 # number of demand (read+write) hits 1281system.cpu0.l2cache.demand_hits::cpu0.itb.walker 179424 # number of demand (read+write) hits 1282system.cpu0.l2cache.demand_hits::cpu0.inst 5121208 # number of demand (read+write) hits 1283system.cpu0.l2cache.demand_hits::cpu0.data 3759468 # number of demand (read+write) hits 1284system.cpu0.l2cache.demand_hits::total 9611870 # number of demand (read+write) hits 1285system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 551770 # number of overall hits 1286system.cpu0.l2cache.overall_hits::cpu0.itb.walker 179424 # number of overall hits 1287system.cpu0.l2cache.overall_hits::cpu0.inst 5121208 # number of overall hits 1288system.cpu0.l2cache.overall_hits::cpu0.data 3759468 # number of overall hits 1289system.cpu0.l2cache.overall_hits::total 9611870 # number of overall hits 1290system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12055 # number of ReadReq misses 1291system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8680 # number of ReadReq misses 1292system.cpu0.l2cache.ReadReq_misses::total 20735 # number of ReadReq misses 1293system.cpu0.l2cache.WritebackDirty_misses::writebacks 3 # number of WritebackDirty misses 1294system.cpu0.l2cache.WritebackDirty_misses::total 3 # number of WritebackDirty misses | 1203system.cpu0.l2cache.prefetcher.pfSpanPage 1008365 # number of prefetches not generated due to page crossing 1204system.cpu0.l2cache.tags.replacements 2565485 # number of replacements 1205system.cpu0.l2cache.tags.tagsinuse 15956.741738 # Cycle average of tags in use 1206system.cpu0.l2cache.tags.total_refs 17408441 # Total number of references to valid blocks. 1207system.cpu0.l2cache.tags.sampled_refs 2581334 # Sample count of references to valid blocks. 1208system.cpu0.l2cache.tags.avg_refs 6.743971 # Average number of references to valid blocks. 1209system.cpu0.l2cache.tags.warmup_cycle 2212473000 # Cycle when the warmup percentage was hit. 1210system.cpu0.l2cache.tags.occ_blocks::writebacks 14849.648482 # Average occupied blocks per requestor 1211system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 36.124813 # Average occupied blocks per requestor 1212system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 23.448036 # Average occupied blocks per requestor 1213system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000032 # Average occupied blocks per requestor 1214system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1047.520376 # Average occupied blocks per requestor 1215system.cpu0.l2cache.tags.occ_percent::writebacks 0.906351 # Average percentage of cache occupancy 1216system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002205 # Average percentage of cache occupancy 1217system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001431 # Average percentage of cache occupancy 1218system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy 1219system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063936 # Average percentage of cache occupancy 1220system.cpu0.l2cache.tags.occ_percent::total 0.973922 # Average percentage of cache occupancy 1221system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1203 # Occupied blocks per task id 1222system.cpu0.l2cache.tags.occ_task_id_blocks::1023 77 # Occupied blocks per task id 1223system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14569 # Occupied blocks per task id 1224system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id 1225system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 211 # Occupied blocks per task id 1226system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 564 # Occupied blocks per task id 1227system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 414 # Occupied blocks per task id 1228system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 59 # Occupied blocks per task id 1229system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 1230system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 1231system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id 1232system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1288 # Occupied blocks per task id 1233system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4722 # Occupied blocks per task id 1234system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4695 # Occupied blocks per task id 1235system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3741 # Occupied blocks per task id 1236system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.073425 # Percentage of cache occupancy per task id 1237system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id 1238system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.889221 # Percentage of cache occupancy per task id 1239system.cpu0.l2cache.tags.tag_accesses 408243228 # Number of tag accesses 1240system.cpu0.l2cache.tags.data_accesses 408243228 # Number of data accesses 1241system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 539952 # number of ReadReq hits 1242system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 183800 # number of ReadReq hits 1243system.cpu0.l2cache.ReadReq_hits::total 723752 # number of ReadReq hits 1244system.cpu0.l2cache.WritebackDirty_hits::writebacks 3863126 # number of WritebackDirty hits 1245system.cpu0.l2cache.WritebackDirty_hits::total 3863126 # number of WritebackDirty hits 1246system.cpu0.l2cache.WritebackClean_hits::writebacks 8065215 # number of WritebackClean hits 1247system.cpu0.l2cache.WritebackClean_hits::total 8065215 # number of WritebackClean hits 1248system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 386 # number of UpgradeReq hits 1249system.cpu0.l2cache.UpgradeReq_hits::total 386 # number of UpgradeReq hits 1250system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 6 # number of SCUpgradeReq hits 1251system.cpu0.l2cache.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits 1252system.cpu0.l2cache.ReadExReq_hits::cpu0.data 895474 # number of ReadExReq hits 1253system.cpu0.l2cache.ReadExReq_hits::total 895474 # number of ReadExReq hits 1254system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5563145 # number of ReadCleanReq hits 1255system.cpu0.l2cache.ReadCleanReq_hits::total 5563145 # number of ReadCleanReq hits 1256system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2937118 # number of ReadSharedReq hits 1257system.cpu0.l2cache.ReadSharedReq_hits::total 2937118 # number of ReadSharedReq hits 1258system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 202987 # number of InvalidateReq hits 1259system.cpu0.l2cache.InvalidateReq_hits::total 202987 # number of InvalidateReq hits 1260system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 539952 # number of demand (read+write) hits 1261system.cpu0.l2cache.demand_hits::cpu0.itb.walker 183800 # number of demand (read+write) hits 1262system.cpu0.l2cache.demand_hits::cpu0.inst 5563145 # number of demand (read+write) hits 1263system.cpu0.l2cache.demand_hits::cpu0.data 3832592 # number of demand (read+write) hits 1264system.cpu0.l2cache.demand_hits::total 10119489 # number of demand (read+write) hits 1265system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 539952 # number of overall hits 1266system.cpu0.l2cache.overall_hits::cpu0.itb.walker 183800 # number of overall hits 1267system.cpu0.l2cache.overall_hits::cpu0.inst 5563145 # number of overall hits 1268system.cpu0.l2cache.overall_hits::cpu0.data 3832592 # number of overall hits 1269system.cpu0.l2cache.overall_hits::total 10119489 # number of overall hits 1270system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10772 # number of ReadReq misses 1271system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7627 # number of ReadReq misses 1272system.cpu0.l2cache.ReadReq_misses::total 18399 # number of ReadReq misses 1273system.cpu0.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses 1274system.cpu0.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses |
| 1295system.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 1296system.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses | 1275system.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 1276system.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses |
| 1297system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 264383 # number of UpgradeReq misses 1298system.cpu0.l2cache.UpgradeReq_misses::total 264383 # number of UpgradeReq misses 1299system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 190766 # number of SCUpgradeReq misses 1300system.cpu0.l2cache.SCUpgradeReq_misses::total 190766 # number of SCUpgradeReq misses 1301system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses 1302system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 1303system.cpu0.l2cache.ReadExReq_misses::cpu0.data 327479 # number of ReadExReq misses 1304system.cpu0.l2cache.ReadExReq_misses::total 327479 # number of ReadExReq misses 1305system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 560388 # number of ReadCleanReq misses 1306system.cpu0.l2cache.ReadCleanReq_misses::total 560388 # number of ReadCleanReq misses 1307system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1024494 # number of ReadSharedReq misses 1308system.cpu0.l2cache.ReadSharedReq_misses::total 1024494 # number of ReadSharedReq misses 1309system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 598286 # number of InvalidateReq misses 1310system.cpu0.l2cache.InvalidateReq_misses::total 598286 # number of InvalidateReq misses 1311system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12055 # number of demand (read+write) misses 1312system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8680 # number of demand (read+write) misses 1313system.cpu0.l2cache.demand_misses::cpu0.inst 560388 # number of demand (read+write) misses 1314system.cpu0.l2cache.demand_misses::cpu0.data 1351973 # number of demand (read+write) misses 1315system.cpu0.l2cache.demand_misses::total 1933096 # number of demand (read+write) misses 1316system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12055 # number of overall misses 1317system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8680 # number of overall misses 1318system.cpu0.l2cache.overall_misses::cpu0.inst 560388 # number of overall misses 1319system.cpu0.l2cache.overall_misses::cpu0.data 1351973 # number of overall misses 1320system.cpu0.l2cache.overall_misses::total 1933096 # number of overall misses 1321system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 639534000 # number of ReadReq miss cycles 1322system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 449293500 # number of ReadReq miss cycles 1323system.cpu0.l2cache.ReadReq_miss_latency::total 1088827500 # number of ReadReq miss cycles 1324system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3359987500 # number of UpgradeReq miss cycles 1325system.cpu0.l2cache.UpgradeReq_miss_latency::total 3359987500 # number of UpgradeReq miss cycles 1326system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1839849500 # number of SCUpgradeReq miss cycles 1327system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1839849500 # number of SCUpgradeReq miss cycles 1328system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 5649000 # number of SCUpgradeFailReq miss cycles 1329system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 5649000 # number of SCUpgradeFailReq miss cycles 1330system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 21332705499 # number of ReadExReq miss cycles 1331system.cpu0.l2cache.ReadExReq_miss_latency::total 21332705499 # number of ReadExReq miss cycles 1332system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 22152073000 # number of ReadCleanReq miss cycles 1333system.cpu0.l2cache.ReadCleanReq_miss_latency::total 22152073000 # number of ReadCleanReq miss cycles 1334system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 44214750984 # number of ReadSharedReq miss cycles 1335system.cpu0.l2cache.ReadSharedReq_miss_latency::total 44214750984 # number of ReadSharedReq miss cycles 1336system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 435322500 # number of InvalidateReq miss cycles 1337system.cpu0.l2cache.InvalidateReq_miss_latency::total 435322500 # number of InvalidateReq miss cycles 1338system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 639534000 # number of demand (read+write) miss cycles 1339system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 449293500 # number of demand (read+write) miss cycles 1340system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22152073000 # number of demand (read+write) miss cycles 1341system.cpu0.l2cache.demand_miss_latency::cpu0.data 65547456483 # number of demand (read+write) miss cycles 1342system.cpu0.l2cache.demand_miss_latency::total 88788356983 # number of demand (read+write) miss cycles 1343system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 639534000 # number of overall miss cycles 1344system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 449293500 # number of overall miss cycles 1345system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22152073000 # number of overall miss cycles 1346system.cpu0.l2cache.overall_miss_latency::cpu0.data 65547456483 # number of overall miss cycles 1347system.cpu0.l2cache.overall_miss_latency::total 88788356983 # number of overall miss cycles 1348system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 563825 # number of ReadReq accesses(hits+misses) 1349system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 188104 # number of ReadReq accesses(hits+misses) 1350system.cpu0.l2cache.ReadReq_accesses::total 751929 # number of ReadReq accesses(hits+misses) 1351system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3854490 # number of WritebackDirty accesses(hits+misses) 1352system.cpu0.l2cache.WritebackDirty_accesses::total 3854490 # number of WritebackDirty accesses(hits+misses) 1353system.cpu0.l2cache.WritebackClean_accesses::writebacks 7627203 # number of WritebackClean accesses(hits+misses) 1354system.cpu0.l2cache.WritebackClean_accesses::total 7627203 # number of WritebackClean accesses(hits+misses) 1355system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 265037 # number of UpgradeReq accesses(hits+misses) 1356system.cpu0.l2cache.UpgradeReq_accesses::total 265037 # number of UpgradeReq accesses(hits+misses) 1357system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 190771 # number of SCUpgradeReq accesses(hits+misses) 1358system.cpu0.l2cache.SCUpgradeReq_accesses::total 190771 # number of SCUpgradeReq accesses(hits+misses) 1359system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 6 # number of SCUpgradeFailReq accesses(hits+misses) 1360system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) 1361system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1206013 # number of ReadExReq accesses(hits+misses) 1362system.cpu0.l2cache.ReadExReq_accesses::total 1206013 # number of ReadExReq accesses(hits+misses) 1363system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5681596 # number of ReadCleanReq accesses(hits+misses) 1364system.cpu0.l2cache.ReadCleanReq_accesses::total 5681596 # number of ReadCleanReq accesses(hits+misses) 1365system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3905428 # number of ReadSharedReq accesses(hits+misses) 1366system.cpu0.l2cache.ReadSharedReq_accesses::total 3905428 # number of ReadSharedReq accesses(hits+misses) 1367system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 786739 # number of InvalidateReq accesses(hits+misses) 1368system.cpu0.l2cache.InvalidateReq_accesses::total 786739 # number of InvalidateReq accesses(hits+misses) 1369system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 563825 # number of demand (read+write) accesses 1370system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 188104 # number of demand (read+write) accesses 1371system.cpu0.l2cache.demand_accesses::cpu0.inst 5681596 # number of demand (read+write) accesses 1372system.cpu0.l2cache.demand_accesses::cpu0.data 5111441 # number of demand (read+write) accesses 1373system.cpu0.l2cache.demand_accesses::total 11544966 # number of demand (read+write) accesses 1374system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 563825 # number of overall (read+write) accesses 1375system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 188104 # number of overall (read+write) accesses 1376system.cpu0.l2cache.overall_accesses::cpu0.inst 5681596 # number of overall (read+write) accesses 1377system.cpu0.l2cache.overall_accesses::cpu0.data 5111441 # number of overall (read+write) accesses 1378system.cpu0.l2cache.overall_accesses::total 11544966 # number of overall (read+write) accesses 1379system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021381 # miss rate for ReadReq accesses 1380system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.046145 # miss rate for ReadReq accesses 1381system.cpu0.l2cache.ReadReq_miss_rate::total 0.027576 # miss rate for ReadReq accesses | 1277system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 260447 # number of UpgradeReq misses 1278system.cpu0.l2cache.UpgradeReq_misses::total 260447 # number of UpgradeReq misses 1279system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 187318 # number of SCUpgradeReq misses 1280system.cpu0.l2cache.SCUpgradeReq_misses::total 187318 # number of SCUpgradeReq misses 1281system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # number of SCUpgradeFailReq misses 1282system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses 1283system.cpu0.l2cache.ReadExReq_misses::cpu0.data 288236 # number of ReadExReq misses 1284system.cpu0.l2cache.ReadExReq_misses::total 288236 # number of ReadExReq misses 1285system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 573862 # number of ReadCleanReq misses 1286system.cpu0.l2cache.ReadCleanReq_misses::total 573862 # number of ReadCleanReq misses 1287system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 973549 # number of ReadSharedReq misses 1288system.cpu0.l2cache.ReadSharedReq_misses::total 973549 # number of ReadSharedReq misses 1289system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 600983 # number of InvalidateReq misses 1290system.cpu0.l2cache.InvalidateReq_misses::total 600983 # number of InvalidateReq misses 1291system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10772 # number of demand (read+write) misses 1292system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7627 # number of demand (read+write) misses 1293system.cpu0.l2cache.demand_misses::cpu0.inst 573862 # number of demand (read+write) misses 1294system.cpu0.l2cache.demand_misses::cpu0.data 1261785 # number of demand (read+write) misses 1295system.cpu0.l2cache.demand_misses::total 1854046 # number of demand (read+write) misses 1296system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10772 # number of overall misses 1297system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7627 # number of overall misses 1298system.cpu0.l2cache.overall_misses::cpu0.inst 573862 # number of overall misses 1299system.cpu0.l2cache.overall_misses::cpu0.data 1261785 # number of overall misses 1300system.cpu0.l2cache.overall_misses::total 1854046 # number of overall misses 1301system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 369514500 # number of ReadReq miss cycles 1302system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 247873000 # number of ReadReq miss cycles 1303system.cpu0.l2cache.ReadReq_miss_latency::total 617387500 # number of ReadReq miss cycles 1304system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2108131500 # number of UpgradeReq miss cycles 1305system.cpu0.l2cache.UpgradeReq_miss_latency::total 2108131500 # number of UpgradeReq miss cycles 1306system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1419046500 # number of SCUpgradeReq miss cycles 1307system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1419046500 # number of SCUpgradeReq miss cycles 1308system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3609499 # number of SCUpgradeFailReq miss cycles 1309system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3609499 # number of SCUpgradeFailReq miss cycles 1310system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 14578954500 # number of ReadExReq miss cycles 1311system.cpu0.l2cache.ReadExReq_miss_latency::total 14578954500 # number of ReadExReq miss cycles 1312system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 20073597500 # number of ReadCleanReq miss cycles 1313system.cpu0.l2cache.ReadCleanReq_miss_latency::total 20073597500 # number of ReadCleanReq miss cycles 1314system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 34202997471 # number of ReadSharedReq miss cycles 1315system.cpu0.l2cache.ReadSharedReq_miss_latency::total 34202997471 # number of ReadSharedReq miss cycles 1316system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 348158000 # number of InvalidateReq miss cycles 1317system.cpu0.l2cache.InvalidateReq_miss_latency::total 348158000 # number of InvalidateReq miss cycles 1318system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 369514500 # number of demand (read+write) miss cycles 1319system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 247873000 # number of demand (read+write) miss cycles 1320system.cpu0.l2cache.demand_miss_latency::cpu0.inst 20073597500 # number of demand (read+write) miss cycles 1321system.cpu0.l2cache.demand_miss_latency::cpu0.data 48781951971 # number of demand (read+write) miss cycles 1322system.cpu0.l2cache.demand_miss_latency::total 69472936971 # number of demand (read+write) miss cycles 1323system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 369514500 # number of overall miss cycles 1324system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 247873000 # number of overall miss cycles 1325system.cpu0.l2cache.overall_miss_latency::cpu0.inst 20073597500 # number of overall miss cycles 1326system.cpu0.l2cache.overall_miss_latency::cpu0.data 48781951971 # number of overall miss cycles 1327system.cpu0.l2cache.overall_miss_latency::total 69472936971 # number of overall miss cycles 1328system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 550724 # number of ReadReq accesses(hits+misses) 1329system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 191427 # number of ReadReq accesses(hits+misses) 1330system.cpu0.l2cache.ReadReq_accesses::total 742151 # number of ReadReq accesses(hits+misses) 1331system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3863128 # number of WritebackDirty accesses(hits+misses) 1332system.cpu0.l2cache.WritebackDirty_accesses::total 3863128 # number of WritebackDirty accesses(hits+misses) 1333system.cpu0.l2cache.WritebackClean_accesses::writebacks 8065216 # number of WritebackClean accesses(hits+misses) 1334system.cpu0.l2cache.WritebackClean_accesses::total 8065216 # number of WritebackClean accesses(hits+misses) 1335system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 260833 # number of UpgradeReq accesses(hits+misses) 1336system.cpu0.l2cache.UpgradeReq_accesses::total 260833 # number of UpgradeReq accesses(hits+misses) 1337system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 187324 # number of SCUpgradeReq accesses(hits+misses) 1338system.cpu0.l2cache.SCUpgradeReq_accesses::total 187324 # number of SCUpgradeReq accesses(hits+misses) 1339system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 7 # number of SCUpgradeFailReq accesses(hits+misses) 1340system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) 1341system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1183710 # number of ReadExReq accesses(hits+misses) 1342system.cpu0.l2cache.ReadExReq_accesses::total 1183710 # number of ReadExReq accesses(hits+misses) 1343system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6137007 # number of ReadCleanReq accesses(hits+misses) 1344system.cpu0.l2cache.ReadCleanReq_accesses::total 6137007 # number of ReadCleanReq accesses(hits+misses) 1345system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3910667 # number of ReadSharedReq accesses(hits+misses) 1346system.cpu0.l2cache.ReadSharedReq_accesses::total 3910667 # number of ReadSharedReq accesses(hits+misses) 1347system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 803970 # number of InvalidateReq accesses(hits+misses) 1348system.cpu0.l2cache.InvalidateReq_accesses::total 803970 # number of InvalidateReq accesses(hits+misses) 1349system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 550724 # number of demand (read+write) accesses 1350system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 191427 # number of demand (read+write) accesses 1351system.cpu0.l2cache.demand_accesses::cpu0.inst 6137007 # number of demand (read+write) accesses 1352system.cpu0.l2cache.demand_accesses::cpu0.data 5094377 # number of demand (read+write) accesses 1353system.cpu0.l2cache.demand_accesses::total 11973535 # number of demand (read+write) accesses 1354system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 550724 # number of overall (read+write) accesses 1355system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 191427 # number of overall (read+write) accesses 1356system.cpu0.l2cache.overall_accesses::cpu0.inst 6137007 # number of overall (read+write) accesses 1357system.cpu0.l2cache.overall_accesses::cpu0.data 5094377 # number of overall (read+write) accesses 1358system.cpu0.l2cache.overall_accesses::total 11973535 # number of overall (read+write) accesses 1359system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.019560 # miss rate for ReadReq accesses 1360system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.039843 # miss rate for ReadReq accesses 1361system.cpu0.l2cache.ReadReq_miss_rate::total 0.024791 # miss rate for ReadReq accesses |
| 1382system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses 1383system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses 1384system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 1385system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses | 1362system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses 1363system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses 1364system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 1365system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses |
| 1386system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.997532 # miss rate for UpgradeReq accesses 1387system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.997532 # miss rate for UpgradeReq accesses 1388system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999974 # miss rate for SCUpgradeReq accesses 1389system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999974 # miss rate for SCUpgradeReq accesses | 1366system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998520 # miss rate for UpgradeReq accesses 1367system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998520 # miss rate for UpgradeReq accesses 1368system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999968 # miss rate for SCUpgradeReq accesses 1369system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999968 # miss rate for SCUpgradeReq accesses |
| 1390system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1391system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 1370system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1371system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 1392system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.271539 # miss rate for ReadExReq accesses 1393system.cpu0.l2cache.ReadExReq_miss_rate::total 0.271539 # miss rate for ReadExReq accesses 1394system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.098632 # miss rate for ReadCleanReq accesses 1395system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.098632 # miss rate for ReadCleanReq accesses 1396system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.262326 # miss rate for ReadSharedReq accesses 1397system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.262326 # miss rate for ReadSharedReq accesses 1398system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.760463 # miss rate for InvalidateReq accesses 1399system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.760463 # miss rate for InvalidateReq accesses 1400system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021381 # miss rate for demand accesses 1401system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.046145 # miss rate for demand accesses 1402system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.098632 # miss rate for demand accesses 1403system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.264499 # miss rate for demand accesses 1404system.cpu0.l2cache.demand_miss_rate::total 0.167441 # miss rate for demand accesses 1405system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021381 # miss rate for overall accesses 1406system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.046145 # miss rate for overall accesses 1407system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.098632 # miss rate for overall accesses 1408system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.264499 # miss rate for overall accesses 1409system.cpu0.l2cache.overall_miss_rate::total 0.167441 # miss rate for overall accesses 1410system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 53051.347988 # average ReadReq miss latency 1411system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 51761.923963 # average ReadReq miss latency 1412system.cpu0.l2cache.ReadReq_avg_miss_latency::total 52511.574632 # average ReadReq miss latency 1413system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 12708.788008 # average UpgradeReq miss latency 1414system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 12708.788008 # average UpgradeReq miss latency 1415system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 9644.535714 # average SCUpgradeReq miss latency 1416system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 9644.535714 # average SCUpgradeReq miss latency 1417system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 941500 # average SCUpgradeFailReq miss latency 1418system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 941500 # average SCUpgradeFailReq miss latency 1419system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 65142.209116 # average ReadExReq miss latency 1420system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 65142.209116 # average ReadExReq miss latency 1421system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39529.884651 # average ReadCleanReq miss latency 1422system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39529.884651 # average ReadCleanReq miss latency 1423system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 43157.647565 # average ReadSharedReq miss latency 1424system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 43157.647565 # average ReadSharedReq miss latency 1425system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 727.616057 # average InvalidateReq miss latency 1426system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 727.616057 # average InvalidateReq miss latency 1427system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 53051.347988 # average overall miss latency 1428system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 51761.923963 # average overall miss latency 1429system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39529.884651 # average overall miss latency 1430system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 48482.814733 # average overall miss latency 1431system.cpu0.l2cache.demand_avg_miss_latency::total 45930.650616 # average overall miss latency 1432system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 53051.347988 # average overall miss latency 1433system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 51761.923963 # average overall miss latency 1434system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39529.884651 # average overall miss latency 1435system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 48482.814733 # average overall miss latency 1436system.cpu0.l2cache.overall_avg_miss_latency::total 45930.650616 # average overall miss latency 1437system.cpu0.l2cache.blocked_cycles::no_mshrs 710 # number of cycles access was blocked | 1372system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.243502 # miss rate for ReadExReq accesses 1373system.cpu0.l2cache.ReadExReq_miss_rate::total 0.243502 # miss rate for ReadExReq accesses 1374system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.093508 # miss rate for ReadCleanReq accesses 1375system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.093508 # miss rate for ReadCleanReq accesses 1376system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.248947 # miss rate for ReadSharedReq accesses 1377system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.248947 # miss rate for ReadSharedReq accesses 1378system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.747519 # miss rate for InvalidateReq accesses 1379system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.747519 # miss rate for InvalidateReq accesses 1380system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.019560 # miss rate for demand accesses 1381system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.039843 # miss rate for demand accesses 1382system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.093508 # miss rate for demand accesses 1383system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.247682 # miss rate for demand accesses 1384system.cpu0.l2cache.demand_miss_rate::total 0.154845 # miss rate for demand accesses 1385system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.019560 # miss rate for overall accesses 1386system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.039843 # miss rate for overall accesses 1387system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.093508 # miss rate for overall accesses 1388system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.247682 # miss rate for overall accesses 1389system.cpu0.l2cache.overall_miss_rate::total 0.154845 # miss rate for overall accesses 1390system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34303.239881 # average ReadReq miss latency 1391system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 32499.409991 # average ReadReq miss latency 1392system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33555.492146 # average ReadReq miss latency 1393system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 8094.282138 # average UpgradeReq miss latency 1394system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 8094.282138 # average UpgradeReq miss latency 1395system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 7575.601384 # average SCUpgradeReq miss latency 1396system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 7575.601384 # average SCUpgradeReq miss latency 1397system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 515642.714286 # average SCUpgradeFailReq miss latency 1398system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 515642.714286 # average SCUpgradeFailReq miss latency 1399system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50579.922355 # average ReadExReq miss latency 1400system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50579.922355 # average ReadExReq miss latency 1401system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 34979.834002 # average ReadCleanReq miss latency 1402system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 34979.834002 # average ReadCleanReq miss latency 1403system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35132.281448 # average ReadSharedReq miss latency 1404system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35132.281448 # average ReadSharedReq miss latency 1405system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 579.314224 # average InvalidateReq miss latency 1406system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 579.314224 # average InvalidateReq miss latency 1407system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34303.239881 # average overall miss latency 1408system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 32499.409991 # average overall miss latency 1409system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34979.834002 # average overall miss latency 1410system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38661.065055 # average overall miss latency 1411system.cpu0.l2cache.demand_avg_miss_latency::total 37470.988838 # average overall miss latency 1412system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34303.239881 # average overall miss latency 1413system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 32499.409991 # average overall miss latency 1414system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34979.834002 # average overall miss latency 1415system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38661.065055 # average overall miss latency 1416system.cpu0.l2cache.overall_avg_miss_latency::total 37470.988838 # average overall miss latency 1417system.cpu0.l2cache.blocked_cycles::no_mshrs 395 # number of cycles access was blocked |
| 1438system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1418system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1439system.cpu0.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked | 1419system.cpu0.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked |
| 1440system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1420system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1441system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 118.333333 # average number of cycles each access was blocked | 1421system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 56.428571 # average number of cycles each access was blocked |
| 1442system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1422system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1443system.cpu0.l2cache.unused_prefetches 45316 # number of HardPF blocks evicted w/o reference 1444system.cpu0.l2cache.writebacks::writebacks 1671374 # number of writebacks 1445system.cpu0.l2cache.writebacks::total 1671374 # number of writebacks 1446system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 3 # number of ReadReq MSHR hits 1447system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 14 # number of ReadReq MSHR hits 1448system.cpu0.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits 1449system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 47908 # number of ReadExReq MSHR hits 1450system.cpu0.l2cache.ReadExReq_mshr_hits::total 47908 # number of ReadExReq MSHR hits 1451system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 7 # number of ReadCleanReq MSHR hits 1452system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits 1453system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 5947 # number of ReadSharedReq MSHR hits 1454system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 5947 # number of ReadSharedReq MSHR hits 1455system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 12 # number of InvalidateReq MSHR hits 1456system.cpu0.l2cache.InvalidateReq_mshr_hits::total 12 # number of InvalidateReq MSHR hits 1457system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 3 # number of demand (read+write) MSHR hits 1458system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 14 # number of demand (read+write) MSHR hits 1459system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits 1460system.cpu0.l2cache.demand_mshr_hits::cpu0.data 53855 # number of demand (read+write) MSHR hits 1461system.cpu0.l2cache.demand_mshr_hits::total 53879 # number of demand (read+write) MSHR hits 1462system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 3 # number of overall MSHR hits 1463system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 14 # number of overall MSHR hits 1464system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits 1465system.cpu0.l2cache.overall_mshr_hits::cpu0.data 53855 # number of overall MSHR hits 1466system.cpu0.l2cache.overall_mshr_hits::total 53879 # number of overall MSHR hits 1467system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12052 # number of ReadReq MSHR misses 1468system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8666 # number of ReadReq MSHR misses 1469system.cpu0.l2cache.ReadReq_mshr_misses::total 20718 # number of ReadReq MSHR misses 1470system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 3 # number of WritebackDirty MSHR misses 1471system.cpu0.l2cache.WritebackDirty_mshr_misses::total 3 # number of WritebackDirty MSHR misses | 1423system.cpu0.l2cache.unused_prefetches 43030 # number of HardPF blocks evicted w/o reference 1424system.cpu0.l2cache.writebacks::writebacks 1602911 # number of writebacks 1425system.cpu0.l2cache.writebacks::total 1602911 # number of writebacks 1426system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 2 # number of ReadReq MSHR hits 1427system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 13 # number of ReadReq MSHR hits 1428system.cpu0.l2cache.ReadReq_mshr_hits::total 15 # number of ReadReq MSHR hits 1429system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 13671 # number of ReadExReq MSHR hits 1430system.cpu0.l2cache.ReadExReq_mshr_hits::total 13671 # number of ReadExReq MSHR hits 1431system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 3 # number of ReadCleanReq MSHR hits 1432system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 1433system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 5375 # number of ReadSharedReq MSHR hits 1434system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 5375 # number of ReadSharedReq MSHR hits 1435system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 2 # number of demand (read+write) MSHR hits 1436system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 13 # number of demand (read+write) MSHR hits 1437system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits 1438system.cpu0.l2cache.demand_mshr_hits::cpu0.data 19046 # number of demand (read+write) MSHR hits 1439system.cpu0.l2cache.demand_mshr_hits::total 19064 # number of demand (read+write) MSHR hits 1440system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 2 # number of overall MSHR hits 1441system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 13 # number of overall MSHR hits 1442system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits 1443system.cpu0.l2cache.overall_mshr_hits::cpu0.data 19046 # number of overall MSHR hits 1444system.cpu0.l2cache.overall_mshr_hits::total 19064 # number of overall MSHR hits 1445system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10770 # number of ReadReq MSHR misses 1446system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7614 # number of ReadReq MSHR misses 1447system.cpu0.l2cache.ReadReq_mshr_misses::total 18384 # number of ReadReq MSHR misses 1448system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 2 # number of WritebackDirty MSHR misses 1449system.cpu0.l2cache.WritebackDirty_mshr_misses::total 2 # number of WritebackDirty MSHR misses |
| 1472system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 1473system.cpu0.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses | 1450system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 1451system.cpu0.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses |
| 1474system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 803197 # number of HardPFReq MSHR misses 1475system.cpu0.l2cache.HardPFReq_mshr_misses::total 803197 # number of HardPFReq MSHR misses 1476system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 264383 # number of UpgradeReq MSHR misses 1477system.cpu0.l2cache.UpgradeReq_mshr_misses::total 264383 # number of UpgradeReq MSHR misses 1478system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 190766 # number of SCUpgradeReq MSHR misses 1479system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 190766 # number of SCUpgradeReq MSHR misses 1480system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses 1481system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses 1482system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 279571 # number of ReadExReq MSHR misses 1483system.cpu0.l2cache.ReadExReq_mshr_misses::total 279571 # number of ReadExReq MSHR misses 1484system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 560381 # number of ReadCleanReq MSHR misses 1485system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 560381 # number of ReadCleanReq MSHR misses 1486system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1018547 # number of ReadSharedReq MSHR misses 1487system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1018547 # number of ReadSharedReq MSHR misses 1488system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 598274 # number of InvalidateReq MSHR misses 1489system.cpu0.l2cache.InvalidateReq_mshr_misses::total 598274 # number of InvalidateReq MSHR misses 1490system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12052 # number of demand (read+write) MSHR misses 1491system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8666 # number of demand (read+write) MSHR misses 1492system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 560381 # number of demand (read+write) MSHR misses 1493system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1298118 # number of demand (read+write) MSHR misses 1494system.cpu0.l2cache.demand_mshr_misses::total 1879217 # number of demand (read+write) MSHR misses 1495system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12052 # number of overall MSHR misses 1496system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8666 # number of overall MSHR misses 1497system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 560381 # number of overall MSHR misses 1498system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1298118 # number of overall MSHR misses 1499system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 803197 # number of overall MSHR misses 1500system.cpu0.l2cache.overall_mshr_misses::total 2682414 # number of overall MSHR misses | 1452system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 773321 # number of HardPFReq MSHR misses 1453system.cpu0.l2cache.HardPFReq_mshr_misses::total 773321 # number of HardPFReq MSHR misses 1454system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 260447 # number of UpgradeReq MSHR misses 1455system.cpu0.l2cache.UpgradeReq_mshr_misses::total 260447 # number of UpgradeReq MSHR misses 1456system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 187318 # number of SCUpgradeReq MSHR misses 1457system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 187318 # number of SCUpgradeReq MSHR misses 1458system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 7 # number of SCUpgradeFailReq MSHR misses 1459system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses 1460system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 274565 # number of ReadExReq MSHR misses 1461system.cpu0.l2cache.ReadExReq_mshr_misses::total 274565 # number of ReadExReq MSHR misses 1462system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 573859 # number of ReadCleanReq MSHR misses 1463system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 573859 # number of ReadCleanReq MSHR misses 1464system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 968174 # number of ReadSharedReq MSHR misses 1465system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 968174 # number of ReadSharedReq MSHR misses 1466system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 600983 # number of InvalidateReq MSHR misses 1467system.cpu0.l2cache.InvalidateReq_mshr_misses::total 600983 # number of InvalidateReq MSHR misses 1468system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10770 # number of demand (read+write) MSHR misses 1469system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7614 # number of demand (read+write) MSHR misses 1470system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 573859 # number of demand (read+write) MSHR misses 1471system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1242739 # number of demand (read+write) MSHR misses 1472system.cpu0.l2cache.demand_mshr_misses::total 1834982 # number of demand (read+write) MSHR misses 1473system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10770 # number of overall MSHR misses 1474system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7614 # number of overall MSHR misses 1475system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 573859 # number of overall MSHR misses 1476system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1242739 # number of overall MSHR misses 1477system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 773321 # number of overall MSHR misses 1478system.cpu0.l2cache.overall_mshr_misses::total 2608303 # number of overall MSHR misses |
| 1501system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable | 1479system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable |
| 1502system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 19706 # number of ReadReq MSHR uncacheable 1503system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40999 # number of ReadReq MSHR uncacheable 1504system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 21266 # number of WriteReq MSHR uncacheable 1505system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 21266 # number of WriteReq MSHR uncacheable | 1480system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32527 # number of ReadReq MSHR uncacheable 1481system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 53820 # number of ReadReq MSHR uncacheable 1482system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32351 # number of WriteReq MSHR uncacheable 1483system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32351 # number of WriteReq MSHR uncacheable |
| 1506system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses | 1484system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses |
| 1507system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 40972 # number of overall MSHR uncacheable misses 1508system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 62265 # number of overall MSHR uncacheable misses 1509system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 567159000 # number of ReadReq MSHR miss cycles 1510system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 396729500 # number of ReadReq MSHR miss cycles 1511system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 963888500 # number of ReadReq MSHR miss cycles 1512system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 57196003159 # number of HardPFReq MSHR miss cycles 1513system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 57196003159 # number of HardPFReq MSHR miss cycles 1514system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7687713495 # number of UpgradeReq MSHR miss cycles 1515system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7687713495 # number of UpgradeReq MSHR miss cycles 1516system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3687086997 # number of SCUpgradeReq MSHR miss cycles 1517system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3687086997 # number of SCUpgradeReq MSHR miss cycles 1518system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 5229000 # number of SCUpgradeFailReq MSHR miss cycles 1519system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 5229000 # number of SCUpgradeFailReq MSHR miss cycles 1520system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 16511973000 # number of ReadExReq MSHR miss cycles 1521system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 16511973000 # number of ReadExReq MSHR miss cycles 1522system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 18789663000 # number of ReadCleanReq MSHR miss cycles 1523system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 18789663000 # number of ReadCleanReq MSHR miss cycles 1524system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 37621826984 # number of ReadSharedReq MSHR miss cycles 1525system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 37621826984 # number of ReadSharedReq MSHR miss cycles 1526system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 42300516999 # number of InvalidateReq MSHR miss cycles 1527system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 42300516999 # number of InvalidateReq MSHR miss cycles 1528system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 567159000 # number of demand (read+write) MSHR miss cycles 1529system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 396729500 # number of demand (read+write) MSHR miss cycles 1530system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 18789663000 # number of demand (read+write) MSHR miss cycles 1531system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 54133799984 # number of demand (read+write) MSHR miss cycles 1532system.cpu0.l2cache.demand_mshr_miss_latency::total 73887351484 # number of demand (read+write) MSHR miss cycles 1533system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 567159000 # number of overall MSHR miss cycles 1534system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 396729500 # number of overall MSHR miss cycles 1535system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 18789663000 # number of overall MSHR miss cycles 1536system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 54133799984 # number of overall MSHR miss cycles 1537system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 57196003159 # number of overall MSHR miss cycles 1538system.cpu0.l2cache.overall_mshr_miss_latency::total 131083354643 # number of overall MSHR miss cycles 1539system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780082000 # number of ReadReq MSHR uncacheable cycles 1540system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3705524000 # number of ReadReq MSHR uncacheable cycles 1541system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6485606000 # number of ReadReq MSHR uncacheable cycles 1542system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 2780082000 # number of overall MSHR uncacheable cycles 1543system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 3705524000 # number of overall MSHR uncacheable cycles 1544system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6485606000 # number of overall MSHR uncacheable cycles 1545system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021375 # mshr miss rate for ReadReq accesses 1546system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.046070 # mshr miss rate for ReadReq accesses 1547system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027553 # mshr miss rate for ReadReq accesses | 1485system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 64878 # number of overall MSHR uncacheable misses 1486system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 86171 # number of overall MSHR uncacheable misses 1487system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 304850000 # number of ReadReq MSHR miss cycles 1488system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 201976000 # number of ReadReq MSHR miss cycles 1489system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 506826000 # number of ReadReq MSHR miss cycles 1490system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 36226481632 # number of HardPFReq MSHR miss cycles 1491system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 36226481632 # number of HardPFReq MSHR miss cycles 1492system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 5428667497 # number of UpgradeReq MSHR miss cycles 1493system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 5428667497 # number of UpgradeReq MSHR miss cycles 1494system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3091853999 # number of SCUpgradeReq MSHR miss cycles 1495system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3091853999 # number of SCUpgradeReq MSHR miss cycles 1496system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 3183499 # number of SCUpgradeFailReq MSHR miss cycles 1497system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3183499 # number of SCUpgradeFailReq MSHR miss cycles 1498system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11062749000 # number of ReadExReq MSHR miss cycles 1499system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11062749000 # number of ReadExReq MSHR miss cycles 1500system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 16630399500 # number of ReadCleanReq MSHR miss cycles 1501system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 16630399500 # number of ReadCleanReq MSHR miss cycles 1502system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 28032243476 # number of ReadSharedReq MSHR miss cycles 1503system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 28032243476 # number of ReadSharedReq MSHR miss cycles 1504system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 21947187999 # number of InvalidateReq MSHR miss cycles 1505system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 21947187999 # number of InvalidateReq MSHR miss cycles 1506system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 304850000 # number of demand (read+write) MSHR miss cycles 1507system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 201976000 # number of demand (read+write) MSHR miss cycles 1508system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 16630399500 # number of demand (read+write) MSHR miss cycles 1509system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 39094992476 # number of demand (read+write) MSHR miss cycles 1510system.cpu0.l2cache.demand_mshr_miss_latency::total 56232217976 # number of demand (read+write) MSHR miss cycles 1511system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 304850000 # number of overall MSHR miss cycles 1512system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 201976000 # number of overall MSHR miss cycles 1513system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 16630399500 # number of overall MSHR miss cycles 1514system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 39094992476 # number of overall MSHR miss cycles 1515system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 36226481632 # number of overall MSHR miss cycles 1516system.cpu0.l2cache.overall_mshr_miss_latency::total 92458699608 # number of overall MSHR miss cycles 1517system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1725979000 # number of ReadReq MSHR uncacheable cycles 1518system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5947854500 # number of ReadReq MSHR uncacheable cycles 1519system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7673833500 # number of ReadReq MSHR uncacheable cycles 1520system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1725979000 # number of overall MSHR uncacheable cycles 1521system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5947854500 # number of overall MSHR uncacheable cycles 1522system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7673833500 # number of overall MSHR uncacheable cycles 1523system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.019556 # mshr miss rate for ReadReq accesses 1524system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.039775 # mshr miss rate for ReadReq accesses 1525system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.024771 # mshr miss rate for ReadReq accesses |
| 1548system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 1549system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses 1550system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 1551system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 1552system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1553system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1526system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 1527system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses 1528system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 1529system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 1530system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1531system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1554system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997532 # mshr miss rate for UpgradeReq accesses 1555system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997532 # mshr miss rate for UpgradeReq accesses 1556system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999974 # mshr miss rate for SCUpgradeReq accesses 1557system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999974 # mshr miss rate for SCUpgradeReq accesses | 1532system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998520 # mshr miss rate for UpgradeReq accesses 1533system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998520 # mshr miss rate for UpgradeReq accesses 1534system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999968 # mshr miss rate for SCUpgradeReq accesses 1535system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999968 # mshr miss rate for SCUpgradeReq accesses |
| 1558system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1559system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 1536system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1537system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 1560system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.231814 # mshr miss rate for ReadExReq accesses 1561system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231814 # mshr miss rate for ReadExReq accesses 1562system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.098631 # mshr miss rate for ReadCleanReq accesses 1563system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098631 # mshr miss rate for ReadCleanReq accesses 1564system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.260803 # mshr miss rate for ReadSharedReq accesses 1565system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.260803 # mshr miss rate for ReadSharedReq accesses 1566system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.760448 # mshr miss rate for InvalidateReq accesses 1567system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.760448 # mshr miss rate for InvalidateReq accesses 1568system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021375 # mshr miss rate for demand accesses 1569system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046070 # mshr miss rate for demand accesses 1570system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.098631 # mshr miss rate for demand accesses 1571system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.253963 # mshr miss rate for demand accesses 1572system.cpu0.l2cache.demand_mshr_miss_rate::total 0.162774 # mshr miss rate for demand accesses 1573system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021375 # mshr miss rate for overall accesses 1574system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046070 # mshr miss rate for overall accesses 1575system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.098631 # mshr miss rate for overall accesses 1576system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.253963 # mshr miss rate for overall accesses | 1538system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.231953 # mshr miss rate for ReadExReq accesses 1539system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231953 # mshr miss rate for ReadExReq accesses 1540system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.093508 # mshr miss rate for ReadCleanReq accesses 1541system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.093508 # mshr miss rate for ReadCleanReq accesses 1542system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.247573 # mshr miss rate for ReadSharedReq accesses 1543system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.247573 # mshr miss rate for ReadSharedReq accesses 1544system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.747519 # mshr miss rate for InvalidateReq accesses 1545system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.747519 # mshr miss rate for InvalidateReq accesses 1546system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.019556 # mshr miss rate for demand accesses 1547system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.039775 # mshr miss rate for demand accesses 1548system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.093508 # mshr miss rate for demand accesses 1549system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.243943 # mshr miss rate for demand accesses 1550system.cpu0.l2cache.demand_mshr_miss_rate::total 0.153253 # mshr miss rate for demand accesses 1551system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.019556 # mshr miss rate for overall accesses 1552system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.039775 # mshr miss rate for overall accesses 1553system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.093508 # mshr miss rate for overall accesses 1554system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.243943 # mshr miss rate for overall accesses |
| 1577system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1555system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1578system.cpu0.l2cache.overall_mshr_miss_rate::total 0.232345 # mshr miss rate for overall accesses 1579system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 47059.326253 # average ReadReq mshr miss latency 1580system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 45780.002308 # average ReadReq mshr miss latency 1581system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 46524.206004 # average ReadReq mshr miss latency 1582system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 71210.429271 # average HardPFReq mshr miss latency 1583system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 71210.429271 # average HardPFReq mshr miss latency 1584system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29077.941831 # average UpgradeReq mshr miss latency 1585system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29077.941831 # average UpgradeReq mshr miss latency 1586system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19327.799487 # average SCUpgradeReq mshr miss latency 1587system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19327.799487 # average SCUpgradeReq mshr miss latency 1588system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 871500 # average SCUpgradeFailReq mshr miss latency 1589system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 871500 # average SCUpgradeFailReq mshr miss latency 1590system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 59061.823294 # average ReadExReq mshr miss latency 1591system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 59061.823294 # average ReadExReq mshr miss latency 1592system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33530.157161 # average ReadCleanReq mshr miss latency 1593system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33530.157161 # average ReadCleanReq mshr miss latency 1594system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 36936.760880 # average ReadSharedReq mshr miss latency 1595system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 36936.760880 # average ReadSharedReq mshr miss latency 1596system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70704.254236 # average InvalidateReq mshr miss latency 1597system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70704.254236 # average InvalidateReq mshr miss latency 1598system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 47059.326253 # average overall mshr miss latency 1599system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 45780.002308 # average overall mshr miss latency 1600system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33530.157161 # average overall mshr miss latency 1601system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 41701.755914 # average overall mshr miss latency 1602system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39318.158299 # average overall mshr miss latency 1603system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 47059.326253 # average overall mshr miss latency 1604system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 45780.002308 # average overall mshr miss latency 1605system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33530.157161 # average overall mshr miss latency 1606system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 41701.755914 # average overall mshr miss latency 1607system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 71210.429271 # average overall mshr miss latency 1608system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48867.682111 # average overall mshr miss latency 1609system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.189781 # average ReadReq mshr uncacheable latency 1610system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188040.393789 # average ReadReq mshr uncacheable latency 1611system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158189.370472 # average ReadReq mshr uncacheable latency 1612system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.189781 # average overall mshr uncacheable latency 1613system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 90440.398321 # average overall mshr uncacheable latency 1614system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104161.342648 # average overall mshr uncacheable latency 1615system.cpu0.toL2Bus.snoop_filter.tot_requests 23859843 # Total number of requests made to the snoop filter. 1616system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12280153 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1617system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1945 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1618system.cpu0.toL2Bus.snoop_filter.tot_snoops 2008292 # Total number of snoops made to the snoop filter. 1619system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2007802 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1620system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 490 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1621system.cpu0.toL2Bus.trans_dist::ReadReq 875651 # Transaction distribution 1622system.cpu0.toL2Bus.trans_dist::ReadResp 10557046 # Transaction distribution 1623system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 1624system.cpu0.toL2Bus.trans_dist::WriteReq 21267 # Transaction distribution 1625system.cpu0.toL2Bus.trans_dist::WriteResp 21266 # Transaction distribution 1626system.cpu0.toL2Bus.trans_dist::WritebackDirty 5532941 # Transaction distribution 1627system.cpu0.toL2Bus.trans_dist::WritebackClean 7629125 # Transaction distribution 1628system.cpu0.toL2Bus.trans_dist::CleanEvict 2654810 # Transaction distribution 1629system.cpu0.toL2Bus.trans_dist::HardPFReq 1033772 # Transaction distribution 1630system.cpu0.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution 1631system.cpu0.toL2Bus.trans_dist::UpgradeReq 476440 # Transaction distribution 1632system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348822 # Transaction distribution 1633system.cpu0.toL2Bus.trans_dist::UpgradeResp 520615 # Transaction distribution 1634system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution 1635system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution 1636system.cpu0.toL2Bus.trans_dist::ReadExReq 1237465 # Transaction distribution 1637system.cpu0.toL2Bus.trans_dist::ReadExResp 1213308 # Transaction distribution 1638system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5681636 # Transaction distribution 1639system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4942147 # Transaction distribution 1640system.cpu0.toL2Bus.trans_dist::InvalidateReq 844889 # Transaction distribution 1641system.cpu0.toL2Bus.trans_dist::InvalidateResp 786739 # Transaction distribution 1642system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17086897 # Packet count per connected master and slave (bytes) 1643system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18759020 # Packet count per connected master and slave (bytes) 1644system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 394013 # Packet count per connected master and slave (bytes) 1645system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1192566 # Packet count per connected master and slave (bytes) 1646system.cpu0.toL2Bus.pkt_count::total 37432496 # Packet count per connected master and slave (bytes) 1647system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 727551888 # Cumulative packet size per connected master and slave (bytes) 1648system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 705113777 # Cumulative packet size per connected master and slave (bytes) 1649system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1504832 # Cumulative packet size per connected master and slave (bytes) 1650system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4510600 # Cumulative packet size per connected master and slave (bytes) 1651system.cpu0.toL2Bus.pkt_size::total 1438681097 # Cumulative packet size per connected master and slave (bytes) 1652system.cpu0.toL2Bus.snoops 7112172 # Total snoops (count) 1653system.cpu0.toL2Bus.snoop_fanout::samples 19795414 # Request fanout histogram 1654system.cpu0.toL2Bus.snoop_fanout::mean 0.118782 # Request fanout histogram 1655system.cpu0.toL2Bus.snoop_fanout::stdev 0.323609 # Request fanout histogram | 1556system.cpu0.l2cache.overall_mshr_miss_rate::total 0.217839 # mshr miss rate for overall accesses 1557system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28305.478180 # average ReadReq mshr miss latency 1558system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26526.924087 # average ReadReq mshr miss latency 1559system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27568.864230 # average ReadReq mshr miss latency 1560system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46845.335420 # average HardPFReq mshr miss latency 1561system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46845.335420 # average HardPFReq mshr miss latency 1562system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20843.655320 # average UpgradeReq mshr miss latency 1563system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20843.655320 # average UpgradeReq mshr miss latency 1564system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16505.909731 # average SCUpgradeReq mshr miss latency 1565system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16505.909731 # average SCUpgradeReq mshr miss latency 1566system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 454785.571429 # average SCUpgradeFailReq mshr miss latency 1567system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 454785.571429 # average SCUpgradeFailReq mshr miss latency 1568system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40291.912662 # average ReadExReq mshr miss latency 1569system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40291.912662 # average ReadExReq mshr miss latency 1570system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28979.940194 # average ReadCleanReq mshr miss latency 1571system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28979.940194 # average ReadCleanReq mshr miss latency 1572system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28953.724719 # average ReadSharedReq mshr miss latency 1573system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28953.724719 # average ReadSharedReq mshr miss latency 1574system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36518.816670 # average InvalidateReq mshr miss latency 1575system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36518.816670 # average InvalidateReq mshr miss latency 1576system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28305.478180 # average overall mshr miss latency 1577system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26526.924087 # average overall mshr miss latency 1578system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28979.940194 # average overall mshr miss latency 1579system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31458.731460 # average overall mshr miss latency 1580system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30644.561078 # average overall mshr miss latency 1581system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28305.478180 # average overall mshr miss latency 1582system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26526.924087 # average overall mshr miss latency 1583system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28979.940194 # average overall mshr miss latency 1584system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31458.731460 # average overall mshr miss latency 1585system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46845.335420 # average overall mshr miss latency 1586system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35447.837007 # average overall mshr miss latency 1587system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average ReadReq mshr uncacheable latency 1588system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182858.994066 # average ReadReq mshr uncacheable latency 1589system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142583.305463 # average ReadReq mshr uncacheable latency 1590system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average overall mshr uncacheable latency 1591system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91677.525509 # average overall mshr uncacheable latency 1592system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89053.550498 # average overall mshr uncacheable latency 1593system.cpu0.toL2Bus.snoop_filter.tot_requests 24754475 # Total number of requests made to the snoop filter. 1594system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12719207 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1595system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2136 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1596system.cpu0.toL2Bus.snoop_filter.tot_snoops 1997962 # Total number of snoops made to the snoop filter. 1597system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1997498 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1598system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 464 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1599system.cpu0.toL2Bus.trans_dist::ReadReq 885324 # Transaction distribution 1600system.cpu0.toL2Bus.trans_dist::ReadResp 11040535 # Transaction distribution 1601system.cpu0.toL2Bus.trans_dist::WriteReq 32352 # Transaction distribution 1602system.cpu0.toL2Bus.trans_dist::WriteResp 32351 # Transaction distribution 1603system.cpu0.toL2Bus.trans_dist::WritebackDirty 5471965 # Transaction distribution 1604system.cpu0.toL2Bus.trans_dist::WritebackClean 8067317 # Transaction distribution 1605system.cpu0.toL2Bus.trans_dist::CleanEvict 2568559 # Transaction distribution 1606system.cpu0.toL2Bus.trans_dist::HardPFReq 991385 # Transaction distribution 1607system.cpu0.toL2Bus.trans_dist::HardPFResp 10 # Transaction distribution 1608system.cpu0.toL2Bus.trans_dist::UpgradeReq 475065 # Transaction distribution 1609system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 341372 # Transaction distribution 1610system.cpu0.toL2Bus.trans_dist::UpgradeResp 522361 # Transaction distribution 1611system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 76 # Transaction distribution 1612system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 140 # Transaction distribution 1613system.cpu0.toL2Bus.trans_dist::ReadExReq 1216718 # Transaction distribution 1614system.cpu0.toL2Bus.trans_dist::ReadExResp 1192935 # Transaction distribution 1615system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6137080 # Transaction distribution 1616system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4901216 # Transaction distribution 1617system.cpu0.toL2Bus.trans_dist::InvalidateReq 866556 # Transaction distribution 1618system.cpu0.toL2Bus.trans_dist::InvalidateResp 803970 # Transaction distribution 1619system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18453192 # Packet count per connected master and slave (bytes) 1620system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18807742 # Packet count per connected master and slave (bytes) 1621system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 402695 # Packet count per connected master and slave (bytes) 1622system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1170958 # Packet count per connected master and slave (bytes) 1623system.cpu0.toL2Bus.pkt_count::total 38834587 # Packet count per connected master and slave (bytes) 1624system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 785846352 # Cumulative packet size per connected master and slave (bytes) 1625system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 704525389 # Cumulative packet size per connected master and slave (bytes) 1626system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1531416 # Cumulative packet size per connected master and slave (bytes) 1627system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4405792 # Cumulative packet size per connected master and slave (bytes) 1628system.cpu0.toL2Bus.pkt_size::total 1496308949 # Cumulative packet size per connected master and slave (bytes) 1629system.cpu0.toL2Bus.snoops 6903738 # Total snoops (count) 1630system.cpu0.toL2Bus.snoop_fanout::samples 20024554 # Request fanout histogram 1631system.cpu0.toL2Bus.snoop_fanout::mean 0.116908 # Request fanout histogram 1632system.cpu0.toL2Bus.snoop_fanout::stdev 0.321383 # Request fanout histogram |
| 1656system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1633system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1657system.cpu0.toL2Bus.snoop_fanout::0 17444556 88.12% 88.12% # Request fanout histogram 1658system.cpu0.toL2Bus.snoop_fanout::1 2350368 11.87% 100.00% # Request fanout histogram 1659system.cpu0.toL2Bus.snoop_fanout::2 490 0.00% 100.00% # Request fanout histogram | 1634system.cpu0.toL2Bus.snoop_fanout::0 17683990 88.31% 88.31% # Request fanout histogram 1635system.cpu0.toL2Bus.snoop_fanout::1 2340100 11.69% 100.00% # Request fanout histogram 1636system.cpu0.toL2Bus.snoop_fanout::2 464 0.00% 100.00% # Request fanout histogram |
| 1660system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1661system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1662system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1637system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1638system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1639system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1663system.cpu0.toL2Bus.snoop_fanout::total 19795414 # Request fanout histogram 1664system.cpu0.toL2Bus.reqLayer0.occupancy 23702360441 # Layer occupancy (ticks) 1665system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1666system.cpu0.toL2Bus.snoopLayer0.occupancy 185100538 # Layer occupancy (ticks) | 1640system.cpu0.toL2Bus.snoop_fanout::total 20024554 # Request fanout histogram 1641system.cpu0.toL2Bus.reqLayer0.occupancy 24612511939 # Layer occupancy (ticks) 1642system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1643system.cpu0.toL2Bus.snoopLayer0.occupancy 212521499 # Layer occupancy (ticks) |
| 1667system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1644system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1668system.cpu0.toL2Bus.respLayer0.occupancy 8549815301 # Layer occupancy (ticks) | 1645system.cpu0.toL2Bus.respLayer0.occupancy 9233457820 # Layer occupancy (ticks) |
| 1669system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1646system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1670system.cpu0.toL2Bus.respLayer1.occupancy 8326796053 # Layer occupancy (ticks) | 1647system.cpu0.toL2Bus.respLayer1.occupancy 8324768239 # Layer occupancy (ticks) |
| 1671system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1648system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1672system.cpu0.toL2Bus.respLayer2.occupancy 206206896 # Layer occupancy (ticks) | 1649system.cpu0.toL2Bus.respLayer2.occupancy 211573883 # Layer occupancy (ticks) |
| 1673system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1650system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1674system.cpu0.toL2Bus.respLayer3.occupancy 629446573 # Layer occupancy (ticks) | 1651system.cpu0.toL2Bus.respLayer3.occupancy 620908635 # Layer occupancy (ticks) |
| 1675system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1652system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1676system.cpu1.branchPred.lookups 144214101 # Number of BP lookups 1677system.cpu1.branchPred.condPredicted 95658264 # Number of conditional branches predicted 1678system.cpu1.branchPred.condIncorrect 7037471 # Number of conditional branches incorrect 1679system.cpu1.branchPred.BTBLookups 101536339 # Number of BTB lookups 1680system.cpu1.branchPred.BTBHits 63283833 # Number of BTB hits | 1653system.cpu1.branchPred.lookups 127244460 # Number of BP lookups 1654system.cpu1.branchPred.condPredicted 83927531 # Number of conditional branches predicted 1655system.cpu1.branchPred.condIncorrect 6411720 # Number of conditional branches incorrect 1656system.cpu1.branchPred.BTBLookups 89791062 # Number of BTB lookups 1657system.cpu1.branchPred.BTBHits 55539581 # Number of BTB hits |
| 1681system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1658system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1682system.cpu1.branchPred.BTBHitPct 62.326290 # BTB Hit Percentage 1683system.cpu1.branchPred.usedRAS 19487906 # Number of times the RAS was used to get a target. 1684system.cpu1.branchPred.RASInCorrect 205159 # Number of incorrect RAS predictions. 1685system.cpu1.branchPred.indirectLookups 4571638 # Number of indirect predictor lookups. 1686system.cpu1.branchPred.indirectHits 2870819 # Number of indirect target hits. 1687system.cpu1.branchPred.indirectMisses 1700819 # Number of indirect misses. 1688system.cpu1.branchPredindirectMispredicted 415354 # Number of mispredicted indirect branches. | 1659system.cpu1.branchPred.BTBHitPct 61.854242 # BTB Hit Percentage 1660system.cpu1.branchPred.usedRAS 17406269 # Number of times the RAS was used to get a target. 1661system.cpu1.branchPred.RASInCorrect 177185 # Number of incorrect RAS predictions. 1662system.cpu1.branchPred.indirectLookups 4036084 # Number of indirect predictor lookups. 1663system.cpu1.branchPred.indirectHits 2495247 # Number of indirect target hits. 1664system.cpu1.branchPred.indirectMisses 1540837 # Number of indirect misses. 1665system.cpu1.branchPredindirectMispredicted 386993 # Number of mispredicted indirect branches. |
| 1689system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1690system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1691system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1692system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1693system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1694system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1695system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1696system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1710system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1711system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1712system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1713system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1714system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1715system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1716system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1717system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1666system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1667system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1668system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1669system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1670system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1671system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1672system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1673system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1687system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1688system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1689system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1690system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1691system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1692system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1693system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1694system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1718system.cpu1.dtb.walker.walks 655828 # Table walker walks requested 1719system.cpu1.dtb.walker.walksLong 655828 # Table walker walks initiated with long descriptors 1720system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 14723 # Level at which table walker walks with long descriptors terminate 1721system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 107099 # Level at which table walker walks with long descriptors terminate 1722system.cpu1.dtb.walker.walksSquashedBefore 315531 # Table walks squashed before starting 1723system.cpu1.dtb.walker.walkWaitTime::samples 340297 # Table walker wait (enqueue to first request) latency 1724system.cpu1.dtb.walker.walkWaitTime::mean 2456.990511 # Table walker wait (enqueue to first request) latency 1725system.cpu1.dtb.walker.walkWaitTime::stdev 14831.918999 # Table walker wait (enqueue to first request) latency 1726system.cpu1.dtb.walker.walkWaitTime::0-65535 337419 99.15% 99.15% # Table walker wait (enqueue to first request) latency 1727system.cpu1.dtb.walker.walkWaitTime::65536-131071 1530 0.45% 99.60% # Table walker wait (enqueue to first request) latency 1728system.cpu1.dtb.walker.walkWaitTime::131072-196607 1096 0.32% 99.93% # Table walker wait (enqueue to first request) latency 1729system.cpu1.dtb.walker.walkWaitTime::196608-262143 124 0.04% 99.96% # Table walker wait (enqueue to first request) latency 1730system.cpu1.dtb.walker.walkWaitTime::262144-327679 45 0.01% 99.98% # Table walker wait (enqueue to first request) latency 1731system.cpu1.dtb.walker.walkWaitTime::327680-393215 65 0.02% 99.99% # Table walker wait (enqueue to first request) latency 1732system.cpu1.dtb.walker.walkWaitTime::393216-458751 10 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1733system.cpu1.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1734system.cpu1.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1735system.cpu1.dtb.walker.walkWaitTime::786432-851967 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1736system.cpu1.dtb.walker.walkWaitTime::total 340297 # Table walker wait (enqueue to first request) latency 1737system.cpu1.dtb.walker.walkCompletionTime::samples 353965 # Table walker service (enqueue to completion) latency 1738system.cpu1.dtb.walker.walkCompletionTime::mean 21023.430283 # Table walker service (enqueue to completion) latency 1739system.cpu1.dtb.walker.walkCompletionTime::gmean 17819.927272 # Table walker service (enqueue to completion) latency 1740system.cpu1.dtb.walker.walkCompletionTime::stdev 22140.509228 # Table walker service (enqueue to completion) latency 1741system.cpu1.dtb.walker.walkCompletionTime::0-65535 349562 98.76% 98.76% # Table walker service (enqueue to completion) latency 1742system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1039 0.29% 99.05% # Table walker service (enqueue to completion) latency 1743system.cpu1.dtb.walker.walkCompletionTime::131072-196607 2363 0.67% 99.72% # Table walker service (enqueue to completion) latency 1744system.cpu1.dtb.walker.walkCompletionTime::196608-262143 142 0.04% 99.76% # Table walker service (enqueue to completion) latency 1745system.cpu1.dtb.walker.walkCompletionTime::262144-327679 520 0.15% 99.90% # Table walker service (enqueue to completion) latency 1746system.cpu1.dtb.walker.walkCompletionTime::327680-393215 154 0.04% 99.95% # Table walker service (enqueue to completion) latency 1747system.cpu1.dtb.walker.walkCompletionTime::393216-458751 109 0.03% 99.98% # Table walker service (enqueue to completion) latency 1748system.cpu1.dtb.walker.walkCompletionTime::458752-524287 57 0.02% 99.99% # Table walker service (enqueue to completion) latency 1749system.cpu1.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency 1750system.cpu1.dtb.walker.walkCompletionTime::589824-655359 8 0.00% 100.00% # Table walker service (enqueue to completion) latency 1751system.cpu1.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 1752system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1753system.cpu1.dtb.walker.walkCompletionTime::total 353965 # Table walker service (enqueue to completion) latency 1754system.cpu1.dtb.walker.walksPending::samples 524755655220 # Table walker pending requests distribution 1755system.cpu1.dtb.walker.walksPending::mean 0.627277 # Table walker pending requests distribution 1756system.cpu1.dtb.walker.walksPending::stdev 0.547876 # Table walker pending requests distribution 1757system.cpu1.dtb.walker.walksPending::0-1 523184603720 99.70% 99.70% # Table walker pending requests distribution 1758system.cpu1.dtb.walker.walksPending::2-3 876126000 0.17% 99.87% # Table walker pending requests distribution 1759system.cpu1.dtb.walker.walksPending::4-5 338256000 0.06% 99.93% # Table walker pending requests distribution 1760system.cpu1.dtb.walker.walksPending::6-7 142712500 0.03% 99.96% # Table walker pending requests distribution 1761system.cpu1.dtb.walker.walksPending::8-9 110713000 0.02% 99.98% # Table walker pending requests distribution 1762system.cpu1.dtb.walker.walksPending::10-11 57399000 0.01% 99.99% # Table walker pending requests distribution 1763system.cpu1.dtb.walker.walksPending::12-13 19068500 0.00% 99.99% # Table walker pending requests distribution 1764system.cpu1.dtb.walker.walksPending::14-15 26227000 0.00% 100.00% # Table walker pending requests distribution 1765system.cpu1.dtb.walker.walksPending::16-17 540000 0.00% 100.00% # Table walker pending requests distribution 1766system.cpu1.dtb.walker.walksPending::18-19 6500 0.00% 100.00% # Table walker pending requests distribution 1767system.cpu1.dtb.walker.walksPending::20-21 1500 0.00% 100.00% # Table walker pending requests distribution 1768system.cpu1.dtb.walker.walksPending::22-23 1500 0.00% 100.00% # Table walker pending requests distribution 1769system.cpu1.dtb.walker.walksPending::total 524755655220 # Table walker pending requests distribution 1770system.cpu1.dtb.walker.walkPageSizes::4K 107100 87.91% 87.91% # Table walker page sizes translated 1771system.cpu1.dtb.walker.walkPageSizes::2M 14723 12.09% 100.00% # Table walker page sizes translated 1772system.cpu1.dtb.walker.walkPageSizes::total 121823 # Table walker page sizes translated 1773system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 655828 # Table walker requests started/completed, data/inst | 1695system.cpu1.dtb.walker.walks 579824 # Table walker walks requested 1696system.cpu1.dtb.walker.walksLong 579824 # Table walker walks initiated with long descriptors 1697system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12232 # Level at which table walker walks with long descriptors terminate 1698system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93540 # Level at which table walker walks with long descriptors terminate 1699system.cpu1.dtb.walker.walksSquashedBefore 278610 # Table walks squashed before starting 1700system.cpu1.dtb.walker.walkWaitTime::samples 301214 # Table walker wait (enqueue to first request) latency 1701system.cpu1.dtb.walker.walkWaitTime::mean 2385.289196 # Table walker wait (enqueue to first request) latency 1702system.cpu1.dtb.walker.walkWaitTime::stdev 13264.000730 # Table walker wait (enqueue to first request) latency 1703system.cpu1.dtb.walker.walkWaitTime::0-65535 298702 99.17% 99.17% # Table walker wait (enqueue to first request) latency 1704system.cpu1.dtb.walker.walkWaitTime::65536-131071 1877 0.62% 99.79% # Table walker wait (enqueue to first request) latency 1705system.cpu1.dtb.walker.walkWaitTime::131072-196607 425 0.14% 99.93% # Table walker wait (enqueue to first request) latency 1706system.cpu1.dtb.walker.walkWaitTime::196608-262143 126 0.04% 99.97% # Table walker wait (enqueue to first request) latency 1707system.cpu1.dtb.walker.walkWaitTime::262144-327679 47 0.02% 99.99% # Table walker wait (enqueue to first request) latency 1708system.cpu1.dtb.walker.walkWaitTime::327680-393215 33 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1709system.cpu1.dtb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1710system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1711system.cpu1.dtb.walker.walkWaitTime::total 301214 # Table walker wait (enqueue to first request) latency 1712system.cpu1.dtb.walker.walkCompletionTime::samples 311038 # Table walker service (enqueue to completion) latency 1713system.cpu1.dtb.walker.walkCompletionTime::mean 20491.173104 # Table walker service (enqueue to completion) latency 1714system.cpu1.dtb.walker.walkCompletionTime::gmean 17661.433181 # Table walker service (enqueue to completion) latency 1715system.cpu1.dtb.walker.walkCompletionTime::stdev 17134.136599 # Table walker service (enqueue to completion) latency 1716system.cpu1.dtb.walker.walkCompletionTime::0-65535 306887 98.67% 98.67% # Table walker service (enqueue to completion) latency 1717system.cpu1.dtb.walker.walkCompletionTime::65536-131071 3006 0.97% 99.63% # Table walker service (enqueue to completion) latency 1718system.cpu1.dtb.walker.walkCompletionTime::131072-196607 404 0.13% 99.76% # Table walker service (enqueue to completion) latency 1719system.cpu1.dtb.walker.walkCompletionTime::196608-262143 531 0.17% 99.93% # Table walker service (enqueue to completion) latency 1720system.cpu1.dtb.walker.walkCompletionTime::262144-327679 109 0.04% 99.97% # Table walker service (enqueue to completion) latency 1721system.cpu1.dtb.walker.walkCompletionTime::327680-393215 60 0.02% 99.99% # Table walker service (enqueue to completion) latency 1722system.cpu1.dtb.walker.walkCompletionTime::393216-458751 29 0.01% 100.00% # Table walker service (enqueue to completion) latency 1723system.cpu1.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency 1724system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 1725system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1726system.cpu1.dtb.walker.walkCompletionTime::total 311038 # Table walker service (enqueue to completion) latency 1727system.cpu1.dtb.walker.walksPending::samples 427436234332 # Table walker pending requests distribution 1728system.cpu1.dtb.walker.walksPending::mean 0.596252 # Table walker pending requests distribution 1729system.cpu1.dtb.walker.walksPending::stdev 0.559035 # Table walker pending requests distribution 1730system.cpu1.dtb.walker.walksPending::0-1 426093627832 99.69% 99.69% # Table walker pending requests distribution 1731system.cpu1.dtb.walker.walksPending::2-3 733360500 0.17% 99.86% # Table walker pending requests distribution 1732system.cpu1.dtb.walker.walksPending::4-5 289523500 0.07% 99.93% # Table walker pending requests distribution 1733system.cpu1.dtb.walker.walksPending::6-7 124054000 0.03% 99.95% # Table walker pending requests distribution 1734system.cpu1.dtb.walker.walksPending::8-9 101131500 0.02% 99.98% # Table walker pending requests distribution 1735system.cpu1.dtb.walker.walksPending::10-11 55199000 0.01% 99.99% # Table walker pending requests distribution 1736system.cpu1.dtb.walker.walksPending::12-13 17877500 0.00% 99.99% # Table walker pending requests distribution 1737system.cpu1.dtb.walker.walksPending::14-15 20812500 0.00% 100.00% # Table walker pending requests distribution 1738system.cpu1.dtb.walker.walksPending::16-17 638500 0.00% 100.00% # Table walker pending requests distribution 1739system.cpu1.dtb.walker.walksPending::18-19 9500 0.00% 100.00% # Table walker pending requests distribution 1740system.cpu1.dtb.walker.walksPending::total 427436234332 # Table walker pending requests distribution 1741system.cpu1.dtb.walker.walkPageSizes::4K 93540 88.44% 88.44% # Table walker page sizes translated 1742system.cpu1.dtb.walker.walkPageSizes::2M 12232 11.56% 100.00% # Table walker page sizes translated 1743system.cpu1.dtb.walker.walkPageSizes::total 105772 # Table walker page sizes translated 1744system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 579824 # Table walker requests started/completed, data/inst |
| 1774system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 1745system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 1775system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 655828 # Table walker requests started/completed, data/inst 1776system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 121823 # Table walker requests started/completed, data/inst | 1746system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 579824 # Table walker requests started/completed, data/inst 1747system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105772 # Table walker requests started/completed, data/inst |
| 1777system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 1748system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 1778system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 121823 # Table walker requests started/completed, data/inst 1779system.cpu1.dtb.walker.walkRequestOrigin::total 777651 # Table walker requests started/completed, data/inst | 1749system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105772 # Table walker requests started/completed, data/inst 1750system.cpu1.dtb.walker.walkRequestOrigin::total 685596 # Table walker requests started/completed, data/inst |
| 1780system.cpu1.dtb.inst_hits 0 # ITB inst hits 1781system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1751system.cpu1.dtb.inst_hits 0 # ITB inst hits 1752system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1782system.cpu1.dtb.read_hits 106468062 # DTB read hits 1783system.cpu1.dtb.read_misses 473211 # DTB read misses 1784system.cpu1.dtb.write_hits 85858726 # DTB write hits 1785system.cpu1.dtb.write_misses 182617 # DTB write misses 1786system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed | 1753system.cpu1.dtb.read_hits 94100008 # DTB read hits 1754system.cpu1.dtb.read_misses 416726 # DTB read misses 1755system.cpu1.dtb.write_hits 75732153 # DTB write hits 1756system.cpu1.dtb.write_misses 163098 # DTB write misses 1757system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed |
| 1787system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 1758system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 1788system.cpu1.dtb.flush_tlb_mva_asid 46091 # Number of times TLB was flushed by MVA & ASID 1789system.cpu1.dtb.flush_tlb_asid 1084 # Number of times TLB was flushed by ASID 1790system.cpu1.dtb.flush_entries 44338 # Number of entries that have been flushed from TLB 1791system.cpu1.dtb.align_faults 492 # Number of TLB faults due to alignment restrictions 1792system.cpu1.dtb.prefetch_faults 7273 # Number of TLB faults due to prefetch | 1759system.cpu1.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID 1760system.cpu1.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID 1761system.cpu1.dtb.flush_entries 40949 # Number of entries that have been flushed from TLB 1762system.cpu1.dtb.align_faults 397 # Number of TLB faults due to alignment restrictions 1763system.cpu1.dtb.prefetch_faults 6052 # Number of TLB faults due to prefetch |
| 1793system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1764system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1794system.cpu1.dtb.perms_faults 40937 # Number of TLB faults due to permissions restrictions 1795system.cpu1.dtb.read_accesses 106941273 # DTB read accesses 1796system.cpu1.dtb.write_accesses 86041343 # DTB write accesses | 1765system.cpu1.dtb.perms_faults 38110 # Number of TLB faults due to permissions restrictions 1766system.cpu1.dtb.read_accesses 94516734 # DTB read accesses 1767system.cpu1.dtb.write_accesses 75895251 # DTB write accesses |
| 1797system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1768system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1798system.cpu1.dtb.hits 192326788 # DTB hits 1799system.cpu1.dtb.misses 655828 # DTB misses 1800system.cpu1.dtb.accesses 192982616 # DTB accesses | 1769system.cpu1.dtb.hits 169832161 # DTB hits 1770system.cpu1.dtb.misses 579824 # DTB misses 1771system.cpu1.dtb.accesses 170411985 # DTB accesses |
| 1801system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1802system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1803system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1804system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1805system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1806system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1807system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1808system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1822system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1823system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1824system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1825system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1826system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1827system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1828system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1829system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1772system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1773system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1774system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1775system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1776system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1777system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1778system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1779system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1793system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1794system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1795system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1796system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1797system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1798system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1799system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1800system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1830system.cpu1.itb.walker.walks 90500 # Table walker walks requested 1831system.cpu1.itb.walker.walksLong 90500 # Table walker walks initiated with long descriptors 1832system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1174 # Level at which table walker walks with long descriptors terminate 1833system.cpu1.itb.walker.walksLongTerminationLevel::Level3 63013 # Level at which table walker walks with long descriptors terminate 1834system.cpu1.itb.walker.walksSquashedBefore 10919 # Table walks squashed before starting 1835system.cpu1.itb.walker.walkWaitTime::samples 79581 # Table walker wait (enqueue to first request) latency 1836system.cpu1.itb.walker.walkWaitTime::mean 1858.653447 # Table walker wait (enqueue to first request) latency 1837system.cpu1.itb.walker.walkWaitTime::stdev 14270.720139 # Table walker wait (enqueue to first request) latency 1838system.cpu1.itb.walker.walkWaitTime::0-65535 78947 99.20% 99.20% # Table walker wait (enqueue to first request) latency 1839system.cpu1.itb.walker.walkWaitTime::65536-131071 217 0.27% 99.48% # Table walker wait (enqueue to first request) latency 1840system.cpu1.itb.walker.walkWaitTime::131072-196607 367 0.46% 99.94% # Table walker wait (enqueue to first request) latency 1841system.cpu1.itb.walker.walkWaitTime::196608-262143 26 0.03% 99.97% # Table walker wait (enqueue to first request) latency 1842system.cpu1.itb.walker.walkWaitTime::262144-327679 15 0.02% 99.99% # Table walker wait (enqueue to first request) latency 1843system.cpu1.itb.walker.walkWaitTime::327680-393215 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1844system.cpu1.itb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1845system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1846system.cpu1.itb.walker.walkWaitTime::total 79581 # Table walker wait (enqueue to first request) latency 1847system.cpu1.itb.walker.walkCompletionTime::samples 75106 # Table walker service (enqueue to completion) latency 1848system.cpu1.itb.walker.walkCompletionTime::mean 27703.186164 # Table walker service (enqueue to completion) latency 1849system.cpu1.itb.walker.walkCompletionTime::gmean 23129.879308 # Table walker service (enqueue to completion) latency 1850system.cpu1.itb.walker.walkCompletionTime::stdev 30256.665627 # Table walker service (enqueue to completion) latency 1851system.cpu1.itb.walker.walkCompletionTime::0-65535 72610 96.68% 96.68% # Table walker service (enqueue to completion) latency 1852system.cpu1.itb.walker.walkCompletionTime::65536-131071 191 0.25% 96.93% # Table walker service (enqueue to completion) latency 1853system.cpu1.itb.walker.walkCompletionTime::131072-196607 1968 2.62% 99.55% # Table walker service (enqueue to completion) latency 1854system.cpu1.itb.walker.walkCompletionTime::196608-262143 115 0.15% 99.70% # Table walker service (enqueue to completion) latency 1855system.cpu1.itb.walker.walkCompletionTime::262144-327679 133 0.18% 99.88% # Table walker service (enqueue to completion) latency 1856system.cpu1.itb.walker.walkCompletionTime::327680-393215 46 0.06% 99.94% # Table walker service (enqueue to completion) latency 1857system.cpu1.itb.walker.walkCompletionTime::393216-458751 21 0.03% 99.97% # Table walker service (enqueue to completion) latency 1858system.cpu1.itb.walker.walkCompletionTime::458752-524287 16 0.02% 99.99% # Table walker service (enqueue to completion) latency 1859system.cpu1.itb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 1860system.cpu1.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1861system.cpu1.itb.walker.walkCompletionTime::total 75106 # Table walker service (enqueue to completion) latency 1862system.cpu1.itb.walker.walksPending::samples 438856254800 # Table walker pending requests distribution 1863system.cpu1.itb.walker.walksPending::mean 0.887236 # Table walker pending requests distribution 1864system.cpu1.itb.walker.walksPending::stdev 0.316700 # Table walker pending requests distribution 1865system.cpu1.itb.walker.walksPending::0 49536953716 11.29% 11.29% # Table walker pending requests distribution 1866system.cpu1.itb.walker.walksPending::1 389273644084 88.70% 99.99% # Table walker pending requests distribution 1867system.cpu1.itb.walker.walksPending::2 42101500 0.01% 100.00% # Table walker pending requests distribution 1868system.cpu1.itb.walker.walksPending::3 2811500 0.00% 100.00% # Table walker pending requests distribution 1869system.cpu1.itb.walker.walksPending::4 744000 0.00% 100.00% # Table walker pending requests distribution 1870system.cpu1.itb.walker.walksPending::total 438856254800 # Table walker pending requests distribution 1871system.cpu1.itb.walker.walkPageSizes::4K 63013 98.17% 98.17% # Table walker page sizes translated 1872system.cpu1.itb.walker.walkPageSizes::2M 1174 1.83% 100.00% # Table walker page sizes translated 1873system.cpu1.itb.walker.walkPageSizes::total 64187 # Table walker page sizes translated | 1801system.cpu1.itb.walker.walks 86146 # Table walker walks requested 1802system.cpu1.itb.walker.walksLong 86146 # Table walker walks initiated with long descriptors 1803system.cpu1.itb.walker.walksLongTerminationLevel::Level2 983 # Level at which table walker walks with long descriptors terminate 1804system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61109 # Level at which table walker walks with long descriptors terminate 1805system.cpu1.itb.walker.walksSquashedBefore 10267 # Table walks squashed before starting 1806system.cpu1.itb.walker.walkWaitTime::samples 75879 # Table walker wait (enqueue to first request) latency 1807system.cpu1.itb.walker.walkWaitTime::mean 1365.727013 # Table walker wait (enqueue to first request) latency 1808system.cpu1.itb.walker.walkWaitTime::stdev 9905.301438 # Table walker wait (enqueue to first request) latency 1809system.cpu1.itb.walker.walkWaitTime::0-32767 74992 98.83% 98.83% # Table walker wait (enqueue to first request) latency 1810system.cpu1.itb.walker.walkWaitTime::32768-65535 442 0.58% 99.41% # Table walker wait (enqueue to first request) latency 1811system.cpu1.itb.walker.walkWaitTime::65536-98303 265 0.35% 99.76% # Table walker wait (enqueue to first request) latency 1812system.cpu1.itb.walker.walkWaitTime::98304-131071 132 0.17% 99.94% # Table walker wait (enqueue to first request) latency 1813system.cpu1.itb.walker.walkWaitTime::131072-163839 11 0.01% 99.95% # Table walker wait (enqueue to first request) latency 1814system.cpu1.itb.walker.walkWaitTime::163840-196607 13 0.02% 99.97% # Table walker wait (enqueue to first request) latency 1815system.cpu1.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency 1816system.cpu1.itb.walker.walkWaitTime::229376-262143 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1817system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency 1818system.cpu1.itb.walker.walkWaitTime::294912-327679 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1819system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 1820system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1821system.cpu1.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1822system.cpu1.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1823system.cpu1.itb.walker.walkWaitTime::total 75879 # Table walker wait (enqueue to first request) latency 1824system.cpu1.itb.walker.walkCompletionTime::samples 72359 # Table walker service (enqueue to completion) latency 1825system.cpu1.itb.walker.walkCompletionTime::mean 25927.458920 # Table walker service (enqueue to completion) latency 1826system.cpu1.itb.walker.walkCompletionTime::gmean 22905.536509 # Table walker service (enqueue to completion) latency 1827system.cpu1.itb.walker.walkCompletionTime::stdev 21012.178040 # Table walker service (enqueue to completion) latency 1828system.cpu1.itb.walker.walkCompletionTime::0-65535 70191 97.00% 97.00% # Table walker service (enqueue to completion) latency 1829system.cpu1.itb.walker.walkCompletionTime::65536-131071 1833 2.53% 99.54% # Table walker service (enqueue to completion) latency 1830system.cpu1.itb.walker.walkCompletionTime::131072-196607 132 0.18% 99.72% # Table walker service (enqueue to completion) latency 1831system.cpu1.itb.walker.walkCompletionTime::196608-262143 128 0.18% 99.90% # Table walker service (enqueue to completion) latency 1832system.cpu1.itb.walker.walkCompletionTime::262144-327679 41 0.06% 99.95% # Table walker service (enqueue to completion) latency 1833system.cpu1.itb.walker.walkCompletionTime::327680-393215 21 0.03% 99.98% # Table walker service (enqueue to completion) latency 1834system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 1835system.cpu1.itb.walker.walkCompletionTime::458752-524287 7 0.01% 100.00% # Table walker service (enqueue to completion) latency 1836system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1837system.cpu1.itb.walker.walkCompletionTime::total 72359 # Table walker service (enqueue to completion) latency 1838system.cpu1.itb.walker.walksPending::samples 388687033168 # Table walker pending requests distribution 1839system.cpu1.itb.walker.walksPending::mean 0.860499 # Table walker pending requests distribution 1840system.cpu1.itb.walker.walksPending::stdev 0.346749 # Table walker pending requests distribution 1841system.cpu1.itb.walker.walksPending::0 54258161808 13.96% 13.96% # Table walker pending requests distribution 1842system.cpu1.itb.walker.walksPending::1 334394621860 86.03% 99.99% # Table walker pending requests distribution 1843system.cpu1.itb.walker.walksPending::2 32560000 0.01% 100.00% # Table walker pending requests distribution 1844system.cpu1.itb.walker.walksPending::3 1626500 0.00% 100.00% # Table walker pending requests distribution 1845system.cpu1.itb.walker.walksPending::4 63000 0.00% 100.00% # Table walker pending requests distribution 1846system.cpu1.itb.walker.walksPending::total 388687033168 # Table walker pending requests distribution 1847system.cpu1.itb.walker.walkPageSizes::4K 61109 98.42% 98.42% # Table walker page sizes translated 1848system.cpu1.itb.walker.walkPageSizes::2M 983 1.58% 100.00% # Table walker page sizes translated 1849system.cpu1.itb.walker.walkPageSizes::total 62092 # Table walker page sizes translated |
| 1874system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 1850system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 1875system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 90500 # Table walker requests started/completed, data/inst 1876system.cpu1.itb.walker.walkRequestOrigin_Requested::total 90500 # Table walker requests started/completed, data/inst | 1851system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 86146 # Table walker requests started/completed, data/inst 1852system.cpu1.itb.walker.walkRequestOrigin_Requested::total 86146 # Table walker requests started/completed, data/inst |
| 1877system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 1853system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 1878system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 64187 # Table walker requests started/completed, data/inst 1879system.cpu1.itb.walker.walkRequestOrigin_Completed::total 64187 # Table walker requests started/completed, data/inst 1880system.cpu1.itb.walker.walkRequestOrigin::total 154687 # Table walker requests started/completed, data/inst 1881system.cpu1.itb.inst_hits 226870355 # ITB inst hits 1882system.cpu1.itb.inst_misses 90500 # ITB inst misses | 1854system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62092 # Table walker requests started/completed, data/inst 1855system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62092 # Table walker requests started/completed, data/inst 1856system.cpu1.itb.walker.walkRequestOrigin::total 148238 # Table walker requests started/completed, data/inst 1857system.cpu1.itb.inst_hits 200179962 # ITB inst hits 1858system.cpu1.itb.inst_misses 86146 # ITB inst misses |
| 1883system.cpu1.itb.read_hits 0 # DTB read hits 1884system.cpu1.itb.read_misses 0 # DTB read misses 1885system.cpu1.itb.write_hits 0 # DTB write hits 1886system.cpu1.itb.write_misses 0 # DTB write misses | 1859system.cpu1.itb.read_hits 0 # DTB read hits 1860system.cpu1.itb.read_misses 0 # DTB read misses 1861system.cpu1.itb.write_hits 0 # DTB write hits 1862system.cpu1.itb.write_misses 0 # DTB write misses |
| 1887system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed | 1863system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed |
| 1888system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 1864system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 1889system.cpu1.itb.flush_tlb_mva_asid 46091 # Number of times TLB was flushed by MVA & ASID 1890system.cpu1.itb.flush_tlb_asid 1084 # Number of times TLB was flushed by ASID 1891system.cpu1.itb.flush_entries 32400 # Number of entries that have been flushed from TLB | 1865system.cpu1.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID 1866system.cpu1.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID 1867system.cpu1.itb.flush_entries 29991 # Number of entries that have been flushed from TLB |
| 1892system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1893system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1894system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1868system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1869system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1870system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1895system.cpu1.itb.perms_faults 223247 # Number of TLB faults due to permissions restrictions | 1871system.cpu1.itb.perms_faults 205105 # Number of TLB faults due to permissions restrictions |
| 1896system.cpu1.itb.read_accesses 0 # DTB read accesses 1897system.cpu1.itb.write_accesses 0 # DTB write accesses | 1872system.cpu1.itb.read_accesses 0 # DTB read accesses 1873system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1898system.cpu1.itb.inst_accesses 226960855 # ITB inst accesses 1899system.cpu1.itb.hits 226870355 # DTB hits 1900system.cpu1.itb.misses 90500 # DTB misses 1901system.cpu1.itb.accesses 226960855 # DTB accesses 1902system.cpu1.numCycles 812532558 # number of cpu cycles simulated | 1874system.cpu1.itb.inst_accesses 200266108 # ITB inst accesses 1875system.cpu1.itb.hits 200179962 # DTB hits 1876system.cpu1.itb.misses 86146 # DTB misses 1877system.cpu1.itb.accesses 200266108 # DTB accesses 1878system.cpu1.numCycles 683375860 # number of cpu cycles simulated |
| 1903system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1904system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1879system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1880system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1905system.cpu1.fetch.icacheStallCycles 91759705 # Number of cycles fetch is stalled on an Icache miss 1906system.cpu1.fetch.Insts 638580491 # Number of instructions fetch has processed 1907system.cpu1.fetch.Branches 144214101 # Number of branches that fetch encountered 1908system.cpu1.fetch.predictedBranches 85642558 # Number of branches that fetch has predicted taken 1909system.cpu1.fetch.Cycles 676433492 # Number of cycles fetch has run and was not squashing or blocked 1910system.cpu1.fetch.SquashCycles 15215298 # Number of cycles fetch has spent squashing 1911system.cpu1.fetch.TlbCycles 2168545 # Number of cycles fetch has spent waiting for tlb 1912system.cpu1.fetch.MiscStallCycles 336979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1913system.cpu1.fetch.PendingTrapStallCycles 6484962 # Number of stall cycles due to pending traps 1914system.cpu1.fetch.PendingQuiesceStallCycles 887415 # Number of stall cycles due to pending quiesce instructions 1915system.cpu1.fetch.IcacheWaitRetryStallCycles 890942 # Number of stall cycles due to full MSHR 1916system.cpu1.fetch.CacheLines 226625049 # Number of cache lines fetched 1917system.cpu1.fetch.IcacheSquashes 1736948 # Number of outstanding Icache misses that were squashed 1918system.cpu1.fetch.ItlbSquashes 29701 # Number of outstanding ITLB misses that were squashed 1919system.cpu1.fetch.rateDist::samples 786569689 # Number of instructions fetched each cycle (Total) 1920system.cpu1.fetch.rateDist::mean 0.951781 # Number of instructions fetched each cycle (Total) 1921system.cpu1.fetch.rateDist::stdev 1.213726 # Number of instructions fetched each cycle (Total) | 1881system.cpu1.fetch.icacheStallCycles 83886783 # Number of cycles fetch is stalled on an Icache miss 1882system.cpu1.fetch.Insts 563469851 # Number of instructions fetch has processed 1883system.cpu1.fetch.Branches 127244460 # Number of branches that fetch encountered 1884system.cpu1.fetch.predictedBranches 75441097 # Number of branches that fetch has predicted taken 1885system.cpu1.fetch.Cycles 564344995 # Number of cycles fetch has run and was not squashing or blocked 1886system.cpu1.fetch.SquashCycles 13807906 # Number of cycles fetch has spent squashing 1887system.cpu1.fetch.TlbCycles 2007349 # Number of cycles fetch has spent waiting for tlb 1888system.cpu1.fetch.MiscStallCycles 258832 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1889system.cpu1.fetch.PendingTrapStallCycles 5872913 # Number of stall cycles due to pending traps 1890system.cpu1.fetch.PendingQuiesceStallCycles 777107 # Number of stall cycles due to pending quiesce instructions 1891system.cpu1.fetch.IcacheWaitRetryStallCycles 768148 # Number of stall cycles due to full MSHR 1892system.cpu1.fetch.CacheLines 199953853 # Number of cache lines fetched 1893system.cpu1.fetch.IcacheSquashes 1622392 # Number of outstanding Icache misses that were squashed 1894system.cpu1.fetch.ItlbSquashes 27919 # Number of outstanding ITLB misses that were squashed 1895system.cpu1.fetch.rateDist::samples 664820080 # Number of instructions fetched each cycle (Total) 1896system.cpu1.fetch.rateDist::mean 0.994147 # Number of instructions fetched each cycle (Total) 1897system.cpu1.fetch.rateDist::stdev 1.223667 # Number of instructions fetched each cycle (Total) |
| 1922system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1898system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1923system.cpu1.fetch.rateDist::0 428022323 54.42% 54.42% # Number of instructions fetched each cycle (Total) 1924system.cpu1.fetch.rateDist::1 139668800 17.76% 72.17% # Number of instructions fetched each cycle (Total) 1925system.cpu1.fetch.rateDist::2 47662444 6.06% 78.23% # Number of instructions fetched each cycle (Total) 1926system.cpu1.fetch.rateDist::3 171216122 21.77% 100.00% # Number of instructions fetched each cycle (Total) | 1899system.cpu1.fetch.rateDist::0 348468390 52.42% 52.42% # Number of instructions fetched each cycle (Total) 1900system.cpu1.fetch.rateDist::1 123001690 18.50% 70.92% # Number of instructions fetched each cycle (Total) 1901system.cpu1.fetch.rateDist::2 42123132 6.34% 77.25% # Number of instructions fetched each cycle (Total) 1902system.cpu1.fetch.rateDist::3 151226868 22.75% 100.00% # Number of instructions fetched each cycle (Total) |
| 1927system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1928system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1929system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 1903system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1904system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1905system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 1930system.cpu1.fetch.rateDist::total 786569689 # Number of instructions fetched each cycle (Total) 1931system.cpu1.fetch.branchRate 0.177487 # Number of branch fetches per cycle 1932system.cpu1.fetch.rate 0.785914 # Number of inst fetches per cycle 1933system.cpu1.decode.IdleCycles 110960591 # Number of cycles decode is idle 1934system.cpu1.decode.BlockedCycles 393393476 # Number of cycles decode is blocked 1935system.cpu1.decode.RunCycles 236254465 # Number of cycles decode is running 1936system.cpu1.decode.UnblockCycles 40475350 # Number of cycles decode is unblocking 1937system.cpu1.decode.SquashCycles 5485807 # Number of cycles decode is squashing 1938system.cpu1.decode.BranchResolved 20188292 # Number of times decode resolved a branch 1939system.cpu1.decode.BranchMispred 2163849 # Number of times decode detected a branch misprediction 1940system.cpu1.decode.DecodedInsts 661116472 # Number of instructions handled by decode 1941system.cpu1.decode.SquashedInsts 24295467 # Number of squashed instructions handled by decode 1942system.cpu1.rename.SquashCycles 5485807 # Number of cycles rename is squashing 1943system.cpu1.rename.IdleCycles 148680347 # Number of cycles rename is idle 1944system.cpu1.rename.BlockCycles 59294510 # Number of cycles rename is blocking 1945system.cpu1.rename.serializeStallCycles 260447701 # count of cycles rename stalled for serializing inst 1946system.cpu1.rename.RunCycles 238523513 # Number of cycles rename is running 1947system.cpu1.rename.UnblockCycles 74137811 # Number of cycles rename is unblocking 1948system.cpu1.rename.RenamedInsts 642734014 # Number of instructions processed by rename 1949system.cpu1.rename.SquashedInsts 6463851 # Number of squashed instructions processed by rename 1950system.cpu1.rename.ROBFullEvents 12050420 # Number of times rename has blocked due to ROB full 1951system.cpu1.rename.IQFullEvents 431614 # Number of times rename has blocked due to IQ full 1952system.cpu1.rename.LQFullEvents 1024133 # Number of times rename has blocked due to LQ full 1953system.cpu1.rename.SQFullEvents 35807802 # Number of times rename has blocked due to SQ full 1954system.cpu1.rename.FullRegisterEvents 12087 # Number of times there has been no free registers 1955system.cpu1.rename.RenamedOperands 613144176 # Number of destination operands rename has renamed 1956system.cpu1.rename.RenameLookups 993338486 # Number of register rename lookups that rename has made 1957system.cpu1.rename.int_rename_lookups 758389620 # Number of integer rename lookups 1958system.cpu1.rename.fp_rename_lookups 787806 # Number of floating rename lookups 1959system.cpu1.rename.CommittedMaps 551826661 # Number of HB maps that are committed 1960system.cpu1.rename.UndoneMaps 61317509 # Number of HB maps that are undone due to squashing 1961system.cpu1.rename.serializingInsts 17340731 # count of serializing insts renamed 1962system.cpu1.rename.tempSerializingInsts 15198476 # count of temporary serializing insts renamed 1963system.cpu1.rename.skidInsts 81471302 # count of insts added to the skid buffer 1964system.cpu1.memDep0.insertedLoads 106673767 # Number of loads inserted to the mem dependence unit. 1965system.cpu1.memDep0.insertedStores 89326102 # Number of stores inserted to the mem dependence unit. 1966system.cpu1.memDep0.conflictingLoads 10094322 # Number of conflicting loads. 1967system.cpu1.memDep0.conflictingStores 8631476 # Number of conflicting stores. 1968system.cpu1.iq.iqInstsAdded 618122262 # Number of instructions added to the IQ (excludes non-spec) 1969system.cpu1.iq.iqNonSpecInstsAdded 17529509 # Number of non-speculative instructions added to the IQ 1970system.cpu1.iq.iqInstsIssued 623787865 # Number of instructions issued 1971system.cpu1.iq.iqSquashedInstsIssued 2873824 # Number of squashed instructions issued 1972system.cpu1.iq.iqSquashedInstsExamined 57783921 # Number of squashed instructions iterated over during squash; mainly for profiling 1973system.cpu1.iq.iqSquashedOperandsExamined 37389903 # Number of squashed operands that are examined and possibly removed from graph 1974system.cpu1.iq.iqSquashedNonSpecRemoved 307135 # Number of squashed non-spec instructions that were removed 1975system.cpu1.iq.issued_per_cycle::samples 786569689 # Number of insts issued each cycle 1976system.cpu1.iq.issued_per_cycle::mean 0.793048 # Number of insts issued each cycle 1977system.cpu1.iq.issued_per_cycle::stdev 1.056857 # Number of insts issued each cycle | 1906system.cpu1.fetch.rateDist::total 664820080 # Number of instructions fetched each cycle (Total) 1907system.cpu1.fetch.branchRate 0.186200 # Number of branch fetches per cycle 1908system.cpu1.fetch.rate 0.824539 # Number of inst fetches per cycle 1909system.cpu1.decode.IdleCycles 100313259 # Number of cycles decode is idle 1910system.cpu1.decode.BlockedCycles 315334519 # Number of cycles decode is blocked 1911system.cpu1.decode.RunCycles 208757120 # Number of cycles decode is running 1912system.cpu1.decode.UnblockCycles 35486026 # Number of cycles decode is unblocking 1913system.cpu1.decode.SquashCycles 4929156 # Number of cycles decode is squashing 1914system.cpu1.decode.BranchResolved 17976704 # Number of times decode resolved a branch 1915system.cpu1.decode.BranchMispred 2012194 # Number of times decode detected a branch misprediction 1916system.cpu1.decode.DecodedInsts 582722672 # Number of instructions handled by decode 1917system.cpu1.decode.SquashedInsts 22029645 # Number of squashed instructions handled by decode 1918system.cpu1.rename.SquashCycles 4929156 # Number of cycles rename is squashing 1919system.cpu1.rename.IdleCycles 133756265 # Number of cycles rename is idle 1920system.cpu1.rename.BlockCycles 43242401 # Number of cycles rename is blocking 1921system.cpu1.rename.serializeStallCycles 214462360 # count of cycles rename stalled for serializing inst 1922system.cpu1.rename.RunCycles 210347945 # Number of cycles rename is running 1923system.cpu1.rename.UnblockCycles 58081953 # Number of cycles rename is unblocking 1924system.cpu1.rename.RenamedInsts 566482483 # Number of instructions processed by rename 1925system.cpu1.rename.SquashedInsts 5736321 # Number of squashed instructions processed by rename 1926system.cpu1.rename.ROBFullEvents 9739688 # Number of times rename has blocked due to ROB full 1927system.cpu1.rename.IQFullEvents 342221 # Number of times rename has blocked due to IQ full 1928system.cpu1.rename.LQFullEvents 843279 # Number of times rename has blocked due to LQ full 1929system.cpu1.rename.SQFullEvents 24527700 # Number of times rename has blocked due to SQ full 1930system.cpu1.rename.FullRegisterEvents 11906 # Number of times there has been no free registers 1931system.cpu1.rename.RenamedOperands 538415916 # Number of destination operands rename has renamed 1932system.cpu1.rename.RenameLookups 871757488 # Number of register rename lookups that rename has made 1933system.cpu1.rename.int_rename_lookups 668460678 # Number of integer rename lookups 1934system.cpu1.rename.fp_rename_lookups 644937 # Number of floating rename lookups 1935system.cpu1.rename.CommittedMaps 483561743 # Number of HB maps that are committed 1936system.cpu1.rename.UndoneMaps 54854172 # Number of HB maps that are undone due to squashing 1937system.cpu1.rename.serializingInsts 15093428 # count of serializing insts renamed 1938system.cpu1.rename.tempSerializingInsts 13190698 # count of temporary serializing insts renamed 1939system.cpu1.rename.skidInsts 71341154 # count of insts added to the skid buffer 1940system.cpu1.memDep0.insertedLoads 94469141 # Number of loads inserted to the mem dependence unit. 1941system.cpu1.memDep0.insertedStores 78816060 # Number of stores inserted to the mem dependence unit. 1942system.cpu1.memDep0.conflictingLoads 9208116 # Number of conflicting loads. 1943system.cpu1.memDep0.conflictingStores 7878049 # Number of conflicting stores. 1944system.cpu1.iq.iqInstsAdded 544809829 # Number of instructions added to the IQ (excludes non-spec) 1945system.cpu1.iq.iqNonSpecInstsAdded 15364466 # Number of non-speculative instructions added to the IQ 1946system.cpu1.iq.iqInstsIssued 549398452 # Number of instructions issued 1947system.cpu1.iq.iqSquashedInstsIssued 2550658 # Number of squashed instructions issued 1948system.cpu1.iq.iqSquashedInstsExamined 51789954 # Number of squashed instructions iterated over during squash; mainly for profiling 1949system.cpu1.iq.iqSquashedOperandsExamined 33366441 # Number of squashed operands that are examined and possibly removed from graph 1950system.cpu1.iq.iqSquashedNonSpecRemoved 282362 # Number of squashed non-spec instructions that were removed 1951system.cpu1.iq.issued_per_cycle::samples 664820080 # Number of insts issued each cycle 1952system.cpu1.iq.issued_per_cycle::mean 0.826387 # Number of insts issued each cycle 1953system.cpu1.iq.issued_per_cycle::stdev 1.065764 # Number of insts issued each cycle |
| 1978system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1954system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1979system.cpu1.iq.issued_per_cycle::0 444068370 56.46% 56.46% # Number of insts issued each cycle 1980system.cpu1.iq.issued_per_cycle::1 146437024 18.62% 75.07% # Number of insts issued each cycle 1981system.cpu1.iq.issued_per_cycle::2 119059525 15.14% 90.21% # Number of insts issued each cycle 1982system.cpu1.iq.issued_per_cycle::3 68792645 8.75% 98.96% # Number of insts issued each cycle 1983system.cpu1.iq.issued_per_cycle::4 8206769 1.04% 100.00% # Number of insts issued each cycle 1984system.cpu1.iq.issued_per_cycle::5 5356 0.00% 100.00% # Number of insts issued each cycle | 1955system.cpu1.iq.issued_per_cycle::0 363096071 54.62% 54.62% # Number of insts issued each cycle 1956system.cpu1.iq.issued_per_cycle::1 129026402 19.41% 74.02% # Number of insts issued each cycle 1957system.cpu1.iq.issued_per_cycle::2 104942160 15.79% 89.81% # Number of insts issued each cycle 1958system.cpu1.iq.issued_per_cycle::3 60539163 9.11% 98.91% # Number of insts issued each cycle 1959system.cpu1.iq.issued_per_cycle::4 7211179 1.08% 100.00% # Number of insts issued each cycle 1960system.cpu1.iq.issued_per_cycle::5 5105 0.00% 100.00% # Number of insts issued each cycle |
| 1985system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1986system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1987system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1988system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1989system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1990system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 1961system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1962system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1963system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1964system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1965system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1966system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 1991system.cpu1.iq.issued_per_cycle::total 786569689 # Number of insts issued each cycle | 1967system.cpu1.iq.issued_per_cycle::total 664820080 # Number of insts issued each cycle |
| 1992system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1968system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1993system.cpu1.iq.fu_full::IntAlu 62505184 44.18% 44.18% # attempts to use FU when none available 1994system.cpu1.iq.fu_full::IntMult 68578 0.05% 44.23% # attempts to use FU when none available 1995system.cpu1.iq.fu_full::IntDiv 15954 0.01% 44.24% # attempts to use FU when none available 1996system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.24% # attempts to use FU when none available 1997system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.24% # attempts to use FU when none available 1998system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.24% # attempts to use FU when none available 1999system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.24% # attempts to use FU when none available 2000system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.24% # attempts to use FU when none available 2001system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.24% # attempts to use FU when none available 2002system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.24% # attempts to use FU when none available 2003system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.24% # attempts to use FU when none available 2004system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.24% # attempts to use FU when none available 2005system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.24% # attempts to use FU when none available 2006system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.24% # attempts to use FU when none available 2007system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.24% # attempts to use FU when none available 2008system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.24% # attempts to use FU when none available 2009system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.24% # attempts to use FU when none available 2010system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.24% # attempts to use FU when none available 2011system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.24% # attempts to use FU when none available 2012system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.24% # attempts to use FU when none available 2013system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.24% # attempts to use FU when none available 2014system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.24% # attempts to use FU when none available 2015system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.24% # attempts to use FU when none available 2016system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.24% # attempts to use FU when none available 2017system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.24% # attempts to use FU when none available 2018system.cpu1.iq.fu_full::SimdFloatMisc 29 0.00% 44.24% # attempts to use FU when none available 2019system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.24% # attempts to use FU when none available 2020system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.24% # attempts to use FU when none available 2021system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.24% # attempts to use FU when none available 2022system.cpu1.iq.fu_full::MemRead 38525280 27.23% 71.47% # attempts to use FU when none available 2023system.cpu1.iq.fu_full::MemWrite 40370294 28.53% 100.00% # attempts to use FU when none available | 1969system.cpu1.iq.fu_full::IntAlu 54936992 44.00% 44.00% # attempts to use FU when none available 1970system.cpu1.iq.fu_full::IntMult 69872 0.06% 44.05% # attempts to use FU when none available 1971system.cpu1.iq.fu_full::IntDiv 6570 0.01% 44.06% # attempts to use FU when none available 1972system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.06% # attempts to use FU when none available 1973system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.06% # attempts to use FU when none available 1974system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.06% # attempts to use FU when none available 1975system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.06% # attempts to use FU when none available 1976system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.06% # attempts to use FU when none available 1977system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.06% # attempts to use FU when none available 1978system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.06% # attempts to use FU when none available 1979system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.06% # attempts to use FU when none available 1980system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.06% # attempts to use FU when none available 1981system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.06% # attempts to use FU when none available 1982system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.06% # attempts to use FU when none available 1983system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.06% # attempts to use FU when none available 1984system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.06% # attempts to use FU when none available 1985system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.06% # attempts to use FU when none available 1986system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.06% # attempts to use FU when none available 1987system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.06% # attempts to use FU when none available 1988system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.06% # attempts to use FU when none available 1989system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.06% # attempts to use FU when none available 1990system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.06% # attempts to use FU when none available 1991system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.06% # attempts to use FU when none available 1992system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.06% # attempts to use FU when none available 1993system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.06% # attempts to use FU when none available 1994system.cpu1.iq.fu_full::SimdFloatMisc 17 0.00% 44.06% # attempts to use FU when none available 1995system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.06% # attempts to use FU when none available 1996system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.06% # attempts to use FU when none available 1997system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.06% # attempts to use FU when none available 1998system.cpu1.iq.fu_full::MemRead 34367116 27.52% 71.58% # attempts to use FU when none available 1999system.cpu1.iq.fu_full::MemWrite 35481157 28.42% 100.00% # attempts to use FU when none available |
| 2024system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2025system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2026system.cpu1.iq.FU_type_0::No_OpClass 56 0.00% 0.00% # Type of FU issued | 2000system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2001system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2002system.cpu1.iq.FU_type_0::No_OpClass 56 0.00% 0.00% # Type of FU issued |
| 2027system.cpu1.iq.FU_type_0::IntAlu 425111535 68.15% 68.15% # Type of FU issued 2028system.cpu1.iq.FU_type_0::IntMult 1458161 0.23% 68.38% # Type of FU issued 2029system.cpu1.iq.FU_type_0::IntDiv 82493 0.01% 68.40% # Type of FU issued 2030system.cpu1.iq.FU_type_0::FloatAdd 4 0.00% 68.40% # Type of FU issued 2031system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.40% # Type of FU issued 2032system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.40% # Type of FU issued 2033system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.40% # Type of FU issued 2034system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.40% # Type of FU issued 2035system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued 2036system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued 2037system.cpu1.iq.FU_type_0::SimdAddAcc 1 0.00% 68.40% # Type of FU issued 2038system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.40% # Type of FU issued 2039system.cpu1.iq.FU_type_0::SimdCmp 1 0.00% 68.40% # Type of FU issued 2040system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.40% # Type of FU issued 2041system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.40% # Type of FU issued 2042system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.40% # Type of FU issued 2043system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.40% # Type of FU issued 2044system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.40% # Type of FU issued 2045system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.40% # Type of FU issued 2046system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.40% # Type of FU issued 2047system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.40% # Type of FU issued 2048system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.40% # Type of FU issued 2049system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.40% # Type of FU issued 2050system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.40% # Type of FU issued 2051system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.40% # Type of FU issued 2052system.cpu1.iq.FU_type_0::SimdFloatMisc 80022 0.01% 68.41% # Type of FU issued 2053system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.41% # Type of FU issued 2054system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.41% # Type of FU issued 2055system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.41% # Type of FU issued 2056system.cpu1.iq.FU_type_0::MemRead 109884961 17.62% 86.03% # Type of FU issued 2057system.cpu1.iq.FU_type_0::MemWrite 87170631 13.97% 100.00% # Type of FU issued | 2003system.cpu1.iq.FU_type_0::IntAlu 373883416 68.05% 68.05% # Type of FU issued 2004system.cpu1.iq.FU_type_0::IntMult 1335155 0.24% 68.30% # Type of FU issued 2005system.cpu1.iq.FU_type_0::IntDiv 74884 0.01% 68.31% # Type of FU issued 2006system.cpu1.iq.FU_type_0::FloatAdd 11 0.00% 68.31% # Type of FU issued 2007system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued 2008system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued 2009system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued 2010system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.31% # Type of FU issued 2011system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.31% # Type of FU issued 2012system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.31% # Type of FU issued 2013system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.31% # Type of FU issued 2014system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.31% # Type of FU issued 2015system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.31% # Type of FU issued 2016system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.31% # Type of FU issued 2017system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.31% # Type of FU issued 2018system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.31% # Type of FU issued 2019system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.31% # Type of FU issued 2020system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.31% # Type of FU issued 2021system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.31% # Type of FU issued 2022system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.31% # Type of FU issued 2023system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.31% # Type of FU issued 2024system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.31% # Type of FU issued 2025system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.31% # Type of FU issued 2026system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.31% # Type of FU issued 2027system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.31% # Type of FU issued 2028system.cpu1.iq.FU_type_0::SimdFloatMisc 48854 0.01% 68.32% # Type of FU issued 2029system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued 2030system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued 2031system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued 2032system.cpu1.iq.FU_type_0::MemRead 97153433 17.68% 86.00% # Type of FU issued 2033system.cpu1.iq.FU_type_0::MemWrite 76902643 14.00% 100.00% # Type of FU issued |
| 2058system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2059system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 2034system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2035system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 2060system.cpu1.iq.FU_type_0::total 623787865 # Type of FU issued 2061system.cpu1.iq.rate 0.767708 # Inst issue rate 2062system.cpu1.iq.fu_busy_cnt 141485319 # FU busy when requested 2063system.cpu1.iq.fu_busy_rate 0.226816 # FU busy rate (busy events/executed inst) 2064system.cpu1.iq.int_inst_queue_reads 2177185436 # Number of integer instruction queue reads 2065system.cpu1.iq.int_inst_queue_writes 693073885 # Number of integer instruction queue writes 2066system.cpu1.iq.int_inst_queue_wakeup_accesses 605244442 # Number of integer instruction queue wakeup accesses 2067system.cpu1.iq.fp_inst_queue_reads 1319124 # Number of floating instruction queue reads 2068system.cpu1.iq.fp_inst_queue_writes 525529 # Number of floating instruction queue writes 2069system.cpu1.iq.fp_inst_queue_wakeup_accesses 491804 # Number of floating instruction queue wakeup accesses 2070system.cpu1.iq.int_alu_accesses 764456486 # Number of integer alu accesses 2071system.cpu1.iq.fp_alu_accesses 816642 # Number of floating point alu accesses 2072system.cpu1.iew.lsq.thread0.forwLoads 2875534 # Number of loads that had data forwarded from stores | 2036system.cpu1.iq.FU_type_0::total 549398452 # Type of FU issued 2037system.cpu1.iq.rate 0.803948 # Inst issue rate 2038system.cpu1.iq.fu_busy_cnt 124861724 # FU busy when requested 2039system.cpu1.iq.fu_busy_rate 0.227270 # FU busy rate (busy events/executed inst) 2040system.cpu1.iq.int_inst_queue_reads 1889962970 # Number of integer instruction queue reads 2041system.cpu1.iq.int_inst_queue_writes 611689245 # Number of integer instruction queue writes 2042system.cpu1.iq.int_inst_queue_wakeup_accesses 533047508 # Number of integer instruction queue wakeup accesses 2043system.cpu1.iq.fp_inst_queue_reads 1066396 # Number of floating instruction queue reads 2044system.cpu1.iq.fp_inst_queue_writes 424008 # Number of floating instruction queue writes 2045system.cpu1.iq.fp_inst_queue_wakeup_accesses 393622 # Number of floating instruction queue wakeup accesses 2046system.cpu1.iq.int_alu_accesses 673596915 # Number of integer alu accesses 2047system.cpu1.iq.fp_alu_accesses 663205 # Number of floating point alu accesses 2048system.cpu1.iew.lsq.thread0.forwLoads 2524444 # Number of loads that had data forwarded from stores |
| 2073system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 2049system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 2074system.cpu1.iew.lsq.thread0.squashedLoads 13536096 # Number of loads squashed 2075system.cpu1.iew.lsq.thread0.ignoredResponses 19732 # Number of memory responses ignored because the instruction is squashed 2076system.cpu1.iew.lsq.thread0.memOrderViolation 165171 # Number of memory ordering violations 2077system.cpu1.iew.lsq.thread0.squashedStores 5907805 # Number of stores squashed | 2050system.cpu1.iew.lsq.thread0.squashedLoads 12144847 # Number of loads squashed 2051system.cpu1.iew.lsq.thread0.ignoredResponses 16403 # Number of memory responses ignored because the instruction is squashed 2052system.cpu1.iew.lsq.thread0.memOrderViolation 149896 # Number of memory ordering violations 2053system.cpu1.iew.lsq.thread0.squashedStores 5262071 # Number of stores squashed |
| 2078system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2079system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 2054system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2055system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 2080system.cpu1.iew.lsq.thread0.rescheduledLoads 2920913 # Number of loads that were rescheduled 2081system.cpu1.iew.lsq.thread0.cacheBlocked 4601873 # Number of times an access to memory failed due to the cache being blocked | 2056system.cpu1.iew.lsq.thread0.rescheduledLoads 2572719 # Number of loads that were rescheduled 2057system.cpu1.iew.lsq.thread0.cacheBlocked 4009144 # Number of times an access to memory failed due to the cache being blocked |
| 2082system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 2058system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 2083system.cpu1.iew.iewSquashCycles 5485807 # Number of cycles IEW is squashing 2084system.cpu1.iew.iewBlockCycles 8833718 # Number of cycles IEW is blocking 2085system.cpu1.iew.iewUnblockCycles 2787810 # Number of cycles IEW is unblocking 2086system.cpu1.iew.iewDispatchedInsts 635796262 # Number of instructions dispatched to IQ | 2059system.cpu1.iew.iewSquashCycles 4929156 # Number of cycles IEW is squashing 2060system.cpu1.iew.iewBlockCycles 7182655 # Number of cycles IEW is blocking 2061system.cpu1.iew.iewUnblockCycles 1646879 # Number of cycles IEW is unblocking 2062system.cpu1.iew.iewDispatchedInsts 560304926 # Number of instructions dispatched to IQ |
| 2087system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 2063system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 2088system.cpu1.iew.iewDispLoadInsts 106673767 # Number of dispatched load instructions 2089system.cpu1.iew.iewDispStoreInsts 89326102 # Number of dispatched store instructions 2090system.cpu1.iew.iewDispNonSpecInsts 14923932 # Number of dispatched non-speculative instructions 2091system.cpu1.iew.iewIQFullEvents 69191 # Number of times the IQ has become full, causing a stall 2092system.cpu1.iew.iewLSQFullEvents 2639688 # Number of times the LSQ has become full, causing a stall 2093system.cpu1.iew.memOrderViolationEvents 165171 # Number of memory order violations 2094system.cpu1.iew.predictedTakenIncorrect 2071854 # Number of branches that were predicted taken incorrectly 2095system.cpu1.iew.predictedNotTakenIncorrect 3210854 # Number of branches that were predicted not taken incorrectly 2096system.cpu1.iew.branchMispredicts 5282708 # Number of branch mispredicts detected at execute 2097system.cpu1.iew.iewExecutedInsts 615332242 # Number of executed instructions 2098system.cpu1.iew.iewExecLoadInsts 106464546 # Number of load instructions executed 2099system.cpu1.iew.iewExecSquashedInsts 7808914 # Number of squashed instructions skipped in execute | 2064system.cpu1.iew.iewDispLoadInsts 94469141 # Number of dispatched load instructions 2065system.cpu1.iew.iewDispStoreInsts 78816060 # Number of dispatched store instructions 2066system.cpu1.iew.iewDispNonSpecInsts 12974148 # Number of dispatched non-speculative instructions 2067system.cpu1.iew.iewIQFullEvents 56258 # Number of times the IQ has become full, causing a stall 2068system.cpu1.iew.iewLSQFullEvents 1524659 # Number of times the LSQ has become full, causing a stall 2069system.cpu1.iew.memOrderViolationEvents 149896 # Number of memory order violations 2070system.cpu1.iew.predictedTakenIncorrect 1843431 # Number of branches that were predicted taken incorrectly 2071system.cpu1.iew.predictedNotTakenIncorrect 2924818 # Number of branches that were predicted not taken incorrectly 2072system.cpu1.iew.branchMispredicts 4768249 # Number of branch mispredicts detected at execute 2073system.cpu1.iew.iewExecutedInsts 541845400 # Number of executed instructions 2074system.cpu1.iew.iewExecLoadInsts 94094962 # Number of load instructions executed 2075system.cpu1.iew.iewExecSquashedInsts 6980663 # Number of squashed instructions skipped in execute |
| 2100system.cpu1.iew.exec_swp 0 # number of swp insts executed | 2076system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 2101system.cpu1.iew.exec_nop 144491 # number of nop insts executed 2102system.cpu1.iew.exec_refs 192321367 # number of memory reference insts executed 2103system.cpu1.iew.exec_branches 115394599 # Number of branches executed 2104system.cpu1.iew.exec_stores 85856821 # Number of stores executed 2105system.cpu1.iew.exec_rate 0.757302 # Inst execution rate 2106system.cpu1.iew.wb_sent 606557665 # cumulative count of insts sent to commit 2107system.cpu1.iew.wb_count 605736246 # cumulative count of insts written-back 2108system.cpu1.iew.wb_producers 294174085 # num instructions producing a value 2109system.cpu1.iew.wb_consumers 482464820 # num instructions consuming a value 2110system.cpu1.iew.wb_rate 0.745492 # insts written-back per cycle 2111system.cpu1.iew.wb_fanout 0.609732 # average fanout of values written-back 2112system.cpu1.commit.commitSquashedInsts 50535620 # The number of squashed insts skipped by commit 2113system.cpu1.commit.commitNonSpecStalls 17222374 # The number of times commit has been forced to stall to communicate backwards 2114system.cpu1.commit.branchMispredicts 4915629 # The number of times a branch was mispredicted 2115system.cpu1.commit.committed_per_cycle::samples 776983088 # Number of insts commited each cycle 2116system.cpu1.commit.committed_per_cycle::mean 0.743733 # Number of insts commited each cycle 2117system.cpu1.commit.committed_per_cycle::stdev 1.546908 # Number of insts commited each cycle | 2077system.cpu1.iew.exec_nop 130631 # number of nop insts executed 2078system.cpu1.iew.exec_refs 169824676 # number of memory reference insts executed 2079system.cpu1.iew.exec_branches 101510793 # Number of branches executed 2080system.cpu1.iew.exec_stores 75729714 # Number of stores executed 2081system.cpu1.iew.exec_rate 0.792895 # Inst execution rate 2082system.cpu1.iew.wb_sent 534152020 # cumulative count of insts sent to commit 2083system.cpu1.iew.wb_count 533441130 # cumulative count of insts written-back 2084system.cpu1.iew.wb_producers 258912640 # num instructions producing a value 2085system.cpu1.iew.wb_consumers 423656459 # num instructions consuming a value 2086system.cpu1.iew.wb_rate 0.780597 # insts written-back per cycle 2087system.cpu1.iew.wb_fanout 0.611138 # average fanout of values written-back 2088system.cpu1.commit.commitSquashedInsts 45293147 # The number of squashed insts skipped by commit 2089system.cpu1.commit.commitNonSpecStalls 15082103 # The number of times commit has been forced to stall to communicate backwards 2090system.cpu1.commit.branchMispredicts 4436923 # The number of times a branch was mispredicted 2091system.cpu1.commit.committed_per_cycle::samples 656213363 # Number of insts commited each cycle 2092system.cpu1.commit.committed_per_cycle::mean 0.774724 # Number of insts commited each cycle 2093system.cpu1.commit.committed_per_cycle::stdev 1.573400 # Number of insts commited each cycle |
| 2118system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 2094system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 2119system.cpu1.commit.committed_per_cycle::0 522401316 67.23% 67.23% # Number of insts commited each cycle 2120system.cpu1.commit.committed_per_cycle::1 133381083 17.17% 84.40% # Number of insts commited each cycle 2121system.cpu1.commit.committed_per_cycle::2 55837578 7.19% 91.59% # Number of insts commited each cycle 2122system.cpu1.commit.committed_per_cycle::3 18787317 2.42% 94.01% # Number of insts commited each cycle 2123system.cpu1.commit.committed_per_cycle::4 13118953 1.69% 95.69% # Number of insts commited each cycle 2124system.cpu1.commit.committed_per_cycle::5 9117290 1.17% 96.87% # Number of insts commited each cycle 2125system.cpu1.commit.committed_per_cycle::6 6295998 0.81% 97.68% # Number of insts commited each cycle 2126system.cpu1.commit.committed_per_cycle::7 3737021 0.48% 98.16% # Number of insts commited each cycle 2127system.cpu1.commit.committed_per_cycle::8 14306532 1.84% 100.00% # Number of insts commited each cycle | 2095system.cpu1.commit.committed_per_cycle::0 432598016 65.92% 65.92% # Number of insts commited each cycle 2096system.cpu1.commit.committed_per_cycle::1 117091486 17.84% 83.77% # Number of insts commited each cycle 2097system.cpu1.commit.committed_per_cycle::2 49126445 7.49% 91.25% # Number of insts commited each cycle 2098system.cpu1.commit.committed_per_cycle::3 16229930 2.47% 93.73% # Number of insts commited each cycle 2099system.cpu1.commit.committed_per_cycle::4 11628277 1.77% 95.50% # Number of insts commited each cycle 2100system.cpu1.commit.committed_per_cycle::5 8033144 1.22% 96.72% # Number of insts commited each cycle 2101system.cpu1.commit.committed_per_cycle::6 5546832 0.85% 97.57% # Number of insts commited each cycle 2102system.cpu1.commit.committed_per_cycle::7 3283510 0.50% 98.07% # Number of insts commited each cycle 2103system.cpu1.commit.committed_per_cycle::8 12675723 1.93% 100.00% # Number of insts commited each cycle |
| 2128system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2129system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2130system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 2104system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2105system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2106system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 2131system.cpu1.commit.committed_per_cycle::total 776983088 # Number of insts commited each cycle 2132system.cpu1.commit.committedInsts 491216523 # Number of instructions committed 2133system.cpu1.commit.committedOps 577867843 # Number of ops (including micro ops) committed | 2107system.cpu1.commit.committed_per_cycle::total 656213363 # Number of insts commited each cycle 2108system.cpu1.commit.committedInsts 431870837 # Number of instructions committed 2109system.cpu1.commit.committedOps 508384340 # Number of ops (including micro ops) committed |
| 2134system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 2110system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 2135system.cpu1.commit.refs 176555967 # Number of memory references committed 2136system.cpu1.commit.loads 93137670 # Number of loads committed 2137system.cpu1.commit.membars 4128399 # Number of memory barriers committed 2138system.cpu1.commit.branches 109594417 # Number of branches committed 2139system.cpu1.commit.fp_insts 483207 # Number of committed floating point instructions. 2140system.cpu1.commit.int_insts 530271703 # Number of committed integer instructions. 2141system.cpu1.commit.function_calls 14440728 # Number of function calls committed. | 2111system.cpu1.commit.refs 155878283 # Number of memory references committed 2112system.cpu1.commit.loads 82324294 # Number of loads committed 2113system.cpu1.commit.membars 3722309 # Number of memory barriers committed 2114system.cpu1.commit.branches 96290107 # Number of branches committed 2115system.cpu1.commit.fp_insts 384716 # Number of committed floating point instructions. 2116system.cpu1.commit.int_insts 467163355 # Number of committed integer instructions. 2117system.cpu1.commit.function_calls 12903273 # Number of function calls committed. |
| 2142system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 2118system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 2143system.cpu1.commit.op_class_0::IntAlu 399975864 69.22% 69.22% # Class of committed instruction 2144system.cpu1.commit.op_class_0::IntMult 1198206 0.21% 69.42% # Class of committed instruction 2145system.cpu1.commit.op_class_0::IntDiv 65313 0.01% 69.43% # Class of committed instruction 2146system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.43% # Class of committed instruction 2147system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.43% # Class of committed instruction 2148system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.43% # Class of committed instruction 2149system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.43% # Class of committed instruction 2150system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.43% # Class of committed instruction 2151system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.43% # Class of committed instruction 2152system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.43% # Class of committed instruction 2153system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.43% # Class of committed instruction 2154system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.43% # Class of committed instruction 2155system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.43% # Class of committed instruction 2156system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.43% # Class of committed instruction 2157system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.43% # Class of committed instruction 2158system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.43% # Class of committed instruction 2159system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.43% # Class of committed instruction 2160system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.43% # Class of committed instruction 2161system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.43% # Class of committed instruction 2162system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.43% # Class of committed instruction 2163system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.43% # Class of committed instruction 2164system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.43% # Class of committed instruction 2165system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.43% # Class of committed instruction 2166system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.43% # Class of committed instruction 2167system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.43% # Class of committed instruction 2168system.cpu1.commit.op_class_0::SimdFloatMisc 72493 0.01% 69.45% # Class of committed instruction 2169system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.45% # Class of committed instruction 2170system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.45% # Class of committed instruction 2171system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.45% # Class of committed instruction 2172system.cpu1.commit.op_class_0::MemRead 93137670 16.12% 85.56% # Class of committed instruction 2173system.cpu1.commit.op_class_0::MemWrite 83418297 14.44% 100.00% # Class of committed instruction | 2119system.cpu1.commit.op_class_0::IntAlu 351312000 69.10% 69.10% # Class of committed instruction 2120system.cpu1.commit.op_class_0::IntMult 1092238 0.21% 69.32% # Class of committed instruction 2121system.cpu1.commit.op_class_0::IntDiv 59391 0.01% 69.33% # Class of committed instruction 2122system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction 2123system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction 2124system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction 2125system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction 2126system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction 2127system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction 2128system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction 2129system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction 2130system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction 2131system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction 2132system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction 2133system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction 2134system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction 2135system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction 2136system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction 2137system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction 2138system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction 2139system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction 2140system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction 2141system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction 2142system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction 2143system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction 2144system.cpu1.commit.op_class_0::SimdFloatMisc 42428 0.01% 69.34% # Class of committed instruction 2145system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.34% # Class of committed instruction 2146system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.34% # Class of committed instruction 2147system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.34% # Class of committed instruction 2148system.cpu1.commit.op_class_0::MemRead 82324294 16.19% 85.53% # Class of committed instruction 2149system.cpu1.commit.op_class_0::MemWrite 73553989 14.47% 100.00% # Class of committed instruction |
| 2174system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2175system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 2150system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2151system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 2176system.cpu1.commit.op_class_0::total 577867843 # Class of committed instruction 2177system.cpu1.commit.bw_lim_events 14306532 # number cycles where commit BW limit reached 2178system.cpu1.rob.rob_reads 1386603636 # The number of ROB reads 2179system.cpu1.rob.rob_writes 1266352729 # The number of ROB writes 2180system.cpu1.timesIdled 1031751 # Number of times that the entire CPU went into an idle state and unscheduled itself 2181system.cpu1.idleCycles 25962869 # Total number of cycles that the CPU has spent unscheduled due to idling 2182system.cpu1.quiesceCycles 94124971438 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2183system.cpu1.committedInsts 491216523 # Number of Instructions Simulated 2184system.cpu1.committedOps 577867843 # Number of Ops (including micro ops) Simulated 2185system.cpu1.cpi 1.654123 # CPI: Cycles Per Instruction 2186system.cpu1.cpi_total 1.654123 # CPI: Total CPI of All Threads 2187system.cpu1.ipc 0.604550 # IPC: Instructions Per Cycle 2188system.cpu1.ipc_total 0.604550 # IPC: Total IPC of All Threads 2189system.cpu1.int_regfile_reads 726234004 # number of integer regfile reads 2190system.cpu1.int_regfile_writes 431188126 # number of integer regfile writes 2191system.cpu1.fp_regfile_reads 774766 # number of floating regfile reads 2192system.cpu1.fp_regfile_writes 462404 # number of floating regfile writes 2193system.cpu1.cc_regfile_reads 133303662 # number of cc regfile reads 2194system.cpu1.cc_regfile_writes 133988748 # number of cc regfile writes 2195system.cpu1.misc_regfile_reads 1377831690 # number of misc regfile reads 2196system.cpu1.misc_regfile_writes 17262707 # number of misc regfile writes 2197system.cpu1.dcache.tags.replacements 6040824 # number of replacements 2198system.cpu1.dcache.tags.tagsinuse 459.378668 # Cycle average of tags in use 2199system.cpu1.dcache.tags.total_refs 164299100 # Total number of references to valid blocks. 2200system.cpu1.dcache.tags.sampled_refs 6041336 # Sample count of references to valid blocks. 2201system.cpu1.dcache.tags.avg_refs 27.195822 # Average number of references to valid blocks. 2202system.cpu1.dcache.tags.warmup_cycle 8482617709500 # Cycle when the warmup percentage was hit. 2203system.cpu1.dcache.tags.occ_blocks::cpu1.data 459.378668 # Average occupied blocks per requestor 2204system.cpu1.dcache.tags.occ_percent::cpu1.data 0.897224 # Average percentage of cache occupancy 2205system.cpu1.dcache.tags.occ_percent::total 0.897224 # Average percentage of cache occupancy 2206system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2207system.cpu1.dcache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 2208system.cpu1.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id 2209system.cpu1.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id 2210system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2211system.cpu1.dcache.tags.tag_accesses 366496301 # Number of tag accesses 2212system.cpu1.dcache.tags.data_accesses 366496301 # Number of data accesses 2213system.cpu1.dcache.ReadReq_hits::cpu1.data 86507946 # number of ReadReq hits 2214system.cpu1.dcache.ReadReq_hits::total 86507946 # number of ReadReq hits 2215system.cpu1.dcache.WriteReq_hits::cpu1.data 72726229 # number of WriteReq hits 2216system.cpu1.dcache.WriteReq_hits::total 72726229 # number of WriteReq hits 2217system.cpu1.dcache.SoftPFReq_hits::cpu1.data 199332 # number of SoftPFReq hits 2218system.cpu1.dcache.SoftPFReq_hits::total 199332 # number of SoftPFReq hits 2219system.cpu1.dcache.WriteLineReq_hits::cpu1.data 142639 # number of WriteLineReq hits 2220system.cpu1.dcache.WriteLineReq_hits::total 142639 # number of WriteLineReq hits 2221system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1934214 # number of LoadLockedReq hits 2222system.cpu1.dcache.LoadLockedReq_hits::total 1934214 # number of LoadLockedReq hits 2223system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1984655 # number of StoreCondReq hits 2224system.cpu1.dcache.StoreCondReq_hits::total 1984655 # number of StoreCondReq hits 2225system.cpu1.dcache.demand_hits::cpu1.data 159376814 # number of demand (read+write) hits 2226system.cpu1.dcache.demand_hits::total 159376814 # number of demand (read+write) hits 2227system.cpu1.dcache.overall_hits::cpu1.data 159576146 # number of overall hits 2228system.cpu1.dcache.overall_hits::total 159576146 # number of overall hits 2229system.cpu1.dcache.ReadReq_misses::cpu1.data 7084890 # number of ReadReq misses 2230system.cpu1.dcache.ReadReq_misses::total 7084890 # number of ReadReq misses 2231system.cpu1.dcache.WriteReq_misses::cpu1.data 7887926 # number of WriteReq misses 2232system.cpu1.dcache.WriteReq_misses::total 7887926 # number of WriteReq misses 2233system.cpu1.dcache.SoftPFReq_misses::cpu1.data 742812 # number of SoftPFReq misses 2234system.cpu1.dcache.SoftPFReq_misses::total 742812 # number of SoftPFReq misses 2235system.cpu1.dcache.WriteLineReq_misses::cpu1.data 468512 # number of WriteLineReq misses 2236system.cpu1.dcache.WriteLineReq_misses::total 468512 # number of WriteLineReq misses 2237system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 301623 # number of LoadLockedReq misses 2238system.cpu1.dcache.LoadLockedReq_misses::total 301623 # number of LoadLockedReq misses 2239system.cpu1.dcache.StoreCondReq_misses::cpu1.data 202162 # number of StoreCondReq misses 2240system.cpu1.dcache.StoreCondReq_misses::total 202162 # number of StoreCondReq misses 2241system.cpu1.dcache.demand_misses::cpu1.data 15441328 # number of demand (read+write) misses 2242system.cpu1.dcache.demand_misses::total 15441328 # number of demand (read+write) misses 2243system.cpu1.dcache.overall_misses::cpu1.data 16184140 # number of overall misses 2244system.cpu1.dcache.overall_misses::total 16184140 # number of overall misses 2245system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 122386342500 # number of ReadReq miss cycles 2246system.cpu1.dcache.ReadReq_miss_latency::total 122386342500 # number of ReadReq miss cycles 2247system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 173974758337 # number of WriteReq miss cycles 2248system.cpu1.dcache.WriteReq_miss_latency::total 173974758337 # number of WriteReq miss cycles 2249system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20327422974 # number of WriteLineReq miss cycles 2250system.cpu1.dcache.WriteLineReq_miss_latency::total 20327422974 # number of WriteLineReq miss cycles 2251system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 5004935500 # number of LoadLockedReq miss cycles 2252system.cpu1.dcache.LoadLockedReq_miss_latency::total 5004935500 # number of LoadLockedReq miss cycles 2253system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5709587500 # number of StoreCondReq miss cycles 2254system.cpu1.dcache.StoreCondReq_miss_latency::total 5709587500 # number of StoreCondReq miss cycles 2255system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3496000 # number of StoreCondFailReq miss cycles 2256system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3496000 # number of StoreCondFailReq miss cycles 2257system.cpu1.dcache.demand_miss_latency::cpu1.data 316688523811 # number of demand (read+write) miss cycles 2258system.cpu1.dcache.demand_miss_latency::total 316688523811 # number of demand (read+write) miss cycles 2259system.cpu1.dcache.overall_miss_latency::cpu1.data 316688523811 # number of overall miss cycles 2260system.cpu1.dcache.overall_miss_latency::total 316688523811 # number of overall miss cycles 2261system.cpu1.dcache.ReadReq_accesses::cpu1.data 93592836 # number of ReadReq accesses(hits+misses) 2262system.cpu1.dcache.ReadReq_accesses::total 93592836 # number of ReadReq accesses(hits+misses) 2263system.cpu1.dcache.WriteReq_accesses::cpu1.data 80614155 # number of WriteReq accesses(hits+misses) 2264system.cpu1.dcache.WriteReq_accesses::total 80614155 # number of WriteReq accesses(hits+misses) 2265system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 942144 # number of SoftPFReq accesses(hits+misses) 2266system.cpu1.dcache.SoftPFReq_accesses::total 942144 # number of SoftPFReq accesses(hits+misses) 2267system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 611151 # number of WriteLineReq accesses(hits+misses) 2268system.cpu1.dcache.WriteLineReq_accesses::total 611151 # number of WriteLineReq accesses(hits+misses) 2269system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2235837 # number of LoadLockedReq accesses(hits+misses) 2270system.cpu1.dcache.LoadLockedReq_accesses::total 2235837 # number of LoadLockedReq accesses(hits+misses) 2271system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2186817 # number of StoreCondReq accesses(hits+misses) 2272system.cpu1.dcache.StoreCondReq_accesses::total 2186817 # number of StoreCondReq accesses(hits+misses) 2273system.cpu1.dcache.demand_accesses::cpu1.data 174818142 # number of demand (read+write) accesses 2274system.cpu1.dcache.demand_accesses::total 174818142 # number of demand (read+write) accesses 2275system.cpu1.dcache.overall_accesses::cpu1.data 175760286 # number of overall (read+write) accesses 2276system.cpu1.dcache.overall_accesses::total 175760286 # number of overall (read+write) accesses 2277system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.075699 # miss rate for ReadReq accesses 2278system.cpu1.dcache.ReadReq_miss_rate::total 0.075699 # miss rate for ReadReq accesses 2279system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.097848 # miss rate for WriteReq accesses 2280system.cpu1.dcache.WriteReq_miss_rate::total 0.097848 # miss rate for WriteReq accesses 2281system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.788427 # miss rate for SoftPFReq accesses 2282system.cpu1.dcache.SoftPFReq_miss_rate::total 0.788427 # miss rate for SoftPFReq accesses 2283system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.766606 # miss rate for WriteLineReq accesses 2284system.cpu1.dcache.WriteLineReq_miss_rate::total 0.766606 # miss rate for WriteLineReq accesses 2285system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.134904 # miss rate for LoadLockedReq accesses 2286system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.134904 # miss rate for LoadLockedReq accesses 2287system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.092446 # miss rate for StoreCondReq accesses 2288system.cpu1.dcache.StoreCondReq_miss_rate::total 0.092446 # miss rate for StoreCondReq accesses 2289system.cpu1.dcache.demand_miss_rate::cpu1.data 0.088328 # miss rate for demand accesses 2290system.cpu1.dcache.demand_miss_rate::total 0.088328 # miss rate for demand accesses 2291system.cpu1.dcache.overall_miss_rate::cpu1.data 0.092081 # miss rate for overall accesses 2292system.cpu1.dcache.overall_miss_rate::total 0.092081 # miss rate for overall accesses 2293system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17274.275606 # average ReadReq miss latency 2294system.cpu1.dcache.ReadReq_avg_miss_latency::total 17274.275606 # average ReadReq miss latency 2295system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22055.830435 # average WriteReq miss latency 2296system.cpu1.dcache.WriteReq_avg_miss_latency::total 22055.830435 # average WriteReq miss latency 2297system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 43387.198138 # average WriteLineReq miss latency 2298system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 43387.198138 # average WriteLineReq miss latency 2299system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16593.348319 # average LoadLockedReq miss latency 2300system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16593.348319 # average LoadLockedReq miss latency 2301system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28242.634620 # average StoreCondReq miss latency 2302system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28242.634620 # average StoreCondReq miss latency | 2152system.cpu1.commit.op_class_0::total 508384340 # Class of committed instruction 2153system.cpu1.commit.bw_lim_events 12675723 # number cycles where commit BW limit reached 2154system.cpu1.rob.rob_reads 1193390155 # The number of ROB reads 2155system.cpu1.rob.rob_writes 1115923607 # The number of ROB writes 2156system.cpu1.timesIdled 934929 # Number of times that the entire CPU went into an idle state and unscheduled itself 2157system.cpu1.idleCycles 18555780 # Total number of cycles that the CPU has spent unscheduled due to idling 2158system.cpu1.quiesceCycles 94085254498 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2159system.cpu1.committedInsts 431870837 # Number of Instructions Simulated 2160system.cpu1.committedOps 508384340 # Number of Ops (including micro ops) Simulated 2161system.cpu1.cpi 1.582362 # CPI: Cycles Per Instruction 2162system.cpu1.cpi_total 1.582362 # CPI: Total CPI of All Threads 2163system.cpu1.ipc 0.631967 # IPC: Instructions Per Cycle 2164system.cpu1.ipc_total 0.631967 # IPC: Total IPC of All Threads 2165system.cpu1.int_regfile_reads 639570382 # number of integer regfile reads 2166system.cpu1.int_regfile_writes 380109427 # number of integer regfile writes 2167system.cpu1.fp_regfile_reads 631427 # number of floating regfile reads 2168system.cpu1.fp_regfile_writes 338972 # number of floating regfile writes 2169system.cpu1.cc_regfile_reads 115255782 # number of cc regfile reads 2170system.cpu1.cc_regfile_writes 115917819 # number of cc regfile writes 2171system.cpu1.misc_regfile_reads 1185795918 # number of misc regfile reads 2172system.cpu1.misc_regfile_writes 15045931 # number of misc regfile writes 2173system.cpu1.dcache.tags.replacements 5420466 # number of replacements 2174system.cpu1.dcache.tags.tagsinuse 437.277482 # Cycle average of tags in use 2175system.cpu1.dcache.tags.total_refs 144971712 # Total number of references to valid blocks. 2176system.cpu1.dcache.tags.sampled_refs 5420977 # Sample count of references to valid blocks. 2177system.cpu1.dcache.tags.avg_refs 26.742728 # Average number of references to valid blocks. 2178system.cpu1.dcache.tags.warmup_cycle 8477404255000 # Cycle when the warmup percentage was hit. 2179system.cpu1.dcache.tags.occ_blocks::cpu1.data 437.277482 # Average occupied blocks per requestor 2180system.cpu1.dcache.tags.occ_percent::cpu1.data 0.854058 # Average percentage of cache occupancy 2181system.cpu1.dcache.tags.occ_percent::total 0.854058 # Average percentage of cache occupancy 2182system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 2183system.cpu1.dcache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id 2184system.cpu1.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id 2185system.cpu1.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 2186system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 2187system.cpu1.dcache.tags.tag_accesses 323922794 # Number of tag accesses 2188system.cpu1.dcache.tags.data_accesses 323922794 # Number of data accesses 2189system.cpu1.dcache.ReadReq_hits::cpu1.data 76466425 # number of ReadReq hits 2190system.cpu1.dcache.ReadReq_hits::total 76466425 # number of ReadReq hits 2191system.cpu1.dcache.WriteReq_hits::cpu1.data 64110613 # number of WriteReq hits 2192system.cpu1.dcache.WriteReq_hits::total 64110613 # number of WriteReq hits 2193system.cpu1.dcache.SoftPFReq_hits::cpu1.data 170428 # number of SoftPFReq hits 2194system.cpu1.dcache.SoftPFReq_hits::total 170428 # number of SoftPFReq hits 2195system.cpu1.dcache.WriteLineReq_hits::cpu1.data 51164 # number of WriteLineReq hits 2196system.cpu1.dcache.WriteLineReq_hits::total 51164 # number of WriteLineReq hits 2197system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1700918 # number of LoadLockedReq hits 2198system.cpu1.dcache.LoadLockedReq_hits::total 1700918 # number of LoadLockedReq hits 2199system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1741756 # number of StoreCondReq hits 2200system.cpu1.dcache.StoreCondReq_hits::total 1741756 # number of StoreCondReq hits 2201system.cpu1.dcache.demand_hits::cpu1.data 140628202 # number of demand (read+write) hits 2202system.cpu1.dcache.demand_hits::total 140628202 # number of demand (read+write) hits 2203system.cpu1.dcache.overall_hits::cpu1.data 140798630 # number of overall hits 2204system.cpu1.dcache.overall_hits::total 140798630 # number of overall hits 2205system.cpu1.dcache.ReadReq_misses::cpu1.data 6372316 # number of ReadReq misses 2206system.cpu1.dcache.ReadReq_misses::total 6372316 # number of ReadReq misses 2207system.cpu1.dcache.WriteReq_misses::cpu1.data 7014697 # number of WriteReq misses 2208system.cpu1.dcache.WriteReq_misses::total 7014697 # number of WriteReq misses 2209system.cpu1.dcache.SoftPFReq_misses::cpu1.data 658076 # number of SoftPFReq misses 2210system.cpu1.dcache.SoftPFReq_misses::total 658076 # number of SoftPFReq misses 2211system.cpu1.dcache.WriteLineReq_misses::cpu1.data 445973 # number of WriteLineReq misses 2212system.cpu1.dcache.WriteLineReq_misses::total 445973 # number of WriteLineReq misses 2213system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 278553 # number of LoadLockedReq misses 2214system.cpu1.dcache.LoadLockedReq_misses::total 278553 # number of LoadLockedReq misses 2215system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193453 # number of StoreCondReq misses 2216system.cpu1.dcache.StoreCondReq_misses::total 193453 # number of StoreCondReq misses 2217system.cpu1.dcache.demand_misses::cpu1.data 13832986 # number of demand (read+write) misses 2218system.cpu1.dcache.demand_misses::total 13832986 # number of demand (read+write) misses 2219system.cpu1.dcache.overall_misses::cpu1.data 14491062 # number of overall misses 2220system.cpu1.dcache.overall_misses::total 14491062 # number of overall misses 2221system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 93736923500 # number of ReadReq miss cycles 2222system.cpu1.dcache.ReadReq_miss_latency::total 93736923500 # number of ReadReq miss cycles 2223system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 131113304741 # number of WriteReq miss cycles 2224system.cpu1.dcache.WriteReq_miss_latency::total 131113304741 # number of WriteReq miss cycles 2225system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11858807099 # number of WriteLineReq miss cycles 2226system.cpu1.dcache.WriteLineReq_miss_latency::total 11858807099 # number of WriteLineReq miss cycles 2227system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4107251000 # number of LoadLockedReq miss cycles 2228system.cpu1.dcache.LoadLockedReq_miss_latency::total 4107251000 # number of LoadLockedReq miss cycles 2229system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4806521000 # number of StoreCondReq miss cycles 2230system.cpu1.dcache.StoreCondReq_miss_latency::total 4806521000 # number of StoreCondReq miss cycles 2231system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3714500 # number of StoreCondFailReq miss cycles 2232system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3714500 # number of StoreCondFailReq miss cycles 2233system.cpu1.dcache.demand_miss_latency::cpu1.data 236709035340 # number of demand (read+write) miss cycles 2234system.cpu1.dcache.demand_miss_latency::total 236709035340 # number of demand (read+write) miss cycles 2235system.cpu1.dcache.overall_miss_latency::cpu1.data 236709035340 # number of overall miss cycles 2236system.cpu1.dcache.overall_miss_latency::total 236709035340 # number of overall miss cycles 2237system.cpu1.dcache.ReadReq_accesses::cpu1.data 82838741 # number of ReadReq accesses(hits+misses) 2238system.cpu1.dcache.ReadReq_accesses::total 82838741 # number of ReadReq accesses(hits+misses) 2239system.cpu1.dcache.WriteReq_accesses::cpu1.data 71125310 # number of WriteReq accesses(hits+misses) 2240system.cpu1.dcache.WriteReq_accesses::total 71125310 # number of WriteReq accesses(hits+misses) 2241system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 828504 # number of SoftPFReq accesses(hits+misses) 2242system.cpu1.dcache.SoftPFReq_accesses::total 828504 # number of SoftPFReq accesses(hits+misses) 2243system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 497137 # number of WriteLineReq accesses(hits+misses) 2244system.cpu1.dcache.WriteLineReq_accesses::total 497137 # number of WriteLineReq accesses(hits+misses) 2245system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1979471 # number of LoadLockedReq accesses(hits+misses) 2246system.cpu1.dcache.LoadLockedReq_accesses::total 1979471 # number of LoadLockedReq accesses(hits+misses) 2247system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1935209 # number of StoreCondReq accesses(hits+misses) 2248system.cpu1.dcache.StoreCondReq_accesses::total 1935209 # number of StoreCondReq accesses(hits+misses) 2249system.cpu1.dcache.demand_accesses::cpu1.data 154461188 # number of demand (read+write) accesses 2250system.cpu1.dcache.demand_accesses::total 154461188 # number of demand (read+write) accesses 2251system.cpu1.dcache.overall_accesses::cpu1.data 155289692 # number of overall (read+write) accesses 2252system.cpu1.dcache.overall_accesses::total 155289692 # number of overall (read+write) accesses 2253system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.076924 # miss rate for ReadReq accesses 2254system.cpu1.dcache.ReadReq_miss_rate::total 0.076924 # miss rate for ReadReq accesses 2255system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.098624 # miss rate for WriteReq accesses 2256system.cpu1.dcache.WriteReq_miss_rate::total 0.098624 # miss rate for WriteReq accesses 2257system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.794294 # miss rate for SoftPFReq accesses 2258system.cpu1.dcache.SoftPFReq_miss_rate::total 0.794294 # miss rate for SoftPFReq accesses 2259system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.897083 # miss rate for WriteLineReq accesses 2260system.cpu1.dcache.WriteLineReq_miss_rate::total 0.897083 # miss rate for WriteLineReq accesses 2261system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.140721 # miss rate for LoadLockedReq accesses 2262system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.140721 # miss rate for LoadLockedReq accesses 2263system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099965 # miss rate for StoreCondReq accesses 2264system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099965 # miss rate for StoreCondReq accesses 2265system.cpu1.dcache.demand_miss_rate::cpu1.data 0.089556 # miss rate for demand accesses 2266system.cpu1.dcache.demand_miss_rate::total 0.089556 # miss rate for demand accesses 2267system.cpu1.dcache.overall_miss_rate::cpu1.data 0.093316 # miss rate for overall accesses 2268system.cpu1.dcache.overall_miss_rate::total 0.093316 # miss rate for overall accesses 2269system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14710.024346 # average ReadReq miss latency 2270system.cpu1.dcache.ReadReq_avg_miss_latency::total 14710.024346 # average ReadReq miss latency 2271system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18691.228536 # average WriteReq miss latency 2272system.cpu1.dcache.WriteReq_avg_miss_latency::total 18691.228536 # average WriteReq miss latency 2273system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 26590.863346 # average WriteLineReq miss latency 2274system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 26590.863346 # average WriteLineReq miss latency 2275system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14744.953384 # average LoadLockedReq miss latency 2276system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14744.953384 # average LoadLockedReq miss latency 2277system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24845.936739 # average StoreCondReq miss latency 2278system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24845.936739 # average StoreCondReq miss latency |
| 2303system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2304system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 2279system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2280system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 2305system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20509.150755 # average overall miss latency 2306system.cpu1.dcache.demand_avg_miss_latency::total 20509.150755 # average overall miss latency 2307system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19567.831458 # average overall miss latency 2308system.cpu1.dcache.overall_avg_miss_latency::total 19567.831458 # average overall miss latency 2309system.cpu1.dcache.blocked_cycles::no_mshrs 5568492 # number of cycles access was blocked 2310system.cpu1.dcache.blocked_cycles::no_targets 28779495 # number of cycles access was blocked 2311system.cpu1.dcache.blocked::no_mshrs 387755 # number of cycles access was blocked 2312system.cpu1.dcache.blocked::no_targets 802381 # number of cycles access was blocked 2313system.cpu1.dcache.avg_blocked_cycles::no_mshrs 14.360852 # average number of cycles each access was blocked 2314system.cpu1.dcache.avg_blocked_cycles::no_targets 35.867618 # average number of cycles each access was blocked 2315system.cpu1.dcache.writebacks::writebacks 6040976 # number of writebacks 2316system.cpu1.dcache.writebacks::total 6040976 # number of writebacks 2317system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3573916 # number of ReadReq MSHR hits 2318system.cpu1.dcache.ReadReq_mshr_hits::total 3573916 # number of ReadReq MSHR hits 2319system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6375716 # number of WriteReq MSHR hits 2320system.cpu1.dcache.WriteReq_mshr_hits::total 6375716 # number of WriteReq MSHR hits 2321system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3475 # number of WriteLineReq MSHR hits 2322system.cpu1.dcache.WriteLineReq_mshr_hits::total 3475 # number of WriteLineReq MSHR hits 2323system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 153685 # number of LoadLockedReq MSHR hits 2324system.cpu1.dcache.LoadLockedReq_mshr_hits::total 153685 # number of LoadLockedReq MSHR hits 2325system.cpu1.dcache.demand_mshr_hits::cpu1.data 9953107 # number of demand (read+write) MSHR hits 2326system.cpu1.dcache.demand_mshr_hits::total 9953107 # number of demand (read+write) MSHR hits 2327system.cpu1.dcache.overall_mshr_hits::cpu1.data 9953107 # number of overall MSHR hits 2328system.cpu1.dcache.overall_mshr_hits::total 9953107 # number of overall MSHR hits 2329system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3510974 # number of ReadReq MSHR misses 2330system.cpu1.dcache.ReadReq_mshr_misses::total 3510974 # number of ReadReq MSHR misses 2331system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1512210 # number of WriteReq MSHR misses 2332system.cpu1.dcache.WriteReq_mshr_misses::total 1512210 # number of WriteReq MSHR misses 2333system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 742708 # number of SoftPFReq MSHR misses 2334system.cpu1.dcache.SoftPFReq_mshr_misses::total 742708 # number of SoftPFReq MSHR misses 2335system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 465037 # number of WriteLineReq MSHR misses 2336system.cpu1.dcache.WriteLineReq_mshr_misses::total 465037 # number of WriteLineReq MSHR misses 2337system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 147938 # number of LoadLockedReq MSHR misses 2338system.cpu1.dcache.LoadLockedReq_mshr_misses::total 147938 # number of LoadLockedReq MSHR misses 2339system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202156 # number of StoreCondReq MSHR misses 2340system.cpu1.dcache.StoreCondReq_mshr_misses::total 202156 # number of StoreCondReq MSHR misses 2341system.cpu1.dcache.demand_mshr_misses::cpu1.data 5488221 # number of demand (read+write) MSHR misses 2342system.cpu1.dcache.demand_mshr_misses::total 5488221 # number of demand (read+write) MSHR misses 2343system.cpu1.dcache.overall_mshr_misses::cpu1.data 6230929 # number of overall MSHR misses 2344system.cpu1.dcache.overall_mshr_misses::total 6230929 # number of overall MSHR misses 2345system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 18701 # number of ReadReq MSHR uncacheable 2346system.cpu1.dcache.ReadReq_mshr_uncacheable::total 18701 # number of ReadReq MSHR uncacheable 2347system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 17029 # number of WriteReq MSHR uncacheable 2348system.cpu1.dcache.WriteReq_mshr_uncacheable::total 17029 # number of WriteReq MSHR uncacheable 2349system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 35730 # number of overall MSHR uncacheable misses 2350system.cpu1.dcache.overall_mshr_uncacheable_misses::total 35730 # number of overall MSHR uncacheable misses 2351system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 55262810500 # number of ReadReq MSHR miss cycles 2352system.cpu1.dcache.ReadReq_mshr_miss_latency::total 55262810500 # number of ReadReq MSHR miss cycles 2353system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 37074565990 # number of WriteReq MSHR miss cycles 2354system.cpu1.dcache.WriteReq_mshr_miss_latency::total 37074565990 # number of WriteReq MSHR miss cycles 2355system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 18477747500 # number of SoftPFReq MSHR miss cycles 2356system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 18477747500 # number of SoftPFReq MSHR miss cycles 2357system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 19695654974 # number of WriteLineReq MSHR miss cycles 2358system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 19695654974 # number of WriteLineReq MSHR miss cycles 2359system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 2170800500 # number of LoadLockedReq MSHR miss cycles 2360system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 2170800500 # number of LoadLockedReq MSHR miss cycles 2361system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5507478500 # number of StoreCondReq MSHR miss cycles 2362system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5507478500 # number of StoreCondReq MSHR miss cycles 2363system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3449000 # number of StoreCondFailReq MSHR miss cycles 2364system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3449000 # number of StoreCondFailReq MSHR miss cycles 2365system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 112033031464 # number of demand (read+write) MSHR miss cycles 2366system.cpu1.dcache.demand_mshr_miss_latency::total 112033031464 # number of demand (read+write) MSHR miss cycles 2367system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 130510778964 # number of overall MSHR miss cycles 2368system.cpu1.dcache.overall_mshr_miss_latency::total 130510778964 # number of overall MSHR miss cycles 2369system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3038329000 # number of ReadReq MSHR uncacheable cycles 2370system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3038329000 # number of ReadReq MSHR uncacheable cycles 2371system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3038329000 # number of overall MSHR uncacheable cycles 2372system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3038329000 # number of overall MSHR uncacheable cycles 2373system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037513 # mshr miss rate for ReadReq accesses 2374system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037513 # mshr miss rate for ReadReq accesses 2375system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018759 # mshr miss rate for WriteReq accesses 2376system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018759 # mshr miss rate for WriteReq accesses 2377system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.788317 # mshr miss rate for SoftPFReq accesses 2378system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.788317 # mshr miss rate for SoftPFReq accesses 2379system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.760920 # mshr miss rate for WriteLineReq accesses 2380system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.760920 # mshr miss rate for WriteLineReq accesses 2381system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066167 # mshr miss rate for LoadLockedReq accesses 2382system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066167 # mshr miss rate for LoadLockedReq accesses 2383system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092443 # mshr miss rate for StoreCondReq accesses 2384system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092443 # mshr miss rate for StoreCondReq accesses 2385system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031394 # mshr miss rate for demand accesses 2386system.cpu1.dcache.demand_mshr_miss_rate::total 0.031394 # mshr miss rate for demand accesses 2387system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035451 # mshr miss rate for overall accesses 2388system.cpu1.dcache.overall_mshr_miss_rate::total 0.035451 # mshr miss rate for overall accesses 2389system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15740.022712 # average ReadReq mshr miss latency 2390system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15740.022712 # average ReadReq mshr miss latency 2391system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24516.810489 # average WriteReq mshr miss latency 2392system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24516.810489 # average WriteReq mshr miss latency 2393system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24878.885780 # average SoftPFReq mshr miss latency 2394system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24878.885780 # average SoftPFReq mshr miss latency 2395system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 42352.877242 # average WriteLineReq mshr miss latency 2396system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 42352.877242 # average WriteLineReq mshr miss latency 2397system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14673.718044 # average LoadLockedReq mshr miss latency 2398system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14673.718044 # average LoadLockedReq mshr miss latency 2399system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27243.705356 # average StoreCondReq mshr miss latency 2400system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27243.705356 # average StoreCondReq mshr miss latency | 2281system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17111.926184 # average overall miss latency 2282system.cpu1.dcache.demand_avg_miss_latency::total 17111.926184 # average overall miss latency 2283system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16334.830072 # average overall miss latency 2284system.cpu1.dcache.overall_avg_miss_latency::total 16334.830072 # average overall miss latency 2285system.cpu1.dcache.blocked_cycles::no_mshrs 3137293 # number of cycles access was blocked 2286system.cpu1.dcache.blocked_cycles::no_targets 21285332 # number of cycles access was blocked 2287system.cpu1.dcache.blocked::no_mshrs 376632 # number of cycles access was blocked 2288system.cpu1.dcache.blocked::no_targets 706469 # number of cycles access was blocked 2289system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.329863 # average number of cycles each access was blocked 2290system.cpu1.dcache.avg_blocked_cycles::no_targets 30.129180 # average number of cycles each access was blocked 2291system.cpu1.dcache.writebacks::writebacks 5420571 # number of writebacks 2292system.cpu1.dcache.writebacks::total 5420571 # number of writebacks 2293system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3225514 # number of ReadReq MSHR hits 2294system.cpu1.dcache.ReadReq_mshr_hits::total 3225514 # number of ReadReq MSHR hits 2295system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5658563 # number of WriteReq MSHR hits 2296system.cpu1.dcache.WriteReq_mshr_hits::total 5658563 # number of WriteReq MSHR hits 2297system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3397 # number of WriteLineReq MSHR hits 2298system.cpu1.dcache.WriteLineReq_mshr_hits::total 3397 # number of WriteLineReq MSHR hits 2299system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 142581 # number of LoadLockedReq MSHR hits 2300system.cpu1.dcache.LoadLockedReq_mshr_hits::total 142581 # number of LoadLockedReq MSHR hits 2301system.cpu1.dcache.demand_mshr_hits::cpu1.data 8887474 # number of demand (read+write) MSHR hits 2302system.cpu1.dcache.demand_mshr_hits::total 8887474 # number of demand (read+write) MSHR hits 2303system.cpu1.dcache.overall_mshr_hits::cpu1.data 8887474 # number of overall MSHR hits 2304system.cpu1.dcache.overall_mshr_hits::total 8887474 # number of overall MSHR hits 2305system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3146802 # number of ReadReq MSHR misses 2306system.cpu1.dcache.ReadReq_mshr_misses::total 3146802 # number of ReadReq MSHR misses 2307system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1356134 # number of WriteReq MSHR misses 2308system.cpu1.dcache.WriteReq_mshr_misses::total 1356134 # number of WriteReq MSHR misses 2309system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 657988 # number of SoftPFReq MSHR misses 2310system.cpu1.dcache.SoftPFReq_mshr_misses::total 657988 # number of SoftPFReq MSHR misses 2311system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 442576 # number of WriteLineReq MSHR misses 2312system.cpu1.dcache.WriteLineReq_mshr_misses::total 442576 # number of WriteLineReq MSHR misses 2313system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 135972 # number of LoadLockedReq MSHR misses 2314system.cpu1.dcache.LoadLockedReq_mshr_misses::total 135972 # number of LoadLockedReq MSHR misses 2315system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193443 # number of StoreCondReq MSHR misses 2316system.cpu1.dcache.StoreCondReq_mshr_misses::total 193443 # number of StoreCondReq MSHR misses 2317system.cpu1.dcache.demand_mshr_misses::cpu1.data 4945512 # number of demand (read+write) MSHR misses 2318system.cpu1.dcache.demand_mshr_misses::total 4945512 # number of demand (read+write) MSHR misses 2319system.cpu1.dcache.overall_mshr_misses::cpu1.data 5603500 # number of overall MSHR misses 2320system.cpu1.dcache.overall_mshr_misses::total 5603500 # number of overall MSHR misses 2321system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6118 # number of ReadReq MSHR uncacheable 2322system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6118 # number of ReadReq MSHR uncacheable 2323system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 6183 # number of WriteReq MSHR uncacheable 2324system.cpu1.dcache.WriteReq_mshr_uncacheable::total 6183 # number of WriteReq MSHR uncacheable 2325system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 12301 # number of overall MSHR uncacheable misses 2326system.cpu1.dcache.overall_mshr_uncacheable_misses::total 12301 # number of overall MSHR uncacheable misses 2327system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43613350000 # number of ReadReq MSHR miss cycles 2328system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43613350000 # number of ReadReq MSHR miss cycles 2329system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26794309953 # number of WriteReq MSHR miss cycles 2330system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26794309953 # number of WriteReq MSHR miss cycles 2331system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14059014500 # number of SoftPFReq MSHR miss cycles 2332system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14059014500 # number of SoftPFReq MSHR miss cycles 2333system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 11316204599 # number of WriteLineReq MSHR miss cycles 2334system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 11316204599 # number of WriteLineReq MSHR miss cycles 2335system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1866790500 # number of LoadLockedReq MSHR miss cycles 2336system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1866790500 # number of LoadLockedReq MSHR miss cycles 2337system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4613147000 # number of StoreCondReq MSHR miss cycles 2338system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4613147000 # number of StoreCondReq MSHR miss cycles 2339system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3645500 # number of StoreCondFailReq MSHR miss cycles 2340system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3645500 # number of StoreCondFailReq MSHR miss cycles 2341system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 81723864552 # number of demand (read+write) MSHR miss cycles 2342system.cpu1.dcache.demand_mshr_miss_latency::total 81723864552 # number of demand (read+write) MSHR miss cycles 2343system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 95782879052 # number of overall MSHR miss cycles 2344system.cpu1.dcache.overall_mshr_miss_latency::total 95782879052 # number of overall MSHR miss cycles 2345system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 749898500 # number of ReadReq MSHR uncacheable cycles 2346system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 749898500 # number of ReadReq MSHR uncacheable cycles 2347system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 749898500 # number of overall MSHR uncacheable cycles 2348system.cpu1.dcache.overall_mshr_uncacheable_latency::total 749898500 # number of overall MSHR uncacheable cycles 2349system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037987 # mshr miss rate for ReadReq accesses 2350system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037987 # mshr miss rate for ReadReq accesses 2351system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019067 # mshr miss rate for WriteReq accesses 2352system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019067 # mshr miss rate for WriteReq accesses 2353system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.794188 # mshr miss rate for SoftPFReq accesses 2354system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.794188 # mshr miss rate for SoftPFReq accesses 2355system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.890250 # mshr miss rate for WriteLineReq accesses 2356system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.890250 # mshr miss rate for WriteLineReq accesses 2357system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068691 # mshr miss rate for LoadLockedReq accesses 2358system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068691 # mshr miss rate for LoadLockedReq accesses 2359system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099960 # mshr miss rate for StoreCondReq accesses 2360system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099960 # mshr miss rate for StoreCondReq accesses 2361system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032018 # mshr miss rate for demand accesses 2362system.cpu1.dcache.demand_mshr_miss_rate::total 0.032018 # mshr miss rate for demand accesses 2363system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036084 # mshr miss rate for overall accesses 2364system.cpu1.dcache.overall_mshr_miss_rate::total 0.036084 # mshr miss rate for overall accesses 2365system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13859.578709 # average ReadReq mshr miss latency 2366system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13859.578709 # average ReadReq mshr miss latency 2367system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19757.863126 # average WriteReq mshr miss latency 2368system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19757.863126 # average WriteReq mshr miss latency 2369system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21366.673100 # average SoftPFReq mshr miss latency 2370system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21366.673100 # average SoftPFReq mshr miss latency 2371system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 25568.952223 # average WriteLineReq mshr miss latency 2372system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 25568.952223 # average WriteLineReq mshr miss latency 2373system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13729.227341 # average LoadLockedReq mshr miss latency 2374system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13729.227341 # average LoadLockedReq mshr miss latency 2375system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23847.577839 # average StoreCondReq mshr miss latency 2376system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23847.577839 # average StoreCondReq mshr miss latency |
| 2401system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2402system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 2377system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2378system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 2403system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20413.360079 # average overall mshr miss latency 2404system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20413.360079 # average overall mshr miss latency 2405system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20945.637314 # average overall mshr miss latency 2406system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20945.637314 # average overall mshr miss latency 2407system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162468.798460 # average ReadReq mshr uncacheable latency 2408system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162468.798460 # average ReadReq mshr uncacheable latency 2409system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 85035.796250 # average overall mshr uncacheable latency 2410system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 85035.796250 # average overall mshr uncacheable latency 2411system.cpu1.icache.tags.replacements 6229961 # number of replacements 2412system.cpu1.icache.tags.tagsinuse 501.669710 # Cycle average of tags in use 2413system.cpu1.icache.tags.total_refs 220025292 # Total number of references to valid blocks. 2414system.cpu1.icache.tags.sampled_refs 6230473 # Sample count of references to valid blocks. 2415system.cpu1.icache.tags.avg_refs 35.314380 # Average number of references to valid blocks. 2416system.cpu1.icache.tags.warmup_cycle 8522353535000 # Cycle when the warmup percentage was hit. 2417system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.669710 # Average occupied blocks per requestor 2418system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979824 # Average percentage of cache occupancy 2419system.cpu1.icache.tags.occ_percent::total 0.979824 # Average percentage of cache occupancy | 2379system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16524.854161 # average overall mshr miss latency 2380system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16524.854161 # average overall mshr miss latency 2381system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17093.402169 # average overall mshr miss latency 2382system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17093.402169 # average overall mshr miss latency 2383system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122572.491010 # average ReadReq mshr uncacheable latency 2384system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 122572.491010 # average ReadReq mshr uncacheable latency 2385system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 60962.401431 # average overall mshr uncacheable latency 2386system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 60962.401431 # average overall mshr uncacheable latency 2387system.cpu1.icache.tags.replacements 5742782 # number of replacements 2388system.cpu1.icache.tags.tagsinuse 501.536552 # Cycle average of tags in use 2389system.cpu1.icache.tags.total_refs 193871102 # Total number of references to valid blocks. 2390system.cpu1.icache.tags.sampled_refs 5743294 # Sample count of references to valid blocks. 2391system.cpu1.icache.tags.avg_refs 33.756082 # Average number of references to valid blocks. 2392system.cpu1.icache.tags.warmup_cycle 8517126060000 # Cycle when the warmup percentage was hit. 2393system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.536552 # Average occupied blocks per requestor 2394system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979564 # Average percentage of cache occupancy 2395system.cpu1.icache.tags.occ_percent::total 0.979564 # Average percentage of cache occupancy |
| 2420system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 2396system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 2421system.cpu1.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 2422system.cpu1.icache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id 2423system.cpu1.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id | 2397system.cpu1.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id 2398system.cpu1.icache.tags.age_task_id_blocks_1024::1 396 # Occupied blocks per task id 2399system.cpu1.icache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id |
| 2424system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 2400system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 2425system.cpu1.icache.tags.tag_accesses 459465626 # Number of tag accesses 2426system.cpu1.icache.tags.data_accesses 459465626 # Number of data accesses 2427system.cpu1.icache.ReadReq_hits::cpu1.inst 220025292 # number of ReadReq hits 2428system.cpu1.icache.ReadReq_hits::total 220025292 # number of ReadReq hits 2429system.cpu1.icache.demand_hits::cpu1.inst 220025292 # number of demand (read+write) hits 2430system.cpu1.icache.demand_hits::total 220025292 # number of demand (read+write) hits 2431system.cpu1.icache.overall_hits::cpu1.inst 220025292 # number of overall hits 2432system.cpu1.icache.overall_hits::total 220025292 # number of overall hits 2433system.cpu1.icache.ReadReq_misses::cpu1.inst 6592262 # number of ReadReq misses 2434system.cpu1.icache.ReadReq_misses::total 6592262 # number of ReadReq misses 2435system.cpu1.icache.demand_misses::cpu1.inst 6592262 # number of demand (read+write) misses 2436system.cpu1.icache.demand_misses::total 6592262 # number of demand (read+write) misses 2437system.cpu1.icache.overall_misses::cpu1.inst 6592262 # number of overall misses 2438system.cpu1.icache.overall_misses::total 6592262 # number of overall misses 2439system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 74756974451 # number of ReadReq miss cycles 2440system.cpu1.icache.ReadReq_miss_latency::total 74756974451 # number of ReadReq miss cycles 2441system.cpu1.icache.demand_miss_latency::cpu1.inst 74756974451 # number of demand (read+write) miss cycles 2442system.cpu1.icache.demand_miss_latency::total 74756974451 # number of demand (read+write) miss cycles 2443system.cpu1.icache.overall_miss_latency::cpu1.inst 74756974451 # number of overall miss cycles 2444system.cpu1.icache.overall_miss_latency::total 74756974451 # number of overall miss cycles 2445system.cpu1.icache.ReadReq_accesses::cpu1.inst 226617554 # number of ReadReq accesses(hits+misses) 2446system.cpu1.icache.ReadReq_accesses::total 226617554 # number of ReadReq accesses(hits+misses) 2447system.cpu1.icache.demand_accesses::cpu1.inst 226617554 # number of demand (read+write) accesses 2448system.cpu1.icache.demand_accesses::total 226617554 # number of demand (read+write) accesses 2449system.cpu1.icache.overall_accesses::cpu1.inst 226617554 # number of overall (read+write) accesses 2450system.cpu1.icache.overall_accesses::total 226617554 # number of overall (read+write) accesses 2451system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029090 # miss rate for ReadReq accesses 2452system.cpu1.icache.ReadReq_miss_rate::total 0.029090 # miss rate for ReadReq accesses 2453system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029090 # miss rate for demand accesses 2454system.cpu1.icache.demand_miss_rate::total 0.029090 # miss rate for demand accesses 2455system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029090 # miss rate for overall accesses 2456system.cpu1.icache.overall_miss_rate::total 0.029090 # miss rate for overall accesses 2457system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11340.109730 # average ReadReq miss latency 2458system.cpu1.icache.ReadReq_avg_miss_latency::total 11340.109730 # average ReadReq miss latency 2459system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11340.109730 # average overall miss latency 2460system.cpu1.icache.demand_avg_miss_latency::total 11340.109730 # average overall miss latency 2461system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11340.109730 # average overall miss latency 2462system.cpu1.icache.overall_avg_miss_latency::total 11340.109730 # average overall miss latency 2463system.cpu1.icache.blocked_cycles::no_mshrs 11528745 # number of cycles access was blocked 2464system.cpu1.icache.blocked_cycles::no_targets 835 # number of cycles access was blocked 2465system.cpu1.icache.blocked::no_mshrs 773545 # number of cycles access was blocked 2466system.cpu1.icache.blocked::no_targets 6 # number of cycles access was blocked 2467system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.903781 # average number of cycles each access was blocked 2468system.cpu1.icache.avg_blocked_cycles::no_targets 139.166667 # average number of cycles each access was blocked 2469system.cpu1.icache.writebacks::writebacks 6229961 # number of writebacks 2470system.cpu1.icache.writebacks::total 6229961 # number of writebacks 2471system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 361744 # number of ReadReq MSHR hits 2472system.cpu1.icache.ReadReq_mshr_hits::total 361744 # number of ReadReq MSHR hits 2473system.cpu1.icache.demand_mshr_hits::cpu1.inst 361744 # number of demand (read+write) MSHR hits 2474system.cpu1.icache.demand_mshr_hits::total 361744 # number of demand (read+write) MSHR hits 2475system.cpu1.icache.overall_mshr_hits::cpu1.inst 361744 # number of overall MSHR hits 2476system.cpu1.icache.overall_mshr_hits::total 361744 # number of overall MSHR hits 2477system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 6230518 # number of ReadReq MSHR misses 2478system.cpu1.icache.ReadReq_mshr_misses::total 6230518 # number of ReadReq MSHR misses 2479system.cpu1.icache.demand_mshr_misses::cpu1.inst 6230518 # number of demand (read+write) MSHR misses 2480system.cpu1.icache.demand_mshr_misses::total 6230518 # number of demand (read+write) MSHR misses 2481system.cpu1.icache.overall_mshr_misses::cpu1.inst 6230518 # number of overall MSHR misses 2482system.cpu1.icache.overall_mshr_misses::total 6230518 # number of overall MSHR misses | 2401system.cpu1.icache.tags.tag_accesses 405638078 # Number of tag accesses 2402system.cpu1.icache.tags.data_accesses 405638078 # Number of data accesses 2403system.cpu1.icache.ReadReq_hits::cpu1.inst 193871102 # number of ReadReq hits 2404system.cpu1.icache.ReadReq_hits::total 193871102 # number of ReadReq hits 2405system.cpu1.icache.demand_hits::cpu1.inst 193871102 # number of demand (read+write) hits 2406system.cpu1.icache.demand_hits::total 193871102 # number of demand (read+write) hits 2407system.cpu1.icache.overall_hits::cpu1.inst 193871102 # number of overall hits 2408system.cpu1.icache.overall_hits::total 193871102 # number of overall hits 2409system.cpu1.icache.ReadReq_misses::cpu1.inst 6076268 # number of ReadReq misses 2410system.cpu1.icache.ReadReq_misses::total 6076268 # number of ReadReq misses 2411system.cpu1.icache.demand_misses::cpu1.inst 6076268 # number of demand (read+write) misses 2412system.cpu1.icache.demand_misses::total 6076268 # number of demand (read+write) misses 2413system.cpu1.icache.overall_misses::cpu1.inst 6076268 # number of overall misses 2414system.cpu1.icache.overall_misses::total 6076268 # number of overall misses 2415system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 64119298557 # number of ReadReq miss cycles 2416system.cpu1.icache.ReadReq_miss_latency::total 64119298557 # number of ReadReq miss cycles 2417system.cpu1.icache.demand_miss_latency::cpu1.inst 64119298557 # number of demand (read+write) miss cycles 2418system.cpu1.icache.demand_miss_latency::total 64119298557 # number of demand (read+write) miss cycles 2419system.cpu1.icache.overall_miss_latency::cpu1.inst 64119298557 # number of overall miss cycles 2420system.cpu1.icache.overall_miss_latency::total 64119298557 # number of overall miss cycles 2421system.cpu1.icache.ReadReq_accesses::cpu1.inst 199947370 # number of ReadReq accesses(hits+misses) 2422system.cpu1.icache.ReadReq_accesses::total 199947370 # number of ReadReq accesses(hits+misses) 2423system.cpu1.icache.demand_accesses::cpu1.inst 199947370 # number of demand (read+write) accesses 2424system.cpu1.icache.demand_accesses::total 199947370 # number of demand (read+write) accesses 2425system.cpu1.icache.overall_accesses::cpu1.inst 199947370 # number of overall (read+write) accesses 2426system.cpu1.icache.overall_accesses::total 199947370 # number of overall (read+write) accesses 2427system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030389 # miss rate for ReadReq accesses 2428system.cpu1.icache.ReadReq_miss_rate::total 0.030389 # miss rate for ReadReq accesses 2429system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030389 # miss rate for demand accesses 2430system.cpu1.icache.demand_miss_rate::total 0.030389 # miss rate for demand accesses 2431system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030389 # miss rate for overall accesses 2432system.cpu1.icache.overall_miss_rate::total 0.030389 # miss rate for overall accesses 2433system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10552.414501 # average ReadReq miss latency 2434system.cpu1.icache.ReadReq_avg_miss_latency::total 10552.414501 # average ReadReq miss latency 2435system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10552.414501 # average overall miss latency 2436system.cpu1.icache.demand_avg_miss_latency::total 10552.414501 # average overall miss latency 2437system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10552.414501 # average overall miss latency 2438system.cpu1.icache.overall_avg_miss_latency::total 10552.414501 # average overall miss latency 2439system.cpu1.icache.blocked_cycles::no_mshrs 9320412 # number of cycles access was blocked 2440system.cpu1.icache.blocked_cycles::no_targets 212 # number of cycles access was blocked 2441system.cpu1.icache.blocked::no_mshrs 713481 # number of cycles access was blocked 2442system.cpu1.icache.blocked::no_targets 3 # number of cycles access was blocked 2443system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.063294 # average number of cycles each access was blocked 2444system.cpu1.icache.avg_blocked_cycles::no_targets 70.666667 # average number of cycles each access was blocked 2445system.cpu1.icache.writebacks::writebacks 5742782 # number of writebacks 2446system.cpu1.icache.writebacks::total 5742782 # number of writebacks 2447system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 332930 # number of ReadReq MSHR hits 2448system.cpu1.icache.ReadReq_mshr_hits::total 332930 # number of ReadReq MSHR hits 2449system.cpu1.icache.demand_mshr_hits::cpu1.inst 332930 # number of demand (read+write) MSHR hits 2450system.cpu1.icache.demand_mshr_hits::total 332930 # number of demand (read+write) MSHR hits 2451system.cpu1.icache.overall_mshr_hits::cpu1.inst 332930 # number of overall MSHR hits 2452system.cpu1.icache.overall_mshr_hits::total 332930 # number of overall MSHR hits 2453system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5743338 # number of ReadReq MSHR misses 2454system.cpu1.icache.ReadReq_mshr_misses::total 5743338 # number of ReadReq MSHR misses 2455system.cpu1.icache.demand_mshr_misses::cpu1.inst 5743338 # number of demand (read+write) MSHR misses 2456system.cpu1.icache.demand_mshr_misses::total 5743338 # number of demand (read+write) MSHR misses 2457system.cpu1.icache.overall_mshr_misses::cpu1.inst 5743338 # number of overall MSHR misses 2458system.cpu1.icache.overall_mshr_misses::total 5743338 # number of overall MSHR misses |
| 2483system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 2484system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable 2485system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 2486system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses | 2459system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 2460system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable 2461system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 2462system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses |
| 2487system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 67349232950 # number of ReadReq MSHR miss cycles 2488system.cpu1.icache.ReadReq_mshr_miss_latency::total 67349232950 # number of ReadReq MSHR miss cycles 2489system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 67349232950 # number of demand (read+write) MSHR miss cycles 2490system.cpu1.icache.demand_mshr_miss_latency::total 67349232950 # number of demand (read+write) MSHR miss cycles 2491system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 67349232950 # number of overall MSHR miss cycles 2492system.cpu1.icache.overall_mshr_miss_latency::total 67349232950 # number of overall MSHR miss cycles 2493system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8957498 # number of ReadReq MSHR uncacheable cycles 2494system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8957498 # number of ReadReq MSHR uncacheable cycles 2495system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8957498 # number of overall MSHR uncacheable cycles 2496system.cpu1.icache.overall_mshr_uncacheable_latency::total 8957498 # number of overall MSHR uncacheable cycles 2497system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027494 # mshr miss rate for ReadReq accesses 2498system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027494 # mshr miss rate for ReadReq accesses 2499system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027494 # mshr miss rate for demand accesses 2500system.cpu1.icache.demand_mshr_miss_rate::total 0.027494 # mshr miss rate for demand accesses 2501system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027494 # mshr miss rate for overall accesses 2502system.cpu1.icache.overall_mshr_miss_rate::total 0.027494 # mshr miss rate for overall accesses 2503system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10809.572005 # average ReadReq mshr miss latency 2504system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10809.572005 # average ReadReq mshr miss latency 2505system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10809.572005 # average overall mshr miss latency 2506system.cpu1.icache.demand_avg_mshr_miss_latency::total 10809.572005 # average overall mshr miss latency 2507system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10809.572005 # average overall mshr miss latency 2508system.cpu1.icache.overall_avg_mshr_miss_latency::total 10809.572005 # average overall mshr miss latency 2509system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133694 # average ReadReq mshr uncacheable latency 2510system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133694 # average ReadReq mshr uncacheable latency 2511system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133694 # average overall mshr uncacheable latency 2512system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133694 # average overall mshr uncacheable latency 2513system.cpu1.l2cache.prefetcher.num_hwpf_issued 8304723 # number of hwpf issued 2514system.cpu1.l2cache.prefetcher.pfIdentified 8311187 # number of prefetch candidates identified 2515system.cpu1.l2cache.prefetcher.pfBufferHit 5839 # number of redundant prefetches already in prefetch queue | 2463system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 58166889552 # number of ReadReq MSHR miss cycles 2464system.cpu1.icache.ReadReq_mshr_miss_latency::total 58166889552 # number of ReadReq MSHR miss cycles 2465system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 58166889552 # number of demand (read+write) MSHR miss cycles 2466system.cpu1.icache.demand_mshr_miss_latency::total 58166889552 # number of demand (read+write) MSHR miss cycles 2467system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58166889552 # number of overall MSHR miss cycles 2468system.cpu1.icache.overall_mshr_miss_latency::total 58166889552 # number of overall MSHR miss cycles 2469system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6789498 # number of ReadReq MSHR uncacheable cycles 2470system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6789498 # number of ReadReq MSHR uncacheable cycles 2471system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6789498 # number of overall MSHR uncacheable cycles 2472system.cpu1.icache.overall_mshr_uncacheable_latency::total 6789498 # number of overall MSHR uncacheable cycles 2473system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028724 # mshr miss rate for ReadReq accesses 2474system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028724 # mshr miss rate for ReadReq accesses 2475system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028724 # mshr miss rate for demand accesses 2476system.cpu1.icache.demand_mshr_miss_rate::total 0.028724 # mshr miss rate for demand accesses 2477system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028724 # mshr miss rate for overall accesses 2478system.cpu1.icache.overall_mshr_miss_rate::total 0.028724 # mshr miss rate for overall accesses 2479system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average ReadReq mshr miss latency 2480system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10127.714850 # average ReadReq mshr miss latency 2481system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency 2482system.cpu1.icache.demand_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency 2483system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency 2484system.cpu1.icache.overall_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency 2485system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average ReadReq mshr uncacheable latency 2486system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101335.791045 # average ReadReq mshr uncacheable latency 2487system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average overall mshr uncacheable latency 2488system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101335.791045 # average overall mshr uncacheable latency 2489system.cpu1.l2cache.prefetcher.num_hwpf_issued 7416585 # number of hwpf issued 2490system.cpu1.l2cache.prefetcher.pfIdentified 7422175 # number of prefetch candidates identified 2491system.cpu1.l2cache.prefetcher.pfBufferHit 5069 # number of redundant prefetches already in prefetch queue |
| 2516system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2517system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 2492system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2493system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 2518system.cpu1.l2cache.prefetcher.pfSpanPage 1024317 # number of prefetches not generated due to page crossing 2519system.cpu1.l2cache.tags.replacements 2528309 # number of replacements 2520system.cpu1.l2cache.tags.tagsinuse 13413.609149 # Cycle average of tags in use 2521system.cpu1.l2cache.tags.total_refs 18251408 # Total number of references to valid blocks. 2522system.cpu1.l2cache.tags.sampled_refs 2544361 # Sample count of references to valid blocks. 2523system.cpu1.l2cache.tags.avg_refs 7.173278 # Average number of references to valid blocks. 2524system.cpu1.l2cache.tags.warmup_cycle 9891515003500 # Cycle when the warmup percentage was hit. 2525system.cpu1.l2cache.tags.occ_blocks::writebacks 12660.361458 # Average occupied blocks per requestor 2526system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 61.649049 # Average occupied blocks per requestor 2527system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 73.939309 # Average occupied blocks per requestor 2528system.cpu1.l2cache.tags.occ_blocks::cpu1.data 0.000012 # Average occupied blocks per requestor 2529system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 617.659322 # Average occupied blocks per requestor 2530system.cpu1.l2cache.tags.occ_percent::writebacks 0.772727 # Average percentage of cache occupancy 2531system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003763 # Average percentage of cache occupancy 2532system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004513 # Average percentage of cache occupancy 2533system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.000000 # Average percentage of cache occupancy 2534system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.037699 # Average percentage of cache occupancy 2535system.cpu1.l2cache.tags.occ_percent::total 0.818702 # Average percentage of cache occupancy 2536system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1288 # Occupied blocks per task id 2537system.cpu1.l2cache.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id 2538system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14705 # Occupied blocks per task id 2539system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id 2540system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 259 # Occupied blocks per task id 2541system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 581 # Occupied blocks per task id 2542system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 431 # Occupied blocks per task id 2543system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 38 # Occupied blocks per task id 2544system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 2545system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id 2546system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 2547system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1409 # Occupied blocks per task id 2548system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5268 # Occupied blocks per task id 2549system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4214 # Occupied blocks per task id 2550system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3711 # Occupied blocks per task id 2551system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078613 # Percentage of cache occupancy per task id 2552system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id 2553system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.897522 # Percentage of cache occupancy per task id 2554system.cpu1.l2cache.tags.tag_accesses 421641447 # Number of tag accesses 2555system.cpu1.l2cache.tags.data_accesses 421641447 # Number of data accesses 2556system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 670573 # number of ReadReq hits 2557system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 201040 # number of ReadReq hits 2558system.cpu1.l2cache.ReadReq_hits::total 871613 # number of ReadReq hits 2559system.cpu1.l2cache.WritebackDirty_hits::writebacks 3790012 # number of WritebackDirty hits 2560system.cpu1.l2cache.WritebackDirty_hits::total 3790012 # number of WritebackDirty hits 2561system.cpu1.l2cache.WritebackClean_hits::writebacks 8479233 # number of WritebackClean hits 2562system.cpu1.l2cache.WritebackClean_hits::total 8479233 # number of WritebackClean hits 2563system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 992 # number of UpgradeReq hits 2564system.cpu1.l2cache.UpgradeReq_hits::total 992 # number of UpgradeReq hits 2565system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 7 # number of SCUpgradeReq hits 2566system.cpu1.l2cache.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits 2567system.cpu1.l2cache.ReadExReq_hits::cpu1.data 953658 # number of ReadExReq hits 2568system.cpu1.l2cache.ReadExReq_hits::total 953658 # number of ReadExReq hits 2569system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5605859 # number of ReadCleanReq hits 2570system.cpu1.l2cache.ReadCleanReq_hits::total 5605859 # number of ReadCleanReq hits 2571system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3317239 # number of ReadSharedReq hits 2572system.cpu1.l2cache.ReadSharedReq_hits::total 3317239 # number of ReadSharedReq hits 2573system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 173754 # number of InvalidateReq hits 2574system.cpu1.l2cache.InvalidateReq_hits::total 173754 # number of InvalidateReq hits 2575system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 670573 # number of demand (read+write) hits 2576system.cpu1.l2cache.demand_hits::cpu1.itb.walker 201040 # number of demand (read+write) hits 2577system.cpu1.l2cache.demand_hits::cpu1.inst 5605859 # number of demand (read+write) hits 2578system.cpu1.l2cache.demand_hits::cpu1.data 4270897 # number of demand (read+write) hits 2579system.cpu1.l2cache.demand_hits::total 10748369 # number of demand (read+write) hits 2580system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 670573 # number of overall hits 2581system.cpu1.l2cache.overall_hits::cpu1.itb.walker 201040 # number of overall hits 2582system.cpu1.l2cache.overall_hits::cpu1.inst 5605859 # number of overall hits 2583system.cpu1.l2cache.overall_hits::cpu1.data 4270897 # number of overall hits 2584system.cpu1.l2cache.overall_hits::total 10748369 # number of overall hits 2585system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 13735 # number of ReadReq misses 2586system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10344 # number of ReadReq misses 2587system.cpu1.l2cache.ReadReq_misses::total 24079 # number of ReadReq misses 2588system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses 2589system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses | 2494system.cpu1.l2cache.prefetcher.pfSpanPage 930081 # number of prefetches not generated due to page crossing 2495system.cpu1.l2cache.tags.replacements 2216875 # number of replacements 2496system.cpu1.l2cache.tags.tagsinuse 13443.573819 # Cycle average of tags in use 2497system.cpu1.l2cache.tags.total_refs 16807540 # Total number of references to valid blocks. 2498system.cpu1.l2cache.tags.sampled_refs 2232789 # Sample count of references to valid blocks. 2499system.cpu1.l2cache.tags.avg_refs 7.527599 # Average number of references to valid blocks. 2500system.cpu1.l2cache.tags.warmup_cycle 9871196159000 # Cycle when the warmup percentage was hit. 2501system.cpu1.l2cache.tags.occ_blocks::writebacks 12560.451650 # Average occupied blocks per requestor 2502system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 62.875087 # Average occupied blocks per requestor 2503system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 63.205555 # Average occupied blocks per requestor 2504system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 757.041527 # Average occupied blocks per requestor 2505system.cpu1.l2cache.tags.occ_percent::writebacks 0.766629 # Average percentage of cache occupancy 2506system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003838 # Average percentage of cache occupancy 2507system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003858 # Average percentage of cache occupancy 2508system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.046206 # Average percentage of cache occupancy 2509system.cpu1.l2cache.tags.occ_percent::total 0.820531 # Average percentage of cache occupancy 2510system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1320 # Occupied blocks per task id 2511system.cpu1.l2cache.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id 2512system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14527 # Occupied blocks per task id 2513system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 25 # Occupied blocks per task id 2514system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 72 # Occupied blocks per task id 2515system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 117 # Occupied blocks per task id 2516system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 681 # Occupied blocks per task id 2517system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 425 # Occupied blocks per task id 2518system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 2519system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id 2520system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id 2521system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 2522system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id 2523system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1030 # Occupied blocks per task id 2524system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5623 # Occupied blocks per task id 2525system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4561 # Occupied blocks per task id 2526system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3143 # Occupied blocks per task id 2527system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080566 # Percentage of cache occupancy per task id 2528system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004089 # Percentage of cache occupancy per task id 2529system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.886658 # Percentage of cache occupancy per task id 2530system.cpu1.l2cache.tags.tag_accesses 383680582 # Number of tag accesses 2531system.cpu1.l2cache.tags.data_accesses 383680582 # Number of data accesses 2532system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 591753 # number of ReadReq hits 2533system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 193382 # number of ReadReq hits 2534system.cpu1.l2cache.ReadReq_hits::total 785135 # number of ReadReq hits 2535system.cpu1.l2cache.WritebackDirty_hits::writebacks 3353025 # number of WritebackDirty hits 2536system.cpu1.l2cache.WritebackDirty_hits::total 3353025 # number of WritebackDirty hits 2537system.cpu1.l2cache.WritebackClean_hits::writebacks 7809020 # number of WritebackClean hits 2538system.cpu1.l2cache.WritebackClean_hits::total 7809020 # number of WritebackClean hits 2539system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 779 # number of UpgradeReq hits 2540system.cpu1.l2cache.UpgradeReq_hits::total 779 # number of UpgradeReq hits 2541system.cpu1.l2cache.ReadExReq_hits::cpu1.data 872441 # number of ReadExReq hits 2542system.cpu1.l2cache.ReadExReq_hits::total 872441 # number of ReadExReq hits 2543system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5195235 # number of ReadCleanReq hits 2544system.cpu1.l2cache.ReadCleanReq_hits::total 5195235 # number of ReadCleanReq hits 2545system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2967964 # number of ReadSharedReq hits 2546system.cpu1.l2cache.ReadSharedReq_hits::total 2967964 # number of ReadSharedReq hits 2547system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 177430 # number of InvalidateReq hits 2548system.cpu1.l2cache.InvalidateReq_hits::total 177430 # number of InvalidateReq hits 2549system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 591753 # number of demand (read+write) hits 2550system.cpu1.l2cache.demand_hits::cpu1.itb.walker 193382 # number of demand (read+write) hits 2551system.cpu1.l2cache.demand_hits::cpu1.inst 5195235 # number of demand (read+write) hits 2552system.cpu1.l2cache.demand_hits::cpu1.data 3840405 # number of demand (read+write) hits 2553system.cpu1.l2cache.demand_hits::total 9820775 # number of demand (read+write) hits 2554system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 591753 # number of overall hits 2555system.cpu1.l2cache.overall_hits::cpu1.itb.walker 193382 # number of overall hits 2556system.cpu1.l2cache.overall_hits::cpu1.inst 5195235 # number of overall hits 2557system.cpu1.l2cache.overall_hits::cpu1.data 3840405 # number of overall hits 2558system.cpu1.l2cache.overall_hits::total 9820775 # number of overall hits 2559system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 13125 # number of ReadReq misses 2560system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9784 # number of ReadReq misses 2561system.cpu1.l2cache.ReadReq_misses::total 22909 # number of ReadReq misses 2562system.cpu1.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses 2563system.cpu1.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses |
| 2590system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 2591system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses | 2564system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 2565system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses |
| 2592system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 250358 # number of UpgradeReq misses 2593system.cpu1.l2cache.UpgradeReq_misses::total 250358 # number of UpgradeReq misses 2594system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 202146 # number of SCUpgradeReq misses 2595system.cpu1.l2cache.SCUpgradeReq_misses::total 202146 # number of SCUpgradeReq misses 2596system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses 2597system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 2598system.cpu1.l2cache.ReadExReq_misses::cpu1.data 315483 # number of ReadExReq misses 2599system.cpu1.l2cache.ReadExReq_misses::total 315483 # number of ReadExReq misses 2600system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 624615 # number of ReadCleanReq misses 2601system.cpu1.l2cache.ReadCleanReq_misses::total 624615 # number of ReadCleanReq misses 2602system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1080990 # number of ReadSharedReq misses 2603system.cpu1.l2cache.ReadSharedReq_misses::total 1080990 # number of ReadSharedReq misses 2604system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 289367 # number of InvalidateReq misses 2605system.cpu1.l2cache.InvalidateReq_misses::total 289367 # number of InvalidateReq misses 2606system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 13735 # number of demand (read+write) misses 2607system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10344 # number of demand (read+write) misses 2608system.cpu1.l2cache.demand_misses::cpu1.inst 624615 # number of demand (read+write) misses 2609system.cpu1.l2cache.demand_misses::cpu1.data 1396473 # number of demand (read+write) misses 2610system.cpu1.l2cache.demand_misses::total 2045167 # number of demand (read+write) misses 2611system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 13735 # number of overall misses 2612system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10344 # number of overall misses 2613system.cpu1.l2cache.overall_misses::cpu1.inst 624615 # number of overall misses 2614system.cpu1.l2cache.overall_misses::cpu1.data 1396473 # number of overall misses 2615system.cpu1.l2cache.overall_misses::total 2045167 # number of overall misses 2616system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 769352500 # number of ReadReq miss cycles 2617system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 652492500 # number of ReadReq miss cycles 2618system.cpu1.l2cache.ReadReq_miss_latency::total 1421845000 # number of ReadReq miss cycles 2619system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3726618500 # number of UpgradeReq miss cycles 2620system.cpu1.l2cache.UpgradeReq_miss_latency::total 3726618500 # number of UpgradeReq miss cycles 2621system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 2054743500 # number of SCUpgradeReq miss cycles 2622system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 2054743500 # number of SCUpgradeReq miss cycles 2623system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3377498 # number of SCUpgradeFailReq miss cycles 2624system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3377498 # number of SCUpgradeFailReq miss cycles 2625system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 18580326500 # number of ReadExReq miss cycles 2626system.cpu1.l2cache.ReadExReq_miss_latency::total 18580326500 # number of ReadExReq miss cycles 2627system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24049432000 # number of ReadCleanReq miss cycles 2628system.cpu1.l2cache.ReadCleanReq_miss_latency::total 24049432000 # number of ReadCleanReq miss cycles 2629system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 47157033477 # number of ReadSharedReq miss cycles 2630system.cpu1.l2cache.ReadSharedReq_miss_latency::total 47157033477 # number of ReadSharedReq miss cycles 2631system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 475628500 # number of InvalidateReq miss cycles 2632system.cpu1.l2cache.InvalidateReq_miss_latency::total 475628500 # number of InvalidateReq miss cycles 2633system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 769352500 # number of demand (read+write) miss cycles 2634system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 652492500 # number of demand (read+write) miss cycles 2635system.cpu1.l2cache.demand_miss_latency::cpu1.inst 24049432000 # number of demand (read+write) miss cycles 2636system.cpu1.l2cache.demand_miss_latency::cpu1.data 65737359977 # number of demand (read+write) miss cycles 2637system.cpu1.l2cache.demand_miss_latency::total 91208636977 # number of demand (read+write) miss cycles 2638system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 769352500 # number of overall miss cycles 2639system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 652492500 # number of overall miss cycles 2640system.cpu1.l2cache.overall_miss_latency::cpu1.inst 24049432000 # number of overall miss cycles 2641system.cpu1.l2cache.overall_miss_latency::cpu1.data 65737359977 # number of overall miss cycles 2642system.cpu1.l2cache.overall_miss_latency::total 91208636977 # number of overall miss cycles 2643system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 684308 # number of ReadReq accesses(hits+misses) 2644system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 211384 # number of ReadReq accesses(hits+misses) 2645system.cpu1.l2cache.ReadReq_accesses::total 895692 # number of ReadReq accesses(hits+misses) 2646system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3790013 # number of WritebackDirty accesses(hits+misses) 2647system.cpu1.l2cache.WritebackDirty_accesses::total 3790013 # number of WritebackDirty accesses(hits+misses) 2648system.cpu1.l2cache.WritebackClean_accesses::writebacks 8479234 # number of WritebackClean accesses(hits+misses) 2649system.cpu1.l2cache.WritebackClean_accesses::total 8479234 # number of WritebackClean accesses(hits+misses) 2650system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 251350 # number of UpgradeReq accesses(hits+misses) 2651system.cpu1.l2cache.UpgradeReq_accesses::total 251350 # number of UpgradeReq accesses(hits+misses) 2652system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 202153 # number of SCUpgradeReq accesses(hits+misses) 2653system.cpu1.l2cache.SCUpgradeReq_accesses::total 202153 # number of SCUpgradeReq accesses(hits+misses) 2654system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 2655system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 2656system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1269141 # number of ReadExReq accesses(hits+misses) 2657system.cpu1.l2cache.ReadExReq_accesses::total 1269141 # number of ReadExReq accesses(hits+misses) 2658system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 6230474 # number of ReadCleanReq accesses(hits+misses) 2659system.cpu1.l2cache.ReadCleanReq_accesses::total 6230474 # number of ReadCleanReq accesses(hits+misses) 2660system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4398229 # number of ReadSharedReq accesses(hits+misses) 2661system.cpu1.l2cache.ReadSharedReq_accesses::total 4398229 # number of ReadSharedReq accesses(hits+misses) 2662system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 463121 # number of InvalidateReq accesses(hits+misses) 2663system.cpu1.l2cache.InvalidateReq_accesses::total 463121 # number of InvalidateReq accesses(hits+misses) 2664system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 684308 # number of demand (read+write) accesses 2665system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 211384 # number of demand (read+write) accesses 2666system.cpu1.l2cache.demand_accesses::cpu1.inst 6230474 # number of demand (read+write) accesses 2667system.cpu1.l2cache.demand_accesses::cpu1.data 5667370 # number of demand (read+write) accesses 2668system.cpu1.l2cache.demand_accesses::total 12793536 # number of demand (read+write) accesses 2669system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 684308 # number of overall (read+write) accesses 2670system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 211384 # number of overall (read+write) accesses 2671system.cpu1.l2cache.overall_accesses::cpu1.inst 6230474 # number of overall (read+write) accesses 2672system.cpu1.l2cache.overall_accesses::cpu1.data 5667370 # number of overall (read+write) accesses 2673system.cpu1.l2cache.overall_accesses::total 12793536 # number of overall (read+write) accesses 2674system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020071 # miss rate for ReadReq accesses 2675system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048935 # miss rate for ReadReq accesses 2676system.cpu1.l2cache.ReadReq_miss_rate::total 0.026883 # miss rate for ReadReq accesses 2677system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses 2678system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses | 2566system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 227942 # number of UpgradeReq misses 2567system.cpu1.l2cache.UpgradeReq_misses::total 227942 # number of UpgradeReq misses 2568system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 193439 # number of SCUpgradeReq misses 2569system.cpu1.l2cache.SCUpgradeReq_misses::total 193439 # number of SCUpgradeReq misses 2570system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses 2571system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 2572system.cpu1.l2cache.ReadExReq_misses::cpu1.data 262152 # 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number of demand (read+write) misses 2584system.cpu1.l2cache.demand_misses::total 1803642 # number of demand (read+write) misses 2585system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 13125 # number of overall misses 2586system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9784 # number of overall misses 2587system.cpu1.l2cache.overall_misses::cpu1.inst 548077 # number of overall misses 2588system.cpu1.l2cache.overall_misses::cpu1.data 1232656 # number of overall misses 2589system.cpu1.l2cache.overall_misses::total 1803642 # number of overall misses 2590system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 561719500 # number of ReadReq miss cycles 2591system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 455404000 # number of ReadReq miss cycles 2592system.cpu1.l2cache.ReadReq_miss_latency::total 1017123500 # number of ReadReq miss cycles 2593system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 1976830000 # number of UpgradeReq miss cycles 2594system.cpu1.l2cache.UpgradeReq_miss_latency::total 1976830000 # number of UpgradeReq miss cycles 2595system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1436047000 # number of SCUpgradeReq miss cycles 2596system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1436047000 # number of SCUpgradeReq miss cycles 2597system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3542000 # number of SCUpgradeFailReq miss cycles 2598system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3542000 # number of SCUpgradeFailReq miss cycles 2599system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12377259499 # number of ReadExReq miss cycles 2600system.cpu1.l2cache.ReadExReq_miss_latency::total 12377259499 # number of ReadExReq miss cycles 2601system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 18066070500 # number of ReadCleanReq miss cycles 2602system.cpu1.l2cache.ReadCleanReq_miss_latency::total 18066070500 # number of ReadCleanReq miss cycles 2603system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 33827571986 # number of ReadSharedReq miss cycles 2604system.cpu1.l2cache.ReadSharedReq_miss_latency::total 33827571986 # number of ReadSharedReq miss cycles 2605system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 317775500 # number of InvalidateReq miss cycles 2606system.cpu1.l2cache.InvalidateReq_miss_latency::total 317775500 # number of InvalidateReq miss cycles 2607system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 561719500 # number of demand (read+write) miss cycles 2608system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 455404000 # number of demand (read+write) miss cycles 2609system.cpu1.l2cache.demand_miss_latency::cpu1.inst 18066070500 # number of demand (read+write) miss cycles 2610system.cpu1.l2cache.demand_miss_latency::cpu1.data 46204831485 # number of demand (read+write) miss cycles 2611system.cpu1.l2cache.demand_miss_latency::total 65288025485 # number of demand (read+write) miss cycles 2612system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 561719500 # number of overall miss cycles 2613system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 455404000 # number of overall miss cycles 2614system.cpu1.l2cache.overall_miss_latency::cpu1.inst 18066070500 # number of overall miss cycles 2615system.cpu1.l2cache.overall_miss_latency::cpu1.data 46204831485 # number of overall miss cycles 2616system.cpu1.l2cache.overall_miss_latency::total 65288025485 # number of overall miss cycles 2617system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 604878 # number of ReadReq accesses(hits+misses) 2618system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 203166 # number of ReadReq accesses(hits+misses) 2619system.cpu1.l2cache.ReadReq_accesses::total 808044 # number of ReadReq accesses(hits+misses) 2620system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3353027 # number of WritebackDirty accesses(hits+misses) 2621system.cpu1.l2cache.WritebackDirty_accesses::total 3353027 # number of WritebackDirty accesses(hits+misses) 2622system.cpu1.l2cache.WritebackClean_accesses::writebacks 7809021 # number of WritebackClean accesses(hits+misses) 2623system.cpu1.l2cache.WritebackClean_accesses::total 7809021 # number of WritebackClean accesses(hits+misses) 2624system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 228721 # number of UpgradeReq accesses(hits+misses) 2625system.cpu1.l2cache.UpgradeReq_accesses::total 228721 # number of UpgradeReq accesses(hits+misses) 2626system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 193439 # number of SCUpgradeReq accesses(hits+misses) 2627system.cpu1.l2cache.SCUpgradeReq_accesses::total 193439 # number of SCUpgradeReq accesses(hits+misses) 2628system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 2629system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 2630system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1134593 # number of ReadExReq accesses(hits+misses) 2631system.cpu1.l2cache.ReadExReq_accesses::total 1134593 # number of ReadExReq accesses(hits+misses) 2632system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5743312 # number of ReadCleanReq accesses(hits+misses) 2633system.cpu1.l2cache.ReadCleanReq_accesses::total 5743312 # number of ReadCleanReq accesses(hits+misses) 2634system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3938468 # number of ReadSharedReq accesses(hits+misses) 2635system.cpu1.l2cache.ReadSharedReq_accesses::total 3938468 # number of ReadSharedReq accesses(hits+misses) 2636system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 441012 # number of InvalidateReq accesses(hits+misses) 2637system.cpu1.l2cache.InvalidateReq_accesses::total 441012 # number of InvalidateReq accesses(hits+misses) 2638system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 604878 # number of demand (read+write) accesses 2639system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 203166 # number of demand (read+write) accesses 2640system.cpu1.l2cache.demand_accesses::cpu1.inst 5743312 # number of demand (read+write) accesses 2641system.cpu1.l2cache.demand_accesses::cpu1.data 5073061 # number of demand (read+write) accesses 2642system.cpu1.l2cache.demand_accesses::total 11624417 # number of demand (read+write) accesses 2643system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 604878 # number of overall (read+write) accesses 2644system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 203166 # number of overall (read+write) accesses 2645system.cpu1.l2cache.overall_accesses::cpu1.inst 5743312 # number of overall (read+write) accesses 2646system.cpu1.l2cache.overall_accesses::cpu1.data 5073061 # number of overall (read+write) accesses 2647system.cpu1.l2cache.overall_accesses::total 11624417 # number of overall (read+write) accesses 2648system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021699 # miss rate for ReadReq accesses 2649system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048158 # miss rate for ReadReq accesses 2650system.cpu1.l2cache.ReadReq_miss_rate::total 0.028351 # miss rate for ReadReq accesses 2651system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses 2652system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses |
| 2679system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 2680system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses | 2653system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 2654system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses |
| 2681system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.996053 # miss rate for UpgradeReq accesses 2682system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.996053 # miss rate for UpgradeReq accesses 2683system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999965 # miss rate for SCUpgradeReq accesses 2684system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999965 # miss rate for SCUpgradeReq accesses | 2655system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.996594 # miss rate for UpgradeReq accesses 2656system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.996594 # miss rate for UpgradeReq accesses 2657system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2658system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses |
| 2685system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2686system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 2659system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2660system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 2687system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.248580 # miss rate for ReadExReq accesses 2688system.cpu1.l2cache.ReadExReq_miss_rate::total 0.248580 # miss rate for ReadExReq accesses 2689system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.100252 # miss rate for ReadCleanReq accesses 2690system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.100252 # miss rate for ReadCleanReq accesses 2691system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.245778 # miss rate for ReadSharedReq accesses 2692system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.245778 # miss rate for ReadSharedReq accesses 2693system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.624819 # miss rate for InvalidateReq accesses 2694system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.624819 # miss rate for InvalidateReq accesses 2695system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020071 # miss rate for demand accesses 2696system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048935 # miss rate for demand accesses 2697system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.100252 # miss rate for demand accesses 2698system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.246406 # miss rate for demand accesses 2699system.cpu1.l2cache.demand_miss_rate::total 0.159859 # miss rate for demand accesses 2700system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020071 # miss rate for overall accesses 2701system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048935 # miss rate for overall accesses 2702system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.100252 # miss rate for overall accesses 2703system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.246406 # miss rate for overall accesses 2704system.cpu1.l2cache.overall_miss_rate::total 0.159859 # miss rate for overall accesses 2705system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 56014.015289 # average ReadReq miss latency 2706system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 63079.321346 # average ReadReq miss latency 2707system.cpu1.l2cache.ReadReq_avg_miss_latency::total 59049.171477 # average ReadReq miss latency 2708system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14885.158453 # average UpgradeReq miss latency 2709system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14885.158453 # average UpgradeReq miss latency 2710system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10164.650797 # average SCUpgradeReq miss latency 2711system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10164.650797 # average SCUpgradeReq miss latency 2712system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1125832.666667 # average SCUpgradeFailReq miss latency 2713system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1125832.666667 # average SCUpgradeFailReq miss latency 2714system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 58894.858043 # average ReadExReq miss latency 2715system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 58894.858043 # average ReadExReq miss latency 2716system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38502.808930 # average ReadCleanReq miss latency 2717system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38502.808930 # average ReadCleanReq miss latency 2718system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 43623.931282 # average ReadSharedReq miss latency 2719system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 43623.931282 # average ReadSharedReq miss latency 2720system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1643.686046 # average InvalidateReq miss latency 2721system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1643.686046 # average InvalidateReq miss latency 2722system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 56014.015289 # average overall miss latency 2723system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 63079.321346 # average overall miss latency 2724system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38502.808930 # average overall miss latency 2725system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 47073.849603 # average overall miss latency 2726system.cpu1.l2cache.demand_avg_miss_latency::total 44597.158558 # average overall miss latency 2727system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 56014.015289 # average overall miss latency 2728system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 63079.321346 # average overall miss latency 2729system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38502.808930 # average overall miss latency 2730system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 47073.849603 # average overall miss latency 2731system.cpu1.l2cache.overall_avg_miss_latency::total 44597.158558 # average overall miss latency 2732system.cpu1.l2cache.blocked_cycles::no_mshrs 1476 # number of cycles access was blocked | 2661system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.231054 # miss rate for ReadExReq accesses 2662system.cpu1.l2cache.ReadExReq_miss_rate::total 0.231054 # miss rate for ReadExReq accesses 2663system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.095429 # miss rate for ReadCleanReq accesses 2664system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.095429 # miss rate for ReadCleanReq accesses 2665system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.246417 # miss rate for ReadSharedReq accesses 2666system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.246417 # miss rate for ReadSharedReq accesses 2667system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.597675 # miss rate for InvalidateReq accesses 2668system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.597675 # miss rate for InvalidateReq accesses 2669system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021699 # miss rate for demand accesses 2670system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048158 # miss rate for demand accesses 2671system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.095429 # miss rate for demand accesses 2672system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.242981 # miss rate for demand accesses 2673system.cpu1.l2cache.demand_miss_rate::total 0.155160 # miss rate for demand accesses 2674system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021699 # miss rate for overall accesses 2675system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048158 # miss rate for overall accesses 2676system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.095429 # miss rate for overall accesses 2677system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.242981 # miss rate for overall accesses 2678system.cpu1.l2cache.overall_miss_rate::total 0.155160 # miss rate for overall accesses 2679system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 42797.676190 # average ReadReq miss latency 2680system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 46545.789043 # average ReadReq miss latency 2681system.cpu1.l2cache.ReadReq_avg_miss_latency::total 44398.424200 # average ReadReq miss latency 2682system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 8672.513183 # average UpgradeReq miss latency 2683system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 8672.513183 # average UpgradeReq miss latency 2684system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 7423.771835 # average SCUpgradeReq miss latency 2685system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 7423.771835 # average SCUpgradeReq miss latency 2686system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 885500 # average SCUpgradeFailReq miss latency 2687system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 885500 # average SCUpgradeFailReq miss latency 2688system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 47214.057108 # average ReadExReq miss latency 2689system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 47214.057108 # average ReadExReq miss latency 2690system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 32962.650321 # average ReadCleanReq miss latency 2691system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 32962.650321 # average ReadCleanReq miss latency 2692system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 34855.674975 # average ReadSharedReq miss latency 2693system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 34855.674975 # average ReadSharedReq miss latency 2694system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1205.603949 # average InvalidateReq miss latency 2695system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1205.603949 # average InvalidateReq miss latency 2696system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 42797.676190 # average overall miss latency 2697system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 46545.789043 # average overall miss latency 2698system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32962.650321 # average overall miss latency 2699system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37483.962667 # average overall miss latency 2700system.cpu1.l2cache.demand_avg_miss_latency::total 36197.884882 # average overall miss latency 2701system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 42797.676190 # average overall miss latency 2702system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 46545.789043 # average overall miss latency 2703system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32962.650321 # average overall miss latency 2704system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37483.962667 # average overall miss latency 2705system.cpu1.l2cache.overall_avg_miss_latency::total 36197.884882 # average overall miss latency 2706system.cpu1.l2cache.blocked_cycles::no_mshrs 860 # number of cycles access was blocked |
| 2733system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2707system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2734system.cpu1.l2cache.blocked::no_mshrs 14 # number of cycles access was blocked | 2708system.cpu1.l2cache.blocked::no_mshrs 17 # number of cycles access was blocked |
| 2735system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 2709system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 2736system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 105.428571 # average number of cycles each access was blocked | 2710system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 50.588235 # average number of cycles each access was blocked |
| 2737system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2711system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2738system.cpu1.l2cache.unused_prefetches 50570 # number of HardPF blocks evicted w/o reference 2739system.cpu1.l2cache.writebacks::writebacks 1373649 # number of writebacks 2740system.cpu1.l2cache.writebacks::total 1373649 # number of writebacks 2741system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 2 # number of ReadReq MSHR hits 2742system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 9 # number of ReadReq MSHR hits 2743system.cpu1.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits 2744system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 59817 # number of ReadExReq MSHR hits 2745system.cpu1.l2cache.ReadExReq_mshr_hits::total 59817 # number of ReadExReq MSHR hits 2746system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 6475 # number of ReadSharedReq MSHR hits 2747system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 6475 # number of ReadSharedReq MSHR hits 2748system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 7 # number of InvalidateReq MSHR hits 2749system.cpu1.l2cache.InvalidateReq_mshr_hits::total 7 # number of InvalidateReq MSHR hits 2750system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 2 # number of demand (read+write) MSHR hits 2751system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 9 # number of demand (read+write) MSHR hits 2752system.cpu1.l2cache.demand_mshr_hits::cpu1.data 66292 # number of demand (read+write) MSHR hits 2753system.cpu1.l2cache.demand_mshr_hits::total 66303 # number of demand (read+write) MSHR hits 2754system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 2 # number of overall MSHR hits 2755system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 9 # number of overall MSHR hits 2756system.cpu1.l2cache.overall_mshr_hits::cpu1.data 66292 # number of overall MSHR hits 2757system.cpu1.l2cache.overall_mshr_hits::total 66303 # number of overall MSHR hits 2758system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 13733 # number of ReadReq MSHR misses 2759system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10335 # number of ReadReq MSHR misses 2760system.cpu1.l2cache.ReadReq_mshr_misses::total 24068 # number of ReadReq MSHR misses 2761system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses 2762system.cpu1.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses | 2712system.cpu1.l2cache.unused_prefetches 44363 # number of HardPF blocks evicted w/o reference 2713system.cpu1.l2cache.writebacks::writebacks 1196648 # number of writebacks 2714system.cpu1.l2cache.writebacks::total 1196648 # number of writebacks 2715system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits 2716system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 8 # number of ReadReq MSHR hits 2717system.cpu1.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits 2718system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 12956 # number of ReadExReq MSHR hits 2719system.cpu1.l2cache.ReadExReq_mshr_hits::total 12956 # number of ReadExReq MSHR hits 2720system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4132 # number of ReadSharedReq MSHR hits 2721system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4132 # number of ReadSharedReq MSHR hits 2722system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 5 # number of InvalidateReq MSHR hits 2723system.cpu1.l2cache.InvalidateReq_mshr_hits::total 5 # number of InvalidateReq MSHR hits 2724system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 2725system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 8 # number of demand (read+write) MSHR hits 2726system.cpu1.l2cache.demand_mshr_hits::cpu1.data 17088 # number of demand (read+write) MSHR hits 2727system.cpu1.l2cache.demand_mshr_hits::total 17097 # number of demand (read+write) MSHR hits 2728system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 2729system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 8 # number of overall MSHR hits 2730system.cpu1.l2cache.overall_mshr_hits::cpu1.data 17088 # number of overall MSHR hits 2731system.cpu1.l2cache.overall_mshr_hits::total 17097 # number of overall MSHR hits 2732system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 13124 # number of ReadReq MSHR misses 2733system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9776 # number of ReadReq MSHR misses 2734system.cpu1.l2cache.ReadReq_mshr_misses::total 22900 # number of ReadReq MSHR misses 2735system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 2 # number of WritebackDirty MSHR misses 2736system.cpu1.l2cache.WritebackDirty_mshr_misses::total 2 # number of WritebackDirty MSHR misses |
| 2763system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 2764system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses | 2737system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 2738system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses |
| 2765system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 868323 # number of HardPFReq MSHR misses 2766system.cpu1.l2cache.HardPFReq_mshr_misses::total 868323 # number of HardPFReq MSHR misses 2767system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 250358 # number of UpgradeReq MSHR misses 2768system.cpu1.l2cache.UpgradeReq_mshr_misses::total 250358 # number of UpgradeReq MSHR misses 2769system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 202146 # number of SCUpgradeReq MSHR misses 2770system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 202146 # number of SCUpgradeReq MSHR misses 2771system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses 2772system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 2773system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 255666 # number of ReadExReq MSHR misses 2774system.cpu1.l2cache.ReadExReq_mshr_misses::total 255666 # number of ReadExReq MSHR misses 2775system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 624615 # number of ReadCleanReq MSHR misses 2776system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 624615 # number of ReadCleanReq MSHR misses 2777system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 1074515 # number of ReadSharedReq MSHR misses 2778system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 1074515 # number of ReadSharedReq MSHR misses 2779system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 289360 # number of InvalidateReq MSHR misses 2780system.cpu1.l2cache.InvalidateReq_mshr_misses::total 289360 # number of InvalidateReq MSHR misses 2781system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 13733 # number of demand (read+write) MSHR misses 2782system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10335 # number of demand (read+write) MSHR misses 2783system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 624615 # number of demand (read+write) MSHR misses 2784system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1330181 # number of demand (read+write) MSHR misses 2785system.cpu1.l2cache.demand_mshr_misses::total 1978864 # number of demand (read+write) MSHR misses 2786system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 13733 # number of overall MSHR misses 2787system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10335 # number of overall MSHR misses 2788system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 624615 # number of overall MSHR misses 2789system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1330181 # number of overall MSHR misses 2790system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 868323 # number of overall MSHR misses 2791system.cpu1.l2cache.overall_mshr_misses::total 2847187 # number of overall MSHR misses | 2739system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 773530 # number of HardPFReq MSHR misses 2740system.cpu1.l2cache.HardPFReq_mshr_misses::total 773530 # number of HardPFReq MSHR misses 2741system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 227942 # number of UpgradeReq MSHR misses 2742system.cpu1.l2cache.UpgradeReq_mshr_misses::total 227942 # number of UpgradeReq MSHR misses 2743system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 193439 # number of SCUpgradeReq MSHR misses 2744system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 193439 # number of SCUpgradeReq MSHR misses 2745system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses 2746system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 2747system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 249196 # number of ReadExReq MSHR misses 2748system.cpu1.l2cache.ReadExReq_mshr_misses::total 249196 # number of ReadExReq MSHR misses 2749system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 548077 # number of ReadCleanReq MSHR misses 2750system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 548077 # number of ReadCleanReq MSHR misses 2751system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 966372 # number of ReadSharedReq MSHR misses 2752system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 966372 # number of ReadSharedReq MSHR misses 2753system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 263577 # number of InvalidateReq MSHR misses 2754system.cpu1.l2cache.InvalidateReq_mshr_misses::total 263577 # number of InvalidateReq MSHR misses 2755system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 13124 # number of demand (read+write) MSHR misses 2756system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9776 # number of demand (read+write) MSHR misses 2757system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 548077 # number of demand (read+write) MSHR misses 2758system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1215568 # number of demand (read+write) MSHR misses 2759system.cpu1.l2cache.demand_mshr_misses::total 1786545 # number of demand (read+write) MSHR misses 2760system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 13124 # number of overall MSHR misses 2761system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9776 # number of overall MSHR misses 2762system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 548077 # number of overall MSHR misses 2763system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1215568 # number of overall MSHR misses 2764system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 773530 # number of overall MSHR misses 2765system.cpu1.l2cache.overall_mshr_misses::total 2560075 # number of overall MSHR misses |
| 2792system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable | 2766system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable |
| 2793system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 18701 # number of ReadReq MSHR uncacheable 2794system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 18768 # number of ReadReq MSHR uncacheable 2795system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 17029 # number of WriteReq MSHR uncacheable 2796system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 17029 # number of WriteReq MSHR uncacheable | 2767system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6118 # number of ReadReq MSHR uncacheable 2768system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 6185 # number of ReadReq MSHR uncacheable 2769system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 6183 # number of WriteReq MSHR uncacheable 2770system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 6183 # number of WriteReq MSHR uncacheable |
| 2797system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses | 2771system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses |
| 2798system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 35730 # number of overall MSHR uncacheable misses 2799system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 35797 # number of overall MSHR uncacheable misses 2800system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 686821000 # number of ReadReq MSHR miss cycles 2801system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 590353500 # number of ReadReq MSHR miss cycles 2802system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1277174500 # number of ReadReq MSHR miss cycles 2803system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 65644901114 # number of HardPFReq MSHR miss cycles 2804system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 65644901114 # number of HardPFReq MSHR miss cycles 2805system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7861561998 # number of UpgradeReq MSHR miss cycles 2806system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7861561998 # number of UpgradeReq MSHR miss cycles 2807system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3988088997 # number of SCUpgradeReq MSHR miss cycles 2808system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3988088997 # number of SCUpgradeReq MSHR miss cycles 2809system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3095498 # number of SCUpgradeFailReq MSHR miss cycles 2810system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3095498 # number of SCUpgradeFailReq MSHR miss cycles 2811system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 13308484000 # number of ReadExReq MSHR miss cycles 2812system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 13308484000 # number of ReadExReq MSHR miss cycles 2813system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20301742000 # number of ReadCleanReq MSHR miss cycles 2814system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20301742000 # number of ReadCleanReq MSHR miss cycles 2815system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 40328599477 # number of ReadSharedReq MSHR miss cycles 2816system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 40328599477 # number of ReadSharedReq MSHR miss cycles 2817system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 15597274497 # number of InvalidateReq MSHR miss cycles 2818system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 15597274497 # number of InvalidateReq MSHR miss cycles 2819system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 686821000 # number of demand (read+write) MSHR miss cycles 2820system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 590353500 # number of demand (read+write) MSHR miss cycles 2821system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20301742000 # number of demand (read+write) MSHR miss cycles 2822system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 53637083477 # number of demand (read+write) MSHR miss cycles 2823system.cpu1.l2cache.demand_mshr_miss_latency::total 75215999977 # number of demand (read+write) MSHR miss cycles 2824system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 686821000 # number of overall MSHR miss cycles 2825system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 590353500 # number of overall MSHR miss cycles 2826system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20301742000 # number of overall MSHR miss cycles 2827system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 53637083477 # number of overall MSHR miss cycles 2828system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 65644901114 # number of overall MSHR miss cycles 2829system.cpu1.l2cache.overall_mshr_miss_latency::total 140860901091 # number of overall MSHR miss cycles 2830system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8454000 # number of ReadReq MSHR uncacheable cycles 2831system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2888554500 # number of ReadReq MSHR uncacheable cycles 2832system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2897008500 # number of ReadReq MSHR uncacheable cycles 2833system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8454000 # number of overall MSHR uncacheable cycles 2834system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2888554500 # number of overall MSHR uncacheable cycles 2835system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2897008500 # number of overall MSHR uncacheable cycles 2836system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020068 # mshr miss rate for ReadReq accesses 2837system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048892 # mshr miss rate for ReadReq accesses 2838system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.026871 # mshr miss rate for ReadReq accesses 2839system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses 2840system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses | 2772system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 12301 # number of overall MSHR uncacheable misses 2773system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 12368 # number of overall MSHR uncacheable misses 2774system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 482957500 # number of ReadReq MSHR miss cycles 2775system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 396613500 # number of ReadReq MSHR miss cycles 2776system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 879571000 # number of ReadReq MSHR miss cycles 2777system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 40678992877 # number of HardPFReq MSHR miss cycles 2778system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 40678992877 # number of HardPFReq MSHR miss cycles 2779system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4718335995 # number of UpgradeReq MSHR miss cycles 2780system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4718335995 # number of UpgradeReq MSHR miss cycles 2781system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3159514995 # number of SCUpgradeReq MSHR miss cycles 2782system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3159514995 # number of SCUpgradeReq MSHR miss cycles 2783system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3128000 # number of SCUpgradeFailReq MSHR miss cycles 2784system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3128000 # number of SCUpgradeFailReq MSHR miss cycles 2785system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8998543499 # number of ReadExReq MSHR miss cycles 2786system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8998543499 # number of ReadExReq MSHR miss cycles 2787system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14777608500 # number of ReadCleanReq MSHR miss cycles 2788system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14777608500 # number of ReadCleanReq MSHR miss cycles 2789system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 27796571986 # number of ReadSharedReq MSHR miss cycles 2790system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 27796571986 # number of ReadSharedReq MSHR miss cycles 2791system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 7398469497 # number of InvalidateReq MSHR miss cycles 2792system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 7398469497 # number of InvalidateReq MSHR miss cycles 2793system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 482957500 # number of demand (read+write) MSHR miss cycles 2794system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 396613500 # number of demand (read+write) MSHR miss cycles 2795system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14777608500 # number of demand (read+write) MSHR miss cycles 2796system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 36795115485 # number of demand (read+write) MSHR miss cycles 2797system.cpu1.l2cache.demand_mshr_miss_latency::total 52452294985 # number of demand (read+write) MSHR miss cycles 2798system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 482957500 # number of overall MSHR miss cycles 2799system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 396613500 # number of overall MSHR miss cycles 2800system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14777608500 # number of overall MSHR miss cycles 2801system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 36795115485 # number of overall MSHR miss cycles 2802system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 40678992877 # number of overall MSHR miss cycles 2803system.cpu1.l2cache.overall_mshr_miss_latency::total 93131287862 # number of overall MSHR miss cycles 2804system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6286000 # number of ReadReq MSHR uncacheable cycles 2805system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 700808000 # number of ReadReq MSHR uncacheable cycles 2806system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 707094000 # number of ReadReq MSHR uncacheable cycles 2807system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6286000 # number of overall MSHR uncacheable cycles 2808system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 700808000 # number of overall MSHR uncacheable cycles 2809system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 707094000 # number of overall MSHR uncacheable cycles 2810system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021697 # mshr miss rate for ReadReq accesses 2811system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048118 # mshr miss rate for ReadReq accesses 2812system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028340 # mshr miss rate for ReadReq accesses 2813system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 2814system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses |
| 2841system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 2842system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 2843system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2844system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 2815system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 2816system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 2817system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2818system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 2845system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996053 # mshr miss rate for UpgradeReq accesses 2846system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996053 # mshr miss rate for UpgradeReq accesses 2847system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999965 # mshr miss rate for SCUpgradeReq accesses 2848system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999965 # mshr miss rate for SCUpgradeReq accesses | 2819system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996594 # mshr miss rate for UpgradeReq accesses 2820system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996594 # mshr miss rate for UpgradeReq accesses 2821system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2822system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses |
| 2849system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2850system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 2823system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2824system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 2851system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.201448 # mshr miss rate for ReadExReq accesses 2852system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.201448 # mshr miss rate for ReadExReq accesses 2853system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.100252 # mshr miss rate for ReadCleanReq accesses 2854system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.100252 # mshr miss rate for ReadCleanReq accesses 2855system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.244306 # mshr miss rate for ReadSharedReq accesses 2856system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.244306 # mshr miss rate for ReadSharedReq accesses 2857system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.624804 # mshr miss rate for InvalidateReq accesses 2858system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.624804 # mshr miss rate for InvalidateReq accesses 2859system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020068 # mshr miss rate for demand accesses 2860system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048892 # mshr miss rate for demand accesses 2861system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.100252 # mshr miss rate for demand accesses 2862system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.234709 # mshr miss rate for demand accesses 2863system.cpu1.l2cache.demand_mshr_miss_rate::total 0.154677 # mshr miss rate for demand accesses 2864system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020068 # mshr miss rate for overall accesses 2865system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048892 # mshr miss rate for overall accesses 2866system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.100252 # mshr miss rate for overall accesses 2867system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.234709 # mshr miss rate for overall accesses | 2825system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.219635 # mshr miss rate for ReadExReq accesses 2826system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.219635 # mshr miss rate for ReadExReq accesses 2827system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.095429 # mshr miss rate for ReadCleanReq accesses 2828system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.095429 # mshr miss rate for ReadCleanReq accesses 2829system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.245367 # mshr miss rate for ReadSharedReq accesses 2830system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.245367 # mshr miss rate for ReadSharedReq accesses 2831system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.597664 # mshr miss rate for InvalidateReq accesses 2832system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.597664 # mshr miss rate for InvalidateReq accesses 2833system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021697 # mshr miss rate for demand accesses 2834system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048118 # mshr miss rate for demand accesses 2835system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.095429 # mshr miss rate for demand accesses 2836system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.239612 # mshr miss rate for demand accesses 2837system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153689 # mshr miss rate for demand accesses 2838system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021697 # mshr miss rate for overall accesses 2839system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048118 # mshr miss rate for overall accesses 2840system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.095429 # mshr miss rate for overall accesses 2841system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.239612 # mshr miss rate for overall accesses |
| 2868system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 2842system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 2869system.cpu1.l2cache.overall_mshr_miss_rate::total 0.222549 # mshr miss rate for overall accesses 2870system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 50012.451759 # average ReadReq mshr miss latency 2871system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 57121.770682 # average ReadReq mshr miss latency 2872system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 53065.252618 # average ReadReq mshr miss latency 2873system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 75599.634138 # average HardPFReq mshr miss latency 2874system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 75599.634138 # average HardPFReq mshr miss latency 2875system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31401.281357 # average UpgradeReq mshr miss latency 2876system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31401.281357 # average UpgradeReq mshr miss latency 2877system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19728.755439 # average SCUpgradeReq mshr miss latency 2878system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19728.755439 # average SCUpgradeReq mshr miss latency 2879system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1031832.666667 # average SCUpgradeFailReq mshr miss latency 2880system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1031832.666667 # average SCUpgradeFailReq mshr miss latency 2881system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 52054.180063 # average ReadExReq mshr miss latency 2882system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 52054.180063 # average ReadExReq mshr miss latency 2883system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32502.808930 # average ReadCleanReq mshr miss latency 2884system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32502.808930 # average ReadCleanReq mshr miss latency 2885system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 37531.909259 # average ReadSharedReq mshr miss latency 2886system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 37531.909259 # average ReadSharedReq mshr miss latency 2887system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 53902.662763 # average InvalidateReq mshr miss latency 2888system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 53902.662763 # average InvalidateReq mshr miss latency 2889system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 50012.451759 # average overall mshr miss latency 2890system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 57121.770682 # average overall mshr miss latency 2891system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32502.808930 # average overall mshr miss latency 2892system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 40323.146607 # average overall mshr miss latency 2893system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 38009.686354 # average overall mshr miss latency 2894system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 50012.451759 # average overall mshr miss latency 2895system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 57121.770682 # average overall mshr miss latency 2896system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32502.808930 # average overall mshr miss latency 2897system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 40323.146607 # average overall mshr miss latency 2898system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 75599.634138 # average overall mshr miss latency 2899system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 49473.708995 # average overall mshr miss latency 2900system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126179.104478 # average ReadReq mshr uncacheable latency 2901system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154459.895193 # average ReadReq mshr uncacheable latency 2902system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 154358.935422 # average ReadReq mshr uncacheable latency 2903system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126179.104478 # average overall mshr uncacheable latency 2904system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 80843.954660 # average overall mshr uncacheable latency 2905system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 80928.806883 # average overall mshr uncacheable latency 2906system.cpu1.toL2Bus.snoop_filter.tot_requests 25472686 # Total number of requests made to the snoop filter. 2907system.cpu1.toL2Bus.snoop_filter.hit_single_requests 13111869 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2908system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1712 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2909system.cpu1.toL2Bus.snoop_filter.tot_snoops 2149417 # Total number of snoops made to the snoop filter. 2910system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2149008 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2911system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 409 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2912system.cpu1.toL2Bus.trans_dist::ReadReq 1009964 # Transaction distribution 2913system.cpu1.toL2Bus.trans_dist::ReadResp 11730214 # Transaction distribution 2914system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution 2915system.cpu1.toL2Bus.trans_dist::WriteReq 17029 # Transaction distribution 2916system.cpu1.toL2Bus.trans_dist::WriteResp 17029 # Transaction distribution 2917system.cpu1.toL2Bus.trans_dist::WritebackDirty 5169290 # Transaction distribution 2918system.cpu1.toL2Bus.trans_dist::WritebackClean 8480923 # Transaction distribution 2919system.cpu1.toL2Bus.trans_dist::CleanEvict 2927219 # Transaction distribution 2920system.cpu1.toL2Bus.trans_dist::HardPFReq 1103039 # Transaction distribution 2921system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution 2922system.cpu1.toL2Bus.trans_dist::UpgradeReq 459055 # Transaction distribution 2923system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 356155 # Transaction distribution 2924system.cpu1.toL2Bus.trans_dist::UpgradeResp 515583 # Transaction distribution 2925system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 73 # Transaction distribution 2926system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution 2927system.cpu1.toL2Bus.trans_dist::ReadExReq 1297103 # Transaction distribution 2928system.cpu1.toL2Bus.trans_dist::ReadExResp 1275135 # Transaction distribution 2929system.cpu1.toL2Bus.trans_dist::ReadCleanReq 6230518 # Transaction distribution 2930system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5372910 # Transaction distribution 2931system.cpu1.toL2Bus.trans_dist::InvalidateReq 516382 # Transaction distribution 2932system.cpu1.toL2Bus.trans_dist::InvalidateResp 463121 # Transaction distribution 2933system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18691087 # Packet count per connected master and slave (bytes) 2934system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 19440124 # Packet count per connected master and slave (bytes) 2935system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 443982 # Packet count per connected master and slave (bytes) 2936system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1442906 # Packet count per connected master and slave (bytes) 2937system.cpu1.toL2Bus.pkt_count::total 40018099 # Packet count per connected master and slave (bytes) 2938system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 797468912 # Cumulative packet size per connected master and slave (bytes) 2939system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 755702222 # Cumulative packet size per connected master and slave (bytes) 2940system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1691072 # Cumulative packet size per connected master and slave (bytes) 2941system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 5474464 # Cumulative packet size per connected master and slave (bytes) 2942system.cpu1.toL2Bus.pkt_size::total 1560336670 # Cumulative packet size per connected master and slave (bytes) 2943system.cpu1.toL2Bus.snoops 7082459 # Total snoops (count) 2944system.cpu1.toL2Bus.snoop_fanout::samples 20668727 # Request fanout histogram 2945system.cpu1.toL2Bus.snoop_fanout::mean 0.122834 # Request fanout histogram 2946system.cpu1.toL2Bus.snoop_fanout::stdev 0.328306 # Request fanout histogram | 2843system.cpu1.l2cache.overall_mshr_miss_rate::total 0.220233 # mshr miss rate for overall accesses 2844system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 36799.565681 # average ReadReq mshr miss latency 2845system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40570.120704 # average ReadReq mshr miss latency 2846system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38409.213974 # average ReadReq mshr miss latency 2847system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52588.772093 # average HardPFReq mshr miss latency 2848system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 52588.772093 # average HardPFReq mshr miss latency 2849system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20699.721837 # average UpgradeReq mshr miss latency 2850system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20699.721837 # average UpgradeReq mshr miss latency 2851system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16333.391896 # average SCUpgradeReq mshr miss latency 2852system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16333.391896 # average SCUpgradeReq mshr miss latency 2853system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 782000 # average SCUpgradeFailReq mshr miss latency 2854system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 782000 # average SCUpgradeFailReq mshr miss latency 2855system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36110.304736 # average ReadExReq mshr miss latency 2856system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36110.304736 # average ReadExReq mshr miss latency 2857system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26962.650321 # average ReadCleanReq mshr miss latency 2858system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26962.650321 # average ReadCleanReq mshr miss latency 2859system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28763.842481 # average ReadSharedReq mshr miss latency 2860system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28763.842481 # average ReadSharedReq mshr miss latency 2861system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 28069.480634 # average InvalidateReq mshr miss latency 2862system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 28069.480634 # average InvalidateReq mshr miss latency 2863system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 36799.565681 # average overall mshr miss latency 2864system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 40570.120704 # average overall mshr miss latency 2865system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26962.650321 # average overall mshr miss latency 2866system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 30269.894802 # average overall mshr miss latency 2867system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29359.627093 # average overall mshr miss latency 2868system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 36799.565681 # average overall mshr miss latency 2869system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 40570.120704 # average overall mshr miss latency 2870system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26962.650321 # average overall mshr miss latency 2871system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 30269.894802 # average overall mshr miss latency 2872system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52588.772093 # average overall mshr miss latency 2873system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36378.343549 # average overall mshr miss latency 2874system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93820.895522 # average ReadReq mshr uncacheable latency 2875system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 114548.545276 # average ReadReq mshr uncacheable latency 2876system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114324.009701 # average ReadReq mshr uncacheable latency 2877system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93820.895522 # average overall mshr uncacheable latency 2878system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 56971.628323 # average overall mshr uncacheable latency 2879system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 57171.248383 # average overall mshr uncacheable latency 2880system.cpu1.toL2Bus.snoop_filter.tot_requests 23197310 # Total number of requests made to the snoop filter. 2881system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11940096 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2882system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2883system.cpu1.toL2Bus.snoop_filter.tot_snoops 1942556 # Total number of snoops made to the snoop filter. 2884system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1942287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2885system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 269 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2886system.cpu1.toL2Bus.trans_dist::ReadReq 900600 # Transaction distribution 2887system.cpu1.toL2Bus.trans_dist::ReadResp 10671947 # Transaction distribution 2888system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 2889system.cpu1.toL2Bus.trans_dist::WriteReq 6183 # Transaction distribution 2890system.cpu1.toL2Bus.trans_dist::WriteResp 6183 # Transaction distribution 2891system.cpu1.toL2Bus.trans_dist::WritebackDirty 4554023 # Transaction distribution 2892system.cpu1.toL2Bus.trans_dist::WritebackClean 7810324 # Transaction distribution 2893system.cpu1.toL2Bus.trans_dist::CleanEvict 2589255 # Transaction distribution 2894system.cpu1.toL2Bus.trans_dist::HardPFReq 981692 # Transaction distribution 2895system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution 2896system.cpu1.toL2Bus.trans_dist::UpgradeReq 441382 # Transaction distribution 2897system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 342905 # Transaction distribution 2898system.cpu1.toL2Bus.trans_dist::UpgradeResp 485827 # Transaction distribution 2899system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution 2900system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 140 # Transaction distribution 2901system.cpu1.toL2Bus.trans_dist::ReadExReq 1162425 # Transaction distribution 2902system.cpu1.toL2Bus.trans_dist::ReadExResp 1140502 # Transaction distribution 2903system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5743338 # Transaction distribution 2904system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4866994 # Transaction distribution 2905system.cpu1.toL2Bus.trans_dist::InvalidateReq 495411 # Transaction distribution 2906system.cpu1.toL2Bus.trans_dist::InvalidateResp 441012 # Transaction distribution 2907system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17229566 # Packet count per connected master and slave (bytes) 2908system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17476902 # Packet count per connected master and slave (bytes) 2909system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 425595 # Packet count per connected master and slave (bytes) 2910system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1276864 # Packet count per connected master and slave (bytes) 2911system.cpu1.toL2Bus.pkt_count::total 36408927 # Packet count per connected master and slave (bytes) 2912system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 735111088 # Cumulative packet size per connected master and slave (bytes) 2913system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 677743701 # Cumulative packet size per connected master and slave (bytes) 2914system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1625328 # Cumulative packet size per connected master and slave (bytes) 2915system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4839024 # Cumulative packet size per connected master and slave (bytes) 2916system.cpu1.toL2Bus.pkt_size::total 1419319141 # Cumulative packet size per connected master and slave (bytes) 2917system.cpu1.toL2Bus.snoops 6390553 # Total snoops (count) 2918system.cpu1.toL2Bus.snoop_fanout::samples 18731260 # Request fanout histogram 2919system.cpu1.toL2Bus.snoop_fanout::mean 0.122712 # Request fanout histogram 2920system.cpu1.toL2Bus.snoop_fanout::stdev 0.328150 # Request fanout histogram |
| 2947system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 2921system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 2948system.cpu1.toL2Bus.snoop_fanout::0 18130322 87.72% 87.72% # Request fanout histogram 2949system.cpu1.toL2Bus.snoop_fanout::1 2537996 12.28% 100.00% # Request fanout histogram 2950system.cpu1.toL2Bus.snoop_fanout::2 409 0.00% 100.00% # Request fanout histogram | 2922system.cpu1.toL2Bus.snoop_fanout::0 16432977 87.73% 87.73% # Request fanout histogram 2923system.cpu1.toL2Bus.snoop_fanout::1 2298014 12.27% 100.00% # Request fanout histogram 2924system.cpu1.toL2Bus.snoop_fanout::2 269 0.00% 100.00% # Request fanout histogram |
| 2951system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2952system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2953system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 2925system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2926system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2927system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 2954system.cpu1.toL2Bus.snoop_fanout::total 20668727 # Request fanout histogram 2955system.cpu1.toL2Bus.reqLayer0.occupancy 25335696459 # Layer occupancy (ticks) 2956system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 2957system.cpu1.toL2Bus.snoopLayer0.occupancy 177629109 # Layer occupancy (ticks) | 2928system.cpu1.toL2Bus.snoop_fanout::total 18731260 # Request fanout histogram 2929system.cpu1.toL2Bus.reqLayer0.occupancy 23041315974 # Layer occupancy (ticks) 2930system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2931system.cpu1.toL2Bus.snoopLayer0.occupancy 175324271 # Layer occupancy (ticks) |
| 2958system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2932system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2959system.cpu1.toL2Bus.respLayer0.occupancy 9352273561 # Layer occupancy (ticks) | 2933system.cpu1.toL2Bus.respLayer0.occupancy 8621166733 # Layer occupancy (ticks) |
| 2960system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 2934system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2961system.cpu1.toL2Bus.respLayer1.occupancy 8995491238 # Layer occupancy (ticks) | 2935system.cpu1.toL2Bus.respLayer1.occupancy 8059431425 # Layer occupancy (ticks) |
| 2962system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 2936system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 2963system.cpu1.toL2Bus.respLayer2.occupancy 232944299 # Layer occupancy (ticks) | 2937system.cpu1.toL2Bus.respLayer2.occupancy 222762323 # Layer occupancy (ticks) |
| 2964system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 2938system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2965system.cpu1.toL2Bus.respLayer3.occupancy 759270636 # Layer occupancy (ticks) | 2939system.cpu1.toL2Bus.respLayer3.occupancy 672656647 # Layer occupancy (ticks) |
| 2966system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2940system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2967system.iobus.trans_dist::ReadReq 40305 # Transaction distribution 2968system.iobus.trans_dist::ReadResp 40305 # Transaction distribution 2969system.iobus.trans_dist::WriteReq 136595 # Transaction distribution 2970system.iobus.trans_dist::WriteResp 136595 # Transaction distribution 2971system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47570 # Packet count per connected master and slave (bytes) | 2941system.iobus.trans_dist::ReadReq 40341 # Transaction distribution 2942system.iobus.trans_dist::ReadResp 40341 # Transaction distribution 2943system.iobus.trans_dist::WriteReq 136646 # Transaction distribution 2944system.iobus.trans_dist::WriteResp 136646 # Transaction distribution 2945system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47790 # Packet count per connected master and slave (bytes) |
| 2972system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2973system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2974system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2975system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2976system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2977system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2978system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2979system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2980system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2981system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) | 2946system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2947system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2948system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2949system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2950system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2951system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2952system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2953system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2954system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2955system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 2982system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) | 2956system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) |
| 2983system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) | 2957system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) |
| 2984system.iobus.pkt_count_system.bridge.master::total 122504 # Packet count per connected master and slave (bytes) 2985system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231216 # Packet count per connected master and slave (bytes) 2986system.iobus.pkt_count_system.realview.ide.dma::total 231216 # Packet count per connected master and slave (bytes) | 2958system.iobus.pkt_count_system.bridge.master::total 122672 # Packet count per connected master and slave (bytes) 2959system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231222 # Packet count per connected master and slave (bytes) 2960system.iobus.pkt_count_system.realview.ide.dma::total 231222 # Packet count per connected master and slave (bytes) |
| 2987system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2988system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) | 2961system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2962system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) |
| 2989system.iobus.pkt_count::total 353800 # Packet count per connected master and slave (bytes) 2990system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47590 # Cumulative packet size per connected master and slave (bytes) | 2963system.iobus.pkt_count::total 353974 # Packet count per connected master and slave (bytes) 2964system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47810 # Cumulative packet size per connected master and slave (bytes) |
| 2991system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2992system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 2993system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2994system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2995system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2996system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2997system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2998system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2999system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 3000system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 2965system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2966system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 2967system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2968system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2969system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2970system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2971system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2972system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2973system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2974system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 3001system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) | 2975system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) |
| 3002system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) | 2976system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) |
| 3003system.iobus.pkt_size_system.bridge.master::total 155611 # Cumulative packet size per connected master and slave (bytes) 3004system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338880 # Cumulative packet size per connected master and slave (bytes) 3005system.iobus.pkt_size_system.realview.ide.dma::total 7338880 # Cumulative packet size per connected master and slave (bytes) | 2977system.iobus.pkt_size_system.bridge.master::total 155802 # Cumulative packet size per connected master and slave (bytes) 2978system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338904 # Cumulative packet size per connected master and slave (bytes) 2979system.iobus.pkt_size_system.realview.ide.dma::total 7338904 # Cumulative packet size per connected master and slave (bytes) |
| 3006system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 3007system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) | 2980system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2981system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) |
| 3008system.iobus.pkt_size::total 7496577 # Cumulative packet size per connected master and slave (bytes) 3009system.iobus.reqLayer0.occupancy 36858001 # Layer occupancy (ticks) | 2982system.iobus.pkt_size::total 7496792 # Cumulative packet size per connected master and slave (bytes) 2983system.iobus.reqLayer0.occupancy 37061004 # Layer occupancy (ticks) |
| 3010system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) | 2984system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 3011system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) | 2985system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) |
| 3012system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) | 2986system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 3013system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks) | 2987system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks) |
| 3014system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 3015system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) 3016system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) | 2988system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2989system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) 2990system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) |
| 3017system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) | 2991system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) |
| 3018system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 3019system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks) 3020system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) | 2992system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2993system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks) 2994system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) |
| 3021system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) | 2995system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) |
| 3022system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 3023system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) 3024system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 3025system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) 3026system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) | 2996system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2997system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) 2998system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2999system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) 3000system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) |
| 3027system.iobus.reqLayer16.occupancy 13500 # Layer occupancy (ticks) | 3001system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) |
| 3028system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) | 3002system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) |
| 3029system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) | 3003system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) |
| 3030system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) | 3004system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) |
| 3031system.iobus.reqLayer23.occupancy 24204504 # Layer occupancy (ticks) | 3005system.iobus.reqLayer23.occupancy 24283001 # Layer occupancy (ticks) |
| 3032system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) | 3006system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
| 3033system.iobus.reqLayer24.occupancy 36391000 # Layer occupancy (ticks) | 3007system.iobus.reqLayer24.occupancy 36403501 # Layer occupancy (ticks) |
| 3034system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 3008system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 3035system.iobus.reqLayer25.occupancy 567248472 # Layer occupancy (ticks) | 3009system.iobus.reqLayer25.occupancy 569028004 # Layer occupancy (ticks) |
| 3036system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) | 3010system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) |
| 3037system.iobus.respLayer0.occupancy 92640000 # Layer occupancy (ticks) | 3011system.iobus.respLayer0.occupancy 92757000 # Layer occupancy (ticks) |
| 3038system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 3012system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 3039system.iobus.respLayer3.occupancy 147912000 # Layer occupancy (ticks) | 3013system.iobus.respLayer3.occupancy 147918000 # Layer occupancy (ticks) |
| 3040system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 3041system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 3042system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) | 3014system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 3015system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 3016system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) |
| 3043system.iocache.tags.replacements 115604 # number of replacements 3044system.iocache.tags.tagsinuse 11.311799 # Cycle average of tags in use | 3017system.iocache.tags.replacements 115592 # number of replacements 3018system.iocache.tags.tagsinuse 11.302694 # Cycle average of tags in use |
| 3045system.iocache.tags.total_refs 3 # Total number of references to valid blocks. | 3019system.iocache.tags.total_refs 3 # Total number of references to valid blocks. |
| 3046system.iocache.tags.sampled_refs 115620 # Sample count of references to valid blocks. | 3020system.iocache.tags.sampled_refs 115608 # Sample count of references to valid blocks. |
| 3047system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. | 3021system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. |
| 3048system.iocache.tags.warmup_cycle 9121271629000 # Cycle when the warmup percentage was hit. 3049system.iocache.tags.occ_blocks::realview.ethernet 7.400215 # Average occupied blocks per requestor 3050system.iocache.tags.occ_blocks::realview.ide 3.911583 # Average occupied blocks per requestor 3051system.iocache.tags.occ_percent::realview.ethernet 0.462513 # Average percentage of cache occupancy 3052system.iocache.tags.occ_percent::realview.ide 0.244474 # Average percentage of cache occupancy 3053system.iocache.tags.occ_percent::total 0.706987 # Average percentage of cache occupancy | 3022system.iocache.tags.warmup_cycle 9115775800000 # Cycle when the warmup percentage was hit. 3023system.iocache.tags.occ_blocks::realview.ethernet 3.842796 # Average occupied blocks per requestor 3024system.iocache.tags.occ_blocks::realview.ide 7.459898 # Average occupied blocks per requestor 3025system.iocache.tags.occ_percent::realview.ethernet 0.240175 # Average percentage of cache occupancy 3026system.iocache.tags.occ_percent::realview.ide 0.466244 # Average percentage of cache occupancy 3027system.iocache.tags.occ_percent::total 0.706418 # Average percentage of cache occupancy |
| 3054system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 3055system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 3056system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 3028system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 3029system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 3030system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 3057system.iocache.tags.tag_accesses 1040829 # Number of tag accesses 3058system.iocache.tags.data_accesses 1040829 # Number of data accesses | 3031system.iocache.tags.tag_accesses 1040856 # Number of tag accesses 3032system.iocache.tags.data_accesses 1040856 # Number of data accesses |
| 3059system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses | 3033system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses |
| 3060system.iocache.ReadReq_misses::realview.ide 8880 # number of ReadReq misses 3061system.iocache.ReadReq_misses::total 8917 # number of ReadReq misses | 3034system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses 3035system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses |
| 3062system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 3063system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 3064system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 3065system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 3066system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses | 3036system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 3037system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 3038system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 3039system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 3040system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses |
| 3067system.iocache.demand_misses::realview.ide 115608 # number of demand (read+write) misses 3068system.iocache.demand_misses::total 115648 # number of demand (read+write) misses | 3041system.iocache.demand_misses::realview.ide 115611 # number of demand (read+write) misses 3042system.iocache.demand_misses::total 115651 # number of demand (read+write) misses |
| 3069system.iocache.overall_misses::realview.ethernet 40 # number of overall misses | 3043system.iocache.overall_misses::realview.ethernet 40 # number of overall misses |
| 3070system.iocache.overall_misses::realview.ide 115608 # number of overall misses 3071system.iocache.overall_misses::total 115648 # number of overall misses 3072system.iocache.ReadReq_miss_latency::realview.ethernet 5214500 # number of ReadReq miss cycles 3073system.iocache.ReadReq_miss_latency::realview.ide 1674617085 # number of ReadReq miss cycles 3074system.iocache.ReadReq_miss_latency::total 1679831585 # number of ReadReq miss cycles | 3044system.iocache.overall_misses::realview.ide 115611 # number of overall misses 3045system.iocache.overall_misses::total 115651 # number of overall misses 3046system.iocache.ReadReq_miss_latency::realview.ethernet 5246000 # number of ReadReq miss cycles 3047system.iocache.ReadReq_miss_latency::realview.ide 1667860010 # number of ReadReq miss cycles 3048system.iocache.ReadReq_miss_latency::total 1673106010 # number of ReadReq miss cycles |
| 3075system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 3076system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles | 3049system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 3050system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles |
| 3077system.iocache.WriteLineReq_miss_latency::realview.ide 13548349887 # number of WriteLineReq miss cycles 3078system.iocache.WriteLineReq_miss_latency::total 13548349887 # number of WriteLineReq miss cycles 3079system.iocache.demand_miss_latency::realview.ethernet 5583500 # number of demand (read+write) miss cycles 3080system.iocache.demand_miss_latency::realview.ide 15222966972 # number of demand (read+write) miss cycles 3081system.iocache.demand_miss_latency::total 15228550472 # number of demand (read+write) miss cycles 3082system.iocache.overall_miss_latency::realview.ethernet 5583500 # number of overall miss cycles 3083system.iocache.overall_miss_latency::realview.ide 15222966972 # number of overall miss cycles 3084system.iocache.overall_miss_latency::total 15228550472 # number of overall miss cycles | 3051system.iocache.WriteLineReq_miss_latency::realview.ide 12956345994 # number of WriteLineReq miss cycles 3052system.iocache.WriteLineReq_miss_latency::total 12956345994 # number of WriteLineReq miss cycles 3053system.iocache.demand_miss_latency::realview.ethernet 5615000 # number of demand (read+write) miss cycles 3054system.iocache.demand_miss_latency::realview.ide 14624206004 # number of demand (read+write) miss cycles 3055system.iocache.demand_miss_latency::total 14629821004 # number of demand (read+write) miss cycles 3056system.iocache.overall_miss_latency::realview.ethernet 5615000 # number of overall miss cycles 3057system.iocache.overall_miss_latency::realview.ide 14624206004 # number of overall miss cycles 3058system.iocache.overall_miss_latency::total 14629821004 # number of overall miss cycles |
| 3085system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) | 3059system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) |
| 3086system.iocache.ReadReq_accesses::realview.ide 8880 # number of ReadReq accesses(hits+misses) 3087system.iocache.ReadReq_accesses::total 8917 # number of ReadReq accesses(hits+misses) | 3060system.iocache.ReadReq_accesses::realview.ide 8883 # number of ReadReq accesses(hits+misses) 3061system.iocache.ReadReq_accesses::total 8920 # number of ReadReq accesses(hits+misses) |
| 3088system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 3089system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 3090system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 3091system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 3092system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses | 3062system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 3063system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 3064system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 3065system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 3066system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses |
| 3093system.iocache.demand_accesses::realview.ide 115608 # number of demand (read+write) accesses 3094system.iocache.demand_accesses::total 115648 # number of demand (read+write) accesses | 3067system.iocache.demand_accesses::realview.ide 115611 # number of demand (read+write) accesses 3068system.iocache.demand_accesses::total 115651 # number of demand (read+write) accesses |
| 3095system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses | 3069system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses |
| 3096system.iocache.overall_accesses::realview.ide 115608 # number of overall (read+write) accesses 3097system.iocache.overall_accesses::total 115648 # number of overall (read+write) accesses | 3070system.iocache.overall_accesses::realview.ide 115611 # number of overall (read+write) accesses 3071system.iocache.overall_accesses::total 115651 # number of overall (read+write) accesses |
| 3098system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 3099system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 3100system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3101system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 3102system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 3103system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 3104system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 3105system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 3106system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 3107system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3108system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 3109system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 3110system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 3072system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 3073system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 3074system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3075system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 3076system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 3077system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 3078system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 3079system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 3080system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 3081system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3082system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 3083system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 3084system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 3111system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140932.432432 # average ReadReq miss latency 3112system.iocache.ReadReq_avg_miss_latency::realview.ide 188583.005068 # average ReadReq miss latency 3113system.iocache.ReadReq_avg_miss_latency::total 188385.284849 # average ReadReq miss latency | 3085system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141783.783784 # average ReadReq miss latency 3086system.iocache.ReadReq_avg_miss_latency::realview.ide 187758.641225 # average ReadReq miss latency 3087system.iocache.ReadReq_avg_miss_latency::total 187567.938341 # average ReadReq miss latency |
| 3114system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 3115system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency | 3088system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 3089system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency |
| 3116system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126942.788087 # average WriteLineReq miss latency 3117system.iocache.WriteLineReq_avg_miss_latency::total 126942.788087 # average WriteLineReq miss latency 3118system.iocache.demand_avg_miss_latency::realview.ethernet 139587.500000 # average overall miss latency 3119system.iocache.demand_avg_miss_latency::realview.ide 131677.452875 # average overall miss latency 3120system.iocache.demand_avg_miss_latency::total 131680.188780 # average overall miss latency 3121system.iocache.overall_avg_miss_latency::realview.ethernet 139587.500000 # average overall miss latency 3122system.iocache.overall_avg_miss_latency::realview.ide 131677.452875 # average overall miss latency 3123system.iocache.overall_avg_miss_latency::total 131680.188780 # average overall miss latency 3124system.iocache.blocked_cycles::no_mshrs 33801 # number of cycles access was blocked | 3090system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121395.941028 # average WriteLineReq miss latency 3091system.iocache.WriteLineReq_avg_miss_latency::total 121395.941028 # average WriteLineReq miss latency 3092system.iocache.demand_avg_miss_latency::realview.ethernet 140375 # average overall miss latency 3093system.iocache.demand_avg_miss_latency::realview.ide 126494.935638 # average overall miss latency 3094system.iocache.demand_avg_miss_latency::total 126499.736310 # average overall miss latency 3095system.iocache.overall_avg_miss_latency::realview.ethernet 140375 # average overall miss latency 3096system.iocache.overall_avg_miss_latency::realview.ide 126494.935638 # average overall miss latency 3097system.iocache.overall_avg_miss_latency::total 126499.736310 # average overall miss latency 3098system.iocache.blocked_cycles::no_mshrs 33436 # number of cycles access was blocked |
| 3125system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 3099system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 3126system.iocache.blocked::no_mshrs 3396 # number of cycles access was blocked | 3100system.iocache.blocked::no_mshrs 3541 # number of cycles access was blocked |
| 3127system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 3101system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 3128system.iocache.avg_blocked_cycles::no_mshrs 9.953180 # average number of cycles each access was blocked | 3102system.iocache.avg_blocked_cycles::no_mshrs 9.442530 # average number of cycles each access was blocked |
| 3129system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3130system.iocache.writebacks::writebacks 106694 # number of writebacks 3131system.iocache.writebacks::total 106694 # number of writebacks 3132system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses | 3103system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3104system.iocache.writebacks::writebacks 106694 # number of writebacks 3105system.iocache.writebacks::total 106694 # number of writebacks 3106system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses |
| 3133system.iocache.ReadReq_mshr_misses::realview.ide 8880 # number of ReadReq MSHR misses 3134system.iocache.ReadReq_mshr_misses::total 8917 # number of ReadReq MSHR misses | 3107system.iocache.ReadReq_mshr_misses::realview.ide 8883 # number of ReadReq MSHR misses 3108system.iocache.ReadReq_mshr_misses::total 8920 # number of ReadReq MSHR misses |
| 3135system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 3136system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 3137system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 3138system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 3139system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses | 3109system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 3110system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 3111system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 3112system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 3113system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses |
| 3140system.iocache.demand_mshr_misses::realview.ide 115608 # number of demand (read+write) MSHR misses 3141system.iocache.demand_mshr_misses::total 115648 # number of demand (read+write) MSHR misses | 3114system.iocache.demand_mshr_misses::realview.ide 115611 # number of demand (read+write) MSHR misses 3115system.iocache.demand_mshr_misses::total 115651 # number of demand (read+write) MSHR misses |
| 3142system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses | 3116system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses |
| 3143system.iocache.overall_mshr_misses::realview.ide 115608 # number of overall MSHR misses 3144system.iocache.overall_mshr_misses::total 115648 # number of overall MSHR misses 3145system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3364500 # number of ReadReq MSHR miss cycles 3146system.iocache.ReadReq_mshr_miss_latency::realview.ide 1230617085 # number of ReadReq MSHR miss cycles 3147system.iocache.ReadReq_mshr_miss_latency::total 1233981585 # number of ReadReq MSHR miss cycles | 3117system.iocache.overall_mshr_misses::realview.ide 115611 # number of overall MSHR misses 3118system.iocache.overall_mshr_misses::total 115651 # number of overall MSHR misses 3119system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3396000 # number of ReadReq MSHR miss cycles 3120system.iocache.ReadReq_mshr_miss_latency::realview.ide 1223710010 # number of ReadReq MSHR miss cycles 3121system.iocache.ReadReq_mshr_miss_latency::total 1227106010 # number of ReadReq MSHR miss cycles |
| 3148system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 3149system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles | 3122system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 3123system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles |
| 3150system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8205400767 # number of WriteLineReq MSHR miss cycles 3151system.iocache.WriteLineReq_mshr_miss_latency::total 8205400767 # number of WriteLineReq MSHR miss cycles 3152system.iocache.demand_mshr_miss_latency::realview.ethernet 3583500 # number of demand (read+write) MSHR miss cycles 3153system.iocache.demand_mshr_miss_latency::realview.ide 9436017852 # number of demand (read+write) MSHR miss cycles 3154system.iocache.demand_mshr_miss_latency::total 9439601352 # number of demand (read+write) MSHR miss cycles 3155system.iocache.overall_mshr_miss_latency::realview.ethernet 3583500 # number of overall MSHR miss cycles 3156system.iocache.overall_mshr_miss_latency::realview.ide 9436017852 # number of overall MSHR miss cycles 3157system.iocache.overall_mshr_miss_latency::total 9439601352 # number of overall MSHR miss cycles | 3124system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7611309187 # number of WriteLineReq MSHR miss cycles 3125system.iocache.WriteLineReq_mshr_miss_latency::total 7611309187 # number of WriteLineReq MSHR miss cycles 3126system.iocache.demand_mshr_miss_latency::realview.ethernet 3615000 # number of demand (read+write) MSHR miss cycles 3127system.iocache.demand_mshr_miss_latency::realview.ide 8835019197 # number of demand (read+write) MSHR miss cycles 3128system.iocache.demand_mshr_miss_latency::total 8838634197 # number of demand (read+write) MSHR miss cycles 3129system.iocache.overall_mshr_miss_latency::realview.ethernet 3615000 # number of overall MSHR miss cycles 3130system.iocache.overall_mshr_miss_latency::realview.ide 8835019197 # number of overall MSHR miss cycles 3131system.iocache.overall_mshr_miss_latency::total 8838634197 # number of overall MSHR miss cycles |
| 3158system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 3159system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3160system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3161system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 3162system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 3163system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 3164system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 3165system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 3166system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3167system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3168system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 3169system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3170system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 3132system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 3133system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3134system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3135system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 3136system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 3137system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 3138system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 3139system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 3140system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3141system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3142system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 3143system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3144system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 3171system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90932.432432 # average ReadReq mshr miss latency 3172system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138583.005068 # average ReadReq mshr miss latency 3173system.iocache.ReadReq_avg_mshr_miss_latency::total 138385.284849 # average ReadReq mshr miss latency | 3145system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91783.783784 # average ReadReq mshr miss latency 3146system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137758.641225 # average ReadReq mshr miss latency 3147system.iocache.ReadReq_avg_mshr_miss_latency::total 137567.938341 # average ReadReq mshr miss latency |
| 3174system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 3175system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency | 3148system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 3149system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency |
| 3176system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76881.425371 # average WriteLineReq mshr miss latency 3177system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76881.425371 # average WriteLineReq mshr miss latency 3178system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89587.500000 # average overall mshr miss latency 3179system.iocache.demand_avg_mshr_miss_latency::realview.ide 81620.803508 # average overall mshr miss latency 3180system.iocache.demand_avg_mshr_miss_latency::total 81623.559007 # average overall mshr miss latency 3181system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89587.500000 # average overall mshr miss latency 3182system.iocache.overall_avg_mshr_miss_latency::realview.ide 81620.803508 # average overall mshr miss latency 3183system.iocache.overall_avg_mshr_miss_latency::total 81623.559007 # average overall mshr miss latency 3184system.l2c.tags.replacements 1658646 # number of replacements 3185system.l2c.tags.tagsinuse 63614.355421 # Cycle average of tags in use 3186system.l2c.tags.total_refs 6503693 # Total number of references to valid blocks. 3187system.l2c.tags.sampled_refs 1717473 # Sample count of references to valid blocks. 3188system.l2c.tags.avg_refs 3.786780 # Average number of references to valid blocks. 3189system.l2c.tags.warmup_cycle 4906135000 # Cycle when the warmup percentage was hit. 3190system.l2c.tags.occ_blocks::writebacks 21778.868920 # Average occupied blocks per requestor 3191system.l2c.tags.occ_blocks::cpu0.dtb.walker 77.174149 # Average occupied blocks per requestor 3192system.l2c.tags.occ_blocks::cpu0.itb.walker 104.892582 # Average occupied blocks per requestor 3193system.l2c.tags.occ_blocks::cpu0.inst 3369.245029 # Average occupied blocks per requestor 3194system.l2c.tags.occ_blocks::cpu0.data 4690.877672 # Average occupied blocks per requestor 3195system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 5127.772728 # Average occupied blocks per requestor 3196system.l2c.tags.occ_blocks::cpu1.dtb.walker 275.118534 # Average occupied blocks per requestor 3197system.l2c.tags.occ_blocks::cpu1.itb.walker 421.752346 # Average occupied blocks per requestor 3198system.l2c.tags.occ_blocks::cpu1.inst 3923.044466 # Average occupied blocks per requestor 3199system.l2c.tags.occ_blocks::cpu1.data 10215.764671 # Average occupied blocks per requestor 3200system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13629.844323 # Average occupied blocks per requestor 3201system.l2c.tags.occ_percent::writebacks 0.332319 # Average percentage of cache occupancy 3202system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001178 # Average percentage of cache occupancy 3203system.l2c.tags.occ_percent::cpu0.itb.walker 0.001601 # Average percentage of cache occupancy 3204system.l2c.tags.occ_percent::cpu0.inst 0.051411 # Average percentage of cache occupancy 3205system.l2c.tags.occ_percent::cpu0.data 0.071577 # Average percentage of cache occupancy 3206system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.078244 # Average percentage of cache occupancy 3207system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004198 # Average percentage of cache occupancy 3208system.l2c.tags.occ_percent::cpu1.itb.walker 0.006435 # Average percentage of cache occupancy 3209system.l2c.tags.occ_percent::cpu1.inst 0.059861 # Average percentage of cache occupancy 3210system.l2c.tags.occ_percent::cpu1.data 0.155880 # Average percentage of cache occupancy 3211system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.207975 # Average percentage of cache occupancy 3212system.l2c.tags.occ_percent::total 0.970678 # Average percentage of cache occupancy 3213system.l2c.tags.occ_task_id_blocks::1022 9349 # Occupied blocks per task id 3214system.l2c.tags.occ_task_id_blocks::1023 246 # Occupied blocks per task id 3215system.l2c.tags.occ_task_id_blocks::1024 49232 # Occupied blocks per task id 3216system.l2c.tags.age_task_id_blocks_1022::0 12 # Occupied blocks per task id 3217system.l2c.tags.age_task_id_blocks_1022::1 39 # Occupied blocks per task id 3218system.l2c.tags.age_task_id_blocks_1022::2 275 # Occupied blocks per task id 3219system.l2c.tags.age_task_id_blocks_1022::3 523 # Occupied blocks per task id 3220system.l2c.tags.age_task_id_blocks_1022::4 8500 # Occupied blocks per task id 3221system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 3222system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 3223system.l2c.tags.age_task_id_blocks_1023::4 244 # Occupied blocks per task id 3224system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id 3225system.l2c.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id 3226system.l2c.tags.age_task_id_blocks_1024::2 2922 # Occupied blocks per task id 3227system.l2c.tags.age_task_id_blocks_1024::3 4073 # Occupied blocks per task id 3228system.l2c.tags.age_task_id_blocks_1024::4 41884 # Occupied blocks per task id 3229system.l2c.tags.occ_task_id_percent::1022 0.142654 # Percentage of cache occupancy per task id 3230system.l2c.tags.occ_task_id_percent::1023 0.003754 # Percentage of cache occupancy per task id 3231system.l2c.tags.occ_task_id_percent::1024 0.751221 # Percentage of cache occupancy per task id 3232system.l2c.tags.tag_accesses 83070472 # Number of tag accesses 3233system.l2c.tags.data_accesses 83070472 # Number of data accesses 3234system.l2c.WritebackDirty_hits::writebacks 3045027 # number of WritebackDirty hits 3235system.l2c.WritebackDirty_hits::total 3045027 # number of WritebackDirty hits 3236system.l2c.WritebackClean_hits::writebacks 2 # number of WritebackClean hits 3237system.l2c.WritebackClean_hits::total 2 # number of WritebackClean hits 3238system.l2c.UpgradeReq_hits::cpu0.data 177681 # number of UpgradeReq hits 3239system.l2c.UpgradeReq_hits::cpu1.data 151575 # number of UpgradeReq hits 3240system.l2c.UpgradeReq_hits::total 329256 # number of UpgradeReq hits 3241system.l2c.SCUpgradeReq_hits::cpu0.data 38520 # number of SCUpgradeReq hits 3242system.l2c.SCUpgradeReq_hits::cpu1.data 46161 # number of SCUpgradeReq hits 3243system.l2c.SCUpgradeReq_hits::total 84681 # number of SCUpgradeReq hits 3244system.l2c.ReadExReq_hits::cpu0.data 58316 # number of ReadExReq hits 3245system.l2c.ReadExReq_hits::cpu1.data 56868 # number of ReadExReq hits 3246system.l2c.ReadExReq_hits::total 115184 # number of ReadExReq hits 3247system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6506 # number of ReadSharedReq hits 3248system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4755 # number of ReadSharedReq hits 3249system.l2c.ReadSharedReq_hits::cpu0.inst 505198 # number of ReadSharedReq hits 3250system.l2c.ReadSharedReq_hits::cpu0.data 629843 # number of ReadSharedReq hits 3251system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 303617 # number of ReadSharedReq hits 3252system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6637 # number of ReadSharedReq hits 3253system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4374 # number of ReadSharedReq hits 3254system.l2c.ReadSharedReq_hits::cpu1.inst 567907 # number of ReadSharedReq hits 3255system.l2c.ReadSharedReq_hits::cpu1.data 649267 # number of ReadSharedReq hits 3256system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 304398 # number of ReadSharedReq hits 3257system.l2c.ReadSharedReq_hits::total 2982502 # number of ReadSharedReq hits 3258system.l2c.InvalidateReq_hits::cpu0.data 134777 # number of InvalidateReq hits 3259system.l2c.InvalidateReq_hits::cpu1.data 127780 # number of InvalidateReq hits 3260system.l2c.InvalidateReq_hits::total 262557 # number of InvalidateReq hits 3261system.l2c.demand_hits::cpu0.dtb.walker 6506 # number of demand (read+write) hits 3262system.l2c.demand_hits::cpu0.itb.walker 4755 # number of demand (read+write) hits 3263system.l2c.demand_hits::cpu0.inst 505198 # number of demand (read+write) hits 3264system.l2c.demand_hits::cpu0.data 688159 # number of demand (read+write) hits 3265system.l2c.demand_hits::cpu0.l2cache.prefetcher 303617 # number of demand (read+write) hits 3266system.l2c.demand_hits::cpu1.dtb.walker 6637 # number of demand (read+write) hits 3267system.l2c.demand_hits::cpu1.itb.walker 4374 # number of demand (read+write) hits 3268system.l2c.demand_hits::cpu1.inst 567907 # number of demand (read+write) hits 3269system.l2c.demand_hits::cpu1.data 706135 # number of demand (read+write) hits 3270system.l2c.demand_hits::cpu1.l2cache.prefetcher 304398 # number of demand (read+write) hits 3271system.l2c.demand_hits::total 3097686 # number of demand (read+write) hits 3272system.l2c.overall_hits::cpu0.dtb.walker 6506 # number of overall hits 3273system.l2c.overall_hits::cpu0.itb.walker 4755 # number of overall hits 3274system.l2c.overall_hits::cpu0.inst 505198 # number of overall hits 3275system.l2c.overall_hits::cpu0.data 688159 # number of overall hits 3276system.l2c.overall_hits::cpu0.l2cache.prefetcher 303617 # number of overall hits 3277system.l2c.overall_hits::cpu1.dtb.walker 6637 # number of overall hits 3278system.l2c.overall_hits::cpu1.itb.walker 4374 # number of overall hits 3279system.l2c.overall_hits::cpu1.inst 567907 # number of overall hits 3280system.l2c.overall_hits::cpu1.data 706135 # number of overall hits 3281system.l2c.overall_hits::cpu1.l2cache.prefetcher 304398 # number of overall hits 3282system.l2c.overall_hits::total 3097686 # number of overall hits 3283system.l2c.UpgradeReq_misses::cpu0.data 62380 # number of UpgradeReq misses 3284system.l2c.UpgradeReq_misses::cpu1.data 67853 # number of UpgradeReq misses 3285system.l2c.UpgradeReq_misses::total 130233 # number of UpgradeReq misses 3286system.l2c.SCUpgradeReq_misses::cpu0.data 11700 # number of SCUpgradeReq misses 3287system.l2c.SCUpgradeReq_misses::cpu1.data 13195 # number of SCUpgradeReq misses 3288system.l2c.SCUpgradeReq_misses::total 24895 # number of SCUpgradeReq misses 3289system.l2c.ReadExReq_misses::cpu0.data 82725 # number of ReadExReq misses 3290system.l2c.ReadExReq_misses::cpu1.data 61895 # number of ReadExReq misses 3291system.l2c.ReadExReq_misses::total 144620 # number of ReadExReq misses 3292system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2677 # number of ReadSharedReq misses 3293system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1890 # number of ReadSharedReq misses 3294system.l2c.ReadSharedReq_misses::cpu0.inst 55177 # number of ReadSharedReq misses 3295system.l2c.ReadSharedReq_misses::cpu0.data 140078 # number of ReadSharedReq misses 3296system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 275934 # number of ReadSharedReq misses 3297system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3410 # number of ReadSharedReq misses 3298system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3269 # number of ReadSharedReq misses 3299system.l2c.ReadSharedReq_misses::cpu1.inst 56707 # number of ReadSharedReq misses 3300system.l2c.ReadSharedReq_misses::cpu1.data 154817 # number of ReadSharedReq misses 3301system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 324363 # number of ReadSharedReq misses 3302system.l2c.ReadSharedReq_misses::total 1018322 # number of ReadSharedReq misses 3303system.l2c.InvalidateReq_misses::cpu0.data 452102 # number of InvalidateReq misses 3304system.l2c.InvalidateReq_misses::cpu1.data 148246 # number of InvalidateReq misses 3305system.l2c.InvalidateReq_misses::total 600348 # number of InvalidateReq misses 3306system.l2c.demand_misses::cpu0.dtb.walker 2677 # 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number of SCUpgradeReq miss cycles 3332system.l2c.SCUpgradeReq_miss_latency::cpu1.data 228989500 # number of SCUpgradeReq miss cycles 3333system.l2c.SCUpgradeReq_miss_latency::total 403354500 # number of SCUpgradeReq miss cycles 3334system.l2c.ReadExReq_miss_latency::cpu0.data 11711225489 # number of ReadExReq miss cycles 3335system.l2c.ReadExReq_miss_latency::cpu1.data 8776678992 # number of ReadExReq miss cycles 3336system.l2c.ReadExReq_miss_latency::total 20487904481 # number of ReadExReq miss cycles 3337system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 384848000 # number of ReadSharedReq miss cycles 3338system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 271512500 # number of ReadSharedReq miss cycles 3339system.l2c.ReadSharedReq_miss_latency::cpu0.inst 7616921000 # number of ReadSharedReq miss cycles 3340system.l2c.ReadSharedReq_miss_latency::cpu0.data 20740892494 # number of ReadSharedReq miss cycles 3341system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 51616446987 # number of ReadSharedReq miss cycles 3342system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 485048000 # number of ReadSharedReq miss cycles 3343system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 453166500 # number of ReadSharedReq miss cycles 3344system.l2c.ReadSharedReq_miss_latency::cpu1.inst 7794605500 # number of ReadSharedReq miss cycles 3345system.l2c.ReadSharedReq_miss_latency::cpu1.data 22700743998 # number of ReadSharedReq miss cycles 3346system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 60057715420 # number of ReadSharedReq miss cycles 3347system.l2c.ReadSharedReq_miss_latency::total 172121900399 # number of ReadSharedReq miss cycles 3348system.l2c.InvalidateReq_miss_latency::cpu0.data 148772000 # number of InvalidateReq miss cycles 3349system.l2c.InvalidateReq_miss_latency::cpu1.data 161516500 # number of InvalidateReq miss cycles 3350system.l2c.InvalidateReq_miss_latency::total 310288500 # number of InvalidateReq miss cycles 3351system.l2c.demand_miss_latency::cpu0.dtb.walker 384848000 # number of demand (read+write) miss cycles 3352system.l2c.demand_miss_latency::cpu0.itb.walker 271512500 # number of demand (read+write) miss cycles 3353system.l2c.demand_miss_latency::cpu0.inst 7616921000 # number of demand (read+write) miss cycles 3354system.l2c.demand_miss_latency::cpu0.data 32452117983 # number of demand (read+write) miss cycles 3355system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 51616446987 # number of demand (read+write) miss cycles 3356system.l2c.demand_miss_latency::cpu1.dtb.walker 485048000 # number of demand (read+write) miss cycles 3357system.l2c.demand_miss_latency::cpu1.itb.walker 453166500 # number of demand (read+write) miss cycles 3358system.l2c.demand_miss_latency::cpu1.inst 7794605500 # number of demand (read+write) miss cycles 3359system.l2c.demand_miss_latency::cpu1.data 31477422990 # number of demand (read+write) miss cycles 3360system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 60057715420 # number of demand (read+write) miss cycles 3361system.l2c.demand_miss_latency::total 192609804880 # number of demand (read+write) miss cycles 3362system.l2c.overall_miss_latency::cpu0.dtb.walker 384848000 # number of overall miss cycles 3363system.l2c.overall_miss_latency::cpu0.itb.walker 271512500 # number of overall miss cycles 3364system.l2c.overall_miss_latency::cpu0.inst 7616921000 # number of overall miss cycles 3365system.l2c.overall_miss_latency::cpu0.data 32452117983 # number of overall miss cycles 3366system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 51616446987 # number of overall miss cycles 3367system.l2c.overall_miss_latency::cpu1.dtb.walker 485048000 # number of overall miss cycles 3368system.l2c.overall_miss_latency::cpu1.itb.walker 453166500 # number of overall miss cycles 3369system.l2c.overall_miss_latency::cpu1.inst 7794605500 # number of overall miss cycles 3370system.l2c.overall_miss_latency::cpu1.data 31477422990 # number of overall miss cycles 3371system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 60057715420 # number of overall miss cycles 3372system.l2c.overall_miss_latency::total 192609804880 # number of overall miss cycles 3373system.l2c.WritebackDirty_accesses::writebacks 3045027 # number of WritebackDirty accesses(hits+misses) 3374system.l2c.WritebackDirty_accesses::total 3045027 # number of WritebackDirty accesses(hits+misses) 3375system.l2c.WritebackClean_accesses::writebacks 2 # number of WritebackClean accesses(hits+misses) 3376system.l2c.WritebackClean_accesses::total 2 # number of WritebackClean accesses(hits+misses) 3377system.l2c.UpgradeReq_accesses::cpu0.data 240061 # number of UpgradeReq accesses(hits+misses) 3378system.l2c.UpgradeReq_accesses::cpu1.data 219428 # number of UpgradeReq accesses(hits+misses) 3379system.l2c.UpgradeReq_accesses::total 459489 # number of UpgradeReq accesses(hits+misses) 3380system.l2c.SCUpgradeReq_accesses::cpu0.data 50220 # number of SCUpgradeReq accesses(hits+misses) 3381system.l2c.SCUpgradeReq_accesses::cpu1.data 59356 # number of SCUpgradeReq accesses(hits+misses) 3382system.l2c.SCUpgradeReq_accesses::total 109576 # number of SCUpgradeReq accesses(hits+misses) 3383system.l2c.ReadExReq_accesses::cpu0.data 141041 # number of ReadExReq accesses(hits+misses) 3384system.l2c.ReadExReq_accesses::cpu1.data 118763 # number of ReadExReq accesses(hits+misses) 3385system.l2c.ReadExReq_accesses::total 259804 # number of ReadExReq accesses(hits+misses) 3386system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 9183 # number of ReadSharedReq accesses(hits+misses) 3387system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6645 # number of ReadSharedReq accesses(hits+misses) 3388system.l2c.ReadSharedReq_accesses::cpu0.inst 560375 # number of ReadSharedReq accesses(hits+misses) 3389system.l2c.ReadSharedReq_accesses::cpu0.data 769921 # number of ReadSharedReq accesses(hits+misses) 3390system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 579551 # number of ReadSharedReq accesses(hits+misses) 3391system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 10047 # number of ReadSharedReq accesses(hits+misses) 3392system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7643 # number of ReadSharedReq accesses(hits+misses) 3393system.l2c.ReadSharedReq_accesses::cpu1.inst 624614 # number of ReadSharedReq accesses(hits+misses) 3394system.l2c.ReadSharedReq_accesses::cpu1.data 804084 # number of ReadSharedReq accesses(hits+misses) 3395system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 628761 # number of ReadSharedReq accesses(hits+misses) 3396system.l2c.ReadSharedReq_accesses::total 4000824 # number of ReadSharedReq accesses(hits+misses) 3397system.l2c.InvalidateReq_accesses::cpu0.data 586879 # number of InvalidateReq accesses(hits+misses) 3398system.l2c.InvalidateReq_accesses::cpu1.data 276026 # number of InvalidateReq accesses(hits+misses) 3399system.l2c.InvalidateReq_accesses::total 862905 # number of InvalidateReq accesses(hits+misses) 3400system.l2c.demand_accesses::cpu0.dtb.walker 9183 # number of demand (read+write) accesses 3401system.l2c.demand_accesses::cpu0.itb.walker 6645 # number of demand (read+write) accesses 3402system.l2c.demand_accesses::cpu0.inst 560375 # number of demand (read+write) accesses 3403system.l2c.demand_accesses::cpu0.data 910962 # number of demand (read+write) accesses 3404system.l2c.demand_accesses::cpu0.l2cache.prefetcher 579551 # number of demand (read+write) accesses 3405system.l2c.demand_accesses::cpu1.dtb.walker 10047 # number of demand (read+write) accesses 3406system.l2c.demand_accesses::cpu1.itb.walker 7643 # number of demand (read+write) accesses 3407system.l2c.demand_accesses::cpu1.inst 624614 # number of demand (read+write) accesses 3408system.l2c.demand_accesses::cpu1.data 922847 # number of demand (read+write) accesses 3409system.l2c.demand_accesses::cpu1.l2cache.prefetcher 628761 # number of demand (read+write) accesses 3410system.l2c.demand_accesses::total 4260628 # number of demand (read+write) accesses 3411system.l2c.overall_accesses::cpu0.dtb.walker 9183 # number of overall (read+write) accesses 3412system.l2c.overall_accesses::cpu0.itb.walker 6645 # number of overall (read+write) accesses 3413system.l2c.overall_accesses::cpu0.inst 560375 # number of overall (read+write) accesses 3414system.l2c.overall_accesses::cpu0.data 910962 # number of overall (read+write) accesses 3415system.l2c.overall_accesses::cpu0.l2cache.prefetcher 579551 # number of overall (read+write) accesses 3416system.l2c.overall_accesses::cpu1.dtb.walker 10047 # number of overall (read+write) accesses 3417system.l2c.overall_accesses::cpu1.itb.walker 7643 # number of overall (read+write) accesses 3418system.l2c.overall_accesses::cpu1.inst 624614 # number of overall (read+write) accesses 3419system.l2c.overall_accesses::cpu1.data 922847 # number of overall (read+write) accesses 3420system.l2c.overall_accesses::cpu1.l2cache.prefetcher 628761 # number of overall (read+write) accesses 3421system.l2c.overall_accesses::total 4260628 # number of overall (read+write) accesses 3422system.l2c.UpgradeReq_miss_rate::cpu0.data 0.259851 # miss rate for UpgradeReq accesses 3423system.l2c.UpgradeReq_miss_rate::cpu1.data 0.309227 # miss rate for UpgradeReq accesses 3424system.l2c.UpgradeReq_miss_rate::total 0.283430 # miss rate for UpgradeReq accesses 3425system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.232975 # miss rate for SCUpgradeReq accesses 3426system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.222303 # miss rate for SCUpgradeReq accesses 3427system.l2c.SCUpgradeReq_miss_rate::total 0.227194 # miss rate for SCUpgradeReq accesses 3428system.l2c.ReadExReq_miss_rate::cpu0.data 0.586532 # miss rate for ReadExReq accesses 3429system.l2c.ReadExReq_miss_rate::cpu1.data 0.521164 # miss rate for ReadExReq accesses 3430system.l2c.ReadExReq_miss_rate::total 0.556650 # miss rate for ReadExReq accesses 3431system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.291517 # miss rate for ReadSharedReq accesses 3432system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.284424 # miss rate for ReadSharedReq accesses 3433system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.098464 # miss rate for ReadSharedReq accesses 3434system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.181938 # miss rate for ReadSharedReq accesses 3435system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.476117 # miss rate for ReadSharedReq accesses 3436system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.339405 # miss rate for ReadSharedReq accesses 3437system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.427712 # miss rate for ReadSharedReq accesses 3438system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.090787 # miss rate for ReadSharedReq accesses 3439system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.192538 # miss rate for ReadSharedReq accesses 3440system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.515876 # miss rate for ReadSharedReq accesses 3441system.l2c.ReadSharedReq_miss_rate::total 0.254528 # miss rate for ReadSharedReq accesses 3442system.l2c.InvalidateReq_miss_rate::cpu0.data 0.770350 # miss rate for InvalidateReq accesses 3443system.l2c.InvalidateReq_miss_rate::cpu1.data 0.537073 # miss rate for InvalidateReq accesses 3444system.l2c.InvalidateReq_miss_rate::total 0.695729 # miss rate for InvalidateReq accesses 3445system.l2c.demand_miss_rate::cpu0.dtb.walker 0.291517 # miss rate for demand accesses 3446system.l2c.demand_miss_rate::cpu0.itb.walker 0.284424 # miss rate for demand accesses 3447system.l2c.demand_miss_rate::cpu0.inst 0.098464 # miss rate for demand accesses 3448system.l2c.demand_miss_rate::cpu0.data 0.244580 # miss rate for demand accesses 3449system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.476117 # miss rate for demand accesses 3450system.l2c.demand_miss_rate::cpu1.dtb.walker 0.339405 # miss rate for demand accesses 3451system.l2c.demand_miss_rate::cpu1.itb.walker 0.427712 # miss rate for demand accesses 3452system.l2c.demand_miss_rate::cpu1.inst 0.090787 # miss rate for demand accesses 3453system.l2c.demand_miss_rate::cpu1.data 0.234830 # miss rate for demand accesses 3454system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.515876 # miss rate for demand accesses 3455system.l2c.demand_miss_rate::total 0.272951 # miss rate for demand accesses 3456system.l2c.overall_miss_rate::cpu0.dtb.walker 0.291517 # miss rate for overall accesses 3457system.l2c.overall_miss_rate::cpu0.itb.walker 0.284424 # miss rate for overall accesses 3458system.l2c.overall_miss_rate::cpu0.inst 0.098464 # miss rate for overall accesses 3459system.l2c.overall_miss_rate::cpu0.data 0.244580 # miss rate for overall accesses 3460system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.476117 # miss rate for overall accesses 3461system.l2c.overall_miss_rate::cpu1.dtb.walker 0.339405 # miss rate for overall accesses 3462system.l2c.overall_miss_rate::cpu1.itb.walker 0.427712 # miss rate for overall accesses 3463system.l2c.overall_miss_rate::cpu1.inst 0.090787 # miss rate for overall accesses 3464system.l2c.overall_miss_rate::cpu1.data 0.234830 # miss rate for overall accesses 3465system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.515876 # miss rate for overall accesses 3466system.l2c.overall_miss_rate::total 0.272951 # miss rate for overall accesses 3467system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16591.167041 # average UpgradeReq miss latency 3468system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17052.495837 # average UpgradeReq miss latency 3469system.l2c.UpgradeReq_avg_miss_latency::total 16831.525036 # average UpgradeReq miss latency 3470system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14902.991453 # average SCUpgradeReq miss latency 3471system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17354.262978 # average SCUpgradeReq miss latency 3472system.l2c.SCUpgradeReq_avg_miss_latency::total 16202.229363 # average SCUpgradeReq miss latency 3473system.l2c.ReadExReq_avg_miss_latency::cpu0.data 141568.153388 # average ReadExReq miss latency 3474system.l2c.ReadExReq_avg_miss_latency::cpu1.data 141799.482866 # average ReadExReq miss latency 3475system.l2c.ReadExReq_avg_miss_latency::total 141667.158630 # average ReadExReq miss latency 3476system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 143760.926410 # average ReadSharedReq miss latency 3477system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 143657.407407 # average ReadSharedReq miss latency 3478system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 138045.218116 # average ReadSharedReq miss latency 3479system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 148066.737775 # average ReadSharedReq miss latency 3480system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 187060.844213 # average ReadSharedReq miss latency 3481system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 142242.815249 # average ReadSharedReq miss latency 3482system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 138625.420618 # average ReadSharedReq miss latency 3483system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137454.026840 # average ReadSharedReq miss latency 3484system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 146629.530336 # average ReadSharedReq miss latency 3485system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 185155.876040 # average ReadSharedReq miss latency 3486system.l2c.ReadSharedReq_avg_miss_latency::total 169025.023911 # average ReadSharedReq miss latency 3487system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 329.067334 # average InvalidateReq miss latency 3488system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 1089.516749 # average InvalidateReq miss latency 3489system.l2c.InvalidateReq_avg_miss_latency::total 516.847728 # average InvalidateReq miss latency 3490system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 143760.926410 # average overall miss latency 3491system.l2c.demand_avg_miss_latency::cpu0.itb.walker 143657.407407 # average overall miss latency 3492system.l2c.demand_avg_miss_latency::cpu0.inst 138045.218116 # average overall miss latency 3493system.l2c.demand_avg_miss_latency::cpu0.data 145653.864549 # average overall miss latency 3494system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 187060.844213 # average overall miss latency 3495system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 142242.815249 # average overall miss latency 3496system.l2c.demand_avg_miss_latency::cpu1.itb.walker 138625.420618 # average overall miss latency 3497system.l2c.demand_avg_miss_latency::cpu1.inst 137454.026840 # average overall miss latency 3498system.l2c.demand_avg_miss_latency::cpu1.data 145250.023026 # average overall miss latency 3499system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 185155.876040 # average overall miss latency 3500system.l2c.demand_avg_miss_latency::total 165622.881347 # average overall miss latency 3501system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 143760.926410 # average overall miss latency 3502system.l2c.overall_avg_miss_latency::cpu0.itb.walker 143657.407407 # average overall miss latency 3503system.l2c.overall_avg_miss_latency::cpu0.inst 138045.218116 # average overall miss latency 3504system.l2c.overall_avg_miss_latency::cpu0.data 145653.864549 # average overall miss latency 3505system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 187060.844213 # average overall miss latency 3506system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 142242.815249 # average overall miss latency 3507system.l2c.overall_avg_miss_latency::cpu1.itb.walker 138625.420618 # average overall miss latency 3508system.l2c.overall_avg_miss_latency::cpu1.inst 137454.026840 # average overall miss latency 3509system.l2c.overall_avg_miss_latency::cpu1.data 145250.023026 # average overall miss latency 3510system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 185155.876040 # average overall miss latency 3511system.l2c.overall_avg_miss_latency::total 165622.881347 # average overall miss latency 3512system.l2c.blocked_cycles::no_mshrs 15923 # number of cycles access was blocked | 3150system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71315.017493 # average WriteLineReq mshr miss latency 3151system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71315.017493 # average WriteLineReq mshr miss latency 3152system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency 3153system.iocache.demand_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency 3154system.iocache.demand_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency 3155system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency 3156system.iocache.overall_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency 3157system.iocache.overall_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency 3158system.l2c.tags.replacements 1423185 # number of replacements 3159system.l2c.tags.tagsinuse 63448.336905 # Cycle average of tags in use 3160system.l2c.tags.total_refs 6060449 # Total number of references to valid blocks. 3161system.l2c.tags.sampled_refs 1482600 # Sample count of references to valid blocks. 3162system.l2c.tags.avg_refs 4.087717 # Average number of references to valid blocks. 3163system.l2c.tags.warmup_cycle 3022937500 # Cycle when the warmup percentage was hit. 3164system.l2c.tags.occ_blocks::writebacks 20826.975184 # Average occupied blocks per requestor 3165system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.832374 # Average occupied blocks per requestor 3166system.l2c.tags.occ_blocks::cpu0.itb.walker 12.742051 # Average occupied blocks per requestor 3167system.l2c.tags.occ_blocks::cpu0.inst 3854.622142 # Average occupied blocks per requestor 3168system.l2c.tags.occ_blocks::cpu0.data 3569.542843 # Average occupied blocks per requestor 3169system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 2315.690288 # Average occupied blocks per requestor 3170system.l2c.tags.occ_blocks::cpu1.dtb.walker 335.622211 # Average occupied blocks per requestor 3171system.l2c.tags.occ_blocks::cpu1.itb.walker 552.279614 # Average occupied blocks per requestor 3172system.l2c.tags.occ_blocks::cpu1.inst 2996.807733 # Average occupied blocks per requestor 3173system.l2c.tags.occ_blocks::cpu1.data 11095.009846 # Average occupied blocks per requestor 3174system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17872.212619 # Average occupied blocks per requestor 3175system.l2c.tags.occ_percent::writebacks 0.317794 # Average percentage of cache occupancy 3176system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000257 # Average percentage of cache occupancy 3177system.l2c.tags.occ_percent::cpu0.itb.walker 0.000194 # Average percentage of cache occupancy 3178system.l2c.tags.occ_percent::cpu0.inst 0.058817 # Average percentage of cache occupancy 3179system.l2c.tags.occ_percent::cpu0.data 0.054467 # Average percentage of cache occupancy 3180system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.035335 # Average percentage of cache occupancy 3181system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005121 # Average percentage of cache occupancy 3182system.l2c.tags.occ_percent::cpu1.itb.walker 0.008427 # Average percentage of cache occupancy 3183system.l2c.tags.occ_percent::cpu1.inst 0.045728 # Average percentage of cache occupancy 3184system.l2c.tags.occ_percent::cpu1.data 0.169296 # Average percentage of cache occupancy 3185system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.272708 # Average percentage of cache occupancy 3186system.l2c.tags.occ_percent::total 0.968145 # Average percentage of cache occupancy 3187system.l2c.tags.occ_task_id_blocks::1022 10702 # Occupied blocks per task id 3188system.l2c.tags.occ_task_id_blocks::1023 222 # Occupied blocks per task id 3189system.l2c.tags.occ_task_id_blocks::1024 48491 # Occupied blocks per task id 3190system.l2c.tags.age_task_id_blocks_1022::0 11 # Occupied blocks per task id 3191system.l2c.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id 3192system.l2c.tags.age_task_id_blocks_1022::2 1377 # Occupied blocks per task id 3193system.l2c.tags.age_task_id_blocks_1022::3 482 # Occupied blocks per task id 3194system.l2c.tags.age_task_id_blocks_1022::4 8826 # Occupied blocks per task id 3195system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 3196system.l2c.tags.age_task_id_blocks_1023::4 218 # Occupied blocks per task id 3197system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 3198system.l2c.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id 3199system.l2c.tags.age_task_id_blocks_1024::2 2760 # Occupied blocks per task id 3200system.l2c.tags.age_task_id_blocks_1024::3 5614 # Occupied blocks per task id 3201system.l2c.tags.age_task_id_blocks_1024::4 39761 # Occupied blocks per task id 3202system.l2c.tags.occ_task_id_percent::1022 0.163300 # Percentage of cache occupancy per task id 3203system.l2c.tags.occ_task_id_percent::1023 0.003387 # Percentage of cache occupancy per task id 3204system.l2c.tags.occ_task_id_percent::1024 0.739914 # Percentage of cache occupancy per task id 3205system.l2c.tags.tag_accesses 76659871 # Number of tag accesses 3206system.l2c.tags.data_accesses 76659871 # Number of data accesses 3207system.l2c.WritebackDirty_hits::writebacks 2799563 # number of WritebackDirty hits 3208system.l2c.WritebackDirty_hits::total 2799563 # number of WritebackDirty hits 3209system.l2c.UpgradeReq_hits::cpu0.data 175772 # number of UpgradeReq hits 3210system.l2c.UpgradeReq_hits::cpu1.data 127713 # number of UpgradeReq hits 3211system.l2c.UpgradeReq_hits::total 303485 # number of UpgradeReq hits 3212system.l2c.SCUpgradeReq_hits::cpu0.data 39800 # number of SCUpgradeReq hits 3213system.l2c.SCUpgradeReq_hits::cpu1.data 41169 # number of SCUpgradeReq hits 3214system.l2c.SCUpgradeReq_hits::total 80969 # number of SCUpgradeReq hits 3215system.l2c.ReadExReq_hits::cpu0.data 55176 # number of ReadExReq hits 3216system.l2c.ReadExReq_hits::cpu1.data 52470 # number of ReadExReq hits 3217system.l2c.ReadExReq_hits::total 107646 # number of ReadExReq hits 3218system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6441 # number of ReadSharedReq hits 3219system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4632 # number of ReadSharedReq hits 3220system.l2c.ReadSharedReq_hits::cpu0.inst 512914 # number of ReadSharedReq hits 3221system.l2c.ReadSharedReq_hits::cpu0.data 602529 # number of ReadSharedReq hits 3222system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 321191 # number of ReadSharedReq hits 3223system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6205 # number of ReadSharedReq hits 3224system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4222 # number of ReadSharedReq hits 3225system.l2c.ReadSharedReq_hits::cpu1.inst 506602 # number of ReadSharedReq hits 3226system.l2c.ReadSharedReq_hits::cpu1.data 564191 # number of ReadSharedReq hits 3227system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 285940 # number of ReadSharedReq hits 3228system.l2c.ReadSharedReq_hits::total 2814867 # number of ReadSharedReq hits 3229system.l2c.InvalidateReq_hits::cpu0.data 134470 # number of InvalidateReq hits 3230system.l2c.InvalidateReq_hits::cpu1.data 123510 # number of InvalidateReq hits 3231system.l2c.InvalidateReq_hits::total 257980 # number of InvalidateReq hits 3232system.l2c.demand_hits::cpu0.dtb.walker 6441 # number of demand (read+write) hits 3233system.l2c.demand_hits::cpu0.itb.walker 4632 # number of demand (read+write) hits 3234system.l2c.demand_hits::cpu0.inst 512914 # number of demand (read+write) hits 3235system.l2c.demand_hits::cpu0.data 657705 # number of demand (read+write) hits 3236system.l2c.demand_hits::cpu0.l2cache.prefetcher 321191 # number of demand (read+write) hits 3237system.l2c.demand_hits::cpu1.dtb.walker 6205 # number of demand (read+write) hits 3238system.l2c.demand_hits::cpu1.itb.walker 4222 # number of demand (read+write) hits 3239system.l2c.demand_hits::cpu1.inst 506602 # number of demand (read+write) hits 3240system.l2c.demand_hits::cpu1.data 616661 # number of demand (read+write) hits 3241system.l2c.demand_hits::cpu1.l2cache.prefetcher 285940 # number of demand (read+write) hits 3242system.l2c.demand_hits::total 2922513 # number of demand (read+write) hits 3243system.l2c.overall_hits::cpu0.dtb.walker 6441 # number of overall hits 3244system.l2c.overall_hits::cpu0.itb.walker 4632 # number of overall hits 3245system.l2c.overall_hits::cpu0.inst 512914 # number of overall hits 3246system.l2c.overall_hits::cpu0.data 657705 # number of overall hits 3247system.l2c.overall_hits::cpu0.l2cache.prefetcher 321191 # number of overall hits 3248system.l2c.overall_hits::cpu1.dtb.walker 6205 # number of overall hits 3249system.l2c.overall_hits::cpu1.itb.walker 4222 # number of overall hits 3250system.l2c.overall_hits::cpu1.inst 506602 # number of overall hits 3251system.l2c.overall_hits::cpu1.data 616661 # number of overall hits 3252system.l2c.overall_hits::cpu1.l2cache.prefetcher 285940 # number of overall hits 3253system.l2c.overall_hits::total 2922513 # number of overall hits 3254system.l2c.UpgradeReq_misses::cpu0.data 65800 # number of UpgradeReq misses 3255system.l2c.UpgradeReq_misses::cpu1.data 60076 # number of UpgradeReq misses 3256system.l2c.UpgradeReq_misses::total 125876 # number of UpgradeReq misses 3257system.l2c.SCUpgradeReq_misses::cpu0.data 12292 # number of SCUpgradeReq misses 3258system.l2c.SCUpgradeReq_misses::cpu1.data 11651 # number of SCUpgradeReq misses 3259system.l2c.SCUpgradeReq_misses::total 23943 # number of SCUpgradeReq misses 3260system.l2c.ReadExReq_misses::cpu0.data 76423 # number of ReadExReq misses 3261system.l2c.ReadExReq_misses::cpu1.data 57499 # number of ReadExReq misses 3262system.l2c.ReadExReq_misses::total 133922 # number of ReadExReq misses 3263system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1380 # number of ReadSharedReq misses 3264system.l2c.ReadSharedReq_misses::cpu0.itb.walker 911 # number of ReadSharedReq misses 3265system.l2c.ReadSharedReq_misses::cpu0.inst 60940 # number of ReadSharedReq misses 3266system.l2c.ReadSharedReq_misses::cpu0.data 127468 # number of ReadSharedReq misses 3267system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 217255 # number of ReadSharedReq misses 3268system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3149 # number of ReadSharedReq misses 3269system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2958 # number of ReadSharedReq misses 3270system.l2c.ReadSharedReq_misses::cpu1.inst 41472 # number of ReadSharedReq misses 3271system.l2c.ReadSharedReq_misses::cpu1.data 123752 # number of ReadSharedReq misses 3272system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 256869 # number of ReadSharedReq misses 3273system.l2c.ReadSharedReq_misses::total 836154 # number of ReadSharedReq misses 3274system.l2c.InvalidateReq_misses::cpu0.data 453643 # number of InvalidateReq misses 3275system.l2c.InvalidateReq_misses::cpu1.data 128024 # number of InvalidateReq misses 3276system.l2c.InvalidateReq_misses::total 581667 # number of InvalidateReq misses 3277system.l2c.demand_misses::cpu0.dtb.walker 1380 # number of demand (read+write) misses 3278system.l2c.demand_misses::cpu0.itb.walker 911 # number of demand (read+write) misses 3279system.l2c.demand_misses::cpu0.inst 60940 # number of demand (read+write) misses 3280system.l2c.demand_misses::cpu0.data 203891 # number of demand (read+write) misses 3281system.l2c.demand_misses::cpu0.l2cache.prefetcher 217255 # number of demand (read+write) misses 3282system.l2c.demand_misses::cpu1.dtb.walker 3149 # number of demand (read+write) misses 3283system.l2c.demand_misses::cpu1.itb.walker 2958 # number of demand (read+write) misses 3284system.l2c.demand_misses::cpu1.inst 41472 # number of demand (read+write) misses 3285system.l2c.demand_misses::cpu1.data 181251 # number of demand (read+write) misses 3286system.l2c.demand_misses::cpu1.l2cache.prefetcher 256869 # number of demand (read+write) misses 3287system.l2c.demand_misses::total 970076 # number of demand (read+write) misses 3288system.l2c.overall_misses::cpu0.dtb.walker 1380 # number of overall misses 3289system.l2c.overall_misses::cpu0.itb.walker 911 # number of overall misses 3290system.l2c.overall_misses::cpu0.inst 60940 # number of overall misses 3291system.l2c.overall_misses::cpu0.data 203891 # number of overall misses 3292system.l2c.overall_misses::cpu0.l2cache.prefetcher 217255 # number of overall misses 3293system.l2c.overall_misses::cpu1.dtb.walker 3149 # number of overall misses 3294system.l2c.overall_misses::cpu1.itb.walker 2958 # number of overall misses 3295system.l2c.overall_misses::cpu1.inst 41472 # number of overall misses 3296system.l2c.overall_misses::cpu1.data 181251 # number of overall misses 3297system.l2c.overall_misses::cpu1.l2cache.prefetcher 256869 # number of overall misses 3298system.l2c.overall_misses::total 970076 # number of overall misses 3299system.l2c.UpgradeReq_miss_latency::cpu0.data 448544000 # number of UpgradeReq miss cycles 3300system.l2c.UpgradeReq_miss_latency::cpu1.data 390663000 # number of UpgradeReq miss cycles 3301system.l2c.UpgradeReq_miss_latency::total 839207000 # number of UpgradeReq miss cycles 3302system.l2c.SCUpgradeReq_miss_latency::cpu0.data 74504000 # number of SCUpgradeReq miss cycles 3303system.l2c.SCUpgradeReq_miss_latency::cpu1.data 75234500 # number of SCUpgradeReq miss cycles 3304system.l2c.SCUpgradeReq_miss_latency::total 149738500 # number of SCUpgradeReq miss cycles 3305system.l2c.ReadExReq_miss_latency::cpu0.data 6937615986 # number of ReadExReq miss cycles 3306system.l2c.ReadExReq_miss_latency::cpu1.data 5199044498 # number of ReadExReq miss cycles 3307system.l2c.ReadExReq_miss_latency::total 12136660484 # number of ReadExReq miss cycles 3308system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 131946500 # number of ReadSharedReq miss cycles 3309system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 85177500 # number of ReadSharedReq miss cycles 3310system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5320925500 # number of ReadSharedReq miss cycles 3311system.l2c.ReadSharedReq_miss_latency::cpu0.data 12028584244 # number of ReadSharedReq miss cycles 3312system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 30519314752 # number of ReadSharedReq miss cycles 3313system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 290010000 # number of ReadSharedReq miss cycles 3314system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 265646000 # number of ReadSharedReq miss cycles 3315system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3652893500 # number of ReadSharedReq miss cycles 3316system.l2c.ReadSharedReq_miss_latency::cpu1.data 11931003997 # number of ReadSharedReq miss cycles 3317system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 35372822568 # number of ReadSharedReq miss cycles 3318system.l2c.ReadSharedReq_miss_latency::total 99598324561 # number of ReadSharedReq miss cycles 3319system.l2c.InvalidateReq_miss_latency::cpu0.data 58512500 # number of InvalidateReq miss cycles 3320system.l2c.InvalidateReq_miss_latency::cpu1.data 49578000 # number of InvalidateReq miss cycles 3321system.l2c.InvalidateReq_miss_latency::total 108090500 # number of InvalidateReq miss cycles 3322system.l2c.demand_miss_latency::cpu0.dtb.walker 131946500 # number of demand (read+write) miss cycles 3323system.l2c.demand_miss_latency::cpu0.itb.walker 85177500 # number of demand (read+write) miss cycles 3324system.l2c.demand_miss_latency::cpu0.inst 5320925500 # number of demand (read+write) miss cycles 3325system.l2c.demand_miss_latency::cpu0.data 18966200230 # number of demand (read+write) miss cycles 3326system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 30519314752 # number of demand (read+write) miss cycles 3327system.l2c.demand_miss_latency::cpu1.dtb.walker 290010000 # number of demand (read+write) miss cycles 3328system.l2c.demand_miss_latency::cpu1.itb.walker 265646000 # number of demand (read+write) miss cycles 3329system.l2c.demand_miss_latency::cpu1.inst 3652893500 # number of demand (read+write) miss cycles 3330system.l2c.demand_miss_latency::cpu1.data 17130048495 # number of demand (read+write) miss cycles 3331system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 35372822568 # number of demand (read+write) miss cycles 3332system.l2c.demand_miss_latency::total 111734985045 # number of demand (read+write) miss cycles 3333system.l2c.overall_miss_latency::cpu0.dtb.walker 131946500 # number of overall miss cycles 3334system.l2c.overall_miss_latency::cpu0.itb.walker 85177500 # number of overall miss cycles 3335system.l2c.overall_miss_latency::cpu0.inst 5320925500 # number of overall miss cycles 3336system.l2c.overall_miss_latency::cpu0.data 18966200230 # number of overall miss cycles 3337system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 30519314752 # number of overall miss cycles 3338system.l2c.overall_miss_latency::cpu1.dtb.walker 290010000 # number of overall miss cycles 3339system.l2c.overall_miss_latency::cpu1.itb.walker 265646000 # number of overall miss cycles 3340system.l2c.overall_miss_latency::cpu1.inst 3652893500 # number of overall miss cycles 3341system.l2c.overall_miss_latency::cpu1.data 17130048495 # number of overall miss cycles 3342system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 35372822568 # number of overall miss cycles 3343system.l2c.overall_miss_latency::total 111734985045 # number of overall miss cycles 3344system.l2c.WritebackDirty_accesses::writebacks 2799563 # number of WritebackDirty accesses(hits+misses) 3345system.l2c.WritebackDirty_accesses::total 2799563 # number of WritebackDirty accesses(hits+misses) 3346system.l2c.UpgradeReq_accesses::cpu0.data 241572 # number of UpgradeReq accesses(hits+misses) 3347system.l2c.UpgradeReq_accesses::cpu1.data 187789 # number of UpgradeReq accesses(hits+misses) 3348system.l2c.UpgradeReq_accesses::total 429361 # number of UpgradeReq accesses(hits+misses) 3349system.l2c.SCUpgradeReq_accesses::cpu0.data 52092 # number of SCUpgradeReq accesses(hits+misses) 3350system.l2c.SCUpgradeReq_accesses::cpu1.data 52820 # number of SCUpgradeReq accesses(hits+misses) 3351system.l2c.SCUpgradeReq_accesses::total 104912 # number of SCUpgradeReq accesses(hits+misses) 3352system.l2c.ReadExReq_accesses::cpu0.data 131599 # number of ReadExReq accesses(hits+misses) 3353system.l2c.ReadExReq_accesses::cpu1.data 109969 # number of ReadExReq accesses(hits+misses) 3354system.l2c.ReadExReq_accesses::total 241568 # number of ReadExReq accesses(hits+misses) 3355system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7821 # number of ReadSharedReq accesses(hits+misses) 3356system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5543 # number of ReadSharedReq accesses(hits+misses) 3357system.l2c.ReadSharedReq_accesses::cpu0.inst 573854 # number of ReadSharedReq accesses(hits+misses) 3358system.l2c.ReadSharedReq_accesses::cpu0.data 729997 # number of ReadSharedReq accesses(hits+misses) 3359system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 538446 # number of ReadSharedReq accesses(hits+misses) 3360system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9354 # number of ReadSharedReq accesses(hits+misses) 3361system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7180 # number of ReadSharedReq accesses(hits+misses) 3362system.l2c.ReadSharedReq_accesses::cpu1.inst 548074 # number of ReadSharedReq accesses(hits+misses) 3363system.l2c.ReadSharedReq_accesses::cpu1.data 687943 # number of ReadSharedReq accesses(hits+misses) 3364system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 542809 # number of ReadSharedReq accesses(hits+misses) 3365system.l2c.ReadSharedReq_accesses::total 3651021 # number of ReadSharedReq accesses(hits+misses) 3366system.l2c.InvalidateReq_accesses::cpu0.data 588113 # number of InvalidateReq accesses(hits+misses) 3367system.l2c.InvalidateReq_accesses::cpu1.data 251534 # number of InvalidateReq accesses(hits+misses) 3368system.l2c.InvalidateReq_accesses::total 839647 # number of InvalidateReq accesses(hits+misses) 3369system.l2c.demand_accesses::cpu0.dtb.walker 7821 # number of demand (read+write) accesses 3370system.l2c.demand_accesses::cpu0.itb.walker 5543 # number of demand (read+write) accesses 3371system.l2c.demand_accesses::cpu0.inst 573854 # number of demand (read+write) accesses 3372system.l2c.demand_accesses::cpu0.data 861596 # number of demand (read+write) accesses 3373system.l2c.demand_accesses::cpu0.l2cache.prefetcher 538446 # number of demand (read+write) accesses 3374system.l2c.demand_accesses::cpu1.dtb.walker 9354 # number of demand (read+write) accesses 3375system.l2c.demand_accesses::cpu1.itb.walker 7180 # number of demand (read+write) accesses 3376system.l2c.demand_accesses::cpu1.inst 548074 # number of demand (read+write) accesses 3377system.l2c.demand_accesses::cpu1.data 797912 # number of demand (read+write) accesses 3378system.l2c.demand_accesses::cpu1.l2cache.prefetcher 542809 # number of demand (read+write) accesses 3379system.l2c.demand_accesses::total 3892589 # number of demand (read+write) accesses 3380system.l2c.overall_accesses::cpu0.dtb.walker 7821 # number of overall (read+write) accesses 3381system.l2c.overall_accesses::cpu0.itb.walker 5543 # number of overall (read+write) accesses 3382system.l2c.overall_accesses::cpu0.inst 573854 # number of overall (read+write) accesses 3383system.l2c.overall_accesses::cpu0.data 861596 # number of overall (read+write) accesses 3384system.l2c.overall_accesses::cpu0.l2cache.prefetcher 538446 # number of overall (read+write) accesses 3385system.l2c.overall_accesses::cpu1.dtb.walker 9354 # number of overall (read+write) accesses 3386system.l2c.overall_accesses::cpu1.itb.walker 7180 # number of overall (read+write) accesses 3387system.l2c.overall_accesses::cpu1.inst 548074 # number of overall (read+write) accesses 3388system.l2c.overall_accesses::cpu1.data 797912 # number of overall (read+write) accesses 3389system.l2c.overall_accesses::cpu1.l2cache.prefetcher 542809 # number of overall (read+write) accesses 3390system.l2c.overall_accesses::total 3892589 # number of overall (read+write) accesses 3391system.l2c.UpgradeReq_miss_rate::cpu0.data 0.272383 # miss rate for UpgradeReq accesses 3392system.l2c.UpgradeReq_miss_rate::cpu1.data 0.319912 # miss rate for UpgradeReq accesses 3393system.l2c.UpgradeReq_miss_rate::total 0.293171 # miss rate for UpgradeReq accesses 3394system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.235967 # miss rate for SCUpgradeReq accesses 3395system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.220579 # miss rate for SCUpgradeReq accesses 3396system.l2c.SCUpgradeReq_miss_rate::total 0.228220 # miss rate for SCUpgradeReq accesses 3397system.l2c.ReadExReq_miss_rate::cpu0.data 0.580726 # miss rate for ReadExReq accesses 3398system.l2c.ReadExReq_miss_rate::cpu1.data 0.522866 # miss rate for ReadExReq accesses 3399system.l2c.ReadExReq_miss_rate::total 0.554386 # miss rate for ReadExReq accesses 3400system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.176448 # miss rate for ReadSharedReq accesses 3401system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.164351 # miss rate for ReadSharedReq accesses 3402system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.106194 # miss rate for ReadSharedReq accesses 3403system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.174614 # miss rate for ReadSharedReq accesses 3404system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.403485 # miss rate for ReadSharedReq accesses 3405system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.336647 # miss rate for ReadSharedReq accesses 3406system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.411978 # miss rate for ReadSharedReq accesses 3407system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.075669 # miss rate for ReadSharedReq accesses 3408system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.179887 # miss rate for ReadSharedReq accesses 3409system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.473222 # miss rate for ReadSharedReq accesses 3410system.l2c.ReadSharedReq_miss_rate::total 0.229019 # miss rate for ReadSharedReq accesses 3411system.l2c.InvalidateReq_miss_rate::cpu0.data 0.771353 # miss rate for InvalidateReq accesses 3412system.l2c.InvalidateReq_miss_rate::cpu1.data 0.508973 # miss rate for InvalidateReq accesses 3413system.l2c.InvalidateReq_miss_rate::total 0.692752 # miss rate for InvalidateReq accesses 3414system.l2c.demand_miss_rate::cpu0.dtb.walker 0.176448 # miss rate for demand accesses 3415system.l2c.demand_miss_rate::cpu0.itb.walker 0.164351 # miss rate for demand accesses 3416system.l2c.demand_miss_rate::cpu0.inst 0.106194 # miss rate for demand accesses 3417system.l2c.demand_miss_rate::cpu0.data 0.236643 # miss rate for demand accesses 3418system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.403485 # miss rate for demand accesses 3419system.l2c.demand_miss_rate::cpu1.dtb.walker 0.336647 # miss rate for demand accesses 3420system.l2c.demand_miss_rate::cpu1.itb.walker 0.411978 # miss rate for demand accesses 3421system.l2c.demand_miss_rate::cpu1.inst 0.075669 # miss rate for demand accesses 3422system.l2c.demand_miss_rate::cpu1.data 0.227157 # miss rate for demand accesses 3423system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.473222 # miss rate for demand accesses 3424system.l2c.demand_miss_rate::total 0.249211 # miss rate for demand accesses 3425system.l2c.overall_miss_rate::cpu0.dtb.walker 0.176448 # miss rate for overall accesses 3426system.l2c.overall_miss_rate::cpu0.itb.walker 0.164351 # miss rate for overall accesses 3427system.l2c.overall_miss_rate::cpu0.inst 0.106194 # miss rate for overall accesses 3428system.l2c.overall_miss_rate::cpu0.data 0.236643 # miss rate for overall accesses 3429system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.403485 # miss rate for overall accesses 3430system.l2c.overall_miss_rate::cpu1.dtb.walker 0.336647 # miss rate for overall accesses 3431system.l2c.overall_miss_rate::cpu1.itb.walker 0.411978 # miss rate for overall accesses 3432system.l2c.overall_miss_rate::cpu1.inst 0.075669 # miss rate for overall accesses 3433system.l2c.overall_miss_rate::cpu1.data 0.227157 # miss rate for overall accesses 3434system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.473222 # miss rate for overall accesses 3435system.l2c.overall_miss_rate::total 0.249211 # miss rate for overall accesses 3436system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6816.778116 # average UpgradeReq miss latency 3437system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6502.813103 # average UpgradeReq miss latency 3438system.l2c.UpgradeReq_avg_miss_latency::total 6666.934126 # average UpgradeReq miss latency 3439system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6061.178002 # average SCUpgradeReq miss latency 3440system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6457.342717 # average SCUpgradeReq miss latency 3441system.l2c.SCUpgradeReq_avg_miss_latency::total 6253.957315 # average SCUpgradeReq miss latency 3442system.l2c.ReadExReq_avg_miss_latency::cpu0.data 90779.163158 # average ReadExReq miss latency 3443system.l2c.ReadExReq_avg_miss_latency::cpu1.data 90419.737700 # average ReadExReq miss latency 3444system.l2c.ReadExReq_avg_miss_latency::total 90624.844940 # average ReadExReq miss latency 3445system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 95613.405797 # average ReadSharedReq miss latency 3446system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 93498.902305 # average ReadSharedReq miss latency 3447system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 87314.169675 # average ReadSharedReq miss latency 3448system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 94365.521103 # average ReadSharedReq miss latency 3449system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 140476.926892 # average ReadSharedReq miss latency 3450system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92095.903461 # average ReadSharedReq miss latency 3451system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 89805.949966 # average ReadSharedReq miss latency 3452system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 88080.958237 # average ReadSharedReq miss latency 3453system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 96410.595360 # average ReadSharedReq miss latency 3454system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 137707.635285 # average ReadSharedReq miss latency 3455system.l2c.ReadSharedReq_avg_miss_latency::total 119114.809665 # average ReadSharedReq miss latency 3456system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 128.983584 # average InvalidateReq miss latency 3457system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 387.255515 # average InvalidateReq miss latency 3458system.l2c.InvalidateReq_avg_miss_latency::total 185.828833 # average InvalidateReq miss latency 3459system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 95613.405797 # average overall miss latency 3460system.l2c.demand_avg_miss_latency::cpu0.itb.walker 93498.902305 # average overall miss latency 3461system.l2c.demand_avg_miss_latency::cpu0.inst 87314.169675 # average overall miss latency 3462system.l2c.demand_avg_miss_latency::cpu0.data 93021.272297 # average overall miss latency 3463system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 140476.926892 # average overall miss latency 3464system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92095.903461 # average overall miss latency 3465system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89805.949966 # average overall miss latency 3466system.l2c.demand_avg_miss_latency::cpu1.inst 88080.958237 # average overall miss latency 3467system.l2c.demand_avg_miss_latency::cpu1.data 94510.090951 # average overall miss latency 3468system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 137707.635285 # average overall miss latency 3469system.l2c.demand_avg_miss_latency::total 115181.681688 # average overall miss latency 3470system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 95613.405797 # average overall miss latency 3471system.l2c.overall_avg_miss_latency::cpu0.itb.walker 93498.902305 # average overall miss latency 3472system.l2c.overall_avg_miss_latency::cpu0.inst 87314.169675 # average overall miss latency 3473system.l2c.overall_avg_miss_latency::cpu0.data 93021.272297 # average overall miss latency 3474system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 140476.926892 # average overall miss latency 3475system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92095.903461 # average overall miss latency 3476system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89805.949966 # average overall miss latency 3477system.l2c.overall_avg_miss_latency::cpu1.inst 88080.958237 # average overall miss latency 3478system.l2c.overall_avg_miss_latency::cpu1.data 94510.090951 # average overall miss latency 3479system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 137707.635285 # average overall miss latency 3480system.l2c.overall_avg_miss_latency::total 115181.681688 # average overall miss latency 3481system.l2c.blocked_cycles::no_mshrs 9550 # number of cycles access was blocked |
| 3513system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked | 3482system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 3514system.l2c.blocked::no_mshrs 177 # number of cycles access was blocked | 3483system.l2c.blocked::no_mshrs 102 # number of cycles access was blocked |
| 3515system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 3484system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 3516system.l2c.avg_blocked_cycles::no_mshrs 89.960452 # average number of cycles each access was blocked | 3485system.l2c.avg_blocked_cycles::no_mshrs 93.627451 # average number of cycles each access was blocked |
| 3517system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 3486system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 3518system.l2c.writebacks::writebacks 1312187 # number of writebacks 3519system.l2c.writebacks::total 1312187 # number of writebacks 3520system.l2c.ReadSharedReq_mshr_hits::cpu0.dtb.walker 3 # number of ReadSharedReq MSHR hits 3521system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 163 # number of ReadSharedReq MSHR hits 3522system.l2c.ReadSharedReq_mshr_hits::cpu0.data 34 # number of ReadSharedReq MSHR hits 3523system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 114 # number of ReadSharedReq MSHR hits 3524system.l2c.ReadSharedReq_mshr_hits::cpu1.data 21 # number of ReadSharedReq MSHR hits 3525system.l2c.ReadSharedReq_mshr_hits::total 335 # number of ReadSharedReq MSHR hits 3526system.l2c.demand_mshr_hits::cpu0.dtb.walker 3 # number of demand (read+write) MSHR hits 3527system.l2c.demand_mshr_hits::cpu0.inst 163 # number of demand (read+write) MSHR hits 3528system.l2c.demand_mshr_hits::cpu0.data 34 # number of demand (read+write) MSHR hits 3529system.l2c.demand_mshr_hits::cpu1.inst 114 # number of demand (read+write) MSHR hits 3530system.l2c.demand_mshr_hits::cpu1.data 21 # number of demand (read+write) MSHR hits 3531system.l2c.demand_mshr_hits::total 335 # number of demand (read+write) MSHR hits 3532system.l2c.overall_mshr_hits::cpu0.dtb.walker 3 # number of overall MSHR hits 3533system.l2c.overall_mshr_hits::cpu0.inst 163 # number of overall MSHR hits 3534system.l2c.overall_mshr_hits::cpu0.data 34 # number of overall MSHR hits 3535system.l2c.overall_mshr_hits::cpu1.inst 114 # number of overall MSHR hits 3536system.l2c.overall_mshr_hits::cpu1.data 21 # number of overall MSHR hits 3537system.l2c.overall_mshr_hits::total 335 # number of overall MSHR hits 3538system.l2c.CleanEvict_mshr_misses::writebacks 62188 # number of CleanEvict MSHR misses 3539system.l2c.CleanEvict_mshr_misses::total 62188 # number of CleanEvict MSHR misses 3540system.l2c.UpgradeReq_mshr_misses::cpu0.data 62380 # number of UpgradeReq MSHR misses 3541system.l2c.UpgradeReq_mshr_misses::cpu1.data 67853 # number of UpgradeReq MSHR misses 3542system.l2c.UpgradeReq_mshr_misses::total 130233 # number of UpgradeReq MSHR misses 3543system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 11700 # number of SCUpgradeReq MSHR misses 3544system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 13195 # number of SCUpgradeReq MSHR misses 3545system.l2c.SCUpgradeReq_mshr_misses::total 24895 # number of SCUpgradeReq MSHR misses 3546system.l2c.ReadExReq_mshr_misses::cpu0.data 82725 # number of ReadExReq MSHR misses 3547system.l2c.ReadExReq_mshr_misses::cpu1.data 61895 # number of ReadExReq MSHR misses 3548system.l2c.ReadExReq_mshr_misses::total 144620 # number of ReadExReq MSHR misses 3549system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2674 # number of ReadSharedReq MSHR misses 3550system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1890 # number of ReadSharedReq MSHR misses 3551system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 55014 # number of ReadSharedReq MSHR misses 3552system.l2c.ReadSharedReq_mshr_misses::cpu0.data 140044 # number of ReadSharedReq MSHR misses 3553system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 275934 # number of ReadSharedReq MSHR misses 3554system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 3410 # number of ReadSharedReq MSHR misses 3555system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 3269 # number of ReadSharedReq MSHR misses 3556system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 56593 # number of ReadSharedReq MSHR misses 3557system.l2c.ReadSharedReq_mshr_misses::cpu1.data 154796 # number of ReadSharedReq MSHR misses 3558system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 324363 # number of ReadSharedReq MSHR misses 3559system.l2c.ReadSharedReq_mshr_misses::total 1017987 # number of ReadSharedReq MSHR misses 3560system.l2c.InvalidateReq_mshr_misses::cpu0.data 452102 # number of InvalidateReq MSHR misses 3561system.l2c.InvalidateReq_mshr_misses::cpu1.data 148246 # number of InvalidateReq MSHR misses 3562system.l2c.InvalidateReq_mshr_misses::total 600348 # number of InvalidateReq MSHR misses 3563system.l2c.demand_mshr_misses::cpu0.dtb.walker 2674 # number of demand (read+write) MSHR misses 3564system.l2c.demand_mshr_misses::cpu0.itb.walker 1890 # number of demand (read+write) MSHR misses 3565system.l2c.demand_mshr_misses::cpu0.inst 55014 # number of demand (read+write) MSHR misses 3566system.l2c.demand_mshr_misses::cpu0.data 222769 # number of demand (read+write) MSHR misses 3567system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 275934 # number of demand (read+write) MSHR misses 3568system.l2c.demand_mshr_misses::cpu1.dtb.walker 3410 # number of demand (read+write) MSHR misses 3569system.l2c.demand_mshr_misses::cpu1.itb.walker 3269 # number of demand (read+write) MSHR misses 3570system.l2c.demand_mshr_misses::cpu1.inst 56593 # number of demand (read+write) MSHR misses 3571system.l2c.demand_mshr_misses::cpu1.data 216691 # number of demand (read+write) MSHR misses 3572system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 324363 # number of demand (read+write) MSHR misses 3573system.l2c.demand_mshr_misses::total 1162607 # number of demand (read+write) MSHR misses 3574system.l2c.overall_mshr_misses::cpu0.dtb.walker 2674 # number of overall MSHR misses 3575system.l2c.overall_mshr_misses::cpu0.itb.walker 1890 # number of overall MSHR misses 3576system.l2c.overall_mshr_misses::cpu0.inst 55014 # number of overall MSHR misses 3577system.l2c.overall_mshr_misses::cpu0.data 222769 # number of overall MSHR misses 3578system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 275934 # number of overall MSHR misses 3579system.l2c.overall_mshr_misses::cpu1.dtb.walker 3410 # number of overall MSHR misses 3580system.l2c.overall_mshr_misses::cpu1.itb.walker 3269 # number of overall MSHR misses 3581system.l2c.overall_mshr_misses::cpu1.inst 56593 # number of overall MSHR misses 3582system.l2c.overall_mshr_misses::cpu1.data 216691 # number of overall MSHR misses 3583system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 324363 # number of overall MSHR misses 3584system.l2c.overall_mshr_misses::total 1162607 # number of overall MSHR misses | 3487system.l2c.writebacks::writebacks 1135323 # number of writebacks 3488system.l2c.writebacks::total 1135323 # number of writebacks 3489system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 111 # number of ReadSharedReq MSHR hits 3490system.l2c.ReadSharedReq_mshr_hits::cpu0.data 20 # number of ReadSharedReq MSHR hits 3491system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 109 # number of ReadSharedReq MSHR hits 3492system.l2c.ReadSharedReq_mshr_hits::cpu1.data 8 # number of ReadSharedReq MSHR hits 3493system.l2c.ReadSharedReq_mshr_hits::total 248 # number of ReadSharedReq MSHR hits 3494system.l2c.demand_mshr_hits::cpu0.inst 111 # number of demand (read+write) MSHR hits 3495system.l2c.demand_mshr_hits::cpu0.data 20 # number of demand (read+write) MSHR hits 3496system.l2c.demand_mshr_hits::cpu1.inst 109 # number of demand (read+write) MSHR hits 3497system.l2c.demand_mshr_hits::cpu1.data 8 # number of demand (read+write) MSHR hits 3498system.l2c.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits 3499system.l2c.overall_mshr_hits::cpu0.inst 111 # number of overall MSHR hits 3500system.l2c.overall_mshr_hits::cpu0.data 20 # number of overall MSHR hits 3501system.l2c.overall_mshr_hits::cpu1.inst 109 # number of overall MSHR hits 3502system.l2c.overall_mshr_hits::cpu1.data 8 # number of overall MSHR hits 3503system.l2c.overall_mshr_hits::total 248 # number of overall MSHR hits 3504system.l2c.CleanEvict_mshr_misses::writebacks 49298 # number of CleanEvict MSHR misses 3505system.l2c.CleanEvict_mshr_misses::total 49298 # number of CleanEvict MSHR misses 3506system.l2c.UpgradeReq_mshr_misses::cpu0.data 65800 # number of UpgradeReq MSHR misses 3507system.l2c.UpgradeReq_mshr_misses::cpu1.data 60076 # number of UpgradeReq MSHR misses 3508system.l2c.UpgradeReq_mshr_misses::total 125876 # number of UpgradeReq MSHR misses 3509system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12292 # number of SCUpgradeReq MSHR misses 3510system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11651 # number of SCUpgradeReq MSHR misses 3511system.l2c.SCUpgradeReq_mshr_misses::total 23943 # number of SCUpgradeReq MSHR misses 3512system.l2c.ReadExReq_mshr_misses::cpu0.data 76423 # number of ReadExReq MSHR misses 3513system.l2c.ReadExReq_mshr_misses::cpu1.data 57499 # number of ReadExReq MSHR misses 3514system.l2c.ReadExReq_mshr_misses::total 133922 # number of ReadExReq MSHR misses 3515system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1380 # number of ReadSharedReq MSHR misses 3516system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 911 # number of ReadSharedReq MSHR misses 3517system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 60829 # number of ReadSharedReq MSHR misses 3518system.l2c.ReadSharedReq_mshr_misses::cpu0.data 127448 # number of ReadSharedReq MSHR misses 3519system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 217255 # number of ReadSharedReq MSHR misses 3520system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 3149 # number of ReadSharedReq MSHR misses 3521system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2958 # number of ReadSharedReq MSHR misses 3522system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 41363 # number of ReadSharedReq MSHR misses 3523system.l2c.ReadSharedReq_mshr_misses::cpu1.data 123744 # number of ReadSharedReq MSHR misses 3524system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 256869 # number of ReadSharedReq MSHR misses 3525system.l2c.ReadSharedReq_mshr_misses::total 835906 # number of ReadSharedReq MSHR misses 3526system.l2c.InvalidateReq_mshr_misses::cpu0.data 453643 # number of InvalidateReq MSHR misses 3527system.l2c.InvalidateReq_mshr_misses::cpu1.data 128024 # number of InvalidateReq MSHR misses 3528system.l2c.InvalidateReq_mshr_misses::total 581667 # number of InvalidateReq MSHR misses 3529system.l2c.demand_mshr_misses::cpu0.dtb.walker 1380 # number of demand (read+write) MSHR misses 3530system.l2c.demand_mshr_misses::cpu0.itb.walker 911 # number of demand (read+write) MSHR misses 3531system.l2c.demand_mshr_misses::cpu0.inst 60829 # number of demand (read+write) MSHR misses 3532system.l2c.demand_mshr_misses::cpu0.data 203871 # number of demand (read+write) MSHR misses 3533system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 217255 # number of demand (read+write) MSHR misses 3534system.l2c.demand_mshr_misses::cpu1.dtb.walker 3149 # number of demand (read+write) MSHR misses 3535system.l2c.demand_mshr_misses::cpu1.itb.walker 2958 # number of demand (read+write) MSHR misses 3536system.l2c.demand_mshr_misses::cpu1.inst 41363 # number of demand (read+write) MSHR misses 3537system.l2c.demand_mshr_misses::cpu1.data 181243 # number of demand (read+write) MSHR misses 3538system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 256869 # number of demand (read+write) MSHR misses 3539system.l2c.demand_mshr_misses::total 969828 # number of demand (read+write) MSHR misses 3540system.l2c.overall_mshr_misses::cpu0.dtb.walker 1380 # number of overall MSHR misses 3541system.l2c.overall_mshr_misses::cpu0.itb.walker 911 # number of overall MSHR misses 3542system.l2c.overall_mshr_misses::cpu0.inst 60829 # number of overall MSHR misses 3543system.l2c.overall_mshr_misses::cpu0.data 203871 # number of overall MSHR misses 3544system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 217255 # number of overall MSHR misses 3545system.l2c.overall_mshr_misses::cpu1.dtb.walker 3149 # number of overall MSHR misses 3546system.l2c.overall_mshr_misses::cpu1.itb.walker 2958 # number of overall MSHR misses 3547system.l2c.overall_mshr_misses::cpu1.inst 41363 # number of overall MSHR misses 3548system.l2c.overall_mshr_misses::cpu1.data 181243 # number of overall MSHR misses 3549system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 256869 # number of overall MSHR misses 3550system.l2c.overall_mshr_misses::total 969828 # number of overall MSHR misses |
| 3585system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable | 3551system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable |
| 3586system.l2c.ReadReq_mshr_uncacheable::cpu0.data 19706 # number of ReadReq MSHR uncacheable | 3552system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32527 # number of ReadReq MSHR uncacheable |
| 3587system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable | 3553system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable |
| 3588system.l2c.ReadReq_mshr_uncacheable::cpu1.data 18699 # number of ReadReq MSHR uncacheable 3589system.l2c.ReadReq_mshr_uncacheable::total 59765 # number of ReadReq MSHR uncacheable 3590system.l2c.WriteReq_mshr_uncacheable::cpu0.data 21266 # number of WriteReq MSHR uncacheable 3591system.l2c.WriteReq_mshr_uncacheable::cpu1.data 17029 # number of WriteReq MSHR uncacheable 3592system.l2c.WriteReq_mshr_uncacheable::total 38295 # number of WriteReq MSHR uncacheable | 3554system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6116 # number of ReadReq MSHR uncacheable 3555system.l2c.ReadReq_mshr_uncacheable::total 60003 # number of ReadReq MSHR uncacheable 3556system.l2c.WriteReq_mshr_uncacheable::cpu0.data 32351 # number of WriteReq MSHR uncacheable 3557system.l2c.WriteReq_mshr_uncacheable::cpu1.data 6183 # number of WriteReq MSHR uncacheable 3558system.l2c.WriteReq_mshr_uncacheable::total 38534 # number of WriteReq MSHR uncacheable |
| 3593system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses | 3559system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses |
| 3594system.l2c.overall_mshr_uncacheable_misses::cpu0.data 40972 # number of overall MSHR uncacheable misses | 3560system.l2c.overall_mshr_uncacheable_misses::cpu0.data 64878 # number of overall MSHR uncacheable misses |
| 3595system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses | 3561system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses |
| 3596system.l2c.overall_mshr_uncacheable_misses::cpu1.data 35728 # number of overall MSHR uncacheable misses 3597system.l2c.overall_mshr_uncacheable_misses::total 98060 # number of overall MSHR uncacheable misses 3598system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4409168995 # number of UpgradeReq MSHR miss cycles 3599system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4786348998 # number of UpgradeReq MSHR miss cycles 3600system.l2c.UpgradeReq_mshr_miss_latency::total 9195517993 # number of UpgradeReq MSHR miss cycles 3601system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 862109992 # number of SCUpgradeReq MSHR miss cycles 3602system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 970555497 # number of SCUpgradeReq MSHR miss cycles 3603system.l2c.SCUpgradeReq_mshr_miss_latency::total 1832665489 # number of SCUpgradeReq MSHR miss cycles 3604system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10883415957 # number of ReadExReq MSHR miss cycles 3605system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 8157375512 # number of ReadExReq MSHR miss cycles 3606system.l2c.ReadExReq_mshr_miss_latency::total 19040791469 # number of ReadExReq MSHR miss cycles 3607system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 357690038 # number of ReadSharedReq MSHR miss cycles 3608system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 252601028 # number of ReadSharedReq MSHR miss cycles 3609system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 7044725224 # number of ReadSharedReq MSHR miss cycles 3610system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19335135004 # number of ReadSharedReq MSHR miss cycles 3611system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 48855278506 # number of ReadSharedReq MSHR miss cycles 3612system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 450944507 # number of ReadSharedReq MSHR miss cycles 3613system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 420472009 # number of ReadSharedReq MSHR miss cycles 3614system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 7214941938 # number of ReadSharedReq MSHR miss cycles 3615system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 21149813267 # number of ReadSharedReq MSHR miss cycles 3616system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 56812837096 # number of ReadSharedReq MSHR miss cycles 3617system.l2c.ReadSharedReq_mshr_miss_latency::total 161894438617 # number of ReadSharedReq MSHR miss cycles 3618system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 31769945999 # number of InvalidateReq MSHR miss cycles 3619system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 10316729000 # number of InvalidateReq MSHR miss cycles 3620system.l2c.InvalidateReq_mshr_miss_latency::total 42086674999 # number of InvalidateReq MSHR miss cycles 3621system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 357690038 # number of demand (read+write) MSHR miss cycles 3622system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 252601028 # number of demand (read+write) MSHR miss cycles 3623system.l2c.demand_mshr_miss_latency::cpu0.inst 7044725224 # number of demand (read+write) MSHR miss cycles 3624system.l2c.demand_mshr_miss_latency::cpu0.data 30218550961 # number of demand (read+write) MSHR miss cycles 3625system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 48855278506 # number of demand (read+write) MSHR miss cycles 3626system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 450944507 # number of demand (read+write) MSHR miss cycles 3627system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 420472009 # number of demand (read+write) MSHR miss cycles 3628system.l2c.demand_mshr_miss_latency::cpu1.inst 7214941938 # number of demand (read+write) MSHR miss cycles 3629system.l2c.demand_mshr_miss_latency::cpu1.data 29307188779 # number of demand (read+write) MSHR miss cycles 3630system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 56812837096 # number of demand (read+write) MSHR miss cycles 3631system.l2c.demand_mshr_miss_latency::total 180935230086 # number of demand (read+write) MSHR miss cycles 3632system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 357690038 # number of overall MSHR miss cycles 3633system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 252601028 # number of overall MSHR miss cycles 3634system.l2c.overall_mshr_miss_latency::cpu0.inst 7044725224 # number of overall MSHR miss cycles 3635system.l2c.overall_mshr_miss_latency::cpu0.data 30218550961 # number of overall MSHR miss cycles 3636system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 48855278506 # number of overall MSHR miss cycles 3637system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 450944507 # number of overall MSHR miss cycles 3638system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 420472009 # number of overall MSHR miss cycles 3639system.l2c.overall_mshr_miss_latency::cpu1.inst 7214941938 # number of overall MSHR miss cycles 3640system.l2c.overall_mshr_miss_latency::cpu1.data 29307188779 # number of overall MSHR miss cycles 3641system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 56812837096 # number of overall MSHR miss cycles 3642system.l2c.overall_mshr_miss_latency::total 180935230086 # number of overall MSHR miss cycles 3643system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2396807500 # number of ReadReq MSHR uncacheable cycles 3644system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3350562534 # number of ReadReq MSHR uncacheable cycles 3645system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7247500 # number of ReadReq MSHR uncacheable cycles 3646system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2551834016 # number of ReadReq MSHR uncacheable cycles 3647system.l2c.ReadReq_mshr_uncacheable_latency::total 8306451550 # number of ReadReq MSHR uncacheable cycles 3648system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2396807500 # number of overall MSHR uncacheable cycles 3649system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3350562534 # number of overall MSHR uncacheable cycles 3650system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7247500 # number of overall MSHR uncacheable cycles 3651system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2551834016 # number of overall MSHR uncacheable cycles 3652system.l2c.overall_mshr_uncacheable_latency::total 8306451550 # number of overall MSHR uncacheable cycles | 3562system.l2c.overall_mshr_uncacheable_misses::cpu1.data 12299 # number of overall MSHR uncacheable misses 3563system.l2c.overall_mshr_uncacheable_misses::total 98537 # number of overall MSHR uncacheable misses 3564system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1434481502 # number of UpgradeReq MSHR miss cycles 3565system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1290497995 # number of UpgradeReq MSHR miss cycles 3566system.l2c.UpgradeReq_mshr_miss_latency::total 2724979497 # number of UpgradeReq MSHR miss cycles 3567system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 303964499 # number of SCUpgradeReq MSHR miss cycles 3568system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 285788496 # number of SCUpgradeReq MSHR miss cycles 3569system.l2c.SCUpgradeReq_mshr_miss_latency::total 589752995 # number of SCUpgradeReq MSHR miss cycles 3570system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6173210845 # number of ReadExReq MSHR miss cycles 3571system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4623959192 # number of ReadExReq MSHR miss cycles 3572system.l2c.ReadExReq_mshr_miss_latency::total 10797170037 # number of ReadExReq MSHR miss cycles 3573system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 118145502 # number of ReadSharedReq MSHR miss cycles 3574system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 76067500 # number of ReadSharedReq MSHR miss cycles 3575system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 4704505587 # number of ReadSharedReq MSHR miss cycles 3576system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 10752452984 # number of ReadSharedReq MSHR miss cycles 3577system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 28346572172 # number of ReadSharedReq MSHR miss cycles 3578system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 258517505 # number of ReadSharedReq MSHR miss cycles 3579system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 236065501 # number of ReadSharedReq MSHR miss cycles 3580system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3231267055 # number of ReadSharedReq MSHR miss cycles 3581system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 10692827748 # number of ReadSharedReq MSHR miss cycles 3582system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 32803939514 # number of ReadSharedReq MSHR miss cycles 3583system.l2c.ReadSharedReq_mshr_miss_latency::total 91220361068 # number of ReadSharedReq MSHR miss cycles 3584system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 11449259098 # number of InvalidateReq MSHR miss cycles 3585system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2669880500 # number of InvalidateReq MSHR miss cycles 3586system.l2c.InvalidateReq_mshr_miss_latency::total 14119139598 # number of InvalidateReq MSHR miss cycles 3587system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 118145502 # number of demand (read+write) MSHR miss cycles 3588system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 76067500 # number of demand (read+write) MSHR miss cycles 3589system.l2c.demand_mshr_miss_latency::cpu0.inst 4704505587 # number of demand (read+write) MSHR miss cycles 3590system.l2c.demand_mshr_miss_latency::cpu0.data 16925663829 # number of demand (read+write) MSHR miss cycles 3591system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 28346572172 # number of demand (read+write) MSHR miss cycles 3592system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 258517505 # number of demand (read+write) MSHR miss cycles 3593system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 236065501 # number of demand (read+write) MSHR miss cycles 3594system.l2c.demand_mshr_miss_latency::cpu1.inst 3231267055 # number of demand (read+write) MSHR miss cycles 3595system.l2c.demand_mshr_miss_latency::cpu1.data 15316786940 # number of demand (read+write) MSHR miss cycles 3596system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 32803939514 # number of demand (read+write) MSHR miss cycles 3597system.l2c.demand_mshr_miss_latency::total 102017531105 # number of demand (read+write) MSHR miss cycles 3598system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 118145502 # number of overall MSHR miss cycles 3599system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 76067500 # number of overall MSHR miss cycles 3600system.l2c.overall_mshr_miss_latency::cpu0.inst 4704505587 # number of overall MSHR miss cycles 3601system.l2c.overall_mshr_miss_latency::cpu0.data 16925663829 # number of overall MSHR miss cycles 3602system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 28346572172 # number of overall MSHR miss cycles 3603system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 258517505 # number of overall MSHR miss cycles 3604system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 236065501 # number of overall MSHR miss cycles 3605system.l2c.overall_mshr_miss_latency::cpu1.inst 3231267055 # number of overall MSHR miss cycles 3606system.l2c.overall_mshr_miss_latency::cpu1.data 15316786940 # number of overall MSHR miss cycles 3607system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 32803939514 # number of overall MSHR miss cycles 3608system.l2c.overall_mshr_miss_latency::total 102017531105 # number of overall MSHR miss cycles 3609system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1342704500 # number of ReadReq MSHR uncacheable cycles 3610system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5362205005 # number of ReadReq MSHR uncacheable cycles 3611system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5079500 # number of ReadReq MSHR uncacheable cycles 3612system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 590567503 # number of ReadReq MSHR uncacheable cycles 3613system.l2c.ReadReq_mshr_uncacheable_latency::total 7300556508 # number of ReadReq MSHR uncacheable cycles 3614system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1342704500 # number of overall MSHR uncacheable cycles 3615system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5362205005 # number of overall MSHR uncacheable cycles 3616system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5079500 # number of overall MSHR uncacheable cycles 3617system.l2c.overall_mshr_uncacheable_latency::cpu1.data 590567503 # number of overall MSHR uncacheable cycles 3618system.l2c.overall_mshr_uncacheable_latency::total 7300556508 # number of overall MSHR uncacheable cycles |
| 3653system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3654system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses | 3619system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3620system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| 3655system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.259851 # mshr miss rate for UpgradeReq accesses 3656system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.309227 # mshr miss rate for UpgradeReq accesses 3657system.l2c.UpgradeReq_mshr_miss_rate::total 0.283430 # mshr miss rate for UpgradeReq accesses 3658system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.232975 # mshr miss rate for SCUpgradeReq accesses 3659system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.222303 # mshr miss rate for SCUpgradeReq accesses 3660system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.227194 # mshr miss rate for SCUpgradeReq accesses 3661system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.586532 # mshr miss rate for ReadExReq accesses 3662system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.521164 # mshr miss rate for ReadExReq accesses 3663system.l2c.ReadExReq_mshr_miss_rate::total 0.556650 # mshr miss rate for ReadExReq accesses 3664system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.291190 # mshr miss rate for ReadSharedReq accesses 3665system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.284424 # mshr miss rate for ReadSharedReq accesses 3666system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.098174 # mshr miss rate for ReadSharedReq accesses 3667system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.181894 # mshr miss rate for ReadSharedReq accesses 3668system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.476117 # mshr miss rate for ReadSharedReq accesses 3669system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.339405 # mshr miss rate for ReadSharedReq accesses 3670system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.427712 # mshr miss rate for ReadSharedReq accesses 3671system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.090605 # mshr miss rate for ReadSharedReq accesses 3672system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.192512 # mshr miss rate for ReadSharedReq accesses 3673system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.515876 # mshr miss rate for ReadSharedReq accesses 3674system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254444 # mshr miss rate for ReadSharedReq accesses 3675system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.770350 # mshr miss rate for InvalidateReq accesses 3676system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.537073 # mshr miss rate for InvalidateReq accesses 3677system.l2c.InvalidateReq_mshr_miss_rate::total 0.695729 # mshr miss rate for InvalidateReq accesses 3678system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.291190 # mshr miss rate for demand accesses 3679system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.284424 # mshr miss rate for demand accesses 3680system.l2c.demand_mshr_miss_rate::cpu0.inst 0.098174 # mshr miss rate for demand accesses 3681system.l2c.demand_mshr_miss_rate::cpu0.data 0.244543 # mshr miss rate for demand accesses 3682system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.476117 # mshr miss rate for demand accesses 3683system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.339405 # mshr miss rate for demand accesses 3684system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.427712 # mshr miss rate for demand accesses 3685system.l2c.demand_mshr_miss_rate::cpu1.inst 0.090605 # mshr miss rate for demand accesses 3686system.l2c.demand_mshr_miss_rate::cpu1.data 0.234807 # mshr miss rate for demand accesses 3687system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.515876 # mshr miss rate for demand accesses 3688system.l2c.demand_mshr_miss_rate::total 0.272872 # mshr miss rate for demand accesses 3689system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.291190 # mshr miss rate for overall accesses 3690system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.284424 # mshr miss rate for overall accesses 3691system.l2c.overall_mshr_miss_rate::cpu0.inst 0.098174 # mshr miss rate for overall accesses 3692system.l2c.overall_mshr_miss_rate::cpu0.data 0.244543 # mshr miss rate for overall accesses 3693system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.476117 # mshr miss rate for overall accesses 3694system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.339405 # mshr miss rate for overall accesses 3695system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.427712 # mshr miss rate for overall accesses 3696system.l2c.overall_mshr_miss_rate::cpu1.inst 0.090605 # mshr miss rate for overall accesses 3697system.l2c.overall_mshr_miss_rate::cpu1.data 0.234807 # mshr miss rate for overall accesses 3698system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.515876 # mshr miss rate for overall accesses 3699system.l2c.overall_mshr_miss_rate::total 0.272872 # mshr miss rate for overall accesses 3700system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70682.414155 # average UpgradeReq mshr miss latency 3701system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70539.976095 # average UpgradeReq mshr miss latency 3702system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70608.202168 # average UpgradeReq mshr miss latency 3703system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73684.614701 # average SCUpgradeReq mshr miss latency 3704system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73554.793255 # average SCUpgradeReq mshr miss latency 3705system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73615.805945 # average SCUpgradeReq mshr miss latency 3706system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 131561.389628 # average ReadExReq mshr miss latency 3707system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 131793.771904 # average ReadExReq mshr miss latency 3708system.l2c.ReadExReq_avg_mshr_miss_latency::total 131660.845450 # average ReadExReq mshr miss latency 3709system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 133765.908003 # average ReadSharedReq mshr miss latency 3710system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 133651.337566 # average ReadSharedReq mshr miss latency 3711system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 128053.317774 # average ReadSharedReq mshr miss latency 3712system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 138064.715404 # average ReadSharedReq mshr miss latency 3713system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177054.217697 # average ReadSharedReq mshr miss latency 3714system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 132241.790909 # average ReadSharedReq mshr miss latency 3715system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 128624.046803 # average ReadSharedReq mshr miss latency 3716system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127488.239500 # average ReadSharedReq mshr miss latency 3717system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 136630.231188 # average ReadSharedReq mshr miss latency 3718system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175152.027500 # average ReadSharedReq mshr miss latency 3719system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 159033.895931 # average ReadSharedReq mshr miss latency 3720system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70271.633390 # average InvalidateReq mshr miss latency 3721system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69591.955264 # average InvalidateReq mshr miss latency 3722system.l2c.InvalidateReq_avg_mshr_miss_latency::total 70103.798129 # average InvalidateReq mshr miss latency 3723system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 133765.908003 # average overall mshr miss latency 3724system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 133651.337566 # average overall mshr miss latency 3725system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 128053.317774 # average overall mshr miss latency 3726system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135649.713205 # average overall mshr miss latency 3727system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177054.217697 # average overall mshr miss latency 3728system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 132241.790909 # average overall mshr miss latency 3729system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128624.046803 # average overall mshr miss latency 3730system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127488.239500 # average overall mshr miss latency 3731system.l2c.demand_avg_mshr_miss_latency::cpu1.data 135248.758735 # average overall mshr miss latency 3732system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175152.027500 # average overall mshr miss latency 3733system.l2c.demand_avg_mshr_miss_latency::total 155628.884125 # average overall mshr miss latency 3734system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 133765.908003 # average overall mshr miss latency 3735system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 133651.337566 # average overall mshr miss latency 3736system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 128053.317774 # average overall mshr miss latency 3737system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135649.713205 # average overall mshr miss latency 3738system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177054.217697 # average overall mshr miss latency 3739system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 132241.790909 # average overall mshr miss latency 3740system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128624.046803 # average overall mshr miss latency 3741system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127488.239500 # average overall mshr miss latency 3742system.l2c.overall_avg_mshr_miss_latency::cpu1.data 135248.758735 # average overall mshr miss latency 3743system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175152.027500 # average overall mshr miss latency 3744system.l2c.overall_avg_mshr_miss_latency::total 155628.884125 # average overall mshr miss latency 3745system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.166299 # average ReadReq mshr uncacheable latency 3746system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170027.531412 # average ReadReq mshr uncacheable latency 3747system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108171.641791 # average ReadReq mshr uncacheable latency 3748system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136469.009894 # average ReadReq mshr uncacheable latency 3749system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138985.217937 # average ReadReq mshr uncacheable latency 3750system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.166299 # average overall mshr uncacheable latency 3751system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 81776.885043 # average overall mshr uncacheable latency 3752system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108171.641791 # average overall mshr uncacheable latency 3753system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 71423.925661 # average overall mshr uncacheable latency 3754system.l2c.overall_avg_mshr_uncacheable_latency::total 84707.847746 # average overall mshr uncacheable latency 3755system.membus.trans_dist::ReadReq 59765 # Transaction distribution 3756system.membus.trans_dist::ReadResp 1086669 # Transaction distribution 3757system.membus.trans_dist::WriteReq 38295 # Transaction distribution 3758system.membus.trans_dist::WriteResp 38295 # Transaction distribution 3759system.membus.trans_dist::WritebackDirty 1418881 # Transaction distribution 3760system.membus.trans_dist::CleanEvict 277094 # Transaction distribution 3761system.membus.trans_dist::UpgradeReq 441724 # Transaction distribution 3762system.membus.trans_dist::SCUpgradeReq 308123 # Transaction distribution | 3621system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.272383 # mshr miss rate for UpgradeReq accesses 3622system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.319912 # mshr miss rate for UpgradeReq accesses 3623system.l2c.UpgradeReq_mshr_miss_rate::total 0.293171 # mshr miss rate for UpgradeReq accesses 3624system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.235967 # mshr miss rate for SCUpgradeReq accesses 3625system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.220579 # mshr miss rate for SCUpgradeReq accesses 3626system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.228220 # mshr miss rate for SCUpgradeReq accesses 3627system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.580726 # mshr miss rate for ReadExReq accesses 3628system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.522866 # mshr miss rate for ReadExReq accesses 3629system.l2c.ReadExReq_mshr_miss_rate::total 0.554386 # mshr miss rate for ReadExReq accesses 3630system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.176448 # mshr miss rate for ReadSharedReq accesses 3631system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.164351 # mshr miss rate for ReadSharedReq accesses 3632system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.106001 # mshr miss rate for ReadSharedReq accesses 3633system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.174587 # mshr miss rate for ReadSharedReq accesses 3634system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403485 # mshr miss rate for ReadSharedReq accesses 3635system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.336647 # mshr miss rate for ReadSharedReq accesses 3636system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.411978 # mshr miss rate for ReadSharedReq accesses 3637system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.075470 # mshr miss rate for ReadSharedReq accesses 3638system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.179875 # mshr miss rate for ReadSharedReq accesses 3639system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.473222 # mshr miss rate for ReadSharedReq accesses 3640system.l2c.ReadSharedReq_mshr_miss_rate::total 0.228951 # mshr miss rate for ReadSharedReq accesses 3641system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.771353 # mshr miss rate for InvalidateReq accesses 3642system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.508973 # mshr miss rate for InvalidateReq accesses 3643system.l2c.InvalidateReq_mshr_miss_rate::total 0.692752 # mshr miss rate for InvalidateReq accesses 3644system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.176448 # mshr miss rate for demand accesses 3645system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.164351 # mshr miss rate for demand accesses 3646system.l2c.demand_mshr_miss_rate::cpu0.inst 0.106001 # mshr miss rate for demand accesses 3647system.l2c.demand_mshr_miss_rate::cpu0.data 0.236620 # mshr miss rate for demand accesses 3648system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403485 # mshr miss rate for demand accesses 3649system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.336647 # mshr miss rate for demand accesses 3650system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.411978 # mshr miss rate for demand accesses 3651system.l2c.demand_mshr_miss_rate::cpu1.inst 0.075470 # mshr miss rate for demand accesses 3652system.l2c.demand_mshr_miss_rate::cpu1.data 0.227147 # mshr miss rate for demand accesses 3653system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.473222 # mshr miss rate for demand accesses 3654system.l2c.demand_mshr_miss_rate::total 0.249147 # mshr miss rate for demand accesses 3655system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.176448 # mshr miss rate for overall accesses 3656system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.164351 # mshr miss rate for overall accesses 3657system.l2c.overall_mshr_miss_rate::cpu0.inst 0.106001 # mshr miss rate for overall accesses 3658system.l2c.overall_mshr_miss_rate::cpu0.data 0.236620 # mshr miss rate for overall accesses 3659system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403485 # mshr miss rate for overall accesses 3660system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.336647 # mshr miss rate for overall accesses 3661system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.411978 # mshr miss rate for overall accesses 3662system.l2c.overall_mshr_miss_rate::cpu1.inst 0.075470 # mshr miss rate for overall accesses 3663system.l2c.overall_mshr_miss_rate::cpu1.data 0.227147 # mshr miss rate for overall accesses 3664system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.473222 # mshr miss rate for overall accesses 3665system.l2c.overall_mshr_miss_rate::total 0.249147 # mshr miss rate for overall accesses 3666system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21800.630729 # average UpgradeReq mshr miss latency 3667system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21481.090535 # average UpgradeReq mshr miss latency 3668system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21648.125910 # average UpgradeReq mshr miss latency 3669system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24728.644566 # average SCUpgradeReq mshr miss latency 3670system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24529.095872 # average SCUpgradeReq mshr miss latency 3671system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24631.541369 # average SCUpgradeReq mshr miss latency 3672system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80776.871426 # average ReadExReq mshr miss latency 3673system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 80418.080175 # average ReadExReq mshr miss latency 3674system.l2c.ReadExReq_avg_mshr_miss_latency::total 80622.825503 # average ReadExReq mshr miss latency 3675system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 85612.682609 # average ReadSharedReq mshr miss latency 3676system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 83498.902305 # average ReadSharedReq mshr miss latency 3677system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 77339.847556 # average ReadSharedReq mshr miss latency 3678system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 84367.373235 # average ReadSharedReq mshr miss latency 3679system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130476.040469 # average ReadSharedReq mshr miss latency 3680system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82095.111146 # average ReadSharedReq mshr miss latency 3681system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79805.781271 # average ReadSharedReq mshr miss latency 3682system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 78119.746029 # average ReadSharedReq mshr miss latency 3683system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 86410.878491 # average ReadSharedReq mshr miss latency 3684system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 127706.883719 # average ReadSharedReq mshr miss latency 3685system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 109127.534756 # average ReadSharedReq mshr miss latency 3686system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 25238.478491 # average InvalidateReq mshr miss latency 3687system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20854.531182 # average InvalidateReq mshr miss latency 3688system.l2c.InvalidateReq_avg_mshr_miss_latency::total 24273.578522 # average InvalidateReq mshr miss latency 3689system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 85612.682609 # average overall mshr miss latency 3690system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 83498.902305 # average overall mshr miss latency 3691system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 77339.847556 # average overall mshr miss latency 3692system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83021.439189 # average overall mshr miss latency 3693system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130476.040469 # average overall mshr miss latency 3694system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82095.111146 # average overall mshr miss latency 3695system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79805.781271 # average overall mshr miss latency 3696system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 78119.746029 # average overall mshr miss latency 3697system.l2c.demand_avg_mshr_miss_latency::cpu1.data 84509.674525 # average overall mshr miss latency 3698system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 127706.883719 # average overall mshr miss latency 3699system.l2c.demand_avg_mshr_miss_latency::total 105191.364969 # average overall mshr miss latency 3700system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 85612.682609 # average overall mshr miss latency 3701system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 83498.902305 # average overall mshr miss latency 3702system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 77339.847556 # average overall mshr miss latency 3703system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83021.439189 # average overall mshr miss latency 3704system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130476.040469 # average overall mshr miss latency 3705system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82095.111146 # average overall mshr miss latency 3706system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79805.781271 # average overall mshr miss latency 3707system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 78119.746029 # average overall mshr miss latency 3708system.l2c.overall_avg_mshr_miss_latency::cpu1.data 84509.674525 # average overall mshr miss latency 3709system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 127706.883719 # average overall mshr miss latency 3710system.l2c.overall_avg_mshr_miss_latency::total 105191.364969 # average overall mshr miss latency 3711system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average ReadReq mshr uncacheable latency 3712system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164853.967627 # average ReadReq mshr uncacheable latency 3713system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75813.432836 # average ReadReq mshr uncacheable latency 3714system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 96561.069817 # average ReadReq mshr uncacheable latency 3715system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 121669.858307 # average ReadReq mshr uncacheable latency 3716system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average overall mshr uncacheable latency 3717system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82650.590416 # average overall mshr uncacheable latency 3718system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 75813.432836 # average overall mshr uncacheable latency 3719system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 48017.521994 # average overall mshr uncacheable latency 3720system.l2c.overall_avg_mshr_uncacheable_latency::total 74089.494383 # average overall mshr uncacheable latency 3721system.membus.snoop_filter.tot_requests 3952559 # Total number of requests made to the snoop filter. 3722system.membus.snoop_filter.hit_single_requests 2414080 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3723system.membus.snoop_filter.hit_multi_requests 2931 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3724system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3725system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3726system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3727system.membus.trans_dist::ReadReq 60003 # Transaction distribution 3728system.membus.trans_dist::ReadResp 904829 # Transaction distribution 3729system.membus.trans_dist::WriteReq 38534 # Transaction distribution 3730system.membus.trans_dist::WriteResp 38534 # Transaction distribution 3731system.membus.trans_dist::WritebackDirty 1242017 # Transaction distribution 3732system.membus.trans_dist::CleanEvict 238236 # Transaction distribution 3733system.membus.trans_dist::UpgradeReq 446737 # Transaction distribution 3734system.membus.trans_dist::SCUpgradeReq 299659 # Transaction distribution |
| 3763system.membus.trans_dist::UpgradeResp 23 # Transaction distribution | 3735system.membus.trans_dist::UpgradeResp 23 # Transaction distribution |
| 3764system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution 3765system.membus.trans_dist::ReadExReq 153866 # Transaction distribution 3766system.membus.trans_dist::ReadExResp 139435 # Transaction distribution 3767system.membus.trans_dist::ReadSharedReq 1026904 # Transaction distribution 3768system.membus.trans_dist::InvalidateReq 703178 # Transaction distribution 3769system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122504 # Packet count per connected master and slave (bytes) | 3736system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 3737system.membus.trans_dist::ReadExReq 144708 # Transaction distribution 3738system.membus.trans_dist::ReadExResp 128413 # Transaction distribution 3739system.membus.trans_dist::ReadSharedReq 844826 # Transaction distribution 3740system.membus.trans_dist::InvalidateReq 684897 # Transaction distribution 3741system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122672 # Packet count per connected master and slave (bytes) |
| 3770system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) | 3742system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) |
| 3771system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25676 # Packet count per connected master and slave (bytes) 3772system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5303073 # Packet count per connected master and slave (bytes) 3773system.membus.pkt_count_system.l2c.mem_side::total 5451329 # Packet count per connected master and slave (bytes) 3774system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237588 # Packet count per connected master and slave (bytes) 3775system.membus.pkt_count_system.iocache.mem_side::total 237588 # Packet count per connected master and slave (bytes) 3776system.membus.pkt_count::total 5688917 # Packet count per connected master and slave (bytes) 3777system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155611 # Cumulative packet size per connected master and slave (bytes) | 3743system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26462 # Packet count per connected master and slave (bytes) 3744system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4681290 # Packet count per connected master and slave (bytes) 3745system.membus.pkt_count_system.l2c.mem_side::total 4830500 # Packet count per connected master and slave (bytes) 3746system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238195 # Packet count per connected master and slave (bytes) 3747system.membus.pkt_count_system.iocache.mem_side::total 238195 # Packet count per connected master and slave (bytes) 3748system.membus.pkt_count::total 5068695 # Packet count per connected master and slave (bytes) 3749system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155802 # Cumulative packet size per connected master and slave (bytes) |
| 3778system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) | 3750system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) |
| 3779system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51352 # Cumulative packet size per connected master and slave (bytes) 3780system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 158370176 # Cumulative packet size per connected master and slave (bytes) 3781system.membus.pkt_size_system.l2c.mem_side::total 158577695 # Cumulative packet size per connected master and slave (bytes) 3782system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7233920 # Cumulative packet size per connected master and slave (bytes) 3783system.membus.pkt_size_system.iocache.mem_side::total 7233920 # Cumulative packet size per connected master and slave (bytes) 3784system.membus.pkt_size::total 165811615 # Cumulative packet size per connected master and slave (bytes) 3785system.membus.snoops 603403 # Total snoops (count) 3786system.membus.snoop_fanout::samples 4427877 # Request fanout histogram 3787system.membus.snoop_fanout::mean 1 # Request fanout histogram 3788system.membus.snoop_fanout::stdev 0 # Request fanout histogram | 3751system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52924 # Cumulative packet size per connected master and slave (bytes) 3752system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 134692416 # Cumulative packet size per connected master and slave (bytes) 3753system.membus.pkt_size_system.l2c.mem_side::total 134901698 # Cumulative packet size per connected master and slave (bytes) 3754system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7273344 # Cumulative packet size per connected master and slave (bytes) 3755system.membus.pkt_size_system.iocache.mem_side::total 7273344 # Cumulative packet size per connected master and slave (bytes) 3756system.membus.pkt_size::total 142175042 # Cumulative packet size per connected master and slave (bytes) 3757system.membus.snoops 606585 # Total snoops (count) 3758system.membus.snoop_fanout::samples 2519367 # Request fanout histogram 3759system.membus.snoop_fanout::mean 0.015113 # Request fanout histogram 3760system.membus.snoop_fanout::stdev 0.122002 # Request fanout histogram |
| 3789system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 3761system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 3790system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3791system.membus.snoop_fanout::1 4427877 100.00% 100.00% # Request fanout histogram | 3762system.membus.snoop_fanout::0 2481292 98.49% 98.49% # Request fanout histogram 3763system.membus.snoop_fanout::1 38075 1.51% 100.00% # Request fanout histogram |
| 3792system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3793system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 3764system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3765system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 3794system.membus.snoop_fanout::min_value 1 # Request fanout histogram | 3766system.membus.snoop_fanout::min_value 0 # Request fanout histogram |
| 3795system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 3767system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 3796system.membus.snoop_fanout::total 4427877 # Request fanout histogram 3797system.membus.reqLayer0.occupancy 97877995 # Layer occupancy (ticks) | 3768system.membus.snoop_fanout::total 2519367 # Request fanout histogram 3769system.membus.reqLayer0.occupancy 98170994 # Layer occupancy (ticks) |
| 3798system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3799system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks) 3800system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 3770system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3771system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks) 3772system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 3801system.membus.reqLayer2.occupancy 21789496 # Layer occupancy (ticks) | 3773system.membus.reqLayer2.occupancy 22248500 # Layer occupancy (ticks) |
| 3802system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 3774system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 3803system.membus.reqLayer5.occupancy 9855054431 # Layer occupancy (ticks) | 3775system.membus.reqLayer5.occupancy 8723892621 # Layer occupancy (ticks) |
| 3804system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 3776system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 3805system.membus.respLayer2.occupancy 6236968511 # Layer occupancy (ticks) | 3777system.membus.respLayer2.occupancy 5223815230 # Layer occupancy (ticks) |
| 3806system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 3778system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 3807system.membus.respLayer3.occupancy 45519188 # Layer occupancy (ticks) | 3779system.membus.respLayer3.occupancy 45514707 # Layer occupancy (ticks) |
| 3808system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3809system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3810system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3811system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3812system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3813system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3814system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3815system.realview.ethernet.txBytes 966 # Bytes Transmitted --- 37 unchanged lines hidden (view full) --- 3853system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3854system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3855system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3856system.realview.ethernet.droppedPackets 0 # number of packets dropped 3857system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3858system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3859system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3860system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 3780system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3781system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3782system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3783system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3784system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3785system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3786system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3787system.realview.ethernet.txBytes 966 # Bytes Transmitted --- 37 unchanged lines hidden (view full) --- 3825system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3826system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3827system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3828system.realview.ethernet.droppedPackets 0 # number of packets dropped 3829system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3830system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3831system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3832system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 3861system.toL2Bus.snoop_filter.tot_requests 12681630 # Total number of requests made to the snoop filter. 3862system.toL2Bus.snoop_filter.hit_single_requests 6883923 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3863system.toL2Bus.snoop_filter.hit_multi_requests 2005926 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3864system.toL2Bus.snoop_filter.tot_snoops 170885 # Total number of snoops made to the snoop filter. 3865system.toL2Bus.snoop_filter.hit_single_snoops 155146 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3866system.toL2Bus.snoop_filter.hit_multi_snoops 15739 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3867system.toL2Bus.trans_dist::ReadReq 59767 # Transaction distribution 3868system.toL2Bus.trans_dist::ReadResp 4843433 # Transaction distribution 3869system.toL2Bus.trans_dist::WriteReq 38295 # Transaction distribution 3870system.toL2Bus.trans_dist::WriteResp 38295 # Transaction distribution 3871system.toL2Bus.trans_dist::WritebackDirty 4463947 # Transaction distribution | 3833system.toL2Bus.snoop_filter.tot_requests 11842018 # Total number of requests made to the snoop filter. 3834system.toL2Bus.snoop_filter.hit_single_requests 6441759 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3835system.toL2Bus.snoop_filter.hit_multi_requests 1913591 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3836system.toL2Bus.snoop_filter.tot_snoops 133722 # Total number of snoops made to the snoop filter. 3837system.toL2Bus.snoop_filter.hit_single_snoops 121814 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3838system.toL2Bus.snoop_filter.hit_multi_snoops 11908 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3839system.toL2Bus.trans_dist::ReadReq 60005 # Transaction distribution 3840system.toL2Bus.trans_dist::ReadResp 4492996 # Transaction distribution 3841system.toL2Bus.trans_dist::WriteReq 38534 # Transaction distribution 3842system.toL2Bus.trans_dist::WriteResp 38534 # Transaction distribution 3843system.toL2Bus.trans_dist::WritebackDirty 3934886 # Transaction distribution |
| 3872system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution | 3844system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution |
| 3873system.toL2Bus.trans_dist::CleanEvict 2878269 # Transaction distribution 3874system.toL2Bus.trans_dist::UpgradeReq 761897 # Transaction distribution 3875system.toL2Bus.trans_dist::SCUpgradeReq 392804 # Transaction distribution 3876system.toL2Bus.trans_dist::UpgradeResp 1154700 # Transaction distribution 3877system.toL2Bus.trans_dist::SCUpgradeFailReq 117 # Transaction distribution 3878system.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution 3879system.toL2Bus.trans_dist::ReadExReq 312867 # Transaction distribution 3880system.toL2Bus.trans_dist::ReadExResp 312867 # Transaction distribution 3881system.toL2Bus.trans_dist::ReadSharedReq 4790902 # Transaction distribution 3882system.toL2Bus.trans_dist::InvalidateReq 969633 # Transaction distribution 3883system.toL2Bus.trans_dist::InvalidateResp 862905 # Transaction distribution 3884system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9568329 # Packet count per connected master and slave (bytes) 3885system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9002574 # Packet count per connected master and slave (bytes) 3886system.toL2Bus.pkt_count::total 18570903 # Packet count per connected master and slave (bytes) 3887system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 239712817 # Cumulative packet size per connected master and slave (bytes) 3888system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 228526446 # Cumulative packet size per connected master and slave (bytes) 3889system.toL2Bus.pkt_size::total 468239263 # Cumulative packet size per connected master and slave (bytes) 3890system.toL2Bus.snoops 3311598 # Total snoops (count) 3891system.toL2Bus.snoop_fanout::samples 9100879 # Request fanout histogram 3892system.toL2Bus.snoop_fanout::mean 0.338787 # Request fanout histogram 3893system.toL2Bus.snoop_fanout::stdev 0.476937 # Request fanout histogram | 3845system.toL2Bus.trans_dist::CleanEvict 2625367 # Transaction distribution 3846system.toL2Bus.trans_dist::UpgradeReq 741215 # Transaction distribution 3847system.toL2Bus.trans_dist::SCUpgradeReq 380628 # Transaction distribution 3848system.toL2Bus.trans_dist::UpgradeResp 1121842 # Transaction distribution 3849system.toL2Bus.trans_dist::SCUpgradeFailReq 140 # Transaction distribution 3850system.toL2Bus.trans_dist::UpgradeFailResp 140 # Transaction distribution 3851system.toL2Bus.trans_dist::ReadExReq 295903 # Transaction distribution 3852system.toL2Bus.trans_dist::ReadExResp 295903 # Transaction distribution 3853system.toL2Bus.trans_dist::ReadSharedReq 4433512 # Transaction distribution 3854system.toL2Bus.trans_dist::InvalidateReq 874748 # Transaction distribution 3855system.toL2Bus.trans_dist::InvalidateResp 839647 # Transaction distribution 3856system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9358904 # Packet count per connected master and slave (bytes) 3857system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7932274 # Packet count per connected master and slave (bytes) 3858system.toL2Bus.pkt_count::total 17291178 # Packet count per connected master and slave (bytes) 3859system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 230390413 # Cumulative packet size per connected master and slave (bytes) 3860system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 198586357 # Cumulative packet size per connected master and slave (bytes) 3861system.toL2Bus.pkt_size::total 428976770 # Cumulative packet size per connected master and slave (bytes) 3862system.toL2Bus.snoops 2884507 # Total snoops (count) 3863system.toL2Bus.snoop_fanout::samples 8248846 # Request fanout histogram 3864system.toL2Bus.snoop_fanout::mean 0.358423 # Request fanout histogram 3865system.toL2Bus.snoop_fanout::stdev 0.482538 # Request fanout histogram |
| 3894system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 3866system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 3895system.toL2Bus.snoop_fanout::0 6033358 66.29% 66.29% # Request fanout histogram 3896system.toL2Bus.snoop_fanout::1 3051782 33.53% 99.83% # Request fanout histogram 3897system.toL2Bus.snoop_fanout::2 15739 0.17% 100.00% # Request fanout histogram | 3867system.toL2Bus.snoop_fanout::0 5304178 64.30% 64.30% # Request fanout histogram 3868system.toL2Bus.snoop_fanout::1 2932760 35.55% 99.86% # Request fanout histogram 3869system.toL2Bus.snoop_fanout::2 11908 0.14% 100.00% # Request fanout histogram |
| 3898system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3899system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3900system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 3870system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3871system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3872system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 3901system.toL2Bus.snoop_fanout::total 9100879 # Request fanout histogram 3902system.toL2Bus.reqLayer0.occupancy 9916846796 # Layer occupancy (ticks) | 3873system.toL2Bus.snoop_fanout::total 8248846 # Request fanout histogram 3874system.toL2Bus.reqLayer0.occupancy 9216694138 # Layer occupancy (ticks) |
| 3903system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 3875system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 3904system.toL2Bus.snoopLayer0.occupancy 2612852 # Layer occupancy (ticks) | 3876system.toL2Bus.snoopLayer0.occupancy 2593163 # Layer occupancy (ticks) |
| 3905system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 3877system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 3906system.toL2Bus.respLayer0.occupancy 4354241663 # Layer occupancy (ticks) | 3878system.toL2Bus.respLayer0.occupancy 4234968582 # Layer occupancy (ticks) |
| 3907system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 3879system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 3908system.toL2Bus.respLayer1.occupancy 4394264623 # Layer occupancy (ticks) | 3880system.toL2Bus.respLayer1.occupancy 3934186551 # Layer occupancy (ticks) |
| 3909system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3910system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 3881system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3882system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 3911system.cpu0.kern.inst.quiesce 4933 # number of quiesce instructions executed | 3883system.cpu0.kern.inst.quiesce 13240 # number of quiesce instructions executed |
| 3912system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 3884system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 3913system.cpu1.kern.inst.quiesce 14218 # number of quiesce instructions executed | 3885system.cpu1.kern.inst.quiesce 5626 # number of quiesce instructions executed |
| 3914 3915---------- End Simulation Statistics ---------- | 3886 3887---------- End Simulation Statistics ---------- |