| stats.txt (10726:8a20e2a1562d) | stats.txt (10736:4433fb00fa7d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.305566 # Number of seconds simulated 4sim_ticks 47305566199500 # Number of ticks simulated 5final_tick 47305566199500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 109110 # Simulator instruction rate (inst/s) 8host_op_rate 128307 # Simulator op (including micro ops) rate (op/s) --- 834 unchanged lines hidden (view full) --- 843system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.56% # Class of committed instruction 844system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.56% # Class of committed instruction 845system.cpu0.commit.op_class_0::MemRead 86857868 15.93% 85.49% # Class of committed instruction 846system.cpu0.commit.op_class_0::MemWrite 79126008 14.51% 100.00% # Class of committed instruction 847system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 848system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 849system.cpu0.commit.op_class_0::total 545285068 # Class of committed instruction 850system.cpu0.commit.bw_lim_events 13335148 # number cycles where commit BW limit reached | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.305566 # Number of seconds simulated 4sim_ticks 47305566199500 # Number of ticks simulated 5final_tick 47305566199500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 109110 # Simulator instruction rate (inst/s) 8host_op_rate 128307 # Simulator op (including micro ops) rate (op/s) --- 834 unchanged lines hidden (view full) --- 843system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.56% # Class of committed instruction 844system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.56% # Class of committed instruction 845system.cpu0.commit.op_class_0::MemRead 86857868 15.93% 85.49% # Class of committed instruction 846system.cpu0.commit.op_class_0::MemWrite 79126008 14.51% 100.00% # Class of committed instruction 847system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 848system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 849system.cpu0.commit.op_class_0::total 545285068 # Class of committed instruction 850system.cpu0.commit.bw_lim_events 13335148 # number cycles where commit BW limit reached |
| 851system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | |
| 852system.cpu0.rob.rob_reads 1272468420 # The number of ROB reads 853system.cpu0.rob.rob_writes 1194722923 # The number of ROB writes 854system.cpu0.timesIdled 998377 # Number of times that the entire CPU went into an idle state and unscheduled itself 855system.cpu0.idleCycles 22469901 # Total number of cycles that the CPU has spent unscheduled due to idling 856system.cpu0.quiesceCycles 93882577668 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 857system.cpu0.committedInsts 464477894 # Number of Instructions Simulated 858system.cpu0.committedOps 545285068 # Number of Ops (including micro ops) Simulated 859system.cpu0.cpi 1.568546 # CPI: Cycles Per Instruction --- 1232 unchanged lines hidden (view full) --- 2092system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.31% # Class of committed instruction 2093system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.31% # Class of committed instruction 2094system.cpu1.commit.op_class_0::MemRead 80761178 16.14% 85.45% # Class of committed instruction 2095system.cpu1.commit.op_class_0::MemWrite 72799700 14.55% 100.00% # Class of committed instruction 2096system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2097system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2098system.cpu1.commit.op_class_0::total 500362777 # Class of committed instruction 2099system.cpu1.commit.bw_lim_events 12356672 # number cycles where commit BW limit reached | 851system.cpu0.rob.rob_reads 1272468420 # The number of ROB reads 852system.cpu0.rob.rob_writes 1194722923 # The number of ROB writes 853system.cpu0.timesIdled 998377 # Number of times that the entire CPU went into an idle state and unscheduled itself 854system.cpu0.idleCycles 22469901 # Total number of cycles that the CPU has spent unscheduled due to idling 855system.cpu0.quiesceCycles 93882577668 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 856system.cpu0.committedInsts 464477894 # Number of Instructions Simulated 857system.cpu0.committedOps 545285068 # Number of Ops (including micro ops) Simulated 858system.cpu0.cpi 1.568546 # CPI: Cycles Per Instruction --- 1232 unchanged lines hidden (view full) --- 2091system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.31% # Class of committed instruction 2092system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.31% # Class of committed instruction 2093system.cpu1.commit.op_class_0::MemRead 80761178 16.14% 85.45% # Class of committed instruction 2094system.cpu1.commit.op_class_0::MemWrite 72799700 14.55% 100.00% # Class of committed instruction 2095system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2096system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2097system.cpu1.commit.op_class_0::total 500362777 # Class of committed instruction 2098system.cpu1.commit.bw_lim_events 12356672 # number cycles where commit BW limit reached |
| 2100system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | |
| 2101system.cpu1.rob.rob_reads 1162834468 # The number of ROB reads 2102system.cpu1.rob.rob_writes 1096743807 # The number of ROB writes 2103system.cpu1.timesIdled 924876 # Number of times that the entire CPU went into an idle state and unscheduled itself 2104system.cpu1.idleCycles 16064791 # Total number of cycles that the CPU has spent unscheduled due to idling 2105system.cpu1.quiesceCycles 93951930875 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2106system.cpu1.committedInsts 424719097 # Number of Instructions Simulated 2107system.cpu1.committedOps 500362777 # Number of Ops (including micro ops) Simulated 2108system.cpu1.cpi 1.552088 # CPI: Cycles Per Instruction --- 1670 unchanged lines hidden --- | 2099system.cpu1.rob.rob_reads 1162834468 # The number of ROB reads 2100system.cpu1.rob.rob_writes 1096743807 # The number of ROB writes 2101system.cpu1.timesIdled 924876 # Number of times that the entire CPU went into an idle state and unscheduled itself 2102system.cpu1.idleCycles 16064791 # Total number of cycles that the CPU has spent unscheduled due to idling 2103system.cpu1.quiesceCycles 93951930875 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2104system.cpu1.committedInsts 424719097 # Number of Instructions Simulated 2105system.cpu1.committedOps 500362777 # Number of Ops (including micro ops) Simulated 2106system.cpu1.cpi 1.552088 # CPI: Cycles Per Instruction --- 1670 unchanged lines hidden --- |