| stats.txt (10628:c9b7e0c69f88) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 47.345385 # Number of seconds simulated 4sim_ticks 47345385235500 # Number of ticks simulated 5final_tick 47345385235500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 47.305566 # Number of seconds simulated 4sim_ticks 47305566199500 # Number of ticks simulated 5final_tick 47305566199500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 106392 # Simulator instruction rate (inst/s) 8host_op_rate 125133 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5453309126 # Simulator tick rate (ticks/s) 10host_mem_usage 767036 # Number of bytes of host memory used 11host_seconds 8681.96 # Real time elapsed on the host 12sim_insts 923688991 # Number of instructions simulated 13sim_ops 1086395427 # Number of ops (including micro ops) simulated | 7host_inst_rate 109110 # Simulator instruction rate (inst/s) 8host_op_rate 128307 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5804669404 # Simulator tick rate (ticks/s) 10host_mem_usage 767140 # Number of bytes of host memory used 11host_seconds 8149.57 # Real time elapsed on the host 12sim_insts 889196991 # Number of instructions simulated 13sim_ops 1045647845 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu0.dtb.walker 161152 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 146432 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 4268768 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 16023832 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 20180672 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 179840 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 156416 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 3463536 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 11559072 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 14510464 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 437312 # Number of bytes read from this memory 27system.physmem.bytes_read::total 71087496 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 4268768 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 3463536 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 7732304 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 86253568 # Number of bytes written to this memory | 16system.physmem.bytes_read::cpu0.dtb.walker 75776 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 60928 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 4503136 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 12909720 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 13016640 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 167424 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 164416 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 2523040 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 10482528 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 14576384 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 439104 # Number of bytes read from this memory 27system.physmem.bytes_read::total 58919096 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 4503136 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 2523040 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 7026176 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 75116864 # Number of bytes written to this memory |
| 32system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory | 32system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory |
| 34system.physmem.bytes_written::total 86274384 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 2518 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 2288 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 82652 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 250394 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 315323 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 2810 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 2444 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 54162 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 180625 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 226726 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6833 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 1126775 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1347712 # Number of write requests responded to by this memory | 34system.physmem.bytes_written::total 75137680 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 1184 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 952 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 86314 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 201736 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 203385 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 2616 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 2569 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 39466 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 163804 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 227756 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6861 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 936643 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1173701 # Number of write requests responded to by this memory |
| 48system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory | 48system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory |
| 50system.physmem.num_writes::total 1350315 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 3404 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 3093 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 90162 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 338445 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 426244 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 3798 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 3304 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 73155 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 244144 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 306481 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9237 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1501466 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 90162 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 73155 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 163317 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1821795 # Write bandwidth from this memory (bytes/s) | 50system.physmem.num_writes::total 1176304 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 1602 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 1288 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 95193 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 272901 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 275161 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 3539 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 3476 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 53335 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 221592 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 308133 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9282 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1245500 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 95193 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 53335 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 148527 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1587908 # Write bandwidth from this memory (bytes/s) |
| 67system.physmem.bw_write::cpu0.data 440 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) | 67system.physmem.bw_write::cpu0.data 440 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) |
| 69system.physmem.bw_write::total 1822234 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1821795 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 3404 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 3093 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 90162 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 338885 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 426244 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 3798 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 3304 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 73155 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 244144 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 306481 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9237 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 3323700 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 1126775 # Number of read requests accepted 84system.physmem.writeReqs 2040290 # Number of write requests accepted 85system.physmem.readBursts 1126775 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 2040290 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 72094336 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 19264 # Total number of bytes read from write queue 89system.physmem.bytesWritten 130093376 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 71087496 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 130432784 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 301 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 7556 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 121134 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 65675 # Per bank write bursts 96system.physmem.perBankRdBursts::1 75833 # Per bank write bursts 97system.physmem.perBankRdBursts::2 67256 # Per bank write bursts 98system.physmem.perBankRdBursts::3 67290 # Per bank write bursts 99system.physmem.perBankRdBursts::4 71240 # Per bank write bursts 100system.physmem.perBankRdBursts::5 82191 # Per bank write bursts 101system.physmem.perBankRdBursts::6 67013 # Per bank write bursts 102system.physmem.perBankRdBursts::7 67787 # Per bank write bursts 103system.physmem.perBankRdBursts::8 61707 # Per bank write bursts 104system.physmem.perBankRdBursts::9 85775 # Per bank write bursts 105system.physmem.perBankRdBursts::10 61014 # Per bank write bursts 106system.physmem.perBankRdBursts::11 72520 # Per bank write bursts 107system.physmem.perBankRdBursts::12 65793 # Per bank write bursts 108system.physmem.perBankRdBursts::13 74631 # Per bank write bursts 109system.physmem.perBankRdBursts::14 69278 # Per bank write bursts 110system.physmem.perBankRdBursts::15 71471 # Per bank write bursts 111system.physmem.perBankWrBursts::0 122526 # Per bank write bursts 112system.physmem.perBankWrBursts::1 130111 # Per bank write bursts 113system.physmem.perBankWrBursts::2 125889 # Per bank write bursts 114system.physmem.perBankWrBursts::3 127486 # Per bank write bursts 115system.physmem.perBankWrBursts::4 126972 # Per bank write bursts 116system.physmem.perBankWrBursts::5 136977 # Per bank write bursts 117system.physmem.perBankWrBursts::6 126845 # Per bank write bursts 118system.physmem.perBankWrBursts::7 128268 # Per bank write bursts 119system.physmem.perBankWrBursts::8 123854 # Per bank write bursts 120system.physmem.perBankWrBursts::9 125736 # Per bank write bursts 121system.physmem.perBankWrBursts::10 125360 # Per bank write bursts 122system.physmem.perBankWrBursts::11 131761 # Per bank write bursts 123system.physmem.perBankWrBursts::12 119984 # Per bank write bursts 124system.physmem.perBankWrBursts::13 126166 # Per bank write bursts 125system.physmem.perBankWrBursts::14 125889 # Per bank write bursts 126system.physmem.perBankWrBursts::15 128885 # Per bank write bursts | 69system.physmem.bw_write::total 1588348 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1587908 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 1602 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 1288 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 95193 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 273341 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 275161 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 3539 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 3476 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 53335 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 221592 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 308133 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9282 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 2833848 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 936643 # Number of read requests accepted 84system.physmem.writeReqs 1837953 # Number of write requests accepted 85system.physmem.readBursts 936643 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1837953 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 59924608 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 20544 # Total number of bytes read from write queue 89system.physmem.bytesWritten 114470976 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 58919096 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 117483216 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 321 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 49325 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 117374 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 55305 # Per bank write bursts 96system.physmem.perBankRdBursts::1 59995 # Per bank write bursts 97system.physmem.perBankRdBursts::2 52034 # Per bank write bursts 98system.physmem.perBankRdBursts::3 56018 # Per bank write bursts 99system.physmem.perBankRdBursts::4 58058 # Per bank write bursts 100system.physmem.perBankRdBursts::5 68871 # Per bank write bursts 101system.physmem.perBankRdBursts::6 59545 # Per bank write bursts 102system.physmem.perBankRdBursts::7 57406 # Per bank write bursts 103system.physmem.perBankRdBursts::8 51483 # Per bank write bursts 104system.physmem.perBankRdBursts::9 77850 # Per bank write bursts 105system.physmem.perBankRdBursts::10 53930 # Per bank write bursts 106system.physmem.perBankRdBursts::11 57982 # Per bank write bursts 107system.physmem.perBankRdBursts::12 54532 # Per bank write bursts 108system.physmem.perBankRdBursts::13 56851 # Per bank write bursts 109system.physmem.perBankRdBursts::14 60976 # Per bank write bursts 110system.physmem.perBankRdBursts::15 55486 # Per bank write bursts 111system.physmem.perBankWrBursts::0 110085 # Per bank write bursts 112system.physmem.perBankWrBursts::1 112883 # Per bank write bursts 113system.physmem.perBankWrBursts::2 108062 # Per bank write bursts 114system.physmem.perBankWrBursts::3 109070 # Per bank write bursts 115system.physmem.perBankWrBursts::4 113169 # Per bank write bursts 116system.physmem.perBankWrBursts::5 118310 # Per bank write bursts 117system.physmem.perBankWrBursts::6 115499 # Per bank write bursts 118system.physmem.perBankWrBursts::7 111959 # Per bank write bursts 119system.physmem.perBankWrBursts::8 107874 # Per bank write bursts 120system.physmem.perBankWrBursts::9 113071 # Per bank write bursts 121system.physmem.perBankWrBursts::10 109141 # Per bank write bursts 122system.physmem.perBankWrBursts::11 113654 # Per bank write bursts 123system.physmem.perBankWrBursts::12 105244 # Per bank write bursts 124system.physmem.perBankWrBursts::13 111328 # Per bank write bursts 125system.physmem.perBankWrBursts::14 115976 # Per bank write bursts 126system.physmem.perBankWrBursts::15 113284 # Per bank write bursts |
| 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 128system.physmem.numWrRetry 614 # Number of times write queue was full causing retry 129system.physmem.totGap 47345383810500 # Total gap between requests | 128system.physmem.numWrRetry 81608 # Number of times write queue was full causing retry 129system.physmem.totGap 47305564753000 # Total gap between requests |
| 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) 133system.physmem.readPktSize::3 37 # Read request sizes (log2) | 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) 133system.physmem.readPktSize::3 37 # Read request sizes (log2) |
| 134system.physmem.readPktSize::4 21334 # Read request sizes (log2) | 134system.physmem.readPktSize::4 21333 # Read request sizes (log2) |
| 135system.physmem.readPktSize::5 0 # Read request sizes (log2) | 135system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 136system.physmem.readPktSize::6 1105404 # Read request sizes (log2) | 136system.physmem.readPktSize::6 915273 # Read request sizes (log2) |
| 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2601 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) | 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2601 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 143system.physmem.writePktSize::6 2037687 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 495851 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 234383 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 118863 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 70028 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 51854 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 39852 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 34830 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 31890 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 28010 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 7930 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 4174 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 2742 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 1780 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 1381 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 844 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 715 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 607 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 457 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 161 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 107 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see | 143system.physmem.writePktSize::6 1835350 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 429452 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 211261 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 82392 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 54481 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 35792 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 29912 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 27031 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 25347 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 22393 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 8038 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 3479 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 2226 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 1304 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 1011 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 581 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 510 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 459 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 398 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 145 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 106 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see |
| 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see --- 8 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see --- 8 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 191system.physmem.wrQLenPdf::15 30752 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 44920 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 58821 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 69578 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 77864 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 89177 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 97306 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 106336 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 112038 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 121912 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 121861 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 124135 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 125483 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 131449 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 118558 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 117002 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 113440 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 105060 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 29238 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 25813 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 22998 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 20720 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 18797 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 16980 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 15279 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 13444 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 11652 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 10311 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 9180 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 8124 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 7426 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 6654 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 6134 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 5597 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 5145 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 4620 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 4249 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 3863 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 3550 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 3131 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 2559 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 2104 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 1878 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 1591 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 1280 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 1141 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 1049 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 1018 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 1502 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 1131657 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 178.664737 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 108.493979 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 249.059793 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 718344 63.48% 63.48% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 219262 19.38% 82.85% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 56669 5.01% 87.86% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 25497 2.25% 90.11% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 20148 1.78% 91.89% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 11584 1.02% 92.92% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 9545 0.84% 93.76% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 8895 0.79% 94.55% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 61713 5.45% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 1131657 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 74075 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 15.207155 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 65.468886 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-511 74072 100.00% 100.00% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::512-1023 1 0.00% 100.00% # Reads before turning the bus around for writes | 191system.physmem.wrQLenPdf::15 25942 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 31294 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 42762 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 50992 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 57625 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 67617 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 67331 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 70370 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 78632 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 77296 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 79817 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 88544 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 82050 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 81883 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 102987 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 87472 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 82523 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 74776 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 11408 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 9295 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 8921 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 9951 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 10393 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 8748 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 8966 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 9255 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 8034 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 7640 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 7450 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 7439 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 6226 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 5791 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 5896 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 5137 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 4222 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 3205 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 3127 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 2893 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 3002 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 2681 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 2695 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 2825 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 2650 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 2954 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 3512 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 4384 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 7063 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 7984 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 354953 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 953575 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 182.885667 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 110.719338 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 252.430373 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 592274 62.11% 62.11% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 190618 19.99% 82.10% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 51298 5.38% 87.48% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 22604 2.37% 89.85% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 16941 1.78% 91.63% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 10334 1.08% 92.71% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 7600 0.80% 93.51% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 7080 0.74% 94.25% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 54826 5.75% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 953575 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 60764 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 15.409042 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 72.355469 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-511 60757 99.99% 99.99% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes |
| 259system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes | 260system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes |
| 261system.physmem.rdPerTurnAround::total 74075 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 74075 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 27.441228 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 19.793858 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 451.068024 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::0-1023 74039 99.95% 99.95% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::1024-2047 13 0.02% 99.97% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::2048-3071 9 0.01% 99.98% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::3072-4095 5 0.01% 99.99% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::4096-5119 2 0.00% 99.99% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::5120-6143 2 0.00% 99.99% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::26624-27647 1 0.00% 99.99% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::33792-34815 1 0.00% 100.00% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::64512-65535 3 0.00% 100.00% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::total 74075 # Writes before turning the bus around for reads 276system.physmem.totQLat 56140564025 # Total ticks spent queuing 277system.physmem.totMemAccLat 77261951525 # Total ticks spent from burst creation until serviced by the DRAM 278system.physmem.totBusLat 5632370000 # Total ticks spent in databus transfers 279system.physmem.avgQLat 49837.43 # Average queueing delay per DRAM burst | 262system.physmem.rdPerTurnAround::total 60764 # Reads before turning the bus around for writes 263system.physmem.wrPerTurnAround::samples 60764 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::mean 29.435340 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::gmean 19.473917 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::stdev 995.068690 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::0-4095 60761 100.00% 100.00% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::98304-102399 1 0.00% 100.00% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::102400-106495 1 0.00% 100.00% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::192512-196607 1 0.00% 100.00% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::total 60764 # Writes before turning the bus around for reads 272system.physmem.totQLat 43948740923 # Total ticks spent queuing 273system.physmem.totMemAccLat 61504778423 # Total ticks spent from burst creation until serviced by the DRAM 274system.physmem.totBusLat 4681610000 # Total ticks spent in databus transfers 275system.physmem.avgQLat 46937.64 # Average queueing delay per DRAM burst |
| 280system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 276system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 281system.physmem.avgMemAccLat 68587.43 # Average memory access latency per DRAM burst 282system.physmem.avgRdBW 1.52 # Average DRAM read bandwidth in MiByte/s 283system.physmem.avgWrBW 2.75 # Average achieved write bandwidth in MiByte/s 284system.physmem.avgRdBWSys 1.50 # Average system read bandwidth in MiByte/s 285system.physmem.avgWrBWSys 2.75 # Average system write bandwidth in MiByte/s | 277system.physmem.avgMemAccLat 65687.64 # Average memory access latency per DRAM burst 278system.physmem.avgRdBW 1.27 # Average DRAM read bandwidth in MiByte/s 279system.physmem.avgWrBW 2.42 # Average achieved write bandwidth in MiByte/s 280system.physmem.avgRdBWSys 1.25 # Average system read bandwidth in MiByte/s 281system.physmem.avgWrBWSys 2.48 # Average system write bandwidth in MiByte/s |
| 286system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 287system.physmem.busUtil 0.03 # Data bus utilization in percentage 288system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 289system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes | 282system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 283system.physmem.busUtil 0.03 # Data bus utilization in percentage 284system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 285system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes |
| 290system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing 291system.physmem.avgWrQLen 24.34 # Average write queue length when enqueuing 292system.physmem.readRowHits 851046 # Number of row buffer hits during reads 293system.physmem.writeRowHits 1176475 # Number of row buffer hits during writes 294system.physmem.readRowHitRate 75.55 # Row buffer hit rate for reads 295system.physmem.writeRowHitRate 57.88 # Row buffer hit rate for writes 296system.physmem.avgGap 14949293.37 # Average gap between requests 297system.physmem.pageHitRate 64.18 # Row buffer hit rate, read and write combined 298system.physmem_0.actEnergy 4318120800 # Energy for activate commands per rank (pJ) 299system.physmem_0.preEnergy 2356117500 # Energy for precharge commands per rank (pJ) 300system.physmem_0.readEnergy 4401423000 # Energy for read commands per rank (pJ) 301system.physmem_0.writeEnergy 6642421200 # Energy for write commands per rank (pJ) 302system.physmem_0.refreshEnergy 3092370278400 # Energy for refresh commands per rank (pJ) 303system.physmem_0.actBackEnergy 1163515422960 # Energy for active background per rank (pJ) 304system.physmem_0.preBackEnergy 27386602512000 # Energy for precharge background per rank (pJ) 305system.physmem_0.totalEnergy 31660206295860 # Total energy per rank (pJ) 306system.physmem_0.averagePower 668.707358 # Core power per rank (mW) 307system.physmem_0.memoryStateTime::IDLE 45559855793000 # Time in different power states 308system.physmem_0.memoryStateTime::REF 1580966400000 # Time in different power states | 286system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 287system.physmem.avgWrQLen 26.58 # Average write queue length when enqueuing 288system.physmem.readRowHits 706637 # Number of row buffer hits during reads 289system.physmem.writeRowHits 1064717 # Number of row buffer hits during writes 290system.physmem.readRowHitRate 75.47 # Row buffer hit rate for reads 291system.physmem.writeRowHitRate 59.53 # Row buffer hit rate for writes 292system.physmem.avgGap 17049532.53 # Average gap between requests 293system.physmem.pageHitRate 65.01 # Row buffer hit rate, read and write combined 294system.physmem_0.actEnergy 3636465840 # Energy for activate commands per rank (pJ) 295system.physmem_0.preEnergy 1984182750 # Energy for precharge commands per rank (pJ) 296system.physmem_0.readEnergy 3644362800 # Energy for read commands per rank (pJ) 297system.physmem_0.writeEnergy 5825759760 # Energy for write commands per rank (pJ) 298system.physmem_0.refreshEnergy 3089769502560 # Energy for refresh commands per rank (pJ) 299system.physmem_0.actBackEnergy 1155369631905 # Energy for active background per rank (pJ) 300system.physmem_0.preBackEnergy 27369856613250 # Energy for precharge background per rank (pJ) 301system.physmem_0.totalEnergy 31630086518865 # Total energy per rank (pJ) 302system.physmem_0.averagePower 668.633528 # Core power per rank (mW) 303system.physmem_0.memoryStateTime::IDLE 45532077679143 # Time in different power states 304system.physmem_0.memoryStateTime::REF 1579636760000 # Time in different power states |
| 309system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 305system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 310system.physmem_0.memoryStateTime::ACT 204562609000 # Time in different power states | 306system.physmem_0.memoryStateTime::ACT 193851315857 # Time in different power states |
| 311system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 307system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 312system.physmem_1.actEnergy 4237153200 # Energy for activate commands per rank (pJ) 313system.physmem_1.preEnergy 2311938750 # Energy for precharge commands per rank (pJ) 314system.physmem_1.readEnergy 4385027400 # Energy for read commands per rank (pJ) 315system.physmem_1.writeEnergy 6529429440 # Energy for write commands per rank (pJ) 316system.physmem_1.refreshEnergy 3092370278400 # Energy for refresh commands per rank (pJ) 317system.physmem_1.actBackEnergy 1165548686490 # Energy for active background per rank (pJ) 318system.physmem_1.preBackEnergy 27384818947500 # Energy for precharge background per rank (pJ) 319system.physmem_1.totalEnergy 31660201461180 # Total energy per rank (pJ) 320system.physmem_1.averagePower 668.707256 # Core power per rank (mW) 321system.physmem_1.memoryStateTime::IDLE 45556862760500 # Time in different power states 322system.physmem_1.memoryStateTime::REF 1580966400000 # Time in different power states | 308system.physmem_1.actEnergy 3572561160 # Energy for activate commands per rank (pJ) 309system.physmem_1.preEnergy 1949314125 # Energy for precharge commands per rank (pJ) 310system.physmem_1.readEnergy 3658902000 # Energy for read commands per rank (pJ) 311system.physmem_1.writeEnergy 5764426560 # Energy for write commands per rank (pJ) 312system.physmem_1.refreshEnergy 3089769502560 # Energy for refresh commands per rank (pJ) 313system.physmem_1.actBackEnergy 1152447208560 # Energy for active background per rank (pJ) 314system.physmem_1.preBackEnergy 27372420142500 # Energy for precharge background per rank (pJ) 315system.physmem_1.totalEnergy 31629582057465 # Total energy per rank (pJ) 316system.physmem_1.averagePower 668.622864 # Core power per rank (mW) 317system.physmem_1.memoryStateTime::IDLE 45536350688414 # Time in different power states 318system.physmem_1.memoryStateTime::REF 1579636760000 # Time in different power states |
| 323system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 319system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 324system.physmem_1.memoryStateTime::ACT 207555509500 # Time in different power states | 320system.physmem_1.memoryStateTime::ACT 189577142836 # Time in different power states |
| 325system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 326system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory 327system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 328system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory 329system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 330system.realview.nvmem.bytes_read::total 572 # Number of bytes read from this memory 331system.realview.nvmem.bytes_inst_read::cpu0.inst 384 # Number of instructions bytes read from this memory 332system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory --- 17 unchanged lines hidden (view full) --- 350system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 351system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) 352system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 353system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 354system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 355system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 356system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 357system.cf0.dma_write_txs 1670 # Number of DMA write transactions. | 321system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 322system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory 323system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 324system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory 325system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 326system.realview.nvmem.bytes_read::total 572 # Number of bytes read from this memory 327system.realview.nvmem.bytes_inst_read::cpu0.inst 384 # Number of instructions bytes read from this memory 328system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory --- 17 unchanged lines hidden (view full) --- 346system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 347system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) 348system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 349system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 350system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 351system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 352system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 353system.cf0.dma_write_txs 1670 # Number of DMA write transactions. |
| 358system.cpu0.branchPred.lookups 145356452 # Number of BP lookups 359system.cpu0.branchPred.condPredicted 96435082 # Number of conditional branches predicted 360system.cpu0.branchPred.condIncorrect 7088203 # Number of conditional branches incorrect 361system.cpu0.branchPred.BTBLookups 101789401 # Number of BTB lookups 362system.cpu0.branchPred.BTBHits 67765064 # Number of BTB hits | 354system.cpu0.branchPred.lookups 136259129 # Number of BP lookups 355system.cpu0.branchPred.condPredicted 90543195 # Number of conditional branches predicted 356system.cpu0.branchPred.condIncorrect 6799058 # Number of conditional branches incorrect 357system.cpu0.branchPred.BTBLookups 95853282 # Number of BTB lookups 358system.cpu0.branchPred.BTBHits 62504832 # Number of BTB hits |
| 363system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 359system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 364system.cpu0.branchPred.BTBHitPct 66.573792 # BTB Hit Percentage 365system.cpu0.branchPred.usedRAS 20004195 # Number of times the RAS was used to get a target. 366system.cpu0.branchPred.RASInCorrect 205158 # Number of incorrect RAS predictions. | 360system.cpu0.branchPred.BTBHitPct 65.208860 # BTB Hit Percentage 361system.cpu0.branchPred.usedRAS 18504887 # Number of times the RAS was used to get a target. 362system.cpu0.branchPred.RASInCorrect 186011 # Number of incorrect RAS predictions. |
| 367system.cpu_clk_domain.clock 500 # Clock period in ticks 368system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 369system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 370system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 371system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 372system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 373system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 374system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 389system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 390system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 391system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 392system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 393system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 394system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 395system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 396system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 363system.cpu_clk_domain.clock 500 # Clock period in ticks 364system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 365system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 366system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 367system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 368system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 369system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 370system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 385system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 386system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 387system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 388system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 389system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 390system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 391system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 392system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 397system.cpu0.dtb.walker.walks 580611 # Table walker walks requested 398system.cpu0.dtb.walker.walksLong 580611 # Table walker walks initiated with long descriptors 399system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13679 # Level at which table walker walks with long descriptors terminate 400system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 93135 # Level at which table walker walks with long descriptors terminate 401system.cpu0.dtb.walker.walksSquashedBefore 259311 # Table walks squashed before starting 402system.cpu0.dtb.walker.walkWaitTime::samples 321300 # Table walker wait (enqueue to first request) latency 403system.cpu0.dtb.walker.walkWaitTime::mean 1669.368192 # Table walker wait (enqueue to first request) latency 404system.cpu0.dtb.walker.walkWaitTime::stdev 10492.971715 # Table walker wait (enqueue to first request) latency 405system.cpu0.dtb.walker.walkWaitTime::0-32767 317448 98.80% 98.80% # Table walker wait (enqueue to first request) latency 406system.cpu0.dtb.walker.walkWaitTime::32768-65535 2037 0.63% 99.44% # Table walker wait (enqueue to first request) latency 407system.cpu0.dtb.walker.walkWaitTime::65536-98303 845 0.26% 99.70% # Table walker wait (enqueue to first request) latency 408system.cpu0.dtb.walker.walkWaitTime::98304-131071 576 0.18% 99.88% # Table walker wait (enqueue to first request) latency 409system.cpu0.dtb.walker.walkWaitTime::131072-163839 232 0.07% 99.95% # Table walker wait (enqueue to first request) latency 410system.cpu0.dtb.walker.walkWaitTime::163840-196607 45 0.01% 99.96% # Table walker wait (enqueue to first request) latency 411system.cpu0.dtb.walker.walkWaitTime::196608-229375 28 0.01% 99.97% # Table walker wait (enqueue to first request) latency 412system.cpu0.dtb.walker.walkWaitTime::229376-262143 26 0.01% 99.98% # Table walker wait (enqueue to first request) latency 413system.cpu0.dtb.walker.walkWaitTime::262144-294911 42 0.01% 99.99% # Table walker wait (enqueue to first request) latency 414system.cpu0.dtb.walker.walkWaitTime::294912-327679 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency 415system.cpu0.dtb.walker.walkWaitTime::327680-360447 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency 416system.cpu0.dtb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 417system.cpu0.dtb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 418system.cpu0.dtb.walker.walkWaitTime::425984-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 419system.cpu0.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkWaitTime::total 321300 # Table walker wait (enqueue to first request) latency 421system.cpu0.dtb.walker.walkCompletionTime::samples 293805 # Table walker service (enqueue to completion) latency 422system.cpu0.dtb.walker.walkCompletionTime::mean 15781.864128 # Table walker service (enqueue to completion) latency 423system.cpu0.dtb.walker.walkCompletionTime::gmean 13334.413537 # Table walker service (enqueue to completion) latency 424system.cpu0.dtb.walker.walkCompletionTime::stdev 14277.098383 # Table walker service (enqueue to completion) latency 425system.cpu0.dtb.walker.walkCompletionTime::0-65535 291279 99.14% 99.14% # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1809 0.62% 99.76% # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::131072-196607 367 0.12% 99.88% # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walkCompletionTime::196608-262143 189 0.06% 99.95% # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::262144-327679 105 0.04% 99.98% # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::393216-458751 21 0.01% 100.00% # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::total 293805 # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walksPending::samples 521650035508 # Table walker pending requests distribution 436system.cpu0.dtb.walker.walksPending::mean 0.610400 # Table walker pending requests distribution 437system.cpu0.dtb.walker.walksPending::stdev 0.526555 # Table walker pending requests distribution 438system.cpu0.dtb.walker.walksPending::0-1 520697119508 99.82% 99.82% # Table walker pending requests distribution 439system.cpu0.dtb.walker.walksPending::2-3 543124000 0.10% 99.92% # Table walker pending requests distribution 440system.cpu0.dtb.walker.walksPending::4-5 195186500 0.04% 99.96% # Table walker pending requests distribution 441system.cpu0.dtb.walker.walksPending::6-7 85165500 0.02% 99.98% # Table walker pending requests distribution 442system.cpu0.dtb.walker.walksPending::8-9 70245500 0.01% 99.99% # Table walker pending requests distribution 443system.cpu0.dtb.walker.walksPending::10-11 34070500 0.01% 100.00% # Table walker pending requests distribution 444system.cpu0.dtb.walker.walksPending::12-13 11934000 0.00% 100.00% # Table walker pending requests distribution 445system.cpu0.dtb.walker.walksPending::14-15 12740000 0.00% 100.00% # Table walker pending requests distribution 446system.cpu0.dtb.walker.walksPending::16-17 448500 0.00% 100.00% # Table walker pending requests distribution 447system.cpu0.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution 448system.cpu0.dtb.walker.walksPending::total 521650035508 # Table walker pending requests distribution 449system.cpu0.dtb.walker.walkPageSizes::4K 93135 87.19% 87.19% # Table walker page sizes translated 450system.cpu0.dtb.walker.walkPageSizes::2M 13679 12.81% 100.00% # Table walker page sizes translated 451system.cpu0.dtb.walker.walkPageSizes::total 106814 # Table walker page sizes translated 452system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 580611 # Table walker requests started/completed, data/inst | 393system.cpu0.dtb.walker.walks 520196 # Table walker walks requested 394system.cpu0.dtb.walker.walksLong 520196 # Table walker walks initiated with long descriptors 395system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10690 # Level at which table walker walks with long descriptors terminate 396system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 81668 # Level at which table walker walks with long descriptors terminate 397system.cpu0.dtb.walker.walksSquashedBefore 225929 # Table walks squashed before starting 398system.cpu0.dtb.walker.walkWaitTime::samples 294267 # Table walker wait (enqueue to first request) latency 399system.cpu0.dtb.walker.walkWaitTime::mean 1575.669375 # Table walker wait (enqueue to first request) latency 400system.cpu0.dtb.walker.walkWaitTime::stdev 10064.565371 # Table walker wait (enqueue to first request) latency 401system.cpu0.dtb.walker.walkWaitTime::0-65535 292845 99.52% 99.52% # Table walker wait (enqueue to first request) latency 402system.cpu0.dtb.walker.walkWaitTime::65536-131071 1067 0.36% 99.88% # Table walker wait (enqueue to first request) latency 403system.cpu0.dtb.walker.walkWaitTime::131072-196607 263 0.09% 99.97% # Table walker wait (enqueue to first request) latency 404system.cpu0.dtb.walker.walkWaitTime::196608-262143 47 0.02% 99.98% # Table walker wait (enqueue to first request) latency 405system.cpu0.dtb.walker.walkWaitTime::262144-327679 36 0.01% 100.00% # Table walker wait (enqueue to first request) latency 406system.cpu0.dtb.walker.walkWaitTime::327680-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 407system.cpu0.dtb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 408system.cpu0.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency 409system.cpu0.dtb.walker.walkWaitTime::total 294267 # Table walker wait (enqueue to first request) latency 410system.cpu0.dtb.walker.walkCompletionTime::samples 252771 # Table walker service (enqueue to completion) latency 411system.cpu0.dtb.walker.walkCompletionTime::mean 15945.045037 # Table walker service (enqueue to completion) latency 412system.cpu0.dtb.walker.walkCompletionTime::gmean 13637.155107 # Table walker service (enqueue to completion) latency 413system.cpu0.dtb.walker.walkCompletionTime::stdev 11018.196964 # Table walker service (enqueue to completion) latency 414system.cpu0.dtb.walker.walkCompletionTime::0-32767 241135 95.40% 95.40% # Table walker service (enqueue to completion) latency 415system.cpu0.dtb.walker.walkCompletionTime::32768-65535 10520 4.16% 99.56% # Table walker service (enqueue to completion) latency 416system.cpu0.dtb.walker.walkCompletionTime::65536-98303 548 0.22% 99.78% # Table walker service (enqueue to completion) latency 417system.cpu0.dtb.walker.walkCompletionTime::98304-131071 339 0.13% 99.91% # Table walker service (enqueue to completion) latency 418system.cpu0.dtb.walker.walkCompletionTime::131072-163839 68 0.03% 99.94% # Table walker service (enqueue to completion) latency 419system.cpu0.dtb.walker.walkCompletionTime::163840-196607 47 0.02% 99.95% # Table walker service (enqueue to completion) latency 420system.cpu0.dtb.walker.walkCompletionTime::196608-229375 65 0.03% 99.98% # Table walker service (enqueue to completion) latency 421system.cpu0.dtb.walker.walkCompletionTime::229376-262143 16 0.01% 99.99% # Table walker service (enqueue to completion) latency 422system.cpu0.dtb.walker.walkCompletionTime::262144-294911 9 0.00% 99.99% # Table walker service (enqueue to completion) latency 423system.cpu0.dtb.walker.walkCompletionTime::294912-327679 12 0.00% 100.00% # Table walker service (enqueue to completion) latency 424system.cpu0.dtb.walker.walkCompletionTime::327680-360447 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 425system.cpu0.dtb.walker.walkCompletionTime::360448-393215 6 0.00% 100.00% # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::total 252771 # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walksPending::samples 499007353192 # Table walker pending requests distribution 429system.cpu0.dtb.walker.walksPending::mean 0.597965 # Table walker pending requests distribution 430system.cpu0.dtb.walker.walksPending::stdev 0.527283 # Table walker pending requests distribution 431system.cpu0.dtb.walker.walksPending::0-1 498187132192 99.84% 99.84% # Table walker pending requests distribution 432system.cpu0.dtb.walker.walksPending::2-3 450171500 0.09% 99.93% # Table walker pending requests distribution 433system.cpu0.dtb.walker.walksPending::4-5 169118500 0.03% 99.96% # Table walker pending requests distribution 434system.cpu0.dtb.walker.walksPending::6-7 80846500 0.02% 99.98% # Table walker pending requests distribution 435system.cpu0.dtb.walker.walksPending::8-9 62229500 0.01% 99.99% # Table walker pending requests distribution 436system.cpu0.dtb.walker.walksPending::10-11 34680000 0.01% 100.00% # Table walker pending requests distribution 437system.cpu0.dtb.walker.walksPending::12-13 10096500 0.00% 100.00% # Table walker pending requests distribution 438system.cpu0.dtb.walker.walksPending::14-15 12800000 0.00% 100.00% # Table walker pending requests distribution 439system.cpu0.dtb.walker.walksPending::16-17 278500 0.00% 100.00% # Table walker pending requests distribution 440system.cpu0.dtb.walker.walksPending::total 499007353192 # Table walker pending requests distribution 441system.cpu0.dtb.walker.walkPageSizes::4K 81668 88.43% 88.43% # Table walker page sizes translated 442system.cpu0.dtb.walker.walkPageSizes::2M 10690 11.57% 100.00% # Table walker page sizes translated 443system.cpu0.dtb.walker.walkPageSizes::total 92358 # Table walker page sizes translated 444system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 520196 # Table walker requests started/completed, data/inst |
| 453system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 445system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 454system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 580611 # Table walker requests started/completed, data/inst 455system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106814 # Table walker requests started/completed, data/inst | 446system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 520196 # Table walker requests started/completed, data/inst 447system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 92358 # Table walker requests started/completed, data/inst |
| 456system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 448system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 457system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106814 # Table walker requests started/completed, data/inst 458system.cpu0.dtb.walker.walkRequestOrigin::total 687425 # Table walker requests started/completed, data/inst | 449system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 92358 # Table walker requests started/completed, data/inst 450system.cpu0.dtb.walker.walkRequestOrigin::total 612554 # Table walker requests started/completed, data/inst |
| 459system.cpu0.dtb.inst_hits 0 # ITB inst hits 460system.cpu0.dtb.inst_misses 0 # ITB inst misses | 451system.cpu0.dtb.inst_hits 0 # ITB inst hits 452system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 461system.cpu0.dtb.read_hits 105404836 # DTB read hits 462system.cpu0.dtb.read_misses 420652 # DTB read misses 463system.cpu0.dtb.write_hits 86890500 # DTB write hits 464system.cpu0.dtb.write_misses 159959 # DTB write misses | 453system.cpu0.dtb.read_hits 98496070 # DTB read hits 454system.cpu0.dtb.read_misses 369414 # DTB read misses 455system.cpu0.dtb.write_hits 81551465 # DTB write hits 456system.cpu0.dtb.write_misses 150782 # DTB write misses |
| 465system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 466system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 457system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 458system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 467system.cpu0.dtb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID 468system.cpu0.dtb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID 469system.cpu0.dtb.flush_entries 40944 # Number of entries that have been flushed from TLB 470system.cpu0.dtb.align_faults 605 # Number of TLB faults due to alignment restrictions 471system.cpu0.dtb.prefetch_faults 8089 # Number of TLB faults due to prefetch | 459system.cpu0.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID 460system.cpu0.dtb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID 461system.cpu0.dtb.flush_entries 36102 # Number of entries that have been flushed from TLB 462system.cpu0.dtb.align_faults 400 # Number of TLB faults due to alignment restrictions 463system.cpu0.dtb.prefetch_faults 5365 # Number of TLB faults due to prefetch |
| 472system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 464system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 473system.cpu0.dtb.perms_faults 40127 # Number of TLB faults due to permissions restrictions 474system.cpu0.dtb.read_accesses 105825488 # DTB read accesses 475system.cpu0.dtb.write_accesses 87050459 # DTB write accesses | 465system.cpu0.dtb.perms_faults 40284 # Number of TLB faults due to permissions restrictions 466system.cpu0.dtb.read_accesses 98865484 # DTB read accesses 467system.cpu0.dtb.write_accesses 81702247 # DTB write accesses |
| 476system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 468system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 477system.cpu0.dtb.hits 192295336 # DTB hits 478system.cpu0.dtb.misses 580611 # DTB misses 479system.cpu0.dtb.accesses 192875947 # DTB accesses | 469system.cpu0.dtb.hits 180047535 # DTB hits 470system.cpu0.dtb.misses 520196 # DTB misses 471system.cpu0.dtb.accesses 180567731 # DTB accesses |
| 480system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 481system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 501system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 502system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 503system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 504system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 505system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 506system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 507system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 508system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 472system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 473system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 474system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 475system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 476system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 477system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 478system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 479system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 493system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 494system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 495system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 496system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 497system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 498system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 499system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 500system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 509system.cpu0.itb.walker.walks 84622 # Table walker walks requested 510system.cpu0.itb.walker.walksLong 84622 # Table walker walks initiated with long descriptors 511system.cpu0.itb.walker.walksLongTerminationLevel::Level2 994 # Level at which table walker walks with long descriptors terminate 512system.cpu0.itb.walker.walksLongTerminationLevel::Level3 61729 # Level at which table walker walks with long descriptors terminate 513system.cpu0.itb.walker.walksSquashedBefore 9515 # Table walks squashed before starting 514system.cpu0.itb.walker.walkWaitTime::samples 75107 # Table walker wait (enqueue to first request) latency 515system.cpu0.itb.walker.walkWaitTime::mean 1146.297948 # Table walker wait (enqueue to first request) latency 516system.cpu0.itb.walker.walkWaitTime::stdev 8819.384812 # Table walker wait (enqueue to first request) latency 517system.cpu0.itb.walker.walkWaitTime::0-32767 74551 99.26% 99.26% # Table walker wait (enqueue to first request) latency 518system.cpu0.itb.walker.walkWaitTime::32768-65535 182 0.24% 99.50% # Table walker wait (enqueue to first request) latency 519system.cpu0.itb.walker.walkWaitTime::65536-98303 223 0.30% 99.80% # Table walker wait (enqueue to first request) latency 520system.cpu0.itb.walker.walkWaitTime::98304-131071 112 0.15% 99.95% # Table walker wait (enqueue to first request) latency 521system.cpu0.itb.walker.walkWaitTime::131072-163839 5 0.01% 99.95% # Table walker wait (enqueue to first request) latency 522system.cpu0.itb.walker.walkWaitTime::163840-196607 9 0.01% 99.97% # Table walker wait (enqueue to first request) latency 523system.cpu0.itb.walker.walkWaitTime::196608-229375 12 0.02% 99.98% # Table walker wait (enqueue to first request) latency 524system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency 525system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency 526system.cpu0.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 527system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 528system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 529system.cpu0.itb.walker.walkWaitTime::total 75107 # Table walker wait (enqueue to first request) latency 530system.cpu0.itb.walker.walkCompletionTime::samples 72238 # Table walker service (enqueue to completion) latency 531system.cpu0.itb.walker.walkCompletionTime::mean 20242.257302 # Table walker service (enqueue to completion) latency 532system.cpu0.itb.walker.walkCompletionTime::gmean 17307.169845 # Table walker service (enqueue to completion) latency 533system.cpu0.itb.walker.walkCompletionTime::stdev 18587.015651 # Table walker service (enqueue to completion) latency 534system.cpu0.itb.walker.walkCompletionTime::0-65535 70635 97.78% 97.78% # Table walker service (enqueue to completion) latency 535system.cpu0.itb.walker.walkCompletionTime::65536-131071 1318 1.82% 99.61% # Table walker service (enqueue to completion) latency 536system.cpu0.itb.walker.walkCompletionTime::131072-196607 148 0.20% 99.81% # Table walker service (enqueue to completion) latency 537system.cpu0.itb.walker.walkCompletionTime::196608-262143 80 0.11% 99.92% # Table walker service (enqueue to completion) latency 538system.cpu0.itb.walker.walkCompletionTime::262144-327679 29 0.04% 99.96% # Table walker service (enqueue to completion) latency 539system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.98% # Table walker service (enqueue to completion) latency 540system.cpu0.itb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 541system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency | 501system.cpu0.itb.walker.walks 81590 # Table walker walks requested 502system.cpu0.itb.walker.walksLong 81590 # Table walker walks initiated with long descriptors 503system.cpu0.itb.walker.walksLongTerminationLevel::Level2 901 # Level at which table walker walks with long descriptors terminate 504system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59909 # Level at which table walker walks with long descriptors terminate 505system.cpu0.itb.walker.walksSquashedBefore 9188 # Table walks squashed before starting 506system.cpu0.itb.walker.walkWaitTime::samples 72402 # Table walker wait (enqueue to first request) latency 507system.cpu0.itb.walker.walkWaitTime::mean 845.170023 # Table walker wait (enqueue to first request) latency 508system.cpu0.itb.walker.walkWaitTime::stdev 6470.995618 # Table walker wait (enqueue to first request) latency 509system.cpu0.itb.walker.walkWaitTime::0-32767 72024 99.48% 99.48% # Table walker wait (enqueue to first request) latency 510system.cpu0.itb.walker.walkWaitTime::32768-65535 242 0.33% 99.81% # Table walker wait (enqueue to first request) latency 511system.cpu0.itb.walker.walkWaitTime::65536-98303 56 0.08% 99.89% # Table walker wait (enqueue to first request) latency 512system.cpu0.itb.walker.walkWaitTime::98304-131071 61 0.08% 99.97% # Table walker wait (enqueue to first request) latency 513system.cpu0.itb.walker.walkWaitTime::131072-163839 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency 514system.cpu0.itb.walker.walkWaitTime::163840-196607 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency 515system.cpu0.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency 516system.cpu0.itb.walker.walkWaitTime::229376-262143 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 517system.cpu0.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 518system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 519system.cpu0.itb.walker.walkWaitTime::total 72402 # Table walker wait (enqueue to first request) latency 520system.cpu0.itb.walker.walkCompletionTime::samples 69998 # Table walker service (enqueue to completion) latency 521system.cpu0.itb.walker.walkCompletionTime::mean 20035.793294 # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walkCompletionTime::gmean 17827.568317 # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walkCompletionTime::stdev 13688.582598 # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walkCompletionTime::0-65535 69301 99.00% 99.00% # Table walker service (enqueue to completion) latency 525system.cpu0.itb.walker.walkCompletionTime::65536-131071 578 0.83% 99.83% # Table walker service (enqueue to completion) latency 526system.cpu0.itb.walker.walkCompletionTime::131072-196607 67 0.10% 99.93% # Table walker service (enqueue to completion) latency 527system.cpu0.itb.walker.walkCompletionTime::196608-262143 29 0.04% 99.97% # Table walker service (enqueue to completion) latency 528system.cpu0.itb.walker.walkCompletionTime::262144-327679 14 0.02% 99.99% # Table walker service (enqueue to completion) latency 529system.cpu0.itb.walker.walkCompletionTime::327680-393215 7 0.01% 100.00% # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency |
| 542system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency | 531system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency |
| 543system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 544system.cpu0.itb.walker.walkCompletionTime::total 72238 # Table walker service (enqueue to completion) latency 545system.cpu0.itb.walker.walksPending::samples 405678068016 # Table walker pending requests distribution 546system.cpu0.itb.walker.walksPending::mean 0.851697 # Table walker pending requests distribution 547system.cpu0.itb.walker.walksPending::stdev 0.355553 # Table walker pending requests distribution 548system.cpu0.itb.walker.walksPending::0 60184359568 14.84% 14.84% # Table walker pending requests distribution 549system.cpu0.itb.walker.walksPending::1 345473805948 85.16% 100.00% # Table walker pending requests distribution 550system.cpu0.itb.walker.walksPending::2 18871000 0.00% 100.00% # Table walker pending requests distribution 551system.cpu0.itb.walker.walksPending::3 1025500 0.00% 100.00% # Table walker pending requests distribution 552system.cpu0.itb.walker.walksPending::4 6000 0.00% 100.00% # Table walker pending requests distribution 553system.cpu0.itb.walker.walksPending::total 405678068016 # Table walker pending requests distribution 554system.cpu0.itb.walker.walkPageSizes::4K 61729 98.42% 98.42% # Table walker page sizes translated 555system.cpu0.itb.walker.walkPageSizes::2M 994 1.58% 100.00% # Table walker page sizes translated 556system.cpu0.itb.walker.walkPageSizes::total 62723 # Table walker page sizes translated | 532system.cpu0.itb.walker.walkCompletionTime::total 69998 # Table walker service (enqueue to completion) latency 533system.cpu0.itb.walker.walksPending::samples 370135740312 # Table walker pending requests distribution 534system.cpu0.itb.walker.walksPending::mean 0.825869 # Table walker pending requests distribution 535system.cpu0.itb.walker.walksPending::stdev 0.379347 # Table walker pending requests distribution 536system.cpu0.itb.walker.walksPending::0 64468447528 17.42% 17.42% # Table walker pending requests distribution 537system.cpu0.itb.walker.walksPending::1 305652352784 82.58% 100.00% # Table walker pending requests distribution 538system.cpu0.itb.walker.walksPending::2 13699000 0.00% 100.00% # Table walker pending requests distribution 539system.cpu0.itb.walker.walksPending::3 1205500 0.00% 100.00% # Table walker pending requests distribution 540system.cpu0.itb.walker.walksPending::4 35500 0.00% 100.00% # Table walker pending requests distribution 541system.cpu0.itb.walker.walksPending::total 370135740312 # Table walker pending requests distribution 542system.cpu0.itb.walker.walkPageSizes::4K 59909 98.52% 98.52% # Table walker page sizes translated 543system.cpu0.itb.walker.walkPageSizes::2M 901 1.48% 100.00% # Table walker page sizes translated 544system.cpu0.itb.walker.walkPageSizes::total 60810 # Table walker page sizes translated |
| 557system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 545system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 558system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 84622 # Table walker requests started/completed, data/inst 559system.cpu0.itb.walker.walkRequestOrigin_Requested::total 84622 # Table walker requests started/completed, data/inst | 546system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 81590 # Table walker requests started/completed, data/inst 547system.cpu0.itb.walker.walkRequestOrigin_Requested::total 81590 # Table walker requests started/completed, data/inst |
| 560system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 548system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 561system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 62723 # Table walker requests started/completed, data/inst 562system.cpu0.itb.walker.walkRequestOrigin_Completed::total 62723 # Table walker requests started/completed, data/inst 563system.cpu0.itb.walker.walkRequestOrigin::total 147345 # Table walker requests started/completed, data/inst 564system.cpu0.itb.inst_hits 229226252 # ITB inst hits 565system.cpu0.itb.inst_misses 84622 # ITB inst misses | 549system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60810 # Table walker requests started/completed, data/inst 550system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60810 # Table walker requests started/completed, data/inst 551system.cpu0.itb.walker.walkRequestOrigin::total 142400 # Table walker requests started/completed, data/inst 552system.cpu0.itb.inst_hits 213929001 # ITB inst hits 553system.cpu0.itb.inst_misses 81590 # ITB inst misses |
| 566system.cpu0.itb.read_hits 0 # DTB read hits 567system.cpu0.itb.read_misses 0 # DTB read misses 568system.cpu0.itb.write_hits 0 # DTB write hits 569system.cpu0.itb.write_misses 0 # DTB write misses 570system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 571system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 554system.cpu0.itb.read_hits 0 # DTB read hits 555system.cpu0.itb.read_misses 0 # DTB read misses 556system.cpu0.itb.write_hits 0 # DTB write hits 557system.cpu0.itb.write_misses 0 # DTB write misses 558system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 559system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 572system.cpu0.itb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID 573system.cpu0.itb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID 574system.cpu0.itb.flush_entries 29308 # Number of entries that have been flushed from TLB | 560system.cpu0.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID 561system.cpu0.itb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID 562system.cpu0.itb.flush_entries 25953 # Number of entries that have been flushed from TLB |
| 575system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 576system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 577system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 563system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 564system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 565system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 578system.cpu0.itb.perms_faults 225641 # Number of TLB faults due to permissions restrictions | 566system.cpu0.itb.perms_faults 203878 # Number of TLB faults due to permissions restrictions |
| 579system.cpu0.itb.read_accesses 0 # DTB read accesses 580system.cpu0.itb.write_accesses 0 # DTB write accesses | 567system.cpu0.itb.read_accesses 0 # DTB read accesses 568system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 581system.cpu0.itb.inst_accesses 229310874 # ITB inst accesses 582system.cpu0.itb.hits 229226252 # DTB hits 583system.cpu0.itb.misses 84622 # DTB misses 584system.cpu0.itb.accesses 229310874 # DTB accesses 585system.cpu0.numCycles 787784387 # number of cpu cycles simulated | 569system.cpu0.itb.inst_accesses 214010591 # ITB inst accesses 570system.cpu0.itb.hits 213929001 # DTB hits 571system.cpu0.itb.misses 81590 # DTB misses 572system.cpu0.itb.accesses 214010591 # DTB accesses 573system.cpu0.numCycles 728554790 # number of cpu cycles simulated |
| 586system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 587system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 574system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 575system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 588system.cpu0.fetch.icacheStallCycles 93175923 # Number of cycles fetch is stalled on an Icache miss 589system.cpu0.fetch.Insts 642526185 # Number of instructions fetch has processed 590system.cpu0.fetch.Branches 145356452 # Number of branches that fetch encountered 591system.cpu0.fetch.predictedBranches 87769259 # Number of branches that fetch has predicted taken 592system.cpu0.fetch.Cycles 654798115 # Number of cycles fetch has run and was not squashing or blocked 593system.cpu0.fetch.SquashCycles 15283958 # Number of cycles fetch has spent squashing 594system.cpu0.fetch.TlbCycles 1702071 # Number of cycles fetch has spent waiting for tlb 595system.cpu0.fetch.MiscStallCycles 255624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 596system.cpu0.fetch.PendingTrapStallCycles 6308926 # Number of stall cycles due to pending traps 597system.cpu0.fetch.PendingQuiesceStallCycles 745987 # Number of stall cycles due to pending quiesce instructions 598system.cpu0.fetch.IcacheWaitRetryStallCycles 671334 # Number of stall cycles due to full MSHR 599system.cpu0.fetch.CacheLines 229000663 # Number of cache lines fetched 600system.cpu0.fetch.IcacheSquashes 1782311 # Number of outstanding Icache misses that were squashed 601system.cpu0.fetch.ItlbSquashes 27660 # Number of outstanding ITLB misses that were squashed 602system.cpu0.fetch.rateDist::samples 765299959 # Number of instructions fetched each cycle (Total) 603system.cpu0.fetch.rateDist::mean 0.983676 # Number of instructions fetched each cycle (Total) 604system.cpu0.fetch.rateDist::stdev 1.220176 # Number of instructions fetched each cycle (Total) | 576system.cpu0.fetch.icacheStallCycles 88185009 # Number of cycles fetch is stalled on an Icache miss 577system.cpu0.fetch.Insts 601844339 # Number of instructions fetch has processed 578system.cpu0.fetch.Branches 136259129 # Number of branches that fetch encountered 579system.cpu0.fetch.predictedBranches 81009719 # Number of branches that fetch has predicted taken 580system.cpu0.fetch.Cycles 601618645 # Number of cycles fetch has run and was not squashing or blocked 581system.cpu0.fetch.SquashCycles 14617520 # Number of cycles fetch has spent squashing 582system.cpu0.fetch.TlbCycles 1590376 # Number of cycles fetch has spent waiting for tlb 583system.cpu0.fetch.MiscStallCycles 274448 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 584system.cpu0.fetch.PendingTrapStallCycles 5655980 # Number of stall cycles due to pending traps 585system.cpu0.fetch.PendingQuiesceStallCycles 730298 # Number of stall cycles due to pending quiesce instructions 586system.cpu0.fetch.IcacheWaitRetryStallCycles 721373 # Number of stall cycles due to full MSHR 587system.cpu0.fetch.CacheLines 213725526 # Number of cache lines fetched 588system.cpu0.fetch.IcacheSquashes 1720356 # Number of outstanding Icache misses that were squashed 589system.cpu0.fetch.ItlbSquashes 27419 # Number of outstanding ITLB misses that were squashed 590system.cpu0.fetch.rateDist::samples 706084889 # Number of instructions fetched each cycle (Total) 591system.cpu0.fetch.rateDist::mean 0.998504 # Number of instructions fetched each cycle (Total) 592system.cpu0.fetch.rateDist::stdev 1.224315 # Number of instructions fetched each cycle (Total) |
| 605system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 593system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 606system.cpu0.fetch.rateDist::0 404626902 52.87% 52.87% # Number of instructions fetched each cycle (Total) 607system.cpu0.fetch.rateDist::1 139960190 18.29% 71.16% # Number of instructions fetched each cycle (Total) 608system.cpu0.fetch.rateDist::2 49291261 6.44% 77.60% # Number of instructions fetched each cycle (Total) 609system.cpu0.fetch.rateDist::3 171421606 22.40% 100.00% # Number of instructions fetched each cycle (Total) | 594system.cpu0.fetch.rateDist::0 368651970 52.21% 52.21% # Number of instructions fetched each cycle (Total) 595system.cpu0.fetch.rateDist::1 130906496 18.54% 70.75% # Number of instructions fetched each cycle (Total) 596system.cpu0.fetch.rateDist::2 45457211 6.44% 77.19% # Number of instructions fetched each cycle (Total) 597system.cpu0.fetch.rateDist::3 161069212 22.81% 100.00% # Number of instructions fetched each cycle (Total) |
| 610system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 611system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 612system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 598system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 599system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 600system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 613system.cpu0.fetch.rateDist::total 765299959 # Number of instructions fetched each cycle (Total) 614system.cpu0.fetch.branchRate 0.184513 # Number of branch fetches per cycle 615system.cpu0.fetch.rate 0.815612 # Number of inst fetches per cycle 616system.cpu0.decode.IdleCycles 110781464 # Number of cycles decode is idle 617system.cpu0.decode.BlockedCycles 368356745 # Number of cycles decode is blocked 618system.cpu0.decode.RunCycles 241543971 # Number of cycles decode is running 619system.cpu0.decode.UnblockCycles 39160465 # Number of cycles decode is unblocking 620system.cpu0.decode.SquashCycles 5457314 # Number of cycles decode is squashing 621system.cpu0.decode.BranchResolved 20998766 # Number of times decode resolved a branch 622system.cpu0.decode.BranchMispred 2230758 # Number of times decode detected a branch misprediction 623system.cpu0.decode.DecodedInsts 666506782 # Number of instructions handled by decode 624system.cpu0.decode.SquashedInsts 24554495 # Number of squashed instructions handled by decode 625system.cpu0.rename.SquashCycles 5457314 # Number of cycles rename is squashing 626system.cpu0.rename.IdleCycles 147799214 # Number of cycles rename is idle 627system.cpu0.rename.BlockCycles 53385858 # Number of cycles rename is blocking 628system.cpu0.rename.serializeStallCycles 247347968 # count of cycles rename stalled for serializing inst 629system.cpu0.rename.RunCycles 243020975 # Number of cycles rename is running 630system.cpu0.rename.UnblockCycles 68288630 # Number of cycles rename is unblocking 631system.cpu0.rename.RenamedInsts 648373688 # Number of instructions processed by rename 632system.cpu0.rename.SquashedInsts 6354822 # Number of squashed instructions processed by rename 633system.cpu0.rename.ROBFullEvents 9340488 # Number of times rename has blocked due to ROB full 634system.cpu0.rename.IQFullEvents 358878 # Number of times rename has blocked due to IQ full 635system.cpu0.rename.LQFullEvents 691420 # Number of times rename has blocked due to LQ full 636system.cpu0.rename.SQFullEvents 31770877 # Number of times rename has blocked due to SQ full 637system.cpu0.rename.FullRegisterEvents 13042 # Number of times there has been no free registers 638system.cpu0.rename.RenamedOperands 618836498 # Number of destination operands rename has renamed 639system.cpu0.rename.RenameLookups 1000163983 # Number of register rename lookups that rename has made 640system.cpu0.rename.int_rename_lookups 765756832 # Number of integer rename lookups 641system.cpu0.rename.fp_rename_lookups 980941 # Number of floating rename lookups 642system.cpu0.rename.CommittedMaps 557557100 # Number of HB maps that are committed 643system.cpu0.rename.UndoneMaps 61279388 # Number of HB maps that are undone due to squashing 644system.cpu0.rename.serializingInsts 16104693 # count of serializing insts renamed 645system.cpu0.rename.tempSerializingInsts 13959035 # count of temporary serializing insts renamed 646system.cpu0.rename.skidInsts 79116837 # count of insts added to the skid buffer 647system.cpu0.memDep0.insertedLoads 106280749 # Number of loads inserted to the mem dependence unit. 648system.cpu0.memDep0.insertedStores 90455195 # Number of stores inserted to the mem dependence unit. 649system.cpu0.memDep0.conflictingLoads 9698755 # Number of conflicting loads. 650system.cpu0.memDep0.conflictingStores 8363084 # Number of conflicting stores. 651system.cpu0.iq.iqInstsAdded 625354037 # Number of instructions added to the IQ (excludes non-spec) 652system.cpu0.iq.iqNonSpecInstsAdded 16149817 # Number of non-speculative instructions added to the IQ 653system.cpu0.iq.iqInstsIssued 628774014 # Number of instructions issued 654system.cpu0.iq.iqSquashedInstsIssued 2896491 # Number of squashed instructions issued 655system.cpu0.iq.iqSquashedInstsExamined 54006760 # Number of squashed instructions iterated over during squash; mainly for profiling 656system.cpu0.iq.iqSquashedOperandsExamined 37569824 # Number of squashed operands that are examined and possibly removed from graph 657system.cpu0.iq.iqSquashedNonSpecRemoved 287316 # Number of squashed non-spec instructions that were removed 658system.cpu0.iq.issued_per_cycle::samples 765299959 # Number of insts issued each cycle 659system.cpu0.iq.issued_per_cycle::mean 0.821605 # Number of insts issued each cycle 660system.cpu0.iq.issued_per_cycle::stdev 1.068919 # Number of insts issued each cycle | 601system.cpu0.fetch.rateDist::total 706084889 # Number of instructions fetched each cycle (Total) 602system.cpu0.fetch.branchRate 0.187027 # Number of branch fetches per cycle 603system.cpu0.fetch.rate 0.826080 # Number of inst fetches per cycle 604system.cpu0.decode.IdleCycles 103877352 # Number of cycles decode is idle 605system.cpu0.decode.BlockedCycles 333585554 # Number of cycles decode is blocked 606system.cpu0.decode.RunCycles 228251571 # Number of cycles decode is running 607system.cpu0.decode.UnblockCycles 35190646 # Number of cycles decode is unblocking 608system.cpu0.decode.SquashCycles 5179766 # Number of cycles decode is squashing 609system.cpu0.decode.BranchResolved 19720762 # Number of times decode resolved a branch 610system.cpu0.decode.BranchMispred 2170804 # Number of times decode detected a branch misprediction 611system.cpu0.decode.DecodedInsts 623516514 # Number of instructions handled by decode 612system.cpu0.decode.SquashedInsts 23718954 # Number of squashed instructions handled by decode 613system.cpu0.rename.SquashCycles 5179766 # Number of cycles rename is squashing 614system.cpu0.rename.IdleCycles 138234059 # Number of cycles rename is idle 615system.cpu0.rename.BlockCycles 46790455 # Number of cycles rename is blocking 616system.cpu0.rename.serializeStallCycles 227164838 # count of cycles rename stalled for serializing inst 617system.cpu0.rename.RunCycles 228535971 # Number of cycles rename is running 618system.cpu0.rename.UnblockCycles 60179800 # Number of cycles rename is unblocking 619system.cpu0.rename.RenamedInsts 606373965 # Number of instructions processed by rename 620system.cpu0.rename.SquashedInsts 6065859 # Number of squashed instructions processed by rename 621system.cpu0.rename.ROBFullEvents 8641063 # Number of times rename has blocked due to ROB full 622system.cpu0.rename.IQFullEvents 231610 # Number of times rename has blocked due to IQ full 623system.cpu0.rename.LQFullEvents 454065 # Number of times rename has blocked due to LQ full 624system.cpu0.rename.SQFullEvents 27284745 # Number of times rename has blocked due to SQ full 625system.cpu0.rename.FullRegisterEvents 11061 # Number of times there has been no free registers 626system.cpu0.rename.RenamedOperands 577786095 # Number of destination operands rename has renamed 627system.cpu0.rename.RenameLookups 931076470 # Number of register rename lookups that rename has made 628system.cpu0.rename.int_rename_lookups 716156173 # Number of integer rename lookups 629system.cpu0.rename.fp_rename_lookups 752358 # Number of floating rename lookups 630system.cpu0.rename.CommittedMaps 519674265 # Number of HB maps that are committed 631system.cpu0.rename.UndoneMaps 58111818 # Number of HB maps that are undone due to squashing 632system.cpu0.rename.serializingInsts 14452887 # count of serializing insts renamed 633system.cpu0.rename.tempSerializingInsts 12546195 # count of temporary serializing insts renamed 634system.cpu0.rename.skidInsts 71496186 # count of insts added to the skid buffer 635system.cpu0.memDep0.insertedLoads 99205558 # Number of loads inserted to the mem dependence unit. 636system.cpu0.memDep0.insertedStores 84922074 # Number of stores inserted to the mem dependence unit. 637system.cpu0.memDep0.conflictingLoads 8773729 # Number of conflicting loads. 638system.cpu0.memDep0.conflictingStores 7651066 # Number of conflicting stores. 639system.cpu0.iq.iqInstsAdded 585335843 # Number of instructions added to the IQ (excludes non-spec) 640system.cpu0.iq.iqNonSpecInstsAdded 14506928 # Number of non-speculative instructions added to the IQ 641system.cpu0.iq.iqInstsIssued 587846614 # Number of instructions issued 642system.cpu0.iq.iqSquashedInstsIssued 2739409 # Number of squashed instructions issued 643system.cpu0.iq.iqSquashedInstsExamined 51306825 # Number of squashed instructions iterated over during squash; mainly for profiling 644system.cpu0.iq.iqSquashedOperandsExamined 35502721 # Number of squashed operands that are examined and possibly removed from graph 645system.cpu0.iq.iqSquashedNonSpecRemoved 263475 # Number of squashed non-spec instructions that were removed 646system.cpu0.iq.issued_per_cycle::samples 706084889 # Number of insts issued each cycle 647system.cpu0.iq.issued_per_cycle::mean 0.832544 # Number of insts issued each cycle 648system.cpu0.iq.issued_per_cycle::stdev 1.074450 # Number of insts issued each cycle |
| 661system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 649system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 662system.cpu0.iq.issued_per_cycle::0 423230722 55.30% 55.30% # Number of insts issued each cycle 663system.cpu0.iq.issued_per_cycle::1 141522259 18.49% 73.79% # Number of insts issued each cycle 664system.cpu0.iq.issued_per_cycle::2 122647115 16.03% 89.82% # Number of insts issued each cycle 665system.cpu0.iq.issued_per_cycle::3 69647275 9.10% 98.92% # Number of insts issued each cycle 666system.cpu0.iq.issued_per_cycle::4 8247243 1.08% 100.00% # Number of insts issued each cycle 667system.cpu0.iq.issued_per_cycle::5 5342 0.00% 100.00% # Number of insts issued each cycle 668system.cpu0.iq.issued_per_cycle::6 3 0.00% 100.00% # Number of insts issued each cycle | 650system.cpu0.iq.issued_per_cycle::0 387752647 54.92% 54.92% # Number of insts issued each cycle 651system.cpu0.iq.issued_per_cycle::1 129908491 18.40% 73.31% # Number of insts issued each cycle 652system.cpu0.iq.issued_per_cycle::2 115071565 16.30% 89.61% # Number of insts issued each cycle 653system.cpu0.iq.issued_per_cycle::3 65618038 9.29% 98.90% # Number of insts issued each cycle 654system.cpu0.iq.issued_per_cycle::4 7729861 1.09% 100.00% # Number of insts issued each cycle 655system.cpu0.iq.issued_per_cycle::5 4287 0.00% 100.00% # Number of insts issued each cycle 656system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle |
| 669system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 670system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 671system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 672system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle | 657system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 658system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 659system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 660system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle |
| 673system.cpu0.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle 674system.cpu0.iq.issued_per_cycle::total 765299959 # Number of insts issued each cycle | 661system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 662system.cpu0.iq.issued_per_cycle::total 706084889 # Number of insts issued each cycle |
| 675system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 663system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 676system.cpu0.iq.fu_full::IntAlu 65414267 45.68% 45.68% # attempts to use FU when none available 677system.cpu0.iq.fu_full::IntMult 59912 0.04% 45.72% # attempts to use FU when none available 678system.cpu0.iq.fu_full::IntDiv 17829 0.01% 45.73% # attempts to use FU when none available 679system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.73% # attempts to use FU when none available 680system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.73% # attempts to use FU when none available 681system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.73% # attempts to use FU when none available 682system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.73% # attempts to use FU when none available 683system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.73% # attempts to use FU when none available 684system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.73% # attempts to use FU when none available 685system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.73% # attempts to use FU when none available 686system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.73% # attempts to use FU when none available 687system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.73% # attempts to use FU when none available 688system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.73% # attempts to use FU when none available 689system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.73% # attempts to use FU when none available 690system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.73% # attempts to use FU when none available 691system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.73% # attempts to use FU when none available 692system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.73% # attempts to use FU when none available 693system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.73% # attempts to use FU when none available 694system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.73% # attempts to use FU when none available 695system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.73% # attempts to use FU when none available 696system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.73% # attempts to use FU when none available 697system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.73% # attempts to use FU when none available 698system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.73% # attempts to use FU when none available 699system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.73% # attempts to use FU when none available 700system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.73% # attempts to use FU when none available 701system.cpu0.iq.fu_full::SimdFloatMisc 19 0.00% 45.73% # attempts to use FU when none available 702system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.73% # attempts to use FU when none available 703system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.73% # attempts to use FU when none available 704system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.73% # attempts to use FU when none available 705system.cpu0.iq.fu_full::MemRead 37349884 26.08% 71.81% # attempts to use FU when none available 706system.cpu0.iq.fu_full::MemWrite 40363750 28.19% 100.00% # attempts to use FU when none available | 664system.cpu0.iq.fu_full::IntAlu 62081849 46.00% 46.00% # attempts to use FU when none available 665system.cpu0.iq.fu_full::IntMult 53806 0.04% 46.04% # attempts to use FU when none available 666system.cpu0.iq.fu_full::IntDiv 26012 0.02% 46.06% # attempts to use FU when none available 667system.cpu0.iq.fu_full::FloatAdd 0 0.00% 46.06% # attempts to use FU when none available 668system.cpu0.iq.fu_full::FloatCmp 0 0.00% 46.06% # attempts to use FU when none available 669system.cpu0.iq.fu_full::FloatCvt 0 0.00% 46.06% # attempts to use FU when none available 670system.cpu0.iq.fu_full::FloatMult 0 0.00% 46.06% # attempts to use FU when none available 671system.cpu0.iq.fu_full::FloatDiv 0 0.00% 46.06% # attempts to use FU when none available 672system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 46.06% # attempts to use FU when none available 673system.cpu0.iq.fu_full::SimdAdd 0 0.00% 46.06% # attempts to use FU when none available 674system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 46.06% # attempts to use FU when none available 675system.cpu0.iq.fu_full::SimdAlu 0 0.00% 46.06% # attempts to use FU when none available 676system.cpu0.iq.fu_full::SimdCmp 0 0.00% 46.06% # attempts to use FU when none available 677system.cpu0.iq.fu_full::SimdCvt 0 0.00% 46.06% # attempts to use FU when none available 678system.cpu0.iq.fu_full::SimdMisc 0 0.00% 46.06% # attempts to use FU when none available 679system.cpu0.iq.fu_full::SimdMult 0 0.00% 46.06% # attempts to use FU when none available 680system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 46.06% # attempts to use FU when none available 681system.cpu0.iq.fu_full::SimdShift 0 0.00% 46.06% # attempts to use FU when none available 682system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 46.06% # attempts to use FU when none available 683system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 46.06% # attempts to use FU when none available 684system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 46.06% # attempts to use FU when none available 685system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 46.06% # attempts to use FU when none available 686system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 46.06% # attempts to use FU when none available 687system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 46.06% # attempts to use FU when none available 688system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 46.06% # attempts to use FU when none available 689system.cpu0.iq.fu_full::SimdFloatMisc 10 0.00% 46.06% # attempts to use FU when none available 690system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 46.06% # attempts to use FU when none available 691system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 46.06% # attempts to use FU when none available 692system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 46.06% # attempts to use FU when none available 693system.cpu0.iq.fu_full::MemRead 34882864 25.85% 71.91% # attempts to use FU when none available 694system.cpu0.iq.fu_full::MemWrite 37902238 28.09% 100.00% # attempts to use FU when none available |
| 707system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 708system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 695system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 696system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 709system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 710system.cpu0.iq.FU_type_0::IntAlu 430163495 68.41% 68.41% # Type of FU issued 711system.cpu0.iq.FU_type_0::IntMult 1578221 0.25% 68.66% # Type of FU issued 712system.cpu0.iq.FU_type_0::IntDiv 81407 0.01% 68.68% # Type of FU issued 713system.cpu0.iq.FU_type_0::FloatAdd 125 0.00% 68.68% # Type of FU issued 714system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.68% # Type of FU issued 715system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.68% # Type of FU issued 716system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.68% # Type of FU issued 717system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.68% # Type of FU issued 718system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.68% # Type of FU issued 719system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.68% # Type of FU issued 720system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.68% # Type of FU issued 721system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.68% # Type of FU issued 722system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.68% # Type of FU issued 723system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.68% # Type of FU issued 724system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.68% # Type of FU issued 725system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.68% # Type of FU issued 726system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.68% # Type of FU issued 727system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.68% # Type of FU issued 728system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.68% # Type of FU issued 729system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.68% # Type of FU issued 730system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.68% # Type of FU issued 731system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.68% # Type of FU issued 732system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.68% # Type of FU issued 733system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.68% # Type of FU issued 734system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.68% # Type of FU issued 735system.cpu0.iq.FU_type_0::SimdFloatMisc 78656 0.01% 68.69% # Type of FU issued 736system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued 737system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued 738system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued 739system.cpu0.iq.FU_type_0::MemRead 108646479 17.28% 85.97% # Type of FU issued 740system.cpu0.iq.FU_type_0::MemWrite 88225631 14.03% 100.00% # Type of FU issued | 697system.cpu0.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued 698system.cpu0.iq.FU_type_0::IntAlu 401971331 68.38% 68.38% # Type of FU issued 699system.cpu0.iq.FU_type_0::IntMult 1424969 0.24% 68.62% # Type of FU issued 700system.cpu0.iq.FU_type_0::IntDiv 76351 0.01% 68.64% # Type of FU issued 701system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.64% # Type of FU issued 702system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued 703system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued 704system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued 705system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued 706system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued 707system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued 708system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.64% # Type of FU issued 709system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued 710system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.64% # Type of FU issued 711system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued 712system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued 713system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued 714system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued 715system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued 716system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued 717system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued 718system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.64% # Type of FU issued 719system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued 720system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.64% # Type of FU issued 721system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.64% # Type of FU issued 722system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued 723system.cpu0.iq.FU_type_0::SimdFloatMisc 44028 0.01% 68.64% # Type of FU issued 724system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.64% # Type of FU issued 725system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.64% # Type of FU issued 726system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.64% # Type of FU issued 727system.cpu0.iq.FU_type_0::MemRead 101506921 17.27% 85.91% # Type of FU issued 728system.cpu0.iq.FU_type_0::MemWrite 82822965 14.09% 100.00% # Type of FU issued |
| 741system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 742system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 729system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 730system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 743system.cpu0.iq.FU_type_0::total 628774014 # Type of FU issued 744system.cpu0.iq.rate 0.798155 # Inst issue rate 745system.cpu0.iq.fu_busy_cnt 143205661 # FU busy when requested 746system.cpu0.iq.fu_busy_rate 0.227754 # FU busy rate (busy events/executed inst) 747system.cpu0.iq.int_inst_queue_reads 2167577171 # Number of integer instruction queue reads 748system.cpu0.iq.int_inst_queue_writes 695106277 # Number of integer instruction queue writes 749system.cpu0.iq.int_inst_queue_wakeup_accesses 611404783 # Number of integer instruction queue wakeup accesses 750system.cpu0.iq.fp_inst_queue_reads 1372966 # Number of floating instruction queue reads 751system.cpu0.iq.fp_inst_queue_writes 554126 # Number of floating instruction queue writes 752system.cpu0.iq.fp_inst_queue_wakeup_accesses 508083 # Number of floating instruction queue wakeup accesses 753system.cpu0.iq.int_alu_accesses 771129089 # Number of integer alu accesses 754system.cpu0.iq.fp_alu_accesses 850586 # Number of floating point alu accesses 755system.cpu0.iew.lsq.thread0.forwLoads 2930031 # Number of loads that had data forwarded from stores | 731system.cpu0.iq.FU_type_0::total 587846614 # Type of FU issued 732system.cpu0.iq.rate 0.806867 # Inst issue rate 733system.cpu0.iq.fu_busy_cnt 134946779 # FU busy when requested 734system.cpu0.iq.fu_busy_rate 0.229561 # FU busy rate (busy events/executed inst) 735system.cpu0.iq.int_inst_queue_reads 2018256641 # Number of integer instruction queue reads 736system.cpu0.iq.int_inst_queue_writes 650811943 # Number of integer instruction queue writes 737system.cpu0.iq.int_inst_queue_wakeup_accesses 571438682 # Number of integer instruction queue wakeup accesses 738system.cpu0.iq.fp_inst_queue_reads 1207660 # Number of floating instruction queue reads 739system.cpu0.iq.fp_inst_queue_writes 476069 # Number of floating instruction queue writes 740system.cpu0.iq.fp_inst_queue_wakeup_accesses 443638 # Number of floating instruction queue wakeup accesses 741system.cpu0.iq.int_alu_accesses 722040340 # Number of integer alu accesses 742system.cpu0.iq.fp_alu_accesses 753051 # Number of floating point alu accesses 743system.cpu0.iew.lsq.thread0.forwLoads 2688850 # Number of loads that had data forwarded from stores |
| 756system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 744system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 757system.cpu0.iew.lsq.thread0.squashedLoads 13213228 # Number of loads squashed 758system.cpu0.iew.lsq.thread0.ignoredResponses 17078 # Number of memory responses ignored because the instruction is squashed 759system.cpu0.iew.lsq.thread0.memOrderViolation 150900 # Number of memory ordering violations 760system.cpu0.iew.lsq.thread0.squashedStores 6091069 # Number of stores squashed | 745system.cpu0.iew.lsq.thread0.squashedLoads 12347690 # Number of loads squashed 746system.cpu0.iew.lsq.thread0.ignoredResponses 15246 # Number of memory responses ignored because the instruction is squashed 747system.cpu0.iew.lsq.thread0.memOrderViolation 139538 # Number of memory ordering violations 748system.cpu0.iew.lsq.thread0.squashedStores 5796061 # Number of stores squashed |
| 761system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 762system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 749system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 750system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 763system.cpu0.iew.lsq.thread0.rescheduledLoads 2819130 # Number of loads that were rescheduled 764system.cpu0.iew.lsq.thread0.cacheBlocked 4221569 # Number of times an access to memory failed due to the cache being blocked | 751system.cpu0.iew.lsq.thread0.rescheduledLoads 2638151 # Number of loads that were rescheduled 752system.cpu0.iew.lsq.thread0.cacheBlocked 4049170 # Number of times an access to memory failed due to the cache being blocked |
| 765system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 753system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 766system.cpu0.iew.iewSquashCycles 5457314 # Number of cycles IEW is squashing 767system.cpu0.iew.iewBlockCycles 7826815 # Number of cycles IEW is blocking 768system.cpu0.iew.iewUnblockCycles 3783393 # Number of cycles IEW is unblocking 769system.cpu0.iew.iewDispatchedInsts 641629807 # Number of instructions dispatched to IQ | 754system.cpu0.iew.iewSquashCycles 5179766 # Number of cycles IEW is squashing 755system.cpu0.iew.iewBlockCycles 6081153 # Number of cycles IEW is blocking 756system.cpu0.iew.iewUnblockCycles 2925805 # Number of cycles IEW is unblocking 757system.cpu0.iew.iewDispatchedInsts 599957845 # Number of instructions dispatched to IQ |
| 770system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 758system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 771system.cpu0.iew.iewDispLoadInsts 106280749 # Number of dispatched load instructions 772system.cpu0.iew.iewDispStoreInsts 90455195 # Number of dispatched store instructions 773system.cpu0.iew.iewDispNonSpecInsts 13677015 # Number of dispatched non-speculative instructions 774system.cpu0.iew.iewIQFullEvents 59030 # Number of times the IQ has become full, causing a stall 775system.cpu0.iew.iewLSQFullEvents 3651240 # Number of times the LSQ has become full, causing a stall 776system.cpu0.iew.memOrderViolationEvents 150900 # Number of memory order violations 777system.cpu0.iew.predictedTakenIncorrect 2214888 # Number of branches that were predicted taken incorrectly 778system.cpu0.iew.predictedNotTakenIncorrect 3025224 # Number of branches that were predicted not taken incorrectly 779system.cpu0.iew.branchMispredicts 5240112 # Number of branch mispredicts detected at execute 780system.cpu0.iew.iewExecutedInsts 620548589 # Number of executed instructions 781system.cpu0.iew.iewExecLoadInsts 105398618 # Number of load instructions executed 782system.cpu0.iew.iewExecSquashedInsts 7653008 # Number of squashed instructions skipped in execute | 759system.cpu0.iew.iewDispLoadInsts 99205558 # Number of dispatched load instructions 760system.cpu0.iew.iewDispStoreInsts 84922074 # Number of dispatched store instructions 761system.cpu0.iew.iewDispNonSpecInsts 12284210 # Number of dispatched non-speculative instructions 762system.cpu0.iew.iewIQFullEvents 51884 # Number of times the IQ has become full, causing a stall 763system.cpu0.iew.iewLSQFullEvents 2819346 # Number of times the LSQ has become full, causing a stall 764system.cpu0.iew.memOrderViolationEvents 139538 # Number of memory order violations 765system.cpu0.iew.predictedTakenIncorrect 2067264 # Number of branches that were predicted taken incorrectly 766system.cpu0.iew.predictedNotTakenIncorrect 2909526 # Number of branches that were predicted not taken incorrectly 767system.cpu0.iew.branchMispredicts 4976790 # Number of branch mispredicts detected at execute 768system.cpu0.iew.iewExecutedInsts 580052597 # Number of executed instructions 769system.cpu0.iew.iewExecLoadInsts 98485742 # Number of load instructions executed 770system.cpu0.iew.iewExecSquashedInsts 7283117 # Number of squashed instructions skipped in execute |
| 783system.cpu0.iew.exec_swp 0 # number of swp insts executed | 771system.cpu0.iew.exec_swp 0 # number of swp insts executed |
| 784system.cpu0.iew.exec_nop 125953 # number of nop insts executed 785system.cpu0.iew.exec_refs 192287971 # number of memory reference insts executed 786system.cpu0.iew.exec_branches 117275797 # Number of branches executed 787system.cpu0.iew.exec_stores 86889353 # Number of stores executed 788system.cpu0.iew.exec_rate 0.787714 # Inst execution rate 789system.cpu0.iew.wb_sent 612710943 # cumulative count of insts sent to commit 790system.cpu0.iew.wb_count 611912866 # cumulative count of insts written-back 791system.cpu0.iew.wb_producers 297952907 # num instructions producing a value 792system.cpu0.iew.wb_consumers 488842231 # num instructions consuming a value | 772system.cpu0.iew.exec_nop 115074 # number of nop insts executed 773system.cpu0.iew.exec_refs 180036231 # number of memory reference insts executed 774system.cpu0.iew.exec_branches 109604684 # Number of branches executed 775system.cpu0.iew.exec_stores 81550489 # Number of stores executed 776system.cpu0.iew.exec_rate 0.796169 # Inst execution rate 777system.cpu0.iew.wb_sent 572646335 # cumulative count of insts sent to commit 778system.cpu0.iew.wb_count 571882320 # cumulative count of insts written-back 779system.cpu0.iew.wb_producers 278067639 # num instructions producing a value 780system.cpu0.iew.wb_consumers 456095391 # num instructions consuming a value |
| 793system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 781system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 794system.cpu0.iew.wb_rate 0.776752 # insts written-back per cycle 795system.cpu0.iew.wb_fanout 0.609507 # average fanout of values written-back | 782system.cpu0.iew.wb_rate 0.784954 # insts written-back per cycle 783system.cpu0.iew.wb_fanout 0.609670 # average fanout of values written-back |
| 796system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 784system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 797system.cpu0.commit.commitSquashedInsts 50177444 # The number of squashed insts skipped by commit 798system.cpu0.commit.commitNonSpecStalls 15862501 # The number of times commit has been forced to stall to communicate backwards 799system.cpu0.commit.branchMispredicts 4903538 # The number of times a branch was mispredicted 800system.cpu0.commit.committed_per_cycle::samples 755787028 # Number of insts commited each cycle 801system.cpu0.commit.committed_per_cycle::mean 0.772749 # Number of insts commited each cycle 802system.cpu0.commit.committed_per_cycle::stdev 1.571704 # Number of insts commited each cycle | 785system.cpu0.commit.commitSquashedInsts 47584416 # The number of squashed insts skipped by commit 786system.cpu0.commit.commitNonSpecStalls 14243453 # The number of times commit has been forced to stall to communicate backwards 787system.cpu0.commit.branchMispredicts 4670064 # The number of times a branch was mispredicted 788system.cpu0.commit.committed_per_cycle::samples 697066716 # Number of insts commited each cycle 789system.cpu0.commit.committed_per_cycle::mean 0.782257 # Number of insts commited each cycle 790system.cpu0.commit.committed_per_cycle::stdev 1.580851 # Number of insts commited each cycle |
| 803system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 791system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 804system.cpu0.commit.committed_per_cycle::0 501065306 66.30% 66.30% # Number of insts commited each cycle 805system.cpu0.commit.committed_per_cycle::1 130810768 17.31% 83.61% # Number of insts commited each cycle 806system.cpu0.commit.committed_per_cycle::2 56911365 7.53% 91.14% # Number of insts commited each cycle 807system.cpu0.commit.committed_per_cycle::3 19253126 2.55% 93.68% # Number of insts commited each cycle 808system.cpu0.commit.committed_per_cycle::4 13929285 1.84% 95.53% # Number of insts commited each cycle 809system.cpu0.commit.committed_per_cycle::5 9339201 1.24% 96.76% # Number of insts commited each cycle 810system.cpu0.commit.committed_per_cycle::6 6281388 0.83% 97.59% # Number of insts commited each cycle 811system.cpu0.commit.committed_per_cycle::7 4033068 0.53% 98.13% # Number of insts commited each cycle 812system.cpu0.commit.committed_per_cycle::8 14163521 1.87% 100.00% # Number of insts commited each cycle | 792system.cpu0.commit.committed_per_cycle::0 460295975 66.03% 66.03% # Number of insts commited each cycle 793system.cpu0.commit.committed_per_cycle::1 120461861 17.28% 83.31% # Number of insts commited each cycle 794system.cpu0.commit.committed_per_cycle::2 53495228 7.67% 90.99% # Number of insts commited each cycle 795system.cpu0.commit.committed_per_cycle::3 18161397 2.61% 93.59% # Number of insts commited each cycle 796system.cpu0.commit.committed_per_cycle::4 13064824 1.87% 95.47% # Number of insts commited each cycle 797system.cpu0.commit.committed_per_cycle::5 8746806 1.25% 96.72% # Number of insts commited each cycle 798system.cpu0.commit.committed_per_cycle::6 5864289 0.84% 97.56% # Number of insts commited each cycle 799system.cpu0.commit.committed_per_cycle::7 3641188 0.52% 98.09% # Number of insts commited each cycle 800system.cpu0.commit.committed_per_cycle::8 13335148 1.91% 100.00% # Number of insts commited each cycle |
| 813system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 814system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 815system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 801system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 802system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 803system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 816system.cpu0.commit.committed_per_cycle::total 755787028 # Number of insts commited each cycle 817system.cpu0.commit.committedInsts 497564314 # Number of instructions committed 818system.cpu0.commit.committedOps 584033993 # Number of ops (including micro ops) committed | 804system.cpu0.commit.committed_per_cycle::total 697066716 # Number of insts commited each cycle 805system.cpu0.commit.committedInsts 464477894 # Number of instructions committed 806system.cpu0.commit.committedOps 545285068 # Number of ops (including micro ops) committed |
| 819system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed | 807system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed |
| 820system.cpu0.commit.refs 177431645 # Number of memory references committed 821system.cpu0.commit.loads 93067519 # Number of loads committed 822system.cpu0.commit.membars 3925399 # Number of memory barriers committed 823system.cpu0.commit.branches 111370146 # Number of branches committed 824system.cpu0.commit.fp_insts 496516 # Number of committed floating point instructions. 825system.cpu0.commit.int_insts 535821487 # Number of committed integer instructions. 826system.cpu0.commit.function_calls 14891305 # Number of function calls committed. | 808system.cpu0.commit.refs 165983876 # Number of memory references committed 809system.cpu0.commit.loads 86857868 # Number of loads committed 810system.cpu0.commit.membars 3594521 # Number of memory barriers committed 811system.cpu0.commit.branches 103961213 # Number of branches committed 812system.cpu0.commit.fp_insts 434735 # Number of committed floating point instructions. 813system.cpu0.commit.int_insts 500421802 # Number of committed integer instructions. 814system.cpu0.commit.function_calls 13758946 # Number of function calls committed. |
| 827system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 815system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 828system.cpu0.commit.op_class_0::IntAlu 405157799 69.37% 69.37% # Class of committed instruction 829system.cpu0.commit.op_class_0::IntMult 1311833 0.22% 69.60% # Class of committed instruction 830system.cpu0.commit.op_class_0::IntDiv 63039 0.01% 69.61% # Class of committed instruction 831system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction 832system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction 833system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction 834system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction 835system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction 836system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction 837system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction 838system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction 839system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction 840system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction 841system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction 842system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction 843system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction 844system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction 845system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction 846system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction 847system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction 848system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction 849system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction 850system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction 851system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction 852system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction 853system.cpu0.commit.op_class_0::SimdFloatMisc 69677 0.01% 69.62% # Class of committed instruction 854system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction 855system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction 856system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction 857system.cpu0.commit.op_class_0::MemRead 93067519 15.94% 85.55% # Class of committed instruction 858system.cpu0.commit.op_class_0::MemWrite 84364126 14.45% 100.00% # Class of committed instruction | 816system.cpu0.commit.op_class_0::IntAlu 378032624 69.33% 69.33% # Class of committed instruction 817system.cpu0.commit.op_class_0::IntMult 1169798 0.21% 69.54% # Class of committed instruction 818system.cpu0.commit.op_class_0::IntDiv 60419 0.01% 69.55% # Class of committed instruction 819system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.55% # Class of committed instruction 820system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.55% # Class of committed instruction 821system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.55% # Class of committed instruction 822system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.55% # Class of committed instruction 823system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.55% # Class of committed instruction 824system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.55% # Class of committed instruction 825system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.55% # Class of committed instruction 826system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.55% # Class of committed instruction 827system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.55% # Class of committed instruction 828system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.55% # Class of committed instruction 829system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.55% # Class of committed instruction 830system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.55% # Class of committed instruction 831system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.55% # Class of committed instruction 832system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.55% # Class of committed instruction 833system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.55% # Class of committed instruction 834system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.55% # Class of committed instruction 835system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.55% # Class of committed instruction 836system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.55% # Class of committed instruction 837system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.55% # Class of committed instruction 838system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.55% # Class of committed instruction 839system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.55% # Class of committed instruction 840system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.55% # Class of committed instruction 841system.cpu0.commit.op_class_0::SimdFloatMisc 38309 0.01% 69.56% # Class of committed instruction 842system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.56% # Class of committed instruction 843system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.56% # Class of committed instruction 844system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.56% # Class of committed instruction 845system.cpu0.commit.op_class_0::MemRead 86857868 15.93% 85.49% # Class of committed instruction 846system.cpu0.commit.op_class_0::MemWrite 79126008 14.51% 100.00% # Class of committed instruction |
| 859system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 860system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 847system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 848system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 861system.cpu0.commit.op_class_0::total 584033993 # Class of committed instruction 862system.cpu0.commit.bw_lim_events 14163521 # number cycles where commit BW limit reached | 849system.cpu0.commit.op_class_0::total 545285068 # Class of committed instruction 850system.cpu0.commit.bw_lim_events 13335148 # number cycles where commit BW limit reached |
| 863system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits | 851system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 864system.cpu0.rob.rob_reads 1371348086 # The number of ROB reads 865system.cpu0.rob.rob_writes 1277898548 # The number of ROB writes 866system.cpu0.timesIdled 1050969 # Number of times that the entire CPU went into an idle state and unscheduled itself 867system.cpu0.idleCycles 22484428 # Total number of cycles that the CPU has spent unscheduled due to idling 868system.cpu0.quiesceCycles 93902986117 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 869system.cpu0.committedInsts 497564314 # Number of Instructions Simulated 870system.cpu0.committedOps 584033993 # Number of Ops (including micro ops) Simulated 871system.cpu0.cpi 1.583282 # CPI: Cycles Per Instruction 872system.cpu0.cpi_total 1.583282 # CPI: Total CPI of All Threads 873system.cpu0.ipc 0.631600 # IPC: Instructions Per Cycle 874system.cpu0.ipc_total 0.631600 # IPC: Total IPC of All Threads 875system.cpu0.int_regfile_reads 732616408 # number of integer regfile reads 876system.cpu0.int_regfile_writes 435784003 # number of integer regfile writes 877system.cpu0.fp_regfile_reads 812591 # number of floating regfile reads 878system.cpu0.fp_regfile_writes 450624 # number of floating regfile writes 879system.cpu0.cc_regfile_reads 135724425 # number of cc regfile reads 880system.cpu0.cc_regfile_writes 136350840 # number of cc regfile writes 881system.cpu0.misc_regfile_reads 3048491910 # number of misc regfile reads 882system.cpu0.misc_regfile_writes 15942846 # number of misc regfile writes 883system.cpu0.dcache.tags.replacements 6332598 # number of replacements 884system.cpu0.dcache.tags.tagsinuse 484.098749 # Cycle average of tags in use 885system.cpu0.dcache.tags.total_refs 164710199 # Total number of references to valid blocks. 886system.cpu0.dcache.tags.sampled_refs 6333110 # Sample count of references to valid blocks. 887system.cpu0.dcache.tags.avg_refs 26.007791 # Average number of references to valid blocks. 888system.cpu0.dcache.tags.warmup_cycle 1750140500 # Cycle when the warmup percentage was hit. 889system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.098749 # Average occupied blocks per requestor 890system.cpu0.dcache.tags.occ_percent::cpu0.data 0.945505 # Average percentage of cache occupancy 891system.cpu0.dcache.tags.occ_percent::total 0.945505 # Average percentage of cache occupancy 892system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 893system.cpu0.dcache.tags.age_task_id_blocks_1024::0 275 # Occupied blocks per task id 894system.cpu0.dcache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id 895system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id 896system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 897system.cpu0.dcache.tags.tag_accesses 368140426 # Number of tag accesses 898system.cpu0.dcache.tags.data_accesses 368140426 # Number of data accesses 899system.cpu0.dcache.ReadReq_hits::cpu0.data 86285504 # number of ReadReq hits 900system.cpu0.dcache.ReadReq_hits::total 86285504 # number of ReadReq hits 901system.cpu0.dcache.WriteReq_hits::cpu0.data 73342402 # number of WriteReq hits 902system.cpu0.dcache.WriteReq_hits::total 73342402 # number of WriteReq hits 903system.cpu0.dcache.SoftPFReq_hits::cpu0.data 227851 # number of SoftPFReq hits 904system.cpu0.dcache.SoftPFReq_hits::total 227851 # number of SoftPFReq hits 905system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 264480 # number of WriteInvalidateReq hits 906system.cpu0.dcache.WriteInvalidateReq_hits::total 264480 # number of WriteInvalidateReq hits 907system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1878345 # number of LoadLockedReq hits 908system.cpu0.dcache.LoadLockedReq_hits::total 1878345 # number of LoadLockedReq hits 909system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1911240 # number of StoreCondReq hits 910system.cpu0.dcache.StoreCondReq_hits::total 1911240 # number of StoreCondReq hits 911system.cpu0.dcache.demand_hits::cpu0.data 159627906 # number of demand (read+write) hits 912system.cpu0.dcache.demand_hits::total 159627906 # number of demand (read+write) hits 913system.cpu0.dcache.overall_hits::cpu0.data 159855757 # number of overall hits 914system.cpu0.dcache.overall_hits::total 159855757 # number of overall hits 915system.cpu0.dcache.ReadReq_misses::cpu0.data 7088092 # number of ReadReq misses 916system.cpu0.dcache.ReadReq_misses::total 7088092 # number of ReadReq misses 917system.cpu0.dcache.WriteReq_misses::cpu0.data 7774496 # number of WriteReq misses 918system.cpu0.dcache.WriteReq_misses::total 7774496 # number of WriteReq misses 919system.cpu0.dcache.SoftPFReq_misses::cpu0.data 746133 # number of SoftPFReq misses 920system.cpu0.dcache.SoftPFReq_misses::total 746133 # number of SoftPFReq misses 921system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 842824 # number of WriteInvalidateReq misses 922system.cpu0.dcache.WriteInvalidateReq_misses::total 842824 # number of WriteInvalidateReq misses 923system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 281020 # number of LoadLockedReq misses 924system.cpu0.dcache.LoadLockedReq_misses::total 281020 # number of LoadLockedReq misses 925system.cpu0.dcache.StoreCondReq_misses::cpu0.data 209055 # number of StoreCondReq misses 926system.cpu0.dcache.StoreCondReq_misses::total 209055 # number of StoreCondReq misses 927system.cpu0.dcache.demand_misses::cpu0.data 14862588 # number of demand (read+write) misses 928system.cpu0.dcache.demand_misses::total 14862588 # number of demand (read+write) misses 929system.cpu0.dcache.overall_misses::cpu0.data 15608721 # number of overall misses 930system.cpu0.dcache.overall_misses::total 15608721 # number of overall misses 931system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 105859717159 # number of ReadReq miss cycles 932system.cpu0.dcache.ReadReq_miss_latency::total 105859717159 # number of ReadReq miss cycles 933system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 137077029934 # number of WriteReq miss cycles 934system.cpu0.dcache.WriteReq_miss_latency::total 137077029934 # number of WriteReq miss cycles 935system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 45622327717 # number of WriteInvalidateReq miss cycles 936system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 45622327717 # number of WriteInvalidateReq miss cycles 937system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4025426932 # number of LoadLockedReq miss cycles 938system.cpu0.dcache.LoadLockedReq_miss_latency::total 4025426932 # number of LoadLockedReq miss cycles 939system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4395434712 # number of StoreCondReq miss cycles 940system.cpu0.dcache.StoreCondReq_miss_latency::total 4395434712 # number of StoreCondReq miss cycles 941system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3232000 # number of StoreCondFailReq miss cycles 942system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3232000 # number of StoreCondFailReq miss cycles 943system.cpu0.dcache.demand_miss_latency::cpu0.data 242936747093 # number of demand (read+write) miss cycles 944system.cpu0.dcache.demand_miss_latency::total 242936747093 # number of demand (read+write) miss cycles 945system.cpu0.dcache.overall_miss_latency::cpu0.data 242936747093 # number of overall miss cycles 946system.cpu0.dcache.overall_miss_latency::total 242936747093 # number of overall miss cycles 947system.cpu0.dcache.ReadReq_accesses::cpu0.data 93373596 # number of ReadReq accesses(hits+misses) 948system.cpu0.dcache.ReadReq_accesses::total 93373596 # number of ReadReq accesses(hits+misses) 949system.cpu0.dcache.WriteReq_accesses::cpu0.data 81116898 # number of WriteReq accesses(hits+misses) 950system.cpu0.dcache.WriteReq_accesses::total 81116898 # number of WriteReq accesses(hits+misses) 951system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 973984 # number of SoftPFReq accesses(hits+misses) 952system.cpu0.dcache.SoftPFReq_accesses::total 973984 # number of SoftPFReq accesses(hits+misses) 953system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1107304 # number of WriteInvalidateReq accesses(hits+misses) 954system.cpu0.dcache.WriteInvalidateReq_accesses::total 1107304 # number of WriteInvalidateReq accesses(hits+misses) 955system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2159365 # number of LoadLockedReq accesses(hits+misses) 956system.cpu0.dcache.LoadLockedReq_accesses::total 2159365 # number of LoadLockedReq accesses(hits+misses) 957system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2120295 # number of StoreCondReq accesses(hits+misses) 958system.cpu0.dcache.StoreCondReq_accesses::total 2120295 # number of StoreCondReq accesses(hits+misses) 959system.cpu0.dcache.demand_accesses::cpu0.data 174490494 # number of demand (read+write) accesses 960system.cpu0.dcache.demand_accesses::total 174490494 # number of demand (read+write) accesses 961system.cpu0.dcache.overall_accesses::cpu0.data 175464478 # number of overall (read+write) accesses 962system.cpu0.dcache.overall_accesses::total 175464478 # number of overall (read+write) accesses 963system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075911 # miss rate for ReadReq accesses 964system.cpu0.dcache.ReadReq_miss_rate::total 0.075911 # miss rate for ReadReq accesses 965system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.095843 # miss rate for WriteReq accesses 966system.cpu0.dcache.WriteReq_miss_rate::total 0.095843 # miss rate for WriteReq accesses 967system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.766063 # miss rate for SoftPFReq accesses 968system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766063 # miss rate for SoftPFReq accesses 969system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.761150 # miss rate for WriteInvalidateReq accesses 970system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.761150 # miss rate for WriteInvalidateReq accesses 971system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.130140 # miss rate for LoadLockedReq accesses 972system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.130140 # miss rate for LoadLockedReq accesses 973system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098597 # miss rate for StoreCondReq accesses 974system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098597 # miss rate for StoreCondReq accesses 975system.cpu0.dcache.demand_miss_rate::cpu0.data 0.085177 # miss rate for demand accesses 976system.cpu0.dcache.demand_miss_rate::total 0.085177 # miss rate for demand accesses 977system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088957 # miss rate for overall accesses 978system.cpu0.dcache.overall_miss_rate::total 0.088957 # miss rate for overall accesses 979system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14934.867826 # average ReadReq miss latency 980system.cpu0.dcache.ReadReq_avg_miss_latency::total 14934.867826 # average ReadReq miss latency 981system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17631.629103 # average WriteReq miss latency 982system.cpu0.dcache.WriteReq_avg_miss_latency::total 17631.629103 # average WriteReq miss latency 983system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 54130.313941 # average WriteInvalidateReq miss latency 984system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 54130.313941 # average WriteInvalidateReq miss latency 985system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14324.343221 # average LoadLockedReq miss latency 986system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14324.343221 # average LoadLockedReq miss latency 987system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21025.255134 # average StoreCondReq miss latency 988system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21025.255134 # average StoreCondReq miss latency | 852system.cpu0.rob.rob_reads 1272468420 # The number of ROB reads 853system.cpu0.rob.rob_writes 1194722923 # The number of ROB writes 854system.cpu0.timesIdled 998377 # Number of times that the entire CPU went into an idle state and unscheduled itself 855system.cpu0.idleCycles 22469901 # Total number of cycles that the CPU has spent unscheduled due to idling 856system.cpu0.quiesceCycles 93882577668 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 857system.cpu0.committedInsts 464477894 # Number of Instructions Simulated 858system.cpu0.committedOps 545285068 # Number of Ops (including micro ops) Simulated 859system.cpu0.cpi 1.568546 # CPI: Cycles Per Instruction 860system.cpu0.cpi_total 1.568546 # CPI: Total CPI of All Threads 861system.cpu0.ipc 0.637533 # IPC: Instructions Per Cycle 862system.cpu0.ipc_total 0.637533 # IPC: Total IPC of All Threads 863system.cpu0.int_regfile_reads 684802624 # number of integer regfile reads 864system.cpu0.int_regfile_writes 407591789 # number of integer regfile writes 865system.cpu0.fp_regfile_reads 737398 # number of floating regfile reads 866system.cpu0.fp_regfile_writes 323628 # number of floating regfile writes 867system.cpu0.cc_regfile_reads 126081114 # number of cc regfile reads 868system.cpu0.cc_regfile_writes 126833812 # number of cc regfile writes 869system.cpu0.misc_regfile_reads 2842254449 # number of misc regfile reads 870system.cpu0.misc_regfile_writes 14406777 # number of misc regfile writes 871system.cpu0.dcache.tags.replacements 5807270 # number of replacements 872system.cpu0.dcache.tags.tagsinuse 503.185727 # Cycle average of tags in use 873system.cpu0.dcache.tags.total_refs 154700200 # Total number of references to valid blocks. 874system.cpu0.dcache.tags.sampled_refs 5807781 # Sample count of references to valid blocks. 875system.cpu0.dcache.tags.avg_refs 26.636714 # Average number of references to valid blocks. 876system.cpu0.dcache.tags.warmup_cycle 1931738500 # Cycle when the warmup percentage was hit. 877system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.185727 # Average occupied blocks per requestor 878system.cpu0.dcache.tags.occ_percent::cpu0.data 0.982785 # Average percentage of cache occupancy 879system.cpu0.dcache.tags.occ_percent::total 0.982785 # Average percentage of cache occupancy 880system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 881system.cpu0.dcache.tags.age_task_id_blocks_1024::0 291 # Occupied blocks per task id 882system.cpu0.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id 883system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id 884system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 885system.cpu0.dcache.tags.tag_accesses 344453115 # Number of tag accesses 886system.cpu0.dcache.tags.data_accesses 344453115 # Number of data accesses 887system.cpu0.dcache.ReadReq_hits::cpu0.data 80805507 # number of ReadReq hits 888system.cpu0.dcache.ReadReq_hits::total 80805507 # number of ReadReq hits 889system.cpu0.dcache.WriteReq_hits::cpu0.data 69071717 # number of WriteReq hits 890system.cpu0.dcache.WriteReq_hits::total 69071717 # number of WriteReq hits 891system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209524 # number of SoftPFReq hits 892system.cpu0.dcache.SoftPFReq_hits::total 209524 # number of SoftPFReq hits 893system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 255543 # number of WriteInvalidateReq hits 894system.cpu0.dcache.WriteInvalidateReq_hits::total 255543 # number of WriteInvalidateReq hits 895system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1772811 # number of LoadLockedReq hits 896system.cpu0.dcache.LoadLockedReq_hits::total 1772811 # number of LoadLockedReq hits 897system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1798532 # number of StoreCondReq hits 898system.cpu0.dcache.StoreCondReq_hits::total 1798532 # number of StoreCondReq hits 899system.cpu0.dcache.demand_hits::cpu0.data 149877224 # number of demand (read+write) hits 900system.cpu0.dcache.demand_hits::total 149877224 # number of demand (read+write) hits 901system.cpu0.dcache.overall_hits::cpu0.data 150086748 # number of overall hits 902system.cpu0.dcache.overall_hits::total 150086748 # number of overall hits 903system.cpu0.dcache.ReadReq_misses::cpu0.data 6456855 # number of ReadReq misses 904system.cpu0.dcache.ReadReq_misses::total 6456855 # number of ReadReq misses 905system.cpu0.dcache.WriteReq_misses::cpu0.data 6956516 # number of WriteReq misses 906system.cpu0.dcache.WriteReq_misses::total 6956516 # number of WriteReq misses 907system.cpu0.dcache.SoftPFReq_misses::cpu0.data 664764 # number of SoftPFReq misses 908system.cpu0.dcache.SoftPFReq_misses::total 664764 # number of SoftPFReq misses 909system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 829133 # number of WriteInvalidateReq misses 910system.cpu0.dcache.WriteInvalidateReq_misses::total 829133 # number of WriteInvalidateReq misses 911system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 256042 # number of LoadLockedReq misses 912system.cpu0.dcache.LoadLockedReq_misses::total 256042 # number of LoadLockedReq misses 913system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194087 # number of StoreCondReq misses 914system.cpu0.dcache.StoreCondReq_misses::total 194087 # number of StoreCondReq misses 915system.cpu0.dcache.demand_misses::cpu0.data 13413371 # number of demand (read+write) misses 916system.cpu0.dcache.demand_misses::total 13413371 # number of demand (read+write) misses 917system.cpu0.dcache.overall_misses::cpu0.data 14078135 # number of overall misses 918system.cpu0.dcache.overall_misses::total 14078135 # number of overall misses 919system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 92345367100 # number of ReadReq miss cycles 920system.cpu0.dcache.ReadReq_miss_latency::total 92345367100 # number of ReadReq miss cycles 921system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 122121346040 # number of WriteReq miss cycles 922system.cpu0.dcache.WriteReq_miss_latency::total 122121346040 # number of WriteReq miss cycles 923system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 37689944158 # number of WriteInvalidateReq miss cycles 924system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 37689944158 # number of WriteInvalidateReq miss cycles 925system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3513328512 # number of LoadLockedReq miss cycles 926system.cpu0.dcache.LoadLockedReq_miss_latency::total 3513328512 # number of LoadLockedReq miss cycles 927system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4123602814 # number of StoreCondReq miss cycles 928system.cpu0.dcache.StoreCondReq_miss_latency::total 4123602814 # number of StoreCondReq miss cycles 929system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5259500 # number of StoreCondFailReq miss cycles 930system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5259500 # number of StoreCondFailReq miss cycles 931system.cpu0.dcache.demand_miss_latency::cpu0.data 214466713140 # number of demand (read+write) miss cycles 932system.cpu0.dcache.demand_miss_latency::total 214466713140 # number of demand (read+write) miss cycles 933system.cpu0.dcache.overall_miss_latency::cpu0.data 214466713140 # number of overall miss cycles 934system.cpu0.dcache.overall_miss_latency::total 214466713140 # number of overall miss cycles 935system.cpu0.dcache.ReadReq_accesses::cpu0.data 87262362 # number of ReadReq accesses(hits+misses) 936system.cpu0.dcache.ReadReq_accesses::total 87262362 # number of ReadReq accesses(hits+misses) 937system.cpu0.dcache.WriteReq_accesses::cpu0.data 76028233 # number of WriteReq accesses(hits+misses) 938system.cpu0.dcache.WriteReq_accesses::total 76028233 # number of WriteReq accesses(hits+misses) 939system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 874288 # number of SoftPFReq accesses(hits+misses) 940system.cpu0.dcache.SoftPFReq_accesses::total 874288 # number of SoftPFReq accesses(hits+misses) 941system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1084676 # number of WriteInvalidateReq accesses(hits+misses) 942system.cpu0.dcache.WriteInvalidateReq_accesses::total 1084676 # number of WriteInvalidateReq accesses(hits+misses) 943system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2028853 # number of LoadLockedReq accesses(hits+misses) 944system.cpu0.dcache.LoadLockedReq_accesses::total 2028853 # number of LoadLockedReq accesses(hits+misses) 945system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1992619 # number of StoreCondReq accesses(hits+misses) 946system.cpu0.dcache.StoreCondReq_accesses::total 1992619 # number of StoreCondReq accesses(hits+misses) 947system.cpu0.dcache.demand_accesses::cpu0.data 163290595 # number of demand (read+write) accesses 948system.cpu0.dcache.demand_accesses::total 163290595 # number of demand (read+write) accesses 949system.cpu0.dcache.overall_accesses::cpu0.data 164164883 # number of overall (read+write) accesses 950system.cpu0.dcache.overall_accesses::total 164164883 # number of overall (read+write) accesses 951system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.073994 # miss rate for ReadReq accesses 952system.cpu0.dcache.ReadReq_miss_rate::total 0.073994 # miss rate for ReadReq accesses 953system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.091499 # miss rate for WriteReq accesses 954system.cpu0.dcache.WriteReq_miss_rate::total 0.091499 # miss rate for WriteReq accesses 955system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760349 # miss rate for SoftPFReq accesses 956system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760349 # miss rate for SoftPFReq accesses 957system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.764406 # miss rate for WriteInvalidateReq accesses 958system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.764406 # miss rate for WriteInvalidateReq accesses 959system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.126200 # miss rate for LoadLockedReq accesses 960system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.126200 # miss rate for LoadLockedReq accesses 961system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097403 # miss rate for StoreCondReq accesses 962system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097403 # miss rate for StoreCondReq accesses 963system.cpu0.dcache.demand_miss_rate::cpu0.data 0.082144 # miss rate for demand accesses 964system.cpu0.dcache.demand_miss_rate::total 0.082144 # miss rate for demand accesses 965system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085756 # miss rate for overall accesses 966system.cpu0.dcache.overall_miss_rate::total 0.085756 # miss rate for overall accesses 967system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14301.911240 # average ReadReq miss latency 968system.cpu0.dcache.ReadReq_avg_miss_latency::total 14301.911240 # average ReadReq miss latency 969system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17554.957976 # average WriteReq miss latency 970system.cpu0.dcache.WriteReq_avg_miss_latency::total 17554.957976 # average WriteReq miss latency 971system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 45457.054728 # average WriteInvalidateReq miss latency 972system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 45457.054728 # average WriteInvalidateReq miss latency 973system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13721.688286 # average LoadLockedReq miss latency 974system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13721.688286 # average LoadLockedReq miss latency 975system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21246.156693 # average StoreCondReq miss latency 976system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21246.156693 # average StoreCondReq miss latency |
| 989system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 990system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 977system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 978system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 991system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16345.521190 # average overall miss latency 992system.cpu0.dcache.demand_avg_miss_latency::total 16345.521190 # average overall miss latency 993system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15564.167435 # average overall miss latency 994system.cpu0.dcache.overall_avg_miss_latency::total 15564.167435 # average overall miss latency 995system.cpu0.dcache.blocked_cycles::no_mshrs 13488103 # number of cycles access was blocked 996system.cpu0.dcache.blocked_cycles::no_targets 19786702 # number of cycles access was blocked 997system.cpu0.dcache.blocked::no_mshrs 752105 # number of cycles access was blocked 998system.cpu0.dcache.blocked::no_targets 757651 # number of cycles access was blocked 999system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.933803 # average number of cycles each access was blocked 1000system.cpu0.dcache.avg_blocked_cycles::no_targets 26.115853 # average number of cycles each access was blocked | 979system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15989.024171 # average overall miss latency 980system.cpu0.dcache.demand_avg_miss_latency::total 15989.024171 # average overall miss latency 981system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15234.028736 # average overall miss latency 982system.cpu0.dcache.overall_avg_miss_latency::total 15234.028736 # average overall miss latency 983system.cpu0.dcache.blocked_cycles::no_mshrs 10974284 # number of cycles access was blocked 984system.cpu0.dcache.blocked_cycles::no_targets 17020056 # number of cycles access was blocked 985system.cpu0.dcache.blocked::no_mshrs 751732 # number of cycles access was blocked 986system.cpu0.dcache.blocked::no_targets 670987 # number of cycles access was blocked 987system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.598665 # average number of cycles each access was blocked 988system.cpu0.dcache.avg_blocked_cycles::no_targets 25.365702 # average number of cycles each access was blocked |
| 1001system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1002system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 989system.cpu0.dcache.fast_writes 0 # number of fast writes performed 990system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 1003system.cpu0.dcache.writebacks::writebacks 4276528 # number of writebacks 1004system.cpu0.dcache.writebacks::total 4276528 # number of writebacks 1005system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3664529 # number of ReadReq MSHR hits 1006system.cpu0.dcache.ReadReq_mshr_hits::total 3664529 # number of ReadReq MSHR hits 1007system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6233308 # number of WriteReq MSHR hits 1008system.cpu0.dcache.WriteReq_mshr_hits::total 6233308 # number of WriteReq MSHR hits 1009system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 4741 # number of WriteInvalidateReq MSHR hits 1010system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4741 # number of WriteInvalidateReq MSHR hits 1011system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 141328 # number of LoadLockedReq MSHR hits 1012system.cpu0.dcache.LoadLockedReq_mshr_hits::total 141328 # number of LoadLockedReq MSHR hits 1013system.cpu0.dcache.demand_mshr_hits::cpu0.data 9897837 # number of demand (read+write) MSHR hits 1014system.cpu0.dcache.demand_mshr_hits::total 9897837 # number of demand (read+write) MSHR hits 1015system.cpu0.dcache.overall_mshr_hits::cpu0.data 9897837 # number of overall MSHR hits 1016system.cpu0.dcache.overall_mshr_hits::total 9897837 # number of overall MSHR hits 1017system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3423563 # number of ReadReq MSHR misses 1018system.cpu0.dcache.ReadReq_mshr_misses::total 3423563 # number of ReadReq MSHR misses 1019system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1541188 # number of WriteReq MSHR misses 1020system.cpu0.dcache.WriteReq_mshr_misses::total 1541188 # number of WriteReq MSHR misses 1021system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 739665 # number of SoftPFReq MSHR misses 1022system.cpu0.dcache.SoftPFReq_mshr_misses::total 739665 # number of SoftPFReq MSHR misses 1023system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 838083 # number of WriteInvalidateReq MSHR misses 1024system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 838083 # number of WriteInvalidateReq MSHR misses 1025system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 139692 # number of LoadLockedReq MSHR misses 1026system.cpu0.dcache.LoadLockedReq_mshr_misses::total 139692 # number of LoadLockedReq MSHR misses 1027system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 209050 # number of StoreCondReq MSHR misses 1028system.cpu0.dcache.StoreCondReq_mshr_misses::total 209050 # number of StoreCondReq MSHR misses 1029system.cpu0.dcache.demand_mshr_misses::cpu0.data 4964751 # number of demand (read+write) MSHR misses 1030system.cpu0.dcache.demand_mshr_misses::total 4964751 # number of demand (read+write) MSHR misses 1031system.cpu0.dcache.overall_mshr_misses::cpu0.data 5704416 # number of overall MSHR misses 1032system.cpu0.dcache.overall_mshr_misses::total 5704416 # number of overall MSHR misses 1033system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44975748199 # number of ReadReq MSHR miss cycles 1034system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44975748199 # number of ReadReq MSHR miss cycles 1035system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 28501279892 # number of WriteReq MSHR miss cycles 1036system.cpu0.dcache.WriteReq_mshr_miss_latency::total 28501279892 # number of WriteReq MSHR miss cycles 1037system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16804666332 # number of SoftPFReq MSHR miss cycles 1038system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16804666332 # number of SoftPFReq MSHR miss cycles 1039system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 43773018566 # number of WriteInvalidateReq MSHR miss cycles 1040system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 43773018566 # number of WriteInvalidateReq MSHR miss cycles 1041system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1737566757 # number of LoadLockedReq MSHR miss cycles 1042system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1737566757 # number of LoadLockedReq MSHR miss cycles 1043system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3967184288 # number of StoreCondReq MSHR miss cycles 1044system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3967184288 # number of StoreCondReq MSHR miss cycles 1045system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3082000 # number of StoreCondFailReq MSHR miss cycles 1046system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3082000 # number of StoreCondFailReq MSHR miss cycles 1047system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 73477028091 # number of demand (read+write) MSHR miss cycles 1048system.cpu0.dcache.demand_mshr_miss_latency::total 73477028091 # number of demand (read+write) MSHR miss cycles 1049system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 90281694423 # number of overall MSHR miss cycles 1050system.cpu0.dcache.overall_mshr_miss_latency::total 90281694423 # number of overall MSHR miss cycles 1051system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5575976491 # number of ReadReq MSHR uncacheable cycles 1052system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5575976491 # number of ReadReq MSHR uncacheable cycles 1053system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5325987989 # number of WriteReq MSHR uncacheable cycles 1054system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5325987989 # number of WriteReq MSHR uncacheable cycles 1055system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10901964480 # number of overall MSHR uncacheable cycles 1056system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10901964480 # number of overall MSHR uncacheable cycles 1057system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036665 # mshr miss rate for ReadReq accesses 1058system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036665 # mshr miss rate for ReadReq accesses 1059system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019000 # mshr miss rate for WriteReq accesses 1060system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019000 # mshr miss rate for WriteReq accesses 1061system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759422 # mshr miss rate for SoftPFReq accesses 1062system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759422 # mshr miss rate for SoftPFReq accesses 1063system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.756868 # mshr miss rate for WriteInvalidateReq accesses 1064system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.756868 # mshr miss rate for WriteInvalidateReq accesses 1065system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064691 # mshr miss rate for LoadLockedReq accesses 1066system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064691 # mshr miss rate for LoadLockedReq accesses 1067system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098595 # mshr miss rate for StoreCondReq accesses 1068system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098595 # mshr miss rate for StoreCondReq accesses 1069system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028453 # mshr miss rate for demand accesses 1070system.cpu0.dcache.demand_mshr_miss_rate::total 0.028453 # mshr miss rate for demand accesses 1071system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032510 # mshr miss rate for overall accesses 1072system.cpu0.dcache.overall_mshr_miss_rate::total 0.032510 # mshr miss rate for overall accesses 1073system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13137.117149 # average ReadReq mshr miss latency 1074system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13137.117149 # average ReadReq mshr miss latency 1075system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18493.058531 # average WriteReq mshr miss latency 1076system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18493.058531 # average WriteReq mshr miss latency 1077system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22719.293642 # average SoftPFReq mshr miss latency 1078system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22719.293642 # average SoftPFReq mshr miss latency 1079system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 52229.932556 # average WriteInvalidateReq mshr miss latency 1080system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 52229.932556 # average WriteInvalidateReq mshr miss latency 1081system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12438.555945 # average LoadLockedReq mshr miss latency 1082system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12438.555945 # average LoadLockedReq mshr miss latency 1083system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18977.203004 # average StoreCondReq mshr miss latency 1084system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18977.203004 # average StoreCondReq mshr miss latency | 991system.cpu0.dcache.writebacks::writebacks 3967066 # number of writebacks 992system.cpu0.dcache.writebacks::total 3967066 # number of writebacks 993system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3312893 # number of ReadReq MSHR hits 994system.cpu0.dcache.ReadReq_mshr_hits::total 3312893 # number of ReadReq MSHR hits 995system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5560546 # number of WriteReq MSHR hits 996system.cpu0.dcache.WriteReq_mshr_hits::total 5560546 # number of WriteReq MSHR hits 997system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 4546 # number of WriteInvalidateReq MSHR hits 998system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4546 # number of WriteInvalidateReq MSHR hits 999system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 132684 # number of LoadLockedReq MSHR hits 1000system.cpu0.dcache.LoadLockedReq_mshr_hits::total 132684 # number of LoadLockedReq MSHR hits 1001system.cpu0.dcache.demand_mshr_hits::cpu0.data 8873439 # number of demand (read+write) MSHR hits 1002system.cpu0.dcache.demand_mshr_hits::total 8873439 # number of demand (read+write) MSHR hits 1003system.cpu0.dcache.overall_mshr_hits::cpu0.data 8873439 # number of overall MSHR hits 1004system.cpu0.dcache.overall_mshr_hits::total 8873439 # number of overall MSHR hits 1005system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3143962 # number of ReadReq MSHR misses 1006system.cpu0.dcache.ReadReq_mshr_misses::total 3143962 # number of ReadReq MSHR misses 1007system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1395970 # number of WriteReq MSHR misses 1008system.cpu0.dcache.WriteReq_mshr_misses::total 1395970 # number of WriteReq MSHR misses 1009system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 657971 # number of SoftPFReq MSHR misses 1010system.cpu0.dcache.SoftPFReq_mshr_misses::total 657971 # number of SoftPFReq MSHR misses 1011system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 824587 # number of WriteInvalidateReq MSHR misses 1012system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 824587 # number of WriteInvalidateReq MSHR misses 1013system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 123358 # number of LoadLockedReq MSHR misses 1014system.cpu0.dcache.LoadLockedReq_mshr_misses::total 123358 # number of LoadLockedReq MSHR misses 1015system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194072 # number of StoreCondReq MSHR misses 1016system.cpu0.dcache.StoreCondReq_mshr_misses::total 194072 # number of StoreCondReq MSHR misses 1017system.cpu0.dcache.demand_mshr_misses::cpu0.data 4539932 # number of demand (read+write) MSHR misses 1018system.cpu0.dcache.demand_mshr_misses::total 4539932 # number of demand (read+write) MSHR misses 1019system.cpu0.dcache.overall_mshr_misses::cpu0.data 5197903 # number of overall MSHR misses 1020system.cpu0.dcache.overall_mshr_misses::total 5197903 # number of overall MSHR misses 1021system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41375173894 # number of ReadReq MSHR miss cycles 1022system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41375173894 # number of ReadReq MSHR miss cycles 1023system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 26017592924 # number of WriteReq MSHR miss cycles 1024system.cpu0.dcache.WriteReq_mshr_miss_latency::total 26017592924 # number of WriteReq MSHR miss cycles 1025system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14556234769 # number of SoftPFReq MSHR miss cycles 1026system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14556234769 # number of SoftPFReq MSHR miss cycles 1027system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 36285250520 # number of WriteInvalidateReq MSHR miss cycles 1028system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 36285250520 # number of WriteInvalidateReq MSHR miss cycles 1029system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1556312588 # number of LoadLockedReq MSHR miss cycles 1030system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1556312588 # number of LoadLockedReq MSHR miss cycles 1031system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3823478686 # number of StoreCondReq MSHR miss cycles 1032system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3823478686 # number of StoreCondReq MSHR miss cycles 1033system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5096000 # number of StoreCondFailReq MSHR miss cycles 1034system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5096000 # number of StoreCondFailReq MSHR miss cycles 1035system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 67392766818 # number of demand (read+write) MSHR miss cycles 1036system.cpu0.dcache.demand_mshr_miss_latency::total 67392766818 # number of demand (read+write) MSHR miss cycles 1037system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 81949001587 # number of overall MSHR miss cycles 1038system.cpu0.dcache.overall_mshr_miss_latency::total 81949001587 # number of overall MSHR miss cycles 1039system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5745168998 # number of ReadReq MSHR uncacheable cycles 1040system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5745168998 # number of ReadReq MSHR uncacheable cycles 1041system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5504162016 # number of WriteReq MSHR uncacheable cycles 1042system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5504162016 # number of WriteReq MSHR uncacheable cycles 1043system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11249331014 # number of overall MSHR uncacheable cycles 1044system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11249331014 # number of overall MSHR uncacheable cycles 1045system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036029 # mshr miss rate for ReadReq accesses 1046system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036029 # mshr miss rate for ReadReq accesses 1047system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018361 # mshr miss rate for WriteReq accesses 1048system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018361 # mshr miss rate for WriteReq accesses 1049system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.752579 # mshr miss rate for SoftPFReq accesses 1050system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.752579 # mshr miss rate for SoftPFReq accesses 1051system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.760215 # mshr miss rate for WriteInvalidateReq accesses 1052system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.760215 # mshr miss rate for WriteInvalidateReq accesses 1053system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060802 # mshr miss rate for LoadLockedReq accesses 1054system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060802 # mshr miss rate for LoadLockedReq accesses 1055system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097395 # mshr miss rate for StoreCondReq accesses 1056system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097395 # mshr miss rate for StoreCondReq accesses 1057system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027803 # mshr miss rate for demand accesses 1058system.cpu0.dcache.demand_mshr_miss_rate::total 0.027803 # mshr miss rate for demand accesses 1059system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031663 # mshr miss rate for overall accesses 1060system.cpu0.dcache.overall_mshr_miss_rate::total 0.031663 # mshr miss rate for overall accesses 1061system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13160.201648 # average ReadReq mshr miss latency 1062system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13160.201648 # average ReadReq mshr miss latency 1063system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18637.644737 # average WriteReq mshr miss latency 1064system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18637.644737 # average WriteReq mshr miss latency 1065system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22122.912361 # average SoftPFReq mshr miss latency 1066system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22122.912361 # average SoftPFReq mshr miss latency 1067system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 44004.150587 # average WriteInvalidateReq mshr miss latency 1068system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 44004.150587 # average WriteInvalidateReq mshr miss latency 1069system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12616.227468 # average LoadLockedReq mshr miss latency 1070system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12616.227468 # average LoadLockedReq mshr miss latency 1071system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19701.341183 # average StoreCondReq mshr miss latency 1072system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19701.341183 # average StoreCondReq mshr miss latency |
| 1085system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1086system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1073system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1074system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1087system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14799.740831 # average overall mshr miss latency 1088system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14799.740831 # average overall mshr miss latency 1089system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15826.632283 # average overall mshr miss latency 1090system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15826.632283 # average overall mshr miss latency | 1075system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14844.444106 # average overall mshr miss latency 1076system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14844.444106 # average overall mshr miss latency 1077system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15765.781237 # average overall mshr miss latency 1078system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15765.781237 # average overall mshr miss latency |
| 1091system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1092system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1093system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1094system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1095system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1096system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1097system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1079system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1080system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1081system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1082system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1083system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1084system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1085system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1098system.cpu0.icache.tags.replacements 6368542 # number of replacements 1099system.cpu0.icache.tags.tagsinuse 511.961816 # Cycle average of tags in use 1100system.cpu0.icache.tags.total_refs 222275153 # Total number of references to valid blocks. 1101system.cpu0.icache.tags.sampled_refs 6369054 # Sample count of references to valid blocks. 1102system.cpu0.icache.tags.avg_refs 34.899241 # Average number of references to valid blocks. 1103system.cpu0.icache.tags.warmup_cycle 14184385750 # Cycle when the warmup percentage was hit. 1104system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.961816 # Average occupied blocks per requestor 1105system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999925 # Average percentage of cache occupancy 1106system.cpu0.icache.tags.occ_percent::total 0.999925 # Average percentage of cache occupancy | 1086system.cpu0.icache.tags.replacements 6071622 # number of replacements 1087system.cpu0.icache.tags.tagsinuse 511.960367 # Cycle average of tags in use 1088system.cpu0.icache.tags.total_refs 207290998 # Total number of references to valid blocks. 1089system.cpu0.icache.tags.sampled_refs 6072134 # Sample count of references to valid blocks. 1090system.cpu0.icache.tags.avg_refs 34.138080 # Average number of references to valid blocks. 1091system.cpu0.icache.tags.warmup_cycle 14063099250 # Cycle when the warmup percentage was hit. 1092system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960367 # Average occupied blocks per requestor 1093system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999923 # Average percentage of cache occupancy 1094system.cpu0.icache.tags.occ_percent::total 0.999923 # Average percentage of cache occupancy |
| 1107system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1095system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1108system.cpu0.icache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id 1109system.cpu0.icache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id 1110system.cpu0.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id | 1096system.cpu0.icache.tags.age_task_id_blocks_1024::0 329 # Occupied blocks per task id 1097system.cpu0.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id 1098system.cpu0.icache.tags.age_task_id_blocks_1024::2 92 # Occupied blocks per task id |
| 1111system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1099system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1112system.cpu0.icache.tags.tag_accesses 464315009 # Number of tag accesses 1113system.cpu0.icache.tags.data_accesses 464315009 # Number of data accesses 1114system.cpu0.icache.ReadReq_hits::cpu0.inst 222275153 # number of ReadReq hits 1115system.cpu0.icache.ReadReq_hits::total 222275153 # number of ReadReq hits 1116system.cpu0.icache.demand_hits::cpu0.inst 222275153 # number of demand (read+write) hits 1117system.cpu0.icache.demand_hits::total 222275153 # number of demand (read+write) hits 1118system.cpu0.icache.overall_hits::cpu0.inst 222275153 # number of overall hits 1119system.cpu0.icache.overall_hits::total 222275153 # number of overall hits 1120system.cpu0.icache.ReadReq_misses::cpu0.inst 6697664 # number of ReadReq misses 1121system.cpu0.icache.ReadReq_misses::total 6697664 # number of ReadReq misses 1122system.cpu0.icache.demand_misses::cpu0.inst 6697664 # number of demand (read+write) misses 1123system.cpu0.icache.demand_misses::total 6697664 # number of demand (read+write) misses 1124system.cpu0.icache.overall_misses::cpu0.inst 6697664 # number of overall misses 1125system.cpu0.icache.overall_misses::total 6697664 # number of overall misses 1126system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 70928372732 # number of ReadReq miss cycles 1127system.cpu0.icache.ReadReq_miss_latency::total 70928372732 # number of ReadReq miss cycles 1128system.cpu0.icache.demand_miss_latency::cpu0.inst 70928372732 # number of demand (read+write) miss cycles 1129system.cpu0.icache.demand_miss_latency::total 70928372732 # number of demand (read+write) miss cycles 1130system.cpu0.icache.overall_miss_latency::cpu0.inst 70928372732 # number of overall miss cycles 1131system.cpu0.icache.overall_miss_latency::total 70928372732 # number of overall miss cycles 1132system.cpu0.icache.ReadReq_accesses::cpu0.inst 228972817 # number of ReadReq accesses(hits+misses) 1133system.cpu0.icache.ReadReq_accesses::total 228972817 # number of ReadReq accesses(hits+misses) 1134system.cpu0.icache.demand_accesses::cpu0.inst 228972817 # number of demand (read+write) accesses 1135system.cpu0.icache.demand_accesses::total 228972817 # number of demand (read+write) accesses 1136system.cpu0.icache.overall_accesses::cpu0.inst 228972817 # number of overall (read+write) accesses 1137system.cpu0.icache.overall_accesses::total 228972817 # number of overall (read+write) accesses 1138system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029251 # miss rate for ReadReq accesses 1139system.cpu0.icache.ReadReq_miss_rate::total 0.029251 # miss rate for ReadReq accesses 1140system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029251 # miss rate for demand accesses 1141system.cpu0.icache.demand_miss_rate::total 0.029251 # miss rate for demand accesses 1142system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029251 # miss rate for overall accesses 1143system.cpu0.icache.overall_miss_rate::total 0.029251 # miss rate for overall accesses 1144system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10590.016569 # average ReadReq miss latency 1145system.cpu0.icache.ReadReq_avg_miss_latency::total 10590.016569 # average ReadReq miss latency 1146system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10590.016569 # average overall miss latency 1147system.cpu0.icache.demand_avg_miss_latency::total 10590.016569 # average overall miss latency 1148system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10590.016569 # average overall miss latency 1149system.cpu0.icache.overall_avg_miss_latency::total 10590.016569 # average overall miss latency 1150system.cpu0.icache.blocked_cycles::no_mshrs 8781241 # number of cycles access was blocked 1151system.cpu0.icache.blocked_cycles::no_targets 821 # number of cycles access was blocked 1152system.cpu0.icache.blocked::no_mshrs 708037 # number of cycles access was blocked 1153system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked 1154system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.402235 # average number of cycles each access was blocked 1155system.cpu0.icache.avg_blocked_cycles::no_targets 74.636364 # average number of cycles each access was blocked | 1100system.cpu0.icache.tags.tag_accesses 433467798 # Number of tag accesses 1101system.cpu0.icache.tags.data_accesses 433467798 # Number of data accesses 1102system.cpu0.icache.ReadReq_hits::cpu0.inst 207290998 # number of ReadReq hits 1103system.cpu0.icache.ReadReq_hits::total 207290998 # number of ReadReq hits 1104system.cpu0.icache.demand_hits::cpu0.inst 207290998 # number of demand (read+write) hits 1105system.cpu0.icache.demand_hits::total 207290998 # number of demand (read+write) hits 1106system.cpu0.icache.overall_hits::cpu0.inst 207290998 # number of overall hits 1107system.cpu0.icache.overall_hits::total 207290998 # number of overall hits 1108system.cpu0.icache.ReadReq_misses::cpu0.inst 6406823 # number of ReadReq misses 1109system.cpu0.icache.ReadReq_misses::total 6406823 # number of ReadReq misses 1110system.cpu0.icache.demand_misses::cpu0.inst 6406823 # number of demand (read+write) misses 1111system.cpu0.icache.demand_misses::total 6406823 # number of demand (read+write) misses 1112system.cpu0.icache.overall_misses::cpu0.inst 6406823 # number of overall misses 1113system.cpu0.icache.overall_misses::total 6406823 # number of overall misses 1114system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 67980327142 # number of ReadReq miss cycles 1115system.cpu0.icache.ReadReq_miss_latency::total 67980327142 # number of ReadReq miss cycles 1116system.cpu0.icache.demand_miss_latency::cpu0.inst 67980327142 # number of demand (read+write) miss cycles 1117system.cpu0.icache.demand_miss_latency::total 67980327142 # number of demand (read+write) miss cycles 1118system.cpu0.icache.overall_miss_latency::cpu0.inst 67980327142 # number of overall miss cycles 1119system.cpu0.icache.overall_miss_latency::total 67980327142 # number of overall miss cycles 1120system.cpu0.icache.ReadReq_accesses::cpu0.inst 213697821 # number of ReadReq accesses(hits+misses) 1121system.cpu0.icache.ReadReq_accesses::total 213697821 # number of ReadReq accesses(hits+misses) 1122system.cpu0.icache.demand_accesses::cpu0.inst 213697821 # number of demand (read+write) accesses 1123system.cpu0.icache.demand_accesses::total 213697821 # number of demand (read+write) accesses 1124system.cpu0.icache.overall_accesses::cpu0.inst 213697821 # number of overall (read+write) accesses 1125system.cpu0.icache.overall_accesses::total 213697821 # number of overall (read+write) accesses 1126system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029981 # miss rate for ReadReq accesses 1127system.cpu0.icache.ReadReq_miss_rate::total 0.029981 # miss rate for ReadReq accesses 1128system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029981 # miss rate for demand accesses 1129system.cpu0.icache.demand_miss_rate::total 0.029981 # miss rate for demand accesses 1130system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029981 # miss rate for overall accesses 1131system.cpu0.icache.overall_miss_rate::total 0.029981 # miss rate for overall accesses 1132system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10610.614206 # average ReadReq miss latency 1133system.cpu0.icache.ReadReq_avg_miss_latency::total 10610.614206 # average ReadReq miss latency 1134system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10610.614206 # average overall miss latency 1135system.cpu0.icache.demand_avg_miss_latency::total 10610.614206 # average overall miss latency 1136system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10610.614206 # average overall miss latency 1137system.cpu0.icache.overall_avg_miss_latency::total 10610.614206 # average overall miss latency 1138system.cpu0.icache.blocked_cycles::no_mshrs 9344678 # number of cycles access was blocked 1139system.cpu0.icache.blocked_cycles::no_targets 782 # number of cycles access was blocked 1140system.cpu0.icache.blocked::no_mshrs 720412 # number of cycles access was blocked 1141system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked 1142system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.971297 # average number of cycles each access was blocked 1143system.cpu0.icache.avg_blocked_cycles::no_targets 78.200000 # average number of cycles each access was blocked |
| 1156system.cpu0.icache.fast_writes 0 # number of fast writes performed 1157system.cpu0.icache.cache_copies 0 # number of cache copies performed | 1144system.cpu0.icache.fast_writes 0 # number of fast writes performed 1145system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 1158system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 328289 # number of ReadReq MSHR hits 1159system.cpu0.icache.ReadReq_mshr_hits::total 328289 # number of ReadReq MSHR hits 1160system.cpu0.icache.demand_mshr_hits::cpu0.inst 328289 # number of demand (read+write) MSHR hits 1161system.cpu0.icache.demand_mshr_hits::total 328289 # number of demand (read+write) MSHR hits 1162system.cpu0.icache.overall_mshr_hits::cpu0.inst 328289 # number of overall MSHR hits 1163system.cpu0.icache.overall_mshr_hits::total 328289 # number of overall MSHR hits 1164system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6369375 # number of ReadReq MSHR misses 1165system.cpu0.icache.ReadReq_mshr_misses::total 6369375 # number of ReadReq MSHR misses 1166system.cpu0.icache.demand_mshr_misses::cpu0.inst 6369375 # number of demand (read+write) MSHR misses 1167system.cpu0.icache.demand_mshr_misses::total 6369375 # number of demand (read+write) MSHR misses 1168system.cpu0.icache.overall_mshr_misses::cpu0.inst 6369375 # number of overall MSHR misses 1169system.cpu0.icache.overall_mshr_misses::total 6369375 # number of overall MSHR misses 1170system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 57966761800 # number of ReadReq MSHR miss cycles 1171system.cpu0.icache.ReadReq_mshr_miss_latency::total 57966761800 # number of ReadReq MSHR miss cycles 1172system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 57966761800 # number of demand (read+write) MSHR miss cycles 1173system.cpu0.icache.demand_mshr_miss_latency::total 57966761800 # number of demand (read+write) MSHR miss cycles 1174system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 57966761800 # number of overall MSHR miss cycles 1175system.cpu0.icache.overall_mshr_miss_latency::total 57966761800 # number of overall MSHR miss cycles 1176system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1699560248 # number of ReadReq MSHR uncacheable cycles 1177system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1699560248 # number of ReadReq MSHR uncacheable cycles 1178system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1699560248 # number of overall MSHR uncacheable cycles 1179system.cpu0.icache.overall_mshr_uncacheable_latency::total 1699560248 # number of overall MSHR uncacheable cycles 1180system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027817 # mshr miss rate for ReadReq accesses 1181system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027817 # mshr miss rate for ReadReq accesses 1182system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027817 # mshr miss rate for demand accesses 1183system.cpu0.icache.demand_mshr_miss_rate::total 0.027817 # mshr miss rate for demand accesses 1184system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027817 # mshr miss rate for overall accesses 1185system.cpu0.icache.overall_mshr_miss_rate::total 0.027817 # mshr miss rate for overall accesses 1186system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9100.855547 # average ReadReq mshr miss latency 1187system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9100.855547 # average ReadReq mshr miss latency 1188system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9100.855547 # average overall mshr miss latency 1189system.cpu0.icache.demand_avg_mshr_miss_latency::total 9100.855547 # average overall mshr miss latency 1190system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9100.855547 # average overall mshr miss latency 1191system.cpu0.icache.overall_avg_mshr_miss_latency::total 9100.855547 # average overall mshr miss latency | 1146system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 334667 # number of ReadReq MSHR hits 1147system.cpu0.icache.ReadReq_mshr_hits::total 334667 # number of ReadReq MSHR hits 1148system.cpu0.icache.demand_mshr_hits::cpu0.inst 334667 # number of demand (read+write) MSHR hits 1149system.cpu0.icache.demand_mshr_hits::total 334667 # number of demand (read+write) MSHR hits 1150system.cpu0.icache.overall_mshr_hits::cpu0.inst 334667 # number of overall MSHR hits 1151system.cpu0.icache.overall_mshr_hits::total 334667 # number of overall MSHR hits 1152system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6072156 # number of ReadReq MSHR misses 1153system.cpu0.icache.ReadReq_mshr_misses::total 6072156 # number of ReadReq MSHR misses 1154system.cpu0.icache.demand_mshr_misses::cpu0.inst 6072156 # number of demand (read+write) MSHR misses 1155system.cpu0.icache.demand_mshr_misses::total 6072156 # number of demand (read+write) MSHR misses 1156system.cpu0.icache.overall_mshr_misses::cpu0.inst 6072156 # number of overall MSHR misses 1157system.cpu0.icache.overall_mshr_misses::total 6072156 # number of overall MSHR misses 1158system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 58462486516 # number of ReadReq MSHR miss cycles 1159system.cpu0.icache.ReadReq_mshr_miss_latency::total 58462486516 # number of ReadReq MSHR miss cycles 1160system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 58462486516 # number of demand (read+write) MSHR miss cycles 1161system.cpu0.icache.demand_mshr_miss_latency::total 58462486516 # number of demand (read+write) MSHR miss cycles 1162system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 58462486516 # number of overall MSHR miss cycles 1163system.cpu0.icache.overall_mshr_miss_latency::total 58462486516 # number of overall MSHR miss cycles 1164system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1881164498 # number of ReadReq MSHR uncacheable cycles 1165system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1881164498 # number of ReadReq MSHR uncacheable cycles 1166system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1881164498 # number of overall MSHR uncacheable cycles 1167system.cpu0.icache.overall_mshr_uncacheable_latency::total 1881164498 # number of overall MSHR uncacheable cycles 1168system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028415 # mshr miss rate for ReadReq accesses 1169system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028415 # mshr miss rate for ReadReq accesses 1170system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028415 # mshr miss rate for demand accesses 1171system.cpu0.icache.demand_mshr_miss_rate::total 0.028415 # mshr miss rate for demand accesses 1172system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028415 # mshr miss rate for overall accesses 1173system.cpu0.icache.overall_mshr_miss_rate::total 0.028415 # mshr miss rate for overall accesses 1174system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9627.961883 # average ReadReq mshr miss latency 1175system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9627.961883 # average ReadReq mshr miss latency 1176system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9627.961883 # average overall mshr miss latency 1177system.cpu0.icache.demand_avg_mshr_miss_latency::total 9627.961883 # average overall mshr miss latency 1178system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9627.961883 # average overall mshr miss latency 1179system.cpu0.icache.overall_avg_mshr_miss_latency::total 9627.961883 # average overall mshr miss latency |
| 1192system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1193system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1194system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1195system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1196system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1180system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1181system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1182system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1183system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1184system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1197system.cpu0.l2cache.prefetcher.num_hwpf_issued 8232125 # number of hwpf issued 1198system.cpu0.l2cache.prefetcher.pfIdentified 8569505 # number of prefetch candidates identified 1199system.cpu0.l2cache.prefetcher.pfBufferHit 292099 # number of redundant prefetches already in prefetch queue | 1185system.cpu0.l2cache.prefetcher.num_hwpf_issued 7322641 # number of hwpf issued 1186system.cpu0.l2cache.prefetcher.pfIdentified 7635134 # number of prefetch candidates identified 1187system.cpu0.l2cache.prefetcher.pfBufferHit 270741 # number of redundant prefetches already in prefetch queue |
| 1200system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1201system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 1188system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1189system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 1202system.cpu0.l2cache.prefetcher.pfSpanPage 1116447 # number of prefetches not generated due to page crossing 1203system.cpu0.l2cache.tags.replacements 2928300 # number of replacements 1204system.cpu0.l2cache.tags.tagsinuse 16202.554411 # Cycle average of tags in use 1205system.cpu0.l2cache.tags.total_refs 13089790 # Total number of references to valid blocks. 1206system.cpu0.l2cache.tags.sampled_refs 2944355 # Sample count of references to valid blocks. 1207system.cpu0.l2cache.tags.avg_refs 4.445724 # Average number of references to valid blocks. 1208system.cpu0.l2cache.tags.warmup_cycle 2067342500 # Cycle when the warmup percentage was hit. 1209system.cpu0.l2cache.tags.occ_blocks::writebacks 7528.605833 # Average occupied blocks per requestor 1210system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 71.466332 # Average occupied blocks per requestor 1211system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 91.040507 # Average occupied blocks per requestor 1212system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3487.680197 # Average occupied blocks per requestor 1213system.cpu0.l2cache.tags.occ_blocks::cpu0.data 4098.714387 # Average occupied blocks per requestor 1214system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 925.047154 # Average occupied blocks per requestor 1215system.cpu0.l2cache.tags.occ_percent::writebacks 0.459510 # Average percentage of cache occupancy 1216system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004362 # Average percentage of cache occupancy 1217system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005557 # Average percentage of cache occupancy 1218system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.212871 # Average percentage of cache occupancy 1219system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.250166 # Average percentage of cache occupancy 1220system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056460 # Average percentage of cache occupancy 1221system.cpu0.l2cache.tags.occ_percent::total 0.988925 # Average percentage of cache occupancy 1222system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1513 # Occupied blocks per task id 1223system.cpu0.l2cache.tags.occ_task_id_blocks::1023 121 # Occupied blocks per task id 1224system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14421 # Occupied blocks per task id 1225system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 66 # Occupied blocks per task id 1226system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id 1227system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 709 # Occupied blocks per task id 1228system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 196 # Occupied blocks per task id 1229system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 537 # Occupied blocks per task id 1230system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 13 # Occupied blocks per task id 1231system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 70 # Occupied blocks per task id 1232system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id 1233system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id 1234system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id 1235system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 818 # Occupied blocks per task id 1236system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6042 # Occupied blocks per task id 1237system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2879 # Occupied blocks per task id 1238system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4513 # Occupied blocks per task id 1239system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.092346 # Percentage of cache occupancy per task id 1240system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.007385 # Percentage of cache occupancy per task id 1241system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.880188 # Percentage of cache occupancy per task id 1242system.cpu0.l2cache.tags.tag_accesses 298616625 # Number of tag accesses 1243system.cpu0.l2cache.tags.data_accesses 298616625 # Number of data accesses 1244system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 582155 # number of ReadReq hits 1245system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 182687 # number of ReadReq hits 1246system.cpu0.l2cache.ReadReq_hits::cpu0.inst 5666433 # number of ReadReq hits 1247system.cpu0.l2cache.ReadReq_hits::cpu0.data 3184946 # number of ReadReq hits 1248system.cpu0.l2cache.ReadReq_hits::total 9616221 # number of ReadReq hits 1249system.cpu0.l2cache.Writeback_hits::writebacks 4276521 # number of Writeback hits 1250system.cpu0.l2cache.Writeback_hits::total 4276521 # number of Writeback hits 1251system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 198743 # number of WriteInvalidateReq hits 1252system.cpu0.l2cache.WriteInvalidateReq_hits::total 198743 # number of WriteInvalidateReq hits 1253system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 114761 # number of UpgradeReq hits 1254system.cpu0.l2cache.UpgradeReq_hits::total 114761 # number of UpgradeReq hits 1255system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 36815 # number of SCUpgradeReq hits 1256system.cpu0.l2cache.SCUpgradeReq_hits::total 36815 # number of SCUpgradeReq hits 1257system.cpu0.l2cache.ReadExReq_hits::cpu0.data 991246 # number of ReadExReq hits 1258system.cpu0.l2cache.ReadExReq_hits::total 991246 # number of ReadExReq hits 1259system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 582155 # number of demand (read+write) hits 1260system.cpu0.l2cache.demand_hits::cpu0.itb.walker 182687 # number of demand (read+write) hits 1261system.cpu0.l2cache.demand_hits::cpu0.inst 5666433 # number of demand (read+write) hits 1262system.cpu0.l2cache.demand_hits::cpu0.data 4176192 # number of demand (read+write) hits 1263system.cpu0.l2cache.demand_hits::total 10607467 # number of demand (read+write) hits 1264system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 582155 # number of overall hits 1265system.cpu0.l2cache.overall_hits::cpu0.itb.walker 182687 # number of overall hits 1266system.cpu0.l2cache.overall_hits::cpu0.inst 5666433 # number of overall hits 1267system.cpu0.l2cache.overall_hits::cpu0.data 4176192 # number of overall hits 1268system.cpu0.l2cache.overall_hits::total 10607467 # number of overall hits 1269system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12607 # number of ReadReq misses 1270system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9261 # number of ReadReq misses 1271system.cpu0.l2cache.ReadReq_misses::cpu0.inst 702626 # number of ReadReq misses 1272system.cpu0.l2cache.ReadReq_misses::cpu0.data 1115482 # number of ReadReq misses 1273system.cpu0.l2cache.ReadReq_misses::total 1839976 # number of ReadReq misses 1274system.cpu0.l2cache.Writeback_misses::writebacks 4 # number of Writeback misses 1275system.cpu0.l2cache.Writeback_misses::total 4 # number of Writeback misses 1276system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 637762 # number of WriteInvalidateReq misses 1277system.cpu0.l2cache.WriteInvalidateReq_misses::total 637762 # number of WriteInvalidateReq misses 1278system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 138114 # number of UpgradeReq misses 1279system.cpu0.l2cache.UpgradeReq_misses::total 138114 # number of UpgradeReq misses 1280system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 172230 # number of SCUpgradeReq misses 1281system.cpu0.l2cache.SCUpgradeReq_misses::total 172230 # number of SCUpgradeReq misses 1282system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses 1283system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 1284system.cpu0.l2cache.ReadExReq_misses::cpu0.data 309290 # number of ReadExReq misses 1285system.cpu0.l2cache.ReadExReq_misses::total 309290 # number of ReadExReq misses 1286system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12607 # number of demand (read+write) misses 1287system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9261 # number of demand (read+write) misses 1288system.cpu0.l2cache.demand_misses::cpu0.inst 702626 # number of demand (read+write) misses 1289system.cpu0.l2cache.demand_misses::cpu0.data 1424772 # number of demand (read+write) misses 1290system.cpu0.l2cache.demand_misses::total 2149266 # number of demand (read+write) misses 1291system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12607 # number of overall misses 1292system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9261 # number of overall misses 1293system.cpu0.l2cache.overall_misses::cpu0.inst 702626 # number of overall misses 1294system.cpu0.l2cache.overall_misses::cpu0.data 1424772 # number of overall misses 1295system.cpu0.l2cache.overall_misses::total 2149266 # number of overall misses 1296system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 468497682 # number of ReadReq miss cycles 1297system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 383886915 # number of ReadReq miss cycles 1298system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 20661944862 # number of ReadReq miss cycles 1299system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 39743352793 # number of ReadReq miss cycles 1300system.cpu0.l2cache.ReadReq_miss_latency::total 61257682252 # number of ReadReq miss cycles 1301system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 212101792 # number of WriteInvalidateReq miss cycles 1302system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 212101792 # number of WriteInvalidateReq miss cycles 1303system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2828322980 # number of UpgradeReq miss cycles 1304system.cpu0.l2cache.UpgradeReq_miss_latency::total 2828322980 # number of UpgradeReq miss cycles 1305system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3448129857 # number of SCUpgradeReq miss cycles 1306system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3448129857 # number of SCUpgradeReq miss cycles 1307system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3007000 # number of SCUpgradeFailReq miss cycles 1308system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3007000 # number of SCUpgradeFailReq miss cycles 1309system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16311576734 # number of ReadExReq miss cycles 1310system.cpu0.l2cache.ReadExReq_miss_latency::total 16311576734 # number of ReadExReq miss cycles 1311system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 468497682 # number of demand (read+write) miss cycles 1312system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 383886915 # number of demand (read+write) miss cycles 1313system.cpu0.l2cache.demand_miss_latency::cpu0.inst 20661944862 # number of demand (read+write) miss cycles 1314system.cpu0.l2cache.demand_miss_latency::cpu0.data 56054929527 # number of demand (read+write) miss cycles 1315system.cpu0.l2cache.demand_miss_latency::total 77569258986 # number of demand (read+write) miss cycles 1316system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 468497682 # number of overall miss cycles 1317system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 383886915 # number of overall miss cycles 1318system.cpu0.l2cache.overall_miss_latency::cpu0.inst 20661944862 # number of overall miss cycles 1319system.cpu0.l2cache.overall_miss_latency::cpu0.data 56054929527 # number of overall miss cycles 1320system.cpu0.l2cache.overall_miss_latency::total 77569258986 # number of overall miss cycles 1321system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 594762 # number of ReadReq accesses(hits+misses) 1322system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 191948 # number of ReadReq accesses(hits+misses) 1323system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 6369059 # number of ReadReq accesses(hits+misses) 1324system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4300428 # number of ReadReq accesses(hits+misses) 1325system.cpu0.l2cache.ReadReq_accesses::total 11456197 # number of ReadReq accesses(hits+misses) 1326system.cpu0.l2cache.Writeback_accesses::writebacks 4276525 # number of Writeback accesses(hits+misses) 1327system.cpu0.l2cache.Writeback_accesses::total 4276525 # number of Writeback accesses(hits+misses) 1328system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 836505 # number of WriteInvalidateReq accesses(hits+misses) 1329system.cpu0.l2cache.WriteInvalidateReq_accesses::total 836505 # number of WriteInvalidateReq accesses(hits+misses) 1330system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 252875 # number of UpgradeReq accesses(hits+misses) 1331system.cpu0.l2cache.UpgradeReq_accesses::total 252875 # number of UpgradeReq accesses(hits+misses) 1332system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 209045 # number of SCUpgradeReq accesses(hits+misses) 1333system.cpu0.l2cache.SCUpgradeReq_accesses::total 209045 # number of SCUpgradeReq accesses(hits+misses) 1334system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 1335system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 1336system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1300536 # number of ReadExReq accesses(hits+misses) 1337system.cpu0.l2cache.ReadExReq_accesses::total 1300536 # number of ReadExReq accesses(hits+misses) 1338system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 594762 # number of demand (read+write) accesses 1339system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 191948 # number of demand (read+write) accesses 1340system.cpu0.l2cache.demand_accesses::cpu0.inst 6369059 # number of demand (read+write) accesses 1341system.cpu0.l2cache.demand_accesses::cpu0.data 5600964 # number of demand (read+write) accesses 1342system.cpu0.l2cache.demand_accesses::total 12756733 # number of demand (read+write) accesses 1343system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 594762 # number of overall (read+write) accesses 1344system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 191948 # number of overall (read+write) accesses 1345system.cpu0.l2cache.overall_accesses::cpu0.inst 6369059 # number of overall (read+write) accesses 1346system.cpu0.l2cache.overall_accesses::cpu0.data 5600964 # number of overall (read+write) accesses 1347system.cpu0.l2cache.overall_accesses::total 12756733 # number of overall (read+write) accesses 1348system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021197 # miss rate for ReadReq accesses 1349system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.048247 # miss rate for ReadReq accesses 1350system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.110319 # miss rate for ReadReq accesses 1351system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.259389 # miss rate for ReadReq accesses 1352system.cpu0.l2cache.ReadReq_miss_rate::total 0.160610 # miss rate for ReadReq accesses 1353system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000001 # miss rate for Writeback accesses 1354system.cpu0.l2cache.Writeback_miss_rate::total 0.000001 # miss rate for Writeback accesses 1355system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.762413 # miss rate for WriteInvalidateReq accesses 1356system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.762413 # miss rate for WriteInvalidateReq accesses 1357system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.546175 # miss rate for UpgradeReq accesses 1358system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.546175 # miss rate for UpgradeReq accesses 1359system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.823890 # miss rate for SCUpgradeReq accesses 1360system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.823890 # miss rate for SCUpgradeReq accesses | 1190system.cpu0.l2cache.prefetcher.pfSpanPage 993362 # number of prefetches not generated due to page crossing 1191system.cpu0.l2cache.tags.replacements 2579397 # number of replacements 1192system.cpu0.l2cache.tags.tagsinuse 16158.447303 # Cycle average of tags in use 1193system.cpu0.l2cache.tags.total_refs 12271567 # Total number of references to valid blocks. 1194system.cpu0.l2cache.tags.sampled_refs 2594941 # Sample count of references to valid blocks. 1195system.cpu0.l2cache.tags.avg_refs 4.729035 # Average number of references to valid blocks. 1196system.cpu0.l2cache.tags.warmup_cycle 2266482500 # Cycle when the warmup percentage was hit. 1197system.cpu0.l2cache.tags.occ_blocks::writebacks 5660.592746 # Average occupied blocks per requestor 1198system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 40.404376 # Average occupied blocks per requestor 1199system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 30.912164 # Average occupied blocks per requestor 1200system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5710.050306 # Average occupied blocks per requestor 1201system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3705.001610 # Average occupied blocks per requestor 1202system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1011.486101 # Average occupied blocks per requestor 1203system.cpu0.l2cache.tags.occ_percent::writebacks 0.345495 # Average percentage of cache occupancy 1204system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002466 # Average percentage of cache occupancy 1205system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001887 # Average percentage of cache occupancy 1206system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.348514 # Average percentage of cache occupancy 1207system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.226135 # Average percentage of cache occupancy 1208system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.061736 # Average percentage of cache occupancy 1209system.cpu0.l2cache.tags.occ_percent::total 0.986233 # Average percentage of cache occupancy 1210system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1380 # Occupied blocks per task id 1211system.cpu0.l2cache.tags.occ_task_id_blocks::1023 93 # Occupied blocks per task id 1212system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14071 # Occupied blocks per task id 1213system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 3 # Occupied blocks per task id 1214system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 72 # Occupied blocks per task id 1215system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 271 # Occupied blocks per task id 1216system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 414 # Occupied blocks per task id 1217system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 620 # Occupied blocks per task id 1218system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 1219system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id 1220system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 63 # Occupied blocks per task id 1221system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id 1222system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id 1223system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id 1224system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 688 # Occupied blocks per task id 1225system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5473 # Occupied blocks per task id 1226system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2257 # Occupied blocks per task id 1227system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5451 # Occupied blocks per task id 1228system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.084229 # Percentage of cache occupancy per task id 1229system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005676 # Percentage of cache occupancy per task id 1230system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.858826 # Percentage of cache occupancy per task id 1231system.cpu0.l2cache.tags.tag_accesses 277998240 # Number of tag accesses 1232system.cpu0.l2cache.tags.data_accesses 277998240 # Number of data accesses 1233system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 501930 # number of ReadReq hits 1234system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 167379 # number of ReadReq hits 1235system.cpu0.l2cache.ReadReq_hits::cpu0.inst 5436143 # number of ReadReq hits 1236system.cpu0.l2cache.ReadReq_hits::cpu0.data 2922103 # number of ReadReq hits 1237system.cpu0.l2cache.ReadReq_hits::total 9027555 # number of ReadReq hits 1238system.cpu0.l2cache.Writeback_hits::writebacks 3967054 # number of Writeback hits 1239system.cpu0.l2cache.Writeback_hits::total 3967054 # number of Writeback hits 1240system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 228126 # number of WriteInvalidateReq hits 1241system.cpu0.l2cache.WriteInvalidateReq_hits::total 228126 # number of WriteInvalidateReq hits 1242system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 108640 # number of UpgradeReq hits 1243system.cpu0.l2cache.UpgradeReq_hits::total 108640 # number of UpgradeReq hits 1244system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 33975 # number of SCUpgradeReq hits 1245system.cpu0.l2cache.SCUpgradeReq_hits::total 33975 # number of SCUpgradeReq hits 1246system.cpu0.l2cache.ReadExReq_hits::cpu0.data 890755 # number of ReadExReq hits 1247system.cpu0.l2cache.ReadExReq_hits::total 890755 # number of ReadExReq hits 1248system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 501930 # number of demand (read+write) hits 1249system.cpu0.l2cache.demand_hits::cpu0.itb.walker 167379 # number of demand (read+write) hits 1250system.cpu0.l2cache.demand_hits::cpu0.inst 5436143 # number of demand (read+write) hits 1251system.cpu0.l2cache.demand_hits::cpu0.data 3812858 # number of demand (read+write) hits 1252system.cpu0.l2cache.demand_hits::total 9918310 # number of demand (read+write) hits 1253system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 501930 # number of overall hits 1254system.cpu0.l2cache.overall_hits::cpu0.itb.walker 167379 # number of overall hits 1255system.cpu0.l2cache.overall_hits::cpu0.inst 5436143 # number of overall hits 1256system.cpu0.l2cache.overall_hits::cpu0.data 3812858 # number of overall hits 1257system.cpu0.l2cache.overall_hits::total 9918310 # number of overall hits 1258system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10652 # number of ReadReq misses 1259system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8152 # number of ReadReq misses 1260system.cpu0.l2cache.ReadReq_misses::cpu0.inst 635995 # number of ReadReq misses 1261system.cpu0.l2cache.ReadReq_misses::cpu0.data 1000489 # number of ReadReq misses 1262system.cpu0.l2cache.ReadReq_misses::total 1655288 # number of ReadReq misses 1263system.cpu0.l2cache.Writeback_misses::writebacks 10 # number of Writeback misses 1264system.cpu0.l2cache.Writeback_misses::total 10 # number of Writeback misses 1265system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 594866 # number of WriteInvalidateReq misses 1266system.cpu0.l2cache.WriteInvalidateReq_misses::total 594866 # number of WriteInvalidateReq misses 1267system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 133117 # number of UpgradeReq misses 1268system.cpu0.l2cache.UpgradeReq_misses::total 133117 # number of UpgradeReq misses 1269system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 160078 # number of SCUpgradeReq misses 1270system.cpu0.l2cache.SCUpgradeReq_misses::total 160078 # number of SCUpgradeReq misses 1271system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 19 # number of SCUpgradeFailReq misses 1272system.cpu0.l2cache.SCUpgradeFailReq_misses::total 19 # number of SCUpgradeFailReq misses 1273system.cpu0.l2cache.ReadExReq_misses::cpu0.data 274591 # number of ReadExReq misses 1274system.cpu0.l2cache.ReadExReq_misses::total 274591 # number of ReadExReq misses 1275system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10652 # number of demand (read+write) misses 1276system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8152 # number of demand (read+write) misses 1277system.cpu0.l2cache.demand_misses::cpu0.inst 635995 # number of demand (read+write) misses 1278system.cpu0.l2cache.demand_misses::cpu0.data 1275080 # number of demand (read+write) misses 1279system.cpu0.l2cache.demand_misses::total 1929879 # number of demand (read+write) misses 1280system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10652 # number of overall misses 1281system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8152 # number of overall misses 1282system.cpu0.l2cache.overall_misses::cpu0.inst 635995 # number of overall misses 1283system.cpu0.l2cache.overall_misses::cpu0.data 1275080 # number of overall misses 1284system.cpu0.l2cache.overall_misses::total 1929879 # number of overall misses 1285system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 338313980 # number of ReadReq miss cycles 1286system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 267505335 # number of ReadReq miss cycles 1287system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 19973277607 # number of ReadReq miss cycles 1288system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 34240699717 # number of ReadReq miss cycles 1289system.cpu0.l2cache.ReadReq_miss_latency::total 54819796639 # number of ReadReq miss cycles 1290system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 238254135 # number of WriteInvalidateReq miss cycles 1291system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 238254135 # number of WriteInvalidateReq miss cycles 1292system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2940744545 # number of UpgradeReq miss cycles 1293system.cpu0.l2cache.UpgradeReq_miss_latency::total 2940744545 # number of UpgradeReq miss cycles 1294system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3318665043 # number of SCUpgradeReq miss cycles 1295system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3318665043 # number of SCUpgradeReq miss cycles 1296system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4985998 # number of SCUpgradeFailReq miss cycles 1297system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4985998 # number of SCUpgradeFailReq miss cycles 1298system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 14040093164 # number of ReadExReq miss cycles 1299system.cpu0.l2cache.ReadExReq_miss_latency::total 14040093164 # number of ReadExReq miss cycles 1300system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 338313980 # number of demand (read+write) miss cycles 1301system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 267505335 # number of demand (read+write) miss cycles 1302system.cpu0.l2cache.demand_miss_latency::cpu0.inst 19973277607 # number of demand (read+write) miss cycles 1303system.cpu0.l2cache.demand_miss_latency::cpu0.data 48280792881 # number of demand (read+write) miss cycles 1304system.cpu0.l2cache.demand_miss_latency::total 68859889803 # number of demand (read+write) miss cycles 1305system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 338313980 # number of overall miss cycles 1306system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 267505335 # number of overall miss cycles 1307system.cpu0.l2cache.overall_miss_latency::cpu0.inst 19973277607 # number of overall miss cycles 1308system.cpu0.l2cache.overall_miss_latency::cpu0.data 48280792881 # number of overall miss cycles 1309system.cpu0.l2cache.overall_miss_latency::total 68859889803 # number of overall miss cycles 1310system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 512582 # number of ReadReq accesses(hits+misses) 1311system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 175531 # number of ReadReq accesses(hits+misses) 1312system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 6072138 # number of ReadReq accesses(hits+misses) 1313system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3922592 # number of ReadReq accesses(hits+misses) 1314system.cpu0.l2cache.ReadReq_accesses::total 10682843 # number of ReadReq accesses(hits+misses) 1315system.cpu0.l2cache.Writeback_accesses::writebacks 3967064 # number of Writeback accesses(hits+misses) 1316system.cpu0.l2cache.Writeback_accesses::total 3967064 # number of Writeback accesses(hits+misses) 1317system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 822992 # number of WriteInvalidateReq accesses(hits+misses) 1318system.cpu0.l2cache.WriteInvalidateReq_accesses::total 822992 # number of WriteInvalidateReq accesses(hits+misses) 1319system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 241757 # number of UpgradeReq accesses(hits+misses) 1320system.cpu0.l2cache.UpgradeReq_accesses::total 241757 # number of UpgradeReq accesses(hits+misses) 1321system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 194053 # number of SCUpgradeReq accesses(hits+misses) 1322system.cpu0.l2cache.SCUpgradeReq_accesses::total 194053 # number of SCUpgradeReq accesses(hits+misses) 1323system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 19 # number of SCUpgradeFailReq accesses(hits+misses) 1324system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 19 # number of SCUpgradeFailReq accesses(hits+misses) 1325system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1165346 # number of ReadExReq accesses(hits+misses) 1326system.cpu0.l2cache.ReadExReq_accesses::total 1165346 # number of ReadExReq accesses(hits+misses) 1327system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 512582 # number of demand (read+write) accesses 1328system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 175531 # number of demand (read+write) accesses 1329system.cpu0.l2cache.demand_accesses::cpu0.inst 6072138 # number of demand (read+write) accesses 1330system.cpu0.l2cache.demand_accesses::cpu0.data 5087938 # number of demand (read+write) accesses 1331system.cpu0.l2cache.demand_accesses::total 11848189 # number of demand (read+write) accesses 1332system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 512582 # number of overall (read+write) accesses 1333system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 175531 # number of overall (read+write) accesses 1334system.cpu0.l2cache.overall_accesses::cpu0.inst 6072138 # number of overall (read+write) accesses 1335system.cpu0.l2cache.overall_accesses::cpu0.data 5087938 # number of overall (read+write) accesses 1336system.cpu0.l2cache.overall_accesses::total 11848189 # number of overall (read+write) accesses 1337system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020781 # miss rate for ReadReq accesses 1338system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.046442 # miss rate for ReadReq accesses 1339system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.104740 # miss rate for ReadReq accesses 1340system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.255058 # miss rate for ReadReq accesses 1341system.cpu0.l2cache.ReadReq_miss_rate::total 0.154948 # miss rate for ReadReq accesses 1342system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000003 # miss rate for Writeback accesses 1343system.cpu0.l2cache.Writeback_miss_rate::total 0.000003 # miss rate for Writeback accesses 1344system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.722809 # miss rate for WriteInvalidateReq accesses 1345system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.722809 # miss rate for WriteInvalidateReq accesses 1346system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.550623 # miss rate for UpgradeReq accesses 1347system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.550623 # miss rate for UpgradeReq accesses 1348system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.824919 # miss rate for SCUpgradeReq accesses 1349system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.824919 # miss rate for SCUpgradeReq accesses |
| 1361system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1362system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 1350system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1351system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 1363system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.237817 # miss rate for ReadExReq accesses 1364system.cpu0.l2cache.ReadExReq_miss_rate::total 0.237817 # miss rate for ReadExReq accesses 1365system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021197 # miss rate for demand accesses 1366system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.048247 # miss rate for demand accesses 1367system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.110319 # miss rate for demand accesses 1368system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.254380 # miss rate for demand accesses 1369system.cpu0.l2cache.demand_miss_rate::total 0.168481 # miss rate for demand accesses 1370system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021197 # miss rate for overall accesses 1371system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.048247 # miss rate for overall accesses 1372system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.110319 # miss rate for overall accesses 1373system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.254380 # miss rate for overall accesses 1374system.cpu0.l2cache.overall_miss_rate::total 0.168481 # miss rate for overall accesses 1375system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 37161.710320 # average ReadReq miss latency 1376system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41451.993845 # average ReadReq miss latency 1377system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 29406.746779 # average ReadReq miss latency 1378system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 35628.860701 # average ReadReq miss latency 1379system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33292.652867 # average ReadReq miss latency 1380system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 332.572013 # average WriteInvalidateReq miss latency 1381system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 332.572013 # average WriteInvalidateReq miss latency 1382system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 20478.177303 # average UpgradeReq miss latency 1383system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 20478.177303 # average UpgradeReq miss latency 1384system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20020.495018 # average SCUpgradeReq miss latency 1385system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20020.495018 # average SCUpgradeReq miss latency 1386system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 601400 # average SCUpgradeFailReq miss latency 1387system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 601400 # average SCUpgradeFailReq miss latency 1388system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 52738.778279 # average ReadExReq miss latency 1389system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 52738.778279 # average ReadExReq miss latency 1390system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 37161.710320 # average overall miss latency 1391system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41451.993845 # average overall miss latency 1392system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29406.746779 # average overall miss latency 1393system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 39343.087545 # average overall miss latency 1394system.cpu0.l2cache.demand_avg_miss_latency::total 36091.046425 # average overall miss latency 1395system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 37161.710320 # average overall miss latency 1396system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41451.993845 # average overall miss latency 1397system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29406.746779 # average overall miss latency 1398system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 39343.087545 # average overall miss latency 1399system.cpu0.l2cache.overall_avg_miss_latency::total 36091.046425 # average overall miss latency 1400system.cpu0.l2cache.blocked_cycles::no_mshrs 272 # number of cycles access was blocked | 1352system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.235630 # miss rate for ReadExReq accesses 1353system.cpu0.l2cache.ReadExReq_miss_rate::total 0.235630 # miss rate for ReadExReq accesses 1354system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020781 # miss rate for demand accesses 1355system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.046442 # miss rate for demand accesses 1356system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.104740 # miss rate for demand accesses 1357system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.250608 # miss rate for demand accesses 1358system.cpu0.l2cache.demand_miss_rate::total 0.162884 # miss rate for demand accesses 1359system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020781 # miss rate for overall accesses 1360system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.046442 # miss rate for overall accesses 1361system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.104740 # miss rate for overall accesses 1362system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.250608 # miss rate for overall accesses 1363system.cpu0.l2cache.overall_miss_rate::total 0.162884 # miss rate for overall accesses 1364system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 31760.606459 # average ReadReq miss latency 1365system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 32814.687807 # average ReadReq miss latency 1366system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 31404.771432 # average ReadReq miss latency 1367system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 34223.964199 # average ReadReq miss latency 1368system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33117.981064 # average ReadReq miss latency 1369system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 400.517318 # average WriteInvalidateReq miss latency 1370system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 400.517318 # average WriteInvalidateReq miss latency 1371system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22091.427429 # average UpgradeReq miss latency 1372system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22091.427429 # average UpgradeReq miss latency 1373system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20731.549888 # average SCUpgradeReq miss latency 1374system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20731.549888 # average SCUpgradeReq miss latency 1375system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 262420.947368 # average SCUpgradeFailReq miss latency 1376system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 262420.947368 # average SCUpgradeFailReq miss latency 1377system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 51130.929870 # average ReadExReq miss latency 1378system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 51130.929870 # average ReadExReq miss latency 1379system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 31760.606459 # average overall miss latency 1380system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 32814.687807 # average overall miss latency 1381system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31404.771432 # average overall miss latency 1382system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37864.912696 # average overall miss latency 1383system.cpu0.l2cache.demand_avg_miss_latency::total 35680.936371 # average overall miss latency 1384system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 31760.606459 # average overall miss latency 1385system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 32814.687807 # average overall miss latency 1386system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31404.771432 # average overall miss latency 1387system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37864.912696 # average overall miss latency 1388system.cpu0.l2cache.overall_avg_miss_latency::total 35680.936371 # average overall miss latency 1389system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 1401system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1390system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1402system.cpu0.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked | 1391system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 1403system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1392system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1404system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 38.857143 # average number of cycles each access was blocked | 1393system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 1405system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1406system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1407system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 1394system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1395system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1396system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 1408system.cpu0.l2cache.writebacks::writebacks 1592666 # number of writebacks 1409system.cpu0.l2cache.writebacks::total 1592666 # number of writebacks 1410system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 3 # number of ReadReq MSHR hits 1411system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 178 # number of ReadReq MSHR hits 1412system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits 1413system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 5842 # number of ReadReq MSHR hits 1414system.cpu0.l2cache.ReadReq_mshr_hits::total 6026 # number of ReadReq MSHR hits 1415system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 65 # number of WriteInvalidateReq MSHR hits 1416system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 65 # number of WriteInvalidateReq MSHR hits 1417system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 39394 # number of ReadExReq MSHR hits 1418system.cpu0.l2cache.ReadExReq_mshr_hits::total 39394 # number of ReadExReq MSHR hits 1419system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 3 # number of demand (read+write) MSHR hits 1420system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 178 # number of demand (read+write) MSHR hits 1421system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits 1422system.cpu0.l2cache.demand_mshr_hits::cpu0.data 45236 # number of demand (read+write) MSHR hits 1423system.cpu0.l2cache.demand_mshr_hits::total 45420 # number of demand (read+write) MSHR hits 1424system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 3 # number of overall MSHR hits 1425system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 178 # number of overall MSHR hits 1426system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits 1427system.cpu0.l2cache.overall_mshr_hits::cpu0.data 45236 # number of overall MSHR hits 1428system.cpu0.l2cache.overall_mshr_hits::total 45420 # number of overall MSHR hits 1429system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12604 # number of ReadReq MSHR misses 1430system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9083 # number of ReadReq MSHR misses 1431system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 702623 # number of ReadReq MSHR misses 1432system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 1109640 # number of ReadReq MSHR misses 1433system.cpu0.l2cache.ReadReq_mshr_misses::total 1833950 # number of ReadReq MSHR misses 1434system.cpu0.l2cache.Writeback_mshr_misses::writebacks 4 # number of Writeback MSHR misses 1435system.cpu0.l2cache.Writeback_mshr_misses::total 4 # number of Writeback MSHR misses 1436system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 823501 # number of HardPFReq MSHR misses 1437system.cpu0.l2cache.HardPFReq_mshr_misses::total 823501 # number of HardPFReq MSHR misses 1438system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 637697 # number of WriteInvalidateReq MSHR misses 1439system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 637697 # number of WriteInvalidateReq MSHR misses 1440system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 138114 # number of UpgradeReq MSHR misses 1441system.cpu0.l2cache.UpgradeReq_mshr_misses::total 138114 # number of UpgradeReq MSHR misses 1442system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 172230 # number of SCUpgradeReq MSHR misses 1443system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 172230 # number of SCUpgradeReq MSHR misses 1444system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses 1445system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 1446system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 269896 # number of ReadExReq MSHR misses 1447system.cpu0.l2cache.ReadExReq_mshr_misses::total 269896 # number of ReadExReq MSHR misses 1448system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12604 # number of demand (read+write) MSHR misses 1449system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9083 # number of demand (read+write) MSHR misses 1450system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 702623 # number of demand (read+write) MSHR misses 1451system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1379536 # number of demand (read+write) MSHR misses 1452system.cpu0.l2cache.demand_mshr_misses::total 2103846 # number of demand (read+write) MSHR misses 1453system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12604 # number of overall MSHR misses 1454system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9083 # number of overall MSHR misses 1455system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 702623 # number of overall MSHR misses 1456system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1379536 # number of overall MSHR misses 1457system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 823501 # number of overall MSHR misses 1458system.cpu0.l2cache.overall_mshr_misses::total 2927347 # number of overall MSHR misses 1459system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 379527210 # number of ReadReq MSHR miss cycles 1460system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 312895441 # number of ReadReq MSHR miss cycles 1461system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 15722901634 # number of ReadReq MSHR miss cycles 1462system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 31613467375 # number of ReadReq MSHR miss cycles 1463system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 48028791660 # number of ReadReq MSHR miss cycles 1464system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 55041075389 # number of HardPFReq MSHR miss cycles 1465system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 55041075389 # number of HardPFReq MSHR miss cycles 1466system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 36305734974 # number of WriteInvalidateReq MSHR miss cycles 1467system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 36305734974 # number of WriteInvalidateReq MSHR miss cycles 1468system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2408365451 # number of UpgradeReq MSHR miss cycles 1469system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2408365451 # number of UpgradeReq MSHR miss cycles 1470system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2333282169 # number of SCUpgradeReq MSHR miss cycles 1471system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2333282169 # number of SCUpgradeReq MSHR miss cycles 1472system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2482000 # number of SCUpgradeFailReq MSHR miss cycles 1473system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2482000 # number of SCUpgradeFailReq MSHR miss cycles 1474system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11186143543 # number of ReadExReq MSHR miss cycles 1475system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11186143543 # number of ReadExReq MSHR miss cycles 1476system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 379527210 # number of demand (read+write) MSHR miss cycles 1477system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 312895441 # number of demand (read+write) MSHR miss cycles 1478system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 15722901634 # number of demand (read+write) MSHR miss cycles 1479system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 42799610918 # number of demand (read+write) MSHR miss cycles 1480system.cpu0.l2cache.demand_mshr_miss_latency::total 59214935203 # number of demand (read+write) MSHR miss cycles 1481system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 379527210 # number of overall MSHR miss cycles 1482system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 312895441 # number of overall MSHR miss cycles 1483system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 15722901634 # number of overall MSHR miss cycles 1484system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 42799610918 # number of overall MSHR miss cycles 1485system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 55041075389 # number of overall MSHR miss cycles 1486system.cpu0.l2cache.overall_mshr_miss_latency::total 114256010592 # number of overall MSHR miss cycles 1487system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1519174250 # number of ReadReq MSHR uncacheable cycles 1488system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5322353508 # number of ReadReq MSHR uncacheable cycles 1489system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6841527758 # number of ReadReq MSHR uncacheable cycles 1490system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5082599974 # number of WriteReq MSHR uncacheable cycles 1491system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5082599974 # number of WriteReq MSHR uncacheable cycles 1492system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1519174250 # number of overall MSHR uncacheable cycles 1493system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10404953482 # number of overall MSHR uncacheable cycles 1494system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11924127732 # number of overall MSHR uncacheable cycles 1495system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021192 # mshr miss rate for ReadReq accesses 1496system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.047320 # mshr miss rate for ReadReq accesses 1497system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.110318 # mshr miss rate for ReadReq accesses 1498system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.258030 # mshr miss rate for ReadReq accesses 1499system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.160084 # mshr miss rate for ReadReq accesses 1500system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for Writeback accesses 1501system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000001 # mshr miss rate for Writeback accesses | 1397system.cpu0.l2cache.writebacks::writebacks 1389796 # number of writebacks 1398system.cpu0.l2cache.writebacks::total 1389796 # number of writebacks 1399system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 4 # number of ReadReq MSHR hits 1400system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 142 # number of ReadReq MSHR hits 1401system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits 1402system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 4324 # number of ReadReq MSHR hits 1403system.cpu0.l2cache.ReadReq_mshr_hits::total 4477 # number of ReadReq MSHR hits 1404system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 6 # number of WriteInvalidateReq MSHR hits 1405system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 6 # number of WriteInvalidateReq MSHR hits 1406system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 17304 # number of ReadExReq MSHR hits 1407system.cpu0.l2cache.ReadExReq_mshr_hits::total 17304 # number of ReadExReq MSHR hits 1408system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 4 # number of demand (read+write) MSHR hits 1409system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 142 # number of demand (read+write) MSHR hits 1410system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits 1411system.cpu0.l2cache.demand_mshr_hits::cpu0.data 21628 # number of demand (read+write) MSHR hits 1412system.cpu0.l2cache.demand_mshr_hits::total 21781 # number of demand (read+write) MSHR hits 1413system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 4 # number of overall MSHR hits 1414system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 142 # number of overall MSHR hits 1415system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits 1416system.cpu0.l2cache.overall_mshr_hits::cpu0.data 21628 # number of overall MSHR hits 1417system.cpu0.l2cache.overall_mshr_hits::total 21781 # number of overall MSHR hits 1418system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10648 # number of ReadReq MSHR misses 1419system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8010 # number of ReadReq MSHR misses 1420system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 635988 # number of ReadReq MSHR misses 1421system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 996165 # number of ReadReq MSHR misses 1422system.cpu0.l2cache.ReadReq_mshr_misses::total 1650811 # number of ReadReq MSHR misses 1423system.cpu0.l2cache.Writeback_mshr_misses::writebacks 10 # number of Writeback MSHR misses 1424system.cpu0.l2cache.Writeback_mshr_misses::total 10 # number of Writeback MSHR misses 1425system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 695022 # number of HardPFReq MSHR misses 1426system.cpu0.l2cache.HardPFReq_mshr_misses::total 695022 # number of HardPFReq MSHR misses 1427system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 594860 # number of WriteInvalidateReq MSHR misses 1428system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 594860 # number of WriteInvalidateReq MSHR misses 1429system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 133117 # number of UpgradeReq MSHR misses 1430system.cpu0.l2cache.UpgradeReq_mshr_misses::total 133117 # number of UpgradeReq MSHR misses 1431system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 160078 # number of SCUpgradeReq MSHR misses 1432system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 160078 # number of SCUpgradeReq MSHR misses 1433system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 19 # number of SCUpgradeFailReq MSHR misses 1434system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 19 # number of SCUpgradeFailReq MSHR misses 1435system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 257287 # number of ReadExReq MSHR misses 1436system.cpu0.l2cache.ReadExReq_mshr_misses::total 257287 # number of ReadExReq MSHR misses 1437system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10648 # number of demand (read+write) MSHR misses 1438system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8010 # number of demand (read+write) MSHR misses 1439system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 635988 # number of demand (read+write) MSHR misses 1440system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1253452 # number of demand (read+write) MSHR misses 1441system.cpu0.l2cache.demand_mshr_misses::total 1908098 # number of demand (read+write) MSHR misses 1442system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10648 # number of overall MSHR misses 1443system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8010 # number of overall MSHR misses 1444system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 635988 # number of overall MSHR misses 1445system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1253452 # number of overall MSHR misses 1446system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 695022 # number of overall MSHR misses 1447system.cpu0.l2cache.overall_mshr_misses::total 2603120 # number of overall MSHR misses 1448system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 268701028 # number of ReadReq MSHR miss cycles 1449system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 209265519 # number of ReadReq MSHR miss cycles 1450system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 15816568891 # number of ReadReq MSHR miss cycles 1451system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 27389377929 # number of ReadReq MSHR miss cycles 1452system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 43683913367 # number of ReadReq MSHR miss cycles 1453system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 34637549956 # number of HardPFReq MSHR miss cycles 1454system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 34637549956 # number of HardPFReq MSHR miss cycles 1455system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 28746452436 # number of WriteInvalidateReq MSHR miss cycles 1456system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 28746452436 # number of WriteInvalidateReq MSHR miss cycles 1457system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2662823288 # number of UpgradeReq MSHR miss cycles 1458system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2662823288 # number of UpgradeReq MSHR miss cycles 1459system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2368378420 # number of SCUpgradeReq MSHR miss cycles 1460system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2368378420 # number of SCUpgradeReq MSHR miss cycles 1461system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4277498 # number of SCUpgradeFailReq MSHR miss cycles 1462system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4277498 # number of SCUpgradeFailReq MSHR miss cycles 1463system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10397244749 # number of ReadExReq MSHR miss cycles 1464system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10397244749 # number of ReadExReq MSHR miss cycles 1465system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 268701028 # number of demand (read+write) MSHR miss cycles 1466system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 209265519 # number of demand (read+write) MSHR miss cycles 1467system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 15816568891 # number of demand (read+write) MSHR miss cycles 1468system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 37786622678 # number of demand (read+write) MSHR miss cycles 1469system.cpu0.l2cache.demand_mshr_miss_latency::total 54081158116 # number of demand (read+write) MSHR miss cycles 1470system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 268701028 # number of overall MSHR miss cycles 1471system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 209265519 # number of overall MSHR miss cycles 1472system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 15816568891 # number of overall MSHR miss cycles 1473system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 37786622678 # number of overall MSHR miss cycles 1474system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 34637549956 # number of overall MSHR miss cycles 1475system.cpu0.l2cache.overall_mshr_miss_latency::total 88718708072 # number of overall MSHR miss cycles 1476system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1711512000 # number of ReadReq MSHR uncacheable cycles 1477system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5486110502 # number of ReadReq MSHR uncacheable cycles 1478system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7197622502 # number of ReadReq MSHR uncacheable cycles 1479system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5256416460 # number of WriteReq MSHR uncacheable cycles 1480system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5256416460 # number of WriteReq MSHR uncacheable cycles 1481system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1711512000 # number of overall MSHR uncacheable cycles 1482system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10742526962 # number of overall MSHR uncacheable cycles 1483system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12454038962 # number of overall MSHR uncacheable cycles 1484system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020773 # mshr miss rate for ReadReq accesses 1485system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045633 # mshr miss rate for ReadReq accesses 1486system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.104739 # mshr miss rate for ReadReq accesses 1487system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.253956 # mshr miss rate for ReadReq accesses 1488system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.154529 # mshr miss rate for ReadReq accesses 1489system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000003 # mshr miss rate for Writeback accesses 1490system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000003 # mshr miss rate for Writeback accesses |
| 1502system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1503system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1491system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1492system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1504system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.762335 # mshr miss rate for WriteInvalidateReq accesses 1505system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.762335 # mshr miss rate for WriteInvalidateReq accesses 1506system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.546175 # mshr miss rate for UpgradeReq accesses 1507system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.546175 # mshr miss rate for UpgradeReq accesses 1508system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.823890 # mshr miss rate for SCUpgradeReq accesses 1509system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.823890 # mshr miss rate for SCUpgradeReq accesses | 1493system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.722802 # mshr miss rate for WriteInvalidateReq accesses 1494system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.722802 # mshr miss rate for WriteInvalidateReq accesses 1495system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.550623 # mshr miss rate for UpgradeReq accesses 1496system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.550623 # mshr miss rate for UpgradeReq accesses 1497system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.824919 # mshr miss rate for SCUpgradeReq accesses 1498system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.824919 # mshr miss rate for SCUpgradeReq accesses |
| 1510system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1511system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 1499system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1500system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 1512system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.207527 # mshr miss rate for ReadExReq accesses 1513system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.207527 # mshr miss rate for ReadExReq accesses 1514system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021192 # mshr miss rate for demand accesses 1515system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.047320 # mshr miss rate for demand accesses 1516system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.110318 # mshr miss rate for demand accesses 1517system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.246303 # mshr miss rate for demand accesses 1518system.cpu0.l2cache.demand_mshr_miss_rate::total 0.164920 # mshr miss rate for demand accesses 1519system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021192 # mshr miss rate for overall accesses 1520system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.047320 # mshr miss rate for overall accesses 1521system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.110318 # mshr miss rate for overall accesses 1522system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.246303 # mshr miss rate for overall accesses | 1501system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.220782 # mshr miss rate for ReadExReq accesses 1502system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.220782 # mshr miss rate for ReadExReq accesses 1503system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.020773 # mshr miss rate for demand accesses 1504system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045633 # mshr miss rate for demand accesses 1505system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.104739 # mshr miss rate for demand accesses 1506system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.246358 # mshr miss rate for demand accesses 1507system.cpu0.l2cache.demand_mshr_miss_rate::total 0.161046 # mshr miss rate for demand accesses 1508system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.020773 # mshr miss rate for overall accesses 1509system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045633 # mshr miss rate for overall accesses 1510system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.104739 # mshr miss rate for overall accesses 1511system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.246358 # mshr miss rate for overall accesses |
| 1523system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1512system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1524system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229475 # mshr miss rate for overall accesses 1525system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890 # average ReadReq mshr miss latency 1526system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678 # average ReadReq mshr miss latency 1527system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22377.436597 # average ReadReq mshr miss latency 1528system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 28489.841187 # average ReadReq mshr miss latency 1529system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26188.713793 # average ReadReq mshr miss latency 1530system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66837.897451 # average HardPFReq mshr miss latency 1531system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 66837.897451 # average HardPFReq mshr miss latency 1532system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 56932.579225 # average WriteInvalidateReq mshr miss latency 1533system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 56932.579225 # average WriteInvalidateReq mshr miss latency 1534system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17437.518651 # average UpgradeReq mshr miss latency 1535system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17437.518651 # average UpgradeReq mshr miss latency 1536system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13547.478192 # average SCUpgradeReq mshr miss latency 1537system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13547.478192 # average SCUpgradeReq mshr miss latency 1538system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 496400 # average SCUpgradeFailReq mshr miss latency 1539system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 496400 # average SCUpgradeFailReq mshr miss latency 1540system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41446.125704 # average ReadExReq mshr miss latency 1541system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41446.125704 # average ReadExReq mshr miss latency 1542system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890 # average overall mshr miss latency 1543system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678 # average overall mshr miss latency 1544system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22377.436597 # average overall mshr miss latency 1545system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31024.642284 # average overall mshr miss latency 1546system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28146.040729 # average overall mshr miss latency 1547system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890 # average overall mshr miss latency 1548system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678 # average overall mshr miss latency 1549system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22377.436597 # average overall mshr miss latency 1550system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31024.642284 # average overall mshr miss latency 1551system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66837.897451 # average overall mshr miss latency 1552system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39030.566104 # average overall mshr miss latency | 1513system.cpu0.l2cache.overall_mshr_miss_rate::total 0.219706 # mshr miss rate for overall accesses 1514system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25234.882419 # average ReadReq mshr miss latency 1515system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26125.532959 # average ReadReq mshr miss latency 1516system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24869.288243 # average ReadReq mshr miss latency 1517system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27494.820566 # average ReadReq mshr miss latency 1518system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26462.092491 # average ReadReq mshr miss latency 1519system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49836.623813 # average HardPFReq mshr miss latency 1520system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49836.623813 # average HardPFReq mshr miss latency 1521system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 48324.735965 # average WriteInvalidateReq mshr miss latency 1522system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 48324.735965 # average WriteInvalidateReq mshr miss latency 1523system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20003.630551 # average UpgradeReq mshr miss latency 1524system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20003.630551 # average UpgradeReq mshr miss latency 1525system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14795.152488 # average SCUpgradeReq mshr miss latency 1526system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14795.152488 # average SCUpgradeReq mshr miss latency 1527system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 225131.473684 # average SCUpgradeFailReq mshr miss latency 1528system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 225131.473684 # average SCUpgradeFailReq mshr miss latency 1529system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40411.076926 # average ReadExReq mshr miss latency 1530system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40411.076926 # average ReadExReq mshr miss latency 1531system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25234.882419 # average overall mshr miss latency 1532system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26125.532959 # average overall mshr miss latency 1533system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24869.288243 # average overall mshr miss latency 1534system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30146.046820 # average overall mshr miss latency 1535system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28342.966722 # average overall mshr miss latency 1536system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25234.882419 # average overall mshr miss latency 1537system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26125.532959 # average overall mshr miss latency 1538system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24869.288243 # average overall mshr miss latency 1539system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30146.046820 # average overall mshr miss latency 1540system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49836.623813 # average overall mshr miss latency 1541system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34081.682009 # average overall mshr miss latency |
| 1553system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1554system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1555system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1556system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1557system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1558system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1559system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1560system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1561system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1542system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1543system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1544system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1545system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1546system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1547system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1548system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1549system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1550system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1562system.cpu0.toL2Bus.trans_dist::ReadReq 13921371 # Transaction distribution 1563system.cpu0.toL2Bus.trans_dist::ReadResp 11750633 # Transaction distribution 1564system.cpu0.toL2Bus.trans_dist::WriteReq 31686 # Transaction distribution 1565system.cpu0.toL2Bus.trans_dist::WriteResp 31686 # Transaction distribution 1566system.cpu0.toL2Bus.trans_dist::Writeback 4276525 # Transaction distribution 1567system.cpu0.toL2Bus.trans_dist::HardPFReq 1274288 # Transaction distribution 1568system.cpu0.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution 1569system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1162561 # Transaction distribution 1570system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 836505 # Transaction distribution 1571system.cpu0.toL2Bus.trans_dist::UpgradeReq 509905 # Transaction distribution 1572system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 381643 # Transaction distribution 1573system.cpu0.toL2Bus.trans_dist::UpgradeResp 535354 # Transaction distribution 1574system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 87 # Transaction distribution 1575system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 157 # Transaction distribution 1576system.cpu0.toL2Bus.trans_dist::ReadExReq 1437620 # Transaction distribution 1577system.cpu0.toL2Bus.trans_dist::ReadExResp 1309284 # Transaction distribution 1578system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12781022 # Packet count per connected master and slave (bytes) 1579system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18390339 # Packet count per connected master and slave (bytes) 1580system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 414542 # Packet count per connected master and slave (bytes) 1581system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1294088 # Packet count per connected master and slave (bytes) 1582system.cpu0.toL2Bus.pkt_count::total 32879991 # Packet count per connected master and slave (bytes) 1583system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 407960480 # Cumulative packet size per connected master and slave (bytes) 1584system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 693234728 # Cumulative packet size per connected master and slave (bytes) 1585system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1535584 # Cumulative packet size per connected master and slave (bytes) 1586system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4758096 # Cumulative packet size per connected master and slave (bytes) 1587system.cpu0.toL2Bus.pkt_size::total 1107488888 # Cumulative packet size per connected master and slave (bytes) 1588system.cpu0.toL2Bus.snoops 4767578 # Total snoops (count) 1589system.cpu0.toL2Bus.snoop_fanout::samples 22911203 # Request fanout histogram 1590system.cpu0.toL2Bus.snoop_fanout::mean 5.193957 # Request fanout histogram 1591system.cpu0.toL2Bus.snoop_fanout::stdev 0.395396 # Request fanout histogram | 1551system.cpu0.toL2Bus.trans_dist::ReadReq 13109671 # Transaction distribution 1552system.cpu0.toL2Bus.trans_dist::ReadResp 10998966 # Transaction distribution 1553system.cpu0.toL2Bus.trans_dist::WriteReq 32265 # Transaction distribution 1554system.cpu0.toL2Bus.trans_dist::WriteResp 32265 # Transaction distribution 1555system.cpu0.toL2Bus.trans_dist::Writeback 3967064 # Transaction distribution 1556system.cpu0.toL2Bus.trans_dist::HardPFReq 987402 # Transaction distribution 1557system.cpu0.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution 1558system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1170476 # Transaction distribution 1559system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 822992 # Transaction distribution 1560system.cpu0.toL2Bus.trans_dist::UpgradeReq 487373 # Transaction distribution 1561system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 355558 # Transaction distribution 1562system.cpu0.toL2Bus.trans_dist::UpgradeResp 509064 # Transaction distribution 1563system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 118 # Transaction distribution 1564system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 208 # Transaction distribution 1565system.cpu0.toL2Bus.trans_dist::ReadExReq 1297704 # Transaction distribution 1566system.cpu0.toL2Bus.trans_dist::ReadExResp 1174184 # Transaction distribution 1567system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12186882 # Packet count per connected master and slave (bytes) 1568system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16978089 # Packet count per connected master and slave (bytes) 1569system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 390292 # Packet count per connected master and slave (bytes) 1570system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1142423 # Packet count per connected master and slave (bytes) 1571system.cpu0.toL2Bus.pkt_count::total 30697686 # Packet count per connected master and slave (bytes) 1572system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 388957536 # Cumulative packet size per connected master and slave (bytes) 1573system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 639747662 # Cumulative packet size per connected master and slave (bytes) 1574system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1404248 # Cumulative packet size per connected master and slave (bytes) 1575system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4100656 # Cumulative packet size per connected master and slave (bytes) 1576system.cpu0.toL2Bus.pkt_size::total 1034210102 # Cumulative packet size per connected master and slave (bytes) 1577system.cpu0.toL2Bus.snoops 4435865 # Total snoops (count) 1578system.cpu0.toL2Bus.snoop_fanout::samples 21321710 # Request fanout histogram 1579system.cpu0.toL2Bus.snoop_fanout::mean 3.191876 # Request fanout histogram 1580system.cpu0.toL2Bus.snoop_fanout::stdev 0.393776 # Request fanout histogram |
| 1592system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1593system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1594system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1595system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 1581system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1582system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1583system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1584system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 1596system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1597system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1598system.cpu0.toL2Bus.snoop_fanout::5 18467409 80.60% 80.60% # Request fanout histogram 1599system.cpu0.toL2Bus.snoop_fanout::6 4443794 19.40% 100.00% # Request fanout histogram | 1585system.cpu0.toL2Bus.snoop_fanout::3 17230589 80.81% 80.81% # Request fanout histogram 1586system.cpu0.toL2Bus.snoop_fanout::4 4091121 19.19% 100.00% # Request fanout histogram |
| 1600system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1587system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1601system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1602system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1603system.cpu0.toL2Bus.snoop_fanout::total 22911203 # Request fanout histogram 1604system.cpu0.toL2Bus.reqLayer0.occupancy 14408211332 # Layer occupancy (ticks) | 1588system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1589system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1590system.cpu0.toL2Bus.snoop_fanout::total 21321710 # Request fanout histogram 1591system.cpu0.toL2Bus.reqLayer0.occupancy 13464993223 # Layer occupancy (ticks) |
| 1605system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1592system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1606system.cpu0.toL2Bus.snoopLayer0.occupancy 208870495 # Layer occupancy (ticks) | 1593system.cpu0.toL2Bus.snoopLayer0.occupancy 208995484 # Layer occupancy (ticks) |
| 1607system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1594system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1608system.cpu0.toL2Bus.respLayer0.occupancy 9596174213 # Layer occupancy (ticks) | 1595system.cpu0.toL2Bus.respLayer0.occupancy 9149850308 # Layer occupancy (ticks) |
| 1609system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1596system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1610system.cpu0.toL2Bus.respLayer1.occupancy 9165770534 # Layer occupancy (ticks) | 1597system.cpu0.toL2Bus.respLayer1.occupancy 8376078494 # Layer occupancy (ticks) |
| 1611system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1598system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1612system.cpu0.toL2Bus.respLayer2.occupancy 223497560 # Layer occupancy (ticks) | 1599system.cpu0.toL2Bus.respLayer2.occupancy 215375806 # Layer occupancy (ticks) |
| 1613system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1600system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1614system.cpu0.toL2Bus.respLayer3.occupancy 700918244 # Layer occupancy (ticks) | 1601system.cpu0.toL2Bus.respLayer3.occupancy 630757127 # Layer occupancy (ticks) |
| 1615system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1602system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1616system.cpu1.branchPred.lookups 124370032 # Number of BP lookups 1617system.cpu1.branchPred.condPredicted 83075187 # Number of conditional branches predicted 1618system.cpu1.branchPred.condIncorrect 6189003 # Number of conditional branches incorrect 1619system.cpu1.branchPred.BTBLookups 87824878 # Number of BTB lookups 1620system.cpu1.branchPred.BTBHits 56905034 # Number of BTB hits | 1603system.cpu1.branchPred.lookups 124182653 # Number of BP lookups 1604system.cpu1.branchPred.condPredicted 82299269 # Number of conditional branches predicted 1605system.cpu1.branchPred.condIncorrect 6251064 # Number of conditional branches incorrect 1606system.cpu1.branchPred.BTBLookups 87493813 # Number of BTB lookups 1607system.cpu1.branchPred.BTBHits 57426824 # Number of BTB hits |
| 1621system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1608system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1622system.cpu1.branchPred.BTBHitPct 64.793752 # BTB Hit Percentage 1623system.cpu1.branchPred.usedRAS 16687776 # Number of times the RAS was used to get a target. 1624system.cpu1.branchPred.RASInCorrect 168367 # Number of incorrect RAS predictions. | 1609system.cpu1.branchPred.BTBHitPct 65.635297 # BTB Hit Percentage 1610system.cpu1.branchPred.usedRAS 17076023 # Number of times the RAS was used to get a target. 1611system.cpu1.branchPred.RASInCorrect 176220 # Number of incorrect RAS predictions. |
| 1625system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1626system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1627system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1628system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1629system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1630system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1631system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1632system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1646system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1647system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1648system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1649system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1650system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1651system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1652system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1653system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1612system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1613system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1614system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1615system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1616system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1617system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1618system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1619system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1633system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1634system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1635system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1636system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1637system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1638system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1639system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1640system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1654system.cpu1.dtb.walker.walks 538943 # Table walker walks requested 1655system.cpu1.dtb.walker.walksLong 538943 # Table walker walks initiated with long descriptors 1656system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11373 # Level at which table walker walks with long descriptors terminate 1657system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 87574 # Level at which table walker walks with long descriptors terminate 1658system.cpu1.dtb.walker.walksSquashedBefore 237839 # Table walks squashed before starting 1659system.cpu1.dtb.walker.walkWaitTime::samples 301104 # Table walker wait (enqueue to first request) latency 1660system.cpu1.dtb.walker.walkWaitTime::mean 1852.353340 # Table walker wait (enqueue to first request) latency 1661system.cpu1.dtb.walker.walkWaitTime::stdev 11107.804354 # Table walker wait (enqueue to first request) latency 1662system.cpu1.dtb.walker.walkWaitTime::0-32767 297190 98.70% 98.70% # Table walker wait (enqueue to first request) latency 1663system.cpu1.dtb.walker.walkWaitTime::32768-65535 2030 0.67% 99.37% # Table walker wait (enqueue to first request) latency 1664system.cpu1.dtb.walker.walkWaitTime::65536-98303 795 0.26% 99.64% # Table walker wait (enqueue to first request) latency 1665system.cpu1.dtb.walker.walkWaitTime::98304-131071 637 0.21% 99.85% # Table walker wait (enqueue to first request) latency 1666system.cpu1.dtb.walker.walkWaitTime::131072-163839 257 0.09% 99.94% # Table walker wait (enqueue to first request) latency 1667system.cpu1.dtb.walker.walkWaitTime::163840-196607 66 0.02% 99.96% # Table walker wait (enqueue to first request) latency 1668system.cpu1.dtb.walker.walkWaitTime::196608-229375 39 0.01% 99.97% # Table walker wait (enqueue to first request) latency 1669system.cpu1.dtb.walker.walkWaitTime::229376-262143 29 0.01% 99.98% # Table walker wait (enqueue to first request) latency 1670system.cpu1.dtb.walker.walkWaitTime::262144-294911 48 0.02% 100.00% # Table walker wait (enqueue to first request) latency 1671system.cpu1.dtb.walker.walkWaitTime::294912-327679 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1672system.cpu1.dtb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1673system.cpu1.dtb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1674system.cpu1.dtb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1675system.cpu1.dtb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1676system.cpu1.dtb.walker.walkWaitTime::total 301104 # Table walker wait (enqueue to first request) latency 1677system.cpu1.dtb.walker.walkCompletionTime::samples 268131 # Table walker service (enqueue to completion) latency 1678system.cpu1.dtb.walker.walkCompletionTime::mean 15772.437909 # Table walker service (enqueue to completion) latency 1679system.cpu1.dtb.walker.walkCompletionTime::gmean 12981.371112 # Table walker service (enqueue to completion) latency 1680system.cpu1.dtb.walker.walkCompletionTime::stdev 15992.673962 # Table walker service (enqueue to completion) latency 1681system.cpu1.dtb.walker.walkCompletionTime::0-65535 265367 98.97% 98.97% # Table walker service (enqueue to completion) latency 1682system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1941 0.72% 99.69% # Table walker service (enqueue to completion) latency 1683system.cpu1.dtb.walker.walkCompletionTime::131072-196607 396 0.15% 99.84% # Table walker service (enqueue to completion) latency 1684system.cpu1.dtb.walker.walkCompletionTime::196608-262143 232 0.09% 99.93% # Table walker service (enqueue to completion) latency 1685system.cpu1.dtb.walker.walkCompletionTime::262144-327679 106 0.04% 99.97% # Table walker service (enqueue to completion) latency 1686system.cpu1.dtb.walker.walkCompletionTime::327680-393215 37 0.01% 99.98% # Table walker service (enqueue to completion) latency 1687system.cpu1.dtb.walker.walkCompletionTime::393216-458751 35 0.01% 99.99% # Table walker service (enqueue to completion) latency 1688system.cpu1.dtb.walker.walkCompletionTime::458752-524287 12 0.00% 100.00% # Table walker service (enqueue to completion) latency | 1641system.cpu1.dtb.walker.walks 534049 # Table walker walks requested 1642system.cpu1.dtb.walker.walksLong 534049 # Table walker walks initiated with long descriptors 1643system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11595 # Level at which table walker walks with long descriptors terminate 1644system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85531 # Level at which table walker walks with long descriptors terminate 1645system.cpu1.dtb.walker.walksSquashedBefore 242787 # Table walks squashed before starting 1646system.cpu1.dtb.walker.walkWaitTime::samples 291262 # Table walker wait (enqueue to first request) latency 1647system.cpu1.dtb.walker.walkWaitTime::mean 2048.229773 # Table walker wait (enqueue to first request) latency 1648system.cpu1.dtb.walker.walkWaitTime::stdev 11850.953616 # Table walker wait (enqueue to first request) latency 1649system.cpu1.dtb.walker.walkWaitTime::0-65535 289126 99.27% 99.27% # Table walker wait (enqueue to first request) latency 1650system.cpu1.dtb.walker.walkWaitTime::65536-131071 1672 0.57% 99.84% # Table walker wait (enqueue to first request) latency 1651system.cpu1.dtb.walker.walkWaitTime::131072-196607 329 0.11% 99.95% # Table walker wait (enqueue to first request) latency 1652system.cpu1.dtb.walker.walkWaitTime::196608-262143 62 0.02% 99.97% # Table walker wait (enqueue to first request) latency 1653system.cpu1.dtb.walker.walkWaitTime::262144-327679 62 0.02% 100.00% # Table walker wait (enqueue to first request) latency 1654system.cpu1.dtb.walker.walkWaitTime::327680-393215 10 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1655system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1656system.cpu1.dtb.walker.walkWaitTime::total 291262 # Table walker wait (enqueue to first request) latency 1657system.cpu1.dtb.walker.walkCompletionTime::samples 270383 # Table walker service (enqueue to completion) latency 1658system.cpu1.dtb.walker.walkCompletionTime::mean 17183.802917 # Table walker service (enqueue to completion) latency 1659system.cpu1.dtb.walker.walkCompletionTime::gmean 14328.415565 # Table walker service (enqueue to completion) latency 1660system.cpu1.dtb.walker.walkCompletionTime::stdev 16454.576356 # Table walker service (enqueue to completion) latency 1661system.cpu1.dtb.walker.walkCompletionTime::0-65535 267229 98.83% 98.83% # Table walker service (enqueue to completion) latency 1662system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2235 0.83% 99.66% # Table walker service (enqueue to completion) latency 1663system.cpu1.dtb.walker.walkCompletionTime::131072-196607 352 0.13% 99.79% # Table walker service (enqueue to completion) latency 1664system.cpu1.dtb.walker.walkCompletionTime::196608-262143 368 0.14% 99.93% # Table walker service (enqueue to completion) latency 1665system.cpu1.dtb.walker.walkCompletionTime::262144-327679 149 0.06% 99.98% # Table walker service (enqueue to completion) latency 1666system.cpu1.dtb.walker.walkCompletionTime::327680-393215 35 0.01% 99.99% # Table walker service (enqueue to completion) latency 1667system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 1668system.cpu1.dtb.walker.walkCompletionTime::458752-524287 10 0.00% 100.00% # Table walker service (enqueue to completion) latency |
| 1689system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency | 1669system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency |
| 1690system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1691system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1692system.cpu1.dtb.walker.walkCompletionTime::total 268131 # Table walker service (enqueue to completion) latency 1693system.cpu1.dtb.walker.walksPending::samples 435751861088 # Table walker pending requests distribution 1694system.cpu1.dtb.walker.walksPending::mean 0.614829 # Table walker pending requests distribution 1695system.cpu1.dtb.walker.walksPending::stdev 0.532518 # Table walker pending requests distribution 1696system.cpu1.dtb.walker.walksPending::0-1 434859464588 99.80% 99.80% # Table walker pending requests distribution 1697system.cpu1.dtb.walker.walksPending::2-3 474800000 0.11% 99.90% # Table walker pending requests distribution 1698system.cpu1.dtb.walker.walksPending::4-5 202701000 0.05% 99.95% # Table walker pending requests distribution 1699system.cpu1.dtb.walker.walksPending::6-7 89682000 0.02% 99.97% # Table walker pending requests distribution 1700system.cpu1.dtb.walker.walksPending::8-9 62866500 0.01% 99.99% # Table walker pending requests distribution 1701system.cpu1.dtb.walker.walksPending::10-11 34103000 0.01% 99.99% # Table walker pending requests distribution 1702system.cpu1.dtb.walker.walksPending::12-13 13310500 0.00% 100.00% # Table walker pending requests distribution 1703system.cpu1.dtb.walker.walksPending::14-15 14713000 0.00% 100.00% # Table walker pending requests distribution 1704system.cpu1.dtb.walker.walksPending::16-17 214000 0.00% 100.00% # Table walker pending requests distribution 1705system.cpu1.dtb.walker.walksPending::18-19 6500 0.00% 100.00% # Table walker pending requests distribution 1706system.cpu1.dtb.walker.walksPending::total 435751861088 # Table walker pending requests distribution 1707system.cpu1.dtb.walker.walkPageSizes::4K 87574 88.51% 88.51% # Table walker page sizes translated 1708system.cpu1.dtb.walker.walkPageSizes::2M 11373 11.49% 100.00% # Table walker page sizes translated 1709system.cpu1.dtb.walker.walkPageSizes::total 98947 # Table walker page sizes translated 1710system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 538943 # Table walker requests started/completed, data/inst | 1670system.cpu1.dtb.walker.walkCompletionTime::total 270383 # Table walker service (enqueue to completion) latency 1671system.cpu1.dtb.walker.walksPending::samples 438879688048 # Table walker pending requests distribution 1672system.cpu1.dtb.walker.walksPending::mean 0.596096 # Table walker pending requests distribution 1673system.cpu1.dtb.walker.walksPending::stdev 0.540539 # Table walker pending requests distribution 1674system.cpu1.dtb.walker.walksPending::0-1 437883178548 99.77% 99.77% # Table walker pending requests distribution 1675system.cpu1.dtb.walker.walksPending::2-3 543837500 0.12% 99.90% # Table walker pending requests distribution 1676system.cpu1.dtb.walker.walksPending::4-5 218551000 0.05% 99.95% # Table walker pending requests distribution 1677system.cpu1.dtb.walker.walksPending::6-7 91365500 0.02% 99.97% # Table walker pending requests distribution 1678system.cpu1.dtb.walker.walksPending::8-9 75836500 0.02% 99.98% # Table walker pending requests distribution 1679system.cpu1.dtb.walker.walksPending::10-11 38561500 0.01% 99.99% # Table walker pending requests distribution 1680system.cpu1.dtb.walker.walksPending::12-13 12555000 0.00% 100.00% # Table walker pending requests distribution 1681system.cpu1.dtb.walker.walksPending::14-15 15271000 0.00% 100.00% # Table walker pending requests distribution 1682system.cpu1.dtb.walker.walksPending::16-17 530000 0.00% 100.00% # Table walker pending requests distribution 1683system.cpu1.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution 1684system.cpu1.dtb.walker.walksPending::total 438879688048 # Table walker pending requests distribution 1685system.cpu1.dtb.walker.walkPageSizes::4K 85532 88.06% 88.06% # Table walker page sizes translated 1686system.cpu1.dtb.walker.walkPageSizes::2M 11595 11.94% 100.00% # Table walker page sizes translated 1687system.cpu1.dtb.walker.walkPageSizes::total 97127 # Table walker page sizes translated 1688system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 534049 # Table walker requests started/completed, data/inst |
| 1711system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 1689system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 1712system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 538943 # Table walker requests started/completed, data/inst 1713system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 98947 # Table walker requests started/completed, data/inst | 1690system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 534049 # Table walker requests started/completed, data/inst 1691system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97127 # Table walker requests started/completed, data/inst |
| 1714system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 1692system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 1715system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 98947 # Table walker requests started/completed, data/inst 1716system.cpu1.dtb.walker.walkRequestOrigin::total 637890 # Table walker requests started/completed, data/inst | 1693system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97127 # Table walker requests started/completed, data/inst 1694system.cpu1.dtb.walker.walkRequestOrigin::total 631176 # Table walker requests started/completed, data/inst |
| 1717system.cpu1.dtb.inst_hits 0 # ITB inst hits 1718system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1695system.cpu1.dtb.inst_hits 0 # ITB inst hits 1696system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1719system.cpu1.dtb.read_hits 91392867 # DTB read hits 1720system.cpu1.dtb.read_misses 373745 # DTB read misses 1721system.cpu1.dtb.write_hits 75805429 # DTB write hits 1722system.cpu1.dtb.write_misses 165198 # DTB write misses | 1697system.cpu1.dtb.read_hits 91849877 # DTB read hits 1698system.cpu1.dtb.read_misses 382442 # DTB read misses 1699system.cpu1.dtb.write_hits 75119650 # DTB write hits 1700system.cpu1.dtb.write_misses 151607 # DTB write misses |
| 1723system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1724system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 1701system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1702system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 1725system.cpu1.dtb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID 1726system.cpu1.dtb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID 1727system.cpu1.dtb.flush_entries 37451 # Number of entries that have been flushed from TLB 1728system.cpu1.dtb.align_faults 309 # Number of TLB faults due to alignment restrictions 1729system.cpu1.dtb.prefetch_faults 5879 # Number of TLB faults due to prefetch | 1703system.cpu1.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID 1704system.cpu1.dtb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID 1705system.cpu1.dtb.flush_entries 39274 # Number of entries that have been flushed from TLB 1706system.cpu1.dtb.align_faults 401 # Number of TLB faults due to alignment restrictions 1707system.cpu1.dtb.prefetch_faults 5573 # Number of TLB faults due to prefetch |
| 1730system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1708system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1731system.cpu1.dtb.perms_faults 40297 # Number of TLB faults due to permissions restrictions 1732system.cpu1.dtb.read_accesses 91766612 # DTB read accesses 1733system.cpu1.dtb.write_accesses 75970627 # DTB write accesses | 1709system.cpu1.dtb.perms_faults 36948 # Number of TLB faults due to permissions restrictions 1710system.cpu1.dtb.read_accesses 92232319 # DTB read accesses 1711system.cpu1.dtb.write_accesses 75271257 # DTB write accesses |
| 1734system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1712system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1735system.cpu1.dtb.hits 167198296 # DTB hits 1736system.cpu1.dtb.misses 538943 # DTB misses 1737system.cpu1.dtb.accesses 167737239 # DTB accesses | 1713system.cpu1.dtb.hits 166969527 # DTB hits 1714system.cpu1.dtb.misses 534049 # DTB misses 1715system.cpu1.dtb.accesses 167503576 # DTB accesses |
| 1738system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1739system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1740system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1741system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1742system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1743system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1744system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1745system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1759system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1760system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1761system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1762system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1763system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1764system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1765system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1766system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1716system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1717system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1718system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1719system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1720system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1721system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1722system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1723system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1737system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1738system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1739system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1740system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1741system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1742system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1743system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1744system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1767system.cpu1.itb.walker.walks 85244 # Table walker walks requested 1768system.cpu1.itb.walker.walksLong 85244 # Table walker walks initiated with long descriptors 1769system.cpu1.itb.walker.walksLongTerminationLevel::Level2 675 # Level at which table walker walks with long descriptors terminate 1770system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61262 # Level at which table walker walks with long descriptors terminate 1771system.cpu1.itb.walker.walksSquashedBefore 9941 # Table walks squashed before starting 1772system.cpu1.itb.walker.walkWaitTime::samples 75303 # Table walker wait (enqueue to first request) latency 1773system.cpu1.itb.walker.walkWaitTime::mean 1139.330438 # Table walker wait (enqueue to first request) latency 1774system.cpu1.itb.walker.walkWaitTime::stdev 8399.837182 # Table walker wait (enqueue to first request) latency 1775system.cpu1.itb.walker.walkWaitTime::0-32767 74771 99.29% 99.29% # Table walker wait (enqueue to first request) latency 1776system.cpu1.itb.walker.walkWaitTime::32768-65535 180 0.24% 99.53% # Table walker wait (enqueue to first request) latency 1777system.cpu1.itb.walker.walkWaitTime::65536-98303 193 0.26% 99.79% # Table walker wait (enqueue to first request) latency 1778system.cpu1.itb.walker.walkWaitTime::98304-131071 128 0.17% 99.96% # Table walker wait (enqueue to first request) latency 1779system.cpu1.itb.walker.walkWaitTime::131072-163839 12 0.02% 99.97% # Table walker wait (enqueue to first request) latency 1780system.cpu1.itb.walker.walkWaitTime::163840-196607 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency 1781system.cpu1.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1782system.cpu1.itb.walker.walkWaitTime::262144-294911 6 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1783system.cpu1.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1784system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1785system.cpu1.itb.walker.walkWaitTime::total 75303 # Table walker wait (enqueue to first request) latency 1786system.cpu1.itb.walker.walkCompletionTime::samples 71878 # Table walker service (enqueue to completion) latency 1787system.cpu1.itb.walker.walkCompletionTime::mean 20268.763168 # Table walker service (enqueue to completion) latency 1788system.cpu1.itb.walker.walkCompletionTime::gmean 17115.147893 # Table walker service (enqueue to completion) latency 1789system.cpu1.itb.walker.walkCompletionTime::stdev 19721.935997 # Table walker service (enqueue to completion) latency 1790system.cpu1.itb.walker.walkCompletionTime::0-65535 70231 97.71% 97.71% # Table walker service (enqueue to completion) latency 1791system.cpu1.itb.walker.walkCompletionTime::65536-131071 1324 1.84% 99.55% # Table walker service (enqueue to completion) latency 1792system.cpu1.itb.walker.walkCompletionTime::131072-196607 179 0.25% 99.80% # Table walker service (enqueue to completion) latency 1793system.cpu1.itb.walker.walkCompletionTime::196608-262143 68 0.09% 99.89% # Table walker service (enqueue to completion) latency 1794system.cpu1.itb.walker.walkCompletionTime::262144-327679 46 0.06% 99.96% # Table walker service (enqueue to completion) latency 1795system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.98% # Table walker service (enqueue to completion) latency 1796system.cpu1.itb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 1797system.cpu1.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 1798system.cpu1.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency | 1745system.cpu1.itb.walker.walks 85651 # Table walker walks requested 1746system.cpu1.itb.walker.walksLong 85651 # Table walker walks initiated with long descriptors 1747system.cpu1.itb.walker.walksLongTerminationLevel::Level2 898 # Level at which table walker walks with long descriptors terminate 1748system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61483 # Level at which table walker walks with long descriptors terminate 1749system.cpu1.itb.walker.walksSquashedBefore 9913 # Table walks squashed before starting 1750system.cpu1.itb.walker.walkWaitTime::samples 75738 # Table walker wait (enqueue to first request) latency 1751system.cpu1.itb.walker.walkWaitTime::mean 1212.145818 # Table walker wait (enqueue to first request) latency 1752system.cpu1.itb.walker.walkWaitTime::stdev 8774.873802 # Table walker wait (enqueue to first request) latency 1753system.cpu1.itb.walker.walkWaitTime::0-32767 75006 99.03% 99.03% # Table walker wait (enqueue to first request) latency 1754system.cpu1.itb.walker.walkWaitTime::32768-65535 365 0.48% 99.52% # Table walker wait (enqueue to first request) latency 1755system.cpu1.itb.walker.walkWaitTime::65536-98303 180 0.24% 99.75% # Table walker wait (enqueue to first request) latency 1756system.cpu1.itb.walker.walkWaitTime::98304-131071 161 0.21% 99.97% # Table walker wait (enqueue to first request) latency 1757system.cpu1.itb.walker.walkWaitTime::131072-163839 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency 1758system.cpu1.itb.walker.walkWaitTime::163840-196607 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency 1759system.cpu1.itb.walker.walkWaitTime::196608-229375 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency 1760system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency 1761system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency 1762system.cpu1.itb.walker.walkWaitTime::294912-327679 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 1763system.cpu1.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1764system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1765system.cpu1.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1766system.cpu1.itb.walker.walkWaitTime::total 75738 # Table walker wait (enqueue to first request) latency 1767system.cpu1.itb.walker.walkCompletionTime::samples 72294 # Table walker service (enqueue to completion) latency 1768system.cpu1.itb.walker.walkCompletionTime::mean 21947.554182 # Table walker service (enqueue to completion) latency 1769system.cpu1.itb.walker.walkCompletionTime::gmean 18825.235250 # Table walker service (enqueue to completion) latency 1770system.cpu1.itb.walker.walkCompletionTime::stdev 19960.579515 # Table walker service (enqueue to completion) latency 1771system.cpu1.itb.walker.walkCompletionTime::0-65535 70492 97.51% 97.51% # Table walker service (enqueue to completion) latency 1772system.cpu1.itb.walker.walkCompletionTime::65536-131071 1482 2.05% 99.56% # Table walker service (enqueue to completion) latency 1773system.cpu1.itb.walker.walkCompletionTime::131072-196607 157 0.22% 99.77% # Table walker service (enqueue to completion) latency 1774system.cpu1.itb.walker.walkCompletionTime::196608-262143 99 0.14% 99.91% # Table walker service (enqueue to completion) latency 1775system.cpu1.itb.walker.walkCompletionTime::262144-327679 33 0.05% 99.96% # Table walker service (enqueue to completion) latency 1776system.cpu1.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.98% # Table walker service (enqueue to completion) latency 1777system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.01% 100.00% # Table walker service (enqueue to completion) latency 1778system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency |
| 1799system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency | 1779system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency |
| 1800system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1801system.cpu1.itb.walker.walkCompletionTime::total 71878 # Table walker service (enqueue to completion) latency 1802system.cpu1.itb.walker.walksPending::samples 397094361424 # Table walker pending requests distribution 1803system.cpu1.itb.walker.walksPending::mean 0.878531 # Table walker pending requests distribution 1804system.cpu1.itb.walker.walksPending::stdev 0.326828 # Table walker pending requests distribution 1805system.cpu1.itb.walker.walksPending::0 48253813024 12.15% 12.15% # Table walker pending requests distribution 1806system.cpu1.itb.walker.walksPending::1 348822790900 87.84% 100.00% # Table walker pending requests distribution 1807system.cpu1.itb.walker.walksPending::2 16535000 0.00% 100.00% # Table walker pending requests distribution 1808system.cpu1.itb.walker.walksPending::3 1219500 0.00% 100.00% # Table walker pending requests distribution 1809system.cpu1.itb.walker.walksPending::4 3000 0.00% 100.00% # Table walker pending requests distribution 1810system.cpu1.itb.walker.walksPending::total 397094361424 # Table walker pending requests distribution 1811system.cpu1.itb.walker.walkPageSizes::4K 61262 98.91% 98.91% # Table walker page sizes translated 1812system.cpu1.itb.walker.walkPageSizes::2M 675 1.09% 100.00% # Table walker page sizes translated 1813system.cpu1.itb.walker.walkPageSizes::total 61937 # Table walker page sizes translated | 1780system.cpu1.itb.walker.walkCompletionTime::total 72294 # Table walker service (enqueue to completion) latency 1781system.cpu1.itb.walker.walksPending::samples 404519897680 # Table walker pending requests distribution 1782system.cpu1.itb.walker.walksPending::mean 0.847972 # Table walker pending requests distribution 1783system.cpu1.itb.walker.walksPending::stdev 0.359205 # Table walker pending requests distribution 1784system.cpu1.itb.walker.walksPending::0 61519279012 15.21% 15.21% # Table walker pending requests distribution 1785system.cpu1.itb.walker.walksPending::1 342981503668 84.79% 100.00% # Table walker pending requests distribution 1786system.cpu1.itb.walker.walksPending::2 17484500 0.00% 100.00% # Table walker pending requests distribution 1787system.cpu1.itb.walker.walksPending::3 1520000 0.00% 100.00% # Table walker pending requests distribution 1788system.cpu1.itb.walker.walksPending::4 101500 0.00% 100.00% # Table walker pending requests distribution 1789system.cpu1.itb.walker.walksPending::5 9000 0.00% 100.00% # Table walker pending requests distribution 1790system.cpu1.itb.walker.walksPending::total 404519897680 # Table walker pending requests distribution 1791system.cpu1.itb.walker.walkPageSizes::4K 61483 98.56% 98.56% # Table walker page sizes translated 1792system.cpu1.itb.walker.walkPageSizes::2M 898 1.44% 100.00% # Table walker page sizes translated 1793system.cpu1.itb.walker.walkPageSizes::total 62381 # Table walker page sizes translated |
| 1814system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 1794system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 1815system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 85244 # Table walker requests started/completed, data/inst 1816system.cpu1.itb.walker.walkRequestOrigin_Requested::total 85244 # Table walker requests started/completed, data/inst | 1795system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 85651 # Table walker requests started/completed, data/inst 1796system.cpu1.itb.walker.walkRequestOrigin_Requested::total 85651 # Table walker requests started/completed, data/inst |
| 1817system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 1797system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 1818system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61937 # Table walker requests started/completed, data/inst 1819system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61937 # Table walker requests started/completed, data/inst 1820system.cpu1.itb.walker.walkRequestOrigin::total 147181 # Table walker requests started/completed, data/inst 1821system.cpu1.itb.inst_hits 196146030 # ITB inst hits 1822system.cpu1.itb.inst_misses 85244 # ITB inst misses | 1798system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62381 # Table walker requests started/completed, data/inst 1799system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62381 # Table walker requests started/completed, data/inst 1800system.cpu1.itb.walker.walkRequestOrigin::total 148032 # Table walker requests started/completed, data/inst 1801system.cpu1.itb.inst_hits 196330607 # ITB inst hits 1802system.cpu1.itb.inst_misses 85651 # ITB inst misses |
| 1823system.cpu1.itb.read_hits 0 # DTB read hits 1824system.cpu1.itb.read_misses 0 # DTB read misses 1825system.cpu1.itb.write_hits 0 # DTB write hits 1826system.cpu1.itb.write_misses 0 # DTB write misses 1827system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1828system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 1803system.cpu1.itb.read_hits 0 # DTB read hits 1804system.cpu1.itb.read_misses 0 # DTB read misses 1805system.cpu1.itb.write_hits 0 # DTB write hits 1806system.cpu1.itb.write_misses 0 # DTB write misses 1807system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1808system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 1829system.cpu1.itb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID 1830system.cpu1.itb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID 1831system.cpu1.itb.flush_entries 26780 # Number of entries that have been flushed from TLB | 1809system.cpu1.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID 1810system.cpu1.itb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID 1811system.cpu1.itb.flush_entries 28544 # Number of entries that have been flushed from TLB |
| 1832system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1833system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1834system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1812system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1813system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1814system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1835system.cpu1.itb.perms_faults 213163 # Number of TLB faults due to permissions restrictions | 1815system.cpu1.itb.perms_faults 219679 # Number of TLB faults due to permissions restrictions |
| 1836system.cpu1.itb.read_accesses 0 # DTB read accesses 1837system.cpu1.itb.write_accesses 0 # DTB write accesses | 1816system.cpu1.itb.read_accesses 0 # DTB read accesses 1817system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1838system.cpu1.itb.inst_accesses 196231274 # ITB inst accesses 1839system.cpu1.itb.hits 196146030 # DTB hits 1840system.cpu1.itb.misses 85244 # DTB misses 1841system.cpu1.itb.accesses 196231274 # DTB accesses 1842system.cpu1.numCycles 664388878 # number of cpu cycles simulated | 1818system.cpu1.itb.inst_accesses 196416258 # ITB inst accesses 1819system.cpu1.itb.hits 196330607 # DTB hits 1820system.cpu1.itb.misses 85651 # DTB misses 1821system.cpu1.itb.accesses 196416258 # DTB accesses 1822system.cpu1.numCycles 659201565 # number of cpu cycles simulated |
| 1843system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1844system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1823system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1824system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1845system.cpu1.fetch.icacheStallCycles 79880322 # Number of cycles fetch is stalled on an Icache miss 1846system.cpu1.fetch.Insts 552169788 # Number of instructions fetch has processed 1847system.cpu1.fetch.Branches 124370032 # Number of branches that fetch encountered 1848system.cpu1.fetch.predictedBranches 73592810 # Number of branches that fetch has predicted taken 1849system.cpu1.fetch.Cycles 551328487 # Number of cycles fetch has run and was not squashing or blocked 1850system.cpu1.fetch.SquashCycles 13340182 # Number of cycles fetch has spent squashing 1851system.cpu1.fetch.TlbCycles 1707326 # Number of cycles fetch has spent waiting for tlb 1852system.cpu1.fetch.MiscStallCycles 246511 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1853system.cpu1.fetch.PendingTrapStallCycles 6080767 # Number of stall cycles due to pending traps 1854system.cpu1.fetch.PendingQuiesceStallCycles 727313 # Number of stall cycles due to pending quiesce instructions 1855system.cpu1.fetch.IcacheWaitRetryStallCycles 602439 # Number of stall cycles due to full MSHR 1856system.cpu1.fetch.CacheLines 195911596 # Number of cache lines fetched 1857system.cpu1.fetch.IcacheSquashes 1586691 # Number of outstanding Icache misses that were squashed 1858system.cpu1.fetch.ItlbSquashes 28723 # Number of outstanding ITLB misses that were squashed 1859system.cpu1.fetch.rateDist::samples 647243256 # Number of instructions fetched each cycle (Total) 1860system.cpu1.fetch.rateDist::mean 1.003235 # Number of instructions fetched each cycle (Total) 1861system.cpu1.fetch.rateDist::stdev 1.226187 # Number of instructions fetched each cycle (Total) | 1825system.cpu1.fetch.icacheStallCycles 81623724 # Number of cycles fetch is stalled on an Icache miss 1826system.cpu1.fetch.Insts 551229784 # Number of instructions fetch has processed 1827system.cpu1.fetch.Branches 124182653 # Number of branches that fetch encountered 1828system.cpu1.fetch.predictedBranches 74502847 # Number of branches that fetch has predicted taken 1829system.cpu1.fetch.Cycles 545141022 # Number of cycles fetch has run and was not squashing or blocked 1830system.cpu1.fetch.SquashCycles 13475474 # Number of cycles fetch has spent squashing 1831system.cpu1.fetch.TlbCycles 1814701 # Number of cycles fetch has spent waiting for tlb 1832system.cpu1.fetch.MiscStallCycles 236397 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1833system.cpu1.fetch.PendingTrapStallCycles 6195125 # Number of stall cycles due to pending traps 1834system.cpu1.fetch.PendingQuiesceStallCycles 729177 # Number of stall cycles due to pending quiesce instructions 1835system.cpu1.fetch.IcacheWaitRetryStallCycles 658891 # Number of stall cycles due to full MSHR 1836system.cpu1.fetch.CacheLines 196089515 # Number of cache lines fetched 1837system.cpu1.fetch.IcacheSquashes 1603144 # Number of outstanding Icache misses that were squashed 1838system.cpu1.fetch.ItlbSquashes 28612 # Number of outstanding ITLB misses that were squashed 1839system.cpu1.fetch.rateDist::samples 643136774 # Number of instructions fetched each cycle (Total) 1840system.cpu1.fetch.rateDist::mean 1.007577 # Number of instructions fetched each cycle (Total) 1841system.cpu1.fetch.rateDist::stdev 1.226676 # Number of instructions fetched each cycle (Total) |
| 1862system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 1842system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 1863system.cpu1.fetch.rateDist::0 336573756 52.00% 52.00% # Number of instructions fetched each cycle (Total) 1864system.cpu1.fetch.rateDist::1 120960986 18.69% 70.69% # Number of instructions fetched each cycle (Total) 1865system.cpu1.fetch.rateDist::2 40749741 6.30% 76.99% # Number of instructions fetched each cycle (Total) 1866system.cpu1.fetch.rateDist::3 148958773 23.01% 100.00% # Number of instructions fetched each cycle (Total) | 1843system.cpu1.fetch.rateDist::0 333162826 51.80% 51.80% # Number of instructions fetched each cycle (Total) 1844system.cpu1.fetch.rateDist::1 120232758 18.69% 70.50% # Number of instructions fetched each cycle (Total) 1845system.cpu1.fetch.rateDist::2 41446819 6.44% 76.94% # Number of instructions fetched each cycle (Total) 1846system.cpu1.fetch.rateDist::3 148294371 23.06% 100.00% # Number of instructions fetched each cycle (Total) |
| 1867system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1868system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1869system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 1847system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1848system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1849system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 1870system.cpu1.fetch.rateDist::total 647243256 # Number of instructions fetched each cycle (Total) 1871system.cpu1.fetch.branchRate 0.187195 # Number of branch fetches per cycle 1872system.cpu1.fetch.rate 0.831094 # Number of inst fetches per cycle 1873system.cpu1.decode.IdleCycles 96356177 # Number of cycles decode is idle 1874system.cpu1.decode.BlockedCycles 306396299 # Number of cycles decode is blocked 1875system.cpu1.decode.RunCycles 204571849 # Number of cycles decode is running 1876system.cpu1.decode.UnblockCycles 35206357 # Number of cycles decode is unblocking 1877system.cpu1.decode.SquashCycles 4712574 # Number of cycles decode is squashing 1878system.cpu1.decode.BranchResolved 17589142 # Number of times decode resolved a branch 1879system.cpu1.decode.BranchMispred 1996203 # Number of times decode detected a branch misprediction 1880system.cpu1.decode.DecodedInsts 573391383 # Number of instructions handled by decode 1881system.cpu1.decode.SquashedInsts 21361954 # Number of squashed instructions handled by decode 1882system.cpu1.rename.SquashCycles 4712574 # Number of cycles rename is squashing 1883system.cpu1.rename.IdleCycles 129172911 # Number of cycles rename is idle 1884system.cpu1.rename.BlockCycles 40460241 # Number of cycles rename is blocking 1885system.cpu1.rename.serializeStallCycles 212107385 # count of cycles rename stalled for serializing inst 1886system.cpu1.rename.RunCycles 206565063 # Number of cycles rename is running 1887system.cpu1.rename.UnblockCycles 54225082 # Number of cycles rename is unblocking 1888system.cpu1.rename.RenamedInsts 557977037 # Number of instructions processed by rename 1889system.cpu1.rename.SquashedInsts 5352379 # Number of squashed instructions processed by rename 1890system.cpu1.rename.ROBFullEvents 8193976 # Number of times rename has blocked due to ROB full 1891system.cpu1.rename.IQFullEvents 222351 # Number of times rename has blocked due to IQ full 1892system.cpu1.rename.LQFullEvents 303036 # Number of times rename has blocked due to LQ full 1893system.cpu1.rename.SQFullEvents 21276416 # Number of times rename has blocked due to SQ full 1894system.cpu1.rename.FullRegisterEvents 13923 # Number of times there has been no free registers 1895system.cpu1.rename.RenamedOperands 530659712 # Number of destination operands rename has renamed 1896system.cpu1.rename.RenameLookups 862978619 # Number of register rename lookups that rename has made 1897system.cpu1.rename.int_rename_lookups 659902858 # Number of integer rename lookups 1898system.cpu1.rename.fp_rename_lookups 766208 # Number of floating rename lookups 1899system.cpu1.rename.CommittedMaps 478267677 # Number of HB maps that are committed 1900system.cpu1.rename.UndoneMaps 52392029 # Number of HB maps that are undone due to squashing 1901system.cpu1.rename.serializingInsts 15246817 # count of serializing insts renamed 1902system.cpu1.rename.tempSerializingInsts 13453544 # count of temporary serializing insts renamed 1903system.cpu1.rename.skidInsts 71065053 # count of insts added to the skid buffer 1904system.cpu1.memDep0.insertedLoads 91863812 # Number of loads inserted to the mem dependence unit. 1905system.cpu1.memDep0.insertedStores 78915989 # Number of stores inserted to the mem dependence unit. 1906system.cpu1.memDep0.conflictingLoads 8629555 # Number of conflicting loads. 1907system.cpu1.memDep0.conflictingStores 7664780 # Number of conflicting stores. 1908system.cpu1.iq.iqInstsAdded 536633802 # Number of instructions added to the IQ (excludes non-spec) 1909system.cpu1.iq.iqNonSpecInstsAdded 15513444 # Number of non-speculative instructions added to the IQ 1910system.cpu1.iq.iqInstsIssued 541699362 # Number of instructions issued 1911system.cpu1.iq.iqSquashedInstsIssued 2485495 # Number of squashed instructions issued 1912system.cpu1.iq.iqSquashedInstsExamined 46695905 # Number of squashed instructions iterated over during squash; mainly for profiling 1913system.cpu1.iq.iqSquashedOperandsExamined 31776612 # Number of squashed operands that are examined and possibly removed from graph 1914system.cpu1.iq.iqSquashedNonSpecRemoved 271399 # Number of squashed non-spec instructions that were removed 1915system.cpu1.iq.issued_per_cycle::samples 647243256 # Number of insts issued each cycle 1916system.cpu1.iq.issued_per_cycle::mean 0.836933 # Number of insts issued each cycle 1917system.cpu1.iq.issued_per_cycle::stdev 1.069144 # Number of insts issued each cycle | 1850system.cpu1.fetch.rateDist::total 643136774 # Number of instructions fetched each cycle (Total) 1851system.cpu1.fetch.branchRate 0.188383 # Number of branch fetches per cycle 1852system.cpu1.fetch.rate 0.836208 # Number of inst fetches per cycle 1853system.cpu1.decode.IdleCycles 97937463 # Number of cycles decode is idle 1854system.cpu1.decode.BlockedCycles 300403958 # Number of cycles decode is blocked 1855system.cpu1.decode.RunCycles 205522733 # Number of cycles decode is running 1856system.cpu1.decode.UnblockCycles 34511986 # Number of cycles decode is unblocking 1857system.cpu1.decode.SquashCycles 4760634 # Number of cycles decode is squashing 1858system.cpu1.decode.BranchResolved 17730932 # Number of times decode resolved a branch 1859system.cpu1.decode.BranchMispred 2017504 # Number of times decode detected a branch misprediction 1860system.cpu1.decode.DecodedInsts 571814983 # Number of instructions handled by decode 1861system.cpu1.decode.SquashedInsts 21511068 # Number of squashed instructions handled by decode 1862system.cpu1.rename.SquashCycles 4760634 # Number of cycles rename is squashing 1863system.cpu1.rename.IdleCycles 130465176 # Number of cycles rename is idle 1864system.cpu1.rename.BlockCycles 39849524 # Number of cycles rename is blocking 1865system.cpu1.rename.serializeStallCycles 206232237 # count of cycles rename stalled for serializing inst 1866system.cpu1.rename.RunCycles 207101717 # Number of cycles rename is running 1867system.cpu1.rename.UnblockCycles 54727486 # Number of cycles rename is unblocking 1868system.cpu1.rename.RenamedInsts 556322152 # Number of instructions processed by rename 1869system.cpu1.rename.SquashedInsts 5380569 # Number of squashed instructions processed by rename 1870system.cpu1.rename.ROBFullEvents 8461915 # Number of times rename has blocked due to ROB full 1871system.cpu1.rename.IQFullEvents 304416 # Number of times rename has blocked due to IQ full 1872system.cpu1.rename.LQFullEvents 605845 # Number of times rename has blocked due to LQ full 1873system.cpu1.rename.SQFullEvents 22227660 # Number of times rename has blocked due to SQ full 1874system.cpu1.rename.FullRegisterEvents 11247 # Number of times there has been no free registers 1875system.cpu1.rename.RenamedOperands 528347539 # Number of destination operands rename has renamed 1876system.cpu1.rename.RenameLookups 856455710 # Number of register rename lookups that rename has made 1877system.cpu1.rename.int_rename_lookups 657084844 # Number of integer rename lookups 1878system.cpu1.rename.fp_rename_lookups 755426 # Number of floating rename lookups 1879system.cpu1.rename.CommittedMaps 475426080 # Number of HB maps that are committed 1880system.cpu1.rename.UndoneMaps 52921453 # Number of HB maps that are undone due to squashing 1881system.cpu1.rename.serializingInsts 14732861 # count of serializing insts renamed 1882system.cpu1.rename.tempSerializingInsts 12829203 # count of temporary serializing insts renamed 1883system.cpu1.rename.skidInsts 69624573 # count of insts added to the skid buffer 1884system.cpu1.memDep0.insertedLoads 92331469 # Number of loads inserted to the mem dependence unit. 1885system.cpu1.memDep0.insertedStores 78236769 # Number of stores inserted to the mem dependence unit. 1886system.cpu1.memDep0.conflictingLoads 8977003 # Number of conflicting loads. 1887system.cpu1.memDep0.conflictingStores 7612209 # Number of conflicting stores. 1888system.cpu1.iq.iqInstsAdded 535459998 # Number of instructions added to the IQ (excludes non-spec) 1889system.cpu1.iq.iqNonSpecInstsAdded 14979383 # Number of non-speculative instructions added to the IQ 1890system.cpu1.iq.iqInstsIssued 539826932 # Number of instructions issued 1891system.cpu1.iq.iqSquashedInstsIssued 2475624 # Number of squashed instructions issued 1892system.cpu1.iq.iqSquashedInstsExamined 46992661 # Number of squashed instructions iterated over during squash; mainly for profiling 1893system.cpu1.iq.iqSquashedOperandsExamined 32301398 # Number of squashed operands that are examined and possibly removed from graph 1894system.cpu1.iq.iqSquashedNonSpecRemoved 273094 # Number of squashed non-spec instructions that were removed 1895system.cpu1.iq.issued_per_cycle::samples 643136774 # Number of insts issued each cycle 1896system.cpu1.iq.issued_per_cycle::mean 0.839366 # Number of insts issued each cycle 1897system.cpu1.iq.issued_per_cycle::stdev 1.069808 # Number of insts issued each cycle |
| 1918system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 1898system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 1919system.cpu1.iq.issued_per_cycle::0 349912497 54.06% 54.06% # Number of insts issued each cycle 1920system.cpu1.iq.issued_per_cycle::1 127097301 19.64% 73.70% # Number of insts issued each cycle 1921system.cpu1.iq.issued_per_cycle::2 103346931 15.97% 89.67% # Number of insts issued each cycle 1922system.cpu1.iq.issued_per_cycle::3 59640858 9.21% 98.88% # Number of insts issued each cycle 1923system.cpu1.iq.issued_per_cycle::4 7242720 1.12% 100.00% # Number of insts issued each cycle 1924system.cpu1.iq.issued_per_cycle::5 2949 0.00% 100.00% # Number of insts issued each cycle | 1899system.cpu1.iq.issued_per_cycle::0 347132433 53.97% 53.97% # Number of insts issued each cycle 1900system.cpu1.iq.issued_per_cycle::1 125915806 19.58% 73.55% # Number of insts issued each cycle 1901system.cpu1.iq.issued_per_cycle::2 103467009 16.09% 89.64% # Number of insts issued each cycle 1902system.cpu1.iq.issued_per_cycle::3 59513725 9.25% 98.89% # Number of insts issued each cycle 1903system.cpu1.iq.issued_per_cycle::4 7103072 1.10% 100.00% # Number of insts issued each cycle 1904system.cpu1.iq.issued_per_cycle::5 4729 0.00% 100.00% # Number of insts issued each cycle |
| 1925system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1926system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1927system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1928system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1929system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1930system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 1905system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1906system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1907system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1908system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1909system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1910system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 1931system.cpu1.iq.issued_per_cycle::total 647243256 # Number of insts issued each cycle | 1911system.cpu1.iq.issued_per_cycle::total 643136774 # Number of insts issued each cycle |
| 1932system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 1912system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 1933system.cpu1.iq.fu_full::IntAlu 54464030 43.99% 43.99% # attempts to use FU when none available 1934system.cpu1.iq.fu_full::IntMult 55578 0.04% 44.03% # attempts to use FU when none available 1935system.cpu1.iq.fu_full::IntDiv 15828 0.01% 44.05% # attempts to use FU when none available 1936system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.05% # attempts to use FU when none available 1937system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.05% # attempts to use FU when none available 1938system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.05% # attempts to use FU when none available 1939system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.05% # attempts to use FU when none available 1940system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.05% # attempts to use FU when none available 1941system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.05% # attempts to use FU when none available 1942system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.05% # attempts to use FU when none available 1943system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.05% # attempts to use FU when none available 1944system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.05% # attempts to use FU when none available 1945system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.05% # attempts to use FU when none available 1946system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.05% # attempts to use FU when none available 1947system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.05% # attempts to use FU when none available 1948system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.05% # attempts to use FU when none available 1949system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.05% # attempts to use FU when none available 1950system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.05% # attempts to use FU when none available 1951system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.05% # attempts to use FU when none available 1952system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.05% # attempts to use FU when none available 1953system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.05% # attempts to use FU when none available 1954system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.05% # attempts to use FU when none available 1955system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.05% # attempts to use FU when none available 1956system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.05% # attempts to use FU when none available 1957system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.05% # attempts to use FU when none available 1958system.cpu1.iq.fu_full::SimdFloatMisc 9 0.00% 44.05% # attempts to use FU when none available 1959system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.05% # attempts to use FU when none available 1960system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.05% # attempts to use FU when none available 1961system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.05% # attempts to use FU when none available 1962system.cpu1.iq.fu_full::MemRead 33234382 26.84% 70.89% # attempts to use FU when none available 1963system.cpu1.iq.fu_full::MemWrite 36043585 29.11% 100.00% # attempts to use FU when none available | 1913system.cpu1.iq.fu_full::IntAlu 53820631 43.79% 43.79% # attempts to use FU when none available 1914system.cpu1.iq.fu_full::IntMult 63940 0.05% 43.85% # attempts to use FU when none available 1915system.cpu1.iq.fu_full::IntDiv 7561 0.01% 43.85% # attempts to use FU when none available 1916system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.85% # attempts to use FU when none available 1917system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.85% # attempts to use FU when none available 1918system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.85% # attempts to use FU when none available 1919system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.85% # attempts to use FU when none available 1920system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.85% # attempts to use FU when none available 1921system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.85% # attempts to use FU when none available 1922system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.85% # attempts to use FU when none available 1923system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.85% # attempts to use FU when none available 1924system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.85% # attempts to use FU when none available 1925system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.85% # attempts to use FU when none available 1926system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.85% # attempts to use FU when none available 1927system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.85% # attempts to use FU when none available 1928system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.85% # attempts to use FU when none available 1929system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.85% # attempts to use FU when none available 1930system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.85% # attempts to use FU when none available 1931system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.85% # attempts to use FU when none available 1932system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.85% # attempts to use FU when none available 1933system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.85% # attempts to use FU when none available 1934system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.85% # attempts to use FU when none available 1935system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.85% # attempts to use FU when none available 1936system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.85% # attempts to use FU when none available 1937system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.85% # attempts to use FU when none available 1938system.cpu1.iq.fu_full::SimdFloatMisc 17 0.00% 43.85% # attempts to use FU when none available 1939system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.85% # attempts to use FU when none available 1940system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.85% # attempts to use FU when none available 1941system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.85% # attempts to use FU when none available 1942system.cpu1.iq.fu_full::MemRead 33515144 27.27% 71.12% # attempts to use FU when none available 1943system.cpu1.iq.fu_full::MemWrite 35487446 28.88% 100.00% # attempts to use FU when none available |
| 1964system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1965system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available | 1944system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1945system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| 1966system.cpu1.iq.FU_type_0::No_OpClass 12 0.00% 0.00% # Type of FU issued 1967system.cpu1.iq.FU_type_0::IntAlu 369233279 68.16% 68.16% # Type of FU issued 1968system.cpu1.iq.FU_type_0::IntMult 1193564 0.22% 68.38% # Type of FU issued 1969system.cpu1.iq.FU_type_0::IntDiv 69127 0.01% 68.40% # Type of FU issued 1970system.cpu1.iq.FU_type_0::FloatAdd 2 0.00% 68.40% # Type of FU issued 1971system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.40% # Type of FU issued 1972system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.40% # Type of FU issued 1973system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.40% # Type of FU issued 1974system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.40% # Type of FU issued 1975system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued 1976system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued 1977system.cpu1.iq.FU_type_0::SimdAddAcc 1 0.00% 68.40% # Type of FU issued 1978system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.40% # Type of FU issued 1979system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.40% # Type of FU issued 1980system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.40% # Type of FU issued 1981system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.40% # Type of FU issued 1982system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.40% # Type of FU issued 1983system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.40% # Type of FU issued 1984system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.40% # Type of FU issued 1985system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.40% # Type of FU issued 1986system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.40% # Type of FU issued 1987system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.40% # Type of FU issued 1988system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.40% # Type of FU issued 1989system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.40% # Type of FU issued 1990system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.40% # Type of FU issued 1991system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.40% # Type of FU issued 1992system.cpu1.iq.FU_type_0::SimdFloatMisc 46847 0.01% 68.40% # Type of FU issued 1993system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.40% # Type of FU issued 1994system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.40% # Type of FU issued 1995system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.40% # Type of FU issued 1996system.cpu1.iq.FU_type_0::MemRead 94164053 17.38% 85.79% # Type of FU issued 1997system.cpu1.iq.FU_type_0::MemWrite 76992429 14.21% 100.00% # Type of FU issued | 1946system.cpu1.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued 1947system.cpu1.iq.FU_type_0::IntAlu 367420702 68.06% 68.06% # Type of FU issued 1948system.cpu1.iq.FU_type_0::IntMult 1281309 0.24% 68.30% # Type of FU issued 1949system.cpu1.iq.FU_type_0::IntDiv 73255 0.01% 68.31% # Type of FU issued 1950system.cpu1.iq.FU_type_0::FloatAdd 4 0.00% 68.31% # Type of FU issued 1951system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued 1952system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued 1953system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued 1954system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.31% # Type of FU issued 1955system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.31% # Type of FU issued 1956system.cpu1.iq.FU_type_0::SimdAdd 2 0.00% 68.31% # Type of FU issued 1957system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.31% # Type of FU issued 1958system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.31% # Type of FU issued 1959system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.31% # Type of FU issued 1960system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.31% # Type of FU issued 1961system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.31% # Type of FU issued 1962system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.31% # Type of FU issued 1963system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.31% # Type of FU issued 1964system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.31% # Type of FU issued 1965system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.31% # Type of FU issued 1966system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.31% # Type of FU issued 1967system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.31% # Type of FU issued 1968system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.31% # Type of FU issued 1969system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.31% # Type of FU issued 1970system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.31% # Type of FU issued 1971system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.31% # Type of FU issued 1972system.cpu1.iq.FU_type_0::SimdFloatMisc 83298 0.02% 68.33% # Type of FU issued 1973system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.33% # Type of FU issued 1974system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.33% # Type of FU issued 1975system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.33% # Type of FU issued 1976system.cpu1.iq.FU_type_0::MemRead 94677124 17.54% 85.87% # Type of FU issued 1977system.cpu1.iq.FU_type_0::MemWrite 76291227 14.13% 100.00% # Type of FU issued |
| 1998system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1999system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 1978system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 1979system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 2000system.cpu1.iq.FU_type_0::total 541699362 # Type of FU issued 2001system.cpu1.iq.rate 0.815335 # Inst issue rate 2002system.cpu1.iq.fu_busy_cnt 123813412 # FU busy when requested 2003system.cpu1.iq.fu_busy_rate 0.228565 # FU busy rate (busy events/executed inst) 2004system.cpu1.iq.int_inst_queue_reads 1855831634 # Number of integer instruction queue reads 2005system.cpu1.iq.int_inst_queue_writes 598546046 # Number of integer instruction queue writes 2006system.cpu1.iq.int_inst_queue_wakeup_accesses 526634223 # Number of integer instruction queue wakeup accesses 2007system.cpu1.iq.fp_inst_queue_reads 1109251 # Number of floating instruction queue reads 2008system.cpu1.iq.fp_inst_queue_writes 439129 # Number of floating instruction queue writes 2009system.cpu1.iq.fp_inst_queue_wakeup_accesses 408402 # Number of floating instruction queue wakeup accesses 2010system.cpu1.iq.int_alu_accesses 664822270 # Number of integer alu accesses 2011system.cpu1.iq.fp_alu_accesses 690492 # Number of floating point alu accesses 2012system.cpu1.iew.lsq.thread0.forwLoads 2431611 # Number of loads that had data forwarded from stores | 1980system.cpu1.iq.FU_type_0::total 539826932 # Type of FU issued 1981system.cpu1.iq.rate 0.818910 # Inst issue rate 1982system.cpu1.iq.fu_busy_cnt 122894739 # FU busy when requested 1983system.cpu1.iq.fu_busy_rate 0.227656 # FU busy rate (busy events/executed inst) 1984system.cpu1.iq.int_inst_queue_reads 1846883379 # Number of integer instruction queue reads 1985system.cpu1.iq.int_inst_queue_writes 597058317 # Number of integer instruction queue writes 1986system.cpu1.iq.int_inst_queue_wakeup_accesses 524462260 # Number of integer instruction queue wakeup accesses 1987system.cpu1.iq.fp_inst_queue_reads 1277620 # Number of floating instruction queue reads 1988system.cpu1.iq.fp_inst_queue_writes 514947 # Number of floating instruction queue writes 1989system.cpu1.iq.fp_inst_queue_wakeup_accesses 476158 # Number of floating instruction queue wakeup accesses 1990system.cpu1.iq.int_alu_accesses 661932910 # Number of integer alu accesses 1991system.cpu1.iq.fp_alu_accesses 788750 # Number of floating point alu accesses 1992system.cpu1.iew.lsq.thread0.forwLoads 2478321 # Number of loads that had data forwarded from stores |
| 2013system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 1993system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 2014system.cpu1.iew.lsq.thread0.squashedLoads 11396985 # Number of loads squashed 2015system.cpu1.iew.lsq.thread0.ignoredResponses 16347 # Number of memory responses ignored because the instruction is squashed 2016system.cpu1.iew.lsq.thread0.memOrderViolation 143339 # Number of memory ordering violations 2017system.cpu1.iew.lsq.thread0.squashedStores 5491640 # Number of stores squashed | 1994system.cpu1.iew.lsq.thread0.squashedLoads 11570290 # Number of loads squashed 1995system.cpu1.iew.lsq.thread0.ignoredResponses 16551 # Number of memory responses ignored because the instruction is squashed 1996system.cpu1.iew.lsq.thread0.memOrderViolation 142141 # Number of memory ordering violations 1997system.cpu1.iew.lsq.thread0.squashedStores 5437069 # Number of stores squashed |
| 2018system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2019system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 1998system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 1999system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 2020system.cpu1.iew.lsq.thread0.rescheduledLoads 2526857 # Number of loads that were rescheduled 2021system.cpu1.iew.lsq.thread0.cacheBlocked 3486247 # Number of times an access to memory failed due to the cache being blocked | 2000system.cpu1.iew.lsq.thread0.rescheduledLoads 2465198 # Number of loads that were rescheduled 2001system.cpu1.iew.lsq.thread0.cacheBlocked 3688063 # Number of times an access to memory failed due to the cache being blocked |
| 2022system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 2002system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 2023system.cpu1.iew.iewSquashCycles 4712574 # Number of cycles IEW is squashing 2024system.cpu1.iew.iewBlockCycles 5829545 # Number of cycles IEW is blocking 2025system.cpu1.iew.iewUnblockCycles 1427417 # Number of cycles IEW is unblocking 2026system.cpu1.iew.iewDispatchedInsts 552265728 # Number of instructions dispatched to IQ | 2003system.cpu1.iew.iewSquashCycles 4760634 # Number of cycles IEW is squashing 2004system.cpu1.iew.iewBlockCycles 6603988 # Number of cycles IEW is blocking 2005system.cpu1.iew.iewUnblockCycles 1453249 # Number of cycles IEW is unblocking 2006system.cpu1.iew.iewDispatchedInsts 550562460 # Number of instructions dispatched to IQ |
| 2027system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 2007system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 2028system.cpu1.iew.iewDispLoadInsts 91863812 # Number of dispatched load instructions 2029system.cpu1.iew.iewDispStoreInsts 78915989 # Number of dispatched store instructions 2030system.cpu1.iew.iewDispNonSpecInsts 13236985 # Number of dispatched non-speculative instructions 2031system.cpu1.iew.iewIQFullEvents 56254 # Number of times the IQ has become full, causing a stall 2032system.cpu1.iew.iewLSQFullEvents 1314129 # Number of times the LSQ has become full, causing a stall 2033system.cpu1.iew.memOrderViolationEvents 143339 # Number of memory order violations 2034system.cpu1.iew.predictedTakenIncorrect 1858186 # Number of branches that were predicted taken incorrectly 2035system.cpu1.iew.predictedNotTakenIncorrect 2653609 # Number of branches that were predicted not taken incorrectly 2036system.cpu1.iew.branchMispredicts 4511795 # Number of branch mispredicts detected at execute 2037system.cpu1.iew.iewExecutedInsts 534690067 # Number of executed instructions 2038system.cpu1.iew.iewExecLoadInsts 91388435 # Number of load instructions executed 2039system.cpu1.iew.iewExecSquashedInsts 6481283 # Number of squashed instructions skipped in execute | 2008system.cpu1.iew.iewDispLoadInsts 92331469 # Number of dispatched load instructions 2009system.cpu1.iew.iewDispStoreInsts 78236769 # Number of dispatched store instructions 2010system.cpu1.iew.iewDispNonSpecInsts 12610859 # Number of dispatched non-speculative instructions 2011system.cpu1.iew.iewIQFullEvents 52882 # Number of times the IQ has become full, causing a stall 2012system.cpu1.iew.iewLSQFullEvents 1339609 # Number of times the LSQ has become full, causing a stall 2013system.cpu1.iew.memOrderViolationEvents 142141 # Number of memory order violations 2014system.cpu1.iew.predictedTakenIncorrect 1900150 # Number of branches that were predicted taken incorrectly 2015system.cpu1.iew.predictedNotTakenIncorrect 2649580 # Number of branches that were predicted not taken incorrectly 2016system.cpu1.iew.branchMispredicts 4549730 # Number of branch mispredicts detected at execute 2017system.cpu1.iew.iewExecutedInsts 532747017 # Number of executed instructions 2018system.cpu1.iew.iewExecLoadInsts 91844367 # Number of load instructions executed 2019system.cpu1.iew.iewExecSquashedInsts 6553150 # Number of squashed instructions skipped in execute |
| 2040system.cpu1.iew.exec_swp 0 # number of swp insts executed | 2020system.cpu1.iew.exec_swp 0 # number of swp insts executed |
| 2041system.cpu1.iew.exec_nop 118482 # number of nop insts executed 2042system.cpu1.iew.exec_refs 167194328 # number of memory reference insts executed 2043system.cpu1.iew.exec_branches 100087893 # Number of branches executed 2044system.cpu1.iew.exec_stores 75805893 # Number of stores executed 2045system.cpu1.iew.exec_rate 0.804785 # Inst execution rate 2046system.cpu1.iew.wb_sent 527704335 # cumulative count of insts sent to commit 2047system.cpu1.iew.wb_count 527042625 # cumulative count of insts written-back 2048system.cpu1.iew.wb_producers 254576573 # num instructions producing a value 2049system.cpu1.iew.wb_consumers 416898701 # num instructions consuming a value | 2021system.cpu1.iew.exec_nop 123079 # number of nop insts executed 2022system.cpu1.iew.exec_refs 166962398 # number of memory reference insts executed 2023system.cpu1.iew.exec_branches 99765376 # Number of branches executed 2024system.cpu1.iew.exec_stores 75118031 # Number of stores executed 2025system.cpu1.iew.exec_rate 0.808170 # Inst execution rate 2026system.cpu1.iew.wb_sent 525632708 # cumulative count of insts sent to commit 2027system.cpu1.iew.wb_count 524938418 # cumulative count of insts written-back 2028system.cpu1.iew.wb_producers 254712512 # num instructions producing a value 2029system.cpu1.iew.wb_consumers 416314102 # num instructions consuming a value |
| 2050system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 2030system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 2051system.cpu1.iew.wb_rate 0.793274 # insts written-back per cycle 2052system.cpu1.iew.wb_fanout 0.610644 # average fanout of values written-back | 2031system.cpu1.iew.wb_rate 0.796325 # insts written-back per cycle 2032system.cpu1.iew.wb_fanout 0.611828 # average fanout of values written-back |
| 2053system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 2033system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 2054system.cpu1.commit.commitSquashedInsts 43642021 # The number of squashed insts skipped by commit 2055system.cpu1.commit.commitNonSpecStalls 15242045 # The number of times commit has been forced to stall to communicate backwards 2056system.cpu1.commit.branchMispredicts 4231486 # The number of times a branch was mispredicted 2057system.cpu1.commit.committed_per_cycle::samples 638973832 # Number of insts commited each cycle 2058system.cpu1.commit.committed_per_cycle::mean 0.786200 # Number of insts commited each cycle 2059system.cpu1.commit.committed_per_cycle::stdev 1.579868 # Number of insts commited each cycle | 2034system.cpu1.commit.commitSquashedInsts 43862550 # The number of squashed insts skipped by commit 2035system.cpu1.commit.commitNonSpecStalls 14706289 # The number of times commit has been forced to stall to communicate backwards 2036system.cpu1.commit.branchMispredicts 4273961 # The number of times a branch was mispredicted 2037system.cpu1.commit.committed_per_cycle::samples 634802902 # Number of insts commited each cycle 2038system.cpu1.commit.committed_per_cycle::mean 0.788218 # Number of insts commited each cycle 2039system.cpu1.commit.committed_per_cycle::stdev 1.581621 # Number of insts commited each cycle |
| 2060system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 2040system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 2061system.cpu1.commit.committed_per_cycle::0 417556945 65.35% 65.35% # Number of insts commited each cycle 2062system.cpu1.commit.committed_per_cycle::1 116379063 18.21% 83.56% # Number of insts commited each cycle 2063system.cpu1.commit.committed_per_cycle::2 48152991 7.54% 91.10% # Number of insts commited each cycle 2064system.cpu1.commit.committed_per_cycle::3 16068254 2.51% 93.61% # Number of insts commited each cycle 2065system.cpu1.commit.committed_per_cycle::4 11811974 1.85% 95.46% # Number of insts commited each cycle 2066system.cpu1.commit.committed_per_cycle::5 7886914 1.23% 96.70% # Number of insts commited each cycle 2067system.cpu1.commit.committed_per_cycle::6 5403679 0.85% 97.54% # Number of insts commited each cycle 2068system.cpu1.commit.committed_per_cycle::7 3345009 0.52% 98.06% # Number of insts commited each cycle 2069system.cpu1.commit.committed_per_cycle::8 12369003 1.94% 100.00% # Number of insts commited each cycle | 2041system.cpu1.commit.committed_per_cycle::0 414870625 65.35% 65.35% # Number of insts commited each cycle 2042system.cpu1.commit.committed_per_cycle::1 114759147 18.08% 83.43% # Number of insts commited each cycle 2043system.cpu1.commit.committed_per_cycle::2 48245889 7.60% 91.03% # Number of insts commited each cycle 2044system.cpu1.commit.committed_per_cycle::3 16373665 2.58% 93.61% # Number of insts commited each cycle 2045system.cpu1.commit.committed_per_cycle::4 11678245 1.84% 95.45% # Number of insts commited each cycle 2046system.cpu1.commit.committed_per_cycle::5 7925650 1.25% 96.70% # Number of insts commited each cycle 2047system.cpu1.commit.committed_per_cycle::6 5354812 0.84% 97.54% # Number of insts commited each cycle 2048system.cpu1.commit.committed_per_cycle::7 3238197 0.51% 98.05% # Number of insts commited each cycle 2049system.cpu1.commit.committed_per_cycle::8 12356672 1.95% 100.00% # Number of insts commited each cycle |
| 2070system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2071system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2072system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 2050system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2051system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2052system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 2073system.cpu1.commit.committed_per_cycle::total 638973832 # Number of insts commited each cycle 2074system.cpu1.commit.committedInsts 426124677 # Number of instructions committed 2075system.cpu1.commit.committedOps 502361434 # Number of ops (including micro ops) committed | 2053system.cpu1.commit.committed_per_cycle::total 634802902 # Number of insts commited each cycle 2054system.cpu1.commit.committedInsts 424719097 # Number of instructions committed 2055system.cpu1.commit.committedOps 500362777 # Number of ops (including micro ops) committed |
| 2076system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed | 2056system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed |
| 2077system.cpu1.commit.refs 153891175 # Number of memory references committed 2078system.cpu1.commit.loads 80466826 # Number of loads committed 2079system.cpu1.commit.membars 3635433 # Number of memory barriers committed 2080system.cpu1.commit.branches 94895008 # Number of branches committed 2081system.cpu1.commit.fp_insts 399904 # Number of committed floating point instructions. 2082system.cpu1.commit.int_insts 461321486 # Number of committed integer instructions. 2083system.cpu1.commit.function_calls 12405087 # Number of function calls committed. | 2057system.cpu1.commit.refs 153560878 # Number of memory references committed 2058system.cpu1.commit.loads 80761178 # Number of loads committed 2059system.cpu1.commit.membars 3652883 # Number of memory barriers committed 2060system.cpu1.commit.branches 94624372 # Number of branches committed 2061system.cpu1.commit.fp_insts 463166 # Number of committed floating point instructions. 2062system.cpu1.commit.int_insts 459868567 # Number of committed integer instructions. 2063system.cpu1.commit.function_calls 12685398 # Number of function calls committed. |
| 2084system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 2064system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 2085system.cpu1.commit.op_class_0::IntAlu 347396188 69.15% 69.15% # Class of committed instruction 2086system.cpu1.commit.op_class_0::IntMult 977319 0.19% 69.35% # Class of committed instruction 2087system.cpu1.commit.op_class_0::IntDiv 55389 0.01% 69.36% # Class of committed instruction 2088system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.36% # Class of committed instruction 2089system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.36% # Class of committed instruction 2090system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.36% # Class of committed instruction 2091system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.36% # Class of committed instruction 2092system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.36% # Class of committed instruction 2093system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.36% # Class of committed instruction 2094system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.36% # Class of committed instruction 2095system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.36% # Class of committed instruction 2096system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.36% # Class of committed instruction 2097system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.36% # Class of committed instruction 2098system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.36% # Class of committed instruction 2099system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.36% # Class of committed instruction 2100system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.36% # Class of committed instruction 2101system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.36% # Class of committed instruction 2102system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.36% # Class of committed instruction 2103system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.36% # Class of committed instruction 2104system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.36% # Class of committed instruction 2105system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.36% # Class of committed instruction 2106system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.36% # Class of committed instruction 2107system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.36% # Class of committed instruction 2108system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.36% # Class of committed instruction 2109system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.36% # Class of committed instruction 2110system.cpu1.commit.op_class_0::SimdFloatMisc 41321 0.01% 69.37% # Class of committed instruction 2111system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.37% # Class of committed instruction 2112system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.37% # Class of committed instruction 2113system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.37% # Class of committed instruction 2114system.cpu1.commit.op_class_0::MemRead 80466826 16.02% 85.38% # Class of committed instruction 2115system.cpu1.commit.op_class_0::MemWrite 73424349 14.62% 100.00% # Class of committed instruction | 2065system.cpu1.commit.op_class_0::IntAlu 345616008 69.07% 69.07% # Class of committed instruction 2066system.cpu1.commit.op_class_0::IntMult 1054252 0.21% 69.28% # Class of committed instruction 2067system.cpu1.commit.op_class_0::IntDiv 58059 0.01% 69.30% # Class of committed instruction 2068system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.30% # Class of committed instruction 2069system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.30% # Class of committed instruction 2070system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.30% # Class of committed instruction 2071system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.30% # Class of committed instruction 2072system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.30% # Class of committed instruction 2073system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.30% # Class of committed instruction 2074system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.30% # Class of committed instruction 2075system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.30% # Class of committed instruction 2076system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.30% # Class of committed instruction 2077system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.30% # Class of committed instruction 2078system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.30% # Class of committed instruction 2079system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.30% # Class of committed instruction 2080system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.30% # Class of committed instruction 2081system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.30% # Class of committed instruction 2082system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.30% # Class of committed instruction 2083system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.30% # Class of committed instruction 2084system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.30% # Class of committed instruction 2085system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.30% # Class of committed instruction 2086system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.30% # Class of committed instruction 2087system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.30% # Class of committed instruction 2088system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.30% # Class of committed instruction 2089system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.30% # Class of committed instruction 2090system.cpu1.commit.op_class_0::SimdFloatMisc 73580 0.01% 69.31% # Class of committed instruction 2091system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.31% # Class of committed instruction 2092system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.31% # Class of committed instruction 2093system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.31% # Class of committed instruction 2094system.cpu1.commit.op_class_0::MemRead 80761178 16.14% 85.45% # Class of committed instruction 2095system.cpu1.commit.op_class_0::MemWrite 72799700 14.55% 100.00% # Class of committed instruction |
| 2116system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2117system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 2096system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2097system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 2118system.cpu1.commit.op_class_0::total 502361434 # Class of committed instruction 2119system.cpu1.commit.bw_lim_events 12369003 # number cycles where commit BW limit reached | 2098system.cpu1.commit.op_class_0::total 500362777 # Class of committed instruction 2099system.cpu1.commit.bw_lim_events 12356672 # number cycles where commit BW limit reached |
| 2120system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits | 2100system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 2121system.cpu1.rob.rob_reads 1168820475 # The number of ROB reads 2122system.cpu1.rob.rob_writes 1100237743 # The number of ROB writes 2123system.cpu1.timesIdled 913492 # Number of times that the entire CPU went into an idle state and unscheduled itself 2124system.cpu1.idleCycles 17145622 # Total number of cycles that the CPU has spent unscheduled due to idling 2125system.cpu1.quiesceCycles 94026381638 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2126system.cpu1.committedInsts 426124677 # Number of Instructions Simulated 2127system.cpu1.committedOps 502361434 # Number of Ops (including micro ops) Simulated 2128system.cpu1.cpi 1.559142 # CPI: Cycles Per Instruction 2129system.cpu1.cpi_total 1.559142 # CPI: Total CPI of All Threads 2130system.cpu1.ipc 0.641378 # IPC: Instructions Per Cycle 2131system.cpu1.ipc_total 0.641378 # IPC: Total IPC of All Threads 2132system.cpu1.int_regfile_reads 632226075 # number of integer regfile reads 2133system.cpu1.int_regfile_writes 374528717 # number of integer regfile writes 2134system.cpu1.fp_regfile_reads 661926 # number of floating regfile reads 2135system.cpu1.fp_regfile_writes 331836 # number of floating regfile writes 2136system.cpu1.cc_regfile_reads 114587184 # number of cc regfile reads 2137system.cpu1.cc_regfile_writes 115385602 # number of cc regfile writes 2138system.cpu1.misc_regfile_reads 2619636946 # number of misc regfile reads 2139system.cpu1.misc_regfile_writes 15333141 # number of misc regfile writes 2140system.cpu1.dcache.tags.replacements 5236220 # number of replacements 2141system.cpu1.dcache.tags.tagsinuse 457.332610 # Cycle average of tags in use 2142system.cpu1.dcache.tags.total_refs 143091306 # Total number of references to valid blocks. 2143system.cpu1.dcache.tags.sampled_refs 5236730 # Sample count of references to valid blocks. 2144system.cpu1.dcache.tags.avg_refs 27.324553 # Average number of references to valid blocks. 2145system.cpu1.dcache.tags.warmup_cycle 8478701081000 # Cycle when the warmup percentage was hit. 2146system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.332610 # Average occupied blocks per requestor 2147system.cpu1.dcache.tags.occ_percent::cpu1.data 0.893228 # Average percentage of cache occupancy 2148system.cpu1.dcache.tags.occ_percent::total 0.893228 # Average percentage of cache occupancy 2149system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 2150system.cpu1.dcache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id 2151system.cpu1.dcache.tags.age_task_id_blocks_1024::1 334 # Occupied blocks per task id 2152system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id 2153system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 2154system.cpu1.dcache.tags.tag_accesses 319394188 # Number of tag accesses 2155system.cpu1.dcache.tags.data_accesses 319394188 # Number of data accesses 2156system.cpu1.dcache.ReadReq_hits::cpu1.data 74655263 # number of ReadReq hits 2157system.cpu1.dcache.ReadReq_hits::total 74655263 # number of ReadReq hits 2158system.cpu1.dcache.WriteReq_hits::cpu1.data 64023189 # number of WriteReq hits 2159system.cpu1.dcache.WriteReq_hits::total 64023189 # number of WriteReq hits 2160system.cpu1.dcache.SoftPFReq_hits::cpu1.data 163779 # number of SoftPFReq hits 2161system.cpu1.dcache.SoftPFReq_hits::total 163779 # number of SoftPFReq hits 2162system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 39797 # number of WriteInvalidateReq hits 2163system.cpu1.dcache.WriteInvalidateReq_hits::total 39797 # number of WriteInvalidateReq hits 2164system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1738928 # number of LoadLockedReq hits 2165system.cpu1.dcache.LoadLockedReq_hits::total 1738928 # number of LoadLockedReq hits 2166system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1751406 # number of StoreCondReq hits 2167system.cpu1.dcache.StoreCondReq_hits::total 1751406 # number of StoreCondReq hits 2168system.cpu1.dcache.demand_hits::cpu1.data 138678452 # number of demand (read+write) hits 2169system.cpu1.dcache.demand_hits::total 138678452 # number of demand (read+write) hits 2170system.cpu1.dcache.overall_hits::cpu1.data 138842231 # number of overall hits 2171system.cpu1.dcache.overall_hits::total 138842231 # number of overall hits 2172system.cpu1.dcache.ReadReq_misses::cpu1.data 6126939 # number of ReadReq misses 2173system.cpu1.dcache.ReadReq_misses::total 6126939 # number of ReadReq misses 2174system.cpu1.dcache.WriteReq_misses::cpu1.data 6982821 # number of WriteReq misses 2175system.cpu1.dcache.WriteReq_misses::total 6982821 # number of WriteReq misses 2176system.cpu1.dcache.SoftPFReq_misses::cpu1.data 659533 # number of SoftPFReq misses 2177system.cpu1.dcache.SoftPFReq_misses::total 659533 # number of SoftPFReq misses 2178system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 425377 # number of WriteInvalidateReq misses 2179system.cpu1.dcache.WriteInvalidateReq_misses::total 425377 # number of WriteInvalidateReq misses 2180system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 260578 # number of LoadLockedReq misses 2181system.cpu1.dcache.LoadLockedReq_misses::total 260578 # number of LoadLockedReq misses 2182system.cpu1.dcache.StoreCondReq_misses::cpu1.data 204152 # number of StoreCondReq misses 2183system.cpu1.dcache.StoreCondReq_misses::total 204152 # number of StoreCondReq misses 2184system.cpu1.dcache.demand_misses::cpu1.data 13109760 # number of demand (read+write) misses 2185system.cpu1.dcache.demand_misses::total 13109760 # number of demand (read+write) misses 2186system.cpu1.dcache.overall_misses::cpu1.data 13769293 # number of overall misses 2187system.cpu1.dcache.overall_misses::total 13769293 # number of overall misses 2188system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 92549514245 # number of ReadReq miss cycles 2189system.cpu1.dcache.ReadReq_miss_latency::total 92549514245 # number of ReadReq miss cycles 2190system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 116311286360 # number of WriteReq miss cycles 2191system.cpu1.dcache.WriteReq_miss_latency::total 116311286360 # number of WriteReq miss cycles 2192system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11708163921 # number of WriteInvalidateReq miss cycles 2193system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11708163921 # number of WriteInvalidateReq miss cycles 2194system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3758503444 # number of LoadLockedReq miss cycles 2195system.cpu1.dcache.LoadLockedReq_miss_latency::total 3758503444 # number of LoadLockedReq miss cycles 2196system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4320848660 # number of StoreCondReq miss cycles 2197system.cpu1.dcache.StoreCondReq_miss_latency::total 4320848660 # number of StoreCondReq miss cycles 2198system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3489000 # number of StoreCondFailReq miss cycles 2199system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3489000 # number of StoreCondFailReq miss cycles 2200system.cpu1.dcache.demand_miss_latency::cpu1.data 208860800605 # number of demand (read+write) miss cycles 2201system.cpu1.dcache.demand_miss_latency::total 208860800605 # number of demand (read+write) miss cycles 2202system.cpu1.dcache.overall_miss_latency::cpu1.data 208860800605 # number of overall miss cycles 2203system.cpu1.dcache.overall_miss_latency::total 208860800605 # number of overall miss cycles 2204system.cpu1.dcache.ReadReq_accesses::cpu1.data 80782202 # number of ReadReq accesses(hits+misses) 2205system.cpu1.dcache.ReadReq_accesses::total 80782202 # number of ReadReq accesses(hits+misses) 2206system.cpu1.dcache.WriteReq_accesses::cpu1.data 71006010 # number of WriteReq accesses(hits+misses) 2207system.cpu1.dcache.WriteReq_accesses::total 71006010 # number of WriteReq accesses(hits+misses) 2208system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 823312 # number of SoftPFReq accesses(hits+misses) 2209system.cpu1.dcache.SoftPFReq_accesses::total 823312 # number of SoftPFReq accesses(hits+misses) 2210system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 465174 # number of WriteInvalidateReq accesses(hits+misses) 2211system.cpu1.dcache.WriteInvalidateReq_accesses::total 465174 # number of WriteInvalidateReq accesses(hits+misses) 2212system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1999506 # number of LoadLockedReq accesses(hits+misses) 2213system.cpu1.dcache.LoadLockedReq_accesses::total 1999506 # number of LoadLockedReq accesses(hits+misses) 2214system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1955558 # number of StoreCondReq accesses(hits+misses) 2215system.cpu1.dcache.StoreCondReq_accesses::total 1955558 # number of StoreCondReq accesses(hits+misses) 2216system.cpu1.dcache.demand_accesses::cpu1.data 151788212 # number of demand (read+write) accesses 2217system.cpu1.dcache.demand_accesses::total 151788212 # number of demand (read+write) accesses 2218system.cpu1.dcache.overall_accesses::cpu1.data 152611524 # number of overall (read+write) accesses 2219system.cpu1.dcache.overall_accesses::total 152611524 # number of overall (read+write) accesses 2220system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.075845 # miss rate for ReadReq accesses 2221system.cpu1.dcache.ReadReq_miss_rate::total 0.075845 # miss rate for ReadReq accesses 2222system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.098341 # miss rate for WriteReq accesses 2223system.cpu1.dcache.WriteReq_miss_rate::total 0.098341 # miss rate for WriteReq accesses 2224system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.801073 # miss rate for SoftPFReq accesses 2225system.cpu1.dcache.SoftPFReq_miss_rate::total 0.801073 # miss rate for SoftPFReq accesses 2226system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.914447 # miss rate for WriteInvalidateReq accesses 2227system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.914447 # miss rate for WriteInvalidateReq accesses 2228system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.130321 # miss rate for LoadLockedReq accesses 2229system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.130321 # miss rate for LoadLockedReq accesses 2230system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104396 # miss rate for StoreCondReq accesses 2231system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104396 # miss rate for StoreCondReq accesses 2232system.cpu1.dcache.demand_miss_rate::cpu1.data 0.086369 # miss rate for demand accesses 2233system.cpu1.dcache.demand_miss_rate::total 0.086369 # miss rate for demand accesses 2234system.cpu1.dcache.overall_miss_rate::cpu1.data 0.090224 # miss rate for overall accesses 2235system.cpu1.dcache.overall_miss_rate::total 0.090224 # miss rate for overall accesses 2236system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15105.342855 # average ReadReq miss latency 2237system.cpu1.dcache.ReadReq_avg_miss_latency::total 15105.342855 # average ReadReq miss latency 2238system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16656.776160 # average WriteReq miss latency 2239system.cpu1.dcache.WriteReq_avg_miss_latency::total 16656.776160 # average WriteReq miss latency 2240system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27524.205401 # average WriteInvalidateReq miss latency 2241system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27524.205401 # average WriteInvalidateReq miss latency 2242system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14423.717444 # average LoadLockedReq miss latency 2243system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14423.717444 # average LoadLockedReq miss latency 2244system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21164.860790 # average StoreCondReq miss latency 2245system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21164.860790 # average StoreCondReq miss latency | 2101system.cpu1.rob.rob_reads 1162834468 # The number of ROB reads 2102system.cpu1.rob.rob_writes 1096743807 # The number of ROB writes 2103system.cpu1.timesIdled 924876 # Number of times that the entire CPU went into an idle state and unscheduled itself 2104system.cpu1.idleCycles 16064791 # Total number of cycles that the CPU has spent unscheduled due to idling 2105system.cpu1.quiesceCycles 93951930875 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2106system.cpu1.committedInsts 424719097 # Number of Instructions Simulated 2107system.cpu1.committedOps 500362777 # Number of Ops (including micro ops) Simulated 2108system.cpu1.cpi 1.552088 # CPI: Cycles Per Instruction 2109system.cpu1.cpi_total 1.552088 # CPI: Total CPI of All Threads 2110system.cpu1.ipc 0.644293 # IPC: Instructions Per Cycle 2111system.cpu1.ipc_total 0.644293 # IPC: Total IPC of All Threads 2112system.cpu1.int_regfile_reads 629086185 # number of integer regfile reads 2113system.cpu1.int_regfile_writes 373708704 # number of integer regfile writes 2114system.cpu1.fp_regfile_reads 742781 # number of floating regfile reads 2115system.cpu1.fp_regfile_writes 462024 # number of floating regfile writes 2116system.cpu1.cc_regfile_reads 113147370 # number of cc regfile reads 2117system.cpu1.cc_regfile_writes 113825607 # number of cc regfile writes 2118system.cpu1.misc_regfile_reads 2613251902 # number of misc regfile reads 2119system.cpu1.misc_regfile_writes 14637394 # number of misc regfile writes 2120system.cpu1.dcache.tags.replacements 5151228 # number of replacements 2121system.cpu1.dcache.tags.tagsinuse 427.693854 # Cycle average of tags in use 2122system.cpu1.dcache.tags.total_refs 143143391 # Total number of references to valid blocks. 2123system.cpu1.dcache.tags.sampled_refs 5151740 # Sample count of references to valid blocks. 2124system.cpu1.dcache.tags.avg_refs 27.785445 # Average number of references to valid blocks. 2125system.cpu1.dcache.tags.warmup_cycle 8478589557500 # Cycle when the warmup percentage was hit. 2126system.cpu1.dcache.tags.occ_blocks::cpu1.data 427.693854 # Average occupied blocks per requestor 2127system.cpu1.dcache.tags.occ_percent::cpu1.data 0.835340 # Average percentage of cache occupancy 2128system.cpu1.dcache.tags.occ_percent::total 0.835340 # Average percentage of cache occupancy 2129system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2130system.cpu1.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 2131system.cpu1.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id 2132system.cpu1.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id 2133system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2134system.cpu1.dcache.tags.tag_accesses 318663535 # Number of tag accesses 2135system.cpu1.dcache.tags.data_accesses 318663535 # Number of data accesses 2136system.cpu1.dcache.ReadReq_hits::cpu1.data 75155961 # number of ReadReq hits 2137system.cpu1.dcache.ReadReq_hits::total 75155961 # number of ReadReq hits 2138system.cpu1.dcache.WriteReq_hits::cpu1.data 63737585 # number of WriteReq hits 2139system.cpu1.dcache.WriteReq_hits::total 63737585 # number of WriteReq hits 2140system.cpu1.dcache.SoftPFReq_hits::cpu1.data 169811 # number of SoftPFReq hits 2141system.cpu1.dcache.SoftPFReq_hits::total 169811 # number of SoftPFReq hits 2142system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 58007 # number of WriteInvalidateReq hits 2143system.cpu1.dcache.WriteInvalidateReq_hits::total 58007 # number of WriteInvalidateReq hits 2144system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1657429 # number of LoadLockedReq hits 2145system.cpu1.dcache.LoadLockedReq_hits::total 1657429 # number of LoadLockedReq hits 2146system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1683439 # number of StoreCondReq hits 2147system.cpu1.dcache.StoreCondReq_hits::total 1683439 # number of StoreCondReq hits 2148system.cpu1.dcache.demand_hits::cpu1.data 138893546 # number of demand (read+write) hits 2149system.cpu1.dcache.demand_hits::total 138893546 # number of demand (read+write) hits 2150system.cpu1.dcache.overall_hits::cpu1.data 139063357 # number of overall hits 2151system.cpu1.dcache.overall_hits::total 139063357 # number of overall hits 2152system.cpu1.dcache.ReadReq_misses::cpu1.data 6025315 # number of ReadReq misses 2153system.cpu1.dcache.ReadReq_misses::total 6025315 # number of ReadReq misses 2154system.cpu1.dcache.WriteReq_misses::cpu1.data 6706823 # number of WriteReq misses 2155system.cpu1.dcache.WriteReq_misses::total 6706823 # number of WriteReq misses 2156system.cpu1.dcache.SoftPFReq_misses::cpu1.data 630176 # number of SoftPFReq misses 2157system.cpu1.dcache.SoftPFReq_misses::total 630176 # number of SoftPFReq misses 2158system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 421123 # number of WriteInvalidateReq misses 2159system.cpu1.dcache.WriteInvalidateReq_misses::total 421123 # number of WriteInvalidateReq misses 2160system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 264252 # number of LoadLockedReq misses 2161system.cpu1.dcache.LoadLockedReq_misses::total 264252 # number of LoadLockedReq misses 2162system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195781 # number of StoreCondReq misses 2163system.cpu1.dcache.StoreCondReq_misses::total 195781 # number of StoreCondReq misses 2164system.cpu1.dcache.demand_misses::cpu1.data 12732138 # number of demand (read+write) misses 2165system.cpu1.dcache.demand_misses::total 12732138 # number of demand (read+write) misses 2166system.cpu1.dcache.overall_misses::cpu1.data 13362314 # number of overall misses 2167system.cpu1.dcache.overall_misses::total 13362314 # number of overall misses 2168system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 87326420147 # number of ReadReq miss cycles 2169system.cpu1.dcache.ReadReq_miss_latency::total 87326420147 # number of ReadReq miss cycles 2170system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 117804291686 # number of WriteReq miss cycles 2171system.cpu1.dcache.WriteReq_miss_latency::total 117804291686 # number of WriteReq miss cycles 2172system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 13004978477 # number of WriteInvalidateReq miss cycles 2173system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 13004978477 # number of WriteInvalidateReq miss cycles 2174system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3882326694 # number of LoadLockedReq miss cycles 2175system.cpu1.dcache.LoadLockedReq_miss_latency::total 3882326694 # number of LoadLockedReq miss cycles 2176system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4150746008 # number of StoreCondReq miss cycles 2177system.cpu1.dcache.StoreCondReq_miss_latency::total 4150746008 # number of StoreCondReq miss cycles 2178system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4758000 # number of StoreCondFailReq miss cycles 2179system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4758000 # number of StoreCondFailReq miss cycles 2180system.cpu1.dcache.demand_miss_latency::cpu1.data 205130711833 # number of demand (read+write) miss cycles 2181system.cpu1.dcache.demand_miss_latency::total 205130711833 # number of demand (read+write) miss cycles 2182system.cpu1.dcache.overall_miss_latency::cpu1.data 205130711833 # number of overall miss cycles 2183system.cpu1.dcache.overall_miss_latency::total 205130711833 # number of overall miss cycles 2184system.cpu1.dcache.ReadReq_accesses::cpu1.data 81181276 # number of ReadReq accesses(hits+misses) 2185system.cpu1.dcache.ReadReq_accesses::total 81181276 # number of ReadReq accesses(hits+misses) 2186system.cpu1.dcache.WriteReq_accesses::cpu1.data 70444408 # number of WriteReq accesses(hits+misses) 2187system.cpu1.dcache.WriteReq_accesses::total 70444408 # number of WriteReq accesses(hits+misses) 2188system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 799987 # number of SoftPFReq accesses(hits+misses) 2189system.cpu1.dcache.SoftPFReq_accesses::total 799987 # number of SoftPFReq accesses(hits+misses) 2190system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 479130 # number of WriteInvalidateReq accesses(hits+misses) 2191system.cpu1.dcache.WriteInvalidateReq_accesses::total 479130 # number of WriteInvalidateReq accesses(hits+misses) 2192system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1921681 # number of LoadLockedReq accesses(hits+misses) 2193system.cpu1.dcache.LoadLockedReq_accesses::total 1921681 # number of LoadLockedReq accesses(hits+misses) 2194system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1879220 # number of StoreCondReq accesses(hits+misses) 2195system.cpu1.dcache.StoreCondReq_accesses::total 1879220 # number of StoreCondReq accesses(hits+misses) 2196system.cpu1.dcache.demand_accesses::cpu1.data 151625684 # number of demand (read+write) accesses 2197system.cpu1.dcache.demand_accesses::total 151625684 # number of demand (read+write) accesses 2198system.cpu1.dcache.overall_accesses::cpu1.data 152425671 # number of overall (read+write) accesses 2199system.cpu1.dcache.overall_accesses::total 152425671 # number of overall (read+write) accesses 2200system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074221 # miss rate for ReadReq accesses 2201system.cpu1.dcache.ReadReq_miss_rate::total 0.074221 # miss rate for ReadReq accesses 2202system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.095207 # miss rate for WriteReq accesses 2203system.cpu1.dcache.WriteReq_miss_rate::total 0.095207 # miss rate for WriteReq accesses 2204system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.787733 # miss rate for SoftPFReq accesses 2205system.cpu1.dcache.SoftPFReq_miss_rate::total 0.787733 # miss rate for SoftPFReq accesses 2206system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.878933 # miss rate for WriteInvalidateReq accesses 2207system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.878933 # miss rate for WriteInvalidateReq accesses 2208system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137511 # miss rate for LoadLockedReq accesses 2209system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137511 # miss rate for LoadLockedReq accesses 2210system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104182 # miss rate for StoreCondReq accesses 2211system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104182 # miss rate for StoreCondReq accesses 2212system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083971 # miss rate for demand accesses 2213system.cpu1.dcache.demand_miss_rate::total 0.083971 # miss rate for demand accesses 2214system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087664 # miss rate for overall accesses 2215system.cpu1.dcache.overall_miss_rate::total 0.087664 # miss rate for overall accesses 2216system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14493.253904 # average ReadReq miss latency 2217system.cpu1.dcache.ReadReq_avg_miss_latency::total 14493.253904 # average ReadReq miss latency 2218system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17564.842801 # average WriteReq miss latency 2219system.cpu1.dcache.WriteReq_avg_miss_latency::total 17564.842801 # average WriteReq miss latency 2220system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 30881.662785 # average WriteInvalidateReq miss latency 2221system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 30881.662785 # average WriteInvalidateReq miss latency 2222system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14691.758980 # average LoadLockedReq miss latency 2223system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14691.758980 # average LoadLockedReq miss latency 2224system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21200.964384 # average StoreCondReq miss latency 2225system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21200.964384 # average StoreCondReq miss latency |
| 2246system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2247system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 2226system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2227system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 2248system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15931.702839 # average overall miss latency 2249system.cpu1.dcache.demand_avg_miss_latency::total 15931.702839 # average overall miss latency 2250system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15168.592941 # average overall miss latency 2251system.cpu1.dcache.overall_avg_miss_latency::total 15168.592941 # average overall miss latency 2252system.cpu1.dcache.blocked_cycles::no_mshrs 2855420 # number of cycles access was blocked 2253system.cpu1.dcache.blocked_cycles::no_targets 17544431 # number of cycles access was blocked 2254system.cpu1.dcache.blocked::no_mshrs 337066 # number of cycles access was blocked 2255system.cpu1.dcache.blocked::no_targets 700468 # number of cycles access was blocked 2256system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.471397 # average number of cycles each access was blocked 2257system.cpu1.dcache.avg_blocked_cycles::no_targets 25.046727 # average number of cycles each access was blocked | 2228system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16111.254200 # average overall miss latency 2229system.cpu1.dcache.demand_avg_miss_latency::total 16111.254200 # average overall miss latency 2230system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15351.436273 # average overall miss latency 2231system.cpu1.dcache.overall_avg_miss_latency::total 15351.436273 # average overall miss latency 2232system.cpu1.dcache.blocked_cycles::no_mshrs 3328310 # number of cycles access was blocked 2233system.cpu1.dcache.blocked_cycles::no_targets 18296285 # number of cycles access was blocked 2234system.cpu1.dcache.blocked::no_mshrs 353421 # number of cycles access was blocked 2235system.cpu1.dcache.blocked::no_targets 675053 # number of cycles access was blocked 2236system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.417409 # average number of cycles each access was blocked 2237system.cpu1.dcache.avg_blocked_cycles::no_targets 27.103479 # average number of cycles each access was blocked |
| 2258system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2259system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 2238system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2239system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 2260system.cpu1.dcache.writebacks::writebacks 3392584 # number of writebacks 2261system.cpu1.dcache.writebacks::total 3392584 # number of writebacks 2262system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3127909 # number of ReadReq MSHR hits 2263system.cpu1.dcache.ReadReq_mshr_hits::total 3127909 # number of ReadReq MSHR hits 2264system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5647115 # number of WriteReq MSHR hits 2265system.cpu1.dcache.WriteReq_mshr_hits::total 5647115 # number of WriteReq MSHR hits 2266system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3296 # number of WriteInvalidateReq MSHR hits 2267system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3296 # number of WriteInvalidateReq MSHR hits 2268system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 132105 # number of LoadLockedReq MSHR hits 2269system.cpu1.dcache.LoadLockedReq_mshr_hits::total 132105 # number of LoadLockedReq MSHR hits 2270system.cpu1.dcache.demand_mshr_hits::cpu1.data 8775024 # number of demand (read+write) MSHR hits 2271system.cpu1.dcache.demand_mshr_hits::total 8775024 # number of demand (read+write) MSHR hits 2272system.cpu1.dcache.overall_mshr_hits::cpu1.data 8775024 # number of overall MSHR hits 2273system.cpu1.dcache.overall_mshr_hits::total 8775024 # number of overall MSHR hits 2274system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2999030 # number of ReadReq MSHR misses 2275system.cpu1.dcache.ReadReq_mshr_misses::total 2999030 # number of ReadReq MSHR misses 2276system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1335706 # number of WriteReq MSHR misses 2277system.cpu1.dcache.WriteReq_mshr_misses::total 1335706 # number of WriteReq MSHR misses 2278system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 659449 # number of SoftPFReq MSHR misses 2279system.cpu1.dcache.SoftPFReq_mshr_misses::total 659449 # number of SoftPFReq MSHR misses 2280system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 422081 # number of WriteInvalidateReq MSHR misses 2281system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 422081 # number of WriteInvalidateReq MSHR misses 2282system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 128473 # number of LoadLockedReq MSHR misses 2283system.cpu1.dcache.LoadLockedReq_mshr_misses::total 128473 # number of LoadLockedReq MSHR misses 2284system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 204145 # number of StoreCondReq MSHR misses 2285system.cpu1.dcache.StoreCondReq_mshr_misses::total 204145 # number of StoreCondReq MSHR misses 2286system.cpu1.dcache.demand_mshr_misses::cpu1.data 4334736 # number of demand (read+write) MSHR misses 2287system.cpu1.dcache.demand_mshr_misses::total 4334736 # number of demand (read+write) MSHR misses 2288system.cpu1.dcache.overall_mshr_misses::cpu1.data 4994185 # number of overall MSHR misses 2289system.cpu1.dcache.overall_mshr_misses::total 4994185 # number of overall MSHR misses 2290system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38225367292 # number of ReadReq MSHR miss cycles 2291system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38225367292 # number of ReadReq MSHR miss cycles 2292system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21845579142 # number of WriteReq MSHR miss cycles 2293system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21845579142 # number of WriteReq MSHR miss cycles 2294system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15240654080 # number of SoftPFReq MSHR miss cycles 2295system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15240654080 # number of SoftPFReq MSHR miss cycles 2296system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 10753431338 # number of WriteInvalidateReq MSHR miss cycles 2297system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 10753431338 # number of WriteInvalidateReq MSHR miss cycles 2298system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1629520255 # number of LoadLockedReq MSHR miss cycles 2299system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1629520255 # number of LoadLockedReq MSHR miss cycles 2300system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3904363340 # number of StoreCondReq MSHR miss cycles 2301system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3904363340 # number of StoreCondReq MSHR miss cycles 2302system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3325000 # number of StoreCondFailReq MSHR miss cycles 2303system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3325000 # number of StoreCondFailReq MSHR miss cycles 2304system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 60070946434 # number of demand (read+write) MSHR miss cycles 2305system.cpu1.dcache.demand_mshr_miss_latency::total 60070946434 # number of demand (read+write) MSHR miss cycles 2306system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 75311600514 # number of overall MSHR miss cycles 2307system.cpu1.dcache.overall_mshr_miss_latency::total 75311600514 # number of overall MSHR miss cycles 2308system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 796916503 # number of ReadReq MSHR uncacheable cycles 2309system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 796916503 # number of ReadReq MSHR uncacheable cycles 2310system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 897774501 # number of WriteReq MSHR uncacheable cycles 2311system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 897774501 # number of WriteReq MSHR uncacheable cycles 2312system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1694691004 # number of overall MSHR uncacheable cycles 2313system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1694691004 # number of overall MSHR uncacheable cycles 2314system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037125 # mshr miss rate for ReadReq accesses 2315system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037125 # mshr miss rate for ReadReq accesses 2316system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018811 # mshr miss rate for WriteReq accesses 2317system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018811 # mshr miss rate for WriteReq accesses 2318system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.800971 # mshr miss rate for SoftPFReq accesses 2319system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.800971 # mshr miss rate for SoftPFReq accesses 2320system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.907362 # mshr miss rate for WriteInvalidateReq accesses 2321system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.907362 # mshr miss rate for WriteInvalidateReq accesses 2322system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064252 # mshr miss rate for LoadLockedReq accesses 2323system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064252 # mshr miss rate for LoadLockedReq accesses 2324system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104392 # mshr miss rate for StoreCondReq accesses 2325system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104392 # mshr miss rate for StoreCondReq accesses 2326system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028558 # mshr miss rate for demand accesses 2327system.cpu1.dcache.demand_mshr_miss_rate::total 0.028558 # mshr miss rate for demand accesses 2328system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032725 # mshr miss rate for overall accesses 2329system.cpu1.dcache.overall_mshr_miss_rate::total 0.032725 # mshr miss rate for overall accesses 2330system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12745.910275 # average ReadReq mshr miss latency 2331system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12745.910275 # average ReadReq mshr miss latency 2332system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16355.080491 # average WriteReq mshr miss latency 2333system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16355.080491 # average WriteReq mshr miss latency 2334system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23111.194467 # average SoftPFReq mshr miss latency 2335system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23111.194467 # average SoftPFReq mshr miss latency 2336system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25477.174613 # average WriteInvalidateReq mshr miss latency 2337system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25477.174613 # average WriteInvalidateReq mshr miss latency 2338system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12683.756548 # average LoadLockedReq mshr miss latency 2339system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12683.756548 # average LoadLockedReq mshr miss latency 2340system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19125.441916 # average StoreCondReq mshr miss latency 2341system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19125.441916 # average StoreCondReq mshr miss latency | 2240system.cpu1.dcache.writebacks::writebacks 3264704 # number of writebacks 2241system.cpu1.dcache.writebacks::total 3264704 # number of writebacks 2242system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3035971 # number of ReadReq MSHR hits 2243system.cpu1.dcache.ReadReq_mshr_hits::total 3035971 # number of ReadReq MSHR hits 2244system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5416489 # number of WriteReq MSHR hits 2245system.cpu1.dcache.WriteReq_mshr_hits::total 5416489 # number of WriteReq MSHR hits 2246system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3258 # number of WriteInvalidateReq MSHR hits 2247system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3258 # number of WriteInvalidateReq MSHR hits 2248system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 136728 # number of LoadLockedReq MSHR hits 2249system.cpu1.dcache.LoadLockedReq_mshr_hits::total 136728 # number of LoadLockedReq MSHR hits 2250system.cpu1.dcache.demand_mshr_hits::cpu1.data 8452460 # number of demand (read+write) MSHR hits 2251system.cpu1.dcache.demand_mshr_hits::total 8452460 # number of demand (read+write) MSHR hits 2252system.cpu1.dcache.overall_mshr_hits::cpu1.data 8452460 # number of overall MSHR hits 2253system.cpu1.dcache.overall_mshr_hits::total 8452460 # number of overall MSHR hits 2254system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2989344 # number of ReadReq MSHR misses 2255system.cpu1.dcache.ReadReq_mshr_misses::total 2989344 # number of ReadReq MSHR misses 2256system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1290334 # number of WriteReq MSHR misses 2257system.cpu1.dcache.WriteReq_mshr_misses::total 1290334 # number of WriteReq MSHR misses 2258system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 630111 # number of SoftPFReq MSHR misses 2259system.cpu1.dcache.SoftPFReq_mshr_misses::total 630111 # number of SoftPFReq MSHR misses 2260system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 417865 # number of WriteInvalidateReq MSHR misses 2261system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 417865 # number of WriteInvalidateReq MSHR misses 2262system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 127524 # number of LoadLockedReq MSHR misses 2263system.cpu1.dcache.LoadLockedReq_mshr_misses::total 127524 # number of LoadLockedReq MSHR misses 2264system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195781 # number of StoreCondReq MSHR misses 2265system.cpu1.dcache.StoreCondReq_mshr_misses::total 195781 # number of StoreCondReq MSHR misses 2266system.cpu1.dcache.demand_mshr_misses::cpu1.data 4279678 # number of demand (read+write) MSHR misses 2267system.cpu1.dcache.demand_mshr_misses::total 4279678 # number of demand (read+write) MSHR misses 2268system.cpu1.dcache.overall_mshr_misses::cpu1.data 4909789 # number of overall MSHR misses 2269system.cpu1.dcache.overall_mshr_misses::total 4909789 # number of overall MSHR misses 2270system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39357294362 # number of ReadReq MSHR miss cycles 2271system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39357294362 # number of ReadReq MSHR miss cycles 2272system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22683763866 # number of WriteReq MSHR miss cycles 2273system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22683763866 # number of WriteReq MSHR miss cycles 2274system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12612160940 # number of SoftPFReq MSHR miss cycles 2275system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12612160940 # number of SoftPFReq MSHR miss cycles 2276system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12265252837 # number of WriteInvalidateReq MSHR miss cycles 2277system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 12265252837 # number of WriteInvalidateReq MSHR miss cycles 2278system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1674709739 # number of LoadLockedReq MSHR miss cycles 2279system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1674709739 # number of LoadLockedReq MSHR miss cycles 2280system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3848237992 # number of StoreCondReq MSHR miss cycles 2281system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3848237992 # number of StoreCondReq MSHR miss cycles 2282system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4609500 # number of StoreCondFailReq MSHR miss cycles 2283system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4609500 # number of StoreCondFailReq MSHR miss cycles 2284system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62041058228 # number of demand (read+write) MSHR miss cycles 2285system.cpu1.dcache.demand_mshr_miss_latency::total 62041058228 # number of demand (read+write) MSHR miss cycles 2286system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 74653219168 # number of overall MSHR miss cycles 2287system.cpu1.dcache.overall_mshr_miss_latency::total 74653219168 # number of overall MSHR miss cycles 2288system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 688989750 # number of ReadReq MSHR uncacheable cycles 2289system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 688989750 # number of ReadReq MSHR uncacheable cycles 2290system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 785556502 # number of WriteReq MSHR uncacheable cycles 2291system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 785556502 # number of WriteReq MSHR uncacheable cycles 2292system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1474546252 # number of overall MSHR uncacheable cycles 2293system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1474546252 # number of overall MSHR uncacheable cycles 2294system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036823 # mshr miss rate for ReadReq accesses 2295system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036823 # mshr miss rate for ReadReq accesses 2296system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018317 # mshr miss rate for WriteReq accesses 2297system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018317 # mshr miss rate for WriteReq accesses 2298system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.787652 # mshr miss rate for SoftPFReq accesses 2299system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.787652 # mshr miss rate for SoftPFReq accesses 2300system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.872133 # mshr miss rate for WriteInvalidateReq accesses 2301system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.872133 # mshr miss rate for WriteInvalidateReq accesses 2302system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066361 # mshr miss rate for LoadLockedReq accesses 2303system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066361 # mshr miss rate for LoadLockedReq accesses 2304system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104182 # mshr miss rate for StoreCondReq accesses 2305system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104182 # mshr miss rate for StoreCondReq accesses 2306system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028225 # mshr miss rate for demand accesses 2307system.cpu1.dcache.demand_mshr_miss_rate::total 0.028225 # mshr miss rate for demand accesses 2308system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032211 # mshr miss rate for overall accesses 2309system.cpu1.dcache.overall_mshr_miss_rate::total 0.032211 # mshr miss rate for overall accesses 2310system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13165.863267 # average ReadReq mshr miss latency 2311system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13165.863267 # average ReadReq mshr miss latency 2312system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17579.761415 # average WriteReq mshr miss latency 2313system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17579.761415 # average WriteReq mshr miss latency 2314system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20015.776490 # average SoftPFReq mshr miss latency 2315system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20015.776490 # average SoftPFReq mshr miss latency 2316system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 29352.189911 # average WriteInvalidateReq mshr miss latency 2317system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29352.189911 # average WriteInvalidateReq mshr miss latency 2318system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13132.506344 # average LoadLockedReq mshr miss latency 2319system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13132.506344 # average LoadLockedReq mshr miss latency 2320system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19655.829687 # average StoreCondReq mshr miss latency 2321system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19655.829687 # average StoreCondReq mshr miss latency |
| 2342system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2343system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 2322system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2323system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 2344system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13858.040359 # average overall mshr miss latency 2345system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13858.040359 # average overall mshr miss latency 2346system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15079.857978 # average overall mshr miss latency 2347system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15079.857978 # average overall mshr miss latency | 2324system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14496.664989 # average overall mshr miss latency 2325system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14496.664989 # average overall mshr miss latency 2326system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15204.975034 # average overall mshr miss latency 2327system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15204.975034 # average overall mshr miss latency |
| 2348system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2349system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2350system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2351system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2352system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2353system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2354system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 2328system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2329system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2330system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2331system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2332system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2333system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2334system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2355system.cpu1.icache.tags.replacements 5522406 # number of replacements 2356system.cpu1.icache.tags.tagsinuse 501.856310 # Cycle average of tags in use 2357system.cpu1.icache.tags.total_refs 190094169 # Total number of references to valid blocks. 2358system.cpu1.icache.tags.sampled_refs 5522918 # Sample count of references to valid blocks. 2359system.cpu1.icache.tags.avg_refs 34.419155 # Average number of references to valid blocks. 2360system.cpu1.icache.tags.warmup_cycle 8518418347000 # Cycle when the warmup percentage was hit. 2361system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.856310 # Average occupied blocks per requestor 2362system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980188 # Average percentage of cache occupancy 2363system.cpu1.icache.tags.occ_percent::total 0.980188 # Average percentage of cache occupancy | 2335system.cpu1.icache.tags.replacements 5667991 # number of replacements 2336system.cpu1.icache.tags.tagsinuse 501.848972 # Cycle average of tags in use 2337system.cpu1.icache.tags.total_refs 190104103 # Total number of references to valid blocks. 2338system.cpu1.icache.tags.sampled_refs 5668503 # Sample count of references to valid blocks. 2339system.cpu1.icache.tags.avg_refs 33.536915 # Average number of references to valid blocks. 2340system.cpu1.icache.tags.warmup_cycle 8518313865250 # Cycle when the warmup percentage was hit. 2341system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.848972 # Average occupied blocks per requestor 2342system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980174 # Average percentage of cache occupancy 2343system.cpu1.icache.tags.occ_percent::total 0.980174 # Average percentage of cache occupancy |
| 2364system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 2344system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 2365system.cpu1.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id 2366system.cpu1.icache.tags.age_task_id_blocks_1024::1 335 # Occupied blocks per task id 2367system.cpu1.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id | 2345system.cpu1.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id 2346system.cpu1.icache.tags.age_task_id_blocks_1024::1 347 # Occupied blocks per task id 2347system.cpu1.icache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id |
| 2368system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 2348system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 2369system.cpu1.icache.tags.tag_accesses 397333844 # Number of tag accesses 2370system.cpu1.icache.tags.data_accesses 397333844 # Number of data accesses 2371system.cpu1.icache.ReadReq_hits::cpu1.inst 190094169 # number of ReadReq hits 2372system.cpu1.icache.ReadReq_hits::total 190094169 # number of ReadReq hits 2373system.cpu1.icache.demand_hits::cpu1.inst 190094169 # number of demand (read+write) hits 2374system.cpu1.icache.demand_hits::total 190094169 # number of demand (read+write) hits 2375system.cpu1.icache.overall_hits::cpu1.inst 190094169 # number of overall hits 2376system.cpu1.icache.overall_hits::total 190094169 # number of overall hits 2377system.cpu1.icache.ReadReq_misses::cpu1.inst 5811281 # number of ReadReq misses 2378system.cpu1.icache.ReadReq_misses::total 5811281 # number of ReadReq misses 2379system.cpu1.icache.demand_misses::cpu1.inst 5811281 # number of demand (read+write) misses 2380system.cpu1.icache.demand_misses::total 5811281 # number of demand (read+write) misses 2381system.cpu1.icache.overall_misses::cpu1.inst 5811281 # number of overall misses 2382system.cpu1.icache.overall_misses::total 5811281 # number of overall misses 2383system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 61520167992 # number of ReadReq miss cycles 2384system.cpu1.icache.ReadReq_miss_latency::total 61520167992 # number of ReadReq miss cycles 2385system.cpu1.icache.demand_miss_latency::cpu1.inst 61520167992 # number of demand (read+write) miss cycles 2386system.cpu1.icache.demand_miss_latency::total 61520167992 # number of demand (read+write) miss cycles 2387system.cpu1.icache.overall_miss_latency::cpu1.inst 61520167992 # number of overall miss cycles 2388system.cpu1.icache.overall_miss_latency::total 61520167992 # number of overall miss cycles 2389system.cpu1.icache.ReadReq_accesses::cpu1.inst 195905450 # number of ReadReq accesses(hits+misses) 2390system.cpu1.icache.ReadReq_accesses::total 195905450 # number of ReadReq accesses(hits+misses) 2391system.cpu1.icache.demand_accesses::cpu1.inst 195905450 # number of demand (read+write) accesses 2392system.cpu1.icache.demand_accesses::total 195905450 # number of demand (read+write) accesses 2393system.cpu1.icache.overall_accesses::cpu1.inst 195905450 # number of overall (read+write) accesses 2394system.cpu1.icache.overall_accesses::total 195905450 # number of overall (read+write) accesses 2395system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029664 # miss rate for ReadReq accesses 2396system.cpu1.icache.ReadReq_miss_rate::total 0.029664 # miss rate for ReadReq accesses 2397system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029664 # miss rate for demand accesses 2398system.cpu1.icache.demand_miss_rate::total 0.029664 # miss rate for demand accesses 2399system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029664 # miss rate for overall accesses 2400system.cpu1.icache.overall_miss_rate::total 0.029664 # miss rate for overall accesses 2401system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10586.335094 # average ReadReq miss latency 2402system.cpu1.icache.ReadReq_avg_miss_latency::total 10586.335094 # average ReadReq miss latency 2403system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10586.335094 # average overall miss latency 2404system.cpu1.icache.demand_avg_miss_latency::total 10586.335094 # average overall miss latency 2405system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10586.335094 # average overall miss latency 2406system.cpu1.icache.overall_avg_miss_latency::total 10586.335094 # average overall miss latency 2407system.cpu1.icache.blocked_cycles::no_mshrs 7857995 # number of cycles access was blocked 2408system.cpu1.icache.blocked_cycles::no_targets 39 # number of cycles access was blocked 2409system.cpu1.icache.blocked::no_mshrs 642168 # number of cycles access was blocked | 2349system.cpu1.icache.tags.tag_accesses 397835903 # Number of tag accesses 2350system.cpu1.icache.tags.data_accesses 397835903 # Number of data accesses 2351system.cpu1.icache.ReadReq_hits::cpu1.inst 190104103 # number of ReadReq hits 2352system.cpu1.icache.ReadReq_hits::total 190104103 # number of ReadReq hits 2353system.cpu1.icache.demand_hits::cpu1.inst 190104103 # number of demand (read+write) hits 2354system.cpu1.icache.demand_hits::total 190104103 # number of demand (read+write) hits 2355system.cpu1.icache.overall_hits::cpu1.inst 190104103 # number of overall hits 2356system.cpu1.icache.overall_hits::total 190104103 # number of overall hits 2357system.cpu1.icache.ReadReq_misses::cpu1.inst 5979587 # number of ReadReq misses 2358system.cpu1.icache.ReadReq_misses::total 5979587 # number of ReadReq misses 2359system.cpu1.icache.demand_misses::cpu1.inst 5979587 # number of demand (read+write) misses 2360system.cpu1.icache.demand_misses::total 5979587 # number of demand (read+write) misses 2361system.cpu1.icache.overall_misses::cpu1.inst 5979587 # number of overall misses 2362system.cpu1.icache.overall_misses::total 5979587 # number of overall misses 2363system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 61433525378 # number of ReadReq miss cycles 2364system.cpu1.icache.ReadReq_miss_latency::total 61433525378 # number of ReadReq miss cycles 2365system.cpu1.icache.demand_miss_latency::cpu1.inst 61433525378 # number of demand (read+write) miss cycles 2366system.cpu1.icache.demand_miss_latency::total 61433525378 # number of demand (read+write) miss cycles 2367system.cpu1.icache.overall_miss_latency::cpu1.inst 61433525378 # number of overall miss cycles 2368system.cpu1.icache.overall_miss_latency::total 61433525378 # number of overall miss cycles 2369system.cpu1.icache.ReadReq_accesses::cpu1.inst 196083690 # number of ReadReq accesses(hits+misses) 2370system.cpu1.icache.ReadReq_accesses::total 196083690 # number of ReadReq accesses(hits+misses) 2371system.cpu1.icache.demand_accesses::cpu1.inst 196083690 # number of demand (read+write) accesses 2372system.cpu1.icache.demand_accesses::total 196083690 # number of demand (read+write) accesses 2373system.cpu1.icache.overall_accesses::cpu1.inst 196083690 # number of overall (read+write) accesses 2374system.cpu1.icache.overall_accesses::total 196083690 # number of overall (read+write) accesses 2375system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030495 # miss rate for ReadReq accesses 2376system.cpu1.icache.ReadReq_miss_rate::total 0.030495 # miss rate for ReadReq accesses 2377system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030495 # miss rate for demand accesses 2378system.cpu1.icache.demand_miss_rate::total 0.030495 # miss rate for demand accesses 2379system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030495 # miss rate for overall accesses 2380system.cpu1.icache.overall_miss_rate::total 0.030495 # miss rate for overall accesses 2381system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10273.874329 # average ReadReq miss latency 2382system.cpu1.icache.ReadReq_avg_miss_latency::total 10273.874329 # average ReadReq miss latency 2383system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10273.874329 # average overall miss latency 2384system.cpu1.icache.demand_avg_miss_latency::total 10273.874329 # average overall miss latency 2385system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10273.874329 # average overall miss latency 2386system.cpu1.icache.overall_avg_miss_latency::total 10273.874329 # average overall miss latency 2387system.cpu1.icache.blocked_cycles::no_mshrs 8139519 # number of cycles access was blocked 2388system.cpu1.icache.blocked_cycles::no_targets 7 # number of cycles access was blocked 2389system.cpu1.icache.blocked::no_mshrs 675212 # number of cycles access was blocked |
| 2410system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked | 2390system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked |
| 2411system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.236665 # average number of cycles each access was blocked 2412system.cpu1.icache.avg_blocked_cycles::no_targets 39 # average number of cycles each access was blocked | 2391system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.054761 # average number of cycles each access was blocked 2392system.cpu1.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked |
| 2413system.cpu1.icache.fast_writes 0 # number of fast writes performed 2414system.cpu1.icache.cache_copies 0 # number of cache copies performed | 2393system.cpu1.icache.fast_writes 0 # number of fast writes performed 2394system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 2415system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 288337 # number of ReadReq MSHR hits 2416system.cpu1.icache.ReadReq_mshr_hits::total 288337 # number of ReadReq MSHR hits 2417system.cpu1.icache.demand_mshr_hits::cpu1.inst 288337 # number of demand (read+write) MSHR hits 2418system.cpu1.icache.demand_mshr_hits::total 288337 # number of demand (read+write) MSHR hits 2419system.cpu1.icache.overall_mshr_hits::cpu1.inst 288337 # number of overall MSHR hits 2420system.cpu1.icache.overall_mshr_hits::total 288337 # number of overall MSHR hits 2421system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5522944 # number of ReadReq MSHR misses 2422system.cpu1.icache.ReadReq_mshr_misses::total 5522944 # number of ReadReq MSHR misses 2423system.cpu1.icache.demand_mshr_misses::cpu1.inst 5522944 # number of demand (read+write) MSHR misses 2424system.cpu1.icache.demand_mshr_misses::total 5522944 # number of demand (read+write) MSHR misses 2425system.cpu1.icache.overall_mshr_misses::cpu1.inst 5522944 # number of overall MSHR misses 2426system.cpu1.icache.overall_mshr_misses::total 5522944 # number of overall MSHR misses 2427system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 50254087338 # number of ReadReq MSHR miss cycles 2428system.cpu1.icache.ReadReq_mshr_miss_latency::total 50254087338 # number of ReadReq MSHR miss cycles 2429system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 50254087338 # number of demand (read+write) MSHR miss cycles 2430system.cpu1.icache.demand_mshr_miss_latency::total 50254087338 # number of demand (read+write) MSHR miss cycles 2431system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 50254087338 # number of overall MSHR miss cycles 2432system.cpu1.icache.overall_mshr_miss_latency::total 50254087338 # number of overall MSHR miss cycles 2433system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5802498 # number of ReadReq MSHR uncacheable cycles 2434system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5802498 # number of ReadReq MSHR uncacheable cycles 2435system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5802498 # number of overall MSHR uncacheable cycles 2436system.cpu1.icache.overall_mshr_uncacheable_latency::total 5802498 # number of overall MSHR uncacheable cycles 2437system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028192 # mshr miss rate for ReadReq accesses 2438system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028192 # mshr miss rate for ReadReq accesses 2439system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028192 # mshr miss rate for demand accesses 2440system.cpu1.icache.demand_mshr_miss_rate::total 0.028192 # mshr miss rate for demand accesses 2441system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028192 # mshr miss rate for overall accesses 2442system.cpu1.icache.overall_mshr_miss_rate::total 0.028192 # mshr miss rate for overall accesses 2443system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9099.148450 # average ReadReq mshr miss latency 2444system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9099.148450 # average ReadReq mshr miss latency 2445system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9099.148450 # average overall mshr miss latency 2446system.cpu1.icache.demand_avg_mshr_miss_latency::total 9099.148450 # average overall mshr miss latency 2447system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9099.148450 # average overall mshr miss latency 2448system.cpu1.icache.overall_avg_mshr_miss_latency::total 9099.148450 # average overall mshr miss latency | 2395system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 311064 # number of ReadReq MSHR hits 2396system.cpu1.icache.ReadReq_mshr_hits::total 311064 # number of ReadReq MSHR hits 2397system.cpu1.icache.demand_mshr_hits::cpu1.inst 311064 # number of demand (read+write) MSHR hits 2398system.cpu1.icache.demand_mshr_hits::total 311064 # number of demand (read+write) MSHR hits 2399system.cpu1.icache.overall_mshr_hits::cpu1.inst 311064 # number of overall MSHR hits 2400system.cpu1.icache.overall_mshr_hits::total 311064 # number of overall MSHR hits 2401system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5668523 # number of ReadReq MSHR misses 2402system.cpu1.icache.ReadReq_mshr_misses::total 5668523 # number of ReadReq MSHR misses 2403system.cpu1.icache.demand_mshr_misses::cpu1.inst 5668523 # number of demand (read+write) MSHR misses 2404system.cpu1.icache.demand_mshr_misses::total 5668523 # number of demand (read+write) MSHR misses 2405system.cpu1.icache.overall_mshr_misses::cpu1.inst 5668523 # number of overall MSHR misses 2406system.cpu1.icache.overall_mshr_misses::total 5668523 # number of overall MSHR misses 2407system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 52921398555 # number of ReadReq MSHR miss cycles 2408system.cpu1.icache.ReadReq_mshr_miss_latency::total 52921398555 # number of ReadReq MSHR miss cycles 2409system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 52921398555 # number of demand (read+write) MSHR miss cycles 2410system.cpu1.icache.demand_mshr_miss_latency::total 52921398555 # number of demand (read+write) MSHR miss cycles 2411system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 52921398555 # number of overall MSHR miss cycles 2412system.cpu1.icache.overall_mshr_miss_latency::total 52921398555 # number of overall MSHR miss cycles 2413system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6131248 # number of ReadReq MSHR uncacheable cycles 2414system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6131248 # number of ReadReq MSHR uncacheable cycles 2415system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6131248 # number of overall MSHR uncacheable cycles 2416system.cpu1.icache.overall_mshr_uncacheable_latency::total 6131248 # number of overall MSHR uncacheable cycles 2417system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028909 # mshr miss rate for ReadReq accesses 2418system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028909 # mshr miss rate for ReadReq accesses 2419system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028909 # mshr miss rate for demand accesses 2420system.cpu1.icache.demand_mshr_miss_rate::total 0.028909 # mshr miss rate for demand accesses 2421system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028909 # mshr miss rate for overall accesses 2422system.cpu1.icache.overall_mshr_miss_rate::total 0.028909 # mshr miss rate for overall accesses 2423system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9336.011966 # average ReadReq mshr miss latency 2424system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9336.011966 # average ReadReq mshr miss latency 2425system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9336.011966 # average overall mshr miss latency 2426system.cpu1.icache.demand_avg_mshr_miss_latency::total 9336.011966 # average overall mshr miss latency 2427system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9336.011966 # average overall mshr miss latency 2428system.cpu1.icache.overall_avg_mshr_miss_latency::total 9336.011966 # average overall mshr miss latency |
| 2449system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2450system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2451system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2452system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2453system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 2429system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2430system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2431system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2432system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2433system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2454system.cpu1.l2cache.prefetcher.num_hwpf_issued 7021877 # number of hwpf issued 2455system.cpu1.l2cache.prefetcher.pfIdentified 7194867 # number of prefetch candidates identified 2456system.cpu1.l2cache.prefetcher.pfBufferHit 149461 # number of redundant prefetches already in prefetch queue | 2434system.cpu1.l2cache.prefetcher.num_hwpf_issued 6924956 # number of hwpf issued 2435system.cpu1.l2cache.prefetcher.pfIdentified 7115948 # number of prefetch candidates identified 2436system.cpu1.l2cache.prefetcher.pfBufferHit 165163 # number of redundant prefetches already in prefetch queue |
| 2457system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2458system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 2437system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2438system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 2459system.cpu1.l2cache.prefetcher.pfSpanPage 884477 # number of prefetches not generated due to page crossing 2460system.cpu1.l2cache.tags.replacements 2159012 # number of replacements 2461system.cpu1.l2cache.tags.tagsinuse 13531.891931 # Cycle average of tags in use 2462system.cpu1.l2cache.tags.total_refs 11463233 # Total number of references to valid blocks. 2463system.cpu1.l2cache.tags.sampled_refs 2175036 # Sample count of references to valid blocks. 2464system.cpu1.l2cache.tags.avg_refs 5.270365 # Average number of references to valid blocks. 2465system.cpu1.l2cache.tags.warmup_cycle 9606894527000 # Cycle when the warmup percentage was hit. 2466system.cpu1.l2cache.tags.occ_blocks::writebacks 5515.011217 # Average occupied blocks per requestor 2467system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 81.352016 # Average occupied blocks per requestor 2468system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 87.650961 # Average occupied blocks per requestor 2469system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3854.550779 # Average occupied blocks per requestor 2470system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3125.340880 # Average occupied blocks per requestor 2471system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 867.986079 # Average occupied blocks per requestor 2472system.cpu1.l2cache.tags.occ_percent::writebacks 0.336610 # Average percentage of cache occupancy 2473system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004965 # Average percentage of cache occupancy 2474system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005350 # Average percentage of cache occupancy 2475system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.235263 # Average percentage of cache occupancy 2476system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.190756 # Average percentage of cache occupancy 2477system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.052978 # Average percentage of cache occupancy 2478system.cpu1.l2cache.tags.occ_percent::total 0.825921 # Average percentage of cache occupancy 2479system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1495 # Occupied blocks per task id 2480system.cpu1.l2cache.tags.occ_task_id_blocks::1023 53 # Occupied blocks per task id 2481system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14476 # Occupied blocks per task id | 2439system.cpu1.l2cache.prefetcher.pfSpanPage 889052 # number of prefetches not generated due to page crossing 2440system.cpu1.l2cache.tags.replacements 2136964 # number of replacements 2441system.cpu1.l2cache.tags.tagsinuse 13504.433199 # Cycle average of tags in use 2442system.cpu1.l2cache.tags.total_refs 11477625 # Total number of references to valid blocks. 2443system.cpu1.l2cache.tags.sampled_refs 2153158 # Sample count of references to valid blocks. 2444system.cpu1.l2cache.tags.avg_refs 5.330600 # Average number of references to valid blocks. 2445system.cpu1.l2cache.tags.warmup_cycle 9723406338993 # Cycle when the warmup percentage was hit. 2446system.cpu1.l2cache.tags.occ_blocks::writebacks 5663.402040 # Average occupied blocks per requestor 2447system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 81.532496 # Average occupied blocks per requestor 2448system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 97.953204 # Average occupied blocks per requestor 2449system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3050.006780 # Average occupied blocks per requestor 2450system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3697.963934 # Average occupied blocks per requestor 2451system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 913.574746 # Average occupied blocks per requestor 2452system.cpu1.l2cache.tags.occ_percent::writebacks 0.345667 # Average percentage of cache occupancy 2453system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004976 # Average percentage of cache occupancy 2454system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005979 # Average percentage of cache occupancy 2455system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.186158 # Average percentage of cache occupancy 2456system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225706 # Average percentage of cache occupancy 2457system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055760 # Average percentage of cache occupancy 2458system.cpu1.l2cache.tags.occ_percent::total 0.824245 # Average percentage of cache occupancy 2459system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1347 # Occupied blocks per task id 2460system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id 2461system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14805 # Occupied blocks per task id |
| 2482system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id | 2462system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id |
| 2483system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 35 # Occupied blocks per task id 2484system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 465 # Occupied blocks per task id 2485system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 510 # Occupied blocks per task id 2486system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 477 # Occupied blocks per task id | 2463system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id 2464system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 237 # Occupied blocks per task id 2465system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 720 # Occupied blocks per task id 2466system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 360 # Occupied blocks per task id |
| 2487system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id | 2467system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id |
| 2488system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id 2489system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 2490system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id 2491system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id 2492system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1150 # Occupied blocks per task id 2493system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5680 # Occupied blocks per task id 2494system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4086 # Occupied blocks per task id 2495system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3438 # Occupied blocks per task id 2496system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.091248 # Percentage of cache occupancy per task id 2497system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003235 # Percentage of cache occupancy per task id 2498system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.883545 # Percentage of cache occupancy per task id 2499system.cpu1.l2cache.tags.tag_accesses 250860566 # Number of tag accesses 2500system.cpu1.l2cache.tags.data_accesses 250860566 # Number of data accesses 2501system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 536921 # number of ReadReq hits 2502system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 182584 # number of ReadReq hits 2503system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4917912 # number of ReadReq hits 2504system.cpu1.l2cache.ReadReq_hits::cpu1.data 2781477 # number of ReadReq hits 2505system.cpu1.l2cache.ReadReq_hits::total 8418894 # number of ReadReq hits 2506system.cpu1.l2cache.Writeback_hits::writebacks 3392565 # number of Writeback hits 2507system.cpu1.l2cache.Writeback_hits::total 3392565 # number of Writeback hits 2508system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 191757 # number of WriteInvalidateReq hits 2509system.cpu1.l2cache.WriteInvalidateReq_hits::total 191757 # number of WriteInvalidateReq hits 2510system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 71744 # number of UpgradeReq hits 2511system.cpu1.l2cache.UpgradeReq_hits::total 71744 # number of UpgradeReq hits 2512system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 31465 # number of SCUpgradeReq hits 2513system.cpu1.l2cache.SCUpgradeReq_hits::total 31465 # number of SCUpgradeReq hits 2514system.cpu1.l2cache.ReadExReq_hits::cpu1.data 867581 # number of ReadExReq hits 2515system.cpu1.l2cache.ReadExReq_hits::total 867581 # number of ReadExReq hits 2516system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 536921 # number of demand (read+write) hits 2517system.cpu1.l2cache.demand_hits::cpu1.itb.walker 182584 # number of demand (read+write) hits 2518system.cpu1.l2cache.demand_hits::cpu1.inst 4917912 # number of demand (read+write) hits 2519system.cpu1.l2cache.demand_hits::cpu1.data 3649058 # number of demand (read+write) hits 2520system.cpu1.l2cache.demand_hits::total 9286475 # number of demand (read+write) hits 2521system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 536921 # number of overall hits 2522system.cpu1.l2cache.overall_hits::cpu1.itb.walker 182584 # number of overall hits 2523system.cpu1.l2cache.overall_hits::cpu1.inst 4917912 # number of overall hits 2524system.cpu1.l2cache.overall_hits::cpu1.data 3649058 # number of overall hits 2525system.cpu1.l2cache.overall_hits::total 9286475 # number of overall hits 2526system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12339 # number of ReadReq misses 2527system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9008 # number of ReadReq misses 2528system.cpu1.l2cache.ReadReq_misses::cpu1.inst 605020 # number of ReadReq misses 2529system.cpu1.l2cache.ReadReq_misses::cpu1.data 1001664 # number of ReadReq misses 2530system.cpu1.l2cache.ReadReq_misses::total 1628031 # number of ReadReq misses 2531system.cpu1.l2cache.Writeback_misses::writebacks 17 # number of Writeback misses 2532system.cpu1.l2cache.Writeback_misses::total 17 # number of Writeback misses 2533system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 228944 # number of WriteInvalidateReq misses 2534system.cpu1.l2cache.WriteInvalidateReq_misses::total 228944 # number of WriteInvalidateReq misses 2535system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 145584 # number of UpgradeReq misses 2536system.cpu1.l2cache.UpgradeReq_misses::total 145584 # number of UpgradeReq misses 2537system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 172667 # number of SCUpgradeReq misses 2538system.cpu1.l2cache.SCUpgradeReq_misses::total 172667 # number of SCUpgradeReq misses 2539system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 13 # number of SCUpgradeFailReq misses 2540system.cpu1.l2cache.SCUpgradeFailReq_misses::total 13 # number of SCUpgradeFailReq misses 2541system.cpu1.l2cache.ReadExReq_misses::cpu1.data 259180 # number of ReadExReq misses 2542system.cpu1.l2cache.ReadExReq_misses::total 259180 # number of ReadExReq misses 2543system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12339 # number of demand (read+write) misses 2544system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9008 # number of demand (read+write) misses 2545system.cpu1.l2cache.demand_misses::cpu1.inst 605020 # number of demand (read+write) misses 2546system.cpu1.l2cache.demand_misses::cpu1.data 1260844 # number of demand (read+write) misses 2547system.cpu1.l2cache.demand_misses::total 1887211 # number of demand (read+write) misses 2548system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12339 # number of overall misses 2549system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9008 # number of overall misses 2550system.cpu1.l2cache.overall_misses::cpu1.inst 605020 # number of overall misses 2551system.cpu1.l2cache.overall_misses::cpu1.data 1260844 # number of overall misses 2552system.cpu1.l2cache.overall_misses::total 1887211 # number of overall misses 2553system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 492758189 # number of ReadReq miss cycles 2554system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 397546188 # number of ReadReq miss cycles 2555system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 17874502757 # number of ReadReq miss cycles 2556system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 34268686598 # number of ReadReq miss cycles 2557system.cpu1.l2cache.ReadReq_miss_latency::total 53033493732 # number of ReadReq miss cycles 2558system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 241449363 # number of WriteInvalidateReq miss cycles 2559system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 241449363 # number of WriteInvalidateReq miss cycles 2560system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2956550746 # number of UpgradeReq miss cycles 2561system.cpu1.l2cache.UpgradeReq_miss_latency::total 2956550746 # number of UpgradeReq miss cycles 2562system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3438458831 # number of SCUpgradeReq miss cycles 2563system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3438458831 # number of SCUpgradeReq miss cycles 2564system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3243000 # number of SCUpgradeFailReq miss cycles 2565system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3243000 # number of SCUpgradeFailReq miss cycles 2566system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10870225593 # number of ReadExReq miss cycles 2567system.cpu1.l2cache.ReadExReq_miss_latency::total 10870225593 # number of ReadExReq miss cycles 2568system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 492758189 # number of demand (read+write) miss cycles 2569system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 397546188 # number of demand (read+write) miss cycles 2570system.cpu1.l2cache.demand_miss_latency::cpu1.inst 17874502757 # number of demand (read+write) miss cycles 2571system.cpu1.l2cache.demand_miss_latency::cpu1.data 45138912191 # number of demand (read+write) miss cycles 2572system.cpu1.l2cache.demand_miss_latency::total 63903719325 # number of demand (read+write) miss cycles 2573system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 492758189 # number of overall miss cycles 2574system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 397546188 # number of overall miss cycles 2575system.cpu1.l2cache.overall_miss_latency::cpu1.inst 17874502757 # number of overall miss cycles 2576system.cpu1.l2cache.overall_miss_latency::cpu1.data 45138912191 # number of overall miss cycles 2577system.cpu1.l2cache.overall_miss_latency::total 63903719325 # number of overall miss cycles 2578system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 549260 # number of ReadReq accesses(hits+misses) 2579system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 191592 # number of ReadReq accesses(hits+misses) 2580system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5522932 # number of ReadReq accesses(hits+misses) 2581system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3783141 # number of ReadReq accesses(hits+misses) 2582system.cpu1.l2cache.ReadReq_accesses::total 10046925 # number of ReadReq accesses(hits+misses) 2583system.cpu1.l2cache.Writeback_accesses::writebacks 3392582 # number of Writeback accesses(hits+misses) 2584system.cpu1.l2cache.Writeback_accesses::total 3392582 # number of Writeback accesses(hits+misses) 2585system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 420701 # number of WriteInvalidateReq accesses(hits+misses) 2586system.cpu1.l2cache.WriteInvalidateReq_accesses::total 420701 # number of WriteInvalidateReq accesses(hits+misses) 2587system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 217328 # number of UpgradeReq accesses(hits+misses) 2588system.cpu1.l2cache.UpgradeReq_accesses::total 217328 # number of UpgradeReq accesses(hits+misses) 2589system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 204132 # number of SCUpgradeReq accesses(hits+misses) 2590system.cpu1.l2cache.SCUpgradeReq_accesses::total 204132 # number of SCUpgradeReq accesses(hits+misses) 2591system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 13 # number of SCUpgradeFailReq accesses(hits+misses) 2592system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 13 # number of SCUpgradeFailReq accesses(hits+misses) 2593system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1126761 # number of ReadExReq accesses(hits+misses) 2594system.cpu1.l2cache.ReadExReq_accesses::total 1126761 # number of ReadExReq accesses(hits+misses) 2595system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 549260 # number of demand (read+write) accesses 2596system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 191592 # number of demand (read+write) accesses 2597system.cpu1.l2cache.demand_accesses::cpu1.inst 5522932 # number of demand (read+write) accesses 2598system.cpu1.l2cache.demand_accesses::cpu1.data 4909902 # number of demand (read+write) accesses 2599system.cpu1.l2cache.demand_accesses::total 11173686 # number of demand (read+write) accesses 2600system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 549260 # number of overall (read+write) accesses 2601system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 191592 # number of overall (read+write) accesses 2602system.cpu1.l2cache.overall_accesses::cpu1.inst 5522932 # number of overall (read+write) accesses 2603system.cpu1.l2cache.overall_accesses::cpu1.data 4909902 # number of overall (read+write) accesses 2604system.cpu1.l2cache.overall_accesses::total 11173686 # number of overall (read+write) accesses 2605system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022465 # miss rate for ReadReq accesses 2606system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.047017 # miss rate for ReadReq accesses 2607system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.109547 # miss rate for ReadReq accesses 2608system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.264770 # miss rate for ReadReq accesses 2609system.cpu1.l2cache.ReadReq_miss_rate::total 0.162043 # miss rate for ReadReq accesses 2610system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000005 # miss rate for Writeback accesses 2611system.cpu1.l2cache.Writeback_miss_rate::total 0.000005 # miss rate for Writeback accesses 2612system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.544196 # miss rate for WriteInvalidateReq accesses 2613system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.544196 # miss rate for WriteInvalidateReq accesses 2614system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.669881 # miss rate for UpgradeReq accesses 2615system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.669881 # miss rate for UpgradeReq accesses 2616system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.845860 # miss rate for SCUpgradeReq accesses 2617system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.845860 # miss rate for SCUpgradeReq accesses | 2468system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 20 # Occupied blocks per task id 2469system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id 2470system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 2471system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id 2472system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1369 # Occupied blocks per task id 2473system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5255 # Occupied blocks per task id 2474system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5224 # Occupied blocks per task id 2475system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2823 # Occupied blocks per task id 2476system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.082214 # Percentage of cache occupancy per task id 2477system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002563 # Percentage of cache occupancy per task id 2478system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903625 # Percentage of cache occupancy per task id 2479system.cpu1.l2cache.tags.tag_accesses 249290678 # Number of tag accesses 2480system.cpu1.l2cache.tags.data_accesses 249290678 # Number of data accesses 2481system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 527309 # number of ReadReq hits 2482system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 181952 # number of ReadReq hits 2483system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5073722 # number of ReadReq hits 2484system.cpu1.l2cache.ReadReq_hits::cpu1.data 2781354 # number of ReadReq hits 2485system.cpu1.l2cache.ReadReq_hits::total 8564337 # number of ReadReq hits 2486system.cpu1.l2cache.Writeback_hits::writebacks 3264689 # number of Writeback hits 2487system.cpu1.l2cache.Writeback_hits::total 3264689 # number of Writeback hits 2488system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 166971 # number of WriteInvalidateReq hits 2489system.cpu1.l2cache.WriteInvalidateReq_hits::total 166971 # number of WriteInvalidateReq hits 2490system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 66098 # number of UpgradeReq hits 2491system.cpu1.l2cache.UpgradeReq_hits::total 66098 # number of UpgradeReq hits 2492system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 34177 # number of SCUpgradeReq hits 2493system.cpu1.l2cache.SCUpgradeReq_hits::total 34177 # number of SCUpgradeReq hits 2494system.cpu1.l2cache.ReadExReq_hits::cpu1.data 845253 # number of ReadExReq hits 2495system.cpu1.l2cache.ReadExReq_hits::total 845253 # number of ReadExReq hits 2496system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 527309 # number of demand (read+write) hits 2497system.cpu1.l2cache.demand_hits::cpu1.itb.walker 181952 # number of demand (read+write) hits 2498system.cpu1.l2cache.demand_hits::cpu1.inst 5073722 # number of demand (read+write) hits 2499system.cpu1.l2cache.demand_hits::cpu1.data 3626607 # number of demand (read+write) hits 2500system.cpu1.l2cache.demand_hits::total 9409590 # number of demand (read+write) hits 2501system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 527309 # number of overall hits 2502system.cpu1.l2cache.overall_hits::cpu1.itb.walker 181952 # number of overall hits 2503system.cpu1.l2cache.overall_hits::cpu1.inst 5073722 # number of overall hits 2504system.cpu1.l2cache.overall_hits::cpu1.data 3626607 # number of overall hits 2505system.cpu1.l2cache.overall_hits::total 9409590 # number of overall hits 2506system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12633 # number of ReadReq misses 2507system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9907 # number of ReadReq misses 2508system.cpu1.l2cache.ReadReq_misses::cpu1.inst 594787 # number of ReadReq misses 2509system.cpu1.l2cache.ReadReq_misses::cpu1.data 963518 # number of ReadReq misses 2510system.cpu1.l2cache.ReadReq_misses::total 1580845 # number of ReadReq misses 2511system.cpu1.l2cache.Writeback_misses::writebacks 14 # number of Writeback misses 2512system.cpu1.l2cache.Writeback_misses::total 14 # number of Writeback misses 2513system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 249743 # number of WriteInvalidateReq misses 2514system.cpu1.l2cache.WriteInvalidateReq_misses::total 249743 # number of WriteInvalidateReq misses 2515system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 139723 # number of UpgradeReq misses 2516system.cpu1.l2cache.UpgradeReq_misses::total 139723 # number of UpgradeReq misses 2517system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 161589 # number of SCUpgradeReq misses 2518system.cpu1.l2cache.SCUpgradeReq_misses::total 161589 # number of SCUpgradeReq misses 2519system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 15 # number of SCUpgradeFailReq misses 2520system.cpu1.l2cache.SCUpgradeFailReq_misses::total 15 # number of SCUpgradeFailReq misses 2521system.cpu1.l2cache.ReadExReq_misses::cpu1.data 245189 # number of ReadExReq misses 2522system.cpu1.l2cache.ReadExReq_misses::total 245189 # number of ReadExReq misses 2523system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12633 # number of demand (read+write) misses 2524system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9907 # number of demand (read+write) misses 2525system.cpu1.l2cache.demand_misses::cpu1.inst 594787 # number of demand (read+write) misses 2526system.cpu1.l2cache.demand_misses::cpu1.data 1208707 # number of demand (read+write) misses 2527system.cpu1.l2cache.demand_misses::total 1826034 # number of demand (read+write) misses 2528system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12633 # number of overall misses 2529system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9907 # number of overall misses 2530system.cpu1.l2cache.overall_misses::cpu1.inst 594787 # number of overall misses 2531system.cpu1.l2cache.overall_misses::cpu1.data 1208707 # number of overall misses 2532system.cpu1.l2cache.overall_misses::total 1826034 # number of overall misses 2533system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 491583485 # number of ReadReq miss cycles 2534system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 427969129 # number of ReadReq miss cycles 2535system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 16999057098 # number of ReadReq miss cycles 2536system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 31500874862 # number of ReadReq miss cycles 2537system.cpu1.l2cache.ReadReq_miss_latency::total 49419484574 # number of ReadReq miss cycles 2538system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 236089966 # number of WriteInvalidateReq miss cycles 2539system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 236089966 # number of WriteInvalidateReq miss cycles 2540system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3003661220 # number of UpgradeReq miss cycles 2541system.cpu1.l2cache.UpgradeReq_miss_latency::total 3003661220 # number of UpgradeReq miss cycles 2542system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3342420381 # number of SCUpgradeReq miss cycles 2543system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3342420381 # number of SCUpgradeReq miss cycles 2544system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4508496 # number of SCUpgradeFailReq miss cycles 2545system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4508496 # number of SCUpgradeFailReq miss cycles 2546system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11309728111 # number of ReadExReq miss cycles 2547system.cpu1.l2cache.ReadExReq_miss_latency::total 11309728111 # number of ReadExReq miss cycles 2548system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 491583485 # number of demand (read+write) miss cycles 2549system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 427969129 # number of demand (read+write) miss cycles 2550system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16999057098 # number of demand (read+write) miss cycles 2551system.cpu1.l2cache.demand_miss_latency::cpu1.data 42810602973 # number of demand (read+write) miss cycles 2552system.cpu1.l2cache.demand_miss_latency::total 60729212685 # number of demand (read+write) miss cycles 2553system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 491583485 # number of overall miss cycles 2554system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 427969129 # number of overall miss cycles 2555system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16999057098 # number of overall miss cycles 2556system.cpu1.l2cache.overall_miss_latency::cpu1.data 42810602973 # number of overall miss cycles 2557system.cpu1.l2cache.overall_miss_latency::total 60729212685 # number of overall miss cycles 2558system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 539942 # number of ReadReq accesses(hits+misses) 2559system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 191859 # number of ReadReq accesses(hits+misses) 2560system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5668509 # number of ReadReq accesses(hits+misses) 2561system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3744872 # number of ReadReq accesses(hits+misses) 2562system.cpu1.l2cache.ReadReq_accesses::total 10145182 # number of ReadReq accesses(hits+misses) 2563system.cpu1.l2cache.Writeback_accesses::writebacks 3264703 # number of Writeback accesses(hits+misses) 2564system.cpu1.l2cache.Writeback_accesses::total 3264703 # number of Writeback accesses(hits+misses) 2565system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 416714 # number of WriteInvalidateReq accesses(hits+misses) 2566system.cpu1.l2cache.WriteInvalidateReq_accesses::total 416714 # number of WriteInvalidateReq accesses(hits+misses) 2567system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 205821 # number of UpgradeReq accesses(hits+misses) 2568system.cpu1.l2cache.UpgradeReq_accesses::total 205821 # number of UpgradeReq accesses(hits+misses) 2569system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195766 # number of SCUpgradeReq accesses(hits+misses) 2570system.cpu1.l2cache.SCUpgradeReq_accesses::total 195766 # number of SCUpgradeReq accesses(hits+misses) 2571system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 15 # number of SCUpgradeFailReq accesses(hits+misses) 2572system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 15 # number of SCUpgradeFailReq accesses(hits+misses) 2573system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1090442 # number of ReadExReq accesses(hits+misses) 2574system.cpu1.l2cache.ReadExReq_accesses::total 1090442 # number of ReadExReq accesses(hits+misses) 2575system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 539942 # number of demand (read+write) accesses 2576system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 191859 # number of demand (read+write) accesses 2577system.cpu1.l2cache.demand_accesses::cpu1.inst 5668509 # number of demand (read+write) accesses 2578system.cpu1.l2cache.demand_accesses::cpu1.data 4835314 # number of demand (read+write) accesses 2579system.cpu1.l2cache.demand_accesses::total 11235624 # number of demand (read+write) accesses 2580system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 539942 # number of overall (read+write) accesses 2581system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 191859 # number of overall (read+write) accesses 2582system.cpu1.l2cache.overall_accesses::cpu1.inst 5668509 # number of overall (read+write) accesses 2583system.cpu1.l2cache.overall_accesses::cpu1.data 4835314 # number of overall (read+write) accesses 2584system.cpu1.l2cache.overall_accesses::total 11235624 # number of overall (read+write) accesses 2585system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023397 # miss rate for ReadReq accesses 2586system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.051637 # miss rate for ReadReq accesses 2587system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.104928 # miss rate for ReadReq accesses 2588system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.257290 # miss rate for ReadReq accesses 2589system.cpu1.l2cache.ReadReq_miss_rate::total 0.155822 # miss rate for ReadReq accesses 2590system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000004 # miss rate for Writeback accesses 2591system.cpu1.l2cache.Writeback_miss_rate::total 0.000004 # miss rate for Writeback accesses 2592system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.599315 # miss rate for WriteInvalidateReq accesses 2593system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.599315 # miss rate for WriteInvalidateReq accesses 2594system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.678857 # miss rate for UpgradeReq accesses 2595system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.678857 # miss rate for UpgradeReq accesses 2596system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.825419 # miss rate for SCUpgradeReq accesses 2597system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.825419 # miss rate for SCUpgradeReq accesses |
| 2618system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2619system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 2598system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2599system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 2620system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.230022 # miss rate for ReadExReq accesses 2621system.cpu1.l2cache.ReadExReq_miss_rate::total 0.230022 # miss rate for ReadExReq accesses 2622system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022465 # miss rate for demand accesses 2623system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.047017 # miss rate for demand accesses 2624system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.109547 # miss rate for demand accesses 2625system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.256796 # miss rate for demand accesses 2626system.cpu1.l2cache.demand_miss_rate::total 0.168898 # miss rate for demand accesses 2627system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022465 # miss rate for overall accesses 2628system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.047017 # miss rate for overall accesses 2629system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.109547 # miss rate for overall accesses 2630system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.256796 # miss rate for overall accesses 2631system.cpu1.l2cache.overall_miss_rate::total 0.168898 # miss rate for overall accesses 2632system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39935.018154 # average ReadReq miss latency 2633system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 44132.569716 # average ReadReq miss latency 2634system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29543.656006 # average ReadReq miss latency 2635system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 34211.758232 # average ReadReq miss latency 2636system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32575.235811 # average ReadReq miss latency 2637system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 1054.621929 # average WriteInvalidateReq miss latency 2638system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 1054.621929 # average WriteInvalidateReq miss latency 2639system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20308.212070 # average UpgradeReq miss latency 2640system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20308.212070 # average UpgradeReq miss latency 2641system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19913.815790 # average SCUpgradeReq miss latency 2642system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19913.815790 # average SCUpgradeReq miss latency 2643system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 249461.538462 # average SCUpgradeFailReq miss latency 2644system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 249461.538462 # average SCUpgradeFailReq miss latency 2645system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 41940.834914 # average ReadExReq miss latency 2646system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41940.834914 # average ReadExReq miss latency 2647system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39935.018154 # average overall miss latency 2648system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 44132.569716 # average overall miss latency 2649system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29543.656006 # average overall miss latency 2650system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35800.552797 # average overall miss latency 2651system.cpu1.l2cache.demand_avg_miss_latency::total 33861.459755 # average overall miss latency 2652system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39935.018154 # average overall miss latency 2653system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 44132.569716 # average overall miss latency 2654system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29543.656006 # average overall miss latency 2655system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35800.552797 # average overall miss latency 2656system.cpu1.l2cache.overall_avg_miss_latency::total 33861.459755 # average overall miss latency 2657system.cpu1.l2cache.blocked_cycles::no_mshrs 9 # number of cycles access was blocked | 2600system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.224853 # miss rate for ReadExReq accesses 2601system.cpu1.l2cache.ReadExReq_miss_rate::total 0.224853 # miss rate for ReadExReq accesses 2602system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023397 # miss rate for demand accesses 2603system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.051637 # miss rate for demand accesses 2604system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.104928 # miss rate for demand accesses 2605system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.249975 # miss rate for demand accesses 2606system.cpu1.l2cache.demand_miss_rate::total 0.162522 # miss rate for demand accesses 2607system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023397 # miss rate for overall accesses 2608system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.051637 # miss rate for overall accesses 2609system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.104928 # miss rate for overall accesses 2610system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.249975 # miss rate for overall accesses 2611system.cpu1.l2cache.overall_miss_rate::total 0.162522 # miss rate for overall accesses 2612system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 38912.648223 # average ReadReq miss latency 2613system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 43198.660442 # average ReadReq miss latency 2614system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 28580.075049 # average ReadReq miss latency 2615system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32693.602882 # average ReadReq miss latency 2616system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31261.435861 # average ReadReq miss latency 2617system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 945.331665 # average WriteInvalidateReq miss latency 2618system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 945.331665 # average WriteInvalidateReq miss latency 2619system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21497.256858 # average UpgradeReq miss latency 2620system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21497.256858 # average UpgradeReq miss latency 2621system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20684.702430 # average SCUpgradeReq miss latency 2622system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20684.702430 # average SCUpgradeReq miss latency 2623system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 300566.400000 # average SCUpgradeFailReq miss latency 2624system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 300566.400000 # average SCUpgradeFailReq miss latency 2625system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 46126.572199 # average ReadExReq miss latency 2626system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 46126.572199 # average ReadExReq miss latency 2627system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 38912.648223 # average overall miss latency 2628system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 43198.660442 # average overall miss latency 2629system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28580.075049 # average overall miss latency 2630system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35418.511660 # average overall miss latency 2631system.cpu1.l2cache.demand_avg_miss_latency::total 33257.438079 # average overall miss latency 2632system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 38912.648223 # average overall miss latency 2633system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 43198.660442 # average overall miss latency 2634system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28580.075049 # average overall miss latency 2635system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35418.511660 # average overall miss latency 2636system.cpu1.l2cache.overall_avg_miss_latency::total 33257.438079 # average overall miss latency 2637system.cpu1.l2cache.blocked_cycles::no_mshrs 100 # number of cycles access was blocked |
| 2658system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2638system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2659system.cpu1.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked | 2639system.cpu1.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked |
| 2660system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 2640system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 2661system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 4.500000 # average number of cycles each access was blocked | 2641system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 25 # average number of cycles each access was blocked |
| 2662system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2663system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2664system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 2642system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2643system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2644system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 2665system.cpu1.l2cache.writebacks::writebacks 971322 # number of writebacks 2666system.cpu1.l2cache.writebacks::total 971322 # number of writebacks 2667system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 2 # number of ReadReq MSHR hits 2668system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 153 # number of ReadReq MSHR hits 2669system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits 2670system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 6612 # number of ReadReq MSHR hits 2671system.cpu1.l2cache.ReadReq_mshr_hits::total 6768 # number of ReadReq MSHR hits 2672system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 63 # number of WriteInvalidateReq MSHR hits 2673system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 63 # number of WriteInvalidateReq MSHR hits 2674system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 20490 # number of ReadExReq MSHR hits 2675system.cpu1.l2cache.ReadExReq_mshr_hits::total 20490 # number of ReadExReq MSHR hits 2676system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 2 # number of demand (read+write) MSHR hits 2677system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 153 # number of demand (read+write) MSHR hits 2678system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits 2679system.cpu1.l2cache.demand_mshr_hits::cpu1.data 27102 # number of demand (read+write) MSHR hits 2680system.cpu1.l2cache.demand_mshr_hits::total 27258 # number of demand (read+write) MSHR hits 2681system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 2 # number of overall MSHR hits 2682system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 153 # number of overall MSHR hits 2683system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits 2684system.cpu1.l2cache.overall_mshr_hits::cpu1.data 27102 # number of overall MSHR hits 2685system.cpu1.l2cache.overall_mshr_hits::total 27258 # number of overall MSHR hits 2686system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12337 # number of ReadReq MSHR misses 2687system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8855 # number of ReadReq MSHR misses 2688system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 605019 # number of ReadReq MSHR misses 2689system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 995052 # number of ReadReq MSHR misses 2690system.cpu1.l2cache.ReadReq_mshr_misses::total 1621263 # number of ReadReq MSHR misses 2691system.cpu1.l2cache.Writeback_mshr_misses::writebacks 17 # number of Writeback MSHR misses 2692system.cpu1.l2cache.Writeback_mshr_misses::total 17 # number of Writeback MSHR misses 2693system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 705681 # number of HardPFReq MSHR misses 2694system.cpu1.l2cache.HardPFReq_mshr_misses::total 705681 # number of HardPFReq MSHR misses 2695system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 228881 # number of WriteInvalidateReq MSHR misses 2696system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 228881 # number of WriteInvalidateReq MSHR misses 2697system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 145584 # number of UpgradeReq MSHR misses 2698system.cpu1.l2cache.UpgradeReq_mshr_misses::total 145584 # number of UpgradeReq MSHR misses 2699system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 172667 # number of SCUpgradeReq MSHR misses 2700system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 172667 # number of SCUpgradeReq MSHR misses 2701system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 13 # number of SCUpgradeFailReq MSHR misses 2702system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 13 # number of SCUpgradeFailReq MSHR misses 2703system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 238690 # number of ReadExReq MSHR misses 2704system.cpu1.l2cache.ReadExReq_mshr_misses::total 238690 # number of ReadExReq MSHR misses 2705system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12337 # number of demand (read+write) MSHR misses 2706system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8855 # number of demand (read+write) MSHR misses 2707system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 605019 # number of demand (read+write) MSHR misses 2708system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1233742 # number of demand (read+write) MSHR misses 2709system.cpu1.l2cache.demand_mshr_misses::total 1859953 # number of demand (read+write) MSHR misses 2710system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12337 # number of overall MSHR misses 2711system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8855 # number of overall MSHR misses 2712system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 605019 # number of overall MSHR misses 2713system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1233742 # number of overall MSHR misses 2714system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 705681 # number of overall MSHR misses 2715system.cpu1.l2cache.overall_mshr_misses::total 2565634 # number of overall MSHR misses 2716system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 405599231 # number of ReadReq MSHR miss cycles 2717system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 327287462 # number of ReadReq MSHR miss cycles 2718system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 13621135743 # number of ReadReq MSHR miss cycles 2719system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 26954578760 # number of ReadReq MSHR miss cycles 2720system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 41308601196 # number of ReadReq MSHR miss cycles 2721system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 39485552404 # number of HardPFReq MSHR miss cycles 2722system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 39485552404 # number of HardPFReq MSHR miss cycles 2723system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 6916972959 # number of WriteInvalidateReq MSHR miss cycles 2724system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 6916972959 # number of WriteInvalidateReq MSHR miss cycles 2725system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2477712924 # number of UpgradeReq MSHR miss cycles 2726system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2477712924 # number of UpgradeReq MSHR miss cycles 2727system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2304203121 # number of SCUpgradeReq MSHR miss cycles 2728system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2304203121 # number of SCUpgradeReq MSHR miss cycles 2729system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2669000 # number of SCUpgradeFailReq MSHR miss cycles 2730system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2669000 # number of SCUpgradeFailReq MSHR miss cycles 2731system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7509818481 # number of ReadExReq MSHR miss cycles 2732system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7509818481 # number of ReadExReq MSHR miss cycles 2733system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 405599231 # number of demand (read+write) MSHR miss cycles 2734system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 327287462 # number of demand (read+write) MSHR miss cycles 2735system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 13621135743 # number of demand (read+write) MSHR miss cycles 2736system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 34464397241 # number of demand (read+write) MSHR miss cycles 2737system.cpu1.l2cache.demand_mshr_miss_latency::total 48818419677 # number of demand (read+write) MSHR miss cycles 2738system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 405599231 # number of overall MSHR miss cycles 2739system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 327287462 # number of overall MSHR miss cycles 2740system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 13621135743 # number of overall MSHR miss cycles 2741system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 34464397241 # number of overall MSHR miss cycles 2742system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 39485552404 # number of overall MSHR miss cycles 2743system.cpu1.l2cache.overall_mshr_miss_latency::total 88303972081 # number of overall MSHR miss cycles 2744system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5233250 # number of ReadReq MSHR uncacheable cycles 2745system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 741632996 # number of ReadReq MSHR uncacheable cycles 2746system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 746866246 # number of ReadReq MSHR uncacheable cycles 2747system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 846035990 # number of WriteReq MSHR uncacheable cycles 2748system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 846035990 # number of WriteReq MSHR uncacheable cycles 2749system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 5233250 # number of overall MSHR uncacheable cycles 2750system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1587668986 # number of overall MSHR uncacheable cycles 2751system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1592902236 # number of overall MSHR uncacheable cycles 2752system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022461 # mshr miss rate for ReadReq accesses 2753system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046218 # mshr miss rate for ReadReq accesses 2754system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.109547 # mshr miss rate for ReadReq accesses 2755system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.263023 # mshr miss rate for ReadReq accesses 2756system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.161369 # mshr miss rate for ReadReq accesses 2757system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000005 # mshr miss rate for Writeback accesses 2758system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000005 # mshr miss rate for Writeback accesses | 2645system.cpu1.l2cache.writebacks::writebacks 969171 # number of writebacks 2646system.cpu1.l2cache.writebacks::total 969171 # number of writebacks 2647system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 3 # number of ReadReq MSHR hits 2648system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 194 # number of ReadReq MSHR hits 2649system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 3035 # number of ReadReq MSHR hits 2650system.cpu1.l2cache.ReadReq_mshr_hits::total 3232 # number of ReadReq MSHR hits 2651system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 1 # number of WriteInvalidateReq MSHR hits 2652system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 1 # number of WriteInvalidateReq MSHR hits 2653system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 16069 # number of ReadExReq MSHR hits 2654system.cpu1.l2cache.ReadExReq_mshr_hits::total 16069 # number of ReadExReq MSHR hits 2655system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 3 # number of demand (read+write) MSHR hits 2656system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 194 # number of demand (read+write) MSHR hits 2657system.cpu1.l2cache.demand_mshr_hits::cpu1.data 19104 # number of demand (read+write) MSHR hits 2658system.cpu1.l2cache.demand_mshr_hits::total 19301 # number of demand (read+write) MSHR hits 2659system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 3 # number of overall MSHR hits 2660system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 194 # number of overall MSHR hits 2661system.cpu1.l2cache.overall_mshr_hits::cpu1.data 19104 # number of overall MSHR hits 2662system.cpu1.l2cache.overall_mshr_hits::total 19301 # number of overall MSHR hits 2663system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12630 # number of ReadReq MSHR misses 2664system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9713 # number of ReadReq MSHR misses 2665system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 594787 # number of ReadReq MSHR misses 2666system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 960483 # number of ReadReq MSHR misses 2667system.cpu1.l2cache.ReadReq_mshr_misses::total 1577613 # number of ReadReq MSHR misses 2668system.cpu1.l2cache.Writeback_mshr_misses::writebacks 14 # number of Writeback MSHR misses 2669system.cpu1.l2cache.Writeback_mshr_misses::total 14 # number of Writeback MSHR misses 2670system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 688186 # number of HardPFReq MSHR misses 2671system.cpu1.l2cache.HardPFReq_mshr_misses::total 688186 # number of HardPFReq MSHR misses 2672system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 249742 # number of WriteInvalidateReq MSHR misses 2673system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 249742 # number of WriteInvalidateReq MSHR misses 2674system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 139723 # number of UpgradeReq MSHR misses 2675system.cpu1.l2cache.UpgradeReq_mshr_misses::total 139723 # number of UpgradeReq MSHR misses 2676system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 161589 # number of SCUpgradeReq MSHR misses 2677system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 161589 # number of SCUpgradeReq MSHR misses 2678system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 15 # number of SCUpgradeFailReq MSHR misses 2679system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 15 # number of SCUpgradeFailReq MSHR misses 2680system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 229120 # number of ReadExReq MSHR misses 2681system.cpu1.l2cache.ReadExReq_mshr_misses::total 229120 # number of ReadExReq MSHR misses 2682system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12630 # number of demand (read+write) MSHR misses 2683system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9713 # number of demand (read+write) MSHR misses 2684system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 594787 # number of demand (read+write) MSHR misses 2685system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1189603 # number of demand (read+write) MSHR misses 2686system.cpu1.l2cache.demand_mshr_misses::total 1806733 # number of demand (read+write) MSHR misses 2687system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12630 # number of overall MSHR misses 2688system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9713 # number of overall MSHR misses 2689system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 594787 # number of overall MSHR misses 2690system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1189603 # number of overall MSHR misses 2691system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 688186 # number of overall MSHR misses 2692system.cpu1.l2cache.overall_mshr_misses::total 2494919 # number of overall MSHR misses 2693system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 408647025 # number of ReadReq MSHR miss cycles 2694system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 358018255 # number of ReadReq MSHR miss cycles 2695system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 13119737402 # number of ReadReq MSHR miss cycles 2696system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 25025673719 # number of ReadReq MSHR miss cycles 2697system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 38912076401 # number of ReadReq MSHR miss cycles 2698system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 36938967043 # number of HardPFReq MSHR miss cycles 2699system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 36938967043 # number of HardPFReq MSHR miss cycles 2700system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 8412735671 # number of WriteInvalidateReq MSHR miss cycles 2701system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 8412735671 # number of WriteInvalidateReq MSHR miss cycles 2702system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2759951656 # number of UpgradeReq MSHR miss cycles 2703system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2759951656 # number of UpgradeReq MSHR miss cycles 2704system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2380296086 # number of SCUpgradeReq MSHR miss cycles 2705system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2380296086 # number of SCUpgradeReq MSHR miss cycles 2706system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3864996 # number of SCUpgradeFailReq MSHR miss cycles 2707system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3864996 # number of SCUpgradeFailReq MSHR miss cycles 2708system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7878318651 # number of ReadExReq MSHR miss cycles 2709system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7878318651 # number of ReadExReq MSHR miss cycles 2710system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 408647025 # number of demand (read+write) MSHR miss cycles 2711system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 358018255 # number of demand (read+write) MSHR miss cycles 2712system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 13119737402 # number of demand (read+write) MSHR miss cycles 2713system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 32903992370 # number of demand (read+write) MSHR miss cycles 2714system.cpu1.l2cache.demand_mshr_miss_latency::total 46790395052 # number of demand (read+write) MSHR miss cycles 2715system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 408647025 # number of overall MSHR miss cycles 2716system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 358018255 # number of overall MSHR miss cycles 2717system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 13119737402 # number of overall MSHR miss cycles 2718system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 32903992370 # number of overall MSHR miss cycles 2719system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 36938967043 # number of overall MSHR miss cycles 2720system.cpu1.l2cache.overall_mshr_miss_latency::total 83729362095 # number of overall MSHR miss cycles 2721system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5602750 # number of ReadReq MSHR uncacheable cycles 2722system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 639050750 # number of ReadReq MSHR uncacheable cycles 2723system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 644653500 # number of ReadReq MSHR uncacheable cycles 2724system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 738464498 # number of WriteReq MSHR uncacheable cycles 2725system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 738464498 # number of WriteReq MSHR uncacheable cycles 2726system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 5602750 # number of overall MSHR uncacheable cycles 2727system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1377515248 # number of overall MSHR uncacheable cycles 2728system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1383117998 # number of overall MSHR uncacheable cycles 2729system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023391 # mshr miss rate for ReadReq accesses 2730system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050626 # mshr miss rate for ReadReq accesses 2731system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.104928 # mshr miss rate for ReadReq accesses 2732system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.256480 # mshr miss rate for ReadReq accesses 2733system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.155504 # mshr miss rate for ReadReq accesses 2734system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000004 # mshr miss rate for Writeback accesses 2735system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000004 # mshr miss rate for Writeback accesses |
| 2759system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2760system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 2736system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2737system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 2761system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.544047 # mshr miss rate for WriteInvalidateReq accesses 2762system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.544047 # mshr miss rate for WriteInvalidateReq accesses 2763system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.669881 # mshr miss rate for UpgradeReq accesses 2764system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.669881 # mshr miss rate for UpgradeReq accesses 2765system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.845860 # mshr miss rate for SCUpgradeReq accesses 2766system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.845860 # mshr miss rate for SCUpgradeReq accesses | 2738system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.599313 # mshr miss rate for WriteInvalidateReq accesses 2739system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.599313 # mshr miss rate for WriteInvalidateReq accesses 2740system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.678857 # mshr miss rate for UpgradeReq accesses 2741system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.678857 # mshr miss rate for UpgradeReq accesses 2742system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.825419 # mshr miss rate for SCUpgradeReq accesses 2743system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.825419 # mshr miss rate for SCUpgradeReq accesses |
| 2767system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2768system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 2744system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2745system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 2769system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.211837 # mshr miss rate for ReadExReq accesses 2770system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.211837 # mshr miss rate for ReadExReq accesses 2771system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022461 # mshr miss rate for demand accesses 2772system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046218 # mshr miss rate for demand accesses 2773system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.109547 # mshr miss rate for demand accesses 2774system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.251276 # mshr miss rate for demand accesses 2775system.cpu1.l2cache.demand_mshr_miss_rate::total 0.166458 # mshr miss rate for demand accesses 2776system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022461 # mshr miss rate for overall accesses 2777system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046218 # mshr miss rate for overall accesses 2778system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.109547 # mshr miss rate for overall accesses 2779system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.251276 # mshr miss rate for overall accesses | 2746system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.210117 # mshr miss rate for ReadExReq accesses 2747system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.210117 # mshr miss rate for ReadExReq accesses 2748system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023391 # mshr miss rate for demand accesses 2749system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050626 # mshr miss rate for demand accesses 2750system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.104928 # mshr miss rate for demand accesses 2751system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.246024 # mshr miss rate for demand accesses 2752system.cpu1.l2cache.demand_mshr_miss_rate::total 0.160804 # mshr miss rate for demand accesses 2753system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023391 # mshr miss rate for overall accesses 2754system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050626 # mshr miss rate for overall accesses 2755system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.104928 # mshr miss rate for overall accesses 2756system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.246024 # mshr miss rate for overall accesses |
| 2780system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 2757system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 2781system.cpu1.l2cache.overall_mshr_miss_rate::total 0.229614 # mshr miss rate for overall accesses 2782system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996 # average ReadReq mshr miss latency 2783system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343 # average ReadReq mshr miss latency 2784system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22513.566918 # average ReadReq mshr miss latency 2785system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 27088.613218 # average ReadReq mshr miss latency 2786system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25479.272145 # average ReadReq mshr miss latency 2787system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55953.826735 # average HardPFReq mshr miss latency 2788system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55953.826735 # average HardPFReq mshr miss latency 2789system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30220.826364 # average WriteInvalidateReq mshr miss latency 2790system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 30220.826364 # average WriteInvalidateReq mshr miss latency 2791system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17019.129327 # average UpgradeReq mshr miss latency 2792system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17019.129327 # average UpgradeReq mshr miss latency 2793system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13344.779958 # average SCUpgradeReq mshr miss latency 2794system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13344.779958 # average SCUpgradeReq mshr miss latency 2795system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 205307.692308 # average SCUpgradeFailReq mshr miss latency 2796system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 205307.692308 # average SCUpgradeFailReq mshr miss latency 2797system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31462.643936 # average ReadExReq mshr miss latency 2798system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31462.643936 # average ReadExReq mshr miss latency 2799system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996 # average overall mshr miss latency 2800system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343 # average overall mshr miss latency 2801system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22513.566918 # average overall mshr miss latency 2802system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27934.849621 # average overall mshr miss latency 2803system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26247.125426 # average overall mshr miss latency 2804system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996 # average overall mshr miss latency 2805system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343 # average overall mshr miss latency 2806system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22513.566918 # average overall mshr miss latency 2807system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27934.849621 # average overall mshr miss latency 2808system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55953.826735 # average overall mshr miss latency 2809system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34417.992621 # average overall mshr miss latency | 2758system.cpu1.l2cache.overall_mshr_miss_rate::total 0.222054 # mshr miss rate for overall accesses 2759system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32355.267221 # average ReadReq mshr miss latency 2760system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 36859.698857 # average ReadReq mshr miss latency 2761system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22057.875175 # average ReadReq mshr miss latency 2762system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26055.301051 # average ReadReq mshr miss latency 2763system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24665.159580 # average ReadReq mshr miss latency 2764system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53675.847871 # average HardPFReq mshr miss latency 2765system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 53675.847871 # average HardPFReq mshr miss latency 2766system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 33685.706333 # average WriteInvalidateReq mshr miss latency 2767system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33685.706333 # average WriteInvalidateReq mshr miss latency 2768system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19753.023167 # average UpgradeReq mshr miss latency 2769system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19753.023167 # average UpgradeReq mshr miss latency 2770system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14730.557686 # average SCUpgradeReq mshr miss latency 2771system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14730.557686 # average SCUpgradeReq mshr miss latency 2772system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 257666.400000 # average SCUpgradeFailReq mshr miss latency 2773system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 257666.400000 # average SCUpgradeFailReq mshr miss latency 2774system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34385.119811 # average ReadExReq mshr miss latency 2775system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34385.119811 # average ReadExReq mshr miss latency 2776system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32355.267221 # average overall mshr miss latency 2777system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 36859.698857 # average overall mshr miss latency 2778system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22057.875175 # average overall mshr miss latency 2779system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27659.641385 # average overall mshr miss latency 2780system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25897.791789 # average overall mshr miss latency 2781system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32355.267221 # average overall mshr miss latency 2782system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 36859.698857 # average overall mshr miss latency 2783system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22057.875175 # average overall mshr miss latency 2784system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27659.641385 # average overall mshr miss latency 2785system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53675.847871 # average overall mshr miss latency 2786system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33559.952085 # average overall mshr miss latency |
| 2810system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2811system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2812system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2813system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2814system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2815system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2816system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2817system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2818system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 2787system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2788system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2789system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2790system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2791system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2792system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2793system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2794system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 2795system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2819system.cpu1.toL2Bus.trans_dist::ReadReq 12802922 # Transaction distribution 2820system.cpu1.toL2Bus.trans_dist::ReadResp 10291743 # Transaction distribution 2821system.cpu1.toL2Bus.trans_dist::WriteReq 6895 # Transaction distribution 2822system.cpu1.toL2Bus.trans_dist::WriteResp 6895 # Transaction distribution 2823system.cpu1.toL2Bus.trans_dist::Writeback 3392582 # Transaction distribution 2824system.cpu1.toL2Bus.trans_dist::HardPFReq 1076196 # Transaction distribution 2825system.cpu1.toL2Bus.trans_dist::HardPFResp 13 # Transaction distribution 2826system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1156933 # Transaction distribution 2827system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 420701 # Transaction distribution 2828system.cpu1.toL2Bus.trans_dist::UpgradeReq 464615 # Transaction distribution 2829system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 376292 # Transaction distribution 2830system.cpu1.toL2Bus.trans_dist::UpgradeResp 486818 # Transaction distribution 2831system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 88 # Transaction distribution 2832system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 157 # Transaction distribution 2833system.cpu1.toL2Bus.trans_dist::ReadExReq 1296360 # Transaction distribution 2834system.cpu1.toL2Bus.trans_dist::ReadExResp 1132878 # Transaction distribution 2835system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11046012 # Packet count per connected master and slave (bytes) 2836system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15089863 # Packet count per connected master and slave (bytes) 2837system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 415115 # Packet count per connected master and slave (bytes) 2838system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1210522 # Packet count per connected master and slave (bytes) 2839system.cpu1.toL2Bus.pkt_count::total 27761512 # Packet count per connected master and slave (bytes) 2840system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 353468736 # Cumulative packet size per connected master and slave (bytes) 2841system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 564735319 # Cumulative packet size per connected master and slave (bytes) 2842system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1532736 # Cumulative packet size per connected master and slave (bytes) 2843system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4394080 # Cumulative packet size per connected master and slave (bytes) 2844system.cpu1.toL2Bus.pkt_size::total 924130871 # Cumulative packet size per connected master and slave (bytes) 2845system.cpu1.toL2Bus.snoops 5316111 # Total snoops (count) 2846system.cpu1.toL2Bus.snoop_fanout::samples 20559073 # Request fanout histogram 2847system.cpu1.toL2Bus.snoop_fanout::mean 5.243524 # Request fanout histogram 2848system.cpu1.toL2Bus.snoop_fanout::stdev 0.429209 # Request fanout histogram | 2796system.cpu1.toL2Bus.trans_dist::ReadReq 12589327 # Transaction distribution 2797system.cpu1.toL2Bus.trans_dist::ReadResp 10390309 # Transaction distribution 2798system.cpu1.toL2Bus.trans_dist::WriteReq 6277 # Transaction distribution 2799system.cpu1.toL2Bus.trans_dist::WriteResp 6277 # Transaction distribution 2800system.cpu1.toL2Bus.trans_dist::Writeback 3264703 # Transaction distribution 2801system.cpu1.toL2Bus.trans_dist::HardPFReq 969369 # Transaction distribution 2802system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution 2803system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1138126 # Transaction distribution 2804system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 416714 # Transaction distribution 2805system.cpu1.toL2Bus.trans_dist::UpgradeReq 449544 # Transaction distribution 2806system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 355754 # Transaction distribution 2807system.cpu1.toL2Bus.trans_dist::UpgradeResp 472453 # Transaction distribution 2808system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 124 # Transaction distribution 2809system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 208 # Transaction distribution 2810system.cpu1.toL2Bus.trans_dist::ReadExReq 1246255 # Transaction distribution 2811system.cpu1.toL2Bus.trans_dist::ReadExResp 1097731 # Transaction distribution 2812system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11337166 # Packet count per connected master and slave (bytes) 2813system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14775069 # Packet count per connected master and slave (bytes) 2814system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 416528 # Packet count per connected master and slave (bytes) 2815system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1186159 # Packet count per connected master and slave (bytes) 2816system.cpu1.toL2Bus.pkt_count::total 27714922 # Packet count per connected master and slave (bytes) 2817system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 362785648 # Cumulative packet size per connected master and slave (bytes) 2818system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 551966772 # Cumulative packet size per connected master and slave (bytes) 2819system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1534872 # Cumulative packet size per connected master and slave (bytes) 2820system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4319536 # Cumulative packet size per connected master and slave (bytes) 2821system.cpu1.toL2Bus.pkt_size::total 920606828 # Cumulative packet size per connected master and slave (bytes) 2822system.cpu1.toL2Bus.snoops 4866324 # Total snoops (count) 2823system.cpu1.toL2Bus.snoop_fanout::samples 20006897 # Request fanout histogram 2824system.cpu1.toL2Bus.snoop_fanout::mean 3.227379 # Request fanout histogram 2825system.cpu1.toL2Bus.snoop_fanout::stdev 0.419140 # Request fanout histogram |
| 2849system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2850system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2851system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2852system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 2826system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2827system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2828system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2829system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 2853system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 2854system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 2855system.cpu1.toL2Bus.snoop_fanout::5 15552442 75.65% 75.65% # Request fanout histogram 2856system.cpu1.toL2Bus.snoop_fanout::6 5006631 24.35% 100.00% # Request fanout histogram | 2830system.cpu1.toL2Bus.snoop_fanout::3 15457744 77.26% 77.26% # Request fanout histogram 2831system.cpu1.toL2Bus.snoop_fanout::4 4549153 22.74% 100.00% # Request fanout histogram |
| 2857system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 2832system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 2858system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 2859system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 2860system.cpu1.toL2Bus.snoop_fanout::total 20559073 # Request fanout histogram 2861system.cpu1.toL2Bus.reqLayer0.occupancy 11602796673 # Layer occupancy (ticks) | 2833system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 2834system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 2835system.cpu1.toL2Bus.snoop_fanout::total 20006897 # Request fanout histogram 2836system.cpu1.toL2Bus.reqLayer0.occupancy 11420254845 # Layer occupancy (ticks) |
| 2862system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 2837system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 2863system.cpu1.toL2Bus.snoopLayer0.occupancy 182870488 # Layer occupancy (ticks) | 2838system.cpu1.toL2Bus.snoopLayer0.occupancy 196151972 # Layer occupancy (ticks) |
| 2864system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2839system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2865system.cpu1.toL2Bus.respLayer0.occupancy 8299279905 # Layer occupancy (ticks) | 2840system.cpu1.toL2Bus.respLayer0.occupancy 8513145317 # Layer occupancy (ticks) |
| 2866system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 2841system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2867system.cpu1.toL2Bus.respLayer1.occupancy 7848510644 # Layer occupancy (ticks) | 2842system.cpu1.toL2Bus.respLayer1.occupancy 7729223292 # Layer occupancy (ticks) |
| 2868system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 2843system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 2869system.cpu1.toL2Bus.respLayer2.occupancy 224378946 # Layer occupancy (ticks) | 2844system.cpu1.toL2Bus.respLayer2.occupancy 225599484 # Layer occupancy (ticks) |
| 2870system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 2845system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2871system.cpu1.toL2Bus.respLayer3.occupancy 662954125 # Layer occupancy (ticks) | 2846system.cpu1.toL2Bus.respLayer3.occupancy 647309419 # Layer occupancy (ticks) |
| 2872system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2847system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2873system.iobus.trans_dist::ReadReq 40399 # Transaction distribution 2874system.iobus.trans_dist::ReadResp 40399 # Transaction distribution 2875system.iobus.trans_dist::WriteReq 136785 # Transaction distribution 2876system.iobus.trans_dist::WriteResp 30057 # Transaction distribution | 2848system.iobus.trans_dist::ReadReq 40298 # Transaction distribution 2849system.iobus.trans_dist::ReadResp 40298 # Transaction distribution 2850system.iobus.trans_dist::WriteReq 136633 # Transaction distribution 2851system.iobus.trans_dist::WriteResp 29905 # Transaction distribution |
| 2877system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution | 2852system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution |
| 2878system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48154 # Packet count per connected master and slave (bytes) | 2853system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47726 # Packet count per connected master and slave (bytes) |
| 2879system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2880system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2881system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2882system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2883system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2884system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2885system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2886system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2887system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) | 2854system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2855system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2856system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2857system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2858system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2859system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2860system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2861system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2862system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 2888system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) | 2863system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) |
| 2889system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2890system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2891system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2892system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | 2864system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2865system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2866system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2867system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 2893system.iobus.pkt_count_system.bridge.master::total 123088 # Packet count per connected master and slave (bytes) 2894system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231200 # Packet count per connected master and slave (bytes) 2895system.iobus.pkt_count_system.realview.ide.dma::total 231200 # Packet count per connected master and slave (bytes) | 2868system.iobus.pkt_count_system.bridge.master::total 122608 # Packet count per connected master and slave (bytes) 2869system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231174 # Packet count per connected master and slave (bytes) 2870system.iobus.pkt_count_system.realview.ide.dma::total 231174 # Packet count per connected master and slave (bytes) |
| 2896system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2897system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) | 2871system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2872system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) |
| 2898system.iobus.pkt_count::total 354368 # Packet count per connected master and slave (bytes) 2899system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48174 # Cumulative packet size per connected master and slave (bytes) | 2873system.iobus.pkt_count::total 353862 # Packet count per connected master and slave (bytes) 2874system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47746 # Cumulative packet size per connected master and slave (bytes) |
| 2900system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2901system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2902system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2903system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2904system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2905system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2906system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2907system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2908system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 2875system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2876system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2877system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2878system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2879system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2880system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2881system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2882system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2883system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 2909system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) | 2884system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) |
| 2910system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 2911system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2912system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 2913system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) | 2885system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 2886system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2887system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 2888system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) |
| 2914system.iobus.pkt_size_system.bridge.master::total 156195 # Cumulative packet size per connected master and slave (bytes) 2915system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338816 # Cumulative packet size per connected master and slave (bytes) 2916system.iobus.pkt_size_system.realview.ide.dma::total 7338816 # Cumulative packet size per connected master and slave (bytes) | 2889system.iobus.pkt_size_system.bridge.master::total 155738 # Cumulative packet size per connected master and slave (bytes) 2890system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338712 # Cumulative packet size per connected master and slave (bytes) 2891system.iobus.pkt_size_system.realview.ide.dma::total 7338712 # Cumulative packet size per connected master and slave (bytes) |
| 2917system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2918system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) | 2892system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2893system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) |
| 2919system.iobus.pkt_size::total 7497097 # Cumulative packet size per connected master and slave (bytes) 2920system.iobus.reqLayer0.occupancy 36604000 # Layer occupancy (ticks) | 2894system.iobus.pkt_size::total 7496536 # Cumulative packet size per connected master and slave (bytes) 2895system.iobus.reqLayer0.occupancy 36251000 # Layer occupancy (ticks) |
| 2921system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2922system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 2923system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2924system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 2925system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2926system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 2927system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2928system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2929system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2930system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2931system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2932system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2933system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2934system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2935system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2936system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 2937system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2938system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2939system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) | 2896system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2897system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 2898system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2899system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 2900system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2901system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 2902system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2903system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2904system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2905system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2906system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2907system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2908system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2909system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2910system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2911system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 2912system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2913system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2914system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) |
| 2940system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) | 2915system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) |
| 2941system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2942system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 2943system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2944system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 2945system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2946system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 2947system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 2916system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2917system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 2918system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2919system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 2920system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2921system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 2922system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 2948system.iobus.reqLayer27.occupancy 1043087367 # Layer occupancy (ticks) | 2923system.iobus.reqLayer27.occupancy 607686128 # Layer occupancy (ticks) |
| 2949system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2950system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2951system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 2924system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2925system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2926system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 2952system.iobus.respLayer0.occupancy 93034000 # Layer occupancy (ticks) | 2927system.iobus.respLayer0.occupancy 92706000 # Layer occupancy (ticks) |
| 2953system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 2928system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2954system.iobus.respLayer3.occupancy 179187461 # Layer occupancy (ticks) | 2929system.iobus.respLayer3.occupancy 148478785 # Layer occupancy (ticks) |
| 2955system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 2930system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2956system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) | 2931system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) |
| 2957system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) | 2932system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) |
| 2958system.iocache.tags.replacements 115604 # number of replacements 2959system.iocache.tags.tagsinuse 11.301402 # Cycle average of tags in use | 2933system.iocache.tags.replacements 115568 # number of replacements 2934system.iocache.tags.tagsinuse 11.294495 # Cycle average of tags in use |
| 2960system.iocache.tags.total_refs 3 # Total number of references to valid blocks. | 2935system.iocache.tags.total_refs 3 # Total number of references to valid blocks. |
| 2961system.iocache.tags.sampled_refs 115620 # Sample count of references to valid blocks. | 2936system.iocache.tags.sampled_refs 115584 # Sample count of references to valid blocks. |
| 2962system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. | 2937system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. |
| 2963system.iocache.tags.warmup_cycle 9117040369000 # Cycle when the warmup percentage was hit. 2964system.iocache.tags.occ_blocks::realview.ethernet 7.419209 # Average occupied blocks per requestor 2965system.iocache.tags.occ_blocks::realview.ide 3.882193 # Average occupied blocks per requestor 2966system.iocache.tags.occ_percent::realview.ethernet 0.463701 # Average percentage of cache occupancy 2967system.iocache.tags.occ_percent::realview.ide 0.242637 # Average percentage of cache occupancy 2968system.iocache.tags.occ_percent::total 0.706338 # Average percentage of cache occupancy | 2938system.iocache.tags.warmup_cycle 9116942023000 # Cycle when the warmup percentage was hit. 2939system.iocache.tags.occ_blocks::realview.ethernet 3.849176 # Average occupied blocks per requestor 2940system.iocache.tags.occ_blocks::realview.ide 7.445319 # Average occupied blocks per requestor 2941system.iocache.tags.occ_percent::realview.ethernet 0.240573 # Average percentage of cache occupancy 2942system.iocache.tags.occ_percent::realview.ide 0.465332 # Average percentage of cache occupancy 2943system.iocache.tags.occ_percent::total 0.705906 # Average percentage of cache occupancy |
| 2969system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2970system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2971system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 2944system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2945system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2946system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 2972system.iocache.tags.tag_accesses 1040757 # Number of tag accesses 2973system.iocache.tags.data_accesses 1040757 # Number of data accesses | 2947system.iocache.tags.tag_accesses 1040640 # Number of tag accesses 2948system.iocache.tags.data_accesses 1040640 # Number of data accesses |
| 2974system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses | 2949system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses |
| 2975system.iocache.ReadReq_misses::realview.ide 8872 # number of ReadReq misses 2976system.iocache.ReadReq_misses::total 8909 # number of ReadReq misses | 2950system.iocache.ReadReq_misses::realview.ide 8859 # number of ReadReq misses 2951system.iocache.ReadReq_misses::total 8896 # number of ReadReq misses |
| 2977system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2978system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2979system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses 2980system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses 2981system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses | 2952system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2953system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2954system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses 2955system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses 2956system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses |
| 2982system.iocache.demand_misses::realview.ide 8872 # number of demand (read+write) misses 2983system.iocache.demand_misses::total 8912 # number of demand (read+write) misses | 2957system.iocache.demand_misses::realview.ide 8859 # number of demand (read+write) misses 2958system.iocache.demand_misses::total 8899 # number of demand (read+write) misses |
| 2984system.iocache.overall_misses::realview.ethernet 40 # number of overall misses | 2959system.iocache.overall_misses::realview.ethernet 40 # number of overall misses |
| 2985system.iocache.overall_misses::realview.ide 8872 # number of overall misses 2986system.iocache.overall_misses::total 8912 # number of overall misses 2987system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles 2988system.iocache.ReadReq_miss_latency::realview.ide 1954318592 # number of ReadReq miss cycles 2989system.iocache.ReadReq_miss_latency::total 1960025592 # number of ReadReq miss cycles 2990system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles 2991system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles 2992system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28939092314 # number of WriteInvalidateReq miss cycles 2993system.iocache.WriteInvalidateReq_miss_latency::total 28939092314 # number of WriteInvalidateReq miss cycles 2994system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles 2995system.iocache.demand_miss_latency::realview.ide 1954318592 # number of demand (read+write) miss cycles 2996system.iocache.demand_miss_latency::total 1960382592 # number of demand (read+write) miss cycles 2997system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles 2998system.iocache.overall_miss_latency::realview.ide 1954318592 # number of overall miss cycles 2999system.iocache.overall_miss_latency::total 1960382592 # number of overall miss cycles | 2960system.iocache.overall_misses::realview.ide 8859 # number of overall misses 2961system.iocache.overall_misses::total 8899 # number of overall misses 2962system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles 2963system.iocache.ReadReq_miss_latency::realview.ide 1636729691 # number of ReadReq miss cycles 2964system.iocache.ReadReq_miss_latency::total 1641925191 # number of ReadReq miss cycles 2965system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2966system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2967system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19864825652 # number of WriteInvalidateReq miss cycles 2968system.iocache.WriteInvalidateReq_miss_latency::total 19864825652 # number of WriteInvalidateReq miss cycles 2969system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles 2970system.iocache.demand_miss_latency::realview.ide 1636729691 # number of demand (read+write) miss cycles 2971system.iocache.demand_miss_latency::total 1642294191 # number of demand (read+write) miss cycles 2972system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles 2973system.iocache.overall_miss_latency::realview.ide 1636729691 # number of overall miss cycles 2974system.iocache.overall_miss_latency::total 1642294191 # number of overall miss cycles |
| 3000system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) | 2975system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) |
| 3001system.iocache.ReadReq_accesses::realview.ide 8872 # number of ReadReq accesses(hits+misses) 3002system.iocache.ReadReq_accesses::total 8909 # number of ReadReq accesses(hits+misses) | 2976system.iocache.ReadReq_accesses::realview.ide 8859 # number of ReadReq accesses(hits+misses) 2977system.iocache.ReadReq_accesses::total 8896 # number of ReadReq accesses(hits+misses) |
| 3003system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 3004system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 3005system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) 3006system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) 3007system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses | 2978system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2979system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2980system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) 2981system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) 2982system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses |
| 3008system.iocache.demand_accesses::realview.ide 8872 # number of demand (read+write) accesses 3009system.iocache.demand_accesses::total 8912 # number of demand (read+write) accesses | 2983system.iocache.demand_accesses::realview.ide 8859 # number of demand (read+write) accesses 2984system.iocache.demand_accesses::total 8899 # number of demand (read+write) accesses |
| 3010system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses | 2985system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses |
| 3011system.iocache.overall_accesses::realview.ide 8872 # number of overall (read+write) accesses 3012system.iocache.overall_accesses::total 8912 # number of overall (read+write) accesses | 2986system.iocache.overall_accesses::realview.ide 8859 # number of overall (read+write) accesses 2987system.iocache.overall_accesses::total 8899 # number of overall (read+write) accesses |
| 3013system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 3014system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 3015system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3016system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 3017system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 3018system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 3019system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 3020system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 3021system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 3022system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3023system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 3024system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 3025system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 2988system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2989system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2990system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2991system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2992system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2993system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2994system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 2995system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2996system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2997system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2998system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2999system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 3000system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 3026system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency 3027system.iocache.ReadReq_avg_miss_latency::realview.ide 220279.372408 # average ReadReq miss latency 3028system.iocache.ReadReq_avg_miss_latency::total 220005.117522 # average ReadReq miss latency 3029system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency 3030system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency 3031system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271148.080298 # average WriteInvalidateReq miss latency 3032system.iocache.WriteInvalidateReq_avg_miss_latency::total 271148.080298 # average WriteInvalidateReq miss latency 3033system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency 3034system.iocache.demand_avg_miss_latency::realview.ide 220279.372408 # average overall miss latency 3035system.iocache.demand_avg_miss_latency::total 219971.116697 # average overall miss latency 3036system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency 3037system.iocache.overall_avg_miss_latency::realview.ide 220279.372408 # average overall miss latency 3038system.iocache.overall_avg_miss_latency::total 219971.116697 # average overall miss latency 3039system.iocache.blocked_cycles::no_mshrs 228427 # number of cycles access was blocked | 3001system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency 3002system.iocache.ReadReq_avg_miss_latency::realview.ide 184753.323287 # average ReadReq miss latency 3003system.iocache.ReadReq_avg_miss_latency::total 184568.928844 # average ReadReq miss latency 3004system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 3005system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 3006system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186125.718200 # average WriteInvalidateReq miss latency 3007system.iocache.WriteInvalidateReq_avg_miss_latency::total 186125.718200 # average WriteInvalidateReq miss latency 3008system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency 3009system.iocache.demand_avg_miss_latency::realview.ide 184753.323287 # average overall miss latency 3010system.iocache.demand_avg_miss_latency::total 184548.172941 # average overall miss latency 3011system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency 3012system.iocache.overall_avg_miss_latency::realview.ide 184753.323287 # average overall miss latency 3013system.iocache.overall_avg_miss_latency::total 184548.172941 # average overall miss latency 3014system.iocache.blocked_cycles::no_mshrs 112586 # number of cycles access was blocked |
| 3040system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 3015system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 3041system.iocache.blocked::no_mshrs 27535 # number of cycles access was blocked | 3016system.iocache.blocked::no_mshrs 16234 # number of cycles access was blocked |
| 3042system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 3017system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 3043system.iocache.avg_blocked_cycles::no_mshrs 8.295878 # average number of cycles each access was blocked | 3018system.iocache.avg_blocked_cycles::no_mshrs 6.935198 # average number of cycles each access was blocked |
| 3044system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3045system.iocache.fast_writes 0 # number of fast writes performed 3046system.iocache.cache_copies 0 # number of cache copies performed | 3019system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3020system.iocache.fast_writes 0 # number of fast writes performed 3021system.iocache.cache_copies 0 # number of cache copies performed |
| 3047system.iocache.writebacks::writebacks 106702 # number of writebacks 3048system.iocache.writebacks::total 106702 # number of writebacks | 3022system.iocache.writebacks::writebacks 106694 # number of writebacks 3023system.iocache.writebacks::total 106694 # number of writebacks |
| 3049system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses | 3024system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses |
| 3050system.iocache.ReadReq_mshr_misses::realview.ide 8872 # number of ReadReq MSHR misses 3051system.iocache.ReadReq_mshr_misses::total 8909 # number of ReadReq MSHR misses | 3025system.iocache.ReadReq_mshr_misses::realview.ide 8859 # number of ReadReq MSHR misses 3026system.iocache.ReadReq_mshr_misses::total 8896 # number of ReadReq MSHR misses |
| 3052system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 3053system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 3054system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses 3055system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses 3056system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses | 3027system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 3028system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 3029system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses 3030system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses 3031system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses |
| 3057system.iocache.demand_mshr_misses::realview.ide 8872 # number of demand (read+write) MSHR misses 3058system.iocache.demand_mshr_misses::total 8912 # number of demand (read+write) MSHR misses | 3032system.iocache.demand_mshr_misses::realview.ide 8859 # number of demand (read+write) MSHR misses 3033system.iocache.demand_mshr_misses::total 8899 # number of demand (read+write) MSHR misses |
| 3059system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses | 3034system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses |
| 3060system.iocache.overall_mshr_misses::realview.ide 8872 # number of overall MSHR misses 3061system.iocache.overall_mshr_misses::total 8912 # number of overall MSHR misses 3062system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles 3063system.iocache.ReadReq_mshr_miss_latency::realview.ide 1492830122 # number of ReadReq MSHR miss cycles 3064system.iocache.ReadReq_mshr_miss_latency::total 1496613122 # number of ReadReq MSHR miss cycles 3065system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 3066system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 3067system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23388843706 # number of WriteInvalidateReq MSHR miss cycles 3068system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23388843706 # number of WriteInvalidateReq MSHR miss cycles 3069system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles 3070system.iocache.demand_mshr_miss_latency::realview.ide 1492830122 # number of demand (read+write) MSHR miss cycles 3071system.iocache.demand_mshr_miss_latency::total 1496814122 # number of demand (read+write) MSHR miss cycles 3072system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles 3073system.iocache.overall_mshr_miss_latency::realview.ide 1492830122 # number of overall MSHR miss cycles 3074system.iocache.overall_mshr_miss_latency::total 1496814122 # number of overall MSHR miss cycles | 3035system.iocache.overall_mshr_misses::realview.ide 8859 # number of overall MSHR misses 3036system.iocache.overall_mshr_misses::total 8899 # number of overall MSHR misses 3037system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles 3038system.iocache.ReadReq_mshr_miss_latency::realview.ide 1174861151 # number of ReadReq MSHR miss cycles 3039system.iocache.ReadReq_mshr_miss_latency::total 1178131651 # number of ReadReq MSHR miss cycles 3040system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles 3041system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles 3042system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14314859762 # number of WriteInvalidateReq MSHR miss cycles 3043system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14314859762 # number of WriteInvalidateReq MSHR miss cycles 3044system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles 3045system.iocache.demand_mshr_miss_latency::realview.ide 1174861151 # number of demand (read+write) MSHR miss cycles 3046system.iocache.demand_mshr_miss_latency::total 1178344651 # number of demand (read+write) MSHR miss cycles 3047system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles 3048system.iocache.overall_mshr_miss_latency::realview.ide 1174861151 # number of overall MSHR miss cycles 3049system.iocache.overall_mshr_miss_latency::total 1178344651 # number of overall MSHR miss cycles |
| 3075system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 3076system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3077system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3078system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 3079system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 3080system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 3081system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 3082system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 3083system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3084system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3085system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 3086system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3087system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 3050system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 3051system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3052system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3053system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 3054system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 3055system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 3056system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 3057system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 3058system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3059system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3060system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 3061system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3062system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 3088system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency 3089system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168263.088593 # average ReadReq mshr miss latency 3090system.iocache.ReadReq_avg_mshr_miss_latency::total 167988.901336 # average ReadReq mshr miss latency 3091system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 3092system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 3093system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219144.401713 # average WriteInvalidateReq mshr miss latency 3094system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219144.401713 # average WriteInvalidateReq mshr miss latency 3095system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency 3096system.iocache.demand_avg_mshr_miss_latency::realview.ide 168263.088593 # average overall mshr miss latency 3097system.iocache.demand_avg_mshr_miss_latency::total 167954.905969 # average overall mshr miss latency 3098system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency 3099system.iocache.overall_avg_mshr_miss_latency::realview.ide 168263.088593 # average overall mshr miss latency 3100system.iocache.overall_avg_mshr_miss_latency::total 167954.905969 # average overall mshr miss latency | 3063system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency 3064system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132617.806863 # average ReadReq mshr miss latency 3065system.iocache.ReadReq_avg_mshr_miss_latency::total 132433.863647 # average ReadReq mshr miss latency 3066system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency 3067system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency 3068system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134124.688573 # average WriteInvalidateReq mshr miss latency 3069system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134124.688573 # average WriteInvalidateReq mshr miss latency 3070system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency 3071system.iocache.demand_avg_mshr_miss_latency::realview.ide 132617.806863 # average overall mshr miss latency 3072system.iocache.demand_avg_mshr_miss_latency::total 132413.153276 # average overall mshr miss latency 3073system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency 3074system.iocache.overall_avg_mshr_miss_latency::realview.ide 132617.806863 # average overall mshr miss latency 3075system.iocache.overall_avg_mshr_miss_latency::total 132413.153276 # average overall mshr miss latency |
| 3101system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 3076system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 3102system.l2c.tags.replacements 1613331 # number of replacements 3103system.l2c.tags.tagsinuse 64339.343113 # Cycle average of tags in use 3104system.l2c.tags.total_refs 4797018 # Total number of references to valid blocks. 3105system.l2c.tags.sampled_refs 1673818 # Sample count of references to valid blocks. 3106system.l2c.tags.avg_refs 2.865914 # Average number of references to valid blocks. 3107system.l2c.tags.warmup_cycle 3243842500 # Cycle when the warmup percentage was hit. 3108system.l2c.tags.occ_blocks::writebacks 19101.398352 # Average occupied blocks per requestor 3109system.l2c.tags.occ_blocks::cpu0.dtb.walker 185.742619 # Average occupied blocks per requestor 3110system.l2c.tags.occ_blocks::cpu0.itb.walker 228.186438 # Average occupied blocks per requestor 3111system.l2c.tags.occ_blocks::cpu0.inst 3981.341018 # Average occupied blocks per requestor 3112system.l2c.tags.occ_blocks::cpu0.data 11353.199987 # Average occupied blocks per requestor 3113system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11643.208368 # Average occupied blocks per requestor 3114system.l2c.tags.occ_blocks::cpu1.dtb.walker 179.349370 # Average occupied blocks per requestor 3115system.l2c.tags.occ_blocks::cpu1.itb.walker 266.651363 # Average occupied blocks per requestor 3116system.l2c.tags.occ_blocks::cpu1.inst 3248.685748 # Average occupied blocks per requestor 3117system.l2c.tags.occ_blocks::cpu1.data 4974.329517 # Average occupied blocks per requestor 3118system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9177.250333 # Average occupied blocks per requestor 3119system.l2c.tags.occ_percent::writebacks 0.291464 # Average percentage of cache occupancy 3120system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002834 # Average percentage of cache occupancy 3121system.l2c.tags.occ_percent::cpu0.itb.walker 0.003482 # Average percentage of cache occupancy 3122system.l2c.tags.occ_percent::cpu0.inst 0.060750 # Average percentage of cache occupancy 3123system.l2c.tags.occ_percent::cpu0.data 0.173236 # Average percentage of cache occupancy 3124system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.177661 # Average percentage of cache occupancy 3125system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002737 # Average percentage of cache occupancy 3126system.l2c.tags.occ_percent::cpu1.itb.walker 0.004069 # Average percentage of cache occupancy 3127system.l2c.tags.occ_percent::cpu1.inst 0.049571 # Average percentage of cache occupancy 3128system.l2c.tags.occ_percent::cpu1.data 0.075902 # Average percentage of cache occupancy 3129system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.140034 # Average percentage of cache occupancy 3130system.l2c.tags.occ_percent::total 0.981740 # Average percentage of cache occupancy 3131system.l2c.tags.occ_task_id_blocks::1022 10683 # Occupied blocks per task id 3132system.l2c.tags.occ_task_id_blocks::1023 245 # Occupied blocks per task id 3133system.l2c.tags.occ_task_id_blocks::1024 49559 # Occupied blocks per task id 3134system.l2c.tags.age_task_id_blocks_1022::0 76 # Occupied blocks per task id 3135system.l2c.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id 3136system.l2c.tags.age_task_id_blocks_1022::2 157 # Occupied blocks per task id 3137system.l2c.tags.age_task_id_blocks_1022::3 995 # Occupied blocks per task id 3138system.l2c.tags.age_task_id_blocks_1022::4 9444 # Occupied blocks per task id 3139system.l2c.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id 3140system.l2c.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id 3141system.l2c.tags.age_task_id_blocks_1023::4 227 # Occupied blocks per task id 3142system.l2c.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id 3143system.l2c.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id 3144system.l2c.tags.age_task_id_blocks_1024::2 3090 # Occupied blocks per task id 3145system.l2c.tags.age_task_id_blocks_1024::3 3968 # Occupied blocks per task id 3146system.l2c.tags.age_task_id_blocks_1024::4 42149 # Occupied blocks per task id 3147system.l2c.tags.occ_task_id_percent::1022 0.163010 # Percentage of cache occupancy per task id 3148system.l2c.tags.occ_task_id_percent::1023 0.003738 # Percentage of cache occupancy per task id 3149system.l2c.tags.occ_task_id_percent::1024 0.756210 # Percentage of cache occupancy per task id 3150system.l2c.tags.tag_accesses 64781750 # Number of tag accesses 3151system.l2c.tags.data_accesses 64781750 # Number of data accesses 3152system.l2c.ReadReq_hits::cpu0.dtb.walker 6508 # number of ReadReq hits 3153system.l2c.ReadReq_hits::cpu0.itb.walker 4319 # number of ReadReq hits 3154system.l2c.ReadReq_hits::cpu0.inst 640995 # number of ReadReq hits 3155system.l2c.ReadReq_hits::cpu0.data 651108 # number of ReadReq hits 3156system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 307248 # number of ReadReq hits 3157system.l2c.ReadReq_hits::cpu1.dtb.walker 6236 # number of ReadReq hits 3158system.l2c.ReadReq_hits::cpu1.itb.walker 4043 # number of ReadReq hits 3159system.l2c.ReadReq_hits::cpu1.inst 550704 # number of ReadReq hits 3160system.l2c.ReadReq_hits::cpu1.data 545723 # number of ReadReq hits 3161system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 278481 # number of ReadReq hits 3162system.l2c.ReadReq_hits::total 2995365 # number of ReadReq hits 3163system.l2c.Writeback_hits::writebacks 2564009 # number of Writeback hits 3164system.l2c.Writeback_hits::total 2564009 # number of Writeback hits 3165system.l2c.WriteInvalidateReq_hits::cpu0.data 138658 # number of WriteInvalidateReq hits 3166system.l2c.WriteInvalidateReq_hits::cpu1.data 123170 # number of WriteInvalidateReq hits 3167system.l2c.WriteInvalidateReq_hits::total 261828 # number of WriteInvalidateReq hits 3168system.l2c.UpgradeReq_hits::cpu0.data 30955 # number of UpgradeReq hits 3169system.l2c.UpgradeReq_hits::cpu1.data 32781 # number of UpgradeReq hits 3170system.l2c.UpgradeReq_hits::total 63736 # number of UpgradeReq hits 3171system.l2c.SCUpgradeReq_hits::cpu0.data 6525 # number of SCUpgradeReq hits 3172system.l2c.SCUpgradeReq_hits::cpu1.data 5847 # number of SCUpgradeReq hits 3173system.l2c.SCUpgradeReq_hits::total 12372 # number of SCUpgradeReq hits 3174system.l2c.ReadExReq_hits::cpu0.data 54058 # number of ReadExReq hits 3175system.l2c.ReadExReq_hits::cpu1.data 53543 # number of ReadExReq hits 3176system.l2c.ReadExReq_hits::total 107601 # number of ReadExReq hits 3177system.l2c.demand_hits::cpu0.dtb.walker 6508 # number of demand (read+write) hits 3178system.l2c.demand_hits::cpu0.itb.walker 4319 # number of demand (read+write) hits 3179system.l2c.demand_hits::cpu0.inst 640995 # number of demand (read+write) hits 3180system.l2c.demand_hits::cpu0.data 705166 # number of demand (read+write) hits 3181system.l2c.demand_hits::cpu0.l2cache.prefetcher 307248 # number of demand (read+write) hits 3182system.l2c.demand_hits::cpu1.dtb.walker 6236 # number of demand (read+write) hits 3183system.l2c.demand_hits::cpu1.itb.walker 4043 # number of demand (read+write) hits 3184system.l2c.demand_hits::cpu1.inst 550704 # number of demand (read+write) hits 3185system.l2c.demand_hits::cpu1.data 599266 # number of demand (read+write) hits 3186system.l2c.demand_hits::cpu1.l2cache.prefetcher 278481 # number of demand (read+write) hits 3187system.l2c.demand_hits::total 3102966 # number of demand (read+write) hits 3188system.l2c.overall_hits::cpu0.dtb.walker 6508 # number of overall hits 3189system.l2c.overall_hits::cpu0.itb.walker 4319 # number of overall hits 3190system.l2c.overall_hits::cpu0.inst 640995 # number of overall hits 3191system.l2c.overall_hits::cpu0.data 705166 # number of overall hits 3192system.l2c.overall_hits::cpu0.l2cache.prefetcher 307248 # number of overall hits 3193system.l2c.overall_hits::cpu1.dtb.walker 6236 # number of overall hits 3194system.l2c.overall_hits::cpu1.itb.walker 4043 # number of overall hits 3195system.l2c.overall_hits::cpu1.inst 550704 # number of overall hits 3196system.l2c.overall_hits::cpu1.data 599266 # number of overall hits 3197system.l2c.overall_hits::cpu1.l2cache.prefetcher 278481 # number of overall hits 3198system.l2c.overall_hits::total 3102966 # number of overall hits 3199system.l2c.ReadReq_misses::cpu0.dtb.walker 2518 # number of ReadReq misses 3200system.l2c.ReadReq_misses::cpu0.itb.walker 2288 # number of ReadReq misses 3201system.l2c.ReadReq_misses::cpu0.inst 61626 # number of ReadReq misses 3202system.l2c.ReadReq_misses::cpu0.data 165027 # number of ReadReq misses 3203system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 315511 # number of ReadReq misses 3204system.l2c.ReadReq_misses::cpu1.dtb.walker 2810 # number of ReadReq misses 3205system.l2c.ReadReq_misses::cpu1.itb.walker 2444 # number of ReadReq misses 3206system.l2c.ReadReq_misses::cpu1.inst 54313 # number of ReadReq misses 3207system.l2c.ReadReq_misses::cpu1.data 130678 # number of ReadReq misses 3208system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 226783 # number of ReadReq misses 3209system.l2c.ReadReq_misses::total 963998 # number of ReadReq misses 3210system.l2c.WriteInvalidateReq_misses::cpu0.data 490361 # number of WriteInvalidateReq misses 3211system.l2c.WriteInvalidateReq_misses::cpu1.data 96104 # number of WriteInvalidateReq misses 3212system.l2c.WriteInvalidateReq_misses::total 586465 # number of WriteInvalidateReq misses 3213system.l2c.UpgradeReq_misses::cpu0.data 48125 # number of UpgradeReq misses 3214system.l2c.UpgradeReq_misses::cpu1.data 46732 # number of UpgradeReq misses 3215system.l2c.UpgradeReq_misses::total 94857 # number of UpgradeReq misses 3216system.l2c.SCUpgradeReq_misses::cpu0.data 10442 # number of SCUpgradeReq misses 3217system.l2c.SCUpgradeReq_misses::cpu1.data 8446 # number of SCUpgradeReq misses 3218system.l2c.SCUpgradeReq_misses::total 18888 # number of SCUpgradeReq misses 3219system.l2c.ReadExReq_misses::cpu0.data 87770 # number of ReadExReq misses 3220system.l2c.ReadExReq_misses::cpu1.data 52309 # number of ReadExReq misses 3221system.l2c.ReadExReq_misses::total 140079 # number of ReadExReq misses 3222system.l2c.demand_misses::cpu0.dtb.walker 2518 # number of demand (read+write) misses 3223system.l2c.demand_misses::cpu0.itb.walker 2288 # number of demand (read+write) misses 3224system.l2c.demand_misses::cpu0.inst 61626 # number of demand (read+write) misses 3225system.l2c.demand_misses::cpu0.data 252797 # number of demand (read+write) misses 3226system.l2c.demand_misses::cpu0.l2cache.prefetcher 315511 # number of demand (read+write) misses 3227system.l2c.demand_misses::cpu1.dtb.walker 2810 # number of demand (read+write) misses 3228system.l2c.demand_misses::cpu1.itb.walker 2444 # number of demand (read+write) misses 3229system.l2c.demand_misses::cpu1.inst 54313 # number of demand (read+write) misses 3230system.l2c.demand_misses::cpu1.data 182987 # number of demand (read+write) misses 3231system.l2c.demand_misses::cpu1.l2cache.prefetcher 226783 # number of demand (read+write) misses 3232system.l2c.demand_misses::total 1104077 # number of demand (read+write) misses 3233system.l2c.overall_misses::cpu0.dtb.walker 2518 # number of overall misses 3234system.l2c.overall_misses::cpu0.itb.walker 2288 # number of overall misses 3235system.l2c.overall_misses::cpu0.inst 61626 # number of overall misses 3236system.l2c.overall_misses::cpu0.data 252797 # number of overall misses 3237system.l2c.overall_misses::cpu0.l2cache.prefetcher 315511 # number of overall misses 3238system.l2c.overall_misses::cpu1.dtb.walker 2810 # number of overall misses 3239system.l2c.overall_misses::cpu1.itb.walker 2444 # number of overall misses 3240system.l2c.overall_misses::cpu1.inst 54313 # number of overall misses 3241system.l2c.overall_misses::cpu1.data 182987 # number of overall misses 3242system.l2c.overall_misses::cpu1.l2cache.prefetcher 226783 # number of overall misses 3243system.l2c.overall_misses::total 1104077 # number of overall misses 3244system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 214285749 # number of ReadReq miss cycles 3245system.l2c.ReadReq_miss_latency::cpu0.itb.walker 198628497 # number of ReadReq miss cycles 3246system.l2c.ReadReq_miss_latency::cpu0.inst 4954310957 # number of ReadReq miss cycles 3247system.l2c.ReadReq_miss_latency::cpu0.data 15651071560 # number of ReadReq miss cycles 3248system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 48231685466 # number of ReadReq miss cycles 3249system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 246385494 # number of ReadReq miss cycles 3250system.l2c.ReadReq_miss_latency::cpu1.itb.walker 217660244 # number of ReadReq miss cycles 3251system.l2c.ReadReq_miss_latency::cpu1.inst 4359245951 # number of ReadReq miss cycles 3252system.l2c.ReadReq_miss_latency::cpu1.data 12707402041 # number of ReadReq miss cycles 3253system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 33186692902 # number of ReadReq miss cycles 3254system.l2c.ReadReq_miss_latency::total 119967368861 # number of ReadReq miss cycles 3255system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 38113099 # number of WriteInvalidateReq miss cycles 3256system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 39381504 # number of WriteInvalidateReq miss cycles 3257system.l2c.WriteInvalidateReq_miss_latency::total 77494603 # number of WriteInvalidateReq miss cycles 3258system.l2c.UpgradeReq_miss_latency::cpu0.data 206747895 # number of UpgradeReq miss cycles 3259system.l2c.UpgradeReq_miss_latency::cpu1.data 214995003 # number of UpgradeReq miss cycles 3260system.l2c.UpgradeReq_miss_latency::total 421742898 # number of UpgradeReq miss cycles 3261system.l2c.SCUpgradeReq_miss_latency::cpu0.data 39945327 # number of SCUpgradeReq miss cycles 3262system.l2c.SCUpgradeReq_miss_latency::cpu1.data 36079463 # number of SCUpgradeReq miss cycles 3263system.l2c.SCUpgradeReq_miss_latency::total 76024790 # number of SCUpgradeReq miss cycles 3264system.l2c.ReadExReq_miss_latency::cpu0.data 7797935308 # number of ReadExReq miss cycles 3265system.l2c.ReadExReq_miss_latency::cpu1.data 4285574180 # number of ReadExReq miss cycles 3266system.l2c.ReadExReq_miss_latency::total 12083509488 # number of ReadExReq miss cycles 3267system.l2c.demand_miss_latency::cpu0.dtb.walker 214285749 # number of demand (read+write) miss cycles 3268system.l2c.demand_miss_latency::cpu0.itb.walker 198628497 # number of demand (read+write) miss cycles 3269system.l2c.demand_miss_latency::cpu0.inst 4954310957 # number of demand (read+write) miss cycles 3270system.l2c.demand_miss_latency::cpu0.data 23449006868 # number of demand (read+write) miss cycles 3271system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 48231685466 # number of demand (read+write) miss cycles 3272system.l2c.demand_miss_latency::cpu1.dtb.walker 246385494 # number of demand (read+write) miss cycles 3273system.l2c.demand_miss_latency::cpu1.itb.walker 217660244 # number of demand (read+write) miss cycles 3274system.l2c.demand_miss_latency::cpu1.inst 4359245951 # number of demand (read+write) miss cycles 3275system.l2c.demand_miss_latency::cpu1.data 16992976221 # number of demand (read+write) miss cycles 3276system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 33186692902 # number of demand (read+write) miss cycles 3277system.l2c.demand_miss_latency::total 132050878349 # number of demand (read+write) miss cycles 3278system.l2c.overall_miss_latency::cpu0.dtb.walker 214285749 # number of overall miss cycles 3279system.l2c.overall_miss_latency::cpu0.itb.walker 198628497 # number of overall miss cycles 3280system.l2c.overall_miss_latency::cpu0.inst 4954310957 # number of overall miss cycles 3281system.l2c.overall_miss_latency::cpu0.data 23449006868 # number of overall miss cycles 3282system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 48231685466 # number of overall miss cycles 3283system.l2c.overall_miss_latency::cpu1.dtb.walker 246385494 # number of overall miss cycles 3284system.l2c.overall_miss_latency::cpu1.itb.walker 217660244 # number of overall miss cycles 3285system.l2c.overall_miss_latency::cpu1.inst 4359245951 # number of overall miss cycles 3286system.l2c.overall_miss_latency::cpu1.data 16992976221 # number of overall miss cycles 3287system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 33186692902 # number of overall miss cycles 3288system.l2c.overall_miss_latency::total 132050878349 # number of overall miss cycles 3289system.l2c.ReadReq_accesses::cpu0.dtb.walker 9026 # number of ReadReq accesses(hits+misses) 3290system.l2c.ReadReq_accesses::cpu0.itb.walker 6607 # number of ReadReq accesses(hits+misses) 3291system.l2c.ReadReq_accesses::cpu0.inst 702621 # number of ReadReq accesses(hits+misses) 3292system.l2c.ReadReq_accesses::cpu0.data 816135 # number of ReadReq accesses(hits+misses) 3293system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 622759 # number of ReadReq accesses(hits+misses) 3294system.l2c.ReadReq_accesses::cpu1.dtb.walker 9046 # number of ReadReq accesses(hits+misses) 3295system.l2c.ReadReq_accesses::cpu1.itb.walker 6487 # number of ReadReq accesses(hits+misses) 3296system.l2c.ReadReq_accesses::cpu1.inst 605017 # number of ReadReq accesses(hits+misses) 3297system.l2c.ReadReq_accesses::cpu1.data 676401 # number of ReadReq accesses(hits+misses) 3298system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 505264 # number of ReadReq accesses(hits+misses) 3299system.l2c.ReadReq_accesses::total 3959363 # number of ReadReq accesses(hits+misses) 3300system.l2c.Writeback_accesses::writebacks 2564009 # number of Writeback accesses(hits+misses) 3301system.l2c.Writeback_accesses::total 2564009 # number of Writeback accesses(hits+misses) 3302system.l2c.WriteInvalidateReq_accesses::cpu0.data 629019 # number of WriteInvalidateReq accesses(hits+misses) 3303system.l2c.WriteInvalidateReq_accesses::cpu1.data 219274 # number of WriteInvalidateReq accesses(hits+misses) 3304system.l2c.WriteInvalidateReq_accesses::total 848293 # number of WriteInvalidateReq accesses(hits+misses) 3305system.l2c.UpgradeReq_accesses::cpu0.data 79080 # number of UpgradeReq accesses(hits+misses) 3306system.l2c.UpgradeReq_accesses::cpu1.data 79513 # number of UpgradeReq accesses(hits+misses) 3307system.l2c.UpgradeReq_accesses::total 158593 # number of UpgradeReq accesses(hits+misses) 3308system.l2c.SCUpgradeReq_accesses::cpu0.data 16967 # number of SCUpgradeReq accesses(hits+misses) 3309system.l2c.SCUpgradeReq_accesses::cpu1.data 14293 # number of SCUpgradeReq accesses(hits+misses) 3310system.l2c.SCUpgradeReq_accesses::total 31260 # number of SCUpgradeReq accesses(hits+misses) 3311system.l2c.ReadExReq_accesses::cpu0.data 141828 # number of ReadExReq accesses(hits+misses) 3312system.l2c.ReadExReq_accesses::cpu1.data 105852 # number of ReadExReq accesses(hits+misses) 3313system.l2c.ReadExReq_accesses::total 247680 # number of ReadExReq accesses(hits+misses) 3314system.l2c.demand_accesses::cpu0.dtb.walker 9026 # number of demand (read+write) accesses 3315system.l2c.demand_accesses::cpu0.itb.walker 6607 # number of demand (read+write) accesses 3316system.l2c.demand_accesses::cpu0.inst 702621 # number of demand (read+write) accesses 3317system.l2c.demand_accesses::cpu0.data 957963 # number of demand (read+write) accesses 3318system.l2c.demand_accesses::cpu0.l2cache.prefetcher 622759 # number of demand (read+write) accesses 3319system.l2c.demand_accesses::cpu1.dtb.walker 9046 # number of demand (read+write) accesses 3320system.l2c.demand_accesses::cpu1.itb.walker 6487 # number of demand (read+write) accesses 3321system.l2c.demand_accesses::cpu1.inst 605017 # number of demand (read+write) accesses 3322system.l2c.demand_accesses::cpu1.data 782253 # number of demand (read+write) accesses 3323system.l2c.demand_accesses::cpu1.l2cache.prefetcher 505264 # number of demand (read+write) accesses 3324system.l2c.demand_accesses::total 4207043 # number of demand (read+write) accesses 3325system.l2c.overall_accesses::cpu0.dtb.walker 9026 # number of overall (read+write) accesses 3326system.l2c.overall_accesses::cpu0.itb.walker 6607 # number of overall (read+write) accesses 3327system.l2c.overall_accesses::cpu0.inst 702621 # number of overall (read+write) accesses 3328system.l2c.overall_accesses::cpu0.data 957963 # number of overall (read+write) accesses 3329system.l2c.overall_accesses::cpu0.l2cache.prefetcher 622759 # number of overall (read+write) accesses 3330system.l2c.overall_accesses::cpu1.dtb.walker 9046 # number of overall (read+write) accesses 3331system.l2c.overall_accesses::cpu1.itb.walker 6487 # number of overall (read+write) accesses 3332system.l2c.overall_accesses::cpu1.inst 605017 # number of overall (read+write) accesses 3333system.l2c.overall_accesses::cpu1.data 782253 # number of overall (read+write) accesses 3334system.l2c.overall_accesses::cpu1.l2cache.prefetcher 505264 # number of overall (read+write) accesses 3335system.l2c.overall_accesses::total 4207043 # number of overall (read+write) accesses 3336system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.278972 # miss rate for ReadReq accesses 3337system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.346299 # miss rate for ReadReq accesses 3338system.l2c.ReadReq_miss_rate::cpu0.inst 0.087709 # miss rate for ReadReq accesses 3339system.l2c.ReadReq_miss_rate::cpu0.data 0.202206 # miss rate for ReadReq accesses 3340system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.506634 # miss rate for ReadReq accesses 3341system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.310635 # miss rate for ReadReq accesses 3342system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.376754 # miss rate for ReadReq accesses 3343system.l2c.ReadReq_miss_rate::cpu1.inst 0.089771 # miss rate for ReadReq accesses 3344system.l2c.ReadReq_miss_rate::cpu1.data 0.193196 # miss rate for ReadReq accesses 3345system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.448841 # miss rate for ReadReq accesses 3346system.l2c.ReadReq_miss_rate::total 0.243473 # miss rate for ReadReq accesses 3347system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.779565 # miss rate for WriteInvalidateReq accesses 3348system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.438283 # miss rate for WriteInvalidateReq accesses 3349system.l2c.WriteInvalidateReq_miss_rate::total 0.691347 # miss rate for WriteInvalidateReq accesses 3350system.l2c.UpgradeReq_miss_rate::cpu0.data 0.608561 # miss rate for UpgradeReq accesses 3351system.l2c.UpgradeReq_miss_rate::cpu1.data 0.587728 # miss rate for UpgradeReq accesses 3352system.l2c.UpgradeReq_miss_rate::total 0.598116 # miss rate for UpgradeReq accesses 3353system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.615430 # miss rate for SCUpgradeReq accesses 3354system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.590919 # miss rate for SCUpgradeReq accesses 3355system.l2c.SCUpgradeReq_miss_rate::total 0.604223 # miss rate for SCUpgradeReq accesses 3356system.l2c.ReadExReq_miss_rate::cpu0.data 0.618848 # miss rate for ReadExReq accesses 3357system.l2c.ReadExReq_miss_rate::cpu1.data 0.494171 # miss rate for ReadExReq accesses 3358system.l2c.ReadExReq_miss_rate::total 0.565564 # miss rate for ReadExReq accesses 3359system.l2c.demand_miss_rate::cpu0.dtb.walker 0.278972 # miss rate for demand accesses 3360system.l2c.demand_miss_rate::cpu0.itb.walker 0.346299 # miss rate for demand accesses 3361system.l2c.demand_miss_rate::cpu0.inst 0.087709 # miss rate for demand accesses 3362system.l2c.demand_miss_rate::cpu0.data 0.263890 # miss rate for demand accesses 3363system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.506634 # miss rate for demand accesses 3364system.l2c.demand_miss_rate::cpu1.dtb.walker 0.310635 # miss rate for demand accesses 3365system.l2c.demand_miss_rate::cpu1.itb.walker 0.376754 # miss rate for demand accesses 3366system.l2c.demand_miss_rate::cpu1.inst 0.089771 # miss rate for demand accesses 3367system.l2c.demand_miss_rate::cpu1.data 0.233923 # miss rate for demand accesses 3368system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.448841 # miss rate for demand accesses 3369system.l2c.demand_miss_rate::total 0.262435 # miss rate for demand accesses 3370system.l2c.overall_miss_rate::cpu0.dtb.walker 0.278972 # miss rate for overall accesses 3371system.l2c.overall_miss_rate::cpu0.itb.walker 0.346299 # miss rate for overall accesses 3372system.l2c.overall_miss_rate::cpu0.inst 0.087709 # miss rate for overall accesses 3373system.l2c.overall_miss_rate::cpu0.data 0.263890 # miss rate for overall accesses 3374system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.506634 # miss rate for overall accesses 3375system.l2c.overall_miss_rate::cpu1.dtb.walker 0.310635 # miss rate for overall accesses 3376system.l2c.overall_miss_rate::cpu1.itb.walker 0.376754 # miss rate for overall accesses 3377system.l2c.overall_miss_rate::cpu1.inst 0.089771 # miss rate for overall accesses 3378system.l2c.overall_miss_rate::cpu1.data 0.233923 # miss rate for overall accesses 3379system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.448841 # miss rate for overall accesses 3380system.l2c.overall_miss_rate::total 0.262435 # miss rate for overall accesses 3381system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 85101.568308 # average ReadReq miss latency 3382system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 86813.154283 # average ReadReq miss latency 3383system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80393.193733 # average ReadReq miss latency 3384system.l2c.ReadReq_avg_miss_latency::cpu0.data 94839.459967 # average ReadReq miss latency 3385system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 152868.475159 # average ReadReq miss latency 3386system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87681.670463 # average ReadReq miss latency 3387system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89059.019640 # average ReadReq miss latency 3388system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80261.557104 # average ReadReq miss latency 3389system.l2c.ReadReq_avg_miss_latency::cpu1.data 97242.091561 # average ReadReq miss latency 3390system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 146336.775252 # average ReadReq miss latency 3391system.l2c.ReadReq_avg_miss_latency::total 124447.736262 # average ReadReq miss latency 3392system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 77.724572 # average WriteInvalidateReq miss latency 3393system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 409.780072 # average WriteInvalidateReq miss latency 3394system.l2c.WriteInvalidateReq_avg_miss_latency::total 132.138496 # average WriteInvalidateReq miss latency 3395system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 4296.060156 # average UpgradeReq miss latency 3396system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4600.594946 # average UpgradeReq miss latency 3397system.l2c.UpgradeReq_avg_miss_latency::total 4446.091464 # average UpgradeReq miss latency 3398system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3825.447903 # average SCUpgradeReq miss latency 3399system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4271.781080 # average SCUpgradeReq miss latency 3400system.l2c.SCUpgradeReq_avg_miss_latency::total 4025.031237 # average SCUpgradeReq miss latency 3401system.l2c.ReadExReq_avg_miss_latency::cpu0.data 88845.110038 # average ReadExReq miss latency 3402system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81928.046416 # average ReadExReq miss latency 3403system.l2c.ReadExReq_avg_miss_latency::total 86262.105583 # average ReadExReq miss latency 3404system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85101.568308 # average overall miss latency 3405system.l2c.demand_avg_miss_latency::cpu0.itb.walker 86813.154283 # average overall miss latency 3406system.l2c.demand_avg_miss_latency::cpu0.inst 80393.193733 # average overall miss latency 3407system.l2c.demand_avg_miss_latency::cpu0.data 92758.248191 # average overall miss latency 3408system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 152868.475159 # average overall miss latency 3409system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87681.670463 # average overall miss latency 3410system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89059.019640 # average overall miss latency 3411system.l2c.demand_avg_miss_latency::cpu1.inst 80261.557104 # average overall miss latency 3412system.l2c.demand_avg_miss_latency::cpu1.data 92864.390481 # average overall miss latency 3413system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 146336.775252 # average overall miss latency 3414system.l2c.demand_avg_miss_latency::total 119602.960979 # average overall miss latency 3415system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 85101.568308 # average overall miss latency 3416system.l2c.overall_avg_miss_latency::cpu0.itb.walker 86813.154283 # average overall miss latency 3417system.l2c.overall_avg_miss_latency::cpu0.inst 80393.193733 # average overall miss latency 3418system.l2c.overall_avg_miss_latency::cpu0.data 92758.248191 # average overall miss latency 3419system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 152868.475159 # average overall miss latency 3420system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87681.670463 # average overall miss latency 3421system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89059.019640 # average overall miss latency 3422system.l2c.overall_avg_miss_latency::cpu1.inst 80261.557104 # average overall miss latency 3423system.l2c.overall_avg_miss_latency::cpu1.data 92864.390481 # average overall miss latency 3424system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 146336.775252 # average overall miss latency 3425system.l2c.overall_avg_miss_latency::total 119602.960979 # average overall miss latency 3426system.l2c.blocked_cycles::no_mshrs 13381 # number of cycles access was blocked | 3077system.l2c.tags.replacements 1377424 # number of replacements 3078system.l2c.tags.tagsinuse 64428.474571 # Cycle average of tags in use 3079system.l2c.tags.total_refs 4496154 # Total number of references to valid blocks. 3080system.l2c.tags.sampled_refs 1437791 # Sample count of references to valid blocks. 3081system.l2c.tags.avg_refs 3.127126 # Average number of references to valid blocks. 3082system.l2c.tags.warmup_cycle 3245891000 # Cycle when the warmup percentage was hit. 3083system.l2c.tags.occ_blocks::writebacks 17415.702003 # Average occupied blocks per requestor 3084system.l2c.tags.occ_blocks::cpu0.dtb.walker 13.555673 # Average occupied blocks per requestor 3085system.l2c.tags.occ_blocks::cpu0.itb.walker 13.071281 # Average occupied blocks per requestor 3086system.l2c.tags.occ_blocks::cpu0.inst 4037.254225 # Average occupied blocks per requestor 3087system.l2c.tags.occ_blocks::cpu0.data 5874.753333 # Average occupied blocks per requestor 3088system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3721.003209 # Average occupied blocks per requestor 3089system.l2c.tags.occ_blocks::cpu1.dtb.walker 357.239386 # Average occupied blocks per requestor 3090system.l2c.tags.occ_blocks::cpu1.itb.walker 523.990627 # Average occupied blocks per requestor 3091system.l2c.tags.occ_blocks::cpu1.inst 2776.282665 # Average occupied blocks per requestor 3092system.l2c.tags.occ_blocks::cpu1.data 11847.144423 # Average occupied blocks per requestor 3093system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17848.477746 # Average occupied blocks per requestor 3094system.l2c.tags.occ_percent::writebacks 0.265743 # Average percentage of cache occupancy 3095system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000207 # Average percentage of cache occupancy 3096system.l2c.tags.occ_percent::cpu0.itb.walker 0.000199 # Average percentage of cache occupancy 3097system.l2c.tags.occ_percent::cpu0.inst 0.061604 # Average percentage of cache occupancy 3098system.l2c.tags.occ_percent::cpu0.data 0.089642 # Average percentage of cache occupancy 3099system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.056778 # Average percentage of cache occupancy 3100system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005451 # Average percentage of cache occupancy 3101system.l2c.tags.occ_percent::cpu1.itb.walker 0.007995 # Average percentage of cache occupancy 3102system.l2c.tags.occ_percent::cpu1.inst 0.042363 # Average percentage of cache occupancy 3103system.l2c.tags.occ_percent::cpu1.data 0.180773 # Average percentage of cache occupancy 3104system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.272346 # Average percentage of cache occupancy 3105system.l2c.tags.occ_percent::total 0.983101 # Average percentage of cache occupancy 3106system.l2c.tags.occ_task_id_blocks::1022 10320 # Occupied blocks per task id 3107system.l2c.tags.occ_task_id_blocks::1023 289 # Occupied blocks per task id 3108system.l2c.tags.occ_task_id_blocks::1024 49758 # Occupied blocks per task id 3109system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id 3110system.l2c.tags.age_task_id_blocks_1022::1 29 # Occupied blocks per task id 3111system.l2c.tags.age_task_id_blocks_1022::2 178 # Occupied blocks per task id 3112system.l2c.tags.age_task_id_blocks_1022::3 260 # Occupied blocks per task id 3113system.l2c.tags.age_task_id_blocks_1022::4 9845 # Occupied blocks per task id 3114system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 3115system.l2c.tags.age_task_id_blocks_1023::4 285 # Occupied blocks per task id 3116system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 3117system.l2c.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id 3118system.l2c.tags.age_task_id_blocks_1024::2 2371 # Occupied blocks per task id 3119system.l2c.tags.age_task_id_blocks_1024::3 4137 # Occupied blocks per task id 3120system.l2c.tags.age_task_id_blocks_1024::4 42888 # Occupied blocks per task id 3121system.l2c.tags.occ_task_id_percent::1022 0.157471 # Percentage of cache occupancy per task id 3122system.l2c.tags.occ_task_id_percent::1023 0.004410 # Percentage of cache occupancy per task id 3123system.l2c.tags.occ_task_id_percent::1024 0.759247 # Percentage of cache occupancy per task id 3124system.l2c.tags.tag_accesses 59850638 # Number of tag accesses 3125system.l2c.tags.data_accesses 59850638 # Number of data accesses 3126system.l2c.ReadReq_hits::cpu0.dtb.walker 6609 # number of ReadReq hits 3127system.l2c.ReadReq_hits::cpu0.itb.walker 5089 # number of ReadReq hits 3128system.l2c.ReadReq_hits::cpu0.inst 570808 # number of ReadReq hits 3129system.l2c.ReadReq_hits::cpu0.data 585040 # number of ReadReq hits 3130system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 302541 # number of ReadReq hits 3131system.l2c.ReadReq_hits::cpu1.dtb.walker 6014 # number of ReadReq hits 3132system.l2c.ReadReq_hits::cpu1.itb.walker 4366 # number of ReadReq hits 3133system.l2c.ReadReq_hits::cpu1.inst 555272 # number of ReadReq hits 3134system.l2c.ReadReq_hits::cpu1.data 535796 # number of ReadReq hits 3135system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 269863 # number of ReadReq hits 3136system.l2c.ReadReq_hits::total 2841398 # number of ReadReq hits 3137system.l2c.Writeback_hits::writebacks 2358990 # number of Writeback hits 3138system.l2c.Writeback_hits::total 2358990 # number of Writeback hits 3139system.l2c.WriteInvalidateReq_hits::cpu0.data 147857 # number of WriteInvalidateReq hits 3140system.l2c.WriteInvalidateReq_hits::cpu1.data 120344 # number of WriteInvalidateReq hits 3141system.l2c.WriteInvalidateReq_hits::total 268201 # number of WriteInvalidateReq hits 3142system.l2c.UpgradeReq_hits::cpu0.data 33100 # number of UpgradeReq hits 3143system.l2c.UpgradeReq_hits::cpu1.data 25345 # number of UpgradeReq hits 3144system.l2c.UpgradeReq_hits::total 58445 # number of UpgradeReq hits 3145system.l2c.SCUpgradeReq_hits::cpu0.data 6120 # number of SCUpgradeReq hits 3146system.l2c.SCUpgradeReq_hits::cpu1.data 5439 # number of SCUpgradeReq hits 3147system.l2c.SCUpgradeReq_hits::total 11559 # number of SCUpgradeReq hits 3148system.l2c.ReadExReq_hits::cpu0.data 54193 # number of ReadExReq hits 3149system.l2c.ReadExReq_hits::cpu1.data 49865 # number of ReadExReq hits 3150system.l2c.ReadExReq_hits::total 104058 # number of ReadExReq hits 3151system.l2c.demand_hits::cpu0.dtb.walker 6609 # number of demand (read+write) hits 3152system.l2c.demand_hits::cpu0.itb.walker 5089 # number of demand (read+write) hits 3153system.l2c.demand_hits::cpu0.inst 570808 # number of demand (read+write) hits 3154system.l2c.demand_hits::cpu0.data 639233 # number of demand (read+write) hits 3155system.l2c.demand_hits::cpu0.l2cache.prefetcher 302541 # number of demand (read+write) hits 3156system.l2c.demand_hits::cpu1.dtb.walker 6014 # number of demand (read+write) hits 3157system.l2c.demand_hits::cpu1.itb.walker 4366 # number of demand (read+write) hits 3158system.l2c.demand_hits::cpu1.inst 555272 # number of demand (read+write) hits 3159system.l2c.demand_hits::cpu1.data 585661 # number of demand (read+write) hits 3160system.l2c.demand_hits::cpu1.l2cache.prefetcher 269863 # number of demand (read+write) hits 3161system.l2c.demand_hits::total 2945456 # number of demand (read+write) hits 3162system.l2c.overall_hits::cpu0.dtb.walker 6609 # number of overall hits 3163system.l2c.overall_hits::cpu0.itb.walker 5089 # number of overall hits 3164system.l2c.overall_hits::cpu0.inst 570808 # number of overall hits 3165system.l2c.overall_hits::cpu0.data 639233 # number of overall hits 3166system.l2c.overall_hits::cpu0.l2cache.prefetcher 302541 # number of overall hits 3167system.l2c.overall_hits::cpu1.dtb.walker 6014 # number of overall hits 3168system.l2c.overall_hits::cpu1.itb.walker 4366 # number of overall hits 3169system.l2c.overall_hits::cpu1.inst 555272 # number of overall hits 3170system.l2c.overall_hits::cpu1.data 585661 # number of overall hits 3171system.l2c.overall_hits::cpu1.l2cache.prefetcher 269863 # number of overall hits 3172system.l2c.overall_hits::total 2945456 # number of overall hits 3173system.l2c.ReadReq_misses::cpu0.dtb.walker 1186 # number of ReadReq misses 3174system.l2c.ReadReq_misses::cpu0.itb.walker 952 # number of ReadReq misses 3175system.l2c.ReadReq_misses::cpu0.inst 65177 # number of ReadReq misses 3176system.l2c.ReadReq_misses::cpu0.data 129551 # number of ReadReq misses 3177system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 203502 # number of ReadReq misses 3178system.l2c.ReadReq_misses::cpu1.dtb.walker 2616 # number of ReadReq misses 3179system.l2c.ReadReq_misses::cpu1.itb.walker 2569 # number of ReadReq misses 3180system.l2c.ReadReq_misses::cpu1.inst 39512 # number of ReadReq misses 3181system.l2c.ReadReq_misses::cpu1.data 114014 # number of ReadReq misses 3182system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 227886 # number of ReadReq misses 3183system.l2c.ReadReq_misses::total 786965 # number of ReadReq misses 3184system.l2c.WriteInvalidateReq_misses::cpu0.data 437920 # number of WriteInvalidateReq misses 3185system.l2c.WriteInvalidateReq_misses::cpu1.data 120290 # number of WriteInvalidateReq misses 3186system.l2c.WriteInvalidateReq_misses::total 558210 # number of WriteInvalidateReq misses 3187system.l2c.UpgradeReq_misses::cpu0.data 45660 # number of UpgradeReq misses 3188system.l2c.UpgradeReq_misses::cpu1.data 46311 # number of UpgradeReq misses 3189system.l2c.UpgradeReq_misses::total 91971 # number of UpgradeReq misses 3190system.l2c.SCUpgradeReq_misses::cpu0.data 9121 # number of SCUpgradeReq misses 3191system.l2c.SCUpgradeReq_misses::cpu1.data 8967 # number of SCUpgradeReq misses 3192system.l2c.SCUpgradeReq_misses::total 18088 # number of SCUpgradeReq misses 3193system.l2c.ReadExReq_misses::cpu0.data 74847 # number of ReadExReq misses 3194system.l2c.ReadExReq_misses::cpu1.data 51643 # number of ReadExReq misses 3195system.l2c.ReadExReq_misses::total 126490 # number of ReadExReq misses 3196system.l2c.demand_misses::cpu0.dtb.walker 1186 # number of demand (read+write) misses 3197system.l2c.demand_misses::cpu0.itb.walker 952 # number of demand (read+write) misses 3198system.l2c.demand_misses::cpu0.inst 65177 # number of demand (read+write) misses 3199system.l2c.demand_misses::cpu0.data 204398 # number of demand (read+write) misses 3200system.l2c.demand_misses::cpu0.l2cache.prefetcher 203502 # number of demand (read+write) misses 3201system.l2c.demand_misses::cpu1.dtb.walker 2616 # number of demand (read+write) misses 3202system.l2c.demand_misses::cpu1.itb.walker 2569 # number of demand (read+write) misses 3203system.l2c.demand_misses::cpu1.inst 39512 # number of demand (read+write) misses 3204system.l2c.demand_misses::cpu1.data 165657 # number of demand (read+write) misses 3205system.l2c.demand_misses::cpu1.l2cache.prefetcher 227886 # number of demand (read+write) misses 3206system.l2c.demand_misses::total 913455 # number of demand (read+write) misses 3207system.l2c.overall_misses::cpu0.dtb.walker 1186 # number of overall misses 3208system.l2c.overall_misses::cpu0.itb.walker 952 # number of overall misses 3209system.l2c.overall_misses::cpu0.inst 65177 # number of overall misses 3210system.l2c.overall_misses::cpu0.data 204398 # number of overall misses 3211system.l2c.overall_misses::cpu0.l2cache.prefetcher 203502 # number of overall misses 3212system.l2c.overall_misses::cpu1.dtb.walker 2616 # number of overall misses 3213system.l2c.overall_misses::cpu1.itb.walker 2569 # number of overall misses 3214system.l2c.overall_misses::cpu1.inst 39512 # number of overall misses 3215system.l2c.overall_misses::cpu1.data 165657 # number of overall misses 3216system.l2c.overall_misses::cpu1.l2cache.prefetcher 227886 # number of overall misses 3217system.l2c.overall_misses::total 913455 # number of overall misses 3218system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 111035273 # number of ReadReq miss cycles 3219system.l2c.ReadReq_miss_latency::cpu0.itb.walker 90655016 # number of ReadReq miss cycles 3220system.l2c.ReadReq_miss_latency::cpu0.inst 5679579933 # number of ReadReq miss cycles 3221system.l2c.ReadReq_miss_latency::cpu0.data 12742001076 # number of ReadReq miss cycles 3222system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 29753788309 # number of ReadReq miss cycles 3223system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 236867766 # number of ReadReq miss cycles 3224system.l2c.ReadReq_miss_latency::cpu1.itb.walker 230645249 # number of ReadReq miss cycles 3225system.l2c.ReadReq_miss_latency::cpu1.inst 3413499724 # number of ReadReq miss cycles 3226system.l2c.ReadReq_miss_latency::cpu1.data 10938718079 # number of ReadReq miss cycles 3227system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 32443014097 # number of ReadReq miss cycles 3228system.l2c.ReadReq_miss_latency::total 95639804522 # number of ReadReq miss cycles 3229system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 58893966 # number of WriteInvalidateReq miss cycles 3230system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 45248781 # number of WriteInvalidateReq miss cycles 3231system.l2c.WriteInvalidateReq_miss_latency::total 104142747 # number of WriteInvalidateReq miss cycles 3232system.l2c.UpgradeReq_miss_latency::cpu0.data 276167379 # number of UpgradeReq miss cycles 3233system.l2c.UpgradeReq_miss_latency::cpu1.data 268661108 # number of UpgradeReq miss cycles 3234system.l2c.UpgradeReq_miss_latency::total 544828487 # number of UpgradeReq miss cycles 3235system.l2c.SCUpgradeReq_miss_latency::cpu0.data 46772512 # number of SCUpgradeReq miss cycles 3236system.l2c.SCUpgradeReq_miss_latency::cpu1.data 48520461 # number of SCUpgradeReq miss cycles 3237system.l2c.SCUpgradeReq_miss_latency::total 95292973 # number of SCUpgradeReq miss cycles 3238system.l2c.ReadExReq_miss_latency::cpu0.data 6912544305 # number of ReadExReq miss cycles 3239system.l2c.ReadExReq_miss_latency::cpu1.data 4650422855 # number of ReadExReq miss cycles 3240system.l2c.ReadExReq_miss_latency::total 11562967160 # number of ReadExReq miss cycles 3241system.l2c.demand_miss_latency::cpu0.dtb.walker 111035273 # number of demand (read+write) miss cycles 3242system.l2c.demand_miss_latency::cpu0.itb.walker 90655016 # number of demand (read+write) miss cycles 3243system.l2c.demand_miss_latency::cpu0.inst 5679579933 # number of demand (read+write) miss cycles 3244system.l2c.demand_miss_latency::cpu0.data 19654545381 # number of demand (read+write) miss cycles 3245system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 29753788309 # number of demand (read+write) miss cycles 3246system.l2c.demand_miss_latency::cpu1.dtb.walker 236867766 # number of demand (read+write) miss cycles 3247system.l2c.demand_miss_latency::cpu1.itb.walker 230645249 # number of demand (read+write) miss cycles 3248system.l2c.demand_miss_latency::cpu1.inst 3413499724 # number of demand (read+write) miss cycles 3249system.l2c.demand_miss_latency::cpu1.data 15589140934 # number of demand (read+write) miss cycles 3250system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 32443014097 # number of demand (read+write) miss cycles 3251system.l2c.demand_miss_latency::total 107202771682 # number of demand (read+write) miss cycles 3252system.l2c.overall_miss_latency::cpu0.dtb.walker 111035273 # number of overall miss cycles 3253system.l2c.overall_miss_latency::cpu0.itb.walker 90655016 # number of overall miss cycles 3254system.l2c.overall_miss_latency::cpu0.inst 5679579933 # number of overall miss cycles 3255system.l2c.overall_miss_latency::cpu0.data 19654545381 # number of overall miss cycles 3256system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 29753788309 # number of overall miss cycles 3257system.l2c.overall_miss_latency::cpu1.dtb.walker 236867766 # number of overall miss cycles 3258system.l2c.overall_miss_latency::cpu1.itb.walker 230645249 # number of overall miss cycles 3259system.l2c.overall_miss_latency::cpu1.inst 3413499724 # number of overall miss cycles 3260system.l2c.overall_miss_latency::cpu1.data 15589140934 # number of overall miss cycles 3261system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 32443014097 # number of overall miss cycles 3262system.l2c.overall_miss_latency::total 107202771682 # number of overall miss cycles 3263system.l2c.ReadReq_accesses::cpu0.dtb.walker 7795 # number of ReadReq accesses(hits+misses) 3264system.l2c.ReadReq_accesses::cpu0.itb.walker 6041 # number of ReadReq accesses(hits+misses) 3265system.l2c.ReadReq_accesses::cpu0.inst 635985 # number of ReadReq accesses(hits+misses) 3266system.l2c.ReadReq_accesses::cpu0.data 714591 # number of ReadReq accesses(hits+misses) 3267system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 506043 # number of ReadReq accesses(hits+misses) 3268system.l2c.ReadReq_accesses::cpu1.dtb.walker 8630 # number of ReadReq accesses(hits+misses) 3269system.l2c.ReadReq_accesses::cpu1.itb.walker 6935 # number of ReadReq accesses(hits+misses) 3270system.l2c.ReadReq_accesses::cpu1.inst 594784 # number of ReadReq accesses(hits+misses) 3271system.l2c.ReadReq_accesses::cpu1.data 649810 # number of ReadReq accesses(hits+misses) 3272system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 497749 # number of ReadReq accesses(hits+misses) 3273system.l2c.ReadReq_accesses::total 3628363 # number of ReadReq accesses(hits+misses) 3274system.l2c.Writeback_accesses::writebacks 2358990 # number of Writeback accesses(hits+misses) 3275system.l2c.Writeback_accesses::total 2358990 # number of Writeback accesses(hits+misses) 3276system.l2c.WriteInvalidateReq_accesses::cpu0.data 585777 # number of WriteInvalidateReq accesses(hits+misses) 3277system.l2c.WriteInvalidateReq_accesses::cpu1.data 240634 # number of WriteInvalidateReq accesses(hits+misses) 3278system.l2c.WriteInvalidateReq_accesses::total 826411 # number of WriteInvalidateReq accesses(hits+misses) 3279system.l2c.UpgradeReq_accesses::cpu0.data 78760 # number of UpgradeReq accesses(hits+misses) 3280system.l2c.UpgradeReq_accesses::cpu1.data 71656 # number of UpgradeReq accesses(hits+misses) 3281system.l2c.UpgradeReq_accesses::total 150416 # number of UpgradeReq accesses(hits+misses) 3282system.l2c.SCUpgradeReq_accesses::cpu0.data 15241 # number of SCUpgradeReq accesses(hits+misses) 3283system.l2c.SCUpgradeReq_accesses::cpu1.data 14406 # number of SCUpgradeReq accesses(hits+misses) 3284system.l2c.SCUpgradeReq_accesses::total 29647 # number of SCUpgradeReq accesses(hits+misses) 3285system.l2c.ReadExReq_accesses::cpu0.data 129040 # number of ReadExReq accesses(hits+misses) 3286system.l2c.ReadExReq_accesses::cpu1.data 101508 # number of ReadExReq accesses(hits+misses) 3287system.l2c.ReadExReq_accesses::total 230548 # number of ReadExReq accesses(hits+misses) 3288system.l2c.demand_accesses::cpu0.dtb.walker 7795 # number of demand (read+write) accesses 3289system.l2c.demand_accesses::cpu0.itb.walker 6041 # number of demand (read+write) accesses 3290system.l2c.demand_accesses::cpu0.inst 635985 # number of demand (read+write) accesses 3291system.l2c.demand_accesses::cpu0.data 843631 # number of demand (read+write) accesses 3292system.l2c.demand_accesses::cpu0.l2cache.prefetcher 506043 # number of demand (read+write) accesses 3293system.l2c.demand_accesses::cpu1.dtb.walker 8630 # number of demand (read+write) accesses 3294system.l2c.demand_accesses::cpu1.itb.walker 6935 # number of demand (read+write) accesses 3295system.l2c.demand_accesses::cpu1.inst 594784 # number of demand (read+write) accesses 3296system.l2c.demand_accesses::cpu1.data 751318 # number of demand (read+write) accesses 3297system.l2c.demand_accesses::cpu1.l2cache.prefetcher 497749 # number of demand (read+write) accesses 3298system.l2c.demand_accesses::total 3858911 # number of demand (read+write) accesses 3299system.l2c.overall_accesses::cpu0.dtb.walker 7795 # number of overall (read+write) accesses 3300system.l2c.overall_accesses::cpu0.itb.walker 6041 # number of overall (read+write) accesses 3301system.l2c.overall_accesses::cpu0.inst 635985 # number of overall (read+write) accesses 3302system.l2c.overall_accesses::cpu0.data 843631 # number of overall (read+write) accesses 3303system.l2c.overall_accesses::cpu0.l2cache.prefetcher 506043 # number of overall (read+write) accesses 3304system.l2c.overall_accesses::cpu1.dtb.walker 8630 # number of overall (read+write) accesses 3305system.l2c.overall_accesses::cpu1.itb.walker 6935 # number of overall (read+write) accesses 3306system.l2c.overall_accesses::cpu1.inst 594784 # number of overall (read+write) accesses 3307system.l2c.overall_accesses::cpu1.data 751318 # number of overall (read+write) accesses 3308system.l2c.overall_accesses::cpu1.l2cache.prefetcher 497749 # number of overall (read+write) accesses 3309system.l2c.overall_accesses::total 3858911 # number of overall (read+write) accesses 3310system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.152149 # miss rate for ReadReq accesses 3311system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.157590 # miss rate for ReadReq accesses 3312system.l2c.ReadReq_miss_rate::cpu0.inst 0.102482 # miss rate for ReadReq accesses 3313system.l2c.ReadReq_miss_rate::cpu0.data 0.181294 # miss rate for ReadReq accesses 3314system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.402144 # miss rate for ReadReq accesses 3315system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.303129 # miss rate for ReadReq accesses 3316system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.370440 # miss rate for ReadReq accesses 3317system.l2c.ReadReq_miss_rate::cpu1.inst 0.066431 # miss rate for ReadReq accesses 3318system.l2c.ReadReq_miss_rate::cpu1.data 0.175457 # miss rate for ReadReq accesses 3319system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.457833 # miss rate for ReadReq accesses 3320system.l2c.ReadReq_miss_rate::total 0.216893 # miss rate for ReadReq accesses 3321system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.747588 # miss rate for WriteInvalidateReq accesses 3322system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.499888 # miss rate for WriteInvalidateReq accesses 3323system.l2c.WriteInvalidateReq_miss_rate::total 0.675463 # miss rate for WriteInvalidateReq accesses 3324system.l2c.UpgradeReq_miss_rate::cpu0.data 0.579736 # miss rate for UpgradeReq accesses 3325system.l2c.UpgradeReq_miss_rate::cpu1.data 0.646296 # miss rate for UpgradeReq accesses 3326system.l2c.UpgradeReq_miss_rate::total 0.611444 # miss rate for UpgradeReq accesses 3327system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.598452 # miss rate for SCUpgradeReq accesses 3328system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.622449 # miss rate for SCUpgradeReq accesses 3329system.l2c.SCUpgradeReq_miss_rate::total 0.610112 # miss rate for SCUpgradeReq accesses 3330system.l2c.ReadExReq_miss_rate::cpu0.data 0.580029 # miss rate for ReadExReq accesses 3331system.l2c.ReadExReq_miss_rate::cpu1.data 0.508758 # miss rate for ReadExReq accesses 3332system.l2c.ReadExReq_miss_rate::total 0.548649 # miss rate for ReadExReq accesses 3333system.l2c.demand_miss_rate::cpu0.dtb.walker 0.152149 # miss rate for demand accesses 3334system.l2c.demand_miss_rate::cpu0.itb.walker 0.157590 # miss rate for demand accesses 3335system.l2c.demand_miss_rate::cpu0.inst 0.102482 # miss rate for demand accesses 3336system.l2c.demand_miss_rate::cpu0.data 0.242284 # miss rate for demand accesses 3337system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.402144 # miss rate for demand accesses 3338system.l2c.demand_miss_rate::cpu1.dtb.walker 0.303129 # miss rate for demand accesses 3339system.l2c.demand_miss_rate::cpu1.itb.walker 0.370440 # miss rate for demand accesses 3340system.l2c.demand_miss_rate::cpu1.inst 0.066431 # miss rate for demand accesses 3341system.l2c.demand_miss_rate::cpu1.data 0.220489 # miss rate for demand accesses 3342system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.457833 # miss rate for demand accesses 3343system.l2c.demand_miss_rate::total 0.236713 # miss rate for demand accesses 3344system.l2c.overall_miss_rate::cpu0.dtb.walker 0.152149 # miss rate for overall accesses 3345system.l2c.overall_miss_rate::cpu0.itb.walker 0.157590 # miss rate for overall accesses 3346system.l2c.overall_miss_rate::cpu0.inst 0.102482 # miss rate for overall accesses 3347system.l2c.overall_miss_rate::cpu0.data 0.242284 # miss rate for overall accesses 3348system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.402144 # miss rate for overall accesses 3349system.l2c.overall_miss_rate::cpu1.dtb.walker 0.303129 # miss rate for overall accesses 3350system.l2c.overall_miss_rate::cpu1.itb.walker 0.370440 # miss rate for overall accesses 3351system.l2c.overall_miss_rate::cpu1.inst 0.066431 # miss rate for overall accesses 3352system.l2c.overall_miss_rate::cpu1.data 0.220489 # miss rate for overall accesses 3353system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.457833 # miss rate for overall accesses 3354system.l2c.overall_miss_rate::total 0.236713 # miss rate for overall accesses 3355system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 93621.646712 # average ReadReq miss latency 3356system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 95225.857143 # average ReadReq miss latency 3357system.l2c.ReadReq_avg_miss_latency::cpu0.inst 87140.861546 # average ReadReq miss latency 3358system.l2c.ReadReq_avg_miss_latency::cpu0.data 98355.096263 # average ReadReq miss latency 3359system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 146208.825019 # average ReadReq miss latency 3360system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 90545.782110 # average ReadReq miss latency 3361system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89780.166991 # average ReadReq miss latency 3362system.l2c.ReadReq_avg_miss_latency::cpu1.inst 86391.469022 # average ReadReq miss latency 3363system.l2c.ReadReq_avg_miss_latency::cpu1.data 95941.885023 # average ReadReq miss latency 3364system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 142365.104030 # average ReadReq miss latency 3365system.l2c.ReadReq_avg_miss_latency::total 121529.934015 # average ReadReq miss latency 3366system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 134.485673 # average WriteInvalidateReq miss latency 3367system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 376.164112 # average WriteInvalidateReq miss latency 3368system.l2c.WriteInvalidateReq_avg_miss_latency::total 186.565534 # average WriteInvalidateReq miss latency 3369system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6048.343824 # average UpgradeReq miss latency 3370system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5801.237460 # average UpgradeReq miss latency 3371system.l2c.UpgradeReq_avg_miss_latency::total 5923.916093 # average UpgradeReq miss latency 3372system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5128.002631 # average SCUpgradeReq miss latency 3373system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5411.002676 # average SCUpgradeReq miss latency 3374system.l2c.SCUpgradeReq_avg_miss_latency::total 5268.297932 # average SCUpgradeReq miss latency 3375system.l2c.ReadExReq_avg_miss_latency::cpu0.data 92355.662952 # average ReadExReq miss latency 3376system.l2c.ReadExReq_avg_miss_latency::cpu1.data 90049.432740 # average ReadExReq miss latency 3377system.l2c.ReadExReq_avg_miss_latency::total 91414.081429 # average ReadExReq miss latency 3378system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 93621.646712 # average overall miss latency 3379system.l2c.demand_avg_miss_latency::cpu0.itb.walker 95225.857143 # average overall miss latency 3380system.l2c.demand_avg_miss_latency::cpu0.inst 87140.861546 # average overall miss latency 3381system.l2c.demand_avg_miss_latency::cpu0.data 96158.207913 # average overall miss latency 3382system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 146208.825019 # average overall miss latency 3383system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90545.782110 # average overall miss latency 3384system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89780.166991 # average overall miss latency 3385system.l2c.demand_avg_miss_latency::cpu1.inst 86391.469022 # average overall miss latency 3386system.l2c.demand_avg_miss_latency::cpu1.data 94104.933290 # average overall miss latency 3387system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 142365.104030 # average overall miss latency 3388system.l2c.demand_avg_miss_latency::total 117359.663784 # average overall miss latency 3389system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 93621.646712 # average overall miss latency 3390system.l2c.overall_avg_miss_latency::cpu0.itb.walker 95225.857143 # average overall miss latency 3391system.l2c.overall_avg_miss_latency::cpu0.inst 87140.861546 # average overall miss latency 3392system.l2c.overall_avg_miss_latency::cpu0.data 96158.207913 # average overall miss latency 3393system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 146208.825019 # average overall miss latency 3394system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90545.782110 # average overall miss latency 3395system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89780.166991 # average overall miss latency 3396system.l2c.overall_avg_miss_latency::cpu1.inst 86391.469022 # average overall miss latency 3397system.l2c.overall_avg_miss_latency::cpu1.data 94104.933290 # average overall miss latency 3398system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 142365.104030 # average overall miss latency 3399system.l2c.overall_avg_miss_latency::total 117359.663784 # average overall miss latency 3400system.l2c.blocked_cycles::no_mshrs 11943 # number of cycles access was blocked |
| 3427system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked | 3401system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 3428system.l2c.blocked::no_mshrs 234 # number of cycles access was blocked | 3402system.l2c.blocked::no_mshrs 84 # number of cycles access was blocked |
| 3429system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 3403system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 3430system.l2c.avg_blocked_cycles::no_mshrs 57.183761 # average number of cycles each access was blocked | 3404system.l2c.avg_blocked_cycles::no_mshrs 142.178571 # average number of cycles each access was blocked |
| 3431system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3432system.l2c.fast_writes 0 # number of fast writes performed 3433system.l2c.cache_copies 0 # number of cache copies performed | 3405system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3406system.l2c.fast_writes 0 # number of fast writes performed 3407system.l2c.cache_copies 0 # number of cache copies performed |
| 3434system.l2c.writebacks::writebacks 1241010 # number of writebacks 3435system.l2c.writebacks::total 1241010 # number of writebacks 3436system.l2c.ReadReq_mshr_hits::cpu0.inst 230 # number of ReadReq MSHR hits 3437system.l2c.ReadReq_mshr_hits::cpu0.data 68 # number of ReadReq MSHR hits 3438system.l2c.ReadReq_mshr_hits::cpu1.inst 210 # number of ReadReq MSHR hits 3439system.l2c.ReadReq_mshr_hits::cpu1.data 83 # number of ReadReq MSHR hits 3440system.l2c.ReadReq_mshr_hits::total 591 # number of ReadReq MSHR hits 3441system.l2c.demand_mshr_hits::cpu0.inst 230 # number of demand (read+write) MSHR hits 3442system.l2c.demand_mshr_hits::cpu0.data 68 # number of demand (read+write) MSHR hits 3443system.l2c.demand_mshr_hits::cpu1.inst 210 # number of demand (read+write) MSHR hits 3444system.l2c.demand_mshr_hits::cpu1.data 83 # number of demand (read+write) MSHR hits 3445system.l2c.demand_mshr_hits::total 591 # number of demand (read+write) MSHR hits 3446system.l2c.overall_mshr_hits::cpu0.inst 230 # number of overall MSHR hits 3447system.l2c.overall_mshr_hits::cpu0.data 68 # number of overall MSHR hits 3448system.l2c.overall_mshr_hits::cpu1.inst 210 # number of overall MSHR hits 3449system.l2c.overall_mshr_hits::cpu1.data 83 # number of overall MSHR hits 3450system.l2c.overall_mshr_hits::total 591 # number of overall MSHR hits 3451system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2518 # number of ReadReq MSHR misses 3452system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2288 # number of ReadReq MSHR misses 3453system.l2c.ReadReq_mshr_misses::cpu0.inst 61396 # number of ReadReq MSHR misses 3454system.l2c.ReadReq_mshr_misses::cpu0.data 164959 # number of ReadReq MSHR misses 3455system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 315511 # number of ReadReq MSHR misses 3456system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2810 # number of ReadReq MSHR misses 3457system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2444 # number of ReadReq MSHR misses 3458system.l2c.ReadReq_mshr_misses::cpu1.inst 54103 # number of ReadReq MSHR misses 3459system.l2c.ReadReq_mshr_misses::cpu1.data 130595 # number of ReadReq MSHR misses 3460system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 226783 # number of ReadReq MSHR misses 3461system.l2c.ReadReq_mshr_misses::total 963407 # number of ReadReq MSHR misses 3462system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 490361 # number of WriteInvalidateReq MSHR misses 3463system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 96104 # number of WriteInvalidateReq MSHR misses 3464system.l2c.WriteInvalidateReq_mshr_misses::total 586465 # number of WriteInvalidateReq MSHR misses 3465system.l2c.UpgradeReq_mshr_misses::cpu0.data 48125 # number of UpgradeReq MSHR misses 3466system.l2c.UpgradeReq_mshr_misses::cpu1.data 46732 # number of UpgradeReq MSHR misses 3467system.l2c.UpgradeReq_mshr_misses::total 94857 # number of UpgradeReq MSHR misses 3468system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 10442 # number of SCUpgradeReq MSHR misses 3469system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 8446 # number of SCUpgradeReq MSHR misses 3470system.l2c.SCUpgradeReq_mshr_misses::total 18888 # number of SCUpgradeReq MSHR misses 3471system.l2c.ReadExReq_mshr_misses::cpu0.data 87770 # number of ReadExReq MSHR misses 3472system.l2c.ReadExReq_mshr_misses::cpu1.data 52309 # number of ReadExReq MSHR misses 3473system.l2c.ReadExReq_mshr_misses::total 140079 # number of ReadExReq MSHR misses 3474system.l2c.demand_mshr_misses::cpu0.dtb.walker 2518 # number of demand (read+write) MSHR misses 3475system.l2c.demand_mshr_misses::cpu0.itb.walker 2288 # number of demand (read+write) MSHR misses 3476system.l2c.demand_mshr_misses::cpu0.inst 61396 # number of demand (read+write) MSHR misses 3477system.l2c.demand_mshr_misses::cpu0.data 252729 # number of demand (read+write) MSHR misses 3478system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 315511 # number of demand (read+write) MSHR misses 3479system.l2c.demand_mshr_misses::cpu1.dtb.walker 2810 # number of demand (read+write) MSHR misses 3480system.l2c.demand_mshr_misses::cpu1.itb.walker 2444 # number of demand (read+write) MSHR misses 3481system.l2c.demand_mshr_misses::cpu1.inst 54103 # number of demand (read+write) MSHR misses 3482system.l2c.demand_mshr_misses::cpu1.data 182904 # number of demand (read+write) MSHR misses 3483system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 226783 # number of demand (read+write) MSHR misses 3484system.l2c.demand_mshr_misses::total 1103486 # number of demand (read+write) MSHR misses 3485system.l2c.overall_mshr_misses::cpu0.dtb.walker 2518 # number of overall MSHR misses 3486system.l2c.overall_mshr_misses::cpu0.itb.walker 2288 # number of overall MSHR misses 3487system.l2c.overall_mshr_misses::cpu0.inst 61396 # number of overall MSHR misses 3488system.l2c.overall_mshr_misses::cpu0.data 252729 # number of overall MSHR misses 3489system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 315511 # number of overall MSHR misses 3490system.l2c.overall_mshr_misses::cpu1.dtb.walker 2810 # number of overall MSHR misses 3491system.l2c.overall_mshr_misses::cpu1.itb.walker 2444 # number of overall MSHR misses 3492system.l2c.overall_mshr_misses::cpu1.inst 54103 # number of overall MSHR misses 3493system.l2c.overall_mshr_misses::cpu1.data 182904 # number of overall MSHR misses 3494system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 226783 # number of overall MSHR misses 3495system.l2c.overall_mshr_misses::total 1103486 # number of overall MSHR misses 3496system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 182832749 # number of ReadReq MSHR miss cycles 3497system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 170078497 # number of ReadReq MSHR miss cycles 3498system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 4169491707 # number of ReadReq MSHR miss cycles 3499system.l2c.ReadReq_mshr_miss_latency::cpu0.data 13595488810 # number of ReadReq MSHR miss cycles 3500system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 44400149466 # number of ReadReq MSHR miss cycles 3501system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 211305994 # number of ReadReq MSHR miss cycles 3502system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 187184244 # 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number of UpgradeReq MSHR miss cycles 3513system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 106392293 # number of SCUpgradeReq MSHR miss cycles 3514system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 85816866 # number of SCUpgradeReq MSHR miss cycles 3515system.l2c.SCUpgradeReq_mshr_miss_latency::total 192209159 # number of SCUpgradeReq MSHR miss cycles 3516system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6696791958 # number of ReadExReq MSHR miss cycles 3517system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3633299230 # number of ReadExReq MSHR miss cycles 3518system.l2c.ReadExReq_mshr_miss_latency::total 10330091188 # number of ReadExReq MSHR miss cycles 3519system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 182832749 # number of demand (read+write) MSHR miss cycles 3520system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 170078497 # number of demand (read+write) MSHR miss cycles 3521system.l2c.demand_mshr_miss_latency::cpu0.inst 4169491707 # number of demand (read+write) MSHR miss cycles 3522system.l2c.demand_mshr_miss_latency::cpu0.data 20292280768 # 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number of overall MSHR miss cycles 3532system.l2c.overall_mshr_miss_latency::cpu0.inst 4169491707 # number of overall MSHR miss cycles 3533system.l2c.overall_mshr_miss_latency::cpu0.data 20292280768 # number of overall MSHR miss cycles 3534system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 44400149466 # number of overall MSHR miss cycles 3535system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 211305994 # number of overall MSHR miss cycles 3536system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 187184244 # number of overall MSHR miss cycles 3537system.l2c.overall_mshr_miss_latency::cpu1.inst 3666713475 # number of overall MSHR miss cycles 3538system.l2c.overall_mshr_miss_latency::cpu1.data 14713887439 # number of overall MSHR miss cycles 3539system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 30429379906 # number of overall MSHR miss cycles 3540system.l2c.overall_mshr_miss_latency::total 118423304245 # number of overall MSHR miss cycles 3541system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1103208750 # number of ReadReq MSHR uncacheable cycles 3542system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4750572496 # number of ReadReq MSHR uncacheable cycles 3543system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3896750 # number of ReadReq MSHR uncacheable cycles 3544system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 616502003 # number of ReadReq MSHR uncacheable cycles 3545system.l2c.ReadReq_mshr_uncacheable_latency::total 6474179999 # number of ReadReq MSHR uncacheable cycles 3546system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4542606997 # number of WriteReq MSHR uncacheable cycles 3547system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 728363997 # number of WriteReq MSHR uncacheable cycles 3548system.l2c.WriteReq_mshr_uncacheable_latency::total 5270970994 # number of WriteReq MSHR uncacheable cycles 3549system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1103208750 # number of overall MSHR uncacheable cycles 3550system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9293179493 # number of overall MSHR uncacheable cycles 3551system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3896750 # number of overall MSHR uncacheable cycles 3552system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1344866000 # number of overall MSHR uncacheable cycles 3553system.l2c.overall_mshr_uncacheable_latency::total 11745150993 # number of overall MSHR uncacheable cycles 3554system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.278972 # mshr miss rate for ReadReq accesses 3555system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.346299 # mshr miss rate for ReadReq accesses 3556system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.087381 # mshr miss rate for ReadReq accesses 3557system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.202122 # mshr miss rate for ReadReq accesses 3558system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.506634 # mshr miss rate for ReadReq accesses 3559system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.310635 # mshr miss rate for ReadReq accesses 3560system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.376754 # mshr miss rate for ReadReq accesses 3561system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.089424 # mshr miss rate for ReadReq accesses 3562system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.193073 # mshr miss rate for ReadReq accesses 3563system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448841 # mshr miss rate for ReadReq accesses 3564system.l2c.ReadReq_mshr_miss_rate::total 0.243324 # mshr miss rate for ReadReq accesses 3565system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.779565 # mshr miss rate for WriteInvalidateReq accesses 3566system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.438283 # mshr miss rate for WriteInvalidateReq accesses 3567system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.691347 # mshr miss rate for WriteInvalidateReq accesses 3568system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.608561 # mshr miss rate for UpgradeReq accesses 3569system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.587728 # mshr miss rate for UpgradeReq accesses 3570system.l2c.UpgradeReq_mshr_miss_rate::total 0.598116 # mshr miss rate for UpgradeReq accesses 3571system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.615430 # mshr miss rate for SCUpgradeReq accesses 3572system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.590919 # mshr miss rate for SCUpgradeReq accesses 3573system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.604223 # mshr miss rate for SCUpgradeReq accesses 3574system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.618848 # mshr miss rate for ReadExReq accesses 3575system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.494171 # mshr miss rate for ReadExReq accesses 3576system.l2c.ReadExReq_mshr_miss_rate::total 0.565564 # mshr miss rate for ReadExReq accesses 3577system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.278972 # mshr miss rate for demand accesses 3578system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.346299 # mshr miss rate for demand accesses 3579system.l2c.demand_mshr_miss_rate::cpu0.inst 0.087381 # mshr miss rate for demand accesses 3580system.l2c.demand_mshr_miss_rate::cpu0.data 0.263819 # mshr miss rate for demand accesses 3581system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.506634 # mshr miss rate for demand accesses 3582system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.310635 # mshr miss rate for demand accesses 3583system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.376754 # mshr miss rate for demand accesses 3584system.l2c.demand_mshr_miss_rate::cpu1.inst 0.089424 # mshr miss rate for demand accesses 3585system.l2c.demand_mshr_miss_rate::cpu1.data 0.233817 # mshr miss rate for demand accesses 3586system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448841 # mshr miss rate for demand accesses 3587system.l2c.demand_mshr_miss_rate::total 0.262295 # mshr miss rate for demand accesses 3588system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.278972 # mshr miss rate for overall accesses 3589system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.346299 # mshr miss rate for overall accesses 3590system.l2c.overall_mshr_miss_rate::cpu0.inst 0.087381 # mshr miss rate for overall accesses 3591system.l2c.overall_mshr_miss_rate::cpu0.data 0.263819 # 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average ReadReq mshr miss latency 3602system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 82417.381349 # average ReadReq mshr miss latency 3603system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140724.568925 # average ReadReq mshr miss latency 3604system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75197.862633 # average ReadReq mshr miss latency 3605system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76589.297872 # average ReadReq mshr miss latency 3606system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67772.830989 # average ReadReq mshr miss latency 3607system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 84846.955925 # average ReadReq mshr miss latency 3608system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134178.399201 # average ReadReq mshr miss latency 3609system.l2c.ReadReq_avg_mshr_miss_latency::total 112198.907686 # average ReadReq mshr miss latency 3610system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 48918.341561 # average WriteInvalidateReq mshr miss latency 3611system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27337.914593 # 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average overall mshr miss latency 3631system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134178.399201 # average overall mshr miss latency 3632system.l2c.demand_avg_mshr_miss_latency::total 107317.450557 # average overall mshr miss latency 3633system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 72610.305401 # average overall mshr miss latency 3634system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74335.007430 # average overall mshr miss latency 3635system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67911.455258 # average overall mshr miss latency 3636system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80292.648521 # average overall mshr miss latency 3637system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140724.568925 # average overall mshr miss latency 3638system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75197.862633 # average overall mshr miss latency 3639system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76589.297872 # average overall mshr miss latency 3640system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67772.830989 # average overall mshr miss latency 3641system.l2c.overall_avg_mshr_miss_latency::cpu1.data 80445.957655 # average overall mshr miss latency 3642system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134178.399201 # average overall mshr miss latency 3643system.l2c.overall_avg_mshr_miss_latency::total 107317.450557 # average overall mshr miss latency | 3408system.l2c.writebacks::writebacks 1067007 # number of writebacks 3409system.l2c.writebacks::total 1067007 # number of writebacks 3410system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker 2 # number of ReadReq MSHR hits 3411system.l2c.ReadReq_mshr_hits::cpu0.inst 133 # number of ReadReq MSHR hits 3412system.l2c.ReadReq_mshr_hits::cpu0.data 17 # number of ReadReq MSHR hits 3413system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 2 # number of ReadReq MSHR hits 3414system.l2c.ReadReq_mshr_hits::cpu1.inst 90 # number of ReadReq MSHR hits 3415system.l2c.ReadReq_mshr_hits::cpu1.data 20 # number of ReadReq MSHR hits 3416system.l2c.ReadReq_mshr_hits::total 264 # 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number of ReadReq MSHR miss cycles 3484system.l2c.ReadReq_mshr_miss_latency::cpu1.data 9514272921 # number of ReadReq MSHR miss cycles 3485system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 29643980025 # number of ReadReq MSHR miss cycles 3486system.l2c.ReadReq_mshr_miss_latency::total 85885889998 # number of ReadReq MSHR miss cycles 3487system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 17416176424 # number of WriteInvalidateReq MSHR miss cycles 3488system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 3960645719 # number of WriteInvalidateReq MSHR miss cycles 3489system.l2c.WriteInvalidateReq_mshr_miss_latency::total 21376822143 # number of WriteInvalidateReq MSHR miss cycles 3490system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 814816958 # number of UpgradeReq MSHR miss cycles 3491system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 825298541 # number of UpgradeReq MSHR miss cycles 3492system.l2c.UpgradeReq_mshr_miss_latency::total 1640115499 # number of UpgradeReq MSHR miss cycles 3493system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 162191592 # number of SCUpgradeReq MSHR miss cycles 3494system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 159645428 # number of SCUpgradeReq MSHR miss cycles 3495system.l2c.SCUpgradeReq_mshr_miss_latency::total 321837020 # number of SCUpgradeReq MSHR miss cycles 3496system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5979693683 # number of ReadExReq MSHR miss cycles 3497system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4008215143 # number of ReadExReq MSHR miss cycles 3498system.l2c.ReadExReq_mshr_miss_latency::total 9987908826 # number of ReadExReq MSHR miss cycles 3499system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 95681979 # number of demand (read+write) MSHR miss cycles 3500system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 78660484 # number of demand (read+write) MSHR miss cycles 3501system.l2c.demand_mshr_miss_latency::cpu0.inst 4853701817 # number of demand (read+write) MSHR miss cycles 3502system.l2c.demand_mshr_miss_latency::cpu0.data 17104310841 # number of demand (read+write) MSHR miss cycles 3503system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 27259941357 # number of demand (read+write) MSHR miss cycles 3504system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 203927234 # number of demand (read+write) MSHR miss cycles 3505system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 198329749 # number of demand (read+write) MSHR miss cycles 3506system.l2c.demand_mshr_miss_latency::cpu1.inst 2912777274 # number of demand (read+write) MSHR miss cycles 3507system.l2c.demand_mshr_miss_latency::cpu1.data 13522488064 # number of demand (read+write) MSHR miss cycles 3508system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 29643980025 # number of demand (read+write) MSHR miss cycles 3509system.l2c.demand_mshr_miss_latency::total 95873798824 # number of demand (read+write) MSHR miss cycles 3510system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 95681979 # number of overall MSHR miss cycles 3511system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 78660484 # number of overall MSHR miss cycles 3512system.l2c.overall_mshr_miss_latency::cpu0.inst 4853701817 # number of overall MSHR miss cycles 3513system.l2c.overall_mshr_miss_latency::cpu0.data 17104310841 # number of overall MSHR miss cycles 3514system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 27259941357 # number of overall MSHR miss cycles 3515system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 203927234 # number of overall MSHR miss cycles 3516system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 198329749 # number of overall MSHR miss cycles 3517system.l2c.overall_mshr_miss_latency::cpu1.inst 2912777274 # number of overall MSHR miss cycles 3518system.l2c.overall_mshr_miss_latency::cpu1.data 13522488064 # number of overall MSHR miss cycles 3519system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 29643980025 # number of overall MSHR miss cycles 3520system.l2c.overall_mshr_miss_latency::total 95873798824 # number of overall MSHR miss cycles 3521system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1285623000 # number of ReadReq MSHR uncacheable cycles 3522system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4853989000 # number of ReadReq MSHR uncacheable cycles 3523system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4264250 # number of ReadReq MSHR uncacheable cycles 3524system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 516390251 # number of ReadReq MSHR uncacheable cycles 3525system.l2c.ReadReq_mshr_uncacheable_latency::total 6660266501 # number of ReadReq MSHR uncacheable cycles 3526system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4658794041 # number of WriteReq MSHR uncacheable cycles 3527system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 621932502 # number of WriteReq MSHR uncacheable cycles 3528system.l2c.WriteReq_mshr_uncacheable_latency::total 5280726543 # number of WriteReq MSHR uncacheable cycles 3529system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1285623000 # number of overall MSHR uncacheable cycles 3530system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9512783041 # number of overall MSHR uncacheable cycles 3531system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4264250 # number of overall MSHR uncacheable cycles 3532system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1138322753 # number of overall MSHR uncacheable cycles 3533system.l2c.overall_mshr_uncacheable_latency::total 11940993044 # number of overall MSHR uncacheable cycles 3534system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.151892 # mshr miss rate for ReadReq accesses 3535system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.157590 # mshr miss rate for ReadReq accesses 3536system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.102273 # mshr miss rate for ReadReq accesses 3537system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.181270 # mshr miss rate for ReadReq accesses 3538system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.402140 # mshr miss rate for ReadReq accesses 3539system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.303129 # mshr miss rate for ReadReq accesses 3540system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.370440 # mshr miss rate for ReadReq accesses 3541system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.066280 # mshr miss rate for ReadReq accesses 3542system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.175427 # mshr miss rate for ReadReq accesses 3543system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.457833 # mshr miss rate for ReadReq accesses 3544system.l2c.ReadReq_mshr_miss_rate::total 0.216820 # mshr miss rate for ReadReq accesses 3545system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.747588 # mshr miss rate for WriteInvalidateReq accesses 3546system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.499888 # mshr miss rate for WriteInvalidateReq accesses 3547system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.675463 # mshr miss rate for WriteInvalidateReq accesses 3548system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.579736 # mshr miss rate for UpgradeReq accesses 3549system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.646296 # mshr miss rate for UpgradeReq accesses 3550system.l2c.UpgradeReq_mshr_miss_rate::total 0.611444 # mshr miss rate for UpgradeReq accesses 3551system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.598452 # mshr miss rate for SCUpgradeReq accesses 3552system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.622449 # mshr miss rate for SCUpgradeReq accesses 3553system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.610112 # mshr miss rate for SCUpgradeReq accesses 3554system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.580029 # mshr miss rate for ReadExReq accesses 3555system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.508758 # mshr miss rate for ReadExReq accesses 3556system.l2c.ReadExReq_mshr_miss_rate::total 0.548649 # mshr miss rate for ReadExReq accesses 3557system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.151892 # mshr miss rate for demand accesses 3558system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.157590 # mshr miss rate for demand accesses 3559system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102273 # mshr miss rate for demand accesses 3560system.l2c.demand_mshr_miss_rate::cpu0.data 0.242264 # mshr miss rate for demand accesses 3561system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.402140 # mshr miss rate for demand accesses 3562system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.303129 # mshr miss rate for demand accesses 3563system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.370440 # mshr miss rate for demand accesses 3564system.l2c.demand_mshr_miss_rate::cpu1.inst 0.066280 # mshr miss rate for demand accesses 3565system.l2c.demand_mshr_miss_rate::cpu1.data 0.220462 # mshr miss rate for demand accesses 3566system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.457833 # mshr miss rate for demand accesses 3567system.l2c.demand_mshr_miss_rate::total 0.236645 # mshr miss rate for demand accesses 3568system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.151892 # mshr miss rate for overall accesses 3569system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.157590 # mshr miss rate for overall accesses 3570system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102273 # mshr miss rate for overall accesses 3571system.l2c.overall_mshr_miss_rate::cpu0.data 0.242264 # mshr miss rate for overall accesses 3572system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.402140 # mshr miss rate for overall accesses 3573system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.303129 # mshr miss rate for overall accesses 3574system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.370440 # mshr miss rate for overall accesses 3575system.l2c.overall_mshr_miss_rate::cpu1.inst 0.066280 # mshr miss rate for overall accesses 3576system.l2c.overall_mshr_miss_rate::cpu1.data 0.220462 # mshr miss rate for overall accesses 3577system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.457833 # mshr miss rate for overall accesses 3578system.l2c.overall_mshr_miss_rate::total 0.236645 # mshr miss rate for overall accesses 3579system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 80812.482264 # average ReadReq mshr miss latency 3580system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 82626.558824 # average ReadReq mshr miss latency 3581system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74621.822413 # average ReadReq mshr miss latency 3582system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 85881.831473 # average ReadReq mshr miss latency 3583system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133955.485784 # average ReadReq mshr miss latency 3584system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77953.835627 # average ReadReq mshr miss latency 3585system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77201.147917 # average ReadReq mshr miss latency 3586system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 73887.100452 # average ReadReq mshr miss latency 3587system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 83462.927180 # average ReadReq mshr miss latency 3588system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130082.497499 # average ReadReq mshr miss latency 3589system.l2c.ReadReq_avg_mshr_miss_latency::total 109172.214092 # average ReadReq mshr miss latency 3590system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39770.223840 # average WriteInvalidateReq mshr miss latency 3591system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32925.810283 # average WriteInvalidateReq mshr miss latency 3592system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 38295.304891 # average WriteInvalidateReq mshr miss latency 3593system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17845.312265 # average UpgradeReq mshr miss latency 3594system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17820.788603 # average UpgradeReq mshr miss latency 3595system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17832.963641 # average UpgradeReq mshr miss latency 3596system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17782.215985 # average SCUpgradeReq mshr miss latency 3597system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17803.660979 # average SCUpgradeReq mshr miss latency 3598system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17792.847192 # average SCUpgradeReq mshr miss latency 3599system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79892.229254 # average ReadExReq mshr miss latency 3600system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 77613.909784 # average ReadExReq mshr miss latency 3601system.l2c.ReadExReq_avg_mshr_miss_latency::total 78962.043055 # average ReadExReq mshr miss latency 3602system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80812.482264 # average overall mshr miss latency 3603system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82626.558824 # average overall mshr miss latency 3604system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74621.822413 # average overall mshr miss latency 3605system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83688.360665 # average overall mshr miss latency 3606system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133955.485784 # average overall mshr miss latency 3607system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77953.835627 # average overall mshr miss latency 3608system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77201.147917 # average overall mshr miss latency 3609system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73887.100452 # average overall mshr miss latency 3610system.l2c.demand_avg_mshr_miss_latency::cpu1.data 81639.295954 # average overall mshr miss latency 3611system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130082.497499 # average overall mshr miss latency 3612system.l2c.demand_avg_mshr_miss_latency::total 104987.673799 # average overall mshr miss latency 3613system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80812.482264 # average overall mshr miss latency 3614system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82626.558824 # average overall mshr miss latency 3615system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74621.822413 # average overall mshr miss latency 3616system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83688.360665 # average overall mshr miss latency 3617system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133955.485784 # average overall mshr miss latency 3618system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77953.835627 # average overall mshr miss latency 3619system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77201.147917 # average overall mshr miss latency 3620system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73887.100452 # average overall mshr miss latency 3621system.l2c.overall_avg_mshr_miss_latency::cpu1.data 81639.295954 # average overall mshr miss latency 3622system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130082.497499 # average overall mshr miss latency 3623system.l2c.overall_avg_mshr_miss_latency::total 104987.673799 # average overall mshr miss latency |
| 3644system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 3645system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 3646system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 3647system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 3648system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3649system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 3650system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 3651system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 3652system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 3653system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 3654system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 3655system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 3656system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 3657system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 3624system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 3625system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 3626system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 3627system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 3628system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 3629system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 3630system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 3631system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 3632system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 3633system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 3634system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 3635system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 3636system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 3637system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 3658system.membus.trans_dist::ReadReq 1032278 # Transaction distribution 3659system.membus.trans_dist::ReadResp 1032278 # Transaction distribution 3660system.membus.trans_dist::WriteReq 38581 # Transaction distribution 3661system.membus.trans_dist::WriteResp 38581 # Transaction distribution 3662system.membus.trans_dist::Writeback 1347712 # Transaction distribution 3663system.membus.trans_dist::WriteInvalidateReq 689975 # Transaction distribution 3664system.membus.trans_dist::WriteInvalidateResp 689975 # Transaction distribution 3665system.membus.trans_dist::UpgradeReq 447979 # Transaction distribution 3666system.membus.trans_dist::SCUpgradeReq 332386 # Transaction distribution 3667system.membus.trans_dist::UpgradeResp 121150 # Transaction distribution 3668system.membus.trans_dist::ReadExReq 152231 # Transaction distribution 3669system.membus.trans_dist::ReadExResp 135895 # Transaction distribution 3670system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123088 # Packet count per connected master and slave (bytes) | 3638system.membus.trans_dist::ReadReq 855568 # Transaction distribution 3639system.membus.trans_dist::ReadResp 855568 # Transaction distribution 3640system.membus.trans_dist::WriteReq 38542 # Transaction distribution 3641system.membus.trans_dist::WriteResp 38542 # Transaction distribution 3642system.membus.trans_dist::Writeback 1173701 # Transaction distribution 3643system.membus.trans_dist::WriteInvalidateReq 661649 # Transaction distribution 3644system.membus.trans_dist::WriteInvalidateResp 661649 # Transaction distribution 3645system.membus.trans_dist::UpgradeReq 438223 # Transaction distribution 3646system.membus.trans_dist::SCUpgradeReq 309934 # Transaction distribution 3647system.membus.trans_dist::UpgradeResp 117397 # Transaction distribution 3648system.membus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution 3649system.membus.trans_dist::ReadExReq 139893 # Transaction distribution 3650system.membus.trans_dist::ReadExResp 122444 # Transaction distribution 3651system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122608 # Packet count per connected master and slave (bytes) |
| 3671system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) | 3652system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) |
| 3672system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25972 # Packet count per connected master and slave (bytes) 3673system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5571157 # Packet count per connected master and slave (bytes) 3674system.membus.pkt_count_system.l2c.mem_side::total 5720295 # Packet count per connected master and slave (bytes) 3675system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335903 # Packet count per connected master and slave (bytes) 3676system.membus.pkt_count_system.iocache.mem_side::total 335903 # Packet count per connected master and slave (bytes) 3677system.membus.pkt_count::total 6056198 # Packet count per connected master and slave (bytes) 3678system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156195 # Cumulative packet size per connected master and slave (bytes) | 3653system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26394 # Packet count per connected master and slave (bytes) 3654system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4925384 # Packet count per connected master and slave (bytes) 3655system.membus.pkt_count_system.l2c.mem_side::total 5074464 # Packet count per connected master and slave (bytes) 3656system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335910 # Packet count per connected master and slave (bytes) 3657system.membus.pkt_count_system.iocache.mem_side::total 335910 # Packet count per connected master and slave (bytes) 3658system.membus.pkt_count::total 5410374 # Packet count per connected master and slave (bytes) 3659system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155738 # Cumulative packet size per connected master and slave (bytes) |
| 3679system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) | 3660system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) |
| 3680system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51944 # Cumulative packet size per connected master and slave (bytes) 3681system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 187423448 # Cumulative packet size per connected master and slave (bytes) 3682system.membus.pkt_size_system.l2c.mem_side::total 187632159 # Cumulative packet size per connected master and slave (bytes) 3683system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14096832 # Cumulative packet size per connected master and slave (bytes) 3684system.membus.pkt_size_system.iocache.mem_side::total 14096832 # Cumulative packet size per connected master and slave (bytes) 3685system.membus.pkt_size::total 201728991 # Cumulative packet size per connected master and slave (bytes) 3686system.membus.snoops 678374 # Total snoops (count) 3687system.membus.snoop_fanout::samples 3943213 # Request fanout histogram | 3661system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52788 # Cumulative packet size per connected master and slave (bytes) 3662system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 162304200 # Cumulative packet size per connected master and slave (bytes) 3663system.membus.pkt_size_system.l2c.mem_side::total 162513298 # Cumulative packet size per connected master and slave (bytes) 3664system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14098112 # Cumulative packet size per connected master and slave (bytes) 3665system.membus.pkt_size_system.iocache.mem_side::total 14098112 # Cumulative packet size per connected master and slave (bytes) 3666system.membus.pkt_size::total 176611410 # Cumulative packet size per connected master and slave (bytes) 3667system.membus.snoops 651055 # Total snoops (count) 3668system.membus.snoop_fanout::samples 3600660 # Request fanout histogram |
| 3688system.membus.snoop_fanout::mean 1 # Request fanout histogram 3689system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3690system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3691system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 3669system.membus.snoop_fanout::mean 1 # Request fanout histogram 3670system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3671system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3672system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 3692system.membus.snoop_fanout::1 3943213 100.00% 100.00% # Request fanout histogram | 3673system.membus.snoop_fanout::1 3600660 100.00% 100.00% # Request fanout histogram |
| 3693system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3694system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3695system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3696system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 3674system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3675system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3676system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3677system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 3697system.membus.snoop_fanout::total 3943213 # Request fanout histogram 3698system.membus.reqLayer0.occupancy 98700492 # Layer occupancy (ticks) | 3678system.membus.snoop_fanout::total 3600660 # Request fanout histogram 3679system.membus.reqLayer0.occupancy 98274497 # Layer occupancy (ticks) |
| 3699system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 3680system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 3700system.membus.reqLayer1.occupancy 45500 # Layer occupancy (ticks) | 3681system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) |
| 3701system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 3682system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 3702system.membus.reqLayer2.occupancy 21600991 # Layer occupancy (ticks) | 3683system.membus.reqLayer2.occupancy 22081484 # Layer occupancy (ticks) |
| 3703system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 3684system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 3704system.membus.reqLayer5.occupancy 19952700228 # Layer occupancy (ticks) | 3685system.membus.reqLayer5.occupancy 10699049257 # Layer occupancy (ticks) |
| 3705system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 3686system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 3706system.membus.respLayer2.occupancy 11115498245 # Layer occupancy (ticks) | 3687system.membus.respLayer2.occupancy 5725496770 # Layer occupancy (ticks) |
| 3707system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 3688system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 3708system.membus.respLayer3.occupancy 187180539 # Layer occupancy (ticks) | 3689system.membus.respLayer3.occupancy 151866715 # Layer occupancy (ticks) |
| 3709system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3710system.realview.ethernet.txBytes 966 # Bytes Transmitted 3711system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3712system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3713system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3714system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3715system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3716system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA --- 27 unchanged lines hidden (view full) --- 3744system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3745system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3746system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3747system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3748system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3749system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3750system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3751system.realview.ethernet.droppedPackets 0 # number of packets dropped | 3690system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3691system.realview.ethernet.txBytes 966 # Bytes Transmitted 3692system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3693system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3694system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3695system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3696system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3697system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA --- 27 unchanged lines hidden (view full) --- 3725system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3726system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3727system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3728system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3729system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3730system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3731system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3732system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 3752system.toL2Bus.trans_dist::ReadReq 4932840 # Transaction distribution 3753system.toL2Bus.trans_dist::ReadResp 4925609 # Transaction distribution 3754system.toL2Bus.trans_dist::WriteReq 38581 # Transaction distribution 3755system.toL2Bus.trans_dist::WriteResp 38581 # Transaction distribution 3756system.toL2Bus.trans_dist::Writeback 2564009 # Transaction distribution 3757system.toL2Bus.trans_dist::WriteInvalidateReq 955023 # Transaction distribution 3758system.toL2Bus.trans_dist::WriteInvalidateResp 848293 # Transaction distribution 3759system.toL2Bus.trans_dist::UpgradeReq 504313 # Transaction distribution 3760system.toL2Bus.trans_dist::SCUpgradeReq 344758 # Transaction distribution 3761system.toL2Bus.trans_dist::UpgradeResp 849071 # Transaction distribution 3762system.toL2Bus.trans_dist::SCUpgradeFailReq 157 # Transaction distribution 3763system.toL2Bus.trans_dist::UpgradeFailResp 157 # Transaction distribution 3764system.toL2Bus.trans_dist::ReadExReq 306644 # Transaction distribution 3765system.toL2Bus.trans_dist::ReadExResp 306644 # Transaction distribution 3766system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8600677 # Packet count per connected master and slave (bytes) 3767system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6275419 # Packet count per connected master and slave (bytes) 3768system.toL2Bus.pkt_count::total 14876096 # Packet count per connected master and slave (bytes) 3769system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 289885704 # Cumulative packet size per connected master and slave (bytes) 3770system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 198430935 # Cumulative packet size per connected master and slave (bytes) 3771system.toL2Bus.pkt_size::total 488316639 # Cumulative packet size per connected master and slave (bytes) 3772system.toL2Bus.snoops 1740265 # Total snoops (count) 3773system.toL2Bus.snoop_fanout::samples 9550575 # Request fanout histogram 3774system.toL2Bus.snoop_fanout::mean 1.012108 # Request fanout histogram 3775system.toL2Bus.snoop_fanout::stdev 0.109370 # Request fanout histogram | 3733system.toL2Bus.trans_dist::ReadReq 4566673 # Transaction distribution 3734system.toL2Bus.trans_dist::ReadResp 4559437 # Transaction distribution 3735system.toL2Bus.trans_dist::WriteReq 38542 # Transaction distribution 3736system.toL2Bus.trans_dist::WriteResp 38542 # Transaction distribution 3737system.toL2Bus.trans_dist::Writeback 2358990 # Transaction distribution 3738system.toL2Bus.trans_dist::WriteInvalidateReq 933261 # Transaction distribution 3739system.toL2Bus.trans_dist::WriteInvalidateResp 826411 # Transaction distribution 3740system.toL2Bus.trans_dist::UpgradeReq 489333 # Transaction distribution 3741system.toL2Bus.trans_dist::SCUpgradeReq 321493 # Transaction distribution 3742system.toL2Bus.trans_dist::UpgradeResp 810826 # Transaction distribution 3743system.toL2Bus.trans_dist::SCUpgradeFailReq 208 # Transaction distribution 3744system.toL2Bus.trans_dist::UpgradeFailResp 208 # Transaction distribution 3745system.toL2Bus.trans_dist::ReadExReq 288168 # Transaction distribution 3746system.toL2Bus.trans_dist::ReadExResp 288168 # Transaction distribution 3747system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7677415 # Packet count per connected master and slave (bytes) 3748system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6169065 # Packet count per connected master and slave (bytes) 3749system.toL2Bus.pkt_count::total 13846480 # Packet count per connected master and slave (bytes) 3750system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255017262 # Cumulative packet size per connected master and slave (bytes) 3751system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 196496484 # Cumulative packet size per connected master and slave (bytes) 3752system.toL2Bus.pkt_size::total 451513746 # Cumulative packet size per connected master and slave (bytes) 3753system.toL2Bus.snoops 1675443 # Total snoops (count) 3754system.toL2Bus.snoop_fanout::samples 8934179 # Request fanout histogram 3755system.toL2Bus.snoop_fanout::mean 1.012956 # Request fanout histogram 3756system.toL2Bus.snoop_fanout::stdev 0.113084 # Request fanout histogram |
| 3776system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3777system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 3757system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3758system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 3778system.toL2Bus.snoop_fanout::1 9434933 98.79% 98.79% # Request fanout histogram 3779system.toL2Bus.snoop_fanout::2 115642 1.21% 100.00% # Request fanout histogram | 3759system.toL2Bus.snoop_fanout::1 8818430 98.70% 98.70% # Request fanout histogram 3760system.toL2Bus.snoop_fanout::2 115749 1.30% 100.00% # Request fanout histogram |
| 3780system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3781system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 3782system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 3761system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3762system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 3763system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 3783system.toL2Bus.snoop_fanout::total 9550575 # Request fanout histogram 3784system.toL2Bus.reqLayer0.occupancy 18722164156 # Layer occupancy (ticks) | 3764system.toL2Bus.snoop_fanout::total 8934179 # Request fanout histogram 3765system.toL2Bus.reqLayer0.occupancy 7984163233 # Layer occupancy (ticks) |
| 3785system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 3766system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 3786system.toL2Bus.snoopLayer0.occupancy 7552500 # Layer occupancy (ticks) | 3767system.toL2Bus.snoopLayer0.occupancy 2491500 # Layer occupancy (ticks) |
| 3787system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 3768system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 3788system.toL2Bus.respLayer0.occupancy 13115425494 # Layer occupancy (ticks) | 3769system.toL2Bus.respLayer0.occupancy 4301185209 # Layer occupancy (ticks) |
| 3789system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 3770system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 3790system.toL2Bus.respLayer1.occupancy 11201753623 # Layer occupancy (ticks) | 3771system.toL2Bus.respLayer1.occupancy 3898685571 # Layer occupancy (ticks) |
| 3791system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3792system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 3772system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3773system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 3793system.cpu0.kern.inst.quiesce 13602 # number of quiesce instructions executed | 3774system.cpu0.kern.inst.quiesce 13668 # number of quiesce instructions executed |
| 3794system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 3775system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 3795system.cpu1.kern.inst.quiesce 5345 # number of quiesce instructions executed | 3776system.cpu1.kern.inst.quiesce 5222 # number of quiesce instructions executed |
| 3796 3797---------- End Simulation Statistics ---------- | 3777 3778---------- End Simulation Statistics ---------- |