3,5c3,5
< sim_seconds 47.384940 # Number of seconds simulated
< sim_ticks 47384940455000 # Number of ticks simulated
< final_tick 47384940455000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 47.341923 # Number of seconds simulated
> sim_ticks 47341923254000 # Number of ticks simulated
> final_tick 47341923254000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 206357 # Simulator instruction rate (inst/s)
< host_op_rate 242664 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 10614318936 # Simulator tick rate (ticks/s)
< host_mem_usage 793572 # Number of bytes of host memory used
< host_seconds 4464.25 # Real time elapsed on the host
< sim_insts 921230293 # Number of instructions simulated
< sim_ops 1083311023 # Number of ops (including micro ops) simulated
---
> host_inst_rate 198941 # Simulator instruction rate (inst/s)
> host_op_rate 237233 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 10723675807 # Simulator tick rate (ticks/s)
> host_mem_usage 786956 # Number of bytes of host memory used
> host_seconds 4414.71 # Real time elapsed on the host
> sim_insts 878265186 # Number of instructions simulated
> sim_ops 1047316960 # Number of ops (including micro ops) simulated
16,32c16,32
< system.physmem.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu0.dtb.walker 222656 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.itb.walker 215552 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.inst 4481312 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 16941064 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 21659840 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 116096 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.itb.walker 80000 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 2978912 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 10395024 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 12881984 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 421760 # Number of bytes read from this memory
< system.physmem.bytes_read::total 70394200 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 4481312 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 2978912 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 7460224 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 86479488 # Number of bytes written to this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu0.dtb.walker 242176 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.itb.walker 233728 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.inst 4193568 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 18888648 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 25252160 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 159808 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.itb.walker 110720 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 3691360 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 11578384 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 16897024 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 434368 # Number of bytes read from this memory
> system.physmem.bytes_read::total 81681944 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 4193568 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 3691360 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 7884928 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 97721664 # Number of bytes written to this memory
35,48c35,48
< system.physmem.bytes_written::total 86500072 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.dtb.walker 3479 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.itb.walker 3368 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.inst 85973 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 264717 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 338435 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 1814 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.itb.walker 1250 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 46589 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 162435 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 201281 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6590 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1115931 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1351242 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 97742248 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.dtb.walker 3784 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.itb.walker 3652 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.inst 67077 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 295148 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 394565 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 2497 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.itb.walker 1730 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 57721 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 180925 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 264016 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6787 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1277902 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1526901 # Number of write requests responded to by this memory
51,68c51,68
< system.physmem.num_writes::total 1353816 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 4699 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.itb.walker 4549 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.inst 94572 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 357520 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 457104 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 2450 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.itb.walker 1688 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 62866 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 219374 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 271858 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 8901 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1485582 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 94572 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 62866 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 157439 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1825042 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 1529475 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 5115 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.itb.walker 4937 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.inst 88580 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 398984 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 533400 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 3376 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.itb.walker 2339 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 77972 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 244569 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 356915 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 9175 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1725362 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 88580 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 77972 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 166553 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 2064168 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
70,94c70,94
< system.physmem.bw_write::total 1825476 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1825042 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 4699 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.itb.walker 4549 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 94572 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 357954 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 457104 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 2450 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.itb.walker 1688 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 62866 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 219374 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 271858 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 8901 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 3311058 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 1115931 # Number of read requests accepted
< system.physmem.writeReqs 1353816 # Number of write requests accepted
< system.physmem.readBursts 1115931 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1353816 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 71392384 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 27200 # Total number of bytes read from write queue
< system.physmem.bytesWritten 86499392 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 70394200 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 86500072 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 425 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.bw_write::total 2064602 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 2064168 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 5115 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.itb.walker 4937 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 88580 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 399418 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 533400 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 3376 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.itb.walker 2339 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 77972 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 244569 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 356915 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 9175 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3789964 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 1277902 # Number of read requests accepted
> system.physmem.writeReqs 1529475 # Number of write requests accepted
> system.physmem.readBursts 1277902 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1529475 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 81759232 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 26496 # Total number of bytes read from write queue
> system.physmem.bytesWritten 97740224 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 81681944 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 97742248 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 414 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 2256 # Number of DRAM write bursts merged with an existing one
96,127c96,127
< system.physmem.perBankRdBursts::0 66640 # Per bank write bursts
< system.physmem.perBankRdBursts::1 69755 # Per bank write bursts
< system.physmem.perBankRdBursts::2 65507 # Per bank write bursts
< system.physmem.perBankRdBursts::3 67407 # Per bank write bursts
< system.physmem.perBankRdBursts::4 65920 # Per bank write bursts
< system.physmem.perBankRdBursts::5 70505 # Per bank write bursts
< system.physmem.perBankRdBursts::6 65125 # Per bank write bursts
< system.physmem.perBankRdBursts::7 71371 # Per bank write bursts
< system.physmem.perBankRdBursts::8 68061 # Per bank write bursts
< system.physmem.perBankRdBursts::9 95897 # Per bank write bursts
< system.physmem.perBankRdBursts::10 65782 # Per bank write bursts
< system.physmem.perBankRdBursts::11 68970 # Per bank write bursts
< system.physmem.perBankRdBursts::12 60174 # Per bank write bursts
< system.physmem.perBankRdBursts::13 71971 # Per bank write bursts
< system.physmem.perBankRdBursts::14 71235 # Per bank write bursts
< system.physmem.perBankRdBursts::15 71186 # Per bank write bursts
< system.physmem.perBankWrBursts::0 81261 # Per bank write bursts
< system.physmem.perBankWrBursts::1 86034 # Per bank write bursts
< system.physmem.perBankWrBursts::2 81926 # Per bank write bursts
< system.physmem.perBankWrBursts::3 83311 # Per bank write bursts
< system.physmem.perBankWrBursts::4 82546 # Per bank write bursts
< system.physmem.perBankWrBursts::5 86081 # Per bank write bursts
< system.physmem.perBankWrBursts::6 81799 # Per bank write bursts
< system.physmem.perBankWrBursts::7 86537 # Per bank write bursts
< system.physmem.perBankWrBursts::8 86254 # Per bank write bursts
< system.physmem.perBankWrBursts::9 89944 # Per bank write bursts
< system.physmem.perBankWrBursts::10 82817 # Per bank write bursts
< system.physmem.perBankWrBursts::11 84554 # Per bank write bursts
< system.physmem.perBankWrBursts::12 78968 # Per bank write bursts
< system.physmem.perBankWrBursts::13 86566 # Per bank write bursts
< system.physmem.perBankWrBursts::14 86628 # Per bank write bursts
< system.physmem.perBankWrBursts::15 86327 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 74308 # Per bank write bursts
> system.physmem.perBankRdBursts::1 87985 # Per bank write bursts
> system.physmem.perBankRdBursts::2 79775 # Per bank write bursts
> system.physmem.perBankRdBursts::3 80704 # Per bank write bursts
> system.physmem.perBankRdBursts::4 79279 # Per bank write bursts
> system.physmem.perBankRdBursts::5 87661 # Per bank write bursts
> system.physmem.perBankRdBursts::6 78349 # Per bank write bursts
> system.physmem.perBankRdBursts::7 78833 # Per bank write bursts
> system.physmem.perBankRdBursts::8 69442 # Per bank write bursts
> system.physmem.perBankRdBursts::9 78370 # Per bank write bursts
> system.physmem.perBankRdBursts::10 69793 # Per bank write bursts
> system.physmem.perBankRdBursts::11 81996 # Per bank write bursts
> system.physmem.perBankRdBursts::12 80451 # Per bank write bursts
> system.physmem.perBankRdBursts::13 82396 # Per bank write bursts
> system.physmem.perBankRdBursts::14 80116 # Per bank write bursts
> system.physmem.perBankRdBursts::15 88030 # Per bank write bursts
> system.physmem.perBankWrBursts::0 92185 # Per bank write bursts
> system.physmem.perBankWrBursts::1 101129 # Per bank write bursts
> system.physmem.perBankWrBursts::2 94103 # Per bank write bursts
> system.physmem.perBankWrBursts::3 97328 # Per bank write bursts
> system.physmem.perBankWrBursts::4 94264 # Per bank write bursts
> system.physmem.perBankWrBursts::5 99023 # Per bank write bursts
> system.physmem.perBankWrBursts::6 94391 # Per bank write bursts
> system.physmem.perBankWrBursts::7 95568 # Per bank write bursts
> system.physmem.perBankWrBursts::8 90026 # Per bank write bursts
> system.physmem.perBankWrBursts::9 95851 # Per bank write bursts
> system.physmem.perBankWrBursts::10 88927 # Per bank write bursts
> system.physmem.perBankWrBursts::11 96294 # Per bank write bursts
> system.physmem.perBankWrBursts::12 94934 # Per bank write bursts
> system.physmem.perBankWrBursts::13 97047 # Per bank write bursts
> system.physmem.perBankWrBursts::14 95210 # Per bank write bursts
> system.physmem.perBankWrBursts::15 100911 # Per bank write bursts
129,130c129,130
< system.physmem.numWrRetry 51513 # Number of times write queue was full causing retry
< system.physmem.totGap 47384938876500 # Total gap between requests
---
> system.physmem.numWrRetry 51774 # Number of times write queue was full causing retry
> system.physmem.totGap 47341921675500 # Total gap between requests
135c135
< system.physmem.readPktSize::4 21333 # Read request sizes (log2)
---
> system.physmem.readPktSize::4 2133 # Read request sizes (log2)
137c137
< system.physmem.readPktSize::6 1094573 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 1275744 # Read request sizes (log2)
144,169c144,169
< system.physmem.writePktSize::6 1351242 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 480312 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 254385 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 111988 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 68856 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 44885 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 37588 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 34371 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 31850 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 28995 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 8446 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 4926 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 2904 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 1783 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 1395 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 820 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 687 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 582 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 476 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 149 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 97 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1526901 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 505708 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 298665 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 136731 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 85460 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 55927 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 46831 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 42547 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 39408 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 35921 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 11095 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 6380 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 3835 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 2485 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 1956 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 1332 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 1133 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 952 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 753 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 214 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 132 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see
192,268c192,268
< system.physmem.wrQLenPdf::15 22318 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 26304 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 36819 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 42386 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 47455 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 51611 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 56891 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 62379 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 68066 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 69883 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 74729 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 78908 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 77080 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 78119 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 84175 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 91218 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 81081 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 75935 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 8194 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 4666 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 3474 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 2709 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 2176 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 1885 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 1809 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 1719 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 1469 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 1479 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 1477 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 1621 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 1614 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 1876 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 1830 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 1798 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 1799 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 1943 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 1999 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 2219 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 2498 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 2690 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 2884 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 3113 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 3416 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 3559 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 3969 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 4586 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 5969 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 24986 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 120772 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 1035166 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 152.526679 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 102.371009 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 198.170623 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 664281 64.17% 64.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 215041 20.77% 84.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 59106 5.71% 90.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 25397 2.45% 93.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 20542 1.98% 95.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 11502 1.11% 96.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 7604 0.73% 96.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 6193 0.60% 97.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 25500 2.46% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1035166 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 63814 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 17.480459 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 70.581857 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-511 63808 99.99% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 63814 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 63814 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 21.179569 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.530322 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 597.849869 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::0-4095 63812 100.00% 100.00% # Writes before turning the bus around for reads
---
> system.physmem.wrQLenPdf::15 24179 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 28209 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 39999 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 46492 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 52355 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 57811 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 64510 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 71167 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 77564 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 80217 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 85971 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 89992 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 89616 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 91327 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 98798 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 107236 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 96475 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 90527 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 10742 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 6106 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 4571 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 3497 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 2697 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 2502 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 2142 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 1954 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 1797 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 1675 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 1702 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 1596 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 1489 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 1728 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 1697 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 1857 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 2065 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 2040 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 2043 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 2289 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 2323 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 2551 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 2701 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 3106 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 3300 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 3341 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 3948 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 4411 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 6171 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 25276 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 121442 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 1170396 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 153.366156 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 102.854296 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 197.868960 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 748847 63.98% 63.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 241823 20.66% 84.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 67607 5.78% 90.42% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 29756 2.54% 92.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 24374 2.08% 95.05% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 14066 1.20% 96.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 9299 0.79% 97.04% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 7338 0.63% 97.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 27286 2.33% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1170396 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 74463 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 17.155890 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 20.196232 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-255 74449 99.98% 99.98% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::256-511 8 0.01% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::512-767 3 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 74463 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 74463 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.509394 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.370303 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 552.030208 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::0-4095 74461 100.00% 100.00% # Writes before turning the bus around for reads
271,275c271,275
< system.physmem.wrPerTurnAround::total 63814 # Writes before turning the bus around for reads
< system.physmem.totQLat 67332860089 # Total ticks spent queuing
< system.physmem.totMemAccLat 88248597589 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 5577530000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 60360.82 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::total 74463 # Writes before turning the bus around for reads
> system.physmem.totQLat 79629370316 # Total ticks spent queuing
> system.physmem.totMemAccLat 103582270316 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 6387440000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 62332.77 # Average queueing delay per DRAM burst
277,281c277,281
< system.physmem.avgMemAccLat 79110.82 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1.51 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 1.83 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 1.49 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 1.83 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 81082.77 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1.73 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 2.06 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 1.73 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 2.06 # Average system write bandwidth in MiByte/s
285,286c285,286
< system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
< system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
---
> system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
> system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing
288,332c288,332
< system.physmem.readRowHits 837889 # Number of row buffer hits during reads
< system.physmem.writeRowHits 593994 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 75.11 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 43.95 # Row buffer hit rate for writes
< system.physmem.avgGap 19186151.00 # Average gap between requests
< system.physmem.pageHitRate 58.04 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 3662384460 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 1946584530 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 3871522200 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 3494763900 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 31929318720.000008 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 40834926540 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1598586240 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 62046559410 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 43455299520 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 11294770338285 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 11487626755995 # Total energy per rank (pJ)
< system.physmem_0.averagePower 242.432018 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 47291190900816 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 2771331378 # Time in different power states
< system.physmem_0.memoryStateTime::REF 13558872000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 47041958774500 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 113164787559 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 77419210306 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 136067479257 # Time in different power states
< system.physmem_1.actEnergy 3728772180 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 1981870440 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 4093190640 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 3560342760 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 33599910240.000008 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 42188393820 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 1621939680 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 66725147910 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 45519792000 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 11290481164380 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 11493516343440 # Total energy per rank (pJ)
< system.physmem_1.averagePower 242.556311 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 47288162727367 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 2732090205 # Time in different power states
< system.physmem_1.memoryStateTime::REF 14267508000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 47023294872500 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 118540781222 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 79778077178 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 146327125895 # Time in different power states
< system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
---
> system.physmem.readRowHits 958718 # Number of row buffer hits during reads
> system.physmem.writeRowHits 675564 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 75.05 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 44.23 # Row buffer hit rate for writes
> system.physmem.avgGap 16863400.13 # Average gap between requests
> system.physmem.pageHitRate 58.27 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 4260723600 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 2264628300 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 4618823160 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 4008913020 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 30164687280.000008 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 41855751510 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1419463680 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 63813765750 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 36794590560 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 11286440815140 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 11475654576000 # Total energy per rank (pJ)
> system.physmem_0.averagePower 242.399417 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 47246408217619 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 2341242543 # Time in different power states
> system.physmem_0.memoryStateTime::REF 12803196000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 47010648524500 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 95818811721 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 80368685838 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 139942793398 # Time in different power states
> system.physmem_1.actEnergy 4095910980 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 2177024520 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 4502441160 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 3963024000 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 30680370240.000008 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 42163353720 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1422051360 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 64060335210 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 38109219360 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 11285470021935 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 11476656465255 # Total energy per rank (pJ)
> system.physmem_1.averagePower 242.420579 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 47245728134436 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 2323672783 # Time in different power states
> system.physmem_1.memoryStateTime::REF 13022950000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 47006002235750 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 99242546502 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 80848444531 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 140483404434 # Time in different power states
> system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
359,361c359,361
< system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
---
> system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
368,372c368,372
< system.cpu0.branchPred.lookups 139151101 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 91634411 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 6732234 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 97916993 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 61670085 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 135771616 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 86347947 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 6838936 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 91129477 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 54316721 # Number of BTB hits
374,380c374,380
< system.cpu0.branchPred.BTBHitPct 62.982005 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 19220371 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 194045 # Number of incorrect RAS predictions.
< system.cpu0.branchPred.indirectLookups 4187621 # Number of indirect predictor lookups.
< system.cpu0.branchPred.indirectHits 2676103 # Number of indirect target hits.
< system.cpu0.branchPred.indirectMisses 1511518 # Number of indirect misses.
< system.cpu0.branchPredindirectMispredicted 384250 # Number of mispredicted indirect branches.
---
> system.cpu0.branchPred.BTBHitPct 59.603899 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 20002366 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 187416 # Number of incorrect RAS predictions.
> system.cpu0.branchPred.indirectLookups 4394152 # Number of indirect predictor lookups.
> system.cpu0.branchPred.indirectHits 2878401 # Number of indirect target hits.
> system.cpu0.branchPred.indirectMisses 1515751 # Number of indirect misses.
> system.cpu0.branchPredindirectMispredicted 382217 # Number of mispredicted indirect branches.
382c382
< system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
---
> system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
412,466c412,465
< system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.cpu0.dtb.walker.walks 608743 # Table walker walks requested
< system.cpu0.dtb.walker.walksLong 608743 # Table walker walks initiated with long descriptors
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13705 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 96942 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walksSquashedBefore 292908 # Table walks squashed before starting
< system.cpu0.dtb.walker.walkWaitTime::samples 315835 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::mean 2627.591939 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::stdev 15089.582893 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0-65535 312900 99.07% 99.07% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::65536-131071 2131 0.67% 99.75% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::131072-196607 548 0.17% 99.92% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::196608-262143 139 0.04% 99.96% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::262144-327679 36 0.01% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::327680-393215 50 0.02% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::393216-458751 5 0.00% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::589824-655359 23 0.01% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::total 315835 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkCompletionTime::samples 324732 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::mean 22165.202382 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::gmean 18853.631715 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::stdev 18861.810606 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::0-65535 320100 98.57% 98.57% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::65536-131071 3009 0.93% 99.50% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::131072-196607 694 0.21% 99.71% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::196608-262143 681 0.21% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::262144-327679 132 0.04% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::327680-393215 68 0.02% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::393216-458751 19 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::458752-524287 13 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::total 324732 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walksPending::samples 522550016344 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::mean 0.577122 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::stdev 0.559179 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::0-1 521035310844 99.71% 99.71% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::2-3 819753000 0.16% 99.87% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::4-5 323762500 0.06% 99.93% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::6-7 144297000 0.03% 99.96% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::8-9 115791000 0.02% 99.98% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::10-11 61783500 0.01% 99.99% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::12-13 19805000 0.00% 99.99% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::14-15 28515500 0.01% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::16-17 990500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::18-19 7500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::total 522550016344 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walkPageSizes::4K 96943 87.61% 87.61% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::2M 13705 12.39% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 110648 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 608743 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.cpu0.dtb.walker.walks 656993 # Table walker walks requested
> system.cpu0.dtb.walker.walksLong 656993 # Table walker walks initiated with long descriptors
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 15295 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 109934 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walksSquashedBefore 315620 # Table walks squashed before starting
> system.cpu0.dtb.walker.walkWaitTime::samples 341373 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::mean 2464.513889 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::stdev 14057.964276 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0-65535 338378 99.12% 99.12% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::65536-131071 2127 0.62% 99.75% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::131072-196607 591 0.17% 99.92% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::196608-262143 168 0.05% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::262144-327679 44 0.01% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::327680-393215 50 0.01% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::393216-458751 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::589824-655359 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::total 341373 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkCompletionTime::samples 358442 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::mean 21996.103972 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::gmean 18865.832829 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::stdev 18729.819330 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::0-65535 353579 98.64% 98.64% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::65536-131071 3217 0.90% 99.54% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::131072-196607 596 0.17% 99.71% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::196608-262143 697 0.19% 99.90% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::262144-327679 228 0.06% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::327680-393215 58 0.02% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::393216-458751 45 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::589824-655359 12 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::total 358442 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walksPending::samples 470936013252 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::mean 0.670912 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::stdev 0.545830 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::0-1 469324214752 99.66% 99.66% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::2-3 904884000 0.19% 99.85% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::4-5 330855500 0.07% 99.92% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::6-7 151555000 0.03% 99.95% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::8-9 116006500 0.02% 99.98% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::10-11 57420000 0.01% 99.99% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::12-13 24613500 0.01% 99.99% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::14-15 25389500 0.01% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::16-17 1013500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::18-19 61000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::total 470936013252 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walkPageSizes::4K 109934 87.79% 87.79% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::2M 15295 12.21% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 125229 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 656993 # Table walker requests started/completed, data/inst
468,469c467,468
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 608743 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 110648 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 656993 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 125229 # Table walker requests started/completed, data/inst
471,472c470,471
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 110648 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 719391 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 125229 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 782222 # Table walker requests started/completed, data/inst
475,479c474,478
< system.cpu0.dtb.read_hits 101564011 # DTB read hits
< system.cpu0.dtb.read_misses 439385 # DTB read misses
< system.cpu0.dtb.write_hits 82403711 # DTB write hits
< system.cpu0.dtb.write_misses 169358 # DTB write misses
< system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
---
> system.cpu0.dtb.read_hits 107772870 # DTB read hits
> system.cpu0.dtb.read_misses 484010 # DTB read misses
> system.cpu0.dtb.write_hits 87417439 # DTB write hits
> system.cpu0.dtb.write_misses 172983 # DTB write misses
> system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
481,485c480,484
< system.cpu0.dtb.flush_tlb_mva_asid 44658 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
< system.cpu0.dtb.flush_entries 43119 # Number of entries that have been flushed from TLB
< system.cpu0.dtb.align_faults 431 # Number of TLB faults due to alignment restrictions
< system.cpu0.dtb.prefetch_faults 7683 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.dtb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID
> system.cpu0.dtb.flush_entries 44511 # Number of entries that have been flushed from TLB
> system.cpu0.dtb.align_faults 282 # Number of TLB faults due to alignment restrictions
> system.cpu0.dtb.prefetch_faults 7018 # Number of TLB faults due to prefetch
487,489c486,488
< system.cpu0.dtb.perms_faults 39881 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 102003396 # DTB read accesses
< system.cpu0.dtb.write_accesses 82573069 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 39566 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 108256880 # DTB read accesses
> system.cpu0.dtb.write_accesses 87590422 # DTB write accesses
491,494c490,493
< system.cpu0.dtb.hits 183967722 # DTB hits
< system.cpu0.dtb.misses 608743 # DTB misses
< system.cpu0.dtb.accesses 184576465 # DTB accesses
< system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
---
> system.cpu0.dtb.hits 195190309 # DTB hits
> system.cpu0.dtb.misses 656993 # DTB misses
> system.cpu0.dtb.accesses 195847302 # DTB accesses
> system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
524,571c523,567
< system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.cpu0.itb.walker.walks 85247 # Table walker walks requested
< system.cpu0.itb.walker.walksLong 85247 # Table walker walks initiated with long descriptors
< system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1031 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58619 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walksSquashedBefore 10594 # Table walks squashed before starting
< system.cpu0.itb.walker.walkWaitTime::samples 74653 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::mean 1640.215397 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::stdev 15358.310447 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::0-65535 74120 99.29% 99.29% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::65536-131071 439 0.59% 99.87% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::131072-196607 37 0.05% 99.92% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::196608-262143 19 0.03% 99.95% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::262144-327679 10 0.01% 99.96% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::327680-393215 2 0.00% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::458752-524287 1 0.00% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::524288-589823 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::589824-655359 19 0.03% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::total 74653 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkCompletionTime::samples 70244 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::mean 27495.914242 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::gmean 23588.322709 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::stdev 27529.617952 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::0-65535 67750 96.45% 96.45% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::65536-131071 1764 2.51% 98.96% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::131072-196607 417 0.59% 99.55% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::196608-262143 170 0.24% 99.80% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::262144-327679 48 0.07% 99.86% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::327680-393215 42 0.06% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::393216-458751 15 0.02% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::589824-655359 26 0.04% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::total 70244 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walksPending::samples 419443065740 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::mean 0.871284 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::stdev 0.335229 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::0 54034549916 12.88% 12.88% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::1 365365302324 87.11% 99.99% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::2 40992500 0.01% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::3 2004000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::4 217000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::total 419443065740 # Table walker pending requests distribution
< system.cpu0.itb.walker.walkPageSizes::4K 58619 98.27% 98.27% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::2M 1031 1.73% 100.00% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::total 59650 # Table walker page sizes translated
---
> system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.cpu0.itb.walker.walks 88518 # Table walker walks requested
> system.cpu0.itb.walker.walksLong 88518 # Table walker walks initiated with long descriptors
> system.cpu0.itb.walker.walksLongTerminationLevel::Level2 982 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walksLongTerminationLevel::Level3 60760 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walksSquashedBefore 10909 # Table walks squashed before starting
> system.cpu0.itb.walker.walkWaitTime::samples 77609 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::mean 1509.006687 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::stdev 11301.495781 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::0-65535 77034 99.26% 99.26% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::65536-131071 519 0.67% 99.93% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::131072-196607 33 0.04% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::196608-262143 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::262144-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::327680-393215 8 0.01% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::total 77609 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkCompletionTime::samples 72651 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::mean 27149.240891 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::gmean 23393.498423 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::stdev 24986.363412 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::0-65535 70103 96.49% 96.49% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::65536-131071 1723 2.37% 98.86% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::131072-196607 517 0.71% 99.58% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::196608-262143 199 0.27% 99.85% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::262144-327679 51 0.07% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::327680-393215 35 0.05% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::524288-589823 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::589824-655359 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::total 72651 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walksPending::samples 367854316648 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::mean 0.912736 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::stdev 0.282646 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::0 32141827252 8.74% 8.74% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::1 335673383896 91.25% 99.99% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::2 36841000 0.01% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::3 2085000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::4 179500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::total 367854316648 # Table walker pending requests distribution
> system.cpu0.itb.walker.walkPageSizes::4K 60760 98.41% 98.41% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::2M 982 1.59% 100.00% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::total 61742 # Table walker page sizes translated
573,574c569,570
< system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85247 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85247 # Table walker requests started/completed, data/inst
---
> system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 88518 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Requested::total 88518 # Table walker requests started/completed, data/inst
576,580c572,576
< system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59650 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59650 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin::total 144897 # Table walker requests started/completed, data/inst
< system.cpu0.itb.inst_hits 219469803 # ITB inst hits
< system.cpu0.itb.inst_misses 85247 # ITB inst misses
---
> system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61742 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61742 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin::total 150260 # Table walker requests started/completed, data/inst
> system.cpu0.itb.inst_hits 209275517 # ITB inst hits
> system.cpu0.itb.inst_misses 88518 # ITB inst misses
585c581
< system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
---
> system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
587,589c583,585
< system.cpu0.itb.flush_tlb_mva_asid 44658 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
< system.cpu0.itb.flush_entries 31398 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.itb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID
> system.cpu0.itb.flush_entries 31869 # Number of entries that have been flushed from TLB
593c589
< system.cpu0.itb.perms_faults 204530 # Number of TLB faults due to permissions restrictions
---
> system.cpu0.itb.perms_faults 214657 # Number of TLB faults due to permissions restrictions
596,617c592,615
< system.cpu0.itb.inst_accesses 219555050 # ITB inst accesses
< system.cpu0.itb.hits 219469803 # DTB hits
< system.cpu0.itb.misses 85247 # DTB misses
< system.cpu0.itb.accesses 219555050 # DTB accesses
< system.cpu0.numPwrStateTransitions 27212 # Number of power state transitions
< system.cpu0.pwrStateClkGateDist::samples 13606 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::mean 3453780783.684036 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::stdev 93985708249.621262 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::underflows 3589 26.38% 26.38% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::1000-5e+10 9986 73.39% 99.77% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::5e+10-1e+11 12 0.09% 99.86% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.88% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::overflows 13 0.10% 100.00% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::max_value 6914083139000 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::total 13606 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateResidencyTicks::ON 392799112195 # Cumulative time (in ticks) in various power states
< system.cpu0.pwrStateResidencyTicks::CLK_GATED 46992141342805 # Cumulative time (in ticks) in various power states
< system.cpu0.numCycles 785608211 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 209364035 # ITB inst accesses
> system.cpu0.itb.hits 209275517 # DTB hits
> system.cpu0.itb.misses 88518 # DTB misses
> system.cpu0.itb.accesses 209364035 # DTB accesses
> system.cpu0.numPwrStateTransitions 11060 # Number of power state transitions
> system.cpu0.pwrStateClkGateDist::samples 5530 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::mean 8500198165.069259 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::stdev 152149510782.295166 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::underflows 4198 75.91% 75.91% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::1000-5e+10 1307 23.63% 99.55% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::5e+10-1e+11 6 0.11% 99.66% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.67% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.71% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.76% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.78% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::overflows 12 0.22% 100.00% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::max_value 6914082541000 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::total 5530 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateResidencyTicks::ON 335827401167 # Cumulative time (in ticks) in various power states
> system.cpu0.pwrStateResidencyTicks::CLK_GATED 47006095852833 # Cumulative time (in ticks) in various power states
> system.cpu0.numCycles 671656145 # number of cpu cycles simulated
620,636c618,634
< system.cpu0.fetch.icacheStallCycles 89154333 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 616347679 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 139151101 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 83566559 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 651741352 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu0.fetch.SquashCycles 14592652 # Number of cycles fetch has spent squashing
< system.cpu0.fetch.TlbCycles 2033431 # Number of cycles fetch has spent waiting for tlb
< system.cpu0.fetch.MiscStallCycles 298378 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu0.fetch.PendingTrapStallCycles 6056906 # Number of stall cycles due to pending traps
< system.cpu0.fetch.PendingQuiesceStallCycles 755254 # Number of stall cycles due to pending quiesce instructions
< system.cpu0.fetch.IcacheWaitRetryStallCycles 834704 # Number of stall cycles due to full MSHR
< system.cpu0.fetch.CacheLines 219265865 # Number of cache lines fetched
< system.cpu0.fetch.IcacheSquashes 1675112 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.ItlbSquashes 28029 # Number of outstanding ITLB misses that were squashed
< system.cpu0.fetch.rateDist::samples 758170684 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 0.951385 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 1.212910 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.icacheStallCycles 89746186 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 605326172 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 135771616 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 77197488 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 539879458 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu0.fetch.SquashCycles 14767666 # Number of cycles fetch has spent squashing
> system.cpu0.fetch.TlbCycles 2125862 # Number of cycles fetch has spent waiting for tlb
> system.cpu0.fetch.MiscStallCycles 314132 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu0.fetch.PendingTrapStallCycles 6298223 # Number of stall cycles due to pending traps
> system.cpu0.fetch.PendingQuiesceStallCycles 772099 # Number of stall cycles due to pending quiesce instructions
> system.cpu0.fetch.IcacheWaitRetryStallCycles 851881 # Number of stall cycles due to full MSHR
> system.cpu0.fetch.CacheLines 209041727 # Number of cache lines fetched
> system.cpu0.fetch.IcacheSquashes 1674502 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.ItlbSquashes 29298 # Number of outstanding ITLB misses that were squashed
> system.cpu0.fetch.rateDist::samples 647371674 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 1.105525 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 1.248840 # Number of instructions fetched each cycle (Total)
638,641c636,639
< system.cpu0.fetch.rateDist::0 412487393 54.41% 54.41% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 134584185 17.75% 72.16% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 46569297 6.14% 78.30% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 164529809 21.70% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 308576951 47.67% 47.67% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 127594651 19.71% 67.38% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 45508982 7.03% 74.41% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 165691090 25.59% 100.00% # Number of instructions fetched each cycle (Total)
645,692c643,690
< system.cpu0.fetch.rateDist::total 758170684 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.177125 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 0.784548 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 107249627 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 379334150 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 227390625 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 38947644 # Number of cycles decode is unblocking
< system.cpu0.decode.SquashCycles 5248638 # Number of cycles decode is squashing
< system.cpu0.decode.BranchResolved 19981467 # Number of times decode resolved a branch
< system.cpu0.decode.BranchMispred 2087891 # Number of times decode detected a branch misprediction
< system.cpu0.decode.DecodedInsts 636989334 # Number of instructions handled by decode
< system.cpu0.decode.SquashedInsts 23191131 # Number of squashed instructions handled by decode
< system.cpu0.rename.SquashCycles 5248638 # Number of cycles rename is squashing
< system.cpu0.rename.IdleCycles 143394034 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 56142021 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 253850770 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 229681319 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 69853902 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 619319594 # Number of instructions processed by rename
< system.cpu0.rename.SquashedInsts 6178554 # Number of squashed instructions processed by rename
< system.cpu0.rename.ROBFullEvents 10862186 # Number of times rename has blocked due to ROB full
< system.cpu0.rename.IQFullEvents 388792 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LQFullEvents 930621 # Number of times rename has blocked due to LQ full
< system.cpu0.rename.SQFullEvents 33162716 # Number of times rename has blocked due to SQ full
< system.cpu0.rename.FullRegisterEvents 11693 # Number of times there has been no free registers
< system.cpu0.rename.RenamedOperands 591176589 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 957415604 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 731049781 # Number of integer rename lookups
< system.cpu0.rename.fp_rename_lookups 649204 # Number of floating rename lookups
< system.cpu0.rename.CommittedMaps 532948721 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 58227868 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 16256269 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 14199870 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 78279720 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 101593087 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 85666218 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 9630459 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 8075180 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 596126359 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu0.iq.iqNonSpecInstsAdded 16460453 # Number of non-speculative instructions added to the IQ
< system.cpu0.iq.iqInstsIssued 601474893 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 2699291 # Number of squashed instructions issued
< system.cpu0.iq.iqSquashedInstsExamined 54684336 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 35421563 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu0.iq.iqSquashedNonSpecRemoved 283328 # Number of squashed non-spec instructions that were removed
< system.cpu0.iq.issued_per_cycle::samples 758170684 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 0.793324 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.057959 # Number of insts issued each cycle
---
> system.cpu0.fetch.rateDist::total 647371674 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.202145 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 0.901244 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 102332613 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 273941666 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 237936691 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 27831297 # Number of cycles decode is unblocking
> system.cpu0.decode.SquashCycles 5329407 # Number of cycles decode is squashing
> system.cpu0.decode.BranchResolved 50359670 # Number of times decode resolved a branch
> system.cpu0.decode.BranchMispred 2095113 # Number of times decode detected a branch misprediction
> system.cpu0.decode.DecodedInsts 630187004 # Number of instructions handled by decode
> system.cpu0.decode.SquashedInsts 23557218 # Number of squashed instructions handled by decode
> system.cpu0.rename.SquashCycles 5329407 # Number of cycles rename is squashing
> system.cpu0.rename.IdleCycles 133079950 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 61214716 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 153180346 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 234286149 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 60281106 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 612391061 # Number of instructions processed by rename
> system.cpu0.rename.SquashedInsts 6345537 # Number of squashed instructions processed by rename
> system.cpu0.rename.ROBFullEvents 11623022 # Number of times rename has blocked due to ROB full
> system.cpu0.rename.IQFullEvents 442390 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LQFullEvents 950471 # Number of times rename has blocked due to LQ full
> system.cpu0.rename.SQFullEvents 35105207 # Number of times rename has blocked due to SQ full
> system.cpu0.rename.FullRegisterEvents 13004 # Number of times there has been no free registers
> system.cpu0.rename.RenamedOperands 561787552 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 866106072 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 720689595 # Number of integer rename lookups
> system.cpu0.rename.fp_rename_lookups 706575 # Number of floating rename lookups
> system.cpu0.rename.CommittedMaps 502207885 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 59579653 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 6816633 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 4684361 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 58564314 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 107690406 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 90791382 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 10221267 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 8541253 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 598417989 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu0.iq.iqNonSpecInstsAdded 7027379 # Number of non-speculative instructions added to the IQ
> system.cpu0.iq.iqInstsIssued 594218555 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 2775784 # Number of squashed instructions issued
> system.cpu0.iq.iqSquashedInstsExamined 55969109 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 36418491 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu0.iq.iqSquashedNonSpecRemoved 281604 # Number of squashed non-spec instructions that were removed
> system.cpu0.iq.issued_per_cycle::samples 647371674 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 0.917894 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.123620 # Number of insts issued each cycle
694,700c692,698
< system.cpu0.iq.issued_per_cycle::0 428799597 56.56% 56.56% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 139371286 18.38% 74.94% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 115828942 15.28% 90.22% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 66243104 8.74% 98.95% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 7922364 1.04% 100.00% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 5391 0.00% 100.00% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 341377364 52.73% 52.73% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 105270736 16.26% 68.99% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 121758490 18.81% 87.80% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 70435170 10.88% 98.68% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 8524242 1.32% 100.00% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 5671 0.00% 100.00% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::6 1 0.00% 100.00% # Number of insts issued each cycle
705,706c703,704
< system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::total 758170684 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::total 647371674 # Number of insts issued each cycle
708,742c706,740
< system.cpu0.iq.fu_full::IntAlu 61955212 45.30% 45.30% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 62513 0.05% 45.34% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 16729 0.01% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMisc 21 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.36% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 36421436 26.63% 71.99% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 37996782 27.78% 99.77% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMemRead 31053 0.02% 99.79% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMemWrite 287360 0.21% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 65687551 45.22% 45.22% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 64582 0.04% 45.27% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 15638 0.01% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMisc 12 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.28% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 38738584 26.67% 71.95% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 40389693 27.81% 99.76% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMemRead 34528 0.02% 99.78% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMemWrite 315988 0.22% 100.00% # attempts to use FU when none available
745,780c743,778
< system.cpu0.iq.FU_type_0::No_OpClass 30 0.00% 0.00% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntAlu 411361741 68.39% 68.39% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 1567778 0.26% 68.65% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntDiv 78948 0.01% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatAdd 15 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMisc 39915 0.01% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.67% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemRead 104723474 17.41% 86.08% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 83352955 13.86% 99.94% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMemRead 49350 0.01% 99.95% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMemWrite 300687 0.05% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::No_OpClass 70 0.00% 0.00% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntAlu 392733469 66.09% 66.09% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 1547002 0.26% 66.35% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntDiv 82083 0.01% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatAdd 53 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCmp 15 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCvt 25 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMisc 42153 0.01% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.37% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemRead 111068257 18.69% 85.07% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 88363067 14.87% 99.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMemRead 53874 0.01% 99.94% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMemWrite 328485 0.06% 100.00% # Type of FU issued
783,795c781,793
< system.cpu0.iq.FU_type_0::total 601474893 # Type of FU issued
< system.cpu0.iq.rate 0.765617 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 136771106 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.227393 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 2099488112 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 667007258 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 583889559 # Number of integer instruction queue wakeup accesses
< system.cpu0.iq.fp_inst_queue_reads 1102755 # Number of floating instruction queue reads
< system.cpu0.iq.fp_inst_queue_writes 413748 # Number of floating instruction queue writes
< system.cpu0.iq.fp_inst_queue_wakeup_accesses 385073 # Number of floating instruction queue wakeup accesses
< system.cpu0.iq.int_alu_accesses 737537568 # Number of integer alu accesses
< system.cpu0.iq.fp_alu_accesses 708401 # Number of floating point alu accesses
< system.cpu0.iew.lsq.thread0.forwLoads 2768605 # Number of loads that had data forwarded from stores
---
> system.cpu0.iq.FU_type_0::total 594218555 # Type of FU issued
> system.cpu0.iq.rate 0.884706 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 145246576 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.244433 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 1982627676 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 661129837 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 575942513 # Number of integer instruction queue wakeup accesses
> system.cpu0.iq.fp_inst_queue_reads 1203467 # Number of floating instruction queue reads
> system.cpu0.iq.fp_inst_queue_writes 445947 # Number of floating instruction queue writes
> system.cpu0.iq.fp_inst_queue_wakeup_accesses 420205 # Number of floating instruction queue wakeup accesses
> system.cpu0.iq.int_alu_accesses 738689926 # Number of integer alu accesses
> system.cpu0.iq.fp_alu_accesses 775135 # Number of floating point alu accesses
> system.cpu0.iew.lsq.thread0.forwLoads 2992085 # Number of loads that had data forwarded from stores
797,800c795,798
< system.cpu0.iew.lsq.thread0.squashedLoads 12684669 # Number of loads squashed
< system.cpu0.iew.lsq.thread0.ignoredResponses 17846 # Number of memory responses ignored because the instruction is squashed
< system.cpu0.iew.lsq.thread0.memOrderViolation 151274 # Number of memory ordering violations
< system.cpu0.iew.lsq.thread0.squashedStores 5522197 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 13179956 # Number of loads squashed
> system.cpu0.iew.lsq.thread0.ignoredResponses 18072 # Number of memory responses ignored because the instruction is squashed
> system.cpu0.iew.lsq.thread0.memOrderViolation 162311 # Number of memory ordering violations
> system.cpu0.iew.lsq.thread0.squashedStores 5715015 # Number of stores squashed
803,804c801,802
< system.cpu0.iew.lsq.thread0.rescheduledLoads 2796342 # Number of loads that were rescheduled
< system.cpu0.iew.lsq.thread0.cacheBlocked 4797484 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.rescheduledLoads 3005258 # Number of loads that were rescheduled
> system.cpu0.iew.lsq.thread0.cacheBlocked 4976098 # Number of times an access to memory failed due to the cache being blocked
806,809c804,807
< system.cpu0.iew.iewSquashCycles 5248638 # Number of cycles IEW is squashing
< system.cpu0.iew.iewBlockCycles 8055865 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 1895421 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 612718172 # Number of instructions dispatched to IQ
---
> system.cpu0.iew.iewSquashCycles 5329407 # Number of cycles IEW is squashing
> system.cpu0.iew.iewBlockCycles 8694006 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 1907824 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 605581185 # Number of instructions dispatched to IQ
811,822c809,820
< system.cpu0.iew.iewDispLoadInsts 101593087 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 85666218 # Number of dispatched store instructions
< system.cpu0.iew.iewDispNonSpecInsts 13907446 # Number of dispatched non-speculative instructions
< system.cpu0.iew.iewIQFullEvents 58112 # Number of times the IQ has become full, causing a stall
< system.cpu0.iew.iewLSQFullEvents 1764578 # Number of times the LSQ has become full, causing a stall
< system.cpu0.iew.memOrderViolationEvents 151274 # Number of memory order violations
< system.cpu0.iew.predictedTakenIncorrect 1949210 # Number of branches that were predicted taken incorrectly
< system.cpu0.iew.predictedNotTakenIncorrect 3085558 # Number of branches that were predicted not taken incorrectly
< system.cpu0.iew.branchMispredicts 5034768 # Number of branch mispredicts detected at execute
< system.cpu0.iew.iewExecutedInsts 593488019 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 101560351 # Number of load instructions executed
< system.cpu0.iew.iewExecSquashedInsts 7385409 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewDispLoadInsts 107690406 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 90791382 # Number of dispatched store instructions
> system.cpu0.iew.iewDispNonSpecInsts 4430701 # Number of dispatched non-speculative instructions
> system.cpu0.iew.iewIQFullEvents 69738 # Number of times the IQ has become full, causing a stall
> system.cpu0.iew.iewLSQFullEvents 1753830 # Number of times the LSQ has become full, causing a stall
> system.cpu0.iew.memOrderViolationEvents 162311 # Number of memory order violations
> system.cpu0.iew.predictedTakenIncorrect 2018069 # Number of branches that were predicted taken incorrectly
> system.cpu0.iew.predictedNotTakenIncorrect 3124602 # Number of branches that were predicted not taken incorrectly
> system.cpu0.iew.branchMispredicts 5142671 # Number of branch mispredicts detected at execute
> system.cpu0.iew.iewExecutedInsts 586012257 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 107766715 # Number of load instructions executed
> system.cpu0.iew.iewExecSquashedInsts 7557397 # Number of squashed instructions skipped in execute
824,840c822,838
< system.cpu0.iew.exec_nop 131360 # number of nop insts executed
< system.cpu0.iew.exec_refs 183963466 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 111638269 # Number of branches executed
< system.cpu0.iew.exec_stores 82403115 # Number of stores executed
< system.cpu0.iew.exec_rate 0.755450 # Inst execution rate
< system.cpu0.iew.wb_sent 585082868 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 584274632 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 284506732 # num instructions producing a value
< system.cpu0.iew.wb_consumers 466304278 # num instructions consuming a value
< system.cpu0.iew.wb_rate 0.743723 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.610131 # average fanout of values written-back
< system.cpu0.commit.commitSquashedInsts 47796807 # The number of squashed insts skipped by commit
< system.cpu0.commit.commitNonSpecStalls 16177125 # The number of times commit has been forced to stall to communicate backwards
< system.cpu0.commit.branchMispredicts 4684546 # The number of times a branch was mispredicted
< system.cpu0.commit.committed_per_cycle::samples 749065087 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 0.744798 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 1.551758 # Number of insts commited each cycle
---
> system.cpu0.iew.exec_nop 135817 # number of nop insts executed
> system.cpu0.iew.exec_refs 195183772 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 107644173 # Number of branches executed
> system.cpu0.iew.exec_stores 87417057 # Number of stores executed
> system.cpu0.iew.exec_rate 0.872488 # Inst execution rate
> system.cpu0.iew.wb_sent 577164047 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 576362718 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 283557258 # num instructions producing a value
> system.cpu0.iew.wb_consumers 461921851 # num instructions consuming a value
> system.cpu0.iew.wb_rate 0.858122 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.613864 # average fanout of values written-back
> system.cpu0.commit.commitSquashedInsts 48922079 # The number of squashed insts skipped by commit
> system.cpu0.commit.commitNonSpecStalls 6745775 # The number of times commit has been forced to stall to communicate backwards
> system.cpu0.commit.branchMispredicts 4784510 # The number of times a branch was mispredicted
> system.cpu0.commit.committed_per_cycle::samples 638061728 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 0.861165 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 1.699392 # Number of insts commited each cycle
842,850c840,848
< system.cpu0.commit.committed_per_cycle::0 504468440 67.35% 67.35% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 127495809 17.02% 84.37% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 53846196 7.19% 91.56% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 17894232 2.39% 93.94% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 12874355 1.72% 95.66% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 8922431 1.19% 96.85% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 5996417 0.80% 97.65% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 3594154 0.48% 98.13% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 13973053 1.87% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 421096864 66.00% 66.00% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 93116977 14.59% 80.59% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 56739989 8.89% 89.48% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 18882229 2.96% 92.44% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 13609968 2.13% 94.57% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 9457933 1.48% 96.06% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 6466471 1.01% 97.07% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 3826133 0.60% 97.67% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 14865164 2.33% 100.00% # Number of insts commited each cycle
854,856c852,854
< system.cpu0.commit.committed_per_cycle::total 749065087 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 475226157 # Number of instructions committed
< system.cpu0.commit.committedOps 557902476 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 638061728 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 461890383 # Number of instructions committed
> system.cpu0.commit.committedOps 549476248 # Number of ops (including micro ops) committed
858,864c856,862
< system.cpu0.commit.refs 169052439 # Number of memory references committed
< system.cpu0.commit.loads 88908418 # Number of loads committed
< system.cpu0.commit.membars 3969625 # Number of memory barriers committed
< system.cpu0.commit.branches 106090436 # Number of branches committed
< system.cpu0.commit.fp_insts 377224 # Number of committed floating point instructions.
< system.cpu0.commit.int_insts 511981133 # Number of committed integer instructions.
< system.cpu0.commit.function_calls 14308761 # Number of function calls committed.
---
> system.cpu0.commit.refs 179586814 # Number of memory references committed
> system.cpu0.commit.loads 94510447 # Number of loads committed
> system.cpu0.commit.membars 4189650 # Number of memory barriers committed
> system.cpu0.commit.branches 102007560 # Number of branches committed
> system.cpu0.commit.fp_insts 412941 # Number of committed floating point instructions.
> system.cpu0.commit.int_insts 511246578 # Number of committed integer instructions.
> system.cpu0.commit.function_calls 15004572 # Number of function calls committed.
866,900c864,898
< system.cpu0.commit.op_class_0::IntAlu 387443640 69.45% 69.45% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntMult 1310567 0.23% 69.68% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntDiv 61901 0.01% 69.69% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.69% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.69% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.69% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.69% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 69.69% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.69% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatMisc 33929 0.01% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.70% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemRead 88862033 15.93% 85.63% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemWrite 79847111 14.31% 99.94% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatMemRead 46385 0.01% 99.95% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatMemWrite 296910 0.05% 100.00% # Class of committed instruction
---
> system.cpu0.commit.op_class_0::IntAlu 368489017 67.06% 67.06% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntMult 1298564 0.24% 67.30% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntDiv 64848 0.01% 67.31% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatAdd 8 0.00% 67.31% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCmp 13 0.00% 67.31% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCvt 21 0.00% 67.31% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.31% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 67.31% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.31% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatMisc 36963 0.01% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.32% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemRead 94459041 17.19% 84.51% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemWrite 84751837 15.42% 99.93% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatMemRead 51406 0.01% 99.94% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatMemWrite 324530 0.06% 100.00% # Class of committed instruction
903,933c901,931
< system.cpu0.commit.op_class_0::total 557902476 # Class of committed instruction
< system.cpu0.commit.bw_lim_events 13973053 # number cycles where commit BW limit reached
< system.cpu0.rob.rob_reads 1336174255 # The number of ROB reads
< system.cpu0.rob.rob_writes 1220466867 # The number of ROB writes
< system.cpu0.timesIdled 1005352 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu0.idleCycles 27437527 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.quiesceCycles 93984272695 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.committedInsts 475226157 # Number of Instructions Simulated
< system.cpu0.committedOps 557902476 # Number of Ops (including micro ops) Simulated
< system.cpu0.cpi 1.653125 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 1.653125 # CPI: Total CPI of All Threads
< system.cpu0.ipc 0.604915 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 0.604915 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 700618930 # number of integer regfile reads
< system.cpu0.int_regfile_writes 416450651 # number of integer regfile writes
< system.cpu0.fp_regfile_reads 634669 # number of floating regfile reads
< system.cpu0.fp_regfile_writes 293776 # number of floating regfile writes
< system.cpu0.cc_regfile_reads 128889270 # number of cc regfile reads
< system.cpu0.cc_regfile_writes 129563151 # number of cc regfile writes
< system.cpu0.misc_regfile_reads 1347671553 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 16172806 # number of misc regfile writes
< system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.cpu0.dcache.tags.replacements 6286438 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 484.582319 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 156315528 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 6286950 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 24.863492 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 2049282000 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.582319 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946450 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.946450 # Average percentage of cache occupancy
---
> system.cpu0.commit.op_class_0::total 549476248 # Class of committed instruction
> system.cpu0.commit.bw_lim_events 14865164 # number cycles where commit BW limit reached
> system.cpu0.rob.rob_reads 1217272285 # The number of ROB reads
> system.cpu0.rob.rob_writes 1206069871 # The number of ROB writes
> system.cpu0.timesIdled 983506 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu0.idleCycles 24284471 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.quiesceCycles 94012190405 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.committedInsts 461890383 # Number of Instructions Simulated
> system.cpu0.committedOps 549476248 # Number of Ops (including micro ops) Simulated
> system.cpu0.cpi 1.454146 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 1.454146 # CPI: Total CPI of All Threads
> system.cpu0.ipc 0.687689 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 0.687689 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 689648120 # number of integer regfile reads
> system.cpu0.int_regfile_writes 419367317 # number of integer regfile writes
> system.cpu0.fp_regfile_reads 692130 # number of floating regfile reads
> system.cpu0.fp_regfile_writes 320584 # number of floating regfile writes
> system.cpu0.cc_regfile_reads 105285978 # number of cc regfile reads
> system.cpu0.cc_regfile_writes 105978286 # number of cc regfile writes
> system.cpu0.misc_regfile_reads 1168751660 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 6863582 # number of misc regfile writes
> system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.cpu0.dcache.tags.replacements 6620968 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 481.361219 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 165967454 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 6621480 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 25.065009 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 204144000 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.361219 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.940159 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.940159 # Average percentage of cache occupancy
935,937c933,935
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id
---
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 433 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id
939,1031c937,1029
< system.cpu0.dcache.tags.tag_accesses 351060755 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 351060755 # Number of data accesses
< system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.cpu0.dcache.ReadReq_hits::cpu0.data 82089512 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 82089512 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 69232216 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 69232216 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209823 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 209823 # number of SoftPFReq hits
< system.cpu0.dcache.WriteLineReq_hits::cpu0.data 173405 # number of WriteLineReq hits
< system.cpu0.dcache.WriteLineReq_hits::total 173405 # number of WriteLineReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1868090 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 1868090 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1930069 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 1930069 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 151495133 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 151495133 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 151704956 # number of overall hits
< system.cpu0.dcache.overall_hits::total 151704956 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 7010414 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 7010414 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 7797174 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 7797174 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 751824 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 751824 # number of SoftPFReq misses
< system.cpu0.dcache.WriteLineReq_misses::cpu0.data 805427 # number of WriteLineReq misses
< system.cpu0.dcache.WriteLineReq_misses::total 805427 # number of WriteLineReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 284725 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 284725 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 186829 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 186829 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 15613015 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 15613015 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 16364839 # number of overall misses
< system.cpu0.dcache.overall_misses::total 16364839 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 112159926000 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 112159926000 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 158052575270 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 158052575270 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 29573159898 # number of WriteLineReq miss cycles
< system.cpu0.dcache.WriteLineReq_miss_latency::total 29573159898 # number of WriteLineReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4301491500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 4301491500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4484661500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 4484661500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2134500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2134500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 299785661168 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 299785661168 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 299785661168 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 299785661168 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 89099926 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 89099926 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 77029390 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 77029390 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 961647 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 961647 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 978832 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::total 978832 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2152815 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 2152815 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2116898 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 2116898 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 167108148 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 167108148 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 168069795 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 168069795 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.078680 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.078680 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.101223 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.101223 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781809 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781809 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.822845 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::total 0.822845 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.132257 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.132257 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.088256 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.088256 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.093431 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.093431 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097369 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.097369 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15999.044564 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 15999.044564 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20270.494832 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 20270.494832 # average WriteReq miss latency
< system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 36717.368424 # average WriteLineReq miss latency
< system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 36717.368424 # average WriteLineReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15107.530073 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15107.530073 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24004.097330 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24004.097330 # average StoreCondReq miss latency
---
> system.cpu0.dcache.tags.tag_accesses 372530825 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 372530825 # Number of data accesses
> system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.cpu0.dcache.ReadReq_hits::cpu0.data 87044023 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 87044023 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 73673205 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 73673205 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 219185 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 219185 # number of SoftPFReq hits
> system.cpu0.dcache.WriteLineReq_hits::cpu0.data 153997 # number of WriteLineReq hits
> system.cpu0.dcache.WriteLineReq_hits::total 153997 # number of WriteLineReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2008223 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 2008223 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2072988 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 2072988 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 160871225 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 160871225 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 161090410 # number of overall hits
> system.cpu0.dcache.overall_hits::total 161090410 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 7470146 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 7470146 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 8166848 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 8166848 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 789396 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 789396 # number of SoftPFReq misses
> system.cpu0.dcache.WriteLineReq_misses::cpu0.data 800299 # number of WriteLineReq misses
> system.cpu0.dcache.WriteLineReq_misses::total 800299 # number of WriteLineReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 307874 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 307874 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202740 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 202740 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 16437293 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 16437293 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 17226689 # number of overall misses
> system.cpu0.dcache.overall_misses::total 17226689 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 120830384000 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 120830384000 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 166078687815 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 166078687815 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 29848601951 # number of WriteLineReq miss cycles
> system.cpu0.dcache.WriteLineReq_miss_latency::total 29848601951 # number of WriteLineReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4689476000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 4689476000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4883927500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 4883927500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2141000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2141000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 316757673766 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 316757673766 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 316757673766 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 316757673766 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 94514169 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 94514169 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 81840053 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 81840053 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1008581 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 1008581 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 954296 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::total 954296 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2316097 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 2316097 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2275728 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 2275728 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 177308518 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 177308518 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 178317099 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 178317099 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.079037 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.079037 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.099790 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.099790 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.782680 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.782680 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.838628 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::total 0.838628 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.132928 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.132928 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089088 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089088 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092704 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.092704 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096607 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.096607 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16175.103405 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 16175.103405 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20335.714319 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 20335.714319 # average WriteReq miss latency
> system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 37296.812755 # average WriteLineReq miss latency
> system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 37296.812755 # average WriteLineReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15231.802621 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15231.802621 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24089.609845 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24089.609845 # average StoreCondReq miss latency
1034,1129c1032,1127
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19201.010258 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 19201.010258 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18318.888513 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 18318.888513 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 8999058 # number of cycles access was blocked
< system.cpu0.dcache.blocked_cycles::no_targets 24447381 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_mshrs 751224 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_targets 774000 # number of cycles access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11.979194 # average number of cycles each access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_targets 31.585764 # average number of cycles each access was blocked
< system.cpu0.dcache.writebacks::writebacks 6286527 # number of writebacks
< system.cpu0.dcache.writebacks::total 6286527 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3589298 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 3589298 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6265824 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 6265824 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4129 # number of WriteLineReq MSHR hits
< system.cpu0.dcache.WriteLineReq_mshr_hits::total 4129 # number of WriteLineReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 147493 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 147493 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 9859251 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 9859251 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 9859251 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 9859251 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3421116 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 3421116 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1531350 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 1531350 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 745052 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 745052 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 801298 # number of WriteLineReq MSHR misses
< system.cpu0.dcache.WriteLineReq_mshr_misses::total 801298 # number of WriteLineReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 137232 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 137232 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 186825 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 186825 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 5753764 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 5753764 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 6498816 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 6498816 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29615 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29615 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29691 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::total 29691 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 59306 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.overall_mshr_uncacheable_misses::total 59306 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 51678055000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 51678055000 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 34197879948 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 34197879948 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17704904500 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17704904500 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28602356899 # number of WriteLineReq MSHR miss cycles
< system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28602356899 # number of WriteLineReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1885182000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1885182000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4297888500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4297888500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2082500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2082500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 114478291847 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 114478291847 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 132183196347 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 132183196347 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5594868000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5594868000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5594868000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5594868000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.038396 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038396 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019880 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019880 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.774767 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.774767 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.818627 # mshr miss rate for WriteLineReq accesses
< system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.818627 # mshr miss rate for WriteLineReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063745 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063745 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.088254 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.088254 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034431 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.034431 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038667 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.038667 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15105.613198 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15105.613198 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22331.850947 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22331.850947 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23763.313836 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23763.313836 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 35695.030936 # average WriteLineReq mshr miss latency
< system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 35695.030936 # average WriteLineReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13737.189577 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13737.189577 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23004.889603 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23004.889603 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19270.671501 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 19270.671501 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18387.612023 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 18387.612023 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 9058407 # number of cycles access was blocked
> system.cpu0.dcache.blocked_cycles::no_targets 25757393 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_mshrs 741437 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_targets 811492 # number of cycles access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.217366 # average number of cycles each access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_targets 31.740785 # average number of cycles each access was blocked
> system.cpu0.dcache.writebacks::writebacks 6621095 # number of writebacks
> system.cpu0.dcache.writebacks::total 6621095 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3832878 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 3832878 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6557291 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 6557291 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4455 # number of WriteLineReq MSHR hits
> system.cpu0.dcache.WriteLineReq_mshr_hits::total 4455 # number of WriteLineReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 156975 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 156975 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 10394624 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 10394624 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 10394624 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 10394624 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3637268 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 3637268 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1609557 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 1609557 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 782554 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 782554 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 795844 # number of WriteLineReq MSHR misses
> system.cpu0.dcache.WriteLineReq_mshr_misses::total 795844 # number of WriteLineReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 150899 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 150899 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202732 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 202732 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 6042669 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 6042669 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 6825223 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 6825223 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15843 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15843 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17283 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 17283 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 33126 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 33126 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 55872486000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 55872486000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 35889720367 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 35889720367 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18736140000 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18736140000 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28877247951 # number of WriteLineReq MSHR miss cycles
> system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28877247951 # number of WriteLineReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2069296000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2069296000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4681247500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4681247500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2089000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2089000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 120639454318 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 120639454318 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 139375594318 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 139375594318 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2897214000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2897214000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2897214000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2897214000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.038484 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038484 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019667 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019667 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.775896 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.775896 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.833959 # mshr miss rate for WriteLineReq accesses
> system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.833959 # mshr miss rate for WriteLineReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065152 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065152 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089084 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089084 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034080 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.034080 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038276 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.038276 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15361.113341 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15361.113341 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22297.887162 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22297.887162 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23942.296634 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23942.296634 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 36285.060830 # average WriteLineReq mshr miss latency
> system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36285.060830 # average WriteLineReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13713.119371 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13713.119371 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23090.816941 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23090.816941 # average StoreCondReq mshr miss latency
1132,1149c1130,1147
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19896.243893 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19896.243893 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20339.581294 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20339.581294 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188920.074287 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188920.074287 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 94338.987624 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 94338.987624 # average overall mshr uncacheable latency
< system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.cpu0.icache.tags.replacements 5974428 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.960293 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 212911456 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 5974940 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 35.634074 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 13477910000 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960293 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999922 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.999922 # Average percentage of cache occupancy
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19964.597485 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19964.597485 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20420.665276 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20420.665276 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182870.289718 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182870.289718 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87460.423836 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87460.423836 # average overall mshr uncacheable latency
> system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.cpu0.icache.tags.replacements 6024041 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.980173 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 202652654 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 6024553 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 33.637791 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 11640760000 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.980173 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999961 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.999961 # Average percentage of cache occupancy
1151,1153c1149,1151
< system.cpu0.icache.tags.age_task_id_blocks_1024::0 293 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
1155,1247c1153,1245
< system.cpu0.icache.tags.tag_accesses 444450377 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 444450377 # Number of data accesses
< system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.cpu0.icache.ReadReq_hits::cpu0.inst 212911456 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 212911456 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 212911456 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 212911456 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 212911456 # number of overall hits
< system.cpu0.icache.overall_hits::total 212911456 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 6326229 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 6326229 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 6326229 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 6326229 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 6326229 # number of overall misses
< system.cpu0.icache.overall_misses::total 6326229 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 70930890398 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 70930890398 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 70930890398 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 70930890398 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 70930890398 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 70930890398 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 219237685 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 219237685 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 219237685 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 219237685 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 219237685 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 219237685 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028856 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.028856 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028856 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.028856 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028856 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.028856 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11212.191402 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 11212.191402 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11212.191402 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 11212.191402 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11212.191402 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 11212.191402 # average overall miss latency
< system.cpu0.icache.blocked_cycles::no_mshrs 10513720 # number of cycles access was blocked
< system.cpu0.icache.blocked_cycles::no_targets 1665 # number of cycles access was blocked
< system.cpu0.icache.blocked::no_mshrs 740505 # number of cycles access was blocked
< system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked
< system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.198041 # average number of cycles each access was blocked
< system.cpu0.icache.avg_blocked_cycles::no_targets 128.076923 # average number of cycles each access was blocked
< system.cpu0.icache.writebacks::writebacks 5974428 # number of writebacks
< system.cpu0.icache.writebacks::total 5974428 # number of writebacks
< system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 351221 # number of ReadReq MSHR hits
< system.cpu0.icache.ReadReq_mshr_hits::total 351221 # number of ReadReq MSHR hits
< system.cpu0.icache.demand_mshr_hits::cpu0.inst 351221 # number of demand (read+write) MSHR hits
< system.cpu0.icache.demand_mshr_hits::total 351221 # number of demand (read+write) MSHR hits
< system.cpu0.icache.overall_mshr_hits::cpu0.inst 351221 # number of overall MSHR hits
< system.cpu0.icache.overall_mshr_hits::total 351221 # number of overall MSHR hits
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5975008 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 5975008 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 5975008 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 5975008 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 5975008 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 5975008 # number of overall MSHR misses
< system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
< system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable
< system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
< system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 63931230447 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 63931230447 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 63931230447 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 63931230447 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 63931230447 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 63931230447 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2027158498 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2027158498 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2027158498 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::total 2027158498 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027254 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027254 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027254 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.027254 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027254 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.027254 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10699.773196 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10699.773196 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10699.773196 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 10699.773196 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10699.773196 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 10699.773196 # average overall mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856 # average ReadReq mshr uncacheable latency
< system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95203.047856 # average ReadReq mshr uncacheable latency
< system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856 # average overall mshr uncacheable latency
< system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95203.047856 # average overall mshr uncacheable latency
< system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.cpu0.l2cache.prefetcher.num_hwpf_issued 8714333 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.pfIdentified 8724211 # number of prefetch candidates identified
< system.cpu0.l2cache.prefetcher.pfBufferHit 8793 # number of redundant prefetches already in prefetch queue
---
> system.cpu0.icache.tags.tag_accesses 424090067 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 424090067 # Number of data accesses
> system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.cpu0.icache.ReadReq_hits::cpu0.inst 202652654 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 202652654 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 202652654 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 202652654 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 202652654 # number of overall hits
> system.cpu0.icache.overall_hits::total 202652654 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 6379961 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 6379961 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 6379961 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 6379961 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 6379961 # number of overall misses
> system.cpu0.icache.overall_misses::total 6379961 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 71606822648 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 71606822648 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 71606822648 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 71606822648 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 71606822648 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 71606822648 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 209032615 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 209032615 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 209032615 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 209032615 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 209032615 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 209032615 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.030521 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.030521 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.030521 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.030521 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.030521 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.030521 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11223.708522 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 11223.708522 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11223.708522 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 11223.708522 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11223.708522 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 11223.708522 # average overall miss latency
> system.cpu0.icache.blocked_cycles::no_mshrs 10553176 # number of cycles access was blocked
> system.cpu0.icache.blocked_cycles::no_targets 2682 # number of cycles access was blocked
> system.cpu0.icache.blocked::no_mshrs 731110 # number of cycles access was blocked
> system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked
> system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.434457 # average number of cycles each access was blocked
> system.cpu0.icache.avg_blocked_cycles::no_targets 243.818182 # average number of cycles each access was blocked
> system.cpu0.icache.writebacks::writebacks 6024041 # number of writebacks
> system.cpu0.icache.writebacks::total 6024041 # number of writebacks
> system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 355124 # number of ReadReq MSHR hits
> system.cpu0.icache.ReadReq_mshr_hits::total 355124 # number of ReadReq MSHR hits
> system.cpu0.icache.demand_mshr_hits::cpu0.inst 355124 # number of demand (read+write) MSHR hits
> system.cpu0.icache.demand_mshr_hits::total 355124 # number of demand (read+write) MSHR hits
> system.cpu0.icache.overall_mshr_hits::cpu0.inst 355124 # number of overall MSHR hits
> system.cpu0.icache.overall_mshr_hits::total 355124 # number of overall MSHR hits
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6024837 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 6024837 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 6024837 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 6024837 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 6024837 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 6024837 # number of overall MSHR misses
> system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 2093 # number of ReadReq MSHR uncacheable
> system.cpu0.icache.ReadReq_mshr_uncacheable::total 2093 # number of ReadReq MSHR uncacheable
> system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 2093 # number of overall MSHR uncacheable misses
> system.cpu0.icache.overall_mshr_uncacheable_misses::total 2093 # number of overall MSHR uncacheable misses
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64522792922 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 64522792922 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64522792922 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 64522792922 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64522792922 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 64522792922 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 201228498 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 201228498 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 201228498 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::total 201228498 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028822 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028822 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028822 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.028822 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028822 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.028822 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10709.466982 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10709.466982 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10709.466982 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 10709.466982 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10709.466982 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 10709.466982 # average overall mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 96143.572862 # average ReadReq mshr uncacheable latency
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 96143.572862 # average ReadReq mshr uncacheable latency
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 96143.572862 # average overall mshr uncacheable latency
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 96143.572862 # average overall mshr uncacheable latency
> system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.cpu0.l2cache.prefetcher.num_hwpf_issued 9077732 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.pfIdentified 9085476 # number of prefetch candidates identified
> system.cpu0.l2cache.prefetcher.pfBufferHit 6999 # number of redundant prefetches already in prefetch queue
1250,1265c1248,1263
< system.cpu0.l2cache.prefetcher.pfSpanPage 1114037 # number of prefetches not generated due to page crossing
< system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.cpu0.l2cache.tags.replacements 2711723 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 15840.616895 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 10811538 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 2727125 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 3.964445 # Average number of references to valid blocks.
< system.cpu0.l2cache.tags.warmup_cycle 2357982000 # Cycle when the warmup percentage was hit.
< system.cpu0.l2cache.tags.occ_blocks::writebacks 15519.308256 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 33.621063 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 19.237059 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000001 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 268.450517 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.947223 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002052 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001174 # Average percentage of cache occupancy
---
> system.cpu0.l2cache.prefetcher.pfSpanPage 1224644 # number of prefetches not generated due to page crossing
> system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.cpu0.l2cache.tags.replacements 2885626 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 15865.684381 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 11160732 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 2901096 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 3.847074 # Average number of references to valid blocks.
> system.cpu0.l2cache.tags.warmup_cycle 512573000 # Cycle when the warmup percentage was hit.
> system.cpu0.l2cache.tags.occ_blocks::writebacks 15504.354139 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 30.001688 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 17.597153 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000007 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 313.731394 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.946311 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001831 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001074 # Average percentage of cache occupancy
1267,1277c1265,1275
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.016385 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.966835 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 381 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14929 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 75 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 118 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 93 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 95 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 69 # Occupied blocks per task id
---
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.019149 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.968365 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 318 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 111 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15041 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 120 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 81 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 114 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 37 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 43 # Occupied blocks per task id
1279,1326c1277,1326
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 499 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1082 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5719 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5657 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1972 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.023254 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.911194 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 427199165 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 427199165 # Number of data accesses
< system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 602660 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 185799 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 788459 # number of ReadReq hits
< system.cpu0.l2cache.WritebackDirty_hits::writebacks 4096903 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackDirty_hits::total 4096903 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackClean_hits::writebacks 8161916 # number of WritebackClean hits
< system.cpu0.l2cache.WritebackClean_hits::total 8161916 # number of WritebackClean hits
< system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 32 # number of UpgradeReq hits
< system.cpu0.l2cache.UpgradeReq_hits::total 32 # number of UpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 986017 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 986017 # number of ReadExReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5386829 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::total 5386829 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3255809 # number of ReadSharedReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::total 3255809 # number of ReadSharedReq hits
< system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 183461 # number of InvalidateReq hits
< system.cpu0.l2cache.InvalidateReq_hits::total 183461 # number of InvalidateReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 602660 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 185799 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 5386829 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 4241826 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 10417114 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 602660 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 185799 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 5386829 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 4241826 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 10417114 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 25200 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 12620 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 37820 # number of ReadReq misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 257381 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 257381 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 186815 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 186815 # number of SCUpgradeReq misses
---
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2178 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7928 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2613 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2218 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.019409 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006775 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.918030 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 441303495 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 441303495 # Number of data accesses
> system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 661323 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 192664 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 853987 # number of ReadReq hits
> system.cpu0.l2cache.WritebackDirty_hits::writebacks 4337132 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackDirty_hits::total 4337132 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackClean_hits::writebacks 8306124 # number of WritebackClean hits
> system.cpu0.l2cache.WritebackClean_hits::total 8306124 # number of WritebackClean hits
> system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 35 # number of UpgradeReq hits
> system.cpu0.l2cache.UpgradeReq_hits::total 35 # number of UpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 3 # number of SCUpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 1063752 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 1063752 # number of ReadExReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5420251 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::total 5420251 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3451457 # number of ReadSharedReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::total 3451457 # number of ReadSharedReq hits
> system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 175529 # number of InvalidateReq hits
> system.cpu0.l2cache.InvalidateReq_hits::total 175529 # number of InvalidateReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 661323 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 192664 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 5420251 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 4515209 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 10789447 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 661323 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 192664 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 5420251 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 4515209 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 10789447 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 24436 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 12223 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 36659 # number of ReadReq misses
> system.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses
> system.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 266353 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 266353 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 202724 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 202724 # number of SCUpgradeReq misses
1329,1384c1329,1384
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 295278 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 295278 # number of ReadExReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 588130 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::total 588130 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1045192 # number of ReadSharedReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::total 1045192 # number of ReadSharedReq misses
< system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 617837 # number of InvalidateReq misses
< system.cpu0.l2cache.InvalidateReq_misses::total 617837 # number of InvalidateReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 25200 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 12620 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 588130 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 1340470 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 1966420 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 25200 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 12620 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 588130 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 1340470 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 1966420 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 896455000 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 597646500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 1494101500 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 982091000 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 982091000 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 295025000 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 295025000 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2003000 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2003000 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 18413910498 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 18413910498 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 22335302000 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::total 22335302000 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 43094995483 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::total 43094995483 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 882000 # number of InvalidateReq miss cycles
< system.cpu0.l2cache.InvalidateReq_miss_latency::total 882000 # number of InvalidateReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 896455000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 597646500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22335302000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 61508905981 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 85338309481 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 896455000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 597646500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22335302000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 61508905981 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 85338309481 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 627860 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 198419 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 826279 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4096903 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::total 4096903 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::writebacks 8161916 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::total 8161916 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 257413 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 257413 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 186820 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 186820 # number of SCUpgradeReq accesses(hits+misses)
---
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 288175 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 288175 # number of ReadExReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 604135 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::total 604135 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1115532 # number of ReadSharedReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::total 1115532 # number of ReadSharedReq misses
> system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 620315 # number of InvalidateReq misses
> system.cpu0.l2cache.InvalidateReq_misses::total 620315 # number of InvalidateReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 24436 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 12223 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 604135 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 1403707 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 2044501 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 24436 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 12223 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 604135 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 1403707 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 2044501 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 912274000 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 596923500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 1509197500 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 951661000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 951661000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 365355500 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 365355500 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2010499 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2010499 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 19225466000 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 19225466000 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 22664217000 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::total 22664217000 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 46789999492 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::total 46789999492 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 209000 # number of InvalidateReq miss cycles
> system.cpu0.l2cache.InvalidateReq_miss_latency::total 209000 # number of InvalidateReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 912274000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 596923500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22664217000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 66015465492 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 90188879992 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 912274000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 596923500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22664217000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 66015465492 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 90188879992 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 685759 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 204887 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 890646 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4337132 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::total 4337132 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::writebacks 8306125 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::total 8306125 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 266388 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 266388 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 202727 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 202727 # number of SCUpgradeReq accesses(hits+misses)
1387,1411c1387,1413
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1281295 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 1281295 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5974959 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::total 5974959 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4301001 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::total 4301001 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 801298 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::total 801298 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 627860 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 198419 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 5974959 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 5582296 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 12383534 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 627860 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 198419 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 5974959 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 5582296 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 12383534 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.040136 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.063603 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.045771 # miss rate for ReadReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999876 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999876 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999973 # miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999973 # miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1351927 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 1351927 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6024386 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::total 6024386 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4566989 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::total 4566989 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 795844 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::total 795844 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 685759 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 204887 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 6024386 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 5918916 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 12833948 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 685759 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 204887 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 6024386 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 5918916 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 12833948 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.035634 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.059657 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.041160 # miss rate for ReadReq accesses
> system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses
> system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999869 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999869 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999985 # miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999985 # miss rate for SCUpgradeReq accesses
1414,1459c1416,1461
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.230453 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.230453 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.098432 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.098432 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.243011 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.243011 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.771045 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.771045 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.040136 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.063603 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.098432 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.240129 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.158793 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.040136 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.063603 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.098432 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.240129 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.158793 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35573.611111 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 47357.091918 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 39505.592279 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3815.709007 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3815.709007 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1579.236143 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1579.236143 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 400600 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 400600 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 62361.268019 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 62361.268019 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37976.811249 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37976.811249 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41231.654551 # average ReadSharedReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41231.654551 # average ReadSharedReq miss latency
< system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 1.427561 # average InvalidateReq miss latency
< system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 1.427561 # average InvalidateReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35573.611111 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 47357.091918 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37976.811249 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45886.074273 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 43397.803867 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35573.611111 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 47357.091918 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37976.811249 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45886.074273 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 43397.803867 # average overall miss latency
< system.cpu0.l2cache.blocked_cycles::no_mshrs 1100 # number of cycles access was blocked
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.213159 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.213159 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.100282 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.100282 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.244260 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.244260 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.779443 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.779443 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.035634 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.059657 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.100282 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.237156 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.159304 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.035634 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.059657 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.100282 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.237156 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.159304 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 37333.196923 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 48836.087704 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 41168.539786 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3572.931411 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3572.931411 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1802.231112 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1802.231112 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 402099.800000 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 402099.800000 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66714.551922 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66714.551922 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37515.153070 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37515.153070 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41944.112309 # average ReadSharedReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41944.112309 # average ReadSharedReq miss latency
> system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 0.336926 # average InvalidateReq miss latency
> system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 0.336926 # average InvalidateReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 37333.196923 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 48836.087704 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37515.153070 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 47029.376851 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 44112.905786 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 37333.196923 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 48836.087704 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37515.153070 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 47029.376851 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 44112.905786 # average overall miss latency
> system.cpu0.l2cache.blocked_cycles::no_mshrs 1145 # number of cycles access was blocked
1461c1463
< system.cpu0.l2cache.blocked::no_mshrs 24 # number of cycles access was blocked
---
> system.cpu0.l2cache.blocked::no_mshrs 20 # number of cycles access was blocked
1463c1465
< system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 45.833333 # average number of cycles each access was blocked
---
> system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 57.250000 # average number of cycles each access was blocked
1465,1497c1467,1501
< system.cpu0.l2cache.unused_prefetches 49027 # number of HardPF blocks evicted w/o reference
< system.cpu0.l2cache.writebacks::writebacks 1747264 # number of writebacks
< system.cpu0.l2cache.writebacks::total 1747264 # number of writebacks
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 192 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 348 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_hits::total 540 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 21118 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 21118 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 4 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 5796 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 5796 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 13 # number of InvalidateReq MSHR hits
< system.cpu0.l2cache.InvalidateReq_mshr_hits::total 13 # number of InvalidateReq MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 192 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 348 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 26914 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 27458 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 192 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 348 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 26914 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 27458 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 25008 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 12272 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 37280 # number of ReadReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 914694 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 914694 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 257381 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 257381 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 186815 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 186815 # number of SCUpgradeReq MSHR misses
---
> system.cpu0.l2cache.unused_prefetches 50024 # number of HardPF blocks evicted w/o reference
> system.cpu0.l2cache.writebacks::writebacks 1896260 # number of writebacks
> system.cpu0.l2cache.writebacks::total 1896260 # number of writebacks
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 178 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 367 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::total 545 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 23776 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 23776 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 3 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 5616 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 5616 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 3 # number of InvalidateReq MSHR hits
> system.cpu0.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 178 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 367 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 29392 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 29940 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 178 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 367 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 29392 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 29940 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 24258 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 11856 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 36114 # number of ReadReq MSHR misses
> system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses
> system.cpu0.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 950932 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 950932 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 266353 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 266353 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 202724 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 202724 # number of SCUpgradeReq MSHR misses
1500,1565c1504,1571
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 274160 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 274160 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 588126 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 588126 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1039396 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1039396 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 617824 # number of InvalidateReq MSHR misses
< system.cpu0.l2cache.InvalidateReq_mshr_misses::total 617824 # number of InvalidateReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 25008 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 12272 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 588126 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1313556 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 1938962 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 25008 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 12272 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 588126 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1313556 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 914694 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 2853656 # number of overall MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29615 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 50908 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 29691 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 29691 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 59306 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 80599 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 742635500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 518427500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1261063000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 57180143123 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 57180143123 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4798228494 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4798228494 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2893409994 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2893409994 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1691000 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1691000 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 13686705498 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 13686705498 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 18806492000 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 18806492000 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 36387650483 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 36387650483 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 21673087497 # number of InvalidateReq MSHR miss cycles
< system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 21673087497 # number of InvalidateReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 742635500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 518427500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 18806492000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 50074355981 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 70141910981 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 742635500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 518427500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 18806492000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 50074355981 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 57180143123 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 127322054104 # number of overall MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1867460000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5357476000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7224936000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1867460000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5357476000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7224936000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.039831 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.061849 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.045118 # mshr miss rate for ReadReq accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 264399 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 264399 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 604132 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 604132 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1109916 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1109916 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 620312 # number of InvalidateReq MSHR misses
> system.cpu0.l2cache.InvalidateReq_mshr_misses::total 620312 # number of InvalidateReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 24258 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 11856 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 604132 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1374315 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 2014561 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 24258 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 11856 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 604132 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1374315 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 950932 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 2965493 # number of overall MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 2093 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 15843 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 17936 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 17283 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 17283 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 2093 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 33126 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 35219 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 763418000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 519315500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1282733500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 66266397744 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 66266397744 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4978129498 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4978129498 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3157260491 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3157260491 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1698499 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1698499 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 14042647500 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14042647500 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 19039385000 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 19039385000 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 39727406492 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 39727406492 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 22010835496 # number of InvalidateReq MSHR miss cycles
> system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 22010835496 # number of InvalidateReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 763418000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 519315500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 19039385000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 53770053992 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 74092172492 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 763418000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 519315500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 19039385000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 53770053992 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 66266397744 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 140358570236 # number of overall MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 185530000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2769951000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 2955481000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 185530000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 2769951000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 2955481000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.035374 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057866 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.040548 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
> system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
1568,1571c1574,1577
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999876 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999876 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999973 # mshr miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999973 # mshr miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999869 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999869 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999985 # mshr miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999985 # mshr miss rate for SCUpgradeReq accesses
1574,1590c1580,1596
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.213971 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.213971 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.098432 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098432 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.241664 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.241664 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.771029 # mshr miss rate for InvalidateReq accesses
< system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.771029 # mshr miss rate for InvalidateReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039831 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.061849 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.098432 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.235307 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.156576 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039831 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.061849 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.098432 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.235307 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.195572 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.195572 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.100281 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.100281 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.243030 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.243030 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.779439 # mshr miss rate for InvalidateReq accesses
> system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.779439 # mshr miss rate for InvalidateReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.035374 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057866 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.100281 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.232190 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.156971 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.035374 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057866 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.100281 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.232190 # mshr miss rate for overall accesses
1592,1670c1598,1676
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230440 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29695.917306 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 42244.744133 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33826.797210 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62512.865639 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 62512.865639 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18642.512439 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18642.512439 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15488.103172 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15488.103172 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 338200 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 338200 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 49922.328195 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 49922.328195 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31976.977722 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31976.977722 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35008.457299 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35008.457299 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 35079.711207 # average InvalidateReq mshr miss latency
< system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 35079.711207 # average InvalidateReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29695.917306 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 42244.744133 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31976.977722 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38121.219028 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36174.979696 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29695.917306 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 42244.744133 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31976.977722 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38121.219028 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62512.865639 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44617.169730 # average overall mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180904.136417 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 141921.426888 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 90336.154858 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89640.516632 # average overall mshr uncacheable latency
< system.cpu0.toL2Bus.snoop_filter.tot_requests 25418604 # Total number of requests made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13061865 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.snoop_filter.tot_snoops 690419 # Total number of snoops made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 690321 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 98 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.cpu0.toL2Bus.trans_dist::ReadReq 966476 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 11336947 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 29691 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 29691 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackDirty 5857040 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackClean 8164049 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::CleanEvict 1344034 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 1151380 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 469212 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 335795 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 509398 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 66 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 113 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 1315239 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 1289150 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5975008 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5298799 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateReq 872203 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateResp 802449 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17966980 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20229549 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 416579 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1325266 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 39938374 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 765101392 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 766341777 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1587352 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5022880 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 1538053401 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 5977120 # Total snoops (count)
< system.cpu0.toL2Bus.snoopTraffic 119917960 # Total snoop traffic (bytes)
< system.cpu0.toL2Bus.snoop_fanout::samples 19518051 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 0.053731 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.225509 # Request fanout histogram
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231066 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31470.772529 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43801.914642 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35519.009248 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69685.737512 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 69685.737512 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18689.969694 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18689.969694 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15574.182095 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15574.182095 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 339699.800000 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 339699.800000 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 53111.575687 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 53111.575687 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31515.273152 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31515.273152 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35793.164971 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35793.164971 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 35483.491366 # average InvalidateReq mshr miss latency
> system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 35483.491366 # average InvalidateReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31470.772529 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43801.914642 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31515.273152 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39124.985169 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36778.321675 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31470.772529 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43801.914642 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31515.273152 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39124.985169 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69685.737512 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 47330.602445 # average overall mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88643.096034 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174837.530771 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164779.270740 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88643.096034 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 83618.637928 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 83917.232176 # average overall mshr uncacheable latency
> system.cpu0.toL2Bus.snoop_filter.tot_requests 26242800 # Total number of requests made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13504787 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 4079 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.snoop_filter.tot_snoops 709472 # Total number of snoops made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 709425 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 47 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.cpu0.toL2Bus.trans_dist::ReadReq 1004788 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 11688716 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 17283 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 17283 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackDirty 6246434 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackClean 8308001 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::CleanEvict 1424808 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 1208828 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 455562 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 363537 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 533487 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 1384860 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 1359346 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6024837 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5574197 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateReq 855548 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateResp 797069 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18077450 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21220350 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 431264 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1446232 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 41175296 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 771132816 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 809027527 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1639096 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5486072 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 1587285511 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 6254740 # Total snoops (count)
> system.cpu0.toL2Bus.snoopTraffic 129367088 # Total snoop traffic (bytes)
> system.cpu0.toL2Bus.snoop_fanout::samples 20223636 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 0.054517 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.227045 # Request fanout histogram
1672,1674c1678,1680
< system.cpu0.toL2Bus.snoop_fanout::0 18469421 94.63% 94.63% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::1 1048532 5.37% 100.00% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::2 98 0.00% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::0 19121152 94.55% 94.55% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::1 1102437 5.45% 100.00% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 47 0.00% 100.00% # Request fanout histogram
1678,1679c1684,1685
< system.cpu0.toL2Bus.snoop_fanout::total 19518051 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 25305808947 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 20223636 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 26091767715 # Layer occupancy (ticks)
1681c1687
< system.cpu0.toL2Bus.snoopLayer0.occupancy 186983903 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 182386585 # Layer occupancy (ticks)
1683c1689
< system.cpu0.toL2Bus.respLayer0.occupancy 8989974042 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 9045827975 # Layer occupancy (ticks)
1685c1691
< system.cpu0.toL2Bus.respLayer1.occupancy 9049403091 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 9544267214 # Layer occupancy (ticks)
1687c1693
< system.cpu0.toL2Bus.respLayer2.occupancy 218640527 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 226891962 # Layer occupancy (ticks)
1689c1695
< system.cpu0.toL2Bus.respLayer3.occupancy 698295209 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 761324284 # Layer occupancy (ticks)
1691,1695c1697,1701
< system.cpu1.branchPred.lookups 130931248 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 87112041 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 6567659 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 91792654 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 56129151 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 124325317 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 79272164 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 6778632 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 83479161 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 47841396 # Number of BTB hits
1697,1704c1703,1710
< system.cpu1.branchPred.BTBHitPct 61.147759 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 17311793 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 174850 # Number of incorrect RAS predictions.
< system.cpu1.branchPred.indirectLookups 4346649 # Number of indirect predictor lookups.
< system.cpu1.branchPred.indirectHits 2655837 # Number of indirect target hits.
< system.cpu1.branchPred.indirectMisses 1690812 # Number of indirect misses.
< system.cpu1.branchPredindirectMispredicted 417178 # Number of mispredicted indirect branches.
< system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
---
> system.cpu1.branchPred.BTBHitPct 57.309388 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 17874464 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 195085 # Number of incorrect RAS predictions.
> system.cpu1.branchPred.indirectLookups 4411145 # Number of indirect predictor lookups.
> system.cpu1.branchPred.indirectHits 2666966 # Number of indirect target hits.
> system.cpu1.branchPred.indirectMisses 1744179 # Number of indirect misses.
> system.cpu1.branchPredindirectMispredicted 432386 # Number of mispredicted indirect branches.
> system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
1734,1787c1740,1793
< system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.cpu1.dtb.walker.walks 551219 # Table walker walks requested
< system.cpu1.dtb.walker.walksLong 551219 # Table walker walks initiated with long descriptors
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11436 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86181 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walksSquashedBefore 255688 # Table walks squashed before starting
< system.cpu1.dtb.walker.walkWaitTime::samples 295531 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::mean 2259.422869 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::stdev 13315.556253 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0-65535 293454 99.30% 99.30% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::65536-131071 1395 0.47% 99.77% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::131072-196607 424 0.14% 99.91% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::196608-262143 158 0.05% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::262144-327679 50 0.02% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::327680-393215 38 0.01% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::total 295531 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkCompletionTime::samples 283173 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::mean 21265.600887 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::gmean 18470.492322 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::stdev 14814.339876 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::0-65535 281324 99.35% 99.35% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1404 0.50% 99.84% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::131072-196607 195 0.07% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::196608-262143 146 0.05% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::262144-327679 42 0.01% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::327680-393215 27 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.00% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::589824-655359 13 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::655360-720895 9 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::total 283173 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walksPending::samples 475307081088 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::mean 0.614132 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::stdev 0.549956 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::0-1 474122952588 99.75% 99.75% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::2-3 603814500 0.13% 99.88% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::4-5 247441500 0.05% 99.93% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::6-7 130616500 0.03% 99.96% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::8-9 93327500 0.02% 99.98% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::10-11 62495500 0.01% 99.99% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::12-13 19627500 0.00% 99.99% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::14-15 26354000 0.01% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::16-17 445000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::18-19 6500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::total 475307081088 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walkPageSizes::4K 86181 88.28% 88.28% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::2M 11436 11.72% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 97617 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 551219 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.cpu1.dtb.walker.walks 580775 # Table walker walks requested
> system.cpu1.dtb.walker.walksLong 580775 # Table walker walks initiated with long descriptors
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12302 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93041 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walksSquashedBefore 266909 # Table walks squashed before starting
> system.cpu1.dtb.walker.walkWaitTime::samples 313866 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::mean 2454.023373 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::stdev 13953.006998 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0-65535 311371 99.21% 99.21% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::65536-131071 1689 0.54% 99.74% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::131072-196607 507 0.16% 99.90% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::196608-262143 189 0.06% 99.96% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::262144-327679 54 0.02% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::327680-393215 44 0.01% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::total 313866 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkCompletionTime::samples 295327 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::mean 21717.315044 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::gmean 18678.510143 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::stdev 17673.432878 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::0-65535 292731 99.12% 99.12% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1780 0.60% 99.72% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::131072-196607 365 0.12% 99.85% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::196608-262143 243 0.08% 99.93% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::262144-327679 59 0.02% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::327680-393215 66 0.02% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.00% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::458752-524287 14 0.00% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::589824-655359 35 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::655360-720895 14 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::total 295327 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walksPending::samples 389340230128 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::mean 0.666551 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::stdev 0.555298 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::0-1 388038620628 99.67% 99.67% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::2-3 674944000 0.17% 99.84% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::4-5 273419500 0.07% 99.91% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::6-7 140502000 0.04% 99.95% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::8-9 100194000 0.03% 99.97% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::10-11 59021000 0.02% 99.99% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::12-13 22755500 0.01% 99.99% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::14-15 30241000 0.01% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::16-17 482500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::18-19 50000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::total 389340230128 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walkPageSizes::4K 93042 88.32% 88.32% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::2M 12302 11.68% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 105344 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 580775 # Table walker requests started/completed, data/inst
1789,1790c1795,1796
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 551219 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97617 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 580775 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105344 # Table walker requests started/completed, data/inst
1792,1793c1798,1799
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97617 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 648836 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105344 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 686119 # Table walker requests started/completed, data/inst
1796,1800c1802,1806
< system.cpu1.dtb.read_hits 95947338 # DTB read hits
< system.cpu1.dtb.read_misses 376138 # DTB read misses
< system.cpu1.dtb.write_hits 79464123 # DTB write hits
< system.cpu1.dtb.write_misses 175081 # DTB write misses
< system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
---
> system.cpu1.dtb.read_hits 97816184 # DTB read hits
> system.cpu1.dtb.read_misses 397931 # DTB read misses
> system.cpu1.dtb.write_hits 81264416 # DTB write hits
> system.cpu1.dtb.write_misses 182844 # DTB write misses
> system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
1802,1806c1808,1812
< system.cpu1.dtb.flush_tlb_mva_asid 44658 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
< system.cpu1.dtb.flush_entries 35142 # Number of entries that have been flushed from TLB
< system.cpu1.dtb.align_faults 372 # Number of TLB faults due to alignment restrictions
< system.cpu1.dtb.prefetch_faults 6075 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.dtb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID
> system.cpu1.dtb.flush_entries 36337 # Number of entries that have been flushed from TLB
> system.cpu1.dtb.align_faults 714 # Number of TLB faults due to alignment restrictions
> system.cpu1.dtb.prefetch_faults 7662 # Number of TLB faults due to prefetch
1808,1810c1814,1816
< system.cpu1.dtb.perms_faults 39563 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 96323476 # DTB read accesses
< system.cpu1.dtb.write_accesses 79639204 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 41901 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 98214115 # DTB read accesses
> system.cpu1.dtb.write_accesses 81447260 # DTB write accesses
1812,1815c1818,1821
< system.cpu1.dtb.hits 175411461 # DTB hits
< system.cpu1.dtb.misses 551219 # DTB misses
< system.cpu1.dtb.accesses 175962680 # DTB accesses
< system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
---
> system.cpu1.dtb.hits 179080600 # DTB hits
> system.cpu1.dtb.misses 580775 # DTB misses
> system.cpu1.dtb.accesses 179661375 # DTB accesses
> system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
1845,1889c1851,1894
< system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.cpu1.itb.walker.walks 82567 # Table walker walks requested
< system.cpu1.itb.walker.walksLong 82567 # Table walker walks initiated with long descriptors
< system.cpu1.itb.walker.walksLongTerminationLevel::Level2 985 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walksLongTerminationLevel::Level3 60088 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walksSquashedBefore 9957 # Table walks squashed before starting
< system.cpu1.itb.walker.walkWaitTime::samples 72610 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::mean 937.467291 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::stdev 7808.036609 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::0-65535 72461 99.79% 99.79% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::65536-131071 121 0.17% 99.96% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::131072-196607 15 0.02% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::196608-262143 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::262144-327679 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::total 72610 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkCompletionTime::samples 71030 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::mean 24890.468816 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::gmean 22675.930059 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::stdev 19295.215598 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::0-65535 70173 98.79% 98.79% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::65536-131071 554 0.78% 99.57% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::131072-196607 204 0.29% 99.86% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::196608-262143 35 0.05% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::262144-327679 20 0.03% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::327680-393215 8 0.01% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::589824-655359 25 0.04% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::total 71030 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walksPending::samples 397994478260 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::mean 0.871343 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::stdev 0.334985 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::0 51225264788 12.87% 12.87% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::1 346750110472 87.12% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::2 17741500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::3 1276000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::4 85500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::total 397994478260 # Table walker pending requests distribution
< system.cpu1.itb.walker.walkPageSizes::4K 60088 98.39% 98.39% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::2M 985 1.61% 100.00% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::total 61073 # Table walker page sizes translated
---
> system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.cpu1.itb.walker.walks 87135 # Table walker walks requested
> system.cpu1.itb.walker.walksLong 87135 # Table walker walks initiated with long descriptors
> system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1092 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walksLongTerminationLevel::Level3 62581 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walksSquashedBefore 10397 # Table walks squashed before starting
> system.cpu1.itb.walker.walkWaitTime::samples 76738 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::mean 1034.422320 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::stdev 9201.232348 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::0-65535 76494 99.68% 99.68% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::65536-131071 186 0.24% 99.92% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::131072-196607 34 0.04% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::196608-262143 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::262144-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::327680-393215 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::total 76738 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkCompletionTime::samples 74070 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::mean 25472.262724 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::gmean 22851.948587 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::stdev 20227.385308 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::0-65535 72813 98.30% 98.30% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::65536-131071 775 1.05% 99.35% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::131072-196607 316 0.43% 99.78% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::196608-262143 87 0.12% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::262144-327679 33 0.04% 99.94% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::589824-655359 17 0.02% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::total 74070 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walksPending::samples 329207699984 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::mean 0.888226 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::stdev 0.315322 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::0 36820179964 11.18% 11.18% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::1 292365319520 88.81% 99.99% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::2 21267000 0.01% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::3 903500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::4 30000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::total 329207699984 # Table walker pending requests distribution
> system.cpu1.itb.walker.walkPageSizes::4K 62581 98.28% 98.28% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::2M 1092 1.72% 100.00% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::total 63673 # Table walker page sizes translated
1891,1892c1896,1897
< system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 82567 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Requested::total 82567 # Table walker requests started/completed, data/inst
---
> system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 87135 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Requested::total 87135 # Table walker requests started/completed, data/inst
1894,1898c1899,1903
< system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61073 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61073 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin::total 143640 # Table walker requests started/completed, data/inst
< system.cpu1.itb.inst_hits 204871540 # ITB inst hits
< system.cpu1.itb.inst_misses 82567 # ITB inst misses
---
> system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63673 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63673 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin::total 150808 # Table walker requests started/completed, data/inst
> system.cpu1.itb.inst_hits 190777093 # ITB inst hits
> system.cpu1.itb.inst_misses 87135 # ITB inst misses
1903c1908
< system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
---
> system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
1905,1907c1910,1912
< system.cpu1.itb.flush_tlb_mva_asid 44658 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
< system.cpu1.itb.flush_entries 24862 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.itb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID
> system.cpu1.itb.flush_entries 25727 # Number of entries that have been flushed from TLB
1911c1916
< system.cpu1.itb.perms_faults 205327 # Number of TLB faults due to permissions restrictions
---
> system.cpu1.itb.perms_faults 222647 # Number of TLB faults due to permissions restrictions
1914,1930c1919,1935
< system.cpu1.itb.inst_accesses 204954107 # ITB inst accesses
< system.cpu1.itb.hits 204871540 # DTB hits
< system.cpu1.itb.misses 82567 # DTB misses
< system.cpu1.itb.accesses 204954107 # DTB accesses
< system.cpu1.numPwrStateTransitions 10338 # Number of power state transitions
< system.cpu1.pwrStateClkGateDist::samples 5169 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::mean 9100042413.076223 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::stdev 142913287882.442078 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::underflows 3563 68.93% 68.93% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::1000-5e+10 1580 30.57% 99.50% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.04% 99.54% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 5 0.10% 99.63% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.04% 99.67% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.69% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::overflows 14 0.27% 100.00% # Distribution of time spent in the clock gated state
---
> system.cpu1.itb.inst_accesses 190864228 # ITB inst accesses
> system.cpu1.itb.hits 190777093 # DTB hits
> system.cpu1.itb.misses 87135 # DTB misses
> system.cpu1.itb.accesses 190864228 # DTB accesses
> system.cpu1.numPwrStateTransitions 27368 # Number of power state transitions
> system.cpu1.pwrStateClkGateDist::samples 13684 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::mean 3437541610.585575 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::stdev 87855050570.390015 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::underflows 3277 23.95% 23.95% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::1000-5e+10 10379 75.85% 99.80% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::5e+10-1e+11 4 0.03% 99.82% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 2 0.01% 99.89% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state
1932,1936c1937,1941
< system.cpu1.pwrStateClkGateDist::max_value 7390880676264 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::total 5169 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateResidencyTicks::ON 346821221809 # Cumulative time (in ticks) in various power states
< system.cpu1.pwrStateResidencyTicks::CLK_GATED 47038119233191 # Cumulative time (in ticks) in various power states
< system.cpu1.numCycles 693644050 # number of cpu cycles simulated
---
> system.cpu1.pwrStateClkGateDist::max_value 7351150614736 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::total 13684 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateResidencyTicks::ON 302603854747 # Cumulative time (in ticks) in various power states
> system.cpu1.pwrStateResidencyTicks::CLK_GATED 47039319399253 # Cumulative time (in ticks) in various power states
> system.cpu1.numCycles 605218102 # number of cpu cycles simulated
1939,1955c1944,1960
< system.cpu1.fetch.icacheStallCycles 87527745 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 578391241 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 130931248 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 76096781 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 569305331 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 14062296 # Number of cycles fetch has spent squashing
< system.cpu1.fetch.TlbCycles 1768387 # Number of cycles fetch has spent waiting for tlb
< system.cpu1.fetch.MiscStallCycles 291884 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu1.fetch.PendingTrapStallCycles 5735168 # Number of stall cycles due to pending traps
< system.cpu1.fetch.PendingQuiesceStallCycles 727906 # Number of stall cycles due to pending quiesce instructions
< system.cpu1.fetch.IcacheWaitRetryStallCycles 800824 # Number of stall cycles due to full MSHR
< system.cpu1.fetch.CacheLines 204645173 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 1664411 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.ItlbSquashes 27214 # Number of outstanding ITLB misses that were squashed
< system.cpu1.fetch.rateDist::samples 673188393 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 1.008077 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 1.227099 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.icacheStallCycles 90677216 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 553360207 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 124325317 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 68382826 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 474472155 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 14605284 # Number of cycles fetch has spent squashing
> system.cpu1.fetch.TlbCycles 1912826 # Number of cycles fetch has spent waiting for tlb
> system.cpu1.fetch.MiscStallCycles 316489 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu1.fetch.PendingTrapStallCycles 6235887 # Number of stall cycles due to pending traps
> system.cpu1.fetch.PendingQuiesceStallCycles 776312 # Number of stall cycles due to pending quiesce instructions
> system.cpu1.fetch.IcacheWaitRetryStallCycles 869780 # Number of stall cycles due to full MSHR
> system.cpu1.fetch.CacheLines 190532631 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 1731041 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.ItlbSquashes 28903 # Number of outstanding ITLB misses that were squashed
> system.cpu1.fetch.rateDist::samples 582563307 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 1.126942 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 1.253057 # Number of instructions fetched each cycle (Total)
1957,1960c1962,1965
< system.cpu1.fetch.rateDist::0 348457754 51.76% 51.76% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 126514971 18.79% 70.56% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 42536092 6.32% 76.87% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 155679576 23.13% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 272142185 46.71% 46.71% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 117259342 20.13% 66.84% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 40229436 6.91% 73.75% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 152932344 26.25% 100.00% # Number of instructions fetched each cycle (Total)
1964,2011c1969,2016
< system.cpu1.fetch.rateDist::total 673188393 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.188759 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 0.833844 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 102787429 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 312284706 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 218180532 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 34930241 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 5005485 # Number of cycles decode is squashing
< system.cpu1.decode.BranchResolved 18306368 # Number of times decode resolved a branch
< system.cpu1.decode.BranchMispred 2064498 # Number of times decode detected a branch misprediction
< system.cpu1.decode.DecodedInsts 600925596 # Number of instructions handled by decode
< system.cpu1.decode.SquashedInsts 22793962 # Number of squashed instructions handled by decode
< system.cpu1.rename.SquashCycles 5005485 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 136395689 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 44912882 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 210797905 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 219085305 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 56991127 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 584399745 # Number of instructions processed by rename
< system.cpu1.rename.SquashedInsts 6001663 # Number of squashed instructions processed by rename
< system.cpu1.rename.ROBFullEvents 9489847 # Number of times rename has blocked due to ROB full
< system.cpu1.rename.IQFullEvents 242679 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LQFullEvents 273258 # Number of times rename has blocked due to LQ full
< system.cpu1.rename.SQFullEvents 24369803 # Number of times rename has blocked due to SQ full
< system.cpu1.rename.FullRegisterEvents 10662 # Number of times there has been no free registers
< system.cpu1.rename.RenamedOperands 555653486 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 898470064 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 689649249 # Number of integer rename lookups
< system.cpu1.rename.fp_rename_lookups 841085 # Number of floating rename lookups
< system.cpu1.rename.CommittedMaps 500004101 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 55649379 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 14907079 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 13060204 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 70305418 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 96437745 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 82644936 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 8695524 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 7557089 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 562795340 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 15022202 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 566786483 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 2618124 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 52408988 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 33720273 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 259964 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 673188393 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 0.841943 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 1.073212 # Number of insts issued each cycle
---
> system.cpu1.fetch.rateDist::total 582563307 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.205422 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 0.914315 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 100710093 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 231252575 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 221227930 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 24164908 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 5207801 # Number of cycles decode is squashing
> system.cpu1.decode.BranchResolved 44439760 # Number of times decode resolved a branch
> system.cpu1.decode.BranchMispred 2135059 # Number of times decode detected a branch misprediction
> system.cpu1.decode.DecodedInsts 575305987 # Number of instructions handled by decode
> system.cpu1.decode.SquashedInsts 23412205 # Number of squashed instructions handled by decode
> system.cpu1.rename.SquashCycles 5207801 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 129334574 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 47434760 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 137391497 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 216168101 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 47026574 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 558184675 # Number of instructions processed by rename
> system.cpu1.rename.SquashedInsts 6143864 # Number of squashed instructions processed by rename
> system.cpu1.rename.ROBFullEvents 9881225 # Number of times rename has blocked due to ROB full
> system.cpu1.rename.IQFullEvents 309237 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LQFullEvents 251476 # Number of times rename has blocked due to LQ full
> system.cpu1.rename.SQFullEvents 25589786 # Number of times rename has blocked due to SQ full
> system.cpu1.rename.FullRegisterEvents 13193 # Number of times there has been no free registers
> system.cpu1.rename.RenamedOperands 510403185 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 786411891 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 655895321 # Number of integer rename lookups
> system.cpu1.rename.fp_rename_lookups 811726 # Number of floating rename lookups
> system.cpu1.rename.CommittedMaps 453487095 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 56916084 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 6219044 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 4304916 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 51458924 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 98128925 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 84474197 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 8967706 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 7764120 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 545083370 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 6336595 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 540345314 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 2650065 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 53579246 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 34592760 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 257601 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 582563307 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 0.927531 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 1.122571 # Number of insts issued each cycle
2013,2018c2018,2023
< system.cpu1.iq.issued_per_cycle::0 363862102 54.05% 54.05% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 129787759 19.28% 73.33% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 109122281 16.21% 89.54% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 62914886 9.35% 98.89% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 7497321 1.11% 100.00% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 4044 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 303220433 52.05% 52.05% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 97196070 16.68% 68.73% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 110913519 19.04% 87.77% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 63614426 10.92% 98.69% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 7615367 1.31% 100.00% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 3492 0.00% 100.00% # Number of insts issued each cycle
2025c2030
< system.cpu1.iq.issued_per_cycle::total 673188393 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 582563307 # Number of insts issued each cycle
2027,2061c2032,2066
< system.cpu1.iq.fu_full::IntAlu 57388953 44.23% 44.23% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 51651 0.04% 44.27% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 16856 0.01% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMisc 103 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.29% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 34250281 26.40% 70.69% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 37595364 28.98% 99.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMemRead 47943 0.04% 99.70% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMemWrite 388183 0.30% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 57271310 43.60% 43.60% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 51119 0.04% 43.64% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 18601 0.01% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMisc 112 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.65% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 35025270 26.66% 70.31% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 38581798 29.37% 99.68% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMemRead 47664 0.04% 99.72% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMemWrite 368619 0.28% 100.00% # attempts to use FU when none available
2064,2099c2069,2104
< system.cpu1.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntAlu 385773007 68.06% 68.06% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 1187343 0.21% 68.27% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 69773 0.01% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 8 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCmp 13 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCvt 27 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMisc 84205 0.01% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAddAcc 2 0.00% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.30% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemRead 98926523 17.45% 85.75% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 80304665 14.17% 99.92% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMemRead 64060 0.01% 99.93% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMemWrite 376846 0.07% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::No_OpClass 76 0.00% 0.00% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntAlu 355477037 65.79% 65.79% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 1278002 0.24% 66.02% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 69863 0.01% 66.04% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 8 0.00% 66.04% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.04% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.04% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.04% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 66.04% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.04% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMisc 79928 0.01% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.05% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemRead 100880874 18.67% 84.72% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 82125393 15.20% 99.92% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMemRead 69486 0.01% 99.93% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMemWrite 364646 0.07% 100.00% # Type of FU issued
2102,2114c2107,2119
< system.cpu1.iq.FU_type_0::total 566786483 # Type of FU issued
< system.cpu1.iq.rate 0.817114 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 129739334 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.228903 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 1937625833 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 629808815 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 550243700 # Number of integer instruction queue wakeup accesses
< system.cpu1.iq.fp_inst_queue_reads 1492982 # Number of floating instruction queue reads
< system.cpu1.iq.fp_inst_queue_writes 556682 # Number of floating instruction queue writes
< system.cpu1.iq.fp_inst_queue_wakeup_accesses 518492 # Number of floating instruction queue wakeup accesses
< system.cpu1.iq.int_alu_accesses 695564416 # Number of integer alu accesses
< system.cpu1.iq.fp_alu_accesses 961390 # Number of floating point alu accesses
< system.cpu1.iew.lsq.thread0.forwLoads 2525668 # Number of loads that had data forwarded from stores
---
> system.cpu1.iq.FU_type_0::total 540345314 # Type of FU issued
> system.cpu1.iq.rate 0.892811 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 131364493 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.243112 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 1795817951 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 604594628 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 523100921 # Number of integer instruction queue wakeup accesses
> system.cpu1.iq.fp_inst_queue_reads 1450540 # Number of floating instruction queue reads
> system.cpu1.iq.fp_inst_queue_writes 543567 # Number of floating instruction queue writes
> system.cpu1.iq.fp_inst_queue_wakeup_accesses 507957 # Number of floating instruction queue wakeup accesses
> system.cpu1.iq.int_alu_accesses 670779267 # Number of integer alu accesses
> system.cpu1.iq.fp_alu_accesses 930464 # Number of floating point alu accesses
> system.cpu1.iew.lsq.thread0.forwLoads 2614124 # Number of loads that had data forwarded from stores
2116,2119c2121,2124
< system.cpu1.iew.lsq.thread0.squashedLoads 12072145 # Number of loads squashed
< system.cpu1.iew.lsq.thread0.ignoredResponses 16264 # Number of memory responses ignored because the instruction is squashed
< system.cpu1.iew.lsq.thread0.memOrderViolation 139965 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 5400546 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 12461558 # Number of loads squashed
> system.cpu1.iew.lsq.thread0.ignoredResponses 17016 # Number of memory responses ignored because the instruction is squashed
> system.cpu1.iew.lsq.thread0.memOrderViolation 140230 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 5490502 # Number of stores squashed
2122,2123c2127,2128
< system.cpu1.iew.lsq.thread0.rescheduledLoads 2506634 # Number of loads that were rescheduled
< system.cpu1.iew.lsq.thread0.cacheBlocked 3911021 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu1.iew.lsq.thread0.rescheduledLoads 2570995 # Number of loads that were rescheduled
> system.cpu1.iew.lsq.thread0.cacheBlocked 4304841 # Number of times an access to memory failed due to the cache being blocked
2125,2128c2130,2133
< system.cpu1.iew.iewSquashCycles 5005485 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 6180671 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 1541266 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 577948873 # Number of instructions dispatched to IQ
---
> system.cpu1.iew.iewSquashCycles 5207801 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 6764064 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 1538743 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 551558167 # Number of instructions dispatched to IQ
2130,2141c2135,2146
< system.cpu1.iew.iewDispLoadInsts 96437745 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 82644936 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 12856669 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 62955 # Number of times the IQ has become full, causing a stall
< system.cpu1.iew.iewLSQFullEvents 1418771 # Number of times the LSQ has become full, causing a stall
< system.cpu1.iew.memOrderViolationEvents 139965 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 1860771 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 3017279 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 4878050 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 559031023 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 95939165 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 7216233 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.iewDispLoadInsts 98128925 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 84474197 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 4043182 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 70701 # Number of times the IQ has become full, causing a stall
> system.cpu1.iew.iewLSQFullEvents 1397089 # Number of times the LSQ has become full, causing a stall
> system.cpu1.iew.memOrderViolationEvents 140230 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 1929682 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 3114694 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 5044376 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 532413736 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 97811900 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 7363284 # Number of squashed instructions skipped in execute
2143,2159c2148,2164
< system.cpu1.iew.exec_nop 131331 # number of nop insts executed
< system.cpu1.iew.exec_refs 175402489 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 104887487 # Number of branches executed
< system.cpu1.iew.exec_stores 79463324 # Number of stores executed
< system.cpu1.iew.exec_rate 0.805934 # Inst execution rate
< system.cpu1.iew.wb_sent 551451357 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 550762192 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 266030186 # num instructions producing a value
< system.cpu1.iew.wb_consumers 436524752 # num instructions consuming a value
< system.cpu1.iew.wb_rate 0.794013 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.609427 # average fanout of values written-back
< system.cpu1.commit.commitSquashedInsts 45696838 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 14762238 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 4541996 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 664504904 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 0.790677 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.583374 # Number of insts commited each cycle
---
> system.cpu1.iew.exec_nop 138202 # number of nop insts executed
> system.cpu1.iew.exec_refs 179076621 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 97312103 # Number of branches executed
> system.cpu1.iew.exec_stores 81264721 # Number of stores executed
> system.cpu1.iew.exec_rate 0.879706 # Inst execution rate
> system.cpu1.iew.wb_sent 524373694 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 523608878 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 254758095 # num instructions producing a value
> system.cpu1.iew.wb_consumers 415275761 # num instructions consuming a value
> system.cpu1.iew.wb_rate 0.865157 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.613467 # average fanout of values written-back
> system.cpu1.commit.commitSquashedInsts 46732947 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 6078994 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 4683791 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 573586803 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 0.867943 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 1.693393 # Number of insts commited each cycle
2161,2169c2166,2174
< system.cpu1.commit.committed_per_cycle::0 434201366 65.34% 65.34% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 119136384 17.93% 83.27% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 51278197 7.72% 90.99% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 17339439 2.61% 93.60% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 12299899 1.85% 95.45% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 8244778 1.24% 96.69% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 5665589 0.85% 97.54% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 3433584 0.52% 98.06% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 12905668 1.94% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 375218582 65.42% 65.42% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 85397429 14.89% 80.30% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 52348334 9.13% 89.43% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 17503204 3.05% 92.48% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 12415456 2.16% 94.65% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 8370820 1.46% 96.11% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 5748485 1.00% 97.11% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 3445775 0.60% 97.71% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 13138718 2.29% 100.00% # Number of insts commited each cycle
2173,2175c2178,2180
< system.cpu1.commit.committed_per_cycle::total 664504904 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 446004136 # Number of instructions committed
< system.cpu1.commit.committedOps 525408547 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 573586803 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 416374803 # Number of instructions committed
> system.cpu1.commit.committedOps 497840712 # Number of ops (including micro ops) committed
2177,2183c2182,2188
< system.cpu1.commit.refs 161609989 # Number of memory references committed
< system.cpu1.commit.loads 84365599 # Number of loads committed
< system.cpu1.commit.membars 3561329 # Number of memory barriers committed
< system.cpu1.commit.branches 99629625 # Number of branches committed
< system.cpu1.commit.fp_insts 509948 # Number of committed floating point instructions.
< system.cpu1.commit.int_insts 482210935 # Number of committed integer instructions.
< system.cpu1.commit.function_calls 12864051 # Number of function calls committed.
---
> system.cpu1.commit.refs 164651061 # Number of memory references committed
> system.cpu1.commit.loads 85667366 # Number of loads committed
> system.cpu1.commit.membars 3698541 # Number of memory barriers committed
> system.cpu1.commit.branches 91988554 # Number of branches committed
> system.cpu1.commit.fp_insts 499479 # Number of committed floating point instructions.
> system.cpu1.commit.int_insts 463071817 # Number of committed integer instructions.
> system.cpu1.commit.function_calls 13152854 # Number of function calls committed.
2185,2219c2190,2224
< system.cpu1.commit.op_class_0::IntAlu 362699186 69.03% 69.03% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntMult 966499 0.18% 69.22% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntDiv 55760 0.01% 69.23% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatAdd 8 0.00% 69.23% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCmp 13 0.00% 69.23% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCvt 21 0.00% 69.23% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.23% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 69.23% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.23% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMisc 77071 0.01% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemRead 84306280 16.05% 85.29% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemWrite 76870874 14.63% 99.92% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMemRead 59319 0.01% 99.93% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMemWrite 373516 0.07% 100.00% # Class of committed instruction
---
> system.cpu1.commit.op_class_0::IntAlu 332017365 66.69% 66.69% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntMult 1043826 0.21% 66.90% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntDiv 55377 0.01% 66.91% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.91% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 66.91% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 66.91% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMult 0 0.00% 66.91% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 66.91% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 66.91% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMisc 73083 0.01% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMult 0 0.00% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShift 0 0.00% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemRead 85601974 17.19% 84.12% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemWrite 78622691 15.79% 99.91% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMemRead 65392 0.01% 99.93% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMemWrite 361004 0.07% 100.00% # Class of committed instruction
2222,2252c2227,2257
< system.cpu1.commit.op_class_0::total 525408547 # Class of committed instruction
< system.cpu1.commit.bw_lim_events 12905668 # number cycles where commit BW limit reached
< system.cpu1.rob.rob_reads 1219098786 # The number of ROB reads
< system.cpu1.rob.rob_writes 1150856845 # The number of ROB writes
< system.cpu1.timesIdled 925679 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 20455657 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 94076236903 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 446004136 # Number of Instructions Simulated
< system.cpu1.committedOps 525408547 # Number of Ops (including micro ops) Simulated
< system.cpu1.cpi 1.555241 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 1.555241 # CPI: Total CPI of All Threads
< system.cpu1.ipc 0.642987 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 0.642987 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 659945611 # number of integer regfile reads
< system.cpu1.int_regfile_writes 391450025 # number of integer regfile writes
< system.cpu1.fp_regfile_reads 826837 # number of floating regfile reads
< system.cpu1.fp_regfile_writes 461620 # number of floating regfile writes
< system.cpu1.cc_regfile_reads 120567774 # number of cc regfile reads
< system.cpu1.cc_regfile_writes 121287073 # number of cc regfile writes
< system.cpu1.misc_regfile_reads 1215585693 # number of misc regfile reads
< system.cpu1.misc_regfile_writes 14957440 # number of misc regfile writes
< system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.cpu1.dcache.tags.replacements 5242137 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 459.717362 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 151071021 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 5242649 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 28.815780 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 8517875621500 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 459.717362 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.897885 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.897885 # Average percentage of cache occupancy
---
> system.cpu1.commit.op_class_0::total 497840712 # Class of committed instruction
> system.cpu1.commit.bw_lim_events 13138718 # number cycles where commit BW limit reached
> system.cpu1.rob.rob_reads 1100782906 # The number of ROB reads
> system.cpu1.rob.rob_writes 1098088032 # The number of ROB writes
> system.cpu1.timesIdled 993023 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 22654795 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 94078628435 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 416374803 # Number of Instructions Simulated
> system.cpu1.committedOps 497840712 # Number of Ops (including micro ops) Simulated
> system.cpu1.cpi 1.453542 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 1.453542 # CPI: Total CPI of All Threads
> system.cpu1.ipc 0.687975 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 0.687975 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 625781479 # number of integer regfile reads
> system.cpu1.int_regfile_writes 379830432 # number of integer regfile writes
> system.cpu1.fp_regfile_reads 798661 # number of floating regfile reads
> system.cpu1.fp_regfile_writes 473896 # number of floating regfile writes
> system.cpu1.cc_regfile_reads 94918566 # number of cc regfile reads
> system.cpu1.cc_regfile_writes 95638413 # number of cc regfile writes
> system.cpu1.misc_regfile_reads 1053266822 # number of misc regfile reads
> system.cpu1.misc_regfile_writes 6252018 # number of misc regfile writes
> system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.cpu1.dcache.tags.replacements 5530000 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 456.074004 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 153151228 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 5530512 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 27.692052 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 8516003368500 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.074004 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890770 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.890770 # Average percentage of cache occupancy
2254,2256c2259,2261
< system.cpu1.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::1 393 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
---
> system.cpu1.dcache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id
2258,2350c2263,2355
< system.cpu1.dcache.tags.tag_accesses 335085452 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 335085452 # Number of data accesses
< system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.cpu1.dcache.ReadReq_hits::cpu1.data 78683388 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 78683388 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 67788952 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 67788952 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 181257 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 181257 # number of SoftPFReq hits
< system.cpu1.dcache.WriteLineReq_hits::cpu1.data 140156 # number of WriteLineReq hits
< system.cpu1.dcache.WriteLineReq_hits::total 140156 # number of WriteLineReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1756750 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 1756750 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1770273 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 1770273 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 146612496 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 146612496 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 146793753 # number of overall hits
< system.cpu1.dcache.overall_hits::total 146793753 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 6126313 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 6126313 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 6911292 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 6911292 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 643081 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 643081 # number of SoftPFReq misses
< system.cpu1.dcache.WriteLineReq_misses::cpu1.data 451908 # number of WriteLineReq misses
< system.cpu1.dcache.WriteLineReq_misses::total 451908 # number of WriteLineReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 241040 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 241040 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 183733 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 183733 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 13489513 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 13489513 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 14132594 # number of overall misses
< system.cpu1.dcache.overall_misses::total 14132594 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 94548549000 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 94548549000 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 128933568944 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 128933568944 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10455217570 # number of WriteLineReq miss cycles
< system.cpu1.dcache.WriteLineReq_miss_latency::total 10455217570 # number of WriteLineReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3390405500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 3390405500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4379858500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 4379858500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2605000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2605000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 233937335514 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 233937335514 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 233937335514 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 233937335514 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 84809701 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 84809701 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 74700244 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 74700244 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 824338 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 824338 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 592064 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::total 592064 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1997790 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 1997790 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1954006 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 1954006 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 160102009 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 160102009 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 160926347 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 160926347 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.072236 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.072236 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.092520 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.092520 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.780118 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.780118 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.763276 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::total 0.763276 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120653 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120653 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094029 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094029 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.084256 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.084256 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087820 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.087820 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15433.189424 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 15433.189424 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18655.494363 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 18655.494363 # average WriteReq miss latency
< system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23135.721364 # average WriteLineReq miss latency
< system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23135.721364 # average WriteLineReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14065.738052 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14065.738052 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23838.170062 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23838.170062 # average StoreCondReq miss latency
---
> system.cpu1.dcache.tags.tag_accesses 341526918 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 341526918 # Number of data accesses
> system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.cpu1.dcache.ReadReq_hits::cpu1.data 79602961 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 79602961 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 68799990 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 68799990 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187687 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 187687 # number of SoftPFReq hits
> system.cpu1.dcache.WriteLineReq_hits::cpu1.data 159948 # number of WriteLineReq hits
> system.cpu1.dcache.WriteLineReq_hits::total 159948 # number of WriteLineReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1827869 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 1827869 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1836377 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 1836377 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 148562899 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 148562899 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 148750586 # number of overall hits
> system.cpu1.dcache.overall_hits::total 148750586 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 6412648 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 6412648 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 7514708 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 7514708 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 707982 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 707982 # number of SoftPFReq misses
> system.cpu1.dcache.WriteLineReq_misses::cpu1.data 465981 # number of WriteLineReq misses
> system.cpu1.dcache.WriteLineReq_misses::total 465981 # number of WriteLineReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 246351 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 246351 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195484 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 195484 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 14393337 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 14393337 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 15101319 # number of overall misses
> system.cpu1.dcache.overall_misses::total 15101319 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 101710324000 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 101710324000 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 138164152559 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 138164152559 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10841403957 # number of WriteLineReq miss cycles
> system.cpu1.dcache.WriteLineReq_miss_latency::total 10841403957 # number of WriteLineReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3505750500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 3505750500 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4668207500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 4668207500 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2827500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2827500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 250715880516 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 250715880516 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 250715880516 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 250715880516 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 86015609 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 86015609 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 76314698 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 76314698 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 895669 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 895669 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 625929 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::total 625929 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2074220 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 2074220 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2031861 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 2031861 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 162956236 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 162956236 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 163851905 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 163851905 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074552 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.074552 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.098470 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.098470 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.790450 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.790450 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.744463 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::total 0.744463 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118768 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118768 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.096209 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.096209 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.088326 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.088326 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.092164 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.092164 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15860.893035 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15860.893035 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18385.831167 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 18385.831167 # average WriteReq miss latency
> system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23265.763962 # average WriteLineReq miss latency
> system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23265.763962 # average WriteLineReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14230.713494 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14230.713494 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23880.253627 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23880.253627 # average StoreCondReq miss latency
2353,2448c2358,2453
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17342.163169 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 17342.163169 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16553.035877 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 16553.035877 # average overall miss latency
< system.cpu1.dcache.blocked_cycles::no_mshrs 2644851 # number of cycles access was blocked
< system.cpu1.dcache.blocked_cycles::no_targets 20463296 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_mshrs 369952 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_targets 688434 # number of cycles access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.149173 # average number of cycles each access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_targets 29.724412 # average number of cycles each access was blocked
< system.cpu1.dcache.writebacks::writebacks 5242162 # number of writebacks
< system.cpu1.dcache.writebacks::total 5242162 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3113636 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 3113636 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5578267 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 5578267 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3659 # number of WriteLineReq MSHR hits
< system.cpu1.dcache.WriteLineReq_mshr_hits::total 3659 # number of WriteLineReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 125068 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 125068 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 8695562 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 8695562 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 8695562 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 8695562 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3012677 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 3012677 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1333025 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 1333025 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 643006 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 643006 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 448249 # number of WriteLineReq MSHR misses
< system.cpu1.dcache.WriteLineReq_mshr_misses::total 448249 # number of WriteLineReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 115972 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 115972 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 183726 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 183726 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 4793951 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 4793951 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 5436957 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 5436957 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8871 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8871 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 8695 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::total 8695 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17566 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17566 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42819104500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42819104500 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26001782801 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26001782801 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14897861000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14897861000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9889085570 # number of WriteLineReq MSHR miss cycles
< system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9889085570 # number of WriteLineReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1553813500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1553813500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4196193500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4196193500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2544000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2544000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 78709972871 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 78709972871 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 93607833871 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 93607833871 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1354957000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1354957000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1354957000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1354957000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035523 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035523 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017845 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017845 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.780027 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.780027 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.757096 # mshr miss rate for WriteLineReq accesses
< system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.757096 # mshr miss rate for WriteLineReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058050 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058050 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094025 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094025 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029943 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.029943 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033785 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.033785 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14212.975536 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14212.975536 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19505.847828 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19505.847828 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23169.085514 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23169.085514 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22061.589808 # average WriteLineReq mshr miss latency
< system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22061.589808 # average WriteLineReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13398.178008 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13398.178008 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22839.410318 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22839.410318 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17418.884899 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 17418.884899 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16602.250473 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 16602.250473 # average overall miss latency
> system.cpu1.dcache.blocked_cycles::no_mshrs 2802154 # number of cycles access was blocked
> system.cpu1.dcache.blocked_cycles::no_targets 21903502 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_mshrs 386416 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_targets 756136 # number of cycles access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.251651 # average number of cycles each access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_targets 28.967675 # average number of cycles each access was blocked
> system.cpu1.dcache.writebacks::writebacks 5530029 # number of writebacks
> system.cpu1.dcache.writebacks::total 5530029 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3294839 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 3294839 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6084278 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 6084278 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3511 # number of WriteLineReq MSHR hits
> system.cpu1.dcache.WriteLineReq_mshr_hits::total 3511 # number of WriteLineReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 126189 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 126189 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 9382628 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 9382628 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 9382628 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 9382628 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3117809 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 3117809 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1430430 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 1430430 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 707901 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 707901 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 462470 # number of WriteLineReq MSHR misses
> system.cpu1.dcache.WriteLineReq_mshr_misses::total 462470 # number of WriteLineReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120162 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120162 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195479 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 195479 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 5010709 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 5010709 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 5718610 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 5718610 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22964 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22964 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 21406 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 21406 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 44370 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 44370 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44191154500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44191154500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 27737660597 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 27737660597 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 17972389000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 17972389000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10263027957 # number of WriteLineReq MSHR miss cycles
> system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10263027957 # number of WriteLineReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1602495500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1602495500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4472798500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4472798500 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2757500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2757500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 82191843054 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 82191843054 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 100164232054 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 100164232054 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4057567500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4057567500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4057567500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4057567500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036247 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036247 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018744 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018744 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.790360 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.790360 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.738854 # mshr miss rate for WriteLineReq accesses
> system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.738854 # mshr miss rate for WriteLineReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.057931 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.057931 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096207 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096207 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030749 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.030749 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034901 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.034901 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14173.785020 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14173.785020 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19391.134552 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19391.134552 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 25388.280282 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 25388.280282 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22191.770184 # average WriteLineReq mshr miss latency
> system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22191.770184 # average WriteLineReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13336.125397 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13336.125397 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22881.222535 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22881.222535 # average StoreCondReq mshr miss latency
2451,2468c2456,2473
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16418.601874 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16418.601874 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17216.953136 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17216.953136 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152740.051854 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 152740.051854 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 77135.204372 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 77135.204372 # average overall mshr uncacheable latency
< system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.cpu1.icache.tags.replacements 5955489 # number of replacements
< system.cpu1.icache.tags.tagsinuse 501.186843 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 198342876 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 5956001 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 33.301350 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 8518419495000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.186843 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.978881 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.978881 # Average percentage of cache occupancy
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16403.236160 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16403.236160 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17515.485766 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17515.485766 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176692.540498 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176692.540498 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91448.444895 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91448.444895 # average overall mshr uncacheable latency
> system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.cpu1.icache.tags.replacements 6156366 # number of replacements
> system.cpu1.icache.tags.tagsinuse 501.025645 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 184011394 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 6156878 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 29.887127 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 8516343949500 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.025645 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.978566 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.978566 # Average percentage of cache occupancy
2470,2472c2475,2477
< system.cpu1.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id
2474,2532c2479,2537
< system.cpu1.icache.tags.tag_accesses 415232377 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 415232377 # Number of data accesses
< system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.cpu1.icache.ReadReq_hits::cpu1.inst 198342876 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 198342876 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 198342876 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 198342876 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 198342876 # number of overall hits
< system.cpu1.icache.overall_hits::total 198342876 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 6295293 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 6295293 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 6295293 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 6295293 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 6295293 # number of overall misses
< system.cpu1.icache.overall_misses::total 6295293 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 67919445914 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 67919445914 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 67919445914 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 67919445914 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 67919445914 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 67919445914 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 204638169 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 204638169 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 204638169 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 204638169 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 204638169 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 204638169 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030763 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.030763 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030763 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.030763 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030763 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.030763 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10788.925299 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 10788.925299 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10788.925299 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 10788.925299 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10788.925299 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 10788.925299 # average overall miss latency
< system.cpu1.icache.blocked_cycles::no_mshrs 9829448 # number of cycles access was blocked
< system.cpu1.icache.blocked_cycles::no_targets 701 # number of cycles access was blocked
< system.cpu1.icache.blocked::no_mshrs 729519 # number of cycles access was blocked
< system.cpu1.icache.blocked::no_targets 3 # number of cycles access was blocked
< system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.473875 # average number of cycles each access was blocked
< system.cpu1.icache.avg_blocked_cycles::no_targets 233.666667 # average number of cycles each access was blocked
< system.cpu1.icache.writebacks::writebacks 5955489 # number of writebacks
< system.cpu1.icache.writebacks::total 5955489 # number of writebacks
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 339254 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 339254 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 339254 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 339254 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 339254 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 339254 # number of overall MSHR hits
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5956039 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 5956039 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 5956039 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 5956039 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 5956039 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 5956039 # number of overall MSHR misses
---
> system.cpu1.icache.tags.tag_accesses 387206970 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 387206970 # Number of data accesses
> system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.cpu1.icache.ReadReq_hits::cpu1.inst 184011394 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 184011394 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 184011394 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 184011394 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 184011394 # number of overall hits
> system.cpu1.icache.overall_hits::total 184011394 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 6513585 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 6513585 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 6513585 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 6513585 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 6513585 # number of overall misses
> system.cpu1.icache.overall_misses::total 6513585 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 71534475691 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 71534475691 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 71534475691 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 71534475691 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 71534475691 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 71534475691 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 190524979 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 190524979 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 190524979 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 190524979 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 190524979 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 190524979 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.034188 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.034188 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.034188 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.034188 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.034188 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.034188 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10982.350839 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 10982.350839 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10982.350839 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 10982.350839 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10982.350839 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 10982.350839 # average overall miss latency
> system.cpu1.icache.blocked_cycles::no_mshrs 10659560 # number of cycles access was blocked
> system.cpu1.icache.blocked_cycles::no_targets 1026 # number of cycles access was blocked
> system.cpu1.icache.blocked::no_mshrs 770474 # number of cycles access was blocked
> system.cpu1.icache.blocked::no_targets 4 # number of cycles access was blocked
> system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.835068 # average number of cycles each access was blocked
> system.cpu1.icache.avg_blocked_cycles::no_targets 256.500000 # average number of cycles each access was blocked
> system.cpu1.icache.writebacks::writebacks 6156366 # number of writebacks
> system.cpu1.icache.writebacks::total 6156366 # number of writebacks
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 356573 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 356573 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 356573 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 356573 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 356573 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 356573 # number of overall MSHR hits
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 6157012 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 6157012 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 6157012 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 6157012 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 6157012 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 6157012 # number of overall MSHR misses
2537,2566c2542,2571
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 61337721519 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 61337721519 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 61337721519 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 61337721519 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 61337721519 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 61337721519 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6801498 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6801498 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6801498 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 6801498 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.029105 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.029105 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.029105 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.029105 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.029105 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.029105 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10298.408308 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10298.408308 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10298.408308 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 10298.408308 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10298.408308 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 10298.408308 # average overall mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101514.895522 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101514.895522 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101514.895522 # average overall mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101514.895522 # average overall mshr uncacheable latency
< system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.cpu1.l2cache.prefetcher.num_hwpf_issued 7017688 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.pfIdentified 7023313 # number of prefetch candidates identified
< system.cpu1.l2cache.prefetcher.pfBufferHit 5116 # number of redundant prefetches already in prefetch queue
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 64558641440 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 64558641440 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 64558641440 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 64558641440 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 64558641440 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 64558641440 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7017998 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7017998 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7017998 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 7017998 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.032316 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.032316 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.032316 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.032316 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.032316 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.032316 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10485.385028 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10485.385028 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10485.385028 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 10485.385028 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10485.385028 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 10485.385028 # average overall mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 104746.238806 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 104746.238806 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 104746.238806 # average overall mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 104746.238806 # average overall mshr uncacheable latency
> system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.cpu1.l2cache.prefetcher.num_hwpf_issued 7532579 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.pfIdentified 7540263 # number of prefetch candidates identified
> system.cpu1.l2cache.prefetcher.pfBufferHit 6914 # number of redundant prefetches already in prefetch queue
2569,2575c2574,2580
< system.cpu1.l2cache.prefetcher.pfSpanPage 831383 # number of prefetches not generated due to page crossing
< system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.cpu1.l2cache.tags.replacements 2042934 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 12933.505047 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 10254699 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 2058843 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 4.980807 # Average number of references to valid blocks.
---
> system.cpu1.l2cache.prefetcher.pfSpanPage 905745 # number of prefetches not generated due to page crossing
> system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.cpu1.l2cache.tags.replacements 2237289 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 12906.637296 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 10683229 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 2253034 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 4.741708 # Average number of references to valid blocks.
2577,2592c2582,2599
< system.cpu1.l2cache.tags.occ_blocks::writebacks 12624.033726 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 36.418354 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 27.691890 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 245.361077 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.770510 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002223 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001690 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014976 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.789399 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 293 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 63 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15553 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 116 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 99 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 69 # Occupied blocks per task id
---
> system.cpu1.l2cache.tags.occ_blocks::writebacks 12598.343747 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 34.232851 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 25.792432 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 248.268266 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.768942 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002089 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001574 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.015153 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.787759 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 360 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15324 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 6 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 163 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 96 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 79 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
2594,2729c2601,2734
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1807 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7301 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4524 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1724 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017883 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.949280 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 390440087 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 390440087 # Number of data accesses
< system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 557579 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 186161 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 743740 # number of ReadReq hits
< system.cpu1.l2cache.WritebackDirty_hits::writebacks 3343376 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackDirty_hits::total 3343376 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackClean_hits::writebacks 7851276 # number of WritebackClean hits
< system.cpu1.l2cache.WritebackClean_hits::total 7851276 # number of WritebackClean hits
< system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits
< system.cpu1.l2cache.UpgradeReq_hits::total 37 # number of UpgradeReq hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 859794 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 859794 # number of ReadExReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5412981 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::total 5412981 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2828036 # number of ReadSharedReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::total 2828036 # number of ReadSharedReq hits
< system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 191737 # number of InvalidateReq hits
< system.cpu1.l2cache.InvalidateReq_hits::total 191737 # number of InvalidateReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 557579 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 186161 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 5412981 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 3687830 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 9844551 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 557579 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 186161 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 5412981 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 3687830 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 9844551 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 21615 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9433 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 31048 # number of ReadReq misses
< system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses
< system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 224939 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 224939 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 183720 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 183720 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 255308 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 255308 # number of ReadExReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 543023 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::total 543023 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 939708 # number of ReadSharedReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::total 939708 # number of ReadSharedReq misses
< system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 256512 # number of InvalidateReq misses
< system.cpu1.l2cache.InvalidateReq_misses::total 256512 # number of InvalidateReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 21615 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9433 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 543023 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 1195016 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 1769087 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 21615 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9433 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 543023 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 1195016 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 1769087 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 686942500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 338389000 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 1025331500 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 939480500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 939480500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 264112000 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 264112000 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2448496 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2448496 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12203061000 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 12203061000 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 19608835500 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::total 19608835500 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 34743736987 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::total 34743736987 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 165000 # number of InvalidateReq miss cycles
< system.cpu1.l2cache.InvalidateReq_miss_latency::total 165000 # number of InvalidateReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 686942500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 338389000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 19608835500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 46946797987 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 67580964987 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 686942500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 338389000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 19608835500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 46946797987 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 67580964987 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 579194 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 195594 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 774788 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3343377 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::total 3343377 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::writebacks 7851276 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::total 7851276 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 224976 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 224976 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 183720 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 183720 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1115102 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 1115102 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5956004 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::total 5956004 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3767744 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::total 3767744 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 448249 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::total 448249 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 579194 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 195594 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 5956004 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 4882846 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 11613638 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 579194 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 195594 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 5956004 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 4882846 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 11613638 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.037319 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048227 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.040073 # miss rate for ReadReq accesses
< system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses
< system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999836 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999836 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
---
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 223 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2395 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7644 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2882 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2180 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.021973 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.935303 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 407515579 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 407515579 # Number of data accesses
> system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 593172 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 194279 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 787451 # number of ReadReq hits
> system.cpu1.l2cache.WritebackDirty_hits::writebacks 3518569 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackDirty_hits::total 3518569 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackClean_hits::writebacks 8164233 # number of WritebackClean hits
> system.cpu1.l2cache.WritebackClean_hits::total 8164233 # number of WritebackClean hits
> system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 105 # number of UpgradeReq hits
> system.cpu1.l2cache.UpgradeReq_hits::total 105 # number of UpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 954506 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 954506 # number of ReadExReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5573390 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::total 5573390 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2940198 # number of ReadSharedReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::total 2940198 # number of ReadSharedReq hits
> system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 209295 # number of InvalidateReq hits
> system.cpu1.l2cache.InvalidateReq_hits::total 209295 # number of InvalidateReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 593172 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 194279 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 5573390 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 3894704 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 10255545 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 593172 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 194279 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 5573390 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 3894704 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 10255545 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 23430 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10710 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 34140 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 228701 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 228701 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 195469 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 195469 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 9 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 254871 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 254871 # number of ReadExReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 583583 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::total 583583 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1000824 # number of ReadSharedReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::total 1000824 # number of ReadSharedReq misses
> system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 253175 # number of InvalidateReq misses
> system.cpu1.l2cache.InvalidateReq_misses::total 253175 # number of InvalidateReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 23430 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10710 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 583583 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 1255695 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 1873418 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 23430 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10710 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 583583 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 1255695 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 1873418 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 794453000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 411582000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 1206035000 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 885247000 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 885247000 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 309725000 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 309725000 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2651498 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2651498 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 13048454496 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 13048454496 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 21566356000 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::total 21566356000 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 38197437985 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::total 38197437985 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 1037000 # number of InvalidateReq miss cycles
> system.cpu1.l2cache.InvalidateReq_miss_latency::total 1037000 # number of InvalidateReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 794453000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 411582000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 21566356000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 51245892481 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 74018283481 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 794453000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 411582000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 21566356000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 51245892481 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 74018283481 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 616602 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 204989 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 821591 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3518569 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::total 3518569 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::writebacks 8164233 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::total 8164233 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 228806 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 228806 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195470 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 195470 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 9 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1209377 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 1209377 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 6156973 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::total 6156973 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3941022 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::total 3941022 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 462470 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::total 462470 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 616602 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 204989 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 6156973 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 5150399 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 12128963 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 616602 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 204989 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 6156973 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 5150399 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 12128963 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.037999 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.052247 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.041554 # miss rate for ReadReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999541 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999541 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999995 # miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999995 # miss rate for SCUpgradeReq accesses
2732,2777c2737,2782
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.228955 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.228955 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.091172 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.091172 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.249409 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.249409 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.572253 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.572253 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.037319 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048227 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.091172 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.244738 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.152328 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.037319 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048227 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.091172 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.244738 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.152328 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 31780.823502 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 35872.893035 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 33024.075625 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4176.601212 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4176.601212 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1437.578924 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1437.578924 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 408082.666667 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 408082.666667 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 47797.409404 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 47797.409404 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36110.506369 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36110.506369 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 36972.907528 # average ReadSharedReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 36972.907528 # average ReadSharedReq miss latency
< system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 0.643245 # average InvalidateReq miss latency
< system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 0.643245 # average InvalidateReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 31780.823502 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 35872.893035 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36110.506369 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 39285.497422 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 38201.040982 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 31780.823502 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 35872.893035 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36110.506369 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 39285.497422 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 38201.040982 # average overall miss latency
< system.cpu1.l2cache.blocked_cycles::no_mshrs 345 # number of cycles access was blocked
---
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.210746 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.210746 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.094784 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.094784 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.253950 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.253950 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.547441 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.547441 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.037999 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.052247 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.094784 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.243805 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.154458 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.037999 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.052247 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.094784 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.243805 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.154458 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 33907.511737 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 38429.691877 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 35326.157001 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 3870.761387 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 3870.761387 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1584.522354 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1584.522354 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 294610.888889 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 294610.888889 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51196.309098 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51196.309098 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36955.079226 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36955.079226 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 38165.989210 # average ReadSharedReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 38165.989210 # average ReadSharedReq miss latency
> system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 4.095981 # average InvalidateReq miss latency
> system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 4.095981 # average InvalidateReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 33907.511737 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 38429.691877 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36955.079226 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 40810.780071 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 39509.753553 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 33907.511737 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 38429.691877 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36955.079226 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40810.780071 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 39509.753553 # average overall miss latency
> system.cpu1.l2cache.blocked_cycles::no_mshrs 273 # number of cycles access was blocked
2779c2784
< system.cpu1.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked
---
> system.cpu1.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked
2781c2786
< system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 43.125000 # average number of cycles each access was blocked
---
> system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 45.500000 # average number of cycles each access was blocked
2783,2838c2788,2841
< system.cpu1.l2cache.unused_prefetches 42412 # number of HardPF blocks evicted w/o reference
< system.cpu1.l2cache.writebacks::writebacks 1137390 # number of writebacks
< system.cpu1.l2cache.writebacks::total 1137390 # number of writebacks
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 59 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 256 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::total 315 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 10963 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 10963 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits
< system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 3995 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 3995 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 3 # number of InvalidateReq MSHR hits
< system.cpu1.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 59 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 256 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 14958 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 15274 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 59 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 256 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 14958 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 15274 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 21556 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9177 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 30733 # number of ReadReq MSHR misses
< system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses
< system.cpu1.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 745312 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 745312 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 224939 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 224939 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 183720 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 183720 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 244345 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 244345 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 543022 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 543022 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 935713 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 935713 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 256509 # number of InvalidateReq MSHR misses
< system.cpu1.l2cache.InvalidateReq_mshr_misses::total 256509 # number of InvalidateReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 21556 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9177 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 543022 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1180058 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 1753813 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 21556 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9177 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 543022 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1180058 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 745312 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 2499125 # number of overall MSHR misses
---
> system.cpu1.l2cache.unused_prefetches 45092 # number of HardPF blocks evicted w/o reference
> system.cpu1.l2cache.writebacks::writebacks 1265703 # number of writebacks
> system.cpu1.l2cache.writebacks::total 1265703 # number of writebacks
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 89 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 277 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::total 366 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 14520 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 14520 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 6 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4370 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4370 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 4 # number of InvalidateReq MSHR hits
> system.cpu1.l2cache.InvalidateReq_mshr_hits::total 4 # number of InvalidateReq MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 89 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 277 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 18890 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 19262 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 89 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 277 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 18890 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 19262 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 23341 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10433 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 33774 # number of ReadReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 793498 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 793498 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 228701 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 228701 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 195469 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 195469 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 9 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 240351 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 240351 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 583577 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 583577 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 996454 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 996454 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 253171 # number of InvalidateReq MSHR misses
> system.cpu1.l2cache.InvalidateReq_mshr_misses::total 253171 # number of InvalidateReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 23341 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10433 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 583577 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1236805 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 1854156 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 23341 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10433 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 583577 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1236805 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 793498 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 2647654 # number of overall MSHR misses
2840,2843c2843,2846
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 8871 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 8938 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 8695 # number of WriteReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 8695 # number of WriteReq MSHR uncacheable
---
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 22964 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 23031 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 21406 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 21406 # number of WriteReq MSHR uncacheable
2845,2887c2848,2888
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 17566 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 17633 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 556465500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 279014500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 835480000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 36237678760 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 36237678760 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4227924487 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4227924487 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2815609497 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2815609497 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2082496 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2082496 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9065423000 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9065423000 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 16350690000 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 16350690000 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 28869020987 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 28869020987 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 5973751999 # number of InvalidateReq MSHR miss cycles
< system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 5973751999 # number of InvalidateReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 556465500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 279014500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 16350690000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 37934443987 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 55120613987 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 556465500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 279014500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16350690000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 37934443987 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 36237678760 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 91358292747 # number of overall MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6298000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1283792500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1290090500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6298000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1283792500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1290090500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.037217 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046919 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.039666 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses
< system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses
---
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 44370 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 44437 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 652898000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 343913500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 996811500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 46156066571 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 46156066571 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4295864494 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4295864494 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3003825995 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3003825995 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2231498 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2231498 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9417872000 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9417872000 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 18064709000 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 18064709000 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 31901371985 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 31901371985 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6217720498 # number of InvalidateReq MSHR miss cycles
> system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6217720498 # number of InvalidateReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 652898000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 343913500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 18064709000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 41319243985 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 60380764485 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 652898000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 343913500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 18064709000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 41319243985 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 46156066571 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 106536831056 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6514500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3873635500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3880150000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6514500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3873635500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3880150000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.037854 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050895 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041108 # mshr miss rate for ReadReq accesses
2890,2893c2891,2894
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999836 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999836 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
---
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999541 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999541 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999995 # mshr miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses
2896,2912c2897,2913
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.219123 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.219123 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.091172 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.091172 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.248348 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248348 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.572247 # mshr miss rate for InvalidateReq accesses
< system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.572247 # mshr miss rate for InvalidateReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.037217 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046919 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.091172 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.241674 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.151013 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.037217 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046919 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.091172 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.241674 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.198740 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.198740 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.094783 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.094783 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.252842 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.252842 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.547432 # mshr miss rate for InvalidateReq accesses
> system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.547432 # mshr miss rate for InvalidateReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.037854 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050895 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.094783 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.240138 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.152870 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.037854 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050895 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.094783 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.240138 # mshr miss rate for overall accesses
2914,2992c2915,2993
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.215189 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 25814.877528 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30403.672224 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 27185.110468 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48620.817537 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48620.817537 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18795.871267 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18795.871267 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15325.547012 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15325.547012 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 347082.666667 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 347082.666667 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37100.914690 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37100.914690 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30110.548007 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30110.548007 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 30852.431234 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30852.431234 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23288.664331 # average InvalidateReq mshr miss latency
< system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23288.664331 # average InvalidateReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 25814.877528 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30403.672224 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30110.548007 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32146.253817 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31429.014374 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 25814.877528 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30403.672224 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30110.548007 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32146.253817 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48620.817537 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36556.111738 # average overall mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94000 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 144717.901026 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 144337.715373 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94000 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 73083.940567 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 73163.415187 # average overall mshr uncacheable latency
< system.cpu1.toL2Bus.snoop_filter.tot_requests 23228623 # Total number of requests made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11943528 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 5072 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.snoop_filter.tot_snoops 598776 # Total number of snoops made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 598706 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 70 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.cpu1.toL2Bus.trans_dist::ReadReq 867379 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 10679013 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 8695 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 8695 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackDirty 4499349 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackClean 7854270 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::CleanEvict 1254191 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 938082 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 428069 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 332128 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 468300 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 113 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 1145370 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 1120388 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5956039 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4785637 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateReq 521245 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateResp 449809 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17867666 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16911297 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 409122 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1224107 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 36412192 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 762336624 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 654015560 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1564752 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4633552 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 1422550488 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 5059056 # Total snoops (count)
< system.cpu1.toL2Bus.snoopTraffic 80617704 # Total snoop traffic (bytes)
< system.cpu1.toL2Bus.snoop_fanout::samples 17392868 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 0.053991 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.226018 # Request fanout histogram
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.218292 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27972.152007 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 32964.008435 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 29514.167703 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58167.842352 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 58167.842352 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18783.759118 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18783.759118 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15367.275604 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15367.275604 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 247944.222222 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 247944.222222 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 39183.826986 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 39183.826986 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30955.142166 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30955.142166 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32014.896809 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32014.896809 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 24559.370931 # average InvalidateReq mshr miss latency
> system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 24559.370931 # average InvalidateReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27972.152007 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 32964.008435 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30955.142166 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 33408.050570 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32565.094029 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27972.152007 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 32964.008435 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30955.142166 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 33408.050570 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58167.842352 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 40238.199952 # average overall mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 97231.343284 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168682.960286 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 168475.098780 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 97231.343284 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87303.031327 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87318.000765 # average overall mshr uncacheable latency
> system.cpu1.toL2Bus.snoop_filter.tot_requests 24247915 # Total number of requests made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_requests 12479959 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 8015 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.snoop_filter.tot_snoops 603053 # Total number of snoops made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 602834 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 219 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.cpu1.toL2Bus.trans_dist::ReadReq 936644 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 11117136 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 21406 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 21406 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackDirty 4809330 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackClean 8167824 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::CleanEvict 1368728 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 1012133 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 404751 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 355876 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 480511 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 1238980 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 1214897 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadCleanReq 6157012 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4940216 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateReq 522762 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateResp 463422 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18470485 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17838362 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 429531 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1305673 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 38044051 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 788054768 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 689328153 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1639912 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4932816 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 1483955649 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 5334462 # Total snoops (count)
> system.cpu1.toL2Bus.snoopTraffic 88980784 # Total snoop traffic (bytes)
> system.cpu1.toL2Bus.snoop_fanout::samples 18249337 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 0.053626 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.225332 # Request fanout histogram
2994,2996c2995,2997
< system.cpu1.toL2Bus.snoop_fanout::0 16453876 94.60% 94.60% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::1 938922 5.40% 100.00% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::2 70 0.00% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::0 17270909 94.64% 94.64% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::1 978209 5.36% 100.00% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 219 0.00% 100.00% # Request fanout histogram
3000,3003c3001,3004
< system.cpu1.toL2Bus.snoop_fanout::total 17392868 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 23086793966 # Layer occupancy (ticks)
< system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
< system.cpu1.toL2Bus.snoopLayer0.occupancy 170580468 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 18249337 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 24116423481 # Layer occupancy (ticks)
> system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
> system.cpu1.toL2Bus.snoopLayer0.occupancy 160883108 # Layer occupancy (ticks)
3005c3006
< system.cpu1.toL2Bus.respLayer0.occupancy 8939751182 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 9241921761 # Layer occupancy (ticks)
3007c3008
< system.cpu1.toL2Bus.respLayer1.occupancy 7774836803 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 8211674528 # Layer occupancy (ticks)
3009c3010
< system.cpu1.toL2Bus.respLayer2.occupancy 213941664 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer2.occupancy 224968642 # Layer occupancy (ticks)
3011c3012
< system.cpu1.toL2Bus.respLayer3.occupancy 645834647 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 690043535 # Layer occupancy (ticks)
3013,3018c3014,3019
< system.iobus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.iobus.trans_dist::ReadReq 40408 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40408 # Transaction distribution
< system.iobus.trans_dist::WriteReq 136658 # Transaction distribution
< system.iobus.trans_dist::WriteResp 136658 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47776 # Packet count per connected master and slave (bytes)
---
> system.iobus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.iobus.trans_dist::ReadReq 40285 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40285 # Transaction distribution
> system.iobus.trans_dist::WriteReq 136579 # Transaction distribution
> system.iobus.trans_dist::WriteResp 136579 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47524 # Packet count per connected master and slave (bytes)
3029c3030
< system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
3031,3033c3032,3034
< system.iobus.pkt_count_system.bridge.master::total 122710 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231342 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 231342 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 122406 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231242 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 231242 # Packet count per connected master and slave (bytes)
3036,3037c3037,3038
< system.iobus.pkt_count::total 354132 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47796 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 353728 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47544 # Cumulative packet size per connected master and slave (bytes)
3048c3049
< system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
3050,3052c3051,3053
< system.iobus.pkt_size_system.bridge.master::total 155817 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339384 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7339384 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 155536 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338984 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7338984 # Cumulative packet size per connected master and slave (bytes)
3055,3056c3056,3057
< system.iobus.pkt_size::total 7497287 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 37041003 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 7496606 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 36861002 # Layer occupancy (ticks)
3058c3059
< system.iobus.reqLayer1.occupancy 9500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
3060c3061
< system.iobus.reqLayer2.occupancy 331500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks)
3062c3063
< system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks)
3072c3073
< system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks)
3074c3075
< system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks)
3076c3077
< system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks)
3078c3079
< system.iobus.reqLayer23.occupancy 24305002 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 24160506 # Layer occupancy (ticks)
3080c3081
< system.iobus.reqLayer24.occupancy 36394500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer24.occupancy 36392501 # Layer occupancy (ticks)
3082c3083
< system.iobus.reqLayer25.occupancy 570335330 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 570209840 # Layer occupancy (ticks)
3084c3085
< system.iobus.respLayer0.occupancy 92783000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 92558000 # Layer occupancy (ticks)
3086c3087
< system.iobus.respLayer3.occupancy 148038000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 147938000 # Layer occupancy (ticks)
3090,3092c3091,3093
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.iocache.tags.replacements 115667 # number of replacements
< system.iocache.tags.tagsinuse 11.289924 # Cycle average of tags in use
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.iocache.tags.replacements 115633 # number of replacements
> system.iocache.tags.tagsinuse 11.369333 # Cycle average of tags in use
3094c3095
< system.iocache.tags.sampled_refs 115683 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 115649 # Sample count of references to valid blocks.
3096,3101c3097,3102
< system.iocache.tags.warmup_cycle 9156457442000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ethernet 7.417343 # Average occupied blocks per requestor
< system.iocache.tags.occ_blocks::realview.ide 3.872581 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ethernet 0.463584 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::realview.ide 0.242036 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.705620 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 9154282048000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ethernet 7.419555 # Average occupied blocks per requestor
> system.iocache.tags.occ_blocks::realview.ide 3.949778 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ethernet 0.463722 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::realview.ide 0.246861 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.710583 # Average percentage of cache occupancy
3105,3107c3106,3108
< system.iocache.tags.tag_accesses 1041396 # Number of tag accesses
< system.iocache.tags.data_accesses 1041396 # Number of data accesses
< system.iocache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.tag_accesses 1040946 # Number of tag accesses
> system.iocache.tags.data_accesses 1040946 # Number of data accesses
> system.iocache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
3109,3110c3110,3111
< system.iocache.ReadReq_misses::realview.ide 8943 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8980 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8893 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8930 # number of ReadReq misses
3116,3117c3117,3118
< system.iocache.demand_misses::realview.ide 115671 # number of demand (read+write) misses
< system.iocache.demand_misses::total 115711 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 115621 # number of demand (read+write) misses
> system.iocache.demand_misses::total 115661 # number of demand (read+write) misses
3119,3133c3120,3134
< system.iocache.overall_misses::realview.ide 115671 # number of overall misses
< system.iocache.overall_misses::total 115711 # number of overall misses
< system.iocache.ReadReq_miss_latency::realview.ethernet 5200000 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::realview.ide 1878808543 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 1884008543 # number of ReadReq miss cycles
< system.iocache.WriteReq_miss_latency::realview.ethernet 370000 # number of WriteReq miss cycles
< system.iocache.WriteReq_miss_latency::total 370000 # number of WriteReq miss cycles
< system.iocache.WriteLineReq_miss_latency::realview.ide 13080956787 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 13080956787 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ethernet 5570000 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::realview.ide 14959765330 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 14965335330 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ethernet 5570000 # number of overall miss cycles
< system.iocache.overall_miss_latency::realview.ide 14959765330 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 14965335330 # number of overall miss cycles
---
> system.iocache.overall_misses::realview.ide 115621 # number of overall misses
> system.iocache.overall_misses::total 115661 # number of overall misses
> system.iocache.ReadReq_miss_latency::realview.ethernet 5192500 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::realview.ide 1787370736 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 1792563236 # number of ReadReq miss cycles
> system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
> system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
> system.iocache.WriteLineReq_miss_latency::realview.ide 12950575604 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 12950575604 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ethernet 5561500 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::realview.ide 14737946340 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 14743507840 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ethernet 5561500 # number of overall miss cycles
> system.iocache.overall_miss_latency::realview.ide 14737946340 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 14743507840 # number of overall miss cycles
3135,3136c3136,3137
< system.iocache.ReadReq_accesses::realview.ide 8943 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8980 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8893 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8930 # number of ReadReq accesses(hits+misses)
3142,3143c3143,3144
< system.iocache.demand_accesses::realview.ide 115671 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 115711 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 115621 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 115661 # number of demand (read+write) accesses
3145,3146c3146,3147
< system.iocache.overall_accesses::realview.ide 115671 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 115711 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 115621 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 115661 # number of overall (read+write) accesses
3160,3173c3161,3174
< system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::realview.ide 210087.056133 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 209800.505902 # average ReadReq miss latency
< system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123333.333333 # average WriteReq miss latency
< system.iocache.WriteReq_avg_miss_latency::total 123333.333333 # average WriteReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 122563.495868 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 122563.495868 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ethernet 139250 # average overall miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 129330.301718 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 129333.730847 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ethernet 139250 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 129330.301718 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 129333.730847 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 43850 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140337.837838 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::realview.ide 200986.251659 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 200734.964838 # average ReadReq miss latency
> system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
> system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121341.874710 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 121341.874710 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ethernet 139037.500000 # average overall miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 127467.729392 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 127471.730661 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ethernet 139037.500000 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 127467.729392 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 127471.730661 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 39227 # number of cycles access was blocked
3175c3176
< system.iocache.blocked::no_mshrs 3467 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3536 # number of cycles access was blocked
3177c3178
< system.iocache.avg_blocked_cycles::no_mshrs 12.647822 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 11.093609 # average number of cycles each access was blocked
3179,3180c3180,3181
< system.iocache.writebacks::writebacks 106694 # number of writebacks
< system.iocache.writebacks::total 106694 # number of writebacks
---
> system.iocache.writebacks::writebacks 106710 # number of writebacks
> system.iocache.writebacks::total 106710 # number of writebacks
3182,3183c3183,3184
< system.iocache.ReadReq_mshr_misses::realview.ide 8943 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 8980 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 8893 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 8930 # number of ReadReq MSHR misses
3189,3190c3190,3191
< system.iocache.demand_mshr_misses::realview.ide 115671 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 115711 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 115621 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 115661 # number of demand (read+write) MSHR misses
3192,3206c3193,3207
< system.iocache.overall_mshr_misses::realview.ide 115671 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 115711 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3350000 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 1431658543 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 1435008543 # number of ReadReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 220000 # number of WriteReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::total 220000 # number of WriteReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7738901569 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 7738901569 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ethernet 3570000 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 9170560112 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 9174130112 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ethernet 3570000 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 9170560112 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 9174130112 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_misses::realview.ide 115621 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 115661 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3342500 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 1342720736 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 1346063236 # number of ReadReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7608008190 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 7608008190 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ethernet 3561500 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 8950728926 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 8954290426 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ethernet 3561500 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 8950728926 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 8954290426 # number of overall MSHR miss cycles
3220,3552c3221,3552
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 160087.056133 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 159800.505902 # average ReadReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73333.333333 # average WriteReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::total 73333.333333 # average WriteReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 72510.508667 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 72510.508667 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89250 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 79281.411175 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 79284.857205 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89250 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 79281.411175 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 79284.857205 # average overall mshr miss latency
< system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.l2c.tags.replacements 1625787 # number of replacements
< system.l2c.tags.tagsinuse 65181.204595 # Cycle average of tags in use
< system.l2c.tags.total_refs 6817657 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 1687923 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 4.039081 # Average number of references to valid blocks.
< system.l2c.tags.warmup_cycle 3083223500 # Cycle when the warmup percentage was hit.
< system.l2c.tags.occ_blocks::writebacks 9617.868100 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 445.484302 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 525.919749 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 4087.647415 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 22210.879235 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 20823.279726 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 29.752566 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 32.095436 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 2691.005366 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 3224.848807 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1492.423894 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.146757 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.006798 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.008025 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.062373 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.338911 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.317738 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000454 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.itb.walker 0.000490 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.041061 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.049207 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022773 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.994586 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 12119 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 287 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 49730 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 1349 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 918 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 9840 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 283 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 2201 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 4435 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 42789 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.184921 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.004379 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.758820 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 77430161 # Number of tag accesses
< system.l2c.tags.data_accesses 77430161 # Number of data accesses
< system.l2c.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.l2c.WritebackDirty_hits::writebacks 2884653 # number of WritebackDirty hits
< system.l2c.WritebackDirty_hits::total 2884653 # number of WritebackDirty hits
< system.l2c.UpgradeReq_hits::cpu0.data 199415 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 166641 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 366056 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 54285 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 48308 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 102593 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 52113 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 55927 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 108040 # number of ReadExReq hits
< system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 12524 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4903 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.inst 523305 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 612159 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 287889 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 14056 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5296 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.inst 496370 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 569933 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 304905 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 2831340 # number of ReadSharedReq hits
< system.l2c.InvalidateReq_hits::cpu0.data 116676 # number of InvalidateReq hits
< system.l2c.InvalidateReq_hits::cpu1.data 127973 # number of InvalidateReq hits
< system.l2c.InvalidateReq_hits::total 244649 # number of InvalidateReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 12524 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 4903 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 523305 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 664272 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 287889 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 14056 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 5296 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 496370 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 625860 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 304905 # number of demand (read+write) hits
< system.l2c.demand_hits::total 2939380 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 12524 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 4903 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 523305 # number of overall hits
< system.l2c.overall_hits::cpu0.data 664272 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 287889 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 14056 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 5296 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 496370 # number of overall hits
< system.l2c.overall_hits::cpu1.data 625860 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 304905 # number of overall hits
< system.l2c.overall_hits::total 2939380 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 23367 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 23265 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 46632 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 687 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 824 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 1511 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 90180 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 49097 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 139277 # number of ReadExReq misses
< system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3479 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3368 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.inst 64819 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 175048 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 338569 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1814 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1250 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.inst 46649 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 114016 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 201392 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 950404 # number of ReadSharedReq misses
< system.l2c.InvalidateReq_misses::cpu0.data 450671 # number of InvalidateReq misses
< system.l2c.InvalidateReq_misses::cpu1.data 82488 # number of InvalidateReq misses
< system.l2c.InvalidateReq_misses::total 533159 # number of InvalidateReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 3479 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.itb.walker 3368 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.inst 64819 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 265228 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 338569 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 1814 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.itb.walker 1250 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 46649 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 163113 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 201392 # number of demand (read+write) misses
< system.l2c.demand_misses::total 1089681 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 3479 # number of overall misses
< system.l2c.overall_misses::cpu0.itb.walker 3368 # number of overall misses
< system.l2c.overall_misses::cpu0.inst 64819 # number of overall misses
< system.l2c.overall_misses::cpu0.data 265228 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 338569 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 1814 # number of overall misses
< system.l2c.overall_misses::cpu1.itb.walker 1250 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 46649 # number of overall misses
< system.l2c.overall_misses::cpu1.data 163113 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 201392 # number of overall misses
< system.l2c.overall_misses::total 1089681 # number of overall misses
< system.l2c.UpgradeReq_miss_latency::cpu0.data 136803000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 150683000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 287486000 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 9622000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 7084500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 16706500 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 9842771994 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 5304657999 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 15147429993 # number of ReadExReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 352314500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 351549500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.inst 7169242500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 19597785998 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 51686460606 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 196164500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 138775500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5424777500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.data 13175715998 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 30642096870 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::total 128734883472 # number of ReadSharedReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 352314500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 351549500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 7169242500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 29440557992 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 51686460606 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 196164500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.itb.walker 138775500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 5424777500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 18480373997 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 30642096870 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 143882313465 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 352314500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 351549500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 7169242500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 29440557992 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 51686460606 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 196164500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.itb.walker 138775500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 5424777500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 18480373997 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 30642096870 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 143882313465 # number of overall miss cycles
< system.l2c.WritebackDirty_accesses::writebacks 2884653 # number of WritebackDirty accesses(hits+misses)
< system.l2c.WritebackDirty_accesses::total 2884653 # number of WritebackDirty accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 222782 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 189906 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 412688 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 54972 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 49132 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 104104 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 142293 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 105024 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 247317 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 16003 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 8271 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.inst 588124 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 787207 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 626458 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 15870 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6546 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.inst 543019 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 683949 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 506297 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 3781744 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.InvalidateReq_accesses::cpu0.data 567347 # number of InvalidateReq accesses(hits+misses)
< system.l2c.InvalidateReq_accesses::cpu1.data 210461 # number of InvalidateReq accesses(hits+misses)
< system.l2c.InvalidateReq_accesses::total 777808 # number of InvalidateReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 16003 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 8271 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 588124 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 929500 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 626458 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 15870 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 6546 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 543019 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 788973 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 506297 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 4029061 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 16003 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 8271 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 588124 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 929500 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 626458 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 15870 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 6546 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 543019 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 788973 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 506297 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 4029061 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.104887 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.122508 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.112996 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.012497 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.016771 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.014514 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.633763 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.467484 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.563152 # miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.217397 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.407206 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.110213 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.222366 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.540450 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.114304 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.190956 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.085907 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.166702 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.397774 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.251314 # miss rate for ReadSharedReq accesses
< system.l2c.InvalidateReq_miss_rate::cpu0.data 0.794348 # miss rate for InvalidateReq accesses
< system.l2c.InvalidateReq_miss_rate::cpu1.data 0.391940 # miss rate for InvalidateReq accesses
< system.l2c.InvalidateReq_miss_rate::total 0.685464 # miss rate for InvalidateReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.217397 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.407206 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.110213 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.285345 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.540450 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.114304 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.190956 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.085907 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.206741 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.397774 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.270455 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.217397 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.407206 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.110213 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.285345 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.540450 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.114304 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.190956 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.085907 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.206741 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.397774 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.270455 # miss rate for overall accesses
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5854.538452 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6476.810660 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 6164.993996 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14005.822416 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 8597.694175 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 11056.585043 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 109145.841583 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108044.442614 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 108757.583758 # average ReadExReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 101268.899109 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 104379.305226 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 110604.028140 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 111956.640453 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 152661.527210 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 108139.195149 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 111020.400000 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 116289.255933 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 115560.237142 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 152151.509842 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::total 135452.800569 # average ReadSharedReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 101268.899109 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 104379.305226 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 110604.028140 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 111000.942555 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 152661.527210 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 108139.195149 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.itb.walker 111020.400000 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 116289.255933 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 113297.983588 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 152151.509842 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 132040.765568 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 101268.899109 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 104379.305226 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 110604.028140 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 111000.942555 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 152661.527210 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 108139.195149 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.itb.walker 111020.400000 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 116289.255933 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 113297.983588 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 152151.509842 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 132040.765568 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 7046 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90337.837838 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 150986.251659 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 150734.964838 # average ReadReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71284.088430 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71284.088430 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89037.500000 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 77414.387750 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 77418.407467 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89037.500000 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 77414.387750 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 77418.407467 # average overall mshr miss latency
> system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.l2c.tags.replacements 1858608 # number of replacements
> system.l2c.tags.tagsinuse 65222.891140 # Cycle average of tags in use
> system.l2c.tags.total_refs 7355255 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 1920213 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 3.830437 # Average number of references to valid blocks.
> system.l2c.tags.warmup_cycle 1229429500 # Cycle when the warmup percentage was hit.
> system.l2c.tags.occ_blocks::writebacks 10209.698759 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 401.592309 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 445.016269 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 3734.616961 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 21322.764244 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 18260.159461 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 76.119212 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.itb.walker 86.745152 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 3160.425498 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 4267.065632 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3258.687641 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.155788 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.006128 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.006790 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.056986 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.325360 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.278628 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001161 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.itb.walker 0.001324 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.048224 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.065110 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.049724 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.995222 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 11759 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 304 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 49542 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 196 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 891 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 10670 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::1 12 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 292 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 367 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 2478 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 2877 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 43809 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.179428 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.004639 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.755951 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 84121444 # Number of tag accesses
> system.l2c.tags.data_accesses 84121444 # Number of data accesses
> system.l2c.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.l2c.WritebackDirty_hits::writebacks 3161961 # number of WritebackDirty hits
> system.l2c.WritebackDirty_hits::total 3161961 # number of WritebackDirty hits
> system.l2c.UpgradeReq_hits::cpu0.data 218473 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 178227 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 396700 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 60416 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 50161 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 110577 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 54320 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 59150 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 113470 # number of ReadExReq hits
> system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 13417 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5017 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.inst 539007 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 668528 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 293105 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 15148 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.itb.walker 6130 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.inst 525725 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 626529 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 298432 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 2991038 # number of ReadSharedReq hits
> system.l2c.InvalidateReq_hits::cpu0.data 122623 # number of InvalidateReq hits
> system.l2c.InvalidateReq_hits::cpu1.data 121091 # number of InvalidateReq hits
> system.l2c.InvalidateReq_hits::total 243714 # number of InvalidateReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 13417 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 5017 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 539007 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 722848 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 293105 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 15148 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 6130 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 525725 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 685679 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 298432 # number of demand (read+write) hits
> system.l2c.demand_hits::total 3104508 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 13417 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 5017 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 539007 # number of overall hits
> system.l2c.overall_hits::cpu0.data 722848 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 293105 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 15148 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 6130 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 525725 # number of overall hits
> system.l2c.overall_hits::cpu1.data 685679 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 298432 # number of overall hits
> system.l2c.overall_hits::total 3104508 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 21614 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 22773 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 44387 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 1033 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 1052 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 2085 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 96389 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 53149 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 149538 # number of ReadExReq misses
> system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3784 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3652 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.inst 65121 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 199292 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 394602 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2497 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1730 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.inst 57847 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 128371 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 264210 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 1121106 # number of ReadSharedReq misses
> system.l2c.InvalidateReq_misses::cpu0.data 461443 # number of InvalidateReq misses
> system.l2c.InvalidateReq_misses::cpu1.data 96191 # number of InvalidateReq misses
> system.l2c.InvalidateReq_misses::total 557634 # number of InvalidateReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 3784 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.itb.walker 3652 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.inst 65121 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 295681 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 394602 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 2497 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.itb.walker 1730 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 57847 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 181520 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 264210 # number of demand (read+write) misses
> system.l2c.demand_misses::total 1270644 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 3784 # number of overall misses
> system.l2c.overall_misses::cpu0.itb.walker 3652 # number of overall misses
> system.l2c.overall_misses::cpu0.inst 65121 # number of overall misses
> system.l2c.overall_misses::cpu0.data 295681 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 394602 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 2497 # number of overall misses
> system.l2c.overall_misses::cpu1.itb.walker 1730 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 57847 # number of overall misses
> system.l2c.overall_misses::cpu1.data 181520 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 264210 # number of overall misses
> system.l2c.overall_misses::total 1270644 # number of overall misses
> system.l2c.UpgradeReq_miss_latency::cpu0.data 151083000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 144162500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 295245500 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 9029500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 10650000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 19679500 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 10395447993 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 5744671997 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 16140119990 # number of ReadExReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 381693500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 359292500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.inst 7105700999 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 21857572496 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 60806343315 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 266793000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 185648500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6445588500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.data 15192688491 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 40621267426 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::total 153222588727 # number of ReadSharedReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 381693500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 359292500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 7105700999 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 32253020489 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 60806343315 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 266793000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.itb.walker 185648500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 6445588500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 20937360488 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 40621267426 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 169362708717 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 381693500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 359292500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 7105700999 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 32253020489 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 60806343315 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 266793000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.itb.walker 185648500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 6445588500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 20937360488 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 40621267426 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 169362708717 # number of overall miss cycles
> system.l2c.WritebackDirty_accesses::writebacks 3161961 # number of WritebackDirty accesses(hits+misses)
> system.l2c.WritebackDirty_accesses::total 3161961 # number of WritebackDirty accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 240087 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 201000 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 441087 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 61449 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 51213 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 112662 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 150709 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 112299 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 263008 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 17201 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 8669 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.inst 604128 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 867820 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 687707 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 17645 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7860 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.inst 583572 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 754900 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 562642 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 4112144 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.InvalidateReq_accesses::cpu0.data 584066 # number of InvalidateReq accesses(hits+misses)
> system.l2c.InvalidateReq_accesses::cpu1.data 217282 # number of InvalidateReq accesses(hits+misses)
> system.l2c.InvalidateReq_accesses::total 801348 # number of InvalidateReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 17201 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 8669 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 604128 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 1018529 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 687707 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 17645 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 7860 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 583572 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 867199 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 562642 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 4375152 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 17201 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 8669 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 604128 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 1018529 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 687707 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 17645 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 7860 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 583572 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 867199 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 562642 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 4375152 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.090026 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.113299 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.100631 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.016811 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.020542 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.018507 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.639570 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.473281 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.568568 # miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.219987 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.421271 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.107793 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.229647 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.573794 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.141513 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.220102 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.099126 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.170050 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.469588 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.272633 # miss rate for ReadSharedReq accesses
> system.l2c.InvalidateReq_miss_rate::cpu0.data 0.790053 # miss rate for InvalidateReq accesses
> system.l2c.InvalidateReq_miss_rate::cpu1.data 0.442701 # miss rate for InvalidateReq accesses
> system.l2c.InvalidateReq_miss_rate::total 0.695870 # miss rate for InvalidateReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.219987 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.421271 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.107793 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.290302 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.573794 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.141513 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.220102 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.099126 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.209318 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.469588 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.290423 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.219987 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.421271 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.107793 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.290302 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.573794 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.141513 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.220102 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.099126 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.209318 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.469588 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.290423 # miss rate for overall accesses
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6990.052744 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6330.413209 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 6651.620970 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 8741.045499 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 10123.574144 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 9438.609113 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 107848.903848 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108086.172778 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 107933.234295 # average ReadExReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 100870.375264 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 98382.393209 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109115.354479 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 109676.115930 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 154095.375378 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 106845.414497 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 107311.271676 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 111424.767058 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 118349.849195 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 153746.139154 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::total 136670.920258 # average ReadSharedReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100870.375264 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 98382.393209 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 109115.354479 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 109080.463368 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 154095.375378 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 106845.414497 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.itb.walker 107311.271676 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 111424.767058 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 115344.647907 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 153746.139154 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 133288.874553 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100870.375264 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 98382.393209 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 109115.354479 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 109080.463368 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 154095.375378 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 106845.414497 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.itb.walker 107311.271676 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 111424.767058 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 115344.647907 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 153746.139154 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 133288.874553 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 15677 # number of cycles access was blocked
3554c3554
< system.l2c.blocked::no_mshrs 62 # number of cycles access was blocked
---
> system.l2c.blocked::no_mshrs 153 # number of cycles access was blocked
3556c3556
< system.l2c.avg_blocked_cycles::no_mshrs 113.645161 # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs 102.464052 # average number of cycles each access was blocked
3558,3623c3558,3626
< system.l2c.writebacks::writebacks 1244548 # number of writebacks
< system.l2c.writebacks::total 1244548 # number of writebacks
< system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 102 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu0.data 15 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 118 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.data 19 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::total 254 # number of ReadSharedReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 102 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu0.data 15 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 118 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.data 19 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 102 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu0.data 15 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 118 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.data 19 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 254 # number of overall MSHR hits
< system.l2c.CleanEvict_mshr_misses::writebacks 67228 # number of CleanEvict MSHR misses
< system.l2c.CleanEvict_mshr_misses::total 67228 # number of CleanEvict MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 23367 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 23265 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 46632 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 687 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 824 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 1511 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 90180 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 49097 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 139277 # number of ReadExReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 3479 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3368 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 64717 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.data 175033 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 338569 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1814 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1250 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 46531 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.data 113997 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 201392 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::total 950150 # number of ReadSharedReq MSHR misses
< system.l2c.InvalidateReq_mshr_misses::cpu0.data 450671 # number of InvalidateReq MSHR misses
< system.l2c.InvalidateReq_mshr_misses::cpu1.data 82488 # number of InvalidateReq MSHR misses
< system.l2c.InvalidateReq_mshr_misses::total 533159 # number of InvalidateReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 3479 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.itb.walker 3368 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 64717 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 265213 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 338569 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 1814 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.itb.walker 1250 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 46531 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 163094 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 201392 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 1089427 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 3479 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.itb.walker 3368 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 64717 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 265213 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 338569 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 1814 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.itb.walker 1250 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 46531 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 163094 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 201392 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 1089427 # number of overall MSHR misses
< system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::cpu0.data 29615 # number of ReadReq MSHR uncacheable
---
> system.l2c.writebacks::writebacks 1420191 # number of writebacks
> system.l2c.writebacks::total 1420191 # number of writebacks
> system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 100 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu0.data 8 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 184 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.data 35 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::total 328 # number of ReadSharedReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 100 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu0.data 8 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 184 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.data 35 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 100 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu0.data 8 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 1 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 184 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.data 35 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 328 # number of overall MSHR hits
> system.l2c.CleanEvict_mshr_misses::writebacks 84488 # number of CleanEvict MSHR misses
> system.l2c.CleanEvict_mshr_misses::total 84488 # number of CleanEvict MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 21614 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 22773 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 44387 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1033 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1052 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 2085 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 96389 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 53149 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 149538 # number of ReadExReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 3784 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3652 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 65021 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.data 199284 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 394601 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2497 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1730 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 57663 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.data 128336 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 264210 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::total 1120778 # number of ReadSharedReq MSHR misses
> system.l2c.InvalidateReq_mshr_misses::cpu0.data 461443 # number of InvalidateReq MSHR misses
> system.l2c.InvalidateReq_mshr_misses::cpu1.data 96191 # number of InvalidateReq MSHR misses
> system.l2c.InvalidateReq_mshr_misses::total 557634 # number of InvalidateReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 3784 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.itb.walker 3652 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 65021 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 295673 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 394601 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 2497 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.itb.walker 1730 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 57663 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 181485 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 264210 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 1270316 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 3784 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.itb.walker 3652 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 65021 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 295673 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 394601 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 2497 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.itb.walker 1730 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 57663 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 181485 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 264210 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 1270316 # number of overall MSHR misses
> system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 2093 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 15843 # number of ReadReq MSHR uncacheable
3625,3631c3628,3634
< system.l2c.ReadReq_mshr_uncacheable::cpu1.data 8869 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::total 59844 # number of ReadReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu0.data 29691 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu1.data 8695 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::total 38386 # number of WriteReq MSHR uncacheable
< system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::cpu0.data 59306 # number of overall MSHR uncacheable misses
---
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 22962 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 40965 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 17283 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 21406 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 38689 # number of WriteReq MSHR uncacheable
> system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 2093 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 33126 # number of overall MSHR uncacheable misses
3633,3689c3636,3692
< system.l2c.overall_mshr_uncacheable_misses::cpu1.data 17564 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::total 98230 # number of overall MSHR uncacheable misses
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 466632500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 483108499 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 949740999 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16616499 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20367500 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 36983999 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8940824795 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4813505389 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 13754330184 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 317523502 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 317869500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6512407062 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17845292687 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 48300635417 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 178023502 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 126275001 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4948966536 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 12033347692 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 28627972330 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::total 119208313229 # number of ReadSharedReq MSHR miss cycles
< system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 11145696799 # number of InvalidateReq MSHR miss cycles
< system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1615953000 # number of InvalidateReq MSHR miss cycles
< system.l2c.InvalidateReq_mshr_miss_latency::total 12761649799 # number of InvalidateReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 317523502 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 317869500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 6512407062 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 26786117482 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 48300635417 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 178023502 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 126275001 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 4948966536 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 16846853081 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 28627972330 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 132962643413 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 317523502 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 317869500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 6512407062 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 26786117482 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 48300635417 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 178023502 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 126275001 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 4948966536 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 16846853081 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 28627972330 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 132962643413 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1484185500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4824158502 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5090000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1123983502 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 7437417504 # number of ReadReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1484185500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4824158502 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5090000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1123983502 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 7437417504 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 44368 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 79654 # number of overall MSHR uncacheable misses
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 437927500 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 473487498 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 911414998 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 24955000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 25870500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 50825500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 9431397842 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5212978417 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 14644376259 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 343853001 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 322772001 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6445445567 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19863990276 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 56859943438 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 241821503 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 168348500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5850563554 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 13904670289 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 37978912479 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::total 141980320608 # number of ReadSharedReq MSHR miss cycles
> system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 11387571771 # number of InvalidateReq MSHR miss cycles
> system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1886134001 # number of InvalidateReq MSHR miss cycles
> system.l2c.InvalidateReq_mshr_miss_latency::total 13273705772 # number of InvalidateReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 343853001 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 322772001 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 6445445567 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 29295388118 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 56859943438 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 241821503 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 168348500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 5850563554 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 19117648706 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 37978912479 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 156624696867 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 343853001 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 322772001 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 6445445567 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 29295388118 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 56859943438 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 241821503 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 168348500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 5850563554 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 19117648706 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 37978912479 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 156624696867 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 147855500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2484594002 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5308000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3460097504 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 6097855006 # number of ReadReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 147855500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2484594002 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5308000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3460097504 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 6097855006 # number of overall MSHR uncacheable cycles
3692,3794c3695,3797
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.104887 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.122508 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.112996 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.012497 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016771 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.014514 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.633763 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.467484 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.563152 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.217397 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.407206 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.110040 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.222347 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.540450 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.114304 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.190956 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.085689 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.166675 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.397774 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::total 0.251247 # mshr miss rate for ReadSharedReq accesses
< system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.794348 # mshr miss rate for InvalidateReq accesses
< system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.391940 # mshr miss rate for InvalidateReq accesses
< system.l2c.InvalidateReq_mshr_miss_rate::total 0.685464 # mshr miss rate for InvalidateReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.217397 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.407206 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.110040 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.285329 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.540450 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.114304 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.190956 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.085689 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.206717 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.397774 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.270392 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.217397 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.407206 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.110040 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.285329 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.540450 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.114304 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.190956 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.085689 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.206717 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.397774 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.270392 # mshr miss rate for overall accesses
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19969.722258 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20765.463099 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20366.722401 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24187.043668 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24717.839806 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24476.504964 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 99144.209304 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98040.723242 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 98755.215750 # average ReadExReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 91268.612245 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 94379.305226 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 100629.001066 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101953.875481 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142661.127915 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 98138.644983 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 101020.000800 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 106358.482216 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 105558.459363 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142150.494210 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 125462.625090 # average ReadSharedReq mshr miss latency
< system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24731.337936 # average InvalidateReq mshr miss latency
< system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19590.158569 # average InvalidateReq mshr miss latency
< system.l2c.InvalidateReq_avg_mshr_miss_latency::total 23935.917426 # average InvalidateReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 91268.612245 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 94379.305226 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 100629.001066 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 100998.508678 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142661.127915 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 98138.644983 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 101020.000800 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 106358.482216 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 103295.357775 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142150.494210 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 122048.235828 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 91268.612245 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 94379.305226 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 100629.001066 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 100998.508678 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142661.127915 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 98138.644983 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 101020.000800 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 106358.482216 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 103295.357775 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142150.494210 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 122048.235828 # average overall mshr miss latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162895.779233 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75970.149254 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 126731.706168 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 124280.086625 # average ReadReq mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 81343.515024 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 75970.149254 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 63993.594967 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 75714.318477 # average overall mshr uncacheable latency
< system.membus.snoop_filter.tot_requests 4039865 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 2364937 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.membus.snoop_filter.hit_multi_requests 3552 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.090026 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.113299 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.100631 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.016811 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.020542 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.018507 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.639570 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.473281 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.568568 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.219987 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.421271 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.107628 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.229637 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.573792 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.141513 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.220102 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.098810 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.170004 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.469588 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::total 0.272553 # mshr miss rate for ReadSharedReq accesses
> system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.790053 # mshr miss rate for InvalidateReq accesses
> system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.442701 # mshr miss rate for InvalidateReq accesses
> system.l2c.InvalidateReq_mshr_miss_rate::total 0.695870 # mshr miss rate for InvalidateReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.219987 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.421271 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.107628 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.290294 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.573792 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.141513 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.220102 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.098810 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.209277 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.469588 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.290348 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.219987 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.421271 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.107628 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.290294 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.573792 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.141513 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.220102 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.098810 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.209277 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.469588 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.290348 # mshr miss rate for overall accesses
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20261.288979 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20791.617178 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20533.376845 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24157.792836 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24591.730038 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24376.738609 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 97847.242341 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98082.342415 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 97930.801930 # average ReadExReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90870.243393 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 88382.256572 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99128.674844 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 99676.794304 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 144094.777859 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 96844.814978 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 97311.271676 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 101461.310615 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 108345.828832 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143745.174214 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126680.145941 # average ReadSharedReq mshr miss latency
> system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24678.176440 # average InvalidateReq mshr miss latency
> system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19608.216995 # average InvalidateReq mshr miss latency
> system.l2c.InvalidateReq_avg_mshr_miss_latency::total 23803.616300 # average InvalidateReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90870.243393 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 88382.256572 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99128.674844 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99080.362827 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 144094.777859 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 96844.814978 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 97311.271676 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 101461.310615 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 105340.103623 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143745.174214 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 123295.854628 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90870.243393 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 88382.256572 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99128.674844 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99080.362827 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 144094.777859 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 96844.814978 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 97311.271676 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 101461.310615 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 105340.103623 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143745.174214 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 123295.854628 # average overall mshr miss latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70642.857143 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156825.980054 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 79223.880597 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150687.984670 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 148855.242426 # average ReadReq mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70642.857143 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 75004.347099 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 79223.880597 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77986.330328 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 76554.284857 # average overall mshr uncacheable latency
> system.membus.snoop_filter.tot_requests 4427188 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 2544778 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 3484 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3798,3814c3801,3817
< system.membus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadReq 59844 # Transaction distribution
< system.membus.trans_dist::ReadResp 1018974 # Transaction distribution
< system.membus.trans_dist::WriteReq 38386 # Transaction distribution
< system.membus.trans_dist::WriteResp 38386 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 1351242 # Transaction distribution
< system.membus.trans_dist::CleanEvict 267627 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 336754 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 267840 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 23 # Transaction distribution
< system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
< system.membus.trans_dist::ReadExReq 152823 # Transaction distribution
< system.membus.trans_dist::ReadExResp 138565 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 959130 # Transaction distribution
< system.membus.trans_dist::InvalidateReq 652932 # Transaction distribution
< system.membus.trans_dist::InvalidateResp 30629 # Transaction distribution
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122710 # Packet count per connected master and slave (bytes)
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadReq 40965 # Transaction distribution
> system.membus.trans_dist::ReadResp 1170673 # Transaction distribution
> system.membus.trans_dist::WriteReq 38689 # Transaction distribution
> system.membus.trans_dist::WriteResp 38689 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 1526901 # Transaction distribution
> system.membus.trans_dist::CleanEvict 301973 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 291943 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 287508 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 8 # Transaction distribution
> system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
> system.membus.trans_dist::ReadExReq 162891 # Transaction distribution
> system.membus.trans_dist::ReadExResp 148894 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 1129708 # Transaction distribution
> system.membus.trans_dist::InvalidateReq 674487 # Transaction distribution
> system.membus.trans_dist::InvalidateResp 26345 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122406 # Packet count per connected master and slave (bytes)
3816,3822c3819,3825
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25810 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4892821 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 5041417 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237968 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 237968 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 5279385 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155817 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27362 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5422541 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 5572385 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238081 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 238081 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 5810466 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155536 # Cumulative packet size per connected master and slave (bytes)
3824,3834c3827,3837
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51620 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 149644096 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 149852089 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7250176 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 7250176 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 157102265 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 616817 # Total snoops (count)
< system.membus.snoopTraffic 199808 # Total snoop traffic (bytes)
< system.membus.snoop_fanout::samples 2467715 # Request fanout histogram
< system.membus.snoop_fanout::mean 0.013862 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0.116919 # Request fanout histogram
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54724 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 172160384 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 172371200 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7263808 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 7263808 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 179635008 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 585668 # Total snoops (count)
> system.membus.snoopTraffic 182912 # Total snoop traffic (bytes)
> system.membus.snoop_fanout::samples 2626196 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.011361 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.105982 # Request fanout histogram
3836,3837c3839,3840
< system.membus.snoop_fanout::0 2433507 98.61% 98.61% # Request fanout histogram
< system.membus.snoop_fanout::1 34208 1.39% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 2596359 98.86% 98.86% # Request fanout histogram
> system.membus.snoop_fanout::1 29837 1.14% 100.00% # Request fanout histogram
3842,3843c3845,3846
< system.membus.snoop_fanout::total 2467715 # Request fanout histogram
< system.membus.reqLayer0.occupancy 98169995 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 2626196 # Request fanout histogram
> system.membus.reqLayer0.occupancy 97843991 # Layer occupancy (ticks)
3847c3850
< system.membus.reqLayer2.occupancy 21686998 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 22899493 # Layer occupancy (ticks)
3849c3852
< system.membus.reqLayer5.occupancy 9247698101 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 10387724889 # Layer occupancy (ticks)
3851c3854
< system.membus.respLayer2.occupancy 5871093052 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 6773203746 # Layer occupancy (ticks)
3853c3856
< system.membus.respLayer3.occupancy 81490219 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 76561844 # Layer occupancy (ticks)
3855,3861c3858,3864
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
---
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
3868,3869c3871,3872
< system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
---
> system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
3912,3918c3915,3921
< system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
---
> system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
3923,3968c3926,3972
< system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.toL2Bus.snoop_filter.tot_requests 12086303 # Total number of requests made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_requests 6387551 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_requests 2235502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.snoop_filter.tot_snoops 239971 # Total number of snoops made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_snoops 217052 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_snoops 22919 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
< system.toL2Bus.trans_dist::ReadReq 59846 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 4613854 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 38386 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 38386 # Transaction distribution
< system.toL2Bus.trans_dist::WritebackDirty 4129201 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 2768870 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 702098 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 370433 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 1072531 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 113 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 113 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 298786 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 298786 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 4554900 # Transaction distribution
< system.toL2Bus.trans_dist::InvalidateReq 905153 # Transaction distribution
< system.toL2Bus.trans_dist::InvalidateResp 886862 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9925339 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7679367 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 17604706 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 251196049 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 191962664 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 443158713 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 3147878 # Total snoops (count)
< system.toL2Bus.snoopTraffic 132377296 # Total snoop traffic (bytes)
< system.toL2Bus.snoop_fanout::samples 8556431 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 0.371457 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.488706 # Request fanout histogram
---
> system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.toL2Bus.snoop_filter.tot_requests 12840687 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 6804210 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 2233432 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.snoop_filter.tot_snoops 286650 # Total number of snoops made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_snoops 259465 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_snoops 27185 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states
> system.toL2Bus.trans_dist::ReadReq 40967 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 4895074 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 38689 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 38689 # Transaction distribution
> system.toL2Bus.trans_dist::WritebackDirty 4582152 # Transaction distribution
> system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 2976886 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 687999 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 398085 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 1086084 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 122 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 311857 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 311857 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 4854758 # Transaction distribution
> system.toL2Bus.trans_dist::InvalidateReq 900244 # Transaction distribution
> system.toL2Bus.trans_dist::InvalidateResp 885499 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10402586 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8325072 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 18727658 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 271068295 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 211681017 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 482749312 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 3295138 # Total snoops (count)
> system.toL2Bus.snoopTraffic 141512016 # Total snoop traffic (bytes)
> system.toL2Bus.snoop_fanout::samples 9092383 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 0.348495 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.482728 # Request fanout histogram
3970,3972c3974,3976
< system.toL2Bus.snoop_fanout::0 5401002 63.12% 63.12% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 3132510 36.61% 99.73% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 22919 0.27% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 5950920 65.45% 65.45% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 3114278 34.25% 99.70% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 27185 0.30% 100.00% # Request fanout histogram
3976,3977c3980,3981
< system.toL2Bus.snoop_fanout::total 8556431 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 9443624545 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 9092383 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 10118543300 # Layer occupancy (ticks)
3979c3983
< system.toL2Bus.snoopLayer0.occupancy 9237873 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 8937131 # Layer occupancy (ticks)
3981c3985
< system.toL2Bus.respLayer0.occupancy 4533014073 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 4714839859 # Layer occupancy (ticks)
3983c3987
< system.toL2Bus.respLayer1.occupancy 3814018472 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 4090244927 # Layer occupancy (ticks)
3986c3990
< system.cpu0.kern.inst.quiesce 13606 # number of quiesce instructions executed
---
> system.cpu0.kern.inst.quiesce 5530 # number of quiesce instructions executed
3988c3992
< system.cpu1.kern.inst.quiesce 5169 # number of quiesce instructions executed
---
> system.cpu1.kern.inst.quiesce 13684 # number of quiesce instructions executed