3,5c3,5
< sim_seconds 47.383918 # Number of seconds simulated
< sim_ticks 47383917710000 # Number of ticks simulated
< final_tick 47383917710000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 47.384943 # Number of seconds simulated
> sim_ticks 47384942719000 # Number of ticks simulated
> final_tick 47384942719000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 126839 # Simulator instruction rate (inst/s)
< host_op_rate 149150 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 6559041658 # Simulator tick rate (ticks/s)
< host_mem_usage 782584 # Number of bytes of host memory used
< host_seconds 7224.21 # Real time elapsed on the host
< sim_insts 916315151 # Number of instructions simulated
< sim_ops 1077489368 # Number of ops (including micro ops) simulated
---
> host_inst_rate 146603 # Simulator instruction rate (inst/s)
> host_op_rate 172405 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 7419029838 # Simulator tick rate (ticks/s)
> host_mem_usage 776468 # Number of bytes of host memory used
> host_seconds 6386.95 # Real time elapsed on the host
> sim_insts 936348150 # Number of instructions simulated
> sim_ops 1101141201 # Number of ops (including micro ops) simulated
16,32c16,32
< system.physmem.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu0.dtb.walker 217728 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.itb.walker 211200 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.inst 4242016 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 16335944 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 21100544 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 95616 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.itb.walker 61568 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 3171760 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 9979472 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 12170752 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 426688 # Number of bytes read from this memory
< system.physmem.bytes_read::total 68013288 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 4242016 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 3171760 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 7413776 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 84160640 # Number of bytes written to this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu0.dtb.walker 225984 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.itb.walker 211072 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.inst 4210272 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 17875336 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 22288384 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 132032 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.itb.walker 98944 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 3431264 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 10538960 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 15414592 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 437696 # Number of bytes read from this memory
> system.physmem.bytes_read::total 74864536 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 4210272 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 3431264 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 7641536 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 90448704 # Number of bytes written to this memory
35,48c35,48
< system.physmem.bytes_written::total 84181224 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.dtb.walker 3402 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.itb.walker 3300 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.inst 82234 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 255262 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 329696 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 1494 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.itb.walker 962 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 49603 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 155942 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 190168 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6667 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1078730 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1315010 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 90469288 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.dtb.walker 3531 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.itb.walker 3298 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.inst 81738 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 279315 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 348256 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 2063 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.itb.walker 1546 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 53657 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 164684 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 240853 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6839 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1185780 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1413261 # Number of write requests responded to by this memory
51,67c51,67
< system.physmem.num_writes::total 1317584 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 4595 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.itb.walker 4457 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.inst 89524 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 344757 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 445310 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 2018 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.itb.walker 1299 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 66937 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 210609 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 256854 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 9005 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1435366 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 89524 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 66937 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 156462 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1776144 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 1415835 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 4769 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.itb.walker 4454 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.inst 88853 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 377237 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 470368 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 2786 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.itb.walker 2088 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 72413 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 222412 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 325306 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 9237 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1579922 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 88853 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 72413 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 161265 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1908807 # Write bandwidth from this memory (bytes/s)
70,94c70,94
< system.physmem.bw_write::total 1776578 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1776144 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 4595 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.itb.walker 4457 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 89524 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 345191 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 445310 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 2018 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.itb.walker 1299 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 66937 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 210609 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 256854 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 9005 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 3211944 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 1078730 # Number of read requests accepted
< system.physmem.writeReqs 1317584 # Number of write requests accepted
< system.physmem.readBursts 1078730 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1317584 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 69010688 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 28032 # Total number of bytes read from write queue
< system.physmem.bytesWritten 84179968 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 68013288 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 84181224 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 438 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.bw_write::total 1909241 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1908807 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 4769 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.itb.walker 4454 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 88853 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 377671 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 470368 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 2786 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.itb.walker 2088 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 72413 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 222412 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 325306 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 9237 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3489164 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 1185780 # Number of read requests accepted
> system.physmem.writeReqs 1415835 # Number of write requests accepted
> system.physmem.readBursts 1185780 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1415835 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 75867200 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 22720 # Total number of bytes read from write queue
> system.physmem.bytesWritten 90467840 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 74864536 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 90469288 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 355 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one
96,127c96,127
< system.physmem.perBankRdBursts::0 67696 # Per bank write bursts
< system.physmem.perBankRdBursts::1 73149 # Per bank write bursts
< system.physmem.perBankRdBursts::2 67549 # Per bank write bursts
< system.physmem.perBankRdBursts::3 71981 # Per bank write bursts
< system.physmem.perBankRdBursts::4 66956 # Per bank write bursts
< system.physmem.perBankRdBursts::5 73789 # Per bank write bursts
< system.physmem.perBankRdBursts::6 64889 # Per bank write bursts
< system.physmem.perBankRdBursts::7 66635 # Per bank write bursts
< system.physmem.perBankRdBursts::8 57075 # Per bank write bursts
< system.physmem.perBankRdBursts::9 82656 # Per bank write bursts
< system.physmem.perBankRdBursts::10 58467 # Per bank write bursts
< system.physmem.perBankRdBursts::11 69413 # Per bank write bursts
< system.physmem.perBankRdBursts::12 60741 # Per bank write bursts
< system.physmem.perBankRdBursts::13 63810 # Per bank write bursts
< system.physmem.perBankRdBursts::14 67156 # Per bank write bursts
< system.physmem.perBankRdBursts::15 66330 # Per bank write bursts
< system.physmem.perBankWrBursts::0 82175 # Per bank write bursts
< system.physmem.perBankWrBursts::1 87404 # Per bank write bursts
< system.physmem.perBankWrBursts::2 82364 # Per bank write bursts
< system.physmem.perBankWrBursts::3 86039 # Per bank write bursts
< system.physmem.perBankWrBursts::4 82832 # Per bank write bursts
< system.physmem.perBankWrBursts::5 88693 # Per bank write bursts
< system.physmem.perBankWrBursts::6 80795 # Per bank write bursts
< system.physmem.perBankWrBursts::7 83065 # Per bank write bursts
< system.physmem.perBankWrBursts::8 76149 # Per bank write bursts
< system.physmem.perBankWrBursts::9 79916 # Per bank write bursts
< system.physmem.perBankWrBursts::10 77037 # Per bank write bursts
< system.physmem.perBankWrBursts::11 82986 # Per bank write bursts
< system.physmem.perBankWrBursts::12 77147 # Per bank write bursts
< system.physmem.perBankWrBursts::13 80171 # Per bank write bursts
< system.physmem.perBankWrBursts::14 84038 # Per bank write bursts
< system.physmem.perBankWrBursts::15 84501 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 74918 # Per bank write bursts
> system.physmem.perBankRdBursts::1 82946 # Per bank write bursts
> system.physmem.perBankRdBursts::2 75146 # Per bank write bursts
> system.physmem.perBankRdBursts::3 74319 # Per bank write bursts
> system.physmem.perBankRdBursts::4 73960 # Per bank write bursts
> system.physmem.perBankRdBursts::5 83356 # Per bank write bursts
> system.physmem.perBankRdBursts::6 71088 # Per bank write bursts
> system.physmem.perBankRdBursts::7 75076 # Per bank write bursts
> system.physmem.perBankRdBursts::8 69225 # Per bank write bursts
> system.physmem.perBankRdBursts::9 91582 # Per bank write bursts
> system.physmem.perBankRdBursts::10 63014 # Per bank write bursts
> system.physmem.perBankRdBursts::11 68676 # Per bank write bursts
> system.physmem.perBankRdBursts::12 68042 # Per bank write bursts
> system.physmem.perBankRdBursts::13 71091 # Per bank write bursts
> system.physmem.perBankRdBursts::14 73017 # Per bank write bursts
> system.physmem.perBankRdBursts::15 69969 # Per bank write bursts
> system.physmem.perBankWrBursts::0 88621 # Per bank write bursts
> system.physmem.perBankWrBursts::1 92960 # Per bank write bursts
> system.physmem.perBankWrBursts::2 88280 # Per bank write bursts
> system.physmem.perBankWrBursts::3 90026 # Per bank write bursts
> system.physmem.perBankWrBursts::4 89701 # Per bank write bursts
> system.physmem.perBankWrBursts::5 97248 # Per bank write bursts
> system.physmem.perBankWrBursts::6 87218 # Per bank write bursts
> system.physmem.perBankWrBursts::7 89230 # Per bank write bursts
> system.physmem.perBankWrBursts::8 86326 # Per bank write bursts
> system.physmem.perBankWrBursts::9 88636 # Per bank write bursts
> system.physmem.perBankWrBursts::10 82100 # Per bank write bursts
> system.physmem.perBankWrBursts::11 87622 # Per bank write bursts
> system.physmem.perBankWrBursts::12 86001 # Per bank write bursts
> system.physmem.perBankWrBursts::13 87485 # Per bank write bursts
> system.physmem.perBankWrBursts::14 85741 # Per bank write bursts
> system.physmem.perBankWrBursts::15 86365 # Per bank write bursts
129,130c129,130
< system.physmem.numWrRetry 50212 # Number of times write queue was full causing retry
< system.physmem.totGap 47383916196500 # Total gap between requests
---
> system.physmem.numWrRetry 51113 # Number of times write queue was full causing retry
> system.physmem.totGap 47384941205500 # Total gap between requests
135c135
< system.physmem.readPktSize::4 21334 # Read request sizes (log2)
---
> system.physmem.readPktSize::4 21333 # Read request sizes (log2)
137c137
< system.physmem.readPktSize::6 1057371 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 1164422 # Read request sizes (log2)
144,166c144,166
< system.physmem.writePktSize::6 1315010 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 477824 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 264556 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 85571 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 63109 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 41587 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 35911 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 32865 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 30424 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 27932 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 7543 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 3912 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 2354 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 1437 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 1085 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 609 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 513 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 445 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 357 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 146 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 93 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1413261 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 492558 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 272193 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 123866 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 77106 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 49827 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 41505 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 37948 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 35214 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 31591 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 9310 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 5210 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 3059 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 1824 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 1397 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 811 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 674 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 576 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 471 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 162 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 110 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see
192,259c192,259
< system.physmem.wrQLenPdf::15 22527 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 26520 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 36837 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 42274 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 46464 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 50322 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 56496 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 61138 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 66561 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 68608 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 74012 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 78194 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 76215 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 79218 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 90231 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 80845 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 75138 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 70175 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 5598 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 3927 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 2866 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 2290 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 1845 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 1544 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 1368 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 1258 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 1266 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 1360 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 1411 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 1419 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 1282 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 1482 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 1488 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 1820 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 1958 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 2035 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 2146 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 2370 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 2522 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 2687 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 2917 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 2998 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 2934 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 3116 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 3382 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 4014 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 5428 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 24238 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 118579 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 1002120 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 152.866515 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 102.517170 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 198.697434 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 641919 64.06% 64.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 209293 20.89% 84.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 56817 5.67% 90.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 24891 2.48% 93.09% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 19538 1.95% 95.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 11144 1.11% 96.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 7510 0.75% 96.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 6154 0.61% 97.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 24854 2.48% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1002120 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 61846 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 17.434870 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 71.484606 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-511 61843 100.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::512-1023 1 0.00% 100.00% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 22656 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 26213 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 37414 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 43560 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 48703 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 53588 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 59870 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 65839 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 71191 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 73927 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 78606 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 82389 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 81499 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 83906 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 89741 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 97285 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 86545 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 80600 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 8679 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 5080 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 3802 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 2902 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 2352 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 2103 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 1842 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 1736 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 1672 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 1659 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 1715 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 1682 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 1630 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 1838 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 1694 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 1790 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 1915 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 1936 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 2089 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 2158 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 2578 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 2909 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 3105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 3321 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 3357 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 3394 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 4009 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 5197 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 6401 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 25051 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 120445 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 1083045 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 153.580618 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 102.695829 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 199.684011 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 694535 64.13% 64.13% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 223527 20.64% 84.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 61545 5.68% 90.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 27125 2.50% 92.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 21919 2.02% 94.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 12312 1.14% 96.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 8465 0.78% 96.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 6818 0.63% 97.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 26799 2.47% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1083045 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 67614 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 17.532168 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 68.484066 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-511 67610 99.99% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes
262,274c262,275
< system.physmem.rdPerTurnAround::total 61846 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 61846 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 21.267535 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.561626 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 606.950117 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::0-4095 61844 100.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40960-45055 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::143360-147455 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 61846 # Writes before turning the bus around for reads
< system.physmem.totQLat 51075620081 # Total ticks spent queuing
< system.physmem.totMemAccLat 71293595081 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 5391460000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 47367.15 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 67614 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 67614 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.906321 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.453992 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 533.973047 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::0-2047 67611 100.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::12288-14335 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::43008-45055 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::129024-131071 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 67614 # Writes before turning the bus around for reads
> system.physmem.totQLat 72498378118 # Total ticks spent queuing
> system.physmem.totMemAccLat 94725096868 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 5927125000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 61158.13 # Average queueing delay per DRAM burst
276,280c277,281
< system.physmem.avgMemAccLat 66117.15 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1.46 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 1.44 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 79908.13 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1.60 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 1.91 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 1.58 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 1.91 # Average system write bandwidth in MiByte/s
285,321c286,332
< system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 23.55 # Average write queue length when enqueuing
< system.physmem.readRowHits 810741 # Number of row buffer hits during reads
< system.physmem.writeRowHits 580742 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 75.19 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 44.15 # Row buffer hit rate for writes
< system.physmem.avgGap 19773667.47 # Average gap between requests
< system.physmem.pageHitRate 58.13 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 3929423400 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 2144030625 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 4310615400 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 4363418160 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 3094887141840 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 1164748800645 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 27408641092500 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 31683024522570 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.645104 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 45596671664426 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1582253140000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 204992820574 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.physmem_1.actEnergy 3646603800 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 1989714375 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 4100054400 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 4159803600 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 3094887141840 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 1159320938310 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 27413402375250 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 31681506631575 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.613070 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 45604605403923 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1582253140000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 197059081077 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
---
> system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing
> system.physmem.readRowHits 894792 # Number of row buffer hits during reads
> system.physmem.writeRowHits 621147 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 75.48 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 43.94 # Row buffer hit rate for writes
> system.physmem.avgGap 18213663.90 # Average gap between requests
> system.physmem.pageHitRate 58.33 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 4041154320 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 2147920665 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 4361176260 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 3775542480 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 33222521280.000008 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 42262106220 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1577144160 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 67404809070 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 44351104800 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 11290594038405 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 11493753562350 # Total energy per rank (pJ)
> system.physmem_0.averagePower 242.561305 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 47288119152834 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 2641670410 # Time in different power states
> system.physmem_0.memoryStateTime::REF 14105156000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 47024804557250 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 115497548988 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 80076687506 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 147817098846 # Time in different power states
> system.physmem_1.actEnergy 3691794120 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 1962235110 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 4102758240 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 3603240720 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 31839581280.000008 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 42875044890 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1564584000 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 59886050220 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 43118785440 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 11295073117425 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 11487733544595 # Total energy per rank (pJ)
> system.physmem_1.averagePower 242.434260 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 47286801320918 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 2657158504 # Time in different power states
> system.physmem_1.memoryStateTime::REF 13520630000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 47043190241000 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 112288389331 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 81956603828 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 131329696337 # Time in different power states
> system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
348,350c359,361
< system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.bridge.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
---
> system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.bridge.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
357,361c368,372
< system.cpu0.branchPred.lookups 139955722 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 92576910 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 6767718 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 98409045 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 61922323 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 139745078 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 92256746 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 6767345 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 98774130 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 61692324 # Number of BTB hits
363,369c374,380
< system.cpu0.branchPred.BTBHitPct 62.923406 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 19026711 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 185987 # Number of incorrect RAS predictions.
< system.cpu0.branchPred.indirectLookups 4326684 # Number of indirect predictor lookups.
< system.cpu0.branchPred.indirectHits 2749366 # Number of indirect target hits.
< system.cpu0.branchPred.indirectMisses 1577318 # Number of indirect misses.
< system.cpu0.branchPredindirectMispredicted 397214 # Number of mispredicted indirect branches.
---
> system.cpu0.branchPred.BTBHitPct 62.457978 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 19130272 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 187780 # Number of incorrect RAS predictions.
> system.cpu0.branchPred.indirectLookups 4236971 # Number of indirect predictor lookups.
> system.cpu0.branchPred.indirectHits 2716946 # Number of indirect target hits.
> system.cpu0.branchPred.indirectMisses 1520025 # Number of indirect misses.
> system.cpu0.branchPredindirectMispredicted 386103 # Number of mispredicted indirect branches.
371c382
< system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
---
> system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
401,432c412,444
< system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.cpu0.dtb.walker.walks 611788 # Table walker walks requested
< system.cpu0.dtb.walker.walksLong 611788 # Table walker walks initiated with long descriptors
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13108 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 98298 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walksSquashedBefore 292807 # Table walks squashed before starting
< system.cpu0.dtb.walker.walkWaitTime::samples 318981 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::mean 2428.828049 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::stdev 13543.109769 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0-65535 316274 99.15% 99.15% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::65536-131071 2036 0.64% 99.79% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::131072-196607 442 0.14% 99.93% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::196608-262143 138 0.04% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::262144-327679 53 0.02% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::327680-393215 29 0.01% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::total 318981 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkCompletionTime::samples 326187 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::mean 22022.583671 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::gmean 18838.451550 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::stdev 17664.426007 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::0-65535 321608 98.60% 98.60% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::65536-131071 3320 1.02% 99.61% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::131072-196607 429 0.13% 99.75% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::196608-262143 611 0.19% 99.93% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::262144-327679 146 0.04% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::327680-393215 45 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::393216-458751 21 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
---
> system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.cpu0.dtb.walker.walks 642249 # Table walker walks requested
> system.cpu0.dtb.walker.walksLong 642249 # Table walker walks initiated with long descriptors
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 14371 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 105891 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walksSquashedBefore 311173 # Table walks squashed before starting
> system.cpu0.dtb.walker.walkWaitTime::samples 331076 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::mean 2394.451727 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::stdev 14284.464178 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0-65535 328283 99.16% 99.16% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::65536-131071 2041 0.62% 99.77% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::131072-196607 492 0.15% 99.92% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::196608-262143 140 0.04% 99.96% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::262144-327679 44 0.01% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::327680-393215 49 0.01% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::393216-458751 5 0.00% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::589824-655359 15 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::total 331076 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkCompletionTime::samples 352054 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::mean 21918.096372 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::gmean 18874.221671 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::stdev 17893.290078 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::0-65535 347548 98.72% 98.72% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::65536-131071 2975 0.85% 99.57% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::131072-196607 632 0.18% 99.74% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::196608-262143 594 0.17% 99.91% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::262144-327679 153 0.04% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::327680-393215 118 0.03% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::393216-458751 25 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
434,452c446,464
< system.cpu0.dtb.walker.walkCompletionTime::total 326187 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walksPending::samples 530119453936 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::mean 0.586335 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::stdev 0.554664 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::0-1 528635854936 99.72% 99.72% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::2-3 807711000 0.15% 99.87% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::4-5 321496500 0.06% 99.93% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::6-7 138249500 0.03% 99.96% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::8-9 109943500 0.02% 99.98% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::10-11 58618500 0.01% 99.99% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::12-13 20610000 0.00% 99.99% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::14-15 26013000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::16-17 940000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::18-19 17000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::total 530119453936 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walkPageSizes::4K 98298 88.23% 88.23% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::2M 13108 11.77% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 111406 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 611788 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkCompletionTime::total 352054 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walksPending::samples 539733877528 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::mean 0.599244 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::stdev 0.552867 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::0-1 538149503028 99.71% 99.71% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::2-3 904434000 0.17% 99.87% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::4-5 320975500 0.06% 99.93% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::6-7 139201000 0.03% 99.96% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::8-9 110066000 0.02% 99.98% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::10-11 60836000 0.01% 99.99% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::12-13 22060500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::14-15 25840500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::16-17 959500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::total 539733877528 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walkPageSizes::4K 105891 88.05% 88.05% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::2M 14371 11.95% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 120262 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 642249 # Table walker requests started/completed, data/inst
454,455c466,467
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 611788 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 111406 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 642249 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 120262 # Table walker requests started/completed, data/inst
457,458c469,470
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 111406 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 723194 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 120262 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 762511 # Table walker requests started/completed, data/inst
461,465c473,477
< system.cpu0.dtb.read_hits 102674478 # DTB read hits
< system.cpu0.dtb.read_misses 445170 # DTB read misses
< system.cpu0.dtb.write_hits 82832935 # DTB write hits
< system.cpu0.dtb.write_misses 166618 # DTB write misses
< system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
---
> system.cpu0.dtb.read_hits 102850435 # DTB read hits
> system.cpu0.dtb.read_misses 467880 # DTB read misses
> system.cpu0.dtb.write_hits 83320332 # DTB write hits
> system.cpu0.dtb.write_misses 174369 # DTB write misses
> system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
467,471c479,483
< system.cpu0.dtb.flush_tlb_mva_asid 44145 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID
< system.cpu0.dtb.flush_entries 42795 # Number of entries that have been flushed from TLB
< system.cpu0.dtb.align_faults 479 # Number of TLB faults due to alignment restrictions
< system.cpu0.dtb.prefetch_faults 7037 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.flush_tlb_mva_asid 45792 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.dtb.flush_tlb_asid 1079 # Number of times TLB was flushed by ASID
> system.cpu0.dtb.flush_entries 42516 # Number of entries that have been flushed from TLB
> system.cpu0.dtb.align_faults 599 # Number of TLB faults due to alignment restrictions
> system.cpu0.dtb.prefetch_faults 7036 # Number of TLB faults due to prefetch
473,475c485,487
< system.cpu0.dtb.perms_faults 40072 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 103119648 # DTB read accesses
< system.cpu0.dtb.write_accesses 82999553 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 38961 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 103318315 # DTB read accesses
> system.cpu0.dtb.write_accesses 83494701 # DTB write accesses
477,480c489,492
< system.cpu0.dtb.hits 185507413 # DTB hits
< system.cpu0.dtb.misses 611788 # DTB misses
< system.cpu0.dtb.accesses 186119201 # DTB accesses
< system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
---
> system.cpu0.dtb.hits 186170767 # DTB hits
> system.cpu0.dtb.misses 642249 # DTB misses
> system.cpu0.dtb.accesses 186813016 # DTB accesses
> system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
510,555c522,567
< system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.cpu0.itb.walker.walks 85546 # Table walker walks requested
< system.cpu0.itb.walker.walksLong 85546 # Table walker walks initiated with long descriptors
< system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1054 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59782 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walksSquashedBefore 10366 # Table walks squashed before starting
< system.cpu0.itb.walker.walkWaitTime::samples 75180 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::mean 1322.160149 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::stdev 9414.531253 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::0-32767 74314 98.85% 98.85% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::32768-65535 448 0.60% 99.44% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::65536-98303 228 0.30% 99.75% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::98304-131071 153 0.20% 99.95% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::131072-163839 9 0.01% 99.96% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::163840-196607 10 0.01% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::total 75180 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkCompletionTime::samples 71202 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::mean 26797.709334 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::gmean 23346.070270 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::stdev 22372.473032 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::0-65535 68772 96.59% 96.59% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::65536-131071 2000 2.81% 99.40% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::131072-196607 197 0.28% 99.67% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::196608-262143 144 0.20% 99.88% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::262144-327679 55 0.08% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::327680-393215 23 0.03% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::total 71202 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walksPending::samples 422744199036 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::mean 0.876427 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::stdev 0.329334 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::0 52271860780 12.36% 12.36% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::1 370441299256 87.63% 99.99% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::2 29828500 0.01% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::3 1210500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::total 422744199036 # Table walker pending requests distribution
< system.cpu0.itb.walker.walkPageSizes::4K 59782 98.27% 98.27% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::2M 1054 1.73% 100.00% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::total 60836 # Table walker page sizes translated
---
> system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.cpu0.itb.walker.walks 84160 # Table walker walks requested
> system.cpu0.itb.walker.walksLong 84160 # Table walker walks initiated with long descriptors
> system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1044 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58792 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walksSquashedBefore 10193 # Table walks squashed before starting
> system.cpu0.itb.walker.walkWaitTime::samples 73967 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::mean 1726.006192 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::stdev 15527.215020 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::0-65535 73402 99.24% 99.24% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::65536-131071 457 0.62% 99.85% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::131072-196607 56 0.08% 99.93% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::196608-262143 12 0.02% 99.95% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::262144-327679 7 0.01% 99.96% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::327680-393215 9 0.01% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::393216-458751 1 0.00% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::524288-589823 1 0.00% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::589824-655359 22 0.03% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::total 73967 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkCompletionTime::samples 70029 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::mean 27234.188693 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::gmean 23423.171681 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::stdev 26401.977199 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::0-65535 67612 96.55% 96.55% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::65536-131071 1634 2.33% 98.88% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::131072-196607 479 0.68% 99.57% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::196608-262143 184 0.26% 99.83% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::262144-327679 51 0.07% 99.90% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::327680-393215 27 0.04% 99.94% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::393216-458751 16 0.02% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::524288-589823 4 0.01% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::589824-655359 21 0.03% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::total 70029 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walksPending::samples 423766533036 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::mean 0.875739 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::stdev 0.330248 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::0 52705402108 12.44% 12.44% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::1 371016436928 87.55% 99.99% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::2 42131000 0.01% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::3 1939000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::4 624000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::total 423766533036 # Table walker pending requests distribution
> system.cpu0.itb.walker.walkPageSizes::4K 58792 98.26% 98.26% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::2M 1044 1.74% 100.00% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::total 59836 # Table walker page sizes translated
557,558c569,570
< system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85546 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85546 # Table walker requests started/completed, data/inst
---
> system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 84160 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Requested::total 84160 # Table walker requests started/completed, data/inst
560,564c572,576
< system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60836 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60836 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin::total 146382 # Table walker requests started/completed, data/inst
< system.cpu0.itb.inst_hits 220474674 # ITB inst hits
< system.cpu0.itb.inst_misses 85546 # ITB inst misses
---
> system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59836 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59836 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin::total 143996 # Table walker requests started/completed, data/inst
> system.cpu0.itb.inst_hits 220066677 # ITB inst hits
> system.cpu0.itb.inst_misses 84160 # ITB inst misses
569c581
< system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
---
> system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
571,573c583,585
< system.cpu0.itb.flush_tlb_mva_asid 44145 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID
< system.cpu0.itb.flush_entries 31037 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_tlb_mva_asid 45792 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.itb.flush_tlb_asid 1079 # Number of times TLB was flushed by ASID
> system.cpu0.itb.flush_entries 30584 # Number of entries that have been flushed from TLB
577c589
< system.cpu0.itb.perms_faults 205838 # Number of TLB faults due to permissions restrictions
---
> system.cpu0.itb.perms_faults 203568 # Number of TLB faults due to permissions restrictions
580,601c592,614
< system.cpu0.itb.inst_accesses 220560220 # ITB inst accesses
< system.cpu0.itb.hits 220474674 # DTB hits
< system.cpu0.itb.misses 85546 # DTB misses
< system.cpu0.itb.accesses 220560220 # DTB accesses
< system.cpu0.numPwrStateTransitions 10840 # Number of power state transitions
< system.cpu0.pwrStateClkGateDist::samples 5420 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::mean 8671662092.472324 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::stdev 149203914828.202179 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::underflows 3833 70.72% 70.72% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::1000-5e+10 1557 28.73% 99.45% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::5e+10-1e+11 11 0.20% 99.65% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 3 0.06% 99.70% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.72% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.74% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.76% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::overflows 13 0.24% 100.00% # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::max_value 6993554617000 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateClkGateDist::total 5420 # Distribution of time spent in the clock gated state
< system.cpu0.pwrStateResidencyTicks::ON 383509168800 # Cumulative time (in ticks) in various power states
< system.cpu0.pwrStateResidencyTicks::CLK_GATED 47000408541200 # Cumulative time (in ticks) in various power states
< system.cpu0.numCycles 767019929 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 220150837 # ITB inst accesses
> system.cpu0.itb.hits 220066677 # DTB hits
> system.cpu0.itb.misses 84160 # DTB misses
> system.cpu0.itb.accesses 220150837 # DTB accesses
> system.cpu0.numPwrStateTransitions 10070 # Number of power state transitions
> system.cpu0.pwrStateClkGateDist::samples 5035 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::mean 9333517887.918768 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::stdev 154504325024.809692 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::underflows 3827 76.01% 76.01% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::1000-5e+10 1181 23.46% 99.46% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::5e+10-1e+11 7 0.14% 99.60% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.62% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 3 0.06% 99.68% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.72% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.74% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::overflows 13 0.26% 100.00% # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::max_value 6914082505000 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateClkGateDist::total 5035 # Distribution of time spent in the clock gated state
> system.cpu0.pwrStateResidencyTicks::ON 390680153329 # Cumulative time (in ticks) in various power states
> system.cpu0.pwrStateResidencyTicks::CLK_GATED 46994262565671 # Cumulative time (in ticks) in various power states
> system.cpu0.numCycles 781361530 # number of cpu cycles simulated
604,620c617,633
< system.cpu0.fetch.icacheStallCycles 88196996 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 619911097 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 139955722 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 83698400 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 636708825 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu0.fetch.SquashCycles 14589342 # Number of cycles fetch has spent squashing
< system.cpu0.fetch.TlbCycles 2007819 # Number of cycles fetch has spent waiting for tlb
< system.cpu0.fetch.MiscStallCycles 289070 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu0.fetch.PendingTrapStallCycles 6017581 # Number of stall cycles due to pending traps
< system.cpu0.fetch.PendingQuiesceStallCycles 759490 # Number of stall cycles due to pending quiesce instructions
< system.cpu0.fetch.IcacheWaitRetryStallCycles 830550 # Number of stall cycles due to full MSHR
< system.cpu0.fetch.CacheLines 220269194 # Number of cache lines fetched
< system.cpu0.fetch.IcacheSquashes 1684756 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.ItlbSquashes 27864 # Number of outstanding ITLB misses that were squashed
< system.cpu0.fetch.rateDist::samples 742105002 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 0.977120 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 1.219124 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.icacheStallCycles 89977379 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 618690334 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 139745078 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 83539542 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 647313928 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu0.fetch.SquashCycles 14578052 # Number of cycles fetch has spent squashing
> system.cpu0.fetch.TlbCycles 1993554 # Number of cycles fetch has spent waiting for tlb
> system.cpu0.fetch.MiscStallCycles 302966 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu0.fetch.PendingTrapStallCycles 5990682 # Number of stall cycles due to pending traps
> system.cpu0.fetch.PendingQuiesceStallCycles 771527 # Number of stall cycles due to pending quiesce instructions
> system.cpu0.fetch.IcacheWaitRetryStallCycles 852599 # Number of stall cycles due to full MSHR
> system.cpu0.fetch.CacheLines 219863904 # Number of cache lines fetched
> system.cpu0.fetch.IcacheSquashes 1701332 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.ItlbSquashes 27447 # Number of outstanding ITLB misses that were squashed
> system.cpu0.fetch.rateDist::samples 754491661 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 0.959990 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 1.215112 # Number of instructions fetched each cycle (Total)
622,625c635,638
< system.cpu0.fetch.rateDist::0 394679215 53.18% 53.18% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 135211877 18.22% 71.40% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 46727804 6.30% 77.70% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 165486106 22.30% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 407421945 54.00% 54.00% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 135112889 17.91% 71.91% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 46679176 6.19% 78.09% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 165277651 21.91% 100.00% # Number of instructions fetched each cycle (Total)
629,676c642,689
< system.cpu0.fetch.rateDist::total 742105002 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.182467 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 0.808207 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 106471358 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 362106065 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 229306920 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 38969186 # Number of cycles decode is unblocking
< system.cpu0.decode.SquashCycles 5251473 # Number of cycles decode is squashing
< system.cpu0.decode.BranchResolved 19951761 # Number of times decode resolved a branch
< system.cpu0.decode.BranchMispred 2082457 # Number of times decode detected a branch misprediction
< system.cpu0.decode.DecodedInsts 641630797 # Number of instructions handled by decode
< system.cpu0.decode.SquashedInsts 23347252 # Number of squashed instructions handled by decode
< system.cpu0.rename.SquashCycles 5251473 # Number of cycles rename is squashing
< system.cpu0.rename.IdleCycles 142650653 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 53065481 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 241402745 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 231558396 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 68176254 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 624076980 # Number of instructions processed by rename
< system.cpu0.rename.SquashedInsts 6229632 # Number of squashed instructions processed by rename
< system.cpu0.rename.ROBFullEvents 10704846 # Number of times rename has blocked due to ROB full
< system.cpu0.rename.IQFullEvents 385160 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LQFullEvents 931811 # Number of times rename has blocked due to LQ full
< system.cpu0.rename.SQFullEvents 31501280 # Number of times rename has blocked due to SQ full
< system.cpu0.rename.FullRegisterEvents 11804 # Number of times there has been no free registers
< system.cpu0.rename.RenamedOperands 596222700 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 963956032 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 736577059 # Number of integer rename lookups
< system.cpu0.rename.fp_rename_lookups 695179 # Number of floating rename lookups
< system.cpu0.rename.CommittedMaps 537389975 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 58832686 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 16140854 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 14103711 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 78118251 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 102816112 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 86124751 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 9533509 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 8142362 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 600960924 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu0.iq.iqNonSpecInstsAdded 16329392 # Number of non-speculative instructions added to the IQ
< system.cpu0.iq.iqInstsIssued 605893488 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 2751703 # Number of squashed instructions issued
< system.cpu0.iq.iqSquashedInstsExamined 55206879 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 35882934 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu0.iq.iqSquashedNonSpecRemoved 285911 # Number of squashed non-spec instructions that were removed
< system.cpu0.iq.issued_per_cycle::samples 742105002 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 0.816453 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.065729 # Number of insts issued each cycle
---
> system.cpu0.fetch.rateDist::total 754491661 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.178848 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 0.791811 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 107863691 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 373653702 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 228590583 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 39162463 # Number of cycles decode is unblocking
> system.cpu0.decode.SquashCycles 5221222 # Number of cycles decode is squashing
> system.cpu0.decode.BranchResolved 20030707 # Number of times decode resolved a branch
> system.cpu0.decode.BranchMispred 2107727 # Number of times decode detected a branch misprediction
> system.cpu0.decode.DecodedInsts 640747867 # Number of instructions handled by decode
> system.cpu0.decode.SquashedInsts 23352656 # Number of squashed instructions handled by decode
> system.cpu0.rename.SquashCycles 5221222 # Number of cycles rename is squashing
> system.cpu0.rename.IdleCycles 144093047 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 59069591 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 244366962 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 230957488 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 70783351 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 623359263 # Number of instructions processed by rename
> system.cpu0.rename.SquashedInsts 6158447 # Number of squashed instructions processed by rename
> system.cpu0.rename.ROBFullEvents 11021555 # Number of times rename has blocked due to ROB full
> system.cpu0.rename.IQFullEvents 440656 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LQFullEvents 940490 # Number of times rename has blocked due to LQ full
> system.cpu0.rename.SQFullEvents 33921586 # Number of times rename has blocked due to SQ full
> system.cpu0.rename.FullRegisterEvents 11494 # Number of times there has been no free registers
> system.cpu0.rename.RenamedOperands 594689945 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 962815337 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 736259751 # Number of integer rename lookups
> system.cpu0.rename.fp_rename_lookups 682623 # Number of floating rename lookups
> system.cpu0.rename.CommittedMaps 536299590 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 58390349 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 16178274 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 14135285 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 78489785 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 102915286 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 86617273 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 9593817 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 8133429 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 600294247 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu0.iq.iqNonSpecInstsAdded 16347683 # Number of non-speculative instructions added to the IQ
> system.cpu0.iq.iqInstsIssued 605471525 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 2720884 # Number of squashed instructions issued
> system.cpu0.iq.iqSquashedInstsExamined 54918264 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 35662191 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu0.iq.iqSquashedNonSpecRemoved 285806 # Number of squashed non-spec instructions that were removed
> system.cpu0.iq.issued_per_cycle::samples 754491661 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 0.802489 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.061507 # Number of insts issued each cycle
678,683c691,696
< system.cpu0.iq.issued_per_cycle::0 411055814 55.39% 55.39% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 139198751 18.76% 74.15% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 116841261 15.74% 89.89% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 67029634 9.03% 98.92% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 7974397 1.07% 100.00% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 5145 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 423297632 56.10% 56.10% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 139867580 18.54% 74.64% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 116427415 15.43% 90.07% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 66852551 8.86% 98.93% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 8040953 1.07% 100.00% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 5530 0.00% 100.00% # Number of insts issued each cycle
690c703
< system.cpu0.iq.issued_per_cycle::total 742105002 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 754491661 # Number of insts issued each cycle
692,722c705,735
< system.cpu0.iq.fu_full::IntAlu 62807824 45.43% 45.43% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 65216 0.05% 45.48% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 15839 0.01% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 32 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.49% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 36880846 26.68% 72.17% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 38467267 27.83% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 62202700 45.10% 45.10% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 65869 0.05% 45.14% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 12866 0.01% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 27 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.15% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 36951420 26.79% 71.94% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 38701650 28.06% 100.00% # attempts to use FU when none available
725,756c738,769
< system.cpu0.iq.FU_type_0::No_OpClass 25 0.00% 0.00% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntAlu 414236377 68.37% 68.37% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 1540158 0.25% 68.62% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntDiv 80647 0.01% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatAdd 9 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCmp 1 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMisc 41778 0.01% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.64% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemRead 105913797 17.48% 86.12% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 84080696 13.88% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::No_OpClass 51 0.00% 0.00% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntAlu 413123878 68.23% 68.23% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 1535668 0.25% 68.49% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntDiv 80204 0.01% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatAdd 6 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAddAcc 1 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.50% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMisc 45354 0.01% 68.51% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.51% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.51% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.51% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemRead 106103331 17.52% 86.03% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 84583031 13.97% 100.00% # Type of FU issued
759,771c772,784
< system.cpu0.iq.FU_type_0::total 605893488 # Type of FU issued
< system.cpu0.iq.rate 0.789932 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 138237024 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.228154 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 2093764115 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 672208466 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 588253598 # Number of integer instruction queue wakeup accesses
< system.cpu0.iq.fp_inst_queue_reads 1116590 # Number of floating instruction queue reads
< system.cpu0.iq.fp_inst_queue_writes 439713 # Number of floating instruction queue writes
< system.cpu0.iq.fp_inst_queue_wakeup_accesses 411739 # Number of floating instruction queue wakeup accesses
< system.cpu0.iq.int_alu_accesses 743434871 # Number of integer alu accesses
< system.cpu0.iq.fp_alu_accesses 695616 # Number of floating point alu accesses
< system.cpu0.iew.lsq.thread0.forwLoads 2774549 # Number of loads that had data forwarded from stores
---
> system.cpu0.iq.FU_type_0::total 605471525 # Type of FU issued
> system.cpu0.iq.rate 0.774893 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 137934532 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.227813 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 2104985611 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 671273361 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 587796479 # Number of integer instruction queue wakeup accesses
> system.cpu0.iq.fp_inst_queue_reads 1104514 # Number of floating instruction queue reads
> system.cpu0.iq.fp_inst_queue_writes 436534 # Number of floating instruction queue writes
> system.cpu0.iq.fp_inst_queue_wakeup_accesses 408765 # Number of floating instruction queue wakeup accesses
> system.cpu0.iq.int_alu_accesses 742719141 # Number of integer alu accesses
> system.cpu0.iq.fp_alu_accesses 686865 # Number of floating point alu accesses
> system.cpu0.iew.lsq.thread0.forwLoads 2818576 # Number of loads that had data forwarded from stores
773,776c786,789
< system.cpu0.iew.lsq.thread0.squashedLoads 12838296 # Number of loads squashed
< system.cpu0.iew.lsq.thread0.ignoredResponses 17783 # Number of memory responses ignored because the instruction is squashed
< system.cpu0.iew.lsq.thread0.memOrderViolation 152412 # Number of memory ordering violations
< system.cpu0.iew.lsq.thread0.squashedStores 5562268 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 12827708 # Number of loads squashed
> system.cpu0.iew.lsq.thread0.ignoredResponses 17934 # Number of memory responses ignored because the instruction is squashed
> system.cpu0.iew.lsq.thread0.memOrderViolation 150945 # Number of memory ordering violations
> system.cpu0.iew.lsq.thread0.squashedStores 5597965 # Number of stores squashed
779,780c792,793
< system.cpu0.iew.lsq.thread0.rescheduledLoads 2788433 # Number of loads that were rescheduled
< system.cpu0.iew.lsq.thread0.cacheBlocked 4754457 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.rescheduledLoads 2832815 # Number of loads that were rescheduled
> system.cpu0.iew.lsq.thread0.cacheBlocked 4794177 # Number of times an access to memory failed due to the cache being blocked
782,785c795,798
< system.cpu0.iew.iewSquashCycles 5251473 # Number of cycles IEW is squashing
< system.cpu0.iew.iewBlockCycles 7932610 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 1687524 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 617423509 # Number of instructions dispatched to IQ
---
> system.cpu0.iew.iewSquashCycles 5221222 # Number of cycles IEW is squashing
> system.cpu0.iew.iewBlockCycles 8523162 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 2018525 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 616773219 # Number of instructions dispatched to IQ
787,798c800,811
< system.cpu0.iew.iewDispLoadInsts 102816112 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 86124751 # Number of dispatched store instructions
< system.cpu0.iew.iewDispNonSpecInsts 13854081 # Number of dispatched non-speculative instructions
< system.cpu0.iew.iewIQFullEvents 62183 # Number of times the IQ has become full, causing a stall
< system.cpu0.iew.iewLSQFullEvents 1552208 # Number of times the LSQ has become full, causing a stall
< system.cpu0.iew.memOrderViolationEvents 152412 # Number of memory order violations
< system.cpu0.iew.predictedTakenIncorrect 1974984 # Number of branches that were predicted taken incorrectly
< system.cpu0.iew.predictedNotTakenIncorrect 3105212 # Number of branches that were predicted not taken incorrectly
< system.cpu0.iew.branchMispredicts 5080196 # Number of branch mispredicts detected at execute
< system.cpu0.iew.iewExecutedInsts 597824194 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 102668745 # Number of load instructions executed
< system.cpu0.iew.iewExecSquashedInsts 7465093 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewDispLoadInsts 102915286 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 86617273 # Number of dispatched store instructions
> system.cpu0.iew.iewDispNonSpecInsts 13889545 # Number of dispatched non-speculative instructions
> system.cpu0.iew.iewIQFullEvents 69101 # Number of times the IQ has become full, causing a stall
> system.cpu0.iew.iewLSQFullEvents 1866975 # Number of times the LSQ has become full, causing a stall
> system.cpu0.iew.memOrderViolationEvents 150945 # Number of memory order violations
> system.cpu0.iew.predictedTakenIncorrect 1955799 # Number of branches that were predicted taken incorrectly
> system.cpu0.iew.predictedNotTakenIncorrect 3092868 # Number of branches that were predicted not taken incorrectly
> system.cpu0.iew.branchMispredicts 5048667 # Number of branch mispredicts detected at execute
> system.cpu0.iew.iewExecutedInsts 597424685 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 102845914 # Number of load instructions executed
> system.cpu0.iew.iewExecSquashedInsts 7413191 # Number of squashed instructions skipped in execute
800,816c813,829
< system.cpu0.iew.exec_nop 133193 # number of nop insts executed
< system.cpu0.iew.exec_refs 185500111 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 112433305 # Number of branches executed
< system.cpu0.iew.exec_stores 82831366 # Number of stores executed
< system.cpu0.iew.exec_rate 0.779412 # Inst execution rate
< system.cpu0.iew.wb_sent 589443856 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 588665337 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 287005457 # num instructions producing a value
< system.cpu0.iew.wb_consumers 470602155 # num instructions consuming a value
< system.cpu0.iew.wb_rate 0.767471 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.609869 # average fanout of values written-back
< system.cpu0.commit.commitSquashedInsts 48230515 # The number of squashed insts skipped by commit
< system.cpu0.commit.commitNonSpecStalls 16043481 # The number of times commit has been forced to stall to communicate backwards
< system.cpu0.commit.branchMispredicts 4724520 # The number of times a branch was mispredicted
< system.cpu0.commit.committed_per_cycle::samples 732949405 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 0.766879 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 1.569816 # Number of insts commited each cycle
---
> system.cpu0.iew.exec_nop 131289 # number of nop insts executed
> system.cpu0.iew.exec_refs 186166471 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 112308682 # Number of branches executed
> system.cpu0.iew.exec_stores 83320557 # Number of stores executed
> system.cpu0.iew.exec_rate 0.764594 # Inst execution rate
> system.cpu0.iew.wb_sent 588977240 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 588205244 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 286222957 # num instructions producing a value
> system.cpu0.iew.wb_consumers 469478170 # num instructions consuming a value
> system.cpu0.iew.wb_rate 0.752795 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.609662 # average fanout of values written-back
> system.cpu0.commit.commitSquashedInsts 48006701 # The number of squashed insts skipped by commit
> system.cpu0.commit.commitNonSpecStalls 16061877 # The number of times commit has been forced to stall to communicate backwards
> system.cpu0.commit.branchMispredicts 4699541 # The number of times a branch was mispredicted
> system.cpu0.commit.committed_per_cycle::samples 745382545 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 0.753605 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 1.560188 # Number of insts commited each cycle
818,826c831,839
< system.cpu0.commit.committed_per_cycle::0 487135616 66.46% 66.46% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 127506386 17.40% 83.86% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 54345658 7.41% 91.27% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 18167389 2.48% 93.75% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 13030534 1.78% 95.53% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 9013680 1.23% 96.76% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 6080548 0.83% 97.59% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 3647046 0.50% 98.09% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 14022548 1.91% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 499589625 67.02% 67.02% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 127846284 17.15% 84.18% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 54154407 7.27% 91.44% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 18022208 2.42% 93.86% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 12958039 1.74% 95.60% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 8991225 1.21% 96.80% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 6101110 0.82% 97.62% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 3650180 0.49% 98.11% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 14069467 1.89% 100.00% # Number of insts commited each cycle
830,832c843,845
< system.cpu0.commit.committed_per_cycle::total 732949405 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 479057822 # Number of instructions committed
< system.cpu0.commit.committedOps 562083399 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 745382545 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 478330111 # Number of instructions committed
> system.cpu0.commit.committedOps 561723659 # Number of ops (including micro ops) committed
834,840c847,853
< system.cpu0.commit.refs 170540284 # Number of memory references committed
< system.cpu0.commit.loads 89977801 # Number of loads committed
< system.cpu0.commit.membars 3918882 # Number of memory barriers committed
< system.cpu0.commit.branches 106864519 # Number of branches committed
< system.cpu0.commit.fp_insts 404083 # Number of committed floating point instructions.
< system.cpu0.commit.int_insts 515735338 # Number of committed integer instructions.
< system.cpu0.commit.function_calls 14196925 # Number of function calls committed.
---
> system.cpu0.commit.refs 171106885 # Number of memory references committed
> system.cpu0.commit.loads 90087577 # Number of loads committed
> system.cpu0.commit.membars 3940521 # Number of memory barriers committed
> system.cpu0.commit.branches 106744395 # Number of branches committed
> system.cpu0.commit.fp_insts 400838 # Number of committed floating point instructions.
> system.cpu0.commit.int_insts 515553500 # Number of committed integer instructions.
> system.cpu0.commit.function_calls 14275050 # Number of function calls committed.
842,872c855,885
< system.cpu0.commit.op_class_0::IntAlu 390151246 69.41% 69.41% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntMult 1292004 0.23% 69.64% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntDiv 63609 0.01% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.65% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMisc 36256 0.01% 69.66% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.66% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.66% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.66% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemRead 89977801 16.01% 85.67% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemWrite 80562483 14.33% 100.00% # Class of committed instruction
---
> system.cpu0.commit.op_class_0::IntAlu 389225467 69.29% 69.29% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntMult 1288146 0.23% 69.52% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntDiv 63590 0.01% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.53% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMisc 39571 0.01% 69.54% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemRead 90087577 16.04% 85.58% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemWrite 81019308 14.42% 100.00% # Class of committed instruction
875,1003c888,1017
< system.cpu0.commit.op_class_0::total 562083399 # Class of committed instruction
< system.cpu0.commit.bw_lim_events 14022548 # number cycles where commit BW limit reached
< system.cpu0.rob.rob_reads 1325013729 # The number of ROB reads
< system.cpu0.rob.rob_writes 1229746140 # The number of ROB writes
< system.cpu0.timesIdled 998783 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu0.idleCycles 24914927 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.quiesceCycles 94000815527 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.committedInsts 479057822 # Number of Instructions Simulated
< system.cpu0.committedOps 562083399 # Number of Ops (including micro ops) Simulated
< system.cpu0.cpi 1.601101 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 1.601101 # CPI: Total CPI of All Threads
< system.cpu0.ipc 0.624570 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 0.624570 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 705670279 # number of integer regfile reads
< system.cpu0.int_regfile_writes 419695299 # number of integer regfile writes
< system.cpu0.fp_regfile_reads 680997 # number of floating regfile reads
< system.cpu0.fp_regfile_writes 310212 # number of floating regfile writes
< system.cpu0.cc_regfile_reads 130338984 # number of cc regfile reads
< system.cpu0.cc_regfile_writes 131056521 # number of cc regfile writes
< system.cpu0.misc_regfile_reads 1328403158 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 16107336 # number of misc regfile writes
< system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.cpu0.dcache.tags.replacements 6279329 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 481.718631 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 157880144 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 6279840 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 25.140791 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 1908955000 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.718631 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.940857 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.940857 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 218 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id
< system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
< system.cpu0.dcache.tags.tag_accesses 354237308 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 354237308 # Number of data accesses
< system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.cpu0.dcache.ReadReq_hits::cpu0.data 83229187 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 83229187 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 69700757 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 69700757 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 201759 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 201759 # number of SoftPFReq hits
< system.cpu0.dcache.WriteLineReq_hits::cpu0.data 148045 # number of WriteLineReq hits
< system.cpu0.dcache.WriteLineReq_hits::total 148045 # number of WriteLineReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1863463 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 1863463 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1922512 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 1922512 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 153077989 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 153077989 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 153279748 # number of overall hits
< system.cpu0.dcache.overall_hits::total 153279748 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 7047364 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 7047364 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 7798246 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 7798246 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 750513 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 750513 # number of SoftPFReq misses
< system.cpu0.dcache.WriteLineReq_misses::cpu0.data 796040 # number of WriteLineReq misses
< system.cpu0.dcache.WriteLineReq_misses::total 796040 # number of WriteLineReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 285990 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 285990 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 189707 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 189707 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 15641650 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 15641650 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 16392163 # number of overall misses
< system.cpu0.dcache.overall_misses::total 16392163 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 106587069500 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 106587069500 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 149276619912 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 149276619912 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 30060531759 # number of WriteLineReq miss cycles
< system.cpu0.dcache.WriteLineReq_miss_latency::total 30060531759 # number of WriteLineReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4170219500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 4170219500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4536657500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 4536657500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2221500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2221500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 285924221171 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 285924221171 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 285924221171 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 285924221171 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 90276551 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 90276551 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 77499003 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 77499003 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 952272 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 952272 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 944085 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::total 944085 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2149453 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 2149453 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2112219 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 2112219 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 168719639 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 168719639 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 169671911 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 169671911 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.078064 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.078064 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.100624 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.100624 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.788129 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788129 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.843187 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::total 0.843187 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.133052 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.133052 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089814 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089814 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092708 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.092708 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096611 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.096611 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15124.388282 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 15124.388282 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19142.332765 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 19142.332765 # average WriteReq miss latency
< system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 37762.589517 # average WriteLineReq miss latency
< system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 37762.589517 # average WriteLineReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14581.696912 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14581.696912 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23914.022677 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23914.022677 # average StoreCondReq miss latency
---
> system.cpu0.commit.op_class_0::total 561723659 # Class of committed instruction
> system.cpu0.commit.bw_lim_events 14069467 # number cycles where commit BW limit reached
> system.cpu0.rob.rob_reads 1336864700 # The number of ROB reads
> system.cpu0.rob.rob_writes 1228532736 # The number of ROB writes
> system.cpu0.timesIdled 1001309 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu0.idleCycles 26869869 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.quiesceCycles 93988523944 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.committedInsts 478330111 # Number of Instructions Simulated
> system.cpu0.committedOps 561723659 # Number of Ops (including micro ops) Simulated
> system.cpu0.cpi 1.633519 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 1.633519 # CPI: Total CPI of All Threads
> system.cpu0.ipc 0.612175 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 0.612175 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 705719528 # number of integer regfile reads
> system.cpu0.int_regfile_writes 419138035 # number of integer regfile writes
> system.cpu0.fp_regfile_reads 669802 # number of floating regfile reads
> system.cpu0.fp_regfile_writes 321532 # number of floating regfile writes
> system.cpu0.cc_regfile_reads 129631161 # number of cc regfile reads
> system.cpu0.cc_regfile_writes 130314957 # number of cc regfile writes
> system.cpu0.misc_regfile_reads 1341639409 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 16172326 # number of misc regfile writes
> system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.cpu0.dcache.tags.replacements 6359267 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 478.495579 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 158196405 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 6359779 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 24.874513 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 2049282000 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.495579 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.934562 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.934562 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
> system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu0.dcache.tags.tag_accesses 355337560 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 355337560 # Number of data accesses
> system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.cpu0.dcache.ReadReq_hits::cpu0.data 83119639 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 83119639 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 70042361 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 70042361 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 205739 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 205739 # number of SoftPFReq hits
> system.cpu0.dcache.WriteLineReq_hits::cpu0.data 143941 # number of WriteLineReq hits
> system.cpu0.dcache.WriteLineReq_hits::total 143941 # number of WriteLineReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1893040 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 1893040 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1948071 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 1948071 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 153305941 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 153305941 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 153511680 # number of overall hits
> system.cpu0.dcache.overall_hits::total 153511680 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 7167523 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 7167523 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 7883078 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 7883078 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 755741 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 755741 # number of SoftPFReq misses
> system.cpu0.dcache.WriteLineReq_misses::cpu0.data 796292 # number of WriteLineReq misses
> system.cpu0.dcache.WriteLineReq_misses::total 796292 # number of WriteLineReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 289192 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 289192 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 197314 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 197314 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 15846893 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 15846893 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 16602634 # number of overall misses
> system.cpu0.dcache.overall_misses::total 16602634 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 116616484000 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 116616484000 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 160918615442 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 160918615442 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 30600076090 # number of WriteLineReq miss cycles
> system.cpu0.dcache.WriteLineReq_miss_latency::total 30600076090 # number of WriteLineReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4458676000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 4458676000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4713253000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 4713253000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2519000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2519000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 308135175532 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 308135175532 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 308135175532 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 308135175532 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 90287162 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 90287162 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 77925439 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 77925439 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 961480 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 961480 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 940233 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::total 940233 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2182232 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 2182232 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2145385 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 2145385 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 169152834 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 169152834 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 170114314 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 170114314 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.079386 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.079386 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.101162 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.101162 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.786018 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.786018 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.846909 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::total 0.846909 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.132521 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.132521 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.091971 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.091971 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.093684 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.093684 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097597 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.097597 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16270.123444 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 16270.123444 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20413.170521 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 20413.170521 # average WriteReq miss latency
> system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 38428.209865 # average WriteLineReq miss latency
> system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 38428.209865 # average WriteLineReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15417.701734 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15417.701734 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23887.068328 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23887.068328 # average StoreCondReq miss latency
1006,1101c1020,1115
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18279.671337 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 18279.671337 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17442.739019 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 17442.739019 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 9136124 # number of cycles access was blocked
< system.cpu0.dcache.blocked_cycles::no_targets 22955799 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_mshrs 744485 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_targets 773832 # number of cycles access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.271737 # average number of cycles each access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_targets 29.665094 # average number of cycles each access was blocked
< system.cpu0.dcache.writebacks::writebacks 6279393 # number of writebacks
< system.cpu0.dcache.writebacks::total 6279393 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3627313 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 3627313 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6268862 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 6268862 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4039 # number of WriteLineReq MSHR hits
< system.cpu0.dcache.WriteLineReq_mshr_hits::total 4039 # number of WriteLineReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 145852 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 145852 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 9900214 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 9900214 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 9900214 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 9900214 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3420051 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 3420051 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1529384 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 1529384 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 743716 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 743716 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 792001 # number of WriteLineReq MSHR misses
< system.cpu0.dcache.WriteLineReq_mshr_misses::total 792001 # number of WriteLineReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 140138 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 140138 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 189707 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 189707 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 5741436 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 5741436 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 6485152 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 6485152 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17085 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17085 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18834 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18834 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 35919 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.overall_mshr_uncacheable_misses::total 35919 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 49260241500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 49260241500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 32250000948 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 32250000948 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16897998500 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16897998500 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 29124405259 # number of WriteLineReq MSHR miss cycles
< system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 29124405259 # number of WriteLineReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1866604500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1866604500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4347004500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4347004500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2167500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2167500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 110634647707 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 110634647707 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 127532646207 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 127532646207 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3215151000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3215151000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3215151000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3215151000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037884 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037884 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019734 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019734 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.780991 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.780991 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.838909 # mshr miss rate for WriteLineReq accesses
< system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.838909 # mshr miss rate for WriteLineReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065197 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065197 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089814 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089814 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034029 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.034029 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038222 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.038222 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14403.364599 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14403.364599 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21086.921890 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21086.921890 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22721.036659 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22721.036659 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 36773.192533 # average WriteLineReq mshr miss latency
< system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36773.192533 # average WriteLineReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13319.759808 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13319.759808 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22914.307327 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22914.307327 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19444.516697 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 19444.516697 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18559.415062 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 18559.415062 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 9297521 # number of cycles access was blocked
> system.cpu0.dcache.blocked_cycles::no_targets 24817691 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_mshrs 744023 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_targets 779199 # number of cycles access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.496282 # average number of cycles each access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_targets 31.850260 # average number of cycles each access was blocked
> system.cpu0.dcache.writebacks::writebacks 6359403 # number of writebacks
> system.cpu0.dcache.writebacks::total 6359403 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3686639 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 3686639 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6327255 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 6327255 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4271 # number of WriteLineReq MSHR hits
> system.cpu0.dcache.WriteLineReq_mshr_hits::total 4271 # number of WriteLineReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 148971 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 148971 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 10018165 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 10018165 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 10018165 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 10018165 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3480884 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 3480884 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1555823 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 1555823 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 748893 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 748893 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 792021 # number of WriteLineReq MSHR misses
> system.cpu0.dcache.WriteLineReq_mshr_misses::total 792021 # number of WriteLineReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 140221 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 140221 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 197311 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 197311 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 5828728 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 5828728 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 6577621 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 6577621 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16980 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16980 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18801 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18801 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 35781 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 35781 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 53164892500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 53164892500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 34944889021 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 34944889021 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18458336500 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18458336500 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 29638184090 # number of WriteLineReq MSHR miss cycles
> system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 29638184090 # number of WriteLineReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1982757000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1982757000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4516003000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4516003000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2458000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2458000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 117747965611 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 117747965611 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 136206302111 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 136206302111 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3133590500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3133590500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3133590500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3133590500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.038553 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038553 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019966 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019966 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.778896 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.778896 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.842367 # mshr miss rate for WriteLineReq accesses
> system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.842367 # mshr miss rate for WriteLineReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064256 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064256 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.091970 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.091970 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034458 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.034458 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038666 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.038666 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15273.388168 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15273.388168 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22460.709876 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22460.709876 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24647.495036 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24647.495036 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 37420.957386 # average WriteLineReq mshr miss latency
> system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 37420.957386 # average WriteLineReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14140.228639 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14140.228639 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22887.740673 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22887.740673 # average StoreCondReq mshr miss latency
1104,1121c1118,1135
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19269.508135 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19269.508135 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19665.328771 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19665.328771 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188185.601405 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188185.601405 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89511.150088 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89511.150088 # average overall mshr uncacheable latency
< system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.cpu0.icache.tags.replacements 5960489 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.962298 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 213927686 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 5961001 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 35.887880 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 13033031000 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.962298 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999926 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.999926 # Average percentage of cache occupancy
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20201.314182 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20201.314182 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20707.532725 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20707.532725 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184545.965842 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184545.965842 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87576.940276 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87576.940276 # average overall mshr uncacheable latency
> system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.cpu0.icache.tags.replacements 6086800 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.960315 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 213393241 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 6087312 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 35.055414 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 13476237000 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960315 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999922 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.999922 # Average percentage of cache occupancy
1123,1125c1137,1139
< system.cpu0.icache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id
1127,1185c1141,1199
< system.cpu0.icache.tags.tag_accesses 446443685 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 446443685 # Number of data accesses
< system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.cpu0.icache.ReadReq_hits::cpu0.inst 213927686 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 213927686 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 213927686 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 213927686 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 213927686 # number of overall hits
< system.cpu0.icache.overall_hits::total 213927686 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 6313628 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 6313628 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 6313628 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 6313628 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 6313628 # number of overall misses
< system.cpu0.icache.overall_misses::total 6313628 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 68941695345 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 68941695345 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 68941695345 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 68941695345 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 68941695345 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 68941695345 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 220241314 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 220241314 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 220241314 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 220241314 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 220241314 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 220241314 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028667 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.028667 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028667 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.028667 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028667 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.028667 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10919.505448 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 10919.505448 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10919.505448 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 10919.505448 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10919.505448 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 10919.505448 # average overall miss latency
< system.cpu0.icache.blocked_cycles::no_mshrs 10186888 # number of cycles access was blocked
< system.cpu0.icache.blocked_cycles::no_targets 465 # number of cycles access was blocked
< system.cpu0.icache.blocked::no_mshrs 736848 # number of cycles access was blocked
< system.cpu0.icache.blocked::no_targets 9 # number of cycles access was blocked
< system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.824952 # average number of cycles each access was blocked
< system.cpu0.icache.avg_blocked_cycles::no_targets 51.666667 # average number of cycles each access was blocked
< system.cpu0.icache.writebacks::writebacks 5960489 # number of writebacks
< system.cpu0.icache.writebacks::total 5960489 # number of writebacks
< system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 352571 # number of ReadReq MSHR hits
< system.cpu0.icache.ReadReq_mshr_hits::total 352571 # number of ReadReq MSHR hits
< system.cpu0.icache.demand_mshr_hits::cpu0.inst 352571 # number of demand (read+write) MSHR hits
< system.cpu0.icache.demand_mshr_hits::total 352571 # number of demand (read+write) MSHR hits
< system.cpu0.icache.overall_mshr_hits::cpu0.inst 352571 # number of overall MSHR hits
< system.cpu0.icache.overall_mshr_hits::total 352571 # number of overall MSHR hits
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5961057 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 5961057 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 5961057 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 5961057 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 5961057 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 5961057 # number of overall MSHR misses
---
> system.cpu0.icache.tags.tag_accesses 445759262 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 445759262 # Number of data accesses
> system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.cpu0.icache.ReadReq_hits::cpu0.inst 213393241 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 213393241 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 213393241 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 213393241 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 213393241 # number of overall hits
> system.cpu0.icache.overall_hits::total 213393241 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 6442715 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 6442715 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 6442715 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 6442715 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 6442715 # number of overall misses
> system.cpu0.icache.overall_misses::total 6442715 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 71477790896 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 71477790896 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 71477790896 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 71477790896 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 71477790896 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 71477790896 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 219835956 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 219835956 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 219835956 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 219835956 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 219835956 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 219835956 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029307 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.029307 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029307 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.029307 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029307 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.029307 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11094.358651 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 11094.358651 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11094.358651 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 11094.358651 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11094.358651 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 11094.358651 # average overall miss latency
> system.cpu0.icache.blocked_cycles::no_mshrs 10557387 # number of cycles access was blocked
> system.cpu0.icache.blocked_cycles::no_targets 2753 # number of cycles access was blocked
> system.cpu0.icache.blocked::no_mshrs 752829 # number of cycles access was blocked
> system.cpu0.icache.blocked::no_targets 14 # number of cycles access was blocked
> system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.023619 # average number of cycles each access was blocked
> system.cpu0.icache.avg_blocked_cycles::no_targets 196.642857 # average number of cycles each access was blocked
> system.cpu0.icache.writebacks::writebacks 6086800 # number of writebacks
> system.cpu0.icache.writebacks::total 6086800 # number of writebacks
> system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 355365 # number of ReadReq MSHR hits
> system.cpu0.icache.ReadReq_mshr_hits::total 355365 # number of ReadReq MSHR hits
> system.cpu0.icache.demand_mshr_hits::cpu0.inst 355365 # number of demand (read+write) MSHR hits
> system.cpu0.icache.demand_mshr_hits::total 355365 # number of demand (read+write) MSHR hits
> system.cpu0.icache.overall_mshr_hits::cpu0.inst 355365 # number of overall MSHR hits
> system.cpu0.icache.overall_mshr_hits::total 355365 # number of overall MSHR hits
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6087350 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 6087350 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 6087350 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 6087350 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 6087350 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 6087350 # number of overall MSHR misses
1190,1219c1204,1233
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 62354110053 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 62354110053 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 62354110053 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 62354110053 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 62354110053 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 62354110053 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1885677498 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::total 1885677498 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027066 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027066 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027066 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.027066 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027066 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.027066 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10460.243888 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10460.243888 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10460.243888 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 10460.243888 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10460.243888 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 10460.243888 # average overall mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average ReadReq mshr uncacheable latency
< system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753 # average ReadReq mshr uncacheable latency
< system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average overall mshr uncacheable latency
< system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753 # average overall mshr uncacheable latency
< system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.cpu0.l2cache.prefetcher.num_hwpf_issued 8592940 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.pfIdentified 8600926 # number of prefetch candidates identified
< system.cpu0.l2cache.prefetcher.pfBufferHit 7220 # number of redundant prefetches already in prefetch queue
---
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64448796094 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 64448796094 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64448796094 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 64448796094 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64448796094 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 64448796094 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2027158498 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2027158498 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2027158498 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::total 2027158498 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027690 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027690 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027690 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.027690 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027690 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.027690 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10587.332106 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10587.332106 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10587.332106 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 10587.332106 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10587.332106 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 10587.332106 # average overall mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856 # average ReadReq mshr uncacheable latency
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95203.047856 # average ReadReq mshr uncacheable latency
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856 # average overall mshr uncacheable latency
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95203.047856 # average overall mshr uncacheable latency
> system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.cpu0.l2cache.prefetcher.num_hwpf_issued 8595677 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.pfIdentified 8603285 # number of prefetch candidates identified
> system.cpu0.l2cache.prefetcher.pfBufferHit 6909 # number of redundant prefetches already in prefetch queue
1222,1246c1236,1261
< system.cpu0.l2cache.prefetcher.pfSpanPage 1116114 # number of prefetches not generated due to page crossing
< system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.cpu0.l2cache.tags.replacements 2719287 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 15847.951353 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 10783985 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 2734787 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 3.943263 # Average number of references to valid blocks.
< system.cpu0.l2cache.tags.warmup_cycle 2212469000 # Cycle when the warmup percentage was hit.
< system.cpu0.l2cache.tags.occ_blocks::writebacks 15472.818870 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 33.262850 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 18.351912 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 323.517722 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.944386 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002030 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001120 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.019746 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.967282 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 300 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 111 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15089 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 95 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 82 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 118 # Occupied blocks per task id
---
> system.cpu0.l2cache.prefetcher.pfSpanPage 1123339 # number of prefetches not generated due to page crossing
> system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.cpu0.l2cache.tags.replacements 2781248 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 15839.093178 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 10966307 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 2797118 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 3.920574 # Average number of references to valid blocks.
> system.cpu0.l2cache.tags.warmup_cycle 2357977000 # Cycle when the warmup percentage was hit.
> system.cpu0.l2cache.tags.occ_blocks::writebacks 15519.164563 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 33.011471 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 18.049668 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000001 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 268.867475 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.947215 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002015 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001102 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.016410 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.966742 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 337 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 83 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15450 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 131 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 116 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 88 # Occupied blocks per task id
1248,1387c1263,1398
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 22 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 45 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2056 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7291 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3067 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2287 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018311 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006775 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.920959 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 426577615 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 426577615 # Number of data accesses
< system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 609078 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 186922 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 796000 # number of ReadReq hits
< system.cpu0.l2cache.WritebackDirty_hits::writebacks 4110828 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackDirty_hits::total 4110828 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackClean_hits::writebacks 8127250 # number of WritebackClean hits
< system.cpu0.l2cache.WritebackClean_hits::total 8127250 # number of WritebackClean hits
< system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 41 # number of UpgradeReq hits
< system.cpu0.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 991441 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 991441 # number of ReadExReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5365262 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::total 5365262 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3250561 # number of ReadSharedReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::total 3250561 # number of ReadSharedReq hits
< system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 179546 # number of InvalidateReq hits
< system.cpu0.l2cache.InvalidateReq_hits::total 179546 # number of InvalidateReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 609078 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 186922 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 5365262 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 4242002 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 10403264 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 609078 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 186922 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 5365262 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 4242002 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 10403264 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 23667 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 12082 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 35749 # number of ReadReq misses
< system.cpu0.l2cache.WritebackClean_misses::writebacks 2 # number of WritebackClean misses
< system.cpu0.l2cache.WritebackClean_misses::total 2 # number of WritebackClean misses
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 259915 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 259915 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 189699 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 189699 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 286982 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 286982 # number of ReadExReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 595762 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::total 595762 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1051075 # number of ReadSharedReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::total 1051075 # number of ReadSharedReq misses
< system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 610539 # number of InvalidateReq misses
< system.cpu0.l2cache.InvalidateReq_misses::total 610539 # number of InvalidateReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 23667 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 12082 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 595762 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 1338057 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 1969568 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 23667 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 12082 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 595762 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 1338057 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 1969568 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 824553000 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 534370500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 1358923500 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 956036000 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 956036000 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 288541500 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 288541500 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2086500 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2086500 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16444485496 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 16444485496 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 20913606500 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::total 20913606500 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 39888753486 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::total 39888753486 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 293901000 # number of InvalidateReq miss cycles
< system.cpu0.l2cache.InvalidateReq_miss_latency::total 293901000 # number of InvalidateReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 824553000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 534370500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 20913606500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 56333238982 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 78605768982 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 824553000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 534370500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 20913606500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 56333238982 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 78605768982 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 632745 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 199004 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 831749 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4110828 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::total 4110828 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::writebacks 8127252 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::total 8127252 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 259956 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 259956 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 189704 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 189704 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1278423 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 1278423 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5961024 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::total 5961024 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4301636 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::total 4301636 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 790085 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::total 790085 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 632745 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 199004 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 5961024 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 5580059 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 12372832 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 632745 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 199004 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 5961024 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 5580059 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 12372832 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.037404 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.060712 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.042981 # miss rate for ReadReq accesses
< system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses
< system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999842 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999842 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999974 # miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999974 # miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 205 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1708 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7197 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4776 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1564 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.020569 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005066 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.942993 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 434183760 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 434183760 # Number of data accesses
> system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 639992 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 185315 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 825307 # number of ReadReq hits
> system.cpu0.l2cache.WritebackDirty_hits::writebacks 4159646 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackDirty_hits::total 4159646 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackClean_hits::writebacks 8284827 # number of WritebackClean hits
> system.cpu0.l2cache.WritebackClean_hits::total 8284827 # number of WritebackClean hits
> system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 23 # number of UpgradeReq hits
> system.cpu0.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 995756 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 995756 # number of ReadExReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5493946 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::total 5493946 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3273779 # number of ReadSharedReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::total 3273779 # number of ReadSharedReq hits
> system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 166627 # number of InvalidateReq hits
> system.cpu0.l2cache.InvalidateReq_hits::total 166627 # number of InvalidateReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 639992 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 185315 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 5493946 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 4269535 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 10588788 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 639992 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 185315 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 5493946 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 4269535 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 10588788 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 23429 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 11592 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 35021 # number of ReadReq misses
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 269158 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 269158 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 197304 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 197304 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 301043 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 301043 # number of ReadExReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 593373 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::total 593373 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1093007 # number of ReadSharedReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::total 1093007 # number of ReadSharedReq misses
> system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 623543 # number of InvalidateReq misses
> system.cpu0.l2cache.InvalidateReq_misses::total 623543 # number of InvalidateReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 23429 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 11592 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 593373 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 1394050 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 2022444 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 23429 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 11592 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 593373 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 1394050 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 2022444 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 862921500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 562577500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 1425499000 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 983366500 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 983366500 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 308777000 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 308777000 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2366500 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2366500 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 18857416997 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 18857416997 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 22027267000 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::total 22027267000 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 45190340989 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::total 45190340989 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 290057500 # number of InvalidateReq miss cycles
> system.cpu0.l2cache.InvalidateReq_miss_latency::total 290057500 # number of InvalidateReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 862921500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 562577500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22027267000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 64047757986 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 87500523986 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 862921500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 562577500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22027267000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 64047757986 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 87500523986 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 663421 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 196907 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 860328 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4159646 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::total 4159646 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::writebacks 8284827 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::total 8284827 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 269181 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 269181 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 197306 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 197306 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1296799 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 1296799 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6087319 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::total 6087319 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4366786 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::total 4366786 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 790170 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::total 790170 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 663421 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 196907 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 6087319 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 5663585 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 12611232 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 663421 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 196907 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 6087319 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 5663585 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 12611232 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.035315 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.058870 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.040707 # miss rate for ReadReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999915 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999915 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999990 # miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999990 # miss rate for SCUpgradeReq accesses
1390,1435c1401,1446
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.224481 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.224481 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.099943 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.099943 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.244343 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.244343 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.772751 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.772751 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.037404 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.060712 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.099943 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.239793 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.159185 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.037404 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.060712 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.099943 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.239793 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.159185 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34839.776905 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 44228.645920 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 38012.909452 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3678.264048 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3678.264048 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1521.049136 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1521.049136 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 695500 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 695500 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 57301.452690 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 57301.452690 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 35103.961817 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 35103.961817 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37950.435017 # average ReadSharedReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37950.435017 # average ReadSharedReq miss latency
< system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 481.379568 # average InvalidateReq miss latency
< system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 481.379568 # average InvalidateReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34839.776905 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 44228.645920 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 35103.961817 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 42100.776710 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 39910.157447 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34839.776905 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 44228.645920 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 35103.961817 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 42100.776710 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 39910.157447 # average overall miss latency
< system.cpu0.l2cache.blocked_cycles::no_mshrs 1132 # number of cycles access was blocked
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.232143 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.232143 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.097477 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.097477 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.250300 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.250300 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.789125 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.789125 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.035315 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.058870 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.097477 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.246143 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.160368 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.035315 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.058870 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.097477 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.246143 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.160368 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36831.341500 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 48531.530366 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 40704.120385 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3653.491629 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3653.491629 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1564.980943 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1564.980943 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 473300 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 473300 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 62640.277293 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 62640.277293 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37122.125543 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37122.125543 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41344.969418 # average ReadSharedReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41344.969418 # average ReadSharedReq miss latency
> system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 465.176419 # average InvalidateReq miss latency
> system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 465.176419 # average InvalidateReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36831.341500 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 48531.530366 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37122.125543 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45943.659113 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 43264.745024 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36831.341500 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 48531.530366 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37122.125543 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45943.659113 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 43264.745024 # average overall miss latency
> system.cpu0.l2cache.blocked_cycles::no_mshrs 1347 # number of cycles access was blocked
1437c1448
< system.cpu0.l2cache.blocked::no_mshrs 30 # number of cycles access was blocked
---
> system.cpu0.l2cache.blocked::no_mshrs 28 # number of cycles access was blocked
1439c1450
< system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 37.733333 # average number of cycles each access was blocked
---
> system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 48.107143 # average number of cycles each access was blocked
1441,1496c1452,1505
< system.cpu0.l2cache.unused_prefetches 48307 # number of HardPF blocks evicted w/o reference
< system.cpu0.l2cache.writebacks::writebacks 1757363 # number of writebacks
< system.cpu0.l2cache.writebacks::total 1757363 # number of writebacks
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 134 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 356 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_hits::total 490 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 18633 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 18633 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 5210 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 5210 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 3 # number of InvalidateReq MSHR hits
< system.cpu0.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 134 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 356 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 23843 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 24334 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 134 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 356 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 23843 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 24334 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 23533 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 11726 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 35259 # number of ReadReq MSHR misses
< system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 2 # number of WritebackClean MSHR misses
< system.cpu0.l2cache.WritebackClean_mshr_misses::total 2 # number of WritebackClean MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 887638 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 887638 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 259915 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 259915 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 189699 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 189699 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 268349 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 268349 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 595761 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 595761 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1045865 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1045865 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 610536 # number of InvalidateReq MSHR misses
< system.cpu0.l2cache.InvalidateReq_mshr_misses::total 610536 # number of InvalidateReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 23533 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 11726 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 595761 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1314214 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 1945234 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 23533 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 11726 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 595761 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1314214 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 887638 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 2832872 # number of overall MSHR misses
---
> system.cpu0.l2cache.unused_prefetches 49330 # number of HardPF blocks evicted w/o reference
> system.cpu0.l2cache.writebacks::writebacks 1802209 # number of writebacks
> system.cpu0.l2cache.writebacks::total 1802209 # number of writebacks
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 136 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 303 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::total 439 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 20845 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 20845 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 2 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 4784 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 4784 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 6 # number of InvalidateReq MSHR hits
> system.cpu0.l2cache.InvalidateReq_mshr_hits::total 6 # number of InvalidateReq MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 136 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 303 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 25629 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 26070 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 136 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 303 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 25629 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 26070 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 23293 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 11289 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 34582 # number of ReadReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 895757 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 895757 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 269158 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 269158 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 197304 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 197304 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 280198 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 280198 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 593371 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 593371 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1088223 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1088223 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 623537 # number of InvalidateReq MSHR misses
> system.cpu0.l2cache.InvalidateReq_mshr_misses::total 623537 # number of InvalidateReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 23293 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 11289 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 593371 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1368421 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 1996374 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 23293 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 11289 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 593371 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1368421 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 895757 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 2892131 # number of overall MSHR misses
1498,1501c1507,1510
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 17085 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 38378 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 18834 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 18834 # number of WriteReq MSHR uncacheable
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 16980 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 38273 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 18801 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 18801 # number of WriteReq MSHR uncacheable
1503,1545c1512,1552
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 35919 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 57212 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 680641500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 457877000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1138518500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 52792392844 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 52792392844 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4817060992 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4817060992 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2920885493 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2920885493 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1762500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1762500 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 12110424498 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 12110424498 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 17339026500 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 17339026500 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 33290154486 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 33290154486 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 22238992991 # number of InvalidateReq MSHR miss cycles
< system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 22238992991 # number of InvalidateReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 680641500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 457877000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 17339026500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 45400578984 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 63878123984 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 680641500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 457877000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 17339026500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 45400578984 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 52792392844 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 116670516828 # number of overall MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1725979000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3078004000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4803983000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1725979000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 3078004000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4803983000 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.037192 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.058923 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.042391 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
< system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
---
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 35781 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 57074 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 720471000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 489799000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1210270000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 58575065392 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 58575065392 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4984780995 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4984780995 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3032798496 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3032798496 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2000500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2000500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 14111841497 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14111841497 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 18467014500 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 18467014500 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 38294410989 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 38294410989 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 22764184995 # number of InvalidateReq MSHR miss cycles
> system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 22764184995 # number of InvalidateReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 720471000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 489799000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 18467014500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 52406252486 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 72083536986 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 720471000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 489799000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 18467014500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 52406252486 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 58575065392 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 130658602378 # number of overall MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1867460000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2997239500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4864699500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1867460000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 2997239500 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4864699500 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.035110 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057332 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.040196 # mshr miss rate for ReadReq accesses
1548,1551c1555,1558
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999842 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999842 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999974 # mshr miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999974 # mshr miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999915 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999915 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999990 # mshr miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999990 # mshr miss rate for SCUpgradeReq accesses
1554,1570c1561,1577
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.209906 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.209906 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.099943 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.099943 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.243132 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.243132 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.772747 # mshr miss rate for InvalidateReq accesses
< system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.772747 # mshr miss rate for InvalidateReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.037192 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.058923 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.099943 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.235520 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157218 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.037192 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.058923 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.099943 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.235520 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.216069 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.216069 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.097477 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097477 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.249205 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249205 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.789118 # mshr miss rate for InvalidateReq accesses
> system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.789118 # mshr miss rate for InvalidateReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.035110 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057332 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.097477 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.241617 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.158301 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.035110 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057332 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.097477 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.241617 # mshr miss rate for overall accesses
1572,1651c1579,1658
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.228959 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28922.853015 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 39048.012963 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 32290.152869 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59475.138338 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59475.138338 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18533.216598 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18533.216598 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15397.474383 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15397.474383 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 587500 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 587500 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45129.381880 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45129.381880 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29103.997241 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29103.997241 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31830.259628 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31830.259628 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36425.359014 # average InvalidateReq mshr miss latency
< system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36425.359014 # average InvalidateReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28922.853015 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 39048.012963 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29103.997241 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34545.803791 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32838.272405 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28922.853015 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 39048.012963 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29103.997241 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34545.803791 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59475.138338 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41184.535280 # average overall mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180158.267486 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125175.439054 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85692.920182 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 83968.101098 # average overall mshr uncacheable latency
< system.cpu0.toL2Bus.snoop_filter.tot_requests 25397703 # Total number of requests made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13066663 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1795 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.snoop_filter.tot_snoops 671473 # Total number of snoops made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 671468 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.cpu0.toL2Bus.trans_dist::ReadReq 963728 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 11315166 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 18834 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 18834 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackDirty 5872564 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackClean 8129050 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::CleanEvict 1348327 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 1122615 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFResp 22 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 466810 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 338240 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 510310 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 1307620 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 1285212 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5961057 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5219350 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateReq 843100 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateResp 790085 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17925156 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20147173 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 419117 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1337980 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 39829426 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 763317520 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 765224037 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1592032 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5061960 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 1535195549 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 5838031 # Total snoops (count)
< system.cpu0.toL2Bus.snoopTraffic 119621704 # Total snoop traffic (bytes)
< system.cpu0.toL2Bus.snoop_fanout::samples 19351504 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 0.054273 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.226556 # Request fanout histogram
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229330 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30930.794659 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43387.279653 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34997.108322 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65391.691488 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65391.691488 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18519.906505 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18519.906505 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15371.196205 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15371.196205 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 400100 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 400100 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 50363.819503 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 50363.819503 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31122.206006 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31122.206006 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35189.856297 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35189.856297 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36508.154280 # average InvalidateReq mshr miss latency
> system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36508.154280 # average InvalidateReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30930.794659 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43387.279653 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31122.206006 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38296.878290 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36107.230903 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30930.794659 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43387.279653 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31122.206006 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38296.878290 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65391.691488 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45177.276679 # average overall mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176515.871614 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 127105.256970 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 83766.230681 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85234.949364 # average overall mshr uncacheable latency
> system.cpu0.toL2Bus.snoop_filter.tot_requests 25828303 # Total number of requests made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13287358 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1712 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.snoop_filter.tot_snoops 676521 # Total number of snoops made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 676518 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.cpu0.toL2Bus.trans_dist::ReadReq 990165 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 11537181 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 18801 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 18801 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackDirty 5966642 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackClean 8286555 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::CleanEvict 1378403 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 1136481 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFResp 14 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 480580 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352407 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 530357 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 1327096 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 1303956 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6087350 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5339261 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateReq 842479 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateResp 790170 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18304055 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20435509 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 413815 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1398403 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 40551782 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 779484304 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 775974521 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1575256 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5307368 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 1562341449 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 5999180 # Total snoops (count)
> system.cpu0.toL2Bus.snoopTraffic 122789024 # Total snoop traffic (bytes)
> system.cpu0.toL2Bus.snoop_fanout::samples 19760108 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 0.053277 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.224586 # Request fanout histogram
1653,1655c1660,1662
< system.cpu0.toL2Bus.snoop_fanout::0 18301249 94.57% 94.57% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::1 1050250 5.43% 100.00% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::2 5 0.00% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::0 18707349 94.67% 94.67% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::1 1052756 5.33% 100.00% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram
1659,1660c1666,1667
< system.cpu0.toL2Bus.snoop_fanout::total 19351504 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 25250991712 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 19760108 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 25687014453 # Layer occupancy (ticks)
1662c1669
< system.cpu0.toL2Bus.snoopLayer0.occupancy 173970437 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 182391125 # Layer occupancy (ticks)
1664c1671
< system.cpu0.toL2Bus.respLayer0.occupancy 8969219750 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 9158694684 # Layer occupancy (ticks)
1666c1673
< system.cpu0.toL2Bus.respLayer1.occupancy 9025116687 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 9158841551 # Layer occupancy (ticks)
1668c1675
< system.cpu0.toL2Bus.respLayer2.occupancy 220608496 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 217386526 # Layer occupancy (ticks)
1670c1677
< system.cpu0.toL2Bus.respLayer3.occupancy 706093257 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 735766915 # Layer occupancy (ticks)
1672,1676c1679,1683
< system.cpu1.branchPred.lookups 128968222 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 85282466 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 6518355 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 89675287 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 55364340 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 134369829 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 89463085 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 6609561 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 94230263 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 58109960 # Number of BTB hits
1678,1685c1685,1692
< system.cpu1.branchPred.BTBHitPct 61.738682 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 17439644 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 182879 # Number of incorrect RAS predictions.
< system.cpu1.branchPred.indirectLookups 4134289 # Number of indirect predictor lookups.
< system.cpu1.branchPred.indirectHits 2557852 # Number of indirect target hits.
< system.cpu1.branchPred.indirectMisses 1576437 # Number of indirect misses.
< system.cpu1.branchPredindirectMispredicted 401535 # Number of mispredicted indirect branches.
< system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
---
> system.cpu1.branchPred.BTBHitPct 61.668044 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 17839939 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 183627 # Number of incorrect RAS predictions.
> system.cpu1.branchPred.indirectLookups 4347444 # Number of indirect predictor lookups.
> system.cpu1.branchPred.indirectHits 2695405 # Number of indirect target hits.
> system.cpu1.branchPred.indirectMisses 1652039 # Number of indirect misses.
> system.cpu1.branchPredindirectMispredicted 417102 # Number of mispredicted indirect branches.
> system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
1715,1776c1722,1773
< system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.cpu1.dtb.walker.walks 531460 # Table walker walks requested
< system.cpu1.dtb.walker.walksLong 531460 # Table walker walks initiated with long descriptors
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10155 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 82594 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walksSquashedBefore 244261 # Table walks squashed before starting
< system.cpu1.dtb.walker.walkWaitTime::samples 287199 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::mean 2189.199823 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::stdev 12408.912934 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0-32767 282304 98.30% 98.30% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::32768-65535 2996 1.04% 99.34% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::65536-98303 743 0.26% 99.60% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::98304-131071 602 0.21% 99.81% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::131072-163839 197 0.07% 99.88% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::163840-196607 152 0.05% 99.93% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::196608-229375 103 0.04% 99.96% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::229376-262143 33 0.01% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::262144-294911 16 0.01% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::294912-327679 35 0.01% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::327680-360447 11 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::425984-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::total 287199 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkCompletionTime::samples 267684 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::mean 20635.114538 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::gmean 18133.747768 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::stdev 11911.787641 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::0-32767 239914 89.63% 89.63% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::32768-65535 26330 9.84% 99.46% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::65536-98303 756 0.28% 99.74% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::98304-131071 476 0.18% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::131072-163839 73 0.03% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::163840-196607 24 0.01% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::196608-229375 55 0.02% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::229376-262143 22 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::262144-294911 9 0.00% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::294912-327679 8 0.00% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::327680-360447 3 0.00% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::360448-393215 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::425984-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::total 267684 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walksPending::samples 465694213496 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::mean 0.593113 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::stdev 0.550788 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::0-1 464589649996 99.76% 99.76% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::2-3 559093500 0.12% 99.88% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::4-5 239052500 0.05% 99.93% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::6-7 120378000 0.03% 99.96% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::8-9 87009500 0.02% 99.98% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::10-11 57335500 0.01% 99.99% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::12-13 14978500 0.00% 99.99% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::14-15 26310000 0.01% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::16-17 396500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::18-19 9500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::total 465694213496 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walkPageSizes::4K 82595 89.05% 89.05% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::2M 10155 10.95% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 92750 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 531460 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.cpu1.dtb.walker.walks 561952 # Table walker walks requested
> system.cpu1.dtb.walker.walksLong 561952 # Table walker walks initiated with long descriptors
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11814 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 88087 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walksSquashedBefore 261651 # Table walks squashed before starting
> system.cpu1.dtb.walker.walkWaitTime::samples 300301 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::mean 2363.057399 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::stdev 13317.227915 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0-65535 298048 99.25% 99.25% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::65536-131071 1567 0.52% 99.77% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::131072-196607 436 0.15% 99.92% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::196608-262143 167 0.06% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::262144-327679 36 0.01% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::327680-393215 40 0.01% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::total 300301 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkCompletionTime::samples 287935 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::mean 21029.369476 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::gmean 18280.568505 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::stdev 15111.837725 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::0-65535 285795 99.26% 99.26% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1436 0.50% 99.76% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::131072-196607 377 0.13% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::196608-262143 181 0.06% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::262144-327679 86 0.03% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::327680-393215 29 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::393216-458751 11 0.00% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::589824-655359 16 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::total 287935 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walksPending::samples 466714959496 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::mean 0.597643 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::stdev 0.555516 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::0-1 465490623496 99.74% 99.74% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::2-3 621983000 0.13% 99.87% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::4-5 266845500 0.06% 99.93% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::6-7 131382500 0.03% 99.96% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::8-9 96036000 0.02% 99.98% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::10-11 60845000 0.01% 99.99% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::12-13 18797500 0.00% 99.99% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::14-15 27878000 0.01% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::16-17 546500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::18-19 22000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::total 466714959496 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walkPageSizes::4K 88088 88.17% 88.17% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::2M 11814 11.83% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 99902 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 561952 # Table walker requests started/completed, data/inst
1778,1779c1775,1776
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 531460 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92750 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 561952 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 99902 # Table walker requests started/completed, data/inst
1781,1782c1778,1779
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92750 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 624210 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 99902 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 661854 # Table walker requests started/completed, data/inst
1785,1789c1782,1786
< system.cpu1.dtb.read_hits 93944307 # DTB read hits
< system.cpu1.dtb.read_misses 364370 # DTB read misses
< system.cpu1.dtb.write_hits 78170381 # DTB write hits
< system.cpu1.dtb.write_misses 167090 # DTB write misses
< system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
---
> system.cpu1.dtb.read_hits 97791245 # DTB read hits
> system.cpu1.dtb.read_misses 385118 # DTB read misses
> system.cpu1.dtb.write_hits 81245431 # DTB write hits
> system.cpu1.dtb.write_misses 176834 # DTB write misses
> system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
1791,1795c1788,1792
< system.cpu1.dtb.flush_tlb_mva_asid 44145 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID
< system.cpu1.dtb.flush_entries 34720 # Number of entries that have been flushed from TLB
< system.cpu1.dtb.align_faults 381 # Number of TLB faults due to alignment restrictions
< system.cpu1.dtb.prefetch_faults 5735 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.flush_tlb_mva_asid 45792 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.dtb.flush_tlb_asid 1079 # Number of times TLB was flushed by ASID
> system.cpu1.dtb.flush_entries 36850 # Number of entries that have been flushed from TLB
> system.cpu1.dtb.align_faults 268 # Number of TLB faults due to alignment restrictions
> system.cpu1.dtb.prefetch_faults 6109 # Number of TLB faults due to prefetch
1797,1799c1794,1796
< system.cpu1.dtb.perms_faults 39000 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 94308677 # DTB read accesses
< system.cpu1.dtb.write_accesses 78337471 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 40755 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 98176363 # DTB read accesses
> system.cpu1.dtb.write_accesses 81422265 # DTB write accesses
1801,1804c1798,1801
< system.cpu1.dtb.hits 172114688 # DTB hits
< system.cpu1.dtb.misses 531460 # DTB misses
< system.cpu1.dtb.accesses 172646148 # DTB accesses
< system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
---
> system.cpu1.dtb.hits 179036676 # DTB hits
> system.cpu1.dtb.misses 561952 # DTB misses
> system.cpu1.dtb.accesses 179598628 # DTB accesses
> system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
1834,1885c1831,1876
< system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.cpu1.itb.walker.walks 82381 # Table walker walks requested
< system.cpu1.itb.walker.walksLong 82381 # Table walker walks initiated with long descriptors
< system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1018 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walksLongTerminationLevel::Level3 59631 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walksSquashedBefore 9853 # Table walks squashed before starting
< system.cpu1.itb.walker.walkWaitTime::samples 72528 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::mean 882.590172 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::stdev 6870.472006 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::0-32767 72114 99.43% 99.43% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::32768-65535 279 0.38% 99.81% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::65536-98303 39 0.05% 99.87% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::98304-131071 75 0.10% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::131072-163839 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::163840-196607 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::total 72528 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkCompletionTime::samples 70502 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::mean 24022.878784 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::gmean 22243.496704 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::stdev 12757.621468 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::0-32767 63844 90.56% 90.56% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::32768-65535 6070 8.61% 99.17% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::65536-98303 93 0.13% 99.30% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::98304-131071 382 0.54% 99.84% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::131072-163839 44 0.06% 99.90% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::163840-196607 19 0.03% 99.93% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::196608-229375 18 0.03% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::229376-262143 8 0.01% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::294912-327679 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::total 70502 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walksPending::samples 379792000076 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::mean 0.874646 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::stdev 0.331269 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::0 47625596788 12.54% 12.54% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::1 332150851288 87.46% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::2 14331500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::3 990000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::4 230500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::total 379792000076 # Table walker pending requests distribution
< system.cpu1.itb.walker.walkPageSizes::4K 59631 98.32% 98.32% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::2M 1018 1.68% 100.00% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::total 60649 # Table walker page sizes translated
---
> system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.cpu1.itb.walker.walks 84407 # Table walker walks requested
> system.cpu1.itb.walker.walksLong 84407 # Table walker walks initiated with long descriptors
> system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1027 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walksLongTerminationLevel::Level3 60740 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walksSquashedBefore 10156 # Table walks squashed before starting
> system.cpu1.itb.walker.walkWaitTime::samples 74251 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::mean 1057.238286 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::stdev 8622.114888 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::0-65535 74015 99.68% 99.68% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::65536-131071 199 0.27% 99.95% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::131072-196607 18 0.02% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::196608-262143 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::262144-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::327680-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::total 74251 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkCompletionTime::samples 71923 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::mean 24988.821378 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::gmean 22597.090075 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::stdev 18666.984039 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::0-65535 70820 98.47% 98.47% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::65536-131071 715 0.99% 99.46% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::131072-196607 265 0.37% 99.83% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::196608-262143 63 0.09% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::262144-327679 24 0.03% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::327680-393215 16 0.02% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::589824-655359 10 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::total 71923 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walksPending::samples 410850107648 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::mean 0.878728 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::stdev 0.326631 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::0 49848543788 12.13% 12.13% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::1 360979116860 87.86% 99.99% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::2 21177000 0.01% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::3 1227500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::4 42500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::total 410850107648 # Table walker pending requests distribution
> system.cpu1.itb.walker.walkPageSizes::4K 60740 98.34% 98.34% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::2M 1027 1.66% 100.00% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::total 61767 # Table walker page sizes translated
1887,1888c1878,1879
< system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 82381 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Requested::total 82381 # Table walker requests started/completed, data/inst
---
> system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 84407 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Requested::total 84407 # Table walker requests started/completed, data/inst
1890,1894c1881,1885
< system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 60649 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Completed::total 60649 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin::total 143030 # Table walker requests started/completed, data/inst
< system.cpu1.itb.inst_hits 201934152 # ITB inst hits
< system.cpu1.itb.inst_misses 82381 # ITB inst misses
---
> system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61767 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61767 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin::total 146174 # Table walker requests started/completed, data/inst
> system.cpu1.itb.inst_hits 210802915 # ITB inst hits
> system.cpu1.itb.inst_misses 84407 # ITB inst misses
1899c1890
< system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
---
> system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
1901,1903c1892,1894
< system.cpu1.itb.flush_tlb_mva_asid 44145 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID
< system.cpu1.itb.flush_entries 24569 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_tlb_mva_asid 45792 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.itb.flush_tlb_asid 1079 # Number of times TLB was flushed by ASID
> system.cpu1.itb.flush_entries 26222 # Number of entries that have been flushed from TLB
1907c1898
< system.cpu1.itb.perms_faults 202631 # Number of TLB faults due to permissions restrictions
---
> system.cpu1.itb.perms_faults 208943 # Number of TLB faults due to permissions restrictions
1910,1926c1901,1915
< system.cpu1.itb.inst_accesses 202016533 # ITB inst accesses
< system.cpu1.itb.hits 201934152 # DTB hits
< system.cpu1.itb.misses 82381 # DTB misses
< system.cpu1.itb.accesses 202016533 # DTB accesses
< system.cpu1.numPwrStateTransitions 26784 # Number of power state transitions
< system.cpu1.pwrStateClkGateDist::samples 13392 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::mean 3512583180.059961 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::stdev 88770415671.353104 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::underflows 3351 25.02% 25.02% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::1000-5e+10 10014 74.78% 99.80% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.82% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 4 0.03% 99.85% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::3.5e+11-4e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
---
> system.cpu1.itb.inst_accesses 210887322 # ITB inst accesses
> system.cpu1.itb.hits 210802915 # DTB hits
> system.cpu1.itb.misses 84407 # DTB misses
> system.cpu1.itb.accesses 210887322 # DTB accesses
> system.cpu1.numPwrStateTransitions 27667 # Number of power state transitions
> system.cpu1.pwrStateClkGateDist::samples 13834 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::mean 3399006591.183533 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::stdev 87524078188.715500 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::underflows 3453 24.96% 24.96% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::1000-5e+10 10352 74.83% 99.79% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.04% 99.83% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
1931,1935c1920,1924
< system.cpu1.pwrStateClkGateDist::max_value 7430623145540 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateClkGateDist::total 13392 # Distribution of time spent in the clock gated state
< system.cpu1.pwrStateResidencyTicks::ON 343403762637 # Cumulative time (in ticks) in various power states
< system.cpu1.pwrStateResidencyTicks::CLK_GATED 47040513947363 # Cumulative time (in ticks) in various power states
< system.cpu1.numCycles 686817572 # number of cpu cycles simulated
---
> system.cpu1.pwrStateClkGateDist::max_value 7390880477084 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateClkGateDist::total 13834 # Distribution of time spent in the clock gated state
> system.cpu1.pwrStateResidencyTicks::ON 363085536567 # Cumulative time (in ticks) in various power states
> system.cpu1.pwrStateResidencyTicks::CLK_GATED 47021857182433 # Cumulative time (in ticks) in various power states
> system.cpu1.numCycles 726181462 # number of cpu cycles simulated
1938,1954c1927,1943
< system.cpu1.fetch.icacheStallCycles 87491536 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 569150585 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 128968222 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 75361836 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 564504137 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 14030828 # Number of cycles fetch has spent squashing
< system.cpu1.fetch.TlbCycles 1743458 # Number of cycles fetch has spent waiting for tlb
< system.cpu1.fetch.MiscStallCycles 273069 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu1.fetch.PendingTrapStallCycles 5670150 # Number of stall cycles due to pending traps
< system.cpu1.fetch.PendingQuiesceStallCycles 713565 # Number of stall cycles due to pending quiesce instructions
< system.cpu1.fetch.IcacheWaitRetryStallCycles 783781 # Number of stall cycles due to full MSHR
< system.cpu1.fetch.CacheLines 201710843 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 1678338 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.ItlbSquashes 26867 # Number of outstanding ITLB misses that were squashed
< system.cpu1.fetch.rateDist::samples 668195110 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 1.000138 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 1.225435 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.icacheStallCycles 86390303 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 594062843 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 134369829 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 78645304 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 601498232 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 14253482 # Number of cycles fetch has spent squashing
> system.cpu1.fetch.TlbCycles 1820697 # Number of cycles fetch has spent waiting for tlb
> system.cpu1.fetch.MiscStallCycles 287238 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu1.fetch.PendingTrapStallCycles 5988786 # Number of stall cycles due to pending traps
> system.cpu1.fetch.PendingQuiesceStallCycles 713679 # Number of stall cycles due to pending quiesce instructions
> system.cpu1.fetch.IcacheWaitRetryStallCycles 819715 # Number of stall cycles due to full MSHR
> system.cpu1.fetch.CacheLines 210572695 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 1658938 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.ItlbSquashes 27666 # Number of outstanding ITLB misses that were squashed
> system.cpu1.fetch.rateDist::samples 704645391 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 0.988963 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 1.222689 # Number of instructions fetched each cycle (Total)
1956,1959c1945,1948
< system.cpu1.fetch.rateDist::0 348421230 52.14% 52.14% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 124504424 18.63% 70.78% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 42025261 6.29% 77.07% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 153244195 22.93% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 370929364 52.64% 52.64% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 130277469 18.49% 71.13% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 43725033 6.21% 77.33% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 159713525 22.67% 100.00% # Number of instructions fetched each cycle (Total)
1963,2010c1952,1999
< system.cpu1.fetch.rateDist::total 668195110 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.187777 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 0.828678 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 102161242 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 311763510 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 215198558 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 34078749 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 4993051 # Number of cycles decode is squashing
< system.cpu1.decode.BranchResolved 18208977 # Number of times decode resolved a branch
< system.cpu1.decode.BranchMispred 2060516 # Number of times decode detected a branch misprediction
< system.cpu1.decode.DecodedInsts 590405276 # Number of instructions handled by decode
< system.cpu1.decode.SquashedInsts 22672761 # Number of squashed instructions handled by decode
< system.cpu1.rename.SquashCycles 4993051 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 135354794 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 41008219 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 216515907 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 215714387 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 54608752 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 573925738 # Number of instructions processed by rename
< system.cpu1.rename.SquashedInsts 5865325 # Number of squashed instructions processed by rename
< system.cpu1.rename.ROBFullEvents 9111156 # Number of times rename has blocked due to ROB full
< system.cpu1.rename.IQFullEvents 235226 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LQFullEvents 246551 # Number of times rename has blocked due to LQ full
< system.cpu1.rename.SQFullEvents 22706071 # Number of times rename has blocked due to SQ full
< system.cpu1.rename.FullRegisterEvents 10845 # Number of times there has been no free registers
< system.cpu1.rename.RenamedOperands 544713354 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 881414288 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 677140554 # Number of integer rename lookups
< system.cpu1.rename.fp_rename_lookups 799785 # Number of floating rename lookups
< system.cpu1.rename.CommittedMaps 489645115 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 55068233 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 14685141 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 12835902 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 68922736 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 94552173 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 81340147 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 8760661 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 7542596 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 552653279 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 14818656 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 556478216 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 2578197 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 52065959 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 33349277 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 259122 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 668195110 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 0.832808 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 1.070079 # Number of insts issued each cycle
---
> system.cpu1.fetch.rateDist::total 704645391 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.185036 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 0.818064 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 103020673 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 337373962 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 222407115 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 36734416 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 5109225 # Number of cycles decode is squashing
> system.cpu1.decode.BranchResolved 18739170 # Number of times decode resolved a branch
> system.cpu1.decode.BranchMispred 2055775 # Number of times decode detected a branch misprediction
> system.cpu1.decode.DecodedInsts 616426802 # Number of instructions handled by decode
> system.cpu1.decode.SquashedInsts 23026844 # Number of squashed instructions handled by decode
> system.cpu1.rename.SquashCycles 5109225 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 137867421 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 45074504 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 232811775 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 223900939 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 59881527 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 599411621 # Number of instructions processed by rename
> system.cpu1.rename.SquashedInsts 6042296 # Number of squashed instructions processed by rename
> system.cpu1.rename.ROBFullEvents 9969882 # Number of times rename has blocked due to ROB full
> system.cpu1.rename.IQFullEvents 242190 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LQFullEvents 299313 # Number of times rename has blocked due to LQ full
> system.cpu1.rename.SQFullEvents 25537080 # Number of times rename has blocked due to SQ full
> system.cpu1.rename.FullRegisterEvents 11262 # Number of times there has been no free registers
> system.cpu1.rename.RenamedOperands 571214843 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 926423560 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 707359605 # Number of integer rename lookups
> system.cpu1.rename.fp_rename_lookups 805393 # Number of floating rename lookups
> system.cpu1.rename.CommittedMaps 514629531 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 56585312 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 15957043 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 14048251 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 73992297 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 98060208 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 84478655 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 8950565 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 7675207 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 576680308 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 16104006 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 581772484 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 2680133 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 53366771 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 34273904 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 266458 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 704645391 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 0.825624 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 1.067009 # Number of insts issued each cycle
2012,2017c2001,2006
< system.cpu1.iq.issued_per_cycle::0 364178661 54.50% 54.50% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 127786531 19.12% 73.63% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 107346035 16.07% 89.69% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 61539810 9.21% 98.90% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 7340180 1.10% 100.00% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 3893 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 385934490 54.77% 54.77% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 135280434 19.20% 73.97% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 111501247 15.82% 89.79% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 64231431 9.12% 98.91% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 7693682 1.09% 100.00% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 4107 0.00% 100.00% # Number of insts issued each cycle
2024c2013
< system.cpu1.iq.issued_per_cycle::total 668195110 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 704645391 # Number of insts issued each cycle
2026,2056c2015,2045
< system.cpu1.iq.fu_full::IntAlu 55774345 44.07% 44.07% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 53478 0.04% 44.12% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 18362 0.01% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 15 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.13% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 33579431 26.53% 70.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 37124892 29.34% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 58591735 44.23% 44.23% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 49305 0.04% 44.27% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 21310 0.02% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 60 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.29% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 35005485 26.43% 70.71% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 38791699 29.29% 100.00% # attempts to use FU when none available
2059,2090c2048,2079
< system.cpu1.iq.FU_type_0::No_OpClass 35 0.00% 0.00% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntAlu 378772554 68.07% 68.07% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 1203453 0.22% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 69506 0.01% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.29% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMisc 82169 0.01% 68.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.31% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemRead 96967073 17.43% 85.73% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 79383378 14.27% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::No_OpClass 36 0.00% 0.00% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntAlu 397008075 68.24% 68.24% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 1247296 0.21% 68.46% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 70487 0.01% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.47% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMisc 78078 0.01% 68.48% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.48% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.48% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.48% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemRead 100884939 17.34% 85.82% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 82483526 14.18% 100.00% # Type of FU issued
2093,2105c2082,2094
< system.cpu1.iq.FU_type_0::total 556478216 # Type of FU issued
< system.cpu1.iq.rate 0.810227 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 126550523 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.227413 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 1908944024 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 619142753 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 540109020 # Number of integer instruction queue wakeup accesses
< system.cpu1.iq.fp_inst_queue_reads 1336236 # Number of floating instruction queue reads
< system.cpu1.iq.fp_inst_queue_writes 533681 # Number of floating instruction queue writes
< system.cpu1.iq.fp_inst_queue_wakeup_accesses 496559 # Number of floating instruction queue wakeup accesses
< system.cpu1.iq.int_alu_accesses 682200972 # Number of integer alu accesses
< system.cpu1.iq.fp_alu_accesses 827732 # Number of floating point alu accesses
< system.cpu1.iew.lsq.thread0.forwLoads 2535076 # Number of loads that had data forwarded from stores
---
> system.cpu1.iq.FU_type_0::total 581772484 # Type of FU issued
> system.cpu1.iq.rate 0.801139 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 132459594 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.227683 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 2001993843 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 645760406 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 564750025 # Number of integer instruction queue wakeup accesses
> system.cpu1.iq.fp_inst_queue_reads 1336243 # Number of floating instruction queue reads
> system.cpu1.iq.fp_inst_queue_writes 531893 # Number of floating instruction queue writes
> system.cpu1.iq.fp_inst_queue_wakeup_accesses 495883 # Number of floating instruction queue wakeup accesses
> system.cpu1.iq.int_alu_accesses 713403384 # Number of integer alu accesses
> system.cpu1.iq.fp_alu_accesses 828658 # Number of floating point alu accesses
> system.cpu1.iew.lsq.thread0.forwLoads 2572358 # Number of loads that had data forwarded from stores
2107,2110c2096,2099
< system.cpu1.iew.lsq.thread0.squashedLoads 12050927 # Number of loads squashed
< system.cpu1.iew.lsq.thread0.ignoredResponses 15964 # Number of memory responses ignored because the instruction is squashed
< system.cpu1.iew.lsq.thread0.memOrderViolation 139670 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 5367770 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 12226985 # Number of loads squashed
> system.cpu1.iew.lsq.thread0.ignoredResponses 16460 # Number of memory responses ignored because the instruction is squashed
> system.cpu1.iew.lsq.thread0.memOrderViolation 142391 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 5497757 # Number of stores squashed
2113,2114c2102,2103
< system.cpu1.iew.lsq.thread0.rescheduledLoads 2479862 # Number of loads that were rescheduled
< system.cpu1.iew.lsq.thread0.cacheBlocked 3811174 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu1.iew.lsq.thread0.rescheduledLoads 2564544 # Number of loads that were rescheduled
> system.cpu1.iew.lsq.thread0.cacheBlocked 4190277 # Number of times an access to memory failed due to the cache being blocked
2116,2119c2105,2108
< system.cpu1.iew.iewSquashCycles 4993051 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 6066595 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 1484920 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 567600146 # Number of instructions dispatched to IQ
---
> system.cpu1.iew.iewSquashCycles 5109225 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 6111838 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 1648605 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 592918318 # Number of instructions dispatched to IQ
2121,2132c2110,2121
< system.cpu1.iew.iewDispLoadInsts 94552173 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 81340147 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 12593166 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 61012 # Number of times the IQ has become full, causing a stall
< system.cpu1.iew.iewLSQFullEvents 1366008 # Number of times the LSQ has become full, causing a stall
< system.cpu1.iew.memOrderViolationEvents 139670 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 1864288 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 2962654 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 4826942 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 548760252 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 93936954 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 7198002 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.iewDispLoadInsts 98060208 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 84478655 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 13792326 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 62841 # Number of times the IQ has become full, causing a stall
> system.cpu1.iew.iewLSQFullEvents 1527139 # Number of times the LSQ has become full, causing a stall
> system.cpu1.iew.memOrderViolationEvents 142391 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 1885740 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 3046567 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 4932307 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 573876367 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 97784309 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 7346483 # Number of squashed instructions skipped in execute
2134,2150c2123,2139
< system.cpu1.iew.exec_nop 128211 # number of nop insts executed
< system.cpu1.iew.exec_refs 172107181 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 103045741 # Number of branches executed
< system.cpu1.iew.exec_stores 78170227 # Number of stores executed
< system.cpu1.iew.exec_rate 0.798990 # Inst execution rate
< system.cpu1.iew.wb_sent 541337937 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 540605579 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 260784878 # num instructions producing a value
< system.cpu1.iew.wb_consumers 427489689 # num instructions consuming a value
< system.cpu1.iew.wb_rate 0.787117 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.610038 # average fanout of values written-back
< system.cpu1.commit.commitSquashedInsts 45375845 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 14559534 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 4495992 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 659550921 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 0.781450 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.574730 # Number of insts commited each cycle
---
> system.cpu1.iew.exec_nop 134004 # number of nop insts executed
> system.cpu1.iew.exec_refs 179029158 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 107707763 # Number of branches executed
> system.cpu1.iew.exec_stores 81244849 # Number of stores executed
> system.cpu1.iew.exec_rate 0.790266 # Inst execution rate
> system.cpu1.iew.wb_sent 565995055 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 565245908 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 273023556 # num instructions producing a value
> system.cpu1.iew.wb_consumers 448078183 # num instructions consuming a value
> system.cpu1.iew.wb_rate 0.778381 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.609321 # average fanout of values written-back
> system.cpu1.commit.commitSquashedInsts 46535716 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 15837548 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 4592045 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 695790390 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 0.775259 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 1.568649 # Number of insts commited each cycle
2152,2160c2141,2149
< system.cpu1.commit.committed_per_cycle::0 433210493 65.68% 65.68% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 117319741 17.79% 83.47% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 50366969 7.64% 91.11% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 16989740 2.58% 93.68% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 12025543 1.82% 95.51% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 8091474 1.23% 96.73% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 5593324 0.85% 97.58% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 3365512 0.51% 98.09% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 12588125 1.91% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 457970279 65.82% 65.82% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 124243355 17.86% 83.68% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 52434114 7.54% 91.21% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 17645088 2.54% 93.75% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 12549968 1.80% 95.55% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 8433891 1.21% 96.76% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 5802471 0.83% 97.60% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 3503250 0.50% 98.10% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 13207974 1.90% 100.00% # Number of insts commited each cycle
2164,2166c2153,2155
< system.cpu1.commit.committed_per_cycle::total 659550921 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 437257329 # Number of instructions committed
< system.cpu1.commit.committedOps 515405969 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 695790390 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 458018039 # Number of instructions committed
> system.cpu1.commit.committedOps 539417542 # Number of ops (including micro ops) committed
2168,2174c2157,2163
< system.cpu1.commit.refs 158473622 # Number of memory references committed
< system.cpu1.commit.loads 82501245 # Number of loads committed
< system.cpu1.commit.membars 3568741 # Number of memory barriers committed
< system.cpu1.commit.branches 97797753 # Number of branches committed
< system.cpu1.commit.fp_insts 487077 # Number of committed floating point instructions.
< system.cpu1.commit.int_insts 473223690 # Number of committed integer instructions.
< system.cpu1.commit.function_calls 12865392 # Number of function calls committed.
---
> system.cpu1.commit.refs 164814121 # Number of memory references committed
> system.cpu1.commit.loads 85833223 # Number of loads committed
> system.cpu1.commit.membars 3719425 # Number of memory barriers committed
> system.cpu1.commit.branches 102343051 # Number of branches committed
> system.cpu1.commit.fp_insts 486729 # Number of committed floating point instructions.
> system.cpu1.commit.int_insts 494686776 # Number of committed integer instructions.
> system.cpu1.commit.function_calls 13237013 # Number of function calls committed.
2176,2206c2165,2195
< system.cpu1.commit.op_class_0::IntAlu 355828768 69.04% 69.04% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntMult 973462 0.19% 69.23% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntDiv 55201 0.01% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.24% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMisc 74874 0.01% 69.25% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.25% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.25% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.25% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemRead 82501245 16.01% 85.26% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemWrite 75972377 14.74% 100.00% # Class of committed instruction
---
> system.cpu1.commit.op_class_0::IntAlu 373462182 69.23% 69.23% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntMult 1014464 0.19% 69.42% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntDiv 55738 0.01% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.43% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMisc 70995 0.01% 69.45% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.45% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.45% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.45% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemRead 85833223 15.91% 85.36% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemWrite 78980898 14.64% 100.00% # Class of committed instruction
2209,2337c2198,2326
< system.cpu1.commit.op_class_0::total 515405969 # Class of committed instruction
< system.cpu1.commit.bw_lim_events 12588125 # number cycles where commit BW limit reached
< system.cpu1.rob.rob_reads 1203797977 # The number of ROB reads
< system.cpu1.rob.rob_writes 1130170940 # The number of ROB writes
< system.cpu1.timesIdled 922689 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 18622462 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 94081017888 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 437257329 # Number of Instructions Simulated
< system.cpu1.committedOps 515405969 # Number of Ops (including micro ops) Simulated
< system.cpu1.cpi 1.570740 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 1.570740 # CPI: Total CPI of All Threads
< system.cpu1.ipc 0.636643 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 0.636643 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 647634757 # number of integer regfile reads
< system.cpu1.int_regfile_writes 384292228 # number of integer regfile writes
< system.cpu1.fp_regfile_reads 785728 # number of floating regfile reads
< system.cpu1.fp_regfile_writes 454696 # number of floating regfile writes
< system.cpu1.cc_regfile_reads 117471222 # number of cc regfile reads
< system.cpu1.cc_regfile_writes 118161265 # number of cc regfile writes
< system.cpu1.misc_regfile_reads 1199366647 # number of misc regfile reads
< system.cpu1.misc_regfile_writes 14671382 # number of misc regfile writes
< system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.cpu1.dcache.tags.replacements 5153619 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 456.044406 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 148207895 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 5154131 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 28.755166 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 8517415326000 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.044406 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890712 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.890712 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 328622817 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 328622817 # Number of data accesses
< system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.cpu1.dcache.ReadReq_hits::cpu1.data 76967758 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 76967758 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 66682281 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 66682281 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 189501 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 189501 # number of SoftPFReq hits
< system.cpu1.dcache.WriteLineReq_hits::cpu1.data 166829 # number of WriteLineReq hits
< system.cpu1.dcache.WriteLineReq_hits::total 166829 # number of WriteLineReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1726427 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 1726427 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1743769 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 1743769 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 143816868 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 143816868 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 144006369 # number of overall hits
< system.cpu1.dcache.overall_hits::total 144006369 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 5978399 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 5978399 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 6727643 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 6727643 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 625948 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 625948 # number of SoftPFReq misses
< system.cpu1.dcache.WriteLineReq_misses::cpu1.data 458256 # number of WriteLineReq misses
< system.cpu1.dcache.WriteLineReq_misses::total 458256 # number of WriteLineReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 242959 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 242959 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 183921 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 183921 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 13164298 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 13164298 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 13790246 # number of overall misses
< system.cpu1.dcache.overall_misses::total 13790246 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 87383841500 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 87383841500 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 119886339095 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 119886339095 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11324190656 # number of WriteLineReq miss cycles
< system.cpu1.dcache.WriteLineReq_miss_latency::total 11324190656 # number of WriteLineReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3328957500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 3328957500 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4379371000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 4379371000 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2907500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2907500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 218594371251 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 218594371251 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 218594371251 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 218594371251 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 82946157 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 82946157 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 73409924 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 73409924 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 815449 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 815449 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 625085 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::total 625085 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1969386 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 1969386 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1927690 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 1927690 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 156981166 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 156981166 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 157796615 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 157796615 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.072076 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.072076 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.091645 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.091645 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.767611 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.767611 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.733110 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::total 0.733110 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.123368 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.123368 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095410 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095410 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083859 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.083859 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087393 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.087393 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14616.595764 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 14616.595764 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17819.961478 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 17819.961478 # average WriteReq miss latency
< system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24711.494571 # average WriteLineReq miss latency
< system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24711.494571 # average WriteLineReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13701.725394 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13701.725394 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23811.152614 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23811.152614 # average StoreCondReq miss latency
---
> system.cpu1.commit.op_class_0::total 539417542 # Class of committed instruction
> system.cpu1.commit.bw_lim_events 13207974 # number cycles where commit BW limit reached
> system.cpu1.rob.rob_reads 1264391907 # The number of ROB reads
> system.cpu1.rob.rob_writes 1180722952 # The number of ROB writes
> system.cpu1.timesIdled 944459 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 21536071 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 94043695657 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 458018039 # Number of Instructions Simulated
> system.cpu1.committedOps 539417542 # Number of Ops (including micro ops) Simulated
> system.cpu1.cpi 1.585487 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 1.585487 # CPI: Total CPI of All Threads
> system.cpu1.ipc 0.630721 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 0.630721 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 677403787 # number of integer regfile reads
> system.cpu1.int_regfile_writes 401367044 # number of integer regfile writes
> system.cpu1.fp_regfile_reads 791707 # number of floating regfile reads
> system.cpu1.fp_regfile_writes 438600 # number of floating regfile writes
> system.cpu1.cc_regfile_reads 124889457 # number of cc regfile reads
> system.cpu1.cc_regfile_writes 125620500 # number of cc regfile writes
> system.cpu1.misc_regfile_reads 1260290191 # number of misc regfile reads
> system.cpu1.misc_regfile_writes 15974322 # number of misc regfile writes
> system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.cpu1.dcache.tags.replacements 5362331 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 456.510727 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 153804268 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 5362842 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 28.679620 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 8517840775000 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.510727 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.891623 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.891623 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::1 382 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 341608540 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 341608540 # Number of data accesses
> system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.cpu1.dcache.ReadReq_hits::cpu1.data 79940930 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 79940930 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 69078558 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 69078558 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 191831 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 191831 # number of SoftPFReq hits
> system.cpu1.dcache.WriteLineReq_hits::cpu1.data 170764 # number of WriteLineReq hits
> system.cpu1.dcache.WriteLineReq_hits::total 170764 # number of WriteLineReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1820637 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 1820637 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1828950 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 1828950 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 149190252 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 149190252 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 149382083 # number of overall hits
> system.cpu1.dcache.overall_hits::total 149382083 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 6220385 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 6220385 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 7237581 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 7237581 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 689658 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 689658 # number of SoftPFReq misses
> system.cpu1.dcache.WriteLineReq_misses::cpu1.data 463987 # number of WriteLineReq misses
> system.cpu1.dcache.WriteLineReq_misses::total 463987 # number of WriteLineReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 244543 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 244543 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 192296 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 192296 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 13921953 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 13921953 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 14611611 # number of overall misses
> system.cpu1.dcache.overall_misses::total 14611611 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96362388500 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 96362388500 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 134833660621 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 134833660621 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11613680644 # number of WriteLineReq miss cycles
> system.cpu1.dcache.WriteLineReq_miss_latency::total 11613680644 # number of WriteLineReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3499456000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 3499456000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4567503000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 4567503000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3019500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3019500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 242809729765 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 242809729765 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 242809729765 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 242809729765 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 86161315 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 86161315 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 76316139 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 76316139 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 881489 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 881489 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 634751 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::total 634751 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2065180 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 2065180 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2021246 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 2021246 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 163112205 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 163112205 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 163993694 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 163993694 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.072195 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.072195 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.094837 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.094837 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.782378 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.782378 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.730975 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::total 0.730975 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118412 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118412 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095137 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095137 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085352 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.085352 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089099 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.089099 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15491.386546 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15491.386546 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18629.658255 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 18629.658255 # average WriteReq miss latency
> system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 25030.185423 # average WriteLineReq miss latency
> system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 25030.185423 # average WriteLineReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14310.186757 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14310.186757 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23752.459750 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23752.459750 # average StoreCondReq miss latency
2340,2381c2329,2370
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16605.091381 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 16605.091381 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15851.375766 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 15851.375766 # average overall miss latency
< system.cpu1.dcache.blocked_cycles::no_mshrs 2917967 # number of cycles access was blocked
< system.cpu1.dcache.blocked_cycles::no_targets 18895353 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_mshrs 374678 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_targets 668758 # number of cycles access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.787933 # average number of cycles each access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_targets 28.254395 # average number of cycles each access was blocked
< system.cpu1.dcache.writebacks::writebacks 5153631 # number of writebacks
< system.cpu1.dcache.writebacks::total 5153631 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3023211 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 3023211 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5427179 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 5427179 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3743 # number of WriteLineReq MSHR hits
< system.cpu1.dcache.WriteLineReq_mshr_hits::total 3743 # number of WriteLineReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 127495 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 127495 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 8454133 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 8454133 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 8454133 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 8454133 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2955188 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 2955188 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1300464 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 1300464 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 625861 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 625861 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 454513 # number of WriteLineReq MSHR misses
< system.cpu1.dcache.WriteLineReq_mshr_misses::total 454513 # number of WriteLineReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 115464 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 115464 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 183920 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 183920 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 4710165 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 4710165 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 5336026 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 5336026 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 21232 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.ReadReq_mshr_uncacheable::total 21232 # number of ReadReq MSHR uncacheable
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17440.780741 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 17440.780741 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16617.587873 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 16617.587873 # average overall miss latency
> system.cpu1.dcache.blocked_cycles::no_mshrs 3018250 # number of cycles access was blocked
> system.cpu1.dcache.blocked_cycles::no_targets 21738633 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_mshrs 378529 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_targets 731712 # number of cycles access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.973629 # average number of cycles each access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_targets 29.709275 # average number of cycles each access was blocked
> system.cpu1.dcache.writebacks::writebacks 5362354 # number of writebacks
> system.cpu1.dcache.writebacks::total 5362354 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3187456 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 3187456 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5861363 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 5861363 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3594 # number of WriteLineReq MSHR hits
> system.cpu1.dcache.WriteLineReq_mshr_hits::total 3594 # number of WriteLineReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 128092 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 128092 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 9052413 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 9052413 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 9052413 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 9052413 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3032929 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 3032929 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1376218 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 1376218 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 689576 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 689576 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 460393 # number of WriteLineReq MSHR misses
> system.cpu1.dcache.WriteLineReq_mshr_misses::total 460393 # number of WriteLineReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116451 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116451 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 192288 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 192288 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 4869540 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 4869540 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 5559116 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 5559116 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 21291 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 21291 # number of ReadReq MSHR uncacheable
2384,2435c2373,2424
< system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 40642 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.overall_mshr_uncacheable_misses::total 40642 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40128990000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40128990000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24368462066 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24368462066 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13718666000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13718666000 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10741056156 # number of WriteLineReq MSHR miss cycles
< system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10741056156 # number of WriteLineReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1514532000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1514532000 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4195522000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4195522000 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2836500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2836500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 75238508222 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 75238508222 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 88957174222 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 88957174222 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3718611500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3718611500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3718611500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3718611500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035628 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035628 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017715 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017715 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.767505 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.767505 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.727122 # mshr miss rate for WriteLineReq accesses
< system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.727122 # mshr miss rate for WriteLineReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058629 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058629 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095410 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095410 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030005 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.030005 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033816 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.033816 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13579.166537 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13579.166537 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18738.282694 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18738.282694 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21919.669064 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21919.669064 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23632.010869 # average WriteLineReq mshr miss latency
< system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23632.010869 # average WriteLineReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13116.919559 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13116.919559 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22811.668117 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22811.668117 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 40701 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 40701 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42726170500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42726170500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26732145261 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26732145261 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16635879000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16635879000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 11021618644 # number of WriteLineReq MSHR miss cycles
> system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 11021618644 # number of WriteLineReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1587191500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1587191500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4375287000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4375287000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2947500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2947500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 80479934405 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 80479934405 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 97115813405 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 97115813405 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3797634000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3797634000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3797634000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3797634000 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035201 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035201 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018033 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018033 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.782285 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.782285 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.725313 # mshr miss rate for WriteLineReq accesses
> system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.725313 # mshr miss rate for WriteLineReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056388 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056388 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095133 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095133 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029854 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.029854 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033898 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.033898 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14087.428522 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14087.428522 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19424.353744 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19424.353744 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24124.794076 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24124.794076 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23939.587796 # average WriteLineReq mshr miss latency
> system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23939.587796 # average WriteLineReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13629.694034 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13629.694034 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22753.822391 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22753.822391 # average StoreCondReq mshr miss latency
2438,2455c2427,2444
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15973.645981 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15973.645981 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16671.053369 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16671.053369 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175141.837792 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 175141.837792 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91496.764431 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91496.764431 # average overall mshr uncacheable latency
< system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.cpu1.icache.tags.replacements 6014648 # number of replacements
< system.cpu1.icache.tags.tagsinuse 501.532915 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 195349774 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 6015160 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 32.476239 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 8517720712000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.532915 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979556 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.979556 # Average percentage of cache occupancy
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16527.214974 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16527.214974 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17469.650463 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17469.650463 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 178368.042835 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 178368.042835 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 93305.668165 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 93305.668165 # average overall mshr uncacheable latency
> system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.cpu1.icache.tags.replacements 5902862 # number of replacements
> system.cpu1.icache.tags.tagsinuse 501.529159 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 204324856 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 5903374 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 34.611538 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 8518180301500 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.529159 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979549 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.979549 # Average percentage of cache occupancy
2457,2459c2446,2448
< system.cpu1.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::1 341 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id
2461,2553c2450,2542
< system.cpu1.icache.tags.tag_accesses 409423979 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 409423979 # Number of data accesses
< system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.cpu1.icache.ReadReq_hits::cpu1.inst 195349774 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 195349774 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 195349774 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 195349774 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 195349774 # number of overall hits
< system.cpu1.icache.overall_hits::total 195349774 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 6354622 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 6354622 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 6354622 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 6354622 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 6354622 # number of overall misses
< system.cpu1.icache.overall_misses::total 6354622 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 66668444908 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 66668444908 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 66668444908 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 66668444908 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 66668444908 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 66668444908 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 201704396 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 201704396 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 201704396 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 201704396 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 201704396 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 201704396 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.031505 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.031505 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.031505 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.031505 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.031505 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.031505 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10491.331335 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 10491.331335 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10491.331335 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 10491.331335 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10491.331335 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 10491.331335 # average overall miss latency
< system.cpu1.icache.blocked_cycles::no_mshrs 9555681 # number of cycles access was blocked
< system.cpu1.icache.blocked_cycles::no_targets 472 # number of cycles access was blocked
< system.cpu1.icache.blocked::no_mshrs 727552 # number of cycles access was blocked
< system.cpu1.icache.blocked::no_targets 4 # number of cycles access was blocked
< system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.134018 # average number of cycles each access was blocked
< system.cpu1.icache.avg_blocked_cycles::no_targets 118 # average number of cycles each access was blocked
< system.cpu1.icache.writebacks::writebacks 6014648 # number of writebacks
< system.cpu1.icache.writebacks::total 6014648 # number of writebacks
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 339435 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 339435 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 339435 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 339435 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 339435 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 339435 # number of overall MSHR hits
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 6015187 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 6015187 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 6015187 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 6015187 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 6015187 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 6015187 # number of overall MSHR misses
< system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 68 # number of ReadReq MSHR uncacheable
< system.cpu1.icache.ReadReq_mshr_uncacheable::total 68 # number of ReadReq MSHR uncacheable
< system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 68 # number of overall MSHR uncacheable misses
< system.cpu1.icache.overall_mshr_uncacheable_misses::total 68 # number of overall MSHR uncacheable misses
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 60428904539 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 60428904539 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 60428904539 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 60428904539 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 60428904539 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 60428904539 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6183499 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6183499 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6183499 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 6183499 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.029822 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.029822 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.029822 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.029822 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.029822 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.029822 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10046.055848 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10046.055848 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10046.055848 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 10046.055848 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10046.055848 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 10046.055848 # average overall mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90933.808824 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90933.808824 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90933.808824 # average overall mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90933.808824 # average overall mshr uncacheable latency
< system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.cpu1.l2cache.prefetcher.num_hwpf_issued 6826847 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.pfIdentified 6833838 # number of prefetch candidates identified
< system.cpu1.l2cache.prefetcher.pfBufferHit 6347 # number of redundant prefetches already in prefetch queue
---
> system.cpu1.icache.tags.tag_accesses 427035149 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 427035149 # Number of data accesses
> system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.cpu1.icache.ReadReq_hits::cpu1.inst 204324856 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 204324856 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 204324856 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 204324856 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 204324856 # number of overall hits
> system.cpu1.icache.overall_hits::total 204324856 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 6241016 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 6241016 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 6241016 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 6241016 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 6241016 # number of overall misses
> system.cpu1.icache.overall_misses::total 6241016 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 68483006769 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 68483006769 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 68483006769 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 68483006769 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 68483006769 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 68483006769 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 210565872 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 210565872 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 210565872 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 210565872 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 210565872 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 210565872 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029639 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.029639 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029639 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.029639 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029639 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.029639 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10973.054190 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 10973.054190 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10973.054190 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 10973.054190 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10973.054190 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 10973.054190 # average overall miss latency
> system.cpu1.icache.blocked_cycles::no_mshrs 10089385 # number of cycles access was blocked
> system.cpu1.icache.blocked_cycles::no_targets 780 # number of cycles access was blocked
> system.cpu1.icache.blocked::no_mshrs 729550 # number of cycles access was blocked
> system.cpu1.icache.blocked::no_targets 2 # number of cycles access was blocked
> system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.829600 # average number of cycles each access was blocked
> system.cpu1.icache.avg_blocked_cycles::no_targets 390 # average number of cycles each access was blocked
> system.cpu1.icache.writebacks::writebacks 5902862 # number of writebacks
> system.cpu1.icache.writebacks::total 5902862 # number of writebacks
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 337611 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 337611 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 337611 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 337611 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 337611 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 337611 # number of overall MSHR hits
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5903405 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 5903405 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 5903405 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 5903405 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 5903405 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 5903405 # number of overall MSHR misses
> system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
> system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable
> system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
> system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 61792345334 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 61792345334 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 61792345334 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 61792345334 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 61792345334 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 61792345334 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7079498 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7079498 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7079498 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 7079498 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028036 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028036 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028036 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.028036 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028036 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.028036 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10467.238032 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10467.238032 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10467.238032 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 10467.238032 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10467.238032 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 10467.238032 # average overall mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 105664.149254 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 105664.149254 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 105664.149254 # average overall mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 105664.149254 # average overall mshr uncacheable latency
> system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.cpu1.l2cache.prefetcher.num_hwpf_issued 7372835 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.pfIdentified 7380898 # number of prefetch candidates identified
> system.cpu1.l2cache.prefetcher.pfBufferHit 7290 # number of redundant prefetches already in prefetch queue
2556,2562c2545,2551
< system.cpu1.l2cache.prefetcher.pfSpanPage 835722 # number of prefetches not generated due to page crossing
< system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.cpu1.l2cache.tags.replacements 1955228 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 12896.405710 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 10261646 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 1970971 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 5.206391 # Average number of references to valid blocks.
---
> system.cpu1.l2cache.prefetcher.pfSpanPage 895622 # number of prefetches not generated due to page crossing
> system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.cpu1.l2cache.tags.replacements 2111480 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 12950.875249 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 10279593 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 2126904 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 4.833125 # Average number of references to valid blocks.
2564,2631c2553,2619
< system.cpu1.l2cache.tags.occ_blocks::writebacks 12598.365224 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 35.187602 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 26.957161 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 235.895723 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.768943 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002148 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001645 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014398 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.787134 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 398 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 66 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15279 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 9 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 186 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 92 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 100 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 49 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2171 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6847 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4119 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1911 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.024292 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004028 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.932556 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 388828691 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 388828691 # Number of data accesses
< system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 536780 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 184573 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 721353 # number of ReadReq hits
< system.cpu1.l2cache.WritebackDirty_hits::writebacks 3280399 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackDirty_hits::total 3280399 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackClean_hits::writebacks 7886275 # number of WritebackClean hits
< system.cpu1.l2cache.WritebackClean_hits::total 7886275 # number of WritebackClean hits
< system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 44 # number of UpgradeReq hits
< system.cpu1.l2cache.UpgradeReq_hits::total 44 # number of UpgradeReq hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 841994 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 841994 # number of ReadExReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5485264 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::total 5485264 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2792582 # number of ReadSharedReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::total 2792582 # number of ReadSharedReq hits
< system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 201829 # number of InvalidateReq hits
< system.cpu1.l2cache.InvalidateReq_hits::total 201829 # number of InvalidateReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 536780 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 184573 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 5485264 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 3634576 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 9841193 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 536780 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 184573 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 5485264 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 3634576 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 9841193 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 18586 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8726 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 27312 # number of ReadReq misses
< system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses
< system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 218938 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 218938 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 183916 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 183916 # number of SCUpgradeReq misses
---
> system.cpu1.l2cache.tags.occ_blocks::writebacks 12615.195694 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 33.253837 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 24.384299 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 278.041418 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.769970 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002030 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001488 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.016970 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.790459 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 414 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 111 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14899 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 65 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 128 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 114 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 107 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 7 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 89 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 279 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1377 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5586 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5487 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2170 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.025269 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006775 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.909363 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 393006433 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 393006433 # Number of data accesses
> system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 563217 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 188120 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 751337 # number of ReadReq hits
> system.cpu1.l2cache.WritebackDirty_hits::writebacks 3404083 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackDirty_hits::total 3404083 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackClean_hits::writebacks 7859423 # number of WritebackClean hits
> system.cpu1.l2cache.WritebackClean_hits::total 7859423 # number of WritebackClean hits
> system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits
> system.cpu1.l2cache.UpgradeReq_hits::total 37 # number of UpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 897837 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 897837 # number of ReadExReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5343474 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::total 5343474 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2865962 # number of ReadSharedReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::total 2865962 # number of ReadSharedReq hits
> system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 200218 # number of InvalidateReq hits
> system.cpu1.l2cache.InvalidateReq_hits::total 200218 # number of InvalidateReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 563217 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 188120 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 5343474 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 3763799 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 9858610 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 563217 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 188120 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 5343474 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 3763799 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 9858610 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 20588 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9811 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 30399 # number of ReadReq misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 230170 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 230170 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 192283 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 192283 # number of SCUpgradeReq misses
2634,2689c2622,2677
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 248462 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 248462 # number of ReadExReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 529890 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::total 529890 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 900142 # number of ReadSharedReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::total 900142 # number of ReadSharedReq misses
< system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 250350 # number of InvalidateReq misses
< system.cpu1.l2cache.InvalidateReq_misses::total 250350 # number of InvalidateReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 18586 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8726 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 529890 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 1148604 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 1705806 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 18586 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8726 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 529890 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 1148604 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 1705806 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 561198500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 279280000 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 840478500 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 939555000 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 939555000 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 281624500 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 281624500 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2725499 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2725499 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10972899994 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 10972899994 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 18159407000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::total 18159407000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31177890486 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::total 31177890486 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 362314500 # number of InvalidateReq miss cycles
< system.cpu1.l2cache.InvalidateReq_miss_latency::total 362314500 # number of InvalidateReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 561198500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 279280000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 18159407000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 42150790480 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 61150675980 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 561198500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 279280000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 18159407000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 42150790480 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 61150675980 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 555366 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 193299 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 748665 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3280399 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::total 3280399 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::writebacks 7886276 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::total 7886276 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 218982 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 218982 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 183916 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 183916 # number of SCUpgradeReq accesses(hits+misses)
---
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 257129 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 257129 # number of ReadExReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 559914 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::total 559914 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 968987 # number of ReadSharedReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::total 968987 # number of ReadSharedReq misses
> system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 258105 # number of InvalidateReq misses
> system.cpu1.l2cache.InvalidateReq_misses::total 258105 # number of InvalidateReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 20588 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9811 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 559914 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 1226116 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 1816429 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 20588 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9811 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 559914 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 1226116 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 1816429 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 677842000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 364880500 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 1042722500 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 983294000 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 983294000 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 271676000 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 271676000 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2839500 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2839500 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12532259990 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 12532259990 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 20571950500 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::total 20571950500 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 36061918479 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::total 36061918479 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 340389000 # number of InvalidateReq miss cycles
> system.cpu1.l2cache.InvalidateReq_miss_latency::total 340389000 # number of InvalidateReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 677842000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 364880500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 20571950500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 48594178469 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 70208851469 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 677842000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 364880500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 20571950500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 48594178469 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 70208851469 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 583805 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 197931 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 781736 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3404083 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::total 3404083 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::writebacks 7859423 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::total 7859423 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 230207 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 230207 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 192284 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 192284 # number of SCUpgradeReq accesses(hits+misses)
2692,2718c2680,2704
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1090456 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 1090456 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 6015154 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::total 6015154 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3692724 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::total 3692724 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 452179 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::total 452179 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 555366 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 193299 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 6015154 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 4783180 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 11546999 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 555366 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 193299 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 6015154 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 4783180 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 11546999 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.033466 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.045142 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.036481 # miss rate for ReadReq accesses
< system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses
< system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999799 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999799 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
---
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1154966 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 1154966 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5903388 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::total 5903388 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3834949 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::total 3834949 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 458323 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::total 458323 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 583805 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 197931 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 5903388 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 4989915 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 11675039 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 583805 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 197931 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 5903388 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 4989915 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 11675039 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.035265 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.049568 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.038887 # miss rate for ReadReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999839 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999839 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999995 # miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999995 # miss rate for SCUpgradeReq accesses
2721,2766c2707,2752
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.227851 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.227851 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.088093 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.088093 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.243761 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.243761 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.553652 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.553652 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.033466 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.045142 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.088093 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.240134 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.147727 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.033466 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.045142 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.088093 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.240134 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.147727 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 30194.689551 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 32005.500802 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 30773.231547 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4291.420402 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4291.420402 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1531.266991 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1531.266991 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 681374.750000 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 681374.750000 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44163.292552 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44163.292552 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 34270.144747 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 34270.144747 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 34636.635649 # average ReadSharedReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 34636.635649 # average ReadSharedReq miss latency
< system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1447.231875 # average InvalidateReq miss latency
< system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1447.231875 # average InvalidateReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 30194.689551 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 32005.500802 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34270.144747 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36697.408750 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 35848.552520 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 30194.689551 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 32005.500802 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34270.144747 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36697.408750 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 35848.552520 # average overall miss latency
< system.cpu1.l2cache.blocked_cycles::no_mshrs 288 # number of cycles access was blocked
---
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.222629 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.222629 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.094846 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.094846 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.252673 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.252673 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.563151 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.563151 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.035265 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.049568 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.094846 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.245719 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.155582 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.035265 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.049568 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.094846 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.245719 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.155582 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 32924.130561 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 37190.959128 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 34301.210566 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4272.033714 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4272.033714 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1412.896616 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1412.896616 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 709875 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 709875 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 48739.193129 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 48739.193129 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36741.268302 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36741.268302 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 37216.101433 # average ReadSharedReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 37216.101433 # average ReadSharedReq miss latency
> system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1318.800488 # average InvalidateReq miss latency
> system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1318.800488 # average InvalidateReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 32924.130561 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 37190.959128 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36741.268302 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 39632.611000 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 38652.130895 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 32924.130561 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 37190.959128 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36741.268302 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 39632.611000 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 38652.130895 # average overall miss latency
> system.cpu1.l2cache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
2768c2754
< system.cpu1.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked
---
> system.cpu1.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked
2770c2756
< system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 57.600000 # average number of cycles each access was blocked
---
> system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 28 # average number of cycles each access was blocked
2772,2806c2758,2790
< system.cpu1.l2cache.unused_prefetches 40502 # number of HardPF blocks evicted w/o reference
< system.cpu1.l2cache.writebacks::writebacks 1084478 # number of writebacks
< system.cpu1.l2cache.writebacks::total 1084478 # number of writebacks
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 75 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 191 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::total 266 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 10775 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 10775 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 2 # number of ReadCleanReq MSHR hits
< system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4833 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4833 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 2 # number of InvalidateReq MSHR hits
< system.cpu1.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 75 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 191 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 15608 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 15876 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 75 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 191 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 15608 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 15876 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 18511 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8535 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 27046 # number of ReadReq MSHR misses
< system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses
< system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 693628 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 693628 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 218938 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 218938 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 183916 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 183916 # number of SCUpgradeReq MSHR misses
---
> system.cpu1.l2cache.unused_prefetches 42085 # number of HardPF blocks evicted w/o reference
> system.cpu1.l2cache.writebacks::writebacks 1170856 # number of writebacks
> system.cpu1.l2cache.writebacks::total 1170856 # number of writebacks
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 68 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 195 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::total 263 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 13529 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 13529 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 3 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4671 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4671 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 5 # number of InvalidateReq MSHR hits
> system.cpu1.l2cache.InvalidateReq_mshr_hits::total 5 # number of InvalidateReq MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 68 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 195 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 18200 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 18466 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 68 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 195 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 18200 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 18466 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 20520 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9616 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 30136 # number of ReadReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 763352 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 763352 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 230170 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 230170 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 192283 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 192283 # number of SCUpgradeReq MSHR misses
2809,2830c2793,2814
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 237687 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 237687 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 529888 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 529888 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 895309 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 895309 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 250348 # number of InvalidateReq MSHR misses
< system.cpu1.l2cache.InvalidateReq_mshr_misses::total 250348 # number of InvalidateReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 18511 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8535 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 529888 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1132996 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 1689930 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 18511 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8535 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 529888 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1132996 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 693628 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 2383558 # number of overall MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 68 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 21232 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 21300 # number of ReadReq MSHR uncacheable
---
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 243600 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 243600 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 559911 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 559911 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 964316 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 964316 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 258100 # number of InvalidateReq MSHR misses
> system.cpu1.l2cache.InvalidateReq_mshr_misses::total 258100 # number of InvalidateReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 20520 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9616 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 559911 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1207916 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 1797963 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 20520 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9616 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 559911 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1207916 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 763352 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 2561315 # number of overall MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 21291 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 21358 # number of ReadReq MSHR uncacheable
2833,2876c2817,2858
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 68 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 40642 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 40710 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 448702000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 224952500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 673654500 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 32672970024 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 32672970024 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4113980492 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4113980492 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2813333996 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2813333996 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2299499 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2299499 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7950875496 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7950875496 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14980050000 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14980050000 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 25503490486 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 25503490486 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6724179499 # number of InvalidateReq MSHR miss cycles
< system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6724179499 # number of InvalidateReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 448702000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 224952500 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14980050000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 33454365982 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 49108070482 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 448702000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 224952500 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14980050000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 33454365982 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 32672970024 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 81781040506 # number of overall MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5673000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3548566000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3554239000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 5673000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3548566000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3554239000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.033331 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.044154 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.036126 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
< system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
---
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 40701 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 40768 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 553404000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 304119000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 857523000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 42319154022 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 42319154022 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4307815491 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4307815491 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2930523994 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2930523994 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2407500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2407500 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8988147495 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8988147495 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 17212365000 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 17212365000 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 29935787486 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 29935787486 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6963364497 # number of InvalidateReq MSHR miss cycles
> system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6963364497 # number of InvalidateReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 553404000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 304119000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 17212365000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 38923934981 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 56993822981 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 553404000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 304119000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 17212365000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 38923934981 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 42319154022 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 99312977003 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6576000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3627092000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3633668000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6576000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3627092000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3633668000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.035149 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048583 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.038550 # mshr miss rate for ReadReq accesses
2879,2882c2861,2864
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999799 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999799 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
---
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999839 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999839 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999995 # mshr miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses
2885,2901c2867,2883
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.217970 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.217970 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.088092 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.088092 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.242452 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242452 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.553648 # mshr miss rate for InvalidateReq accesses
< system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.553648 # mshr miss rate for InvalidateReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.033331 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.044154 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.088092 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.236871 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.146352 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.033331 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.044154 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.088092 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.236871 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.210915 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.210915 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.094846 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.094846 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.251455 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.251455 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.563140 # mshr miss rate for InvalidateReq accesses
> system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.563140 # mshr miss rate for InvalidateReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.035149 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048583 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.094846 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.242071 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.154001 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.035149 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048583 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.094846 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.242071 # mshr miss rate for overall accesses
2903,2944c2885,2926
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.206422 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24239.749338 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 26356.473345 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24907.731273 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47104.456602 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 47104.456602 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18790.618769 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18790.618769 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15296.842015 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15296.842015 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 574874.750000 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 574874.750000 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33451.032223 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33451.032223 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28270.219367 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28270.219367 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28485.685373 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28485.685373 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26859.329809 # average InvalidateReq mshr miss latency
< system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26859.329809 # average InvalidateReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24239.749338 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26356.473345 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28270.219367 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29527.346947 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29059.233508 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24239.749338 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26356.473345 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28270.219367 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29527.346947 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47104.456602 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34310.488986 # average overall mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83426.470588 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 167132.912585 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166865.680751 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83426.470588 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87312.779883 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87306.288381 # average overall mshr uncacheable latency
< system.cpu1.toL2Bus.snoop_filter.tot_requests 23161545 # Total number of requests made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11911126 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1586 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.snoop_filter.tot_snoops 559932 # Total number of snoops made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 559928 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.219384 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26969.005848 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31626.351913 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28455.103531 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55438.584063 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55438.584063 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18715.799153 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18715.799153 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15240.681672 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15240.681672 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 601875 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 601875 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36897.157204 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36897.157204 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30741.251735 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30741.251735 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31043.545359 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31043.545359 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26979.327768 # average InvalidateReq mshr miss latency
> system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26979.327768 # average InvalidateReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26969.005848 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31626.351913 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30741.251735 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32224.041226 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31699.107813 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26969.005848 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31626.351913 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30741.251735 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32224.041226 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55438.584063 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 38774.214418 # average overall mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98149.253731 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170357.991640 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 170131.472984 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98149.253731 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 89115.549986 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 89130.396389 # average overall mshr uncacheable latency
> system.cpu1.toL2Bus.snoop_filter.tot_requests 23401917 # Total number of requests made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_requests 12050394 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1685 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.snoop_filter.tot_snoops 583324 # Total number of snoops made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 583320 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2946,2948c2928,2931
< system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.cpu1.toL2Bus.trans_dist::ReadReq 858463 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 10650090 # Transaction distribution
---
> system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.cpu1.toL2Bus.trans_dist::ReadReq 895492 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 10720388 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution
2951,2981c2934,2964
< system.cpu1.toL2Bus.trans_dist::WritebackDirty 4372034 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackClean 7887876 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::CleanEvict 1202832 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 877539 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFResp 29 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 412195 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 333118 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 458356 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 1116808 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 1095312 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadCleanReq 6015187 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4685876 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateReq 509592 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateResp 452179 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18045125 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16655613 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 406321 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1179507 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 36286566 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 769908416 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 641765745 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1546392 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4442928 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 1417663481 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 4824103 # Total snoops (count)
< system.cpu1.toL2Bus.snoopTraffic 76247568 # Total snoop traffic (bytes)
< system.cpu1.toL2Bus.snoop_fanout::samples 17122714 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 0.052642 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.223318 # Request fanout histogram
---
> system.cpu1.toL2Bus.trans_dist::WritebackDirty 4582624 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackClean 7861129 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::CleanEvict 1298468 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 967756 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFResp 11 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 436519 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 348532 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 480708 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 65 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 1183332 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 1160512 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5903405 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4845353 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateReq 522418 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateResp 458323 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17709789 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17335665 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 416038 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1239832 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 36701324 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 755601072 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 668583302 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1583448 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4670440 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 1430438262 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 5153113 # Total snoops (count)
> system.cpu1.toL2Bus.snoopTraffic 82064432 # Total snoop traffic (bytes)
> system.cpu1.toL2Bus.snoop_fanout::samples 17599300 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 0.053842 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.225707 # Request fanout histogram
2983,2984c2966,2967
< system.cpu1.toL2Bus.snoop_fanout::0 16221347 94.74% 94.74% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::1 901363 5.26% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::0 16651717 94.62% 94.62% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::1 947579 5.38% 100.00% # Request fanout histogram
2989,2990c2972,2973
< system.cpu1.toL2Bus.snoop_fanout::total 17122714 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 23027796506 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 17599300 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 23252082447 # Layer occupancy (ticks)
2992c2975
< system.cpu1.toL2Bus.snoopLayer0.occupancy 160947650 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 167523282 # Layer occupancy (ticks)
2994c2977
< system.cpu1.toL2Bus.respLayer0.occupancy 9028759604 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 8861086123 # Layer occupancy (ticks)
2996c2979
< system.cpu1.toL2Bus.respLayer1.occupancy 7641863842 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 7965231666 # Layer occupancy (ticks)
2998c2981
< system.cpu1.toL2Bus.respLayer2.occupancy 213393747 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer2.occupancy 218506693 # Layer occupancy (ticks)
3000c2983
< system.cpu1.toL2Bus.respLayer3.occupancy 624968323 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 656902733 # Layer occupancy (ticks)
3002,3007c2985,2990
< system.iobus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.iobus.trans_dist::ReadReq 40315 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40315 # Transaction distribution
< system.iobus.trans_dist::WriteReq 136630 # Transaction distribution
< system.iobus.trans_dist::WriteResp 136630 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47698 # Packet count per connected master and slave (bytes)
---
> system.iobus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.iobus.trans_dist::ReadReq 40332 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40332 # Transaction distribution
> system.iobus.trans_dist::WriteReq 136631 # Transaction distribution
> system.iobus.trans_dist::WriteResp 136631 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47650 # Packet count per connected master and slave (bytes)
3018c3001
< system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
3020,3022c3003,3005
< system.iobus.pkt_count_system.bridge.master::total 122580 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231230 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 231230 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 122584 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231262 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 231262 # Packet count per connected master and slave (bytes)
3025,3026c3008,3009
< system.iobus.pkt_count::total 353890 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47718 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 353926 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47670 # Cumulative packet size per connected master and slave (bytes)
3037c3020
< system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
3039,3041c3022,3024
< system.iobus.pkt_size_system.bridge.master::total 155710 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338936 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7338936 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 155691 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339064 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7339064 # Cumulative packet size per connected master and slave (bytes)
3044,3045c3027,3028
< system.iobus.pkt_size::total 7496732 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 36996503 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 7496841 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 36933004 # Layer occupancy (ticks)
3047c3030
< system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer1.occupancy 9500 # Layer occupancy (ticks)
3049c3032
< system.iobus.reqLayer2.occupancy 325000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks)
3051c3034
< system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks)
3057c3040
< system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks)
3065c3048
< system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks)
3067c3050
< system.iobus.reqLayer23.occupancy 24232502 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 24511500 # Layer occupancy (ticks)
3069c3052
< system.iobus.reqLayer24.occupancy 36410001 # Layer occupancy (ticks)
---
> system.iobus.reqLayer24.occupancy 36406001 # Layer occupancy (ticks)
3071c3054
< system.iobus.reqLayer25.occupancy 568919799 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 569333352 # Layer occupancy (ticks)
3073c3056
< system.iobus.respLayer0.occupancy 92681000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 92684000 # Layer occupancy (ticks)
3075c3058
< system.iobus.respLayer3.occupancy 147926000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 147958000 # Layer occupancy (ticks)
3079,3081c3062,3064
< system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.iocache.tags.replacements 115610 # number of replacements
< system.iocache.tags.tagsinuse 11.211324 # Cycle average of tags in use
---
> system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.iocache.tags.replacements 115627 # number of replacements
> system.iocache.tags.tagsinuse 11.209625 # Cycle average of tags in use
3083c3066
< system.iocache.tags.sampled_refs 115626 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 115643 # Sample count of references to valid blocks.
3085,3090c3068,3073
< system.iocache.tags.warmup_cycle 9155814843000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ethernet 7.413268 # Average occupied blocks per requestor
< system.iocache.tags.occ_blocks::realview.ide 3.798056 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ethernet 0.463329 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::realview.ide 0.237379 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.700708 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 9156281985000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ethernet 7.417323 # Average occupied blocks per requestor
> system.iocache.tags.occ_blocks::realview.ide 3.792302 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ethernet 0.463583 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::realview.ide 0.237019 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.700602 # Average percentage of cache occupancy
3094,3096c3077,3079
< system.iocache.tags.tag_accesses 1040892 # Number of tag accesses
< system.iocache.tags.data_accesses 1040892 # Number of data accesses
< system.iocache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
---
> system.iocache.tags.tag_accesses 1041036 # Number of tag accesses
> system.iocache.tags.data_accesses 1041036 # Number of data accesses
> system.iocache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
3098,3099c3081,3082
< system.iocache.ReadReq_misses::realview.ide 8887 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8924 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8903 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8940 # number of ReadReq misses
3105,3106c3088,3089
< system.iocache.demand_misses::realview.ide 115615 # number of demand (read+write) misses
< system.iocache.demand_misses::total 115655 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 115631 # number of demand (read+write) misses
> system.iocache.demand_misses::total 115671 # number of demand (read+write) misses
3108,3109c3091,3092
< system.iocache.overall_misses::realview.ide 115615 # number of overall misses
< system.iocache.overall_misses::total 115655 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 115631 # number of overall misses
> system.iocache.overall_misses::total 115671 # number of overall misses
3111,3112c3094,3095
< system.iocache.ReadReq_miss_latency::realview.ide 1677259553 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 1682459553 # number of ReadReq miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 1786499757 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 1791699757 # number of ReadReq miss cycles
3115,3116c3098,3099
< system.iocache.WriteLineReq_miss_latency::realview.ide 12947566246 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 12947566246 # number of WriteLineReq miss cycles
---
> system.iocache.WriteLineReq_miss_latency::realview.ide 13185420595 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 13185420595 # number of WriteLineReq miss cycles
3118,3119c3101,3102
< system.iocache.demand_miss_latency::realview.ide 14624825799 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 14630394799 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 14971920352 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 14977489352 # number of demand (read+write) miss cycles
3121,3122c3104,3105
< system.iocache.overall_miss_latency::realview.ide 14624825799 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 14630394799 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 14971920352 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 14977489352 # number of overall miss cycles
3124,3125c3107,3108
< system.iocache.ReadReq_accesses::realview.ide 8887 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8924 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8903 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8940 # number of ReadReq accesses(hits+misses)
3131,3132c3114,3115
< system.iocache.demand_accesses::realview.ide 115615 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 115655 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 115631 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 115671 # number of demand (read+write) accesses
3134,3135c3117,3118
< system.iocache.overall_accesses::realview.ide 115615 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 115655 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 115631 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 115671 # number of overall (read+write) accesses
3150,3151c3133,3134
< system.iocache.ReadReq_avg_miss_latency::realview.ide 188731.805221 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 188531.998319 # average ReadReq miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 200662.670673 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 200413.843065 # average ReadReq miss latency
3154,3155c3137,3138
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121313.678191 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 121313.678191 # average WriteLineReq miss latency
---
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123542.281266 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 123542.281266 # average WriteLineReq miss latency
3157,3158c3140,3141
< system.iocache.demand_avg_miss_latency::realview.ide 126495.920071 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 126500.322502 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 129480.159750 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 129483.529597 # average overall miss latency
3160,3162c3143,3145
< system.iocache.overall_avg_miss_latency::realview.ide 126495.920071 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 126500.322502 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 33395 # number of cycles access was blocked
---
> system.iocache.overall_avg_miss_latency::realview.ide 129480.159750 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 129483.529597 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 39692 # number of cycles access was blocked
3164c3147
< system.iocache.blocked::no_mshrs 3494 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3537 # number of cycles access was blocked
3166c3149
< system.iocache.avg_blocked_cycles::no_mshrs 9.557813 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 11.221939 # average number of cycles each access was blocked
3168,3169c3151,3152
< system.iocache.writebacks::writebacks 106693 # number of writebacks
< system.iocache.writebacks::total 106693 # number of writebacks
---
> system.iocache.writebacks::writebacks 106694 # number of writebacks
> system.iocache.writebacks::total 106694 # number of writebacks
3171,3172c3154,3155
< system.iocache.ReadReq_mshr_misses::realview.ide 8887 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 8924 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 8903 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 8940 # number of ReadReq MSHR misses
3178,3179c3161,3162
< system.iocache.demand_mshr_misses::realview.ide 115615 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 115655 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 115631 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 115671 # number of demand (read+write) MSHR misses
3181,3182c3164,3165
< system.iocache.overall_mshr_misses::realview.ide 115615 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 115655 # number of overall MSHR misses
---
> system.iocache.overall_mshr_misses::realview.ide 115631 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 115671 # number of overall MSHR misses
3184,3185c3167,3168
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 1232909553 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 1236259553 # number of ReadReq MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 1341349757 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 1344699757 # number of ReadReq MSHR miss cycles
3188,3189c3171,3172
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7602399187 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 7602399187 # number of WriteLineReq MSHR miss cycles
---
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7839860905 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 7839860905 # number of WriteLineReq MSHR miss cycles
3191,3192c3174,3175
< system.iocache.demand_mshr_miss_latency::realview.ide 8835308740 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 8838877740 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 9181210662 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 9184779662 # number of demand (read+write) MSHR miss cycles
3194,3195c3177,3178
< system.iocache.overall_mshr_miss_latency::realview.ide 8835308740 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 8838877740 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 9181210662 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 9184779662 # number of overall MSHR miss cycles
3210,3211c3193,3194
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138731.805221 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 138531.998319 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 150662.670673 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 150413.843065 # average ReadReq mshr miss latency
3214,3215c3197,3198
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71231.534246 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71231.534246 # average WriteLineReq mshr miss latency
---
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73456.458521 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 73456.458521 # average WriteLineReq mshr miss latency
3217,3218c3200,3201
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 76420.090300 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 76424.518957 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 79400.944920 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 79404.342160 # average overall mshr miss latency
3220,3252c3203,3235
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 76420.090300 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 76424.518957 # average overall mshr miss latency
< system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.l2c.tags.replacements 1575605 # number of replacements
< system.l2c.tags.tagsinuse 65208.311267 # Cycle average of tags in use
< system.l2c.tags.total_refs 6750580 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 1636875 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 4.124066 # Average number of references to valid blocks.
< system.l2c.tags.warmup_cycle 3024712500 # Cycle when the warmup percentage was hit.
< system.l2c.tags.occ_blocks::writebacks 9648.504654 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 430.210636 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 509.722466 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 4113.935017 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 22579.924066 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 21373.967512 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.667516 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 13.437669 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 2580.265558 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 2788.873436 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1154.802739 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.147224 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.006564 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.007778 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.062774 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.344542 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.326141 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000224 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.itb.walker 0.000205 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.039372 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.042555 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.017621 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.995000 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 10940 # Occupied blocks per task id
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 79400.944920 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 79404.342160 # average overall mshr miss latency
> system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.l2c.tags.replacements 1712520 # number of replacements
> system.l2c.tags.tagsinuse 65207.555116 # Cycle average of tags in use
> system.l2c.tags.total_refs 7020190 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 1774780 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 3.955527 # Average number of references to valid blocks.
> system.l2c.tags.warmup_cycle 3083323500 # Cycle when the warmup percentage was hit.
> system.l2c.tags.occ_blocks::writebacks 10815.100932 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 305.602667 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 366.195320 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 3964.024216 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 19638.791484 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14261.868883 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 151.853339 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.itb.walker 181.379081 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 3223.101636 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 5938.767305 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6360.870252 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.165025 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004663 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.005588 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.060486 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.299664 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.217619 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002317 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.itb.walker 0.002768 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.049181 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.090618 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.097059 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.994988 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 11498 # Occupied blocks per task id
3254,3267c3237,3249
< system.l2c.tags.occ_task_id_blocks::1024 50081 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 103 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 404 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 10423 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 244 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 2182 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 3614 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 44004 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.166931 # Percentage of cache occupancy per task id
---
> system.l2c.tags.occ_task_id_blocks::1024 50513 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 1395 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 577 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 9525 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 246 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 2497 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 4893 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 42814 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.175446 # Percentage of cache occupancy per task id
3269,3551c3251,3529
< system.l2c.tags.occ_task_id_percent::1024 0.764175 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 76956529 # Number of tag accesses
< system.l2c.tags.data_accesses 76956529 # Number of data accesses
< system.l2c.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.l2c.WritebackDirty_hits::writebacks 2841841 # number of WritebackDirty hits
< system.l2c.WritebackDirty_hits::total 2841841 # number of WritebackDirty hits
< system.l2c.WritebackClean_hits::writebacks 3 # number of WritebackClean hits
< system.l2c.WritebackClean_hits::total 3 # number of WritebackClean hits
< system.l2c.UpgradeReq_hits::cpu0.data 208782 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 171973 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 380755 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 54097 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 47819 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 101916 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 54890 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 53294 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 108184 # number of ReadExReq hits
< system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 12794 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5104 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.inst 534660 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 628574 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 294599 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 11629 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5041 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.inst 480238 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 542860 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 283154 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 2798653 # number of ReadSharedReq hits
< system.l2c.InvalidateReq_hits::cpu0.data 134880 # number of InvalidateReq hits
< system.l2c.InvalidateReq_hits::cpu1.data 130480 # number of InvalidateReq hits
< system.l2c.InvalidateReq_hits::total 265360 # number of InvalidateReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 12794 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 5104 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 534660 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 683464 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 294599 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 11629 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 5041 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 480238 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 596154 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 283154 # number of demand (read+write) hits
< system.l2c.demand_hits::total 2906837 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 12794 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 5104 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 534660 # number of overall hits
< system.l2c.overall_hits::cpu0.data 683464 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 294599 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 11629 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 5041 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 480238 # number of overall hits
< system.l2c.overall_hits::cpu1.data 596154 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 283154 # number of overall hits
< system.l2c.overall_hits::total 2906837 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 24185 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 25856 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 50041 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 906 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 988 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 1894 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 87757 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 47516 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 135273 # number of ReadExReq misses
< system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3402 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3300 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.inst 61095 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 168033 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 329831 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1494 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.itb.walker 962 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.inst 49649 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 109122 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 190278 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 917166 # number of ReadSharedReq misses
< system.l2c.InvalidateReq_misses::cpu0.data 463890 # number of InvalidateReq misses
< system.l2c.InvalidateReq_misses::cpu1.data 106177 # number of InvalidateReq misses
< system.l2c.InvalidateReq_misses::total 570067 # number of InvalidateReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 3402 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.itb.walker 3300 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.inst 61095 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 255790 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 329831 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 1494 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.itb.walker 962 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 49649 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 156638 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 190278 # number of demand (read+write) misses
< system.l2c.demand_misses::total 1052439 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 3402 # number of overall misses
< system.l2c.overall_misses::cpu0.itb.walker 3300 # number of overall misses
< system.l2c.overall_misses::cpu0.inst 61095 # number of overall misses
< system.l2c.overall_misses::cpu0.data 255790 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 329831 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 1494 # number of overall misses
< system.l2c.overall_misses::cpu1.itb.walker 962 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 49649 # number of overall misses
< system.l2c.overall_misses::cpu1.data 156638 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 190278 # number of overall misses
< system.l2c.overall_misses::total 1052439 # number of overall misses
< system.l2c.UpgradeReq_miss_latency::cpu0.data 155584500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 165207000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 320791500 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 10231000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 8907000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 19138000 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 8384405997 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 4313472997 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 12697878994 # number of ReadExReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 311169000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 297359500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5460514000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 16355884996 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 47369049298 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 141229500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 92798500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.inst 4383525500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.data 10640360000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 27539015255 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::total 112590905549 # number of ReadSharedReq miss cycles
< system.l2c.InvalidateReq_miss_latency::cpu0.data 36778500 # number of InvalidateReq miss cycles
< system.l2c.InvalidateReq_miss_latency::cpu1.data 35261000 # number of InvalidateReq miss cycles
< system.l2c.InvalidateReq_miss_latency::total 72039500 # number of InvalidateReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 311169000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 297359500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 5460514000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 24740290993 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 47369049298 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 141229500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.itb.walker 92798500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 4383525500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 14953832997 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 27539015255 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 125288784543 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 311169000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 297359500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 5460514000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 24740290993 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 47369049298 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 141229500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.itb.walker 92798500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 4383525500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 14953832997 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 27539015255 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 125288784543 # number of overall miss cycles
< system.l2c.WritebackDirty_accesses::writebacks 2841841 # number of WritebackDirty accesses(hits+misses)
< system.l2c.WritebackDirty_accesses::total 2841841 # number of WritebackDirty accesses(hits+misses)
< system.l2c.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses)
< system.l2c.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 232967 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 197829 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 430796 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 55003 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 48807 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 103810 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 142647 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 100810 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 243457 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 16196 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 8404 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.inst 595755 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 796607 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 624430 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 13123 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6003 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.inst 529887 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 651982 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 473432 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 3715819 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.InvalidateReq_accesses::cpu0.data 598770 # number of InvalidateReq accesses(hits+misses)
< system.l2c.InvalidateReq_accesses::cpu1.data 236657 # number of InvalidateReq accesses(hits+misses)
< system.l2c.InvalidateReq_accesses::total 835427 # number of InvalidateReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 16196 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 8404 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 595755 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 939254 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 624430 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 13123 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 6003 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 529887 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 752792 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 473432 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 3959276 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 16196 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 8404 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 595755 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 939254 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 624430 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 13123 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 6003 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 529887 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 752792 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 473432 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 3959276 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.103813 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.130699 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.116159 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.016472 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.020243 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.018245 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.615204 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.471342 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.555634 # miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.210052 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.392670 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.102551 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.210936 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.528211 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.113846 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.160253 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.093697 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.167370 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.401912 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.246827 # miss rate for ReadSharedReq accesses
< system.l2c.InvalidateReq_miss_rate::cpu0.data 0.774738 # miss rate for InvalidateReq accesses
< system.l2c.InvalidateReq_miss_rate::cpu1.data 0.448654 # miss rate for InvalidateReq accesses
< system.l2c.InvalidateReq_miss_rate::total 0.682366 # miss rate for InvalidateReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.210052 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.392670 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.102551 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.272333 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.528211 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.113846 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.160253 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.093697 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.208076 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.401912 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.265816 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.210052 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.392670 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.102551 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.272333 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.528211 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.113846 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.160253 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.093697 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.208076 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.401912 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.265816 # miss rate for overall accesses
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6433.099028 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6389.503403 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 6410.573330 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 11292.494481 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9015.182186 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 10104.540655 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 95541.164773 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 90779.379514 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 93868.539871 # average ReadExReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 91466.490300 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 90108.939394 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 89377.428595 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 97337.338475 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 143616.122493 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 94531.124498 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 96464.137214 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 88290.307962 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 97508.843313 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 144730.422093 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::total 122759.571930 # average ReadSharedReq miss latency
< system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 79.282804 # average InvalidateReq miss latency
< system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 332.096405 # average InvalidateReq miss latency
< system.l2c.InvalidateReq_avg_miss_latency::total 126.370234 # average InvalidateReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 91466.490300 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 90108.939394 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 89377.428595 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 96721.103221 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 143616.122493 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 94531.124498 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.itb.walker 96464.137214 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 88290.307962 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 95467.466368 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 144730.422093 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 119046.124804 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 91466.490300 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 90108.939394 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 89377.428595 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 96721.103221 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 143616.122493 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 94531.124498 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.itb.walker 96464.137214 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 88290.307962 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 95467.466368 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 144730.422093 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 119046.124804 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 7554 # number of cycles access was blocked
---
> system.l2c.tags.occ_task_id_percent::1024 0.770767 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 80570058 # Number of tag accesses
> system.l2c.tags.data_accesses 80570058 # Number of data accesses
> system.l2c.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.l2c.WritebackDirty_hits::writebacks 2973062 # number of WritebackDirty hits
> system.l2c.WritebackDirty_hits::total 2973062 # number of WritebackDirty hits
> system.l2c.UpgradeReq_hits::cpu0.data 212913 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 179277 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 392190 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 55777 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 49656 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 105433 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 53324 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 56619 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 109943 # number of ReadExReq hits
> system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 12274 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4633 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.inst 532793 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 642111 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 285366 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12502 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5292 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.inst 506134 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 588825 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 298655 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 2888585 # number of ReadSharedReq hits
> system.l2c.InvalidateReq_hits::cpu0.data 133712 # number of InvalidateReq hits
> system.l2c.InvalidateReq_hits::cpu1.data 132940 # number of InvalidateReq hits
> system.l2c.InvalidateReq_hits::total 266652 # number of InvalidateReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 12274 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 4633 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 532793 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 695435 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 285366 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 12502 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 5292 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 506134 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 645444 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 298655 # number of demand (read+write) hits
> system.l2c.demand_hits::total 2998528 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 12274 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 4633 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 532793 # number of overall hits
> system.l2c.overall_hits::cpu0.data 695435 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 285366 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 12502 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 5292 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 506134 # number of overall hits
> system.l2c.overall_hits::cpu1.data 645444 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 298655 # number of overall hits
> system.l2c.overall_hits::total 2998528 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 25668 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 25681 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 51349 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 646 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 809 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 1455 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 94289 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 48061 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 142350 # number of ReadExReq misses
> system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3531 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3298 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.inst 60576 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 185593 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 348444 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2063 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1546 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.inst 53773 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 117277 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 240910 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 1017011 # number of ReadSharedReq misses
> system.l2c.InvalidateReq_misses::cpu0.data 478287 # number of InvalidateReq misses
> system.l2c.InvalidateReq_misses::cpu1.data 112149 # number of InvalidateReq misses
> system.l2c.InvalidateReq_misses::total 590436 # number of InvalidateReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 3531 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.itb.walker 3298 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.inst 60576 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 279882 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 348444 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 2063 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.itb.walker 1546 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 53773 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 165338 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 240910 # number of demand (read+write) misses
> system.l2c.demand_misses::total 1159361 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 3531 # number of overall misses
> system.l2c.overall_misses::cpu0.itb.walker 3298 # number of overall misses
> system.l2c.overall_misses::cpu0.inst 60576 # number of overall misses
> system.l2c.overall_misses::cpu0.data 279882 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 348444 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 2063 # number of overall misses
> system.l2c.overall_misses::cpu1.itb.walker 1546 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 53773 # number of overall misses
> system.l2c.overall_misses::cpu1.data 165338 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 240910 # number of overall misses
> system.l2c.overall_misses::total 1159361 # number of overall misses
> system.l2c.UpgradeReq_miss_latency::cpu0.data 172222000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 155225500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 327447500 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 9175000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5803000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 14978000 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 10233917991 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 5260660499 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 15494578490 # number of ReadExReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 356299000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 337167500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6654556500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 20784674000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 53218202875 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 218154000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 160424000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6046329000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.data 13882177499 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 36908535986 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::total 138566520360 # number of ReadSharedReq miss cycles
> system.l2c.InvalidateReq_miss_latency::cpu0.data 31590000 # number of InvalidateReq miss cycles
> system.l2c.InvalidateReq_miss_latency::cpu1.data 32968000 # number of InvalidateReq miss cycles
> system.l2c.InvalidateReq_miss_latency::total 64558000 # number of InvalidateReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 356299000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 337167500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 6654556500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 31018591991 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 53218202875 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 218154000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.itb.walker 160424000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 6046329000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 19142837998 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 36908535986 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 154061098850 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 356299000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 337167500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 6654556500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 31018591991 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 53218202875 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 218154000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.itb.walker 160424000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 6046329000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 19142837998 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 36908535986 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 154061098850 # number of overall miss cycles
> system.l2c.WritebackDirty_accesses::writebacks 2973062 # number of WritebackDirty accesses(hits+misses)
> system.l2c.WritebackDirty_accesses::total 2973062 # number of WritebackDirty accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 238581 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 204958 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 443539 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 56423 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 50465 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 106888 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 147613 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 104680 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 252293 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 15805 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7931 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.inst 593369 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 827704 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 633810 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 14565 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6838 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.inst 559907 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 706102 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 539565 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 3905596 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.InvalidateReq_accesses::cpu0.data 611999 # number of InvalidateReq accesses(hits+misses)
> system.l2c.InvalidateReq_accesses::cpu1.data 245089 # number of InvalidateReq accesses(hits+misses)
> system.l2c.InvalidateReq_accesses::total 857088 # number of InvalidateReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 15805 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 7931 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 593369 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 975317 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 633810 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 14565 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 6838 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 559907 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 810782 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 539565 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 4157889 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 15805 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 7931 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 593369 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 975317 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 633810 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 14565 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 6838 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 559907 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 810782 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 539565 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 4157889 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.107586 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.125299 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.115771 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.011449 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.016031 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.013612 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.638758 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.459123 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.564225 # miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.223410 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.415837 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.102088 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.224226 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.549761 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.141641 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.226089 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.096039 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.166091 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.446489 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.260398 # miss rate for ReadSharedReq accesses
> system.l2c.InvalidateReq_miss_rate::cpu0.data 0.781516 # miss rate for InvalidateReq accesses
> system.l2c.InvalidateReq_miss_rate::cpu1.data 0.457585 # miss rate for InvalidateReq accesses
> system.l2c.InvalidateReq_miss_rate::total 0.688886 # miss rate for InvalidateReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.223410 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.415837 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.102088 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.286965 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.549761 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.141641 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.226089 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.096039 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.203924 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.446489 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.278834 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.223410 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.415837 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.102088 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.286965 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.549761 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.141641 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.226089 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.096039 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.203924 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.446489 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.278834 # miss rate for overall accesses
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6709.599501 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6044.371325 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 6376.901205 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14202.786378 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 7173.053152 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 10294.158076 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 108537.772073 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109457.990866 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 108848.461468 # average ReadExReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 100905.975644 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 102233.929654 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109854.670166 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 111990.613870 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 152731.006632 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 105746.000969 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103767.141009 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 112441.727261 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 118370.844232 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 153204.665585 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::total 136248.792157 # average ReadSharedReq miss latency
> system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 66.048210 # average InvalidateReq miss latency
> system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 293.966063 # average InvalidateReq miss latency
> system.l2c.InvalidateReq_avg_miss_latency::total 109.339539 # average InvalidateReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100905.975644 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 102233.929654 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 109854.670166 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 110827.391511 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 152731.006632 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 105746.000969 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.itb.walker 103767.141009 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 112441.727261 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 115780.026358 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 153204.665585 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 132884.493139 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100905.975644 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 102233.929654 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 109854.670166 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 110827.391511 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 152731.006632 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 105746.000969 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.itb.walker 103767.141009 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 112441.727261 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 115780.026358 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 153204.665585 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 132884.493139 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 11042 # number of cycles access was blocked
3553c3531
< system.l2c.blocked::no_mshrs 86 # number of cycles access was blocked
---
> system.l2c.blocked::no_mshrs 109 # number of cycles access was blocked
3555c3533
< system.l2c.avg_blocked_cycles::no_mshrs 87.837209 # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs 101.302752 # average number of cycles each access was blocked
3557,3620c3535,3598
< system.l2c.writebacks::writebacks 1208317 # number of writebacks
< system.l2c.writebacks::total 1208317 # number of writebacks
< system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 117 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu0.data 19 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 105 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.data 30 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::total 271 # number of ReadSharedReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 117 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu0.data 19 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 105 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.data 30 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 271 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 117 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu0.data 19 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 105 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.data 30 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 271 # number of overall MSHR hits
< system.l2c.CleanEvict_mshr_misses::writebacks 63698 # number of CleanEvict MSHR misses
< system.l2c.CleanEvict_mshr_misses::total 63698 # number of CleanEvict MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 24185 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 25856 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 50041 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 906 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 988 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 1894 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 87757 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 47516 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 135273 # number of ReadExReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 3402 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3300 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 60978 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.data 168014 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 329831 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1494 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 962 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 49544 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.data 109092 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 190278 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::total 916895 # number of ReadSharedReq MSHR misses
< system.l2c.InvalidateReq_mshr_misses::cpu0.data 463890 # number of InvalidateReq MSHR misses
< system.l2c.InvalidateReq_mshr_misses::cpu1.data 106177 # number of InvalidateReq MSHR misses
< system.l2c.InvalidateReq_mshr_misses::total 570067 # number of InvalidateReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 3402 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.itb.walker 3300 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 60978 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 255771 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 329831 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 1494 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.itb.walker 962 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 49544 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 156608 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 190278 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 1052168 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 3402 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.itb.walker 3300 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 60978 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 255771 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 329831 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 1494 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.itb.walker 962 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 49544 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 156608 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 190278 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 1052168 # number of overall MSHR misses
---
> system.l2c.writebacks::writebacks 1306567 # number of writebacks
> system.l2c.writebacks::total 1306567 # number of writebacks
> system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 94 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu0.data 23 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 174 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.data 24 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::total 315 # number of ReadSharedReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 94 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu0.data 23 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 174 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 94 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu0.data 23 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 174 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 315 # number of overall MSHR hits
> system.l2c.CleanEvict_mshr_misses::writebacks 73117 # number of CleanEvict MSHR misses
> system.l2c.CleanEvict_mshr_misses::total 73117 # number of CleanEvict MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 25668 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 25681 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 51349 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 646 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 809 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 1455 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 94289 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 48061 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 142350 # number of ReadExReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 3531 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3298 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 60482 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.data 185570 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 348444 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2063 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1546 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 53599 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.data 117253 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 240910 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::total 1016696 # number of ReadSharedReq MSHR misses
> system.l2c.InvalidateReq_mshr_misses::cpu0.data 478287 # number of InvalidateReq MSHR misses
> system.l2c.InvalidateReq_mshr_misses::cpu1.data 112149 # number of InvalidateReq MSHR misses
> system.l2c.InvalidateReq_mshr_misses::total 590436 # number of InvalidateReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 3531 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.itb.walker 3298 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 60482 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 279859 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 348444 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 2063 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.itb.walker 1546 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 53599 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 165314 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 240910 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 1159046 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 3531 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.itb.walker 3298 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 60482 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 279859 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 348444 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 2063 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.itb.walker 1546 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 53599 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 165314 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 240910 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 1159046 # number of overall MSHR misses
3622,3626c3600,3604
< system.l2c.ReadReq_mshr_uncacheable::cpu0.data 17085 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 68 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::cpu1.data 21230 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::total 59676 # number of ReadReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu0.data 18834 # number of WriteReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16980 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 21289 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 59629 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 18801 # number of WriteReq MSHR uncacheable
3628c3606
< system.l2c.WriteReq_mshr_uncacheable::total 38244 # number of WriteReq MSHR uncacheable
---
> system.l2c.WriteReq_mshr_uncacheable::total 38211 # number of WriteReq MSHR uncacheable
3630,3688c3608,3666
< system.l2c.overall_mshr_uncacheable_misses::cpu0.data 35919 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 68 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::cpu1.data 40640 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::total 97920 # number of overall MSHR uncacheable misses
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 483874498 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 540970500 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 1024844998 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 22167999 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 24045000 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 46212999 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7506749175 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3838136855 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 11344886030 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 277149000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 264359500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 4841507552 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14674367202 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 44070592122 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 126288502 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 83178500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3879884570 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 9547031729 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 25636045664 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::total 103400404341 # number of ReadSharedReq MSHR miss cycles
< system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 11548986121 # number of InvalidateReq MSHR miss cycles
< system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2199719000 # number of InvalidateReq MSHR miss cycles
< system.l2c.InvalidateReq_mshr_miss_latency::total 13748705121 # number of InvalidateReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 277149000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 264359500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 4841507552 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 22181116377 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 44070592122 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 126288502 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 83178500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 3879884570 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 13385168584 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 25636045664 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 114745290371 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 277149000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 264359500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 4841507552 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 22181116377 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 44070592122 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 126288502 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 83178500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 3879884570 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 13385168584 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 25636045664 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 114745290371 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1342704500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2770278503 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4446500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3166216503 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 7283646006 # number of ReadReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1342704500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2770278503 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4446500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3166216503 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 7283646006 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 35781 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 40699 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 97840 # number of overall MSHR uncacheable misses
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 520949500 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 534002500 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 1054952000 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15625500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 19999000 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 35624500 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 9290880791 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4779832460 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 14070713251 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 320987004 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 304187500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6041672064 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 18926430190 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 49733607723 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 197523002 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 144964000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5494647043 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 12706523221 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 34499199531 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::total 128369741278 # number of ReadSharedReq MSHR miss cycles
> system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 11811554063 # number of InvalidateReq MSHR miss cycles
> system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2326727500 # number of InvalidateReq MSHR miss cycles
> system.l2c.InvalidateReq_mshr_miss_latency::total 14138281563 # number of InvalidateReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 320987004 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 304187500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 6041672064 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 28217310981 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 49733607723 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 197523002 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 144964000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 5494647043 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 17486355681 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 34499199531 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 142440454529 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 320987004 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 304187500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 6041672064 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 28217310981 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 49733607723 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 197523002 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 144964000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 5494647043 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 17486355681 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 34499199531 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 142440454529 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1484185500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2691376000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5368000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3243740000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 7424669500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1484185500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2691376000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5368000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3243740000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 7424669500 # number of overall MSHR uncacheable cycles
3691,3793c3669,3771
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.103813 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.130699 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.116159 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.016472 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.020243 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.018245 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.615204 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.471342 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.555634 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.210052 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.392670 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.102354 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.210912 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.528211 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.113846 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.160253 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.093499 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.167324 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.401912 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::total 0.246754 # mshr miss rate for ReadSharedReq accesses
< system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.774738 # mshr miss rate for InvalidateReq accesses
< system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.448654 # mshr miss rate for InvalidateReq accesses
< system.l2c.InvalidateReq_mshr_miss_rate::total 0.682366 # mshr miss rate for InvalidateReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.210052 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.392670 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102354 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.272313 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.528211 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.113846 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.160253 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.093499 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.208036 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.401912 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.265748 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.210052 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.392670 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102354 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.272313 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.528211 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.113846 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.160253 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.093499 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.208036 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.401912 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.265748 # mshr miss rate for overall accesses
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20007.215133 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20922.435798 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20480.106273 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24467.990066 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24337.044534 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24399.682682 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85540.175428 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 80775.672510 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 83866.595921 # average ReadExReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 81466.490300 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80108.939394 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 79397.611466 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 87340.145476 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133615.676277 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 84530.456493 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 86464.137214 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 78311.895891 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 87513.582380 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134729.425703 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 112772.350532 # average ReadSharedReq mshr miss latency
< system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24895.958354 # average InvalidateReq mshr miss latency
< system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20717.471769 # average InvalidateReq mshr miss latency
< system.l2c.InvalidateReq_avg_mshr_miss_latency::total 24117.700412 # average InvalidateReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 81466.490300 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80108.939394 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 79397.611466 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 86722.561889 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133615.676277 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 84530.456493 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 86464.137214 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 78311.895891 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 85469.251788 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134729.425703 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 109056.054139 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 81466.490300 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80108.939394 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 79397.611466 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 86722.561889 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133615.676277 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 84530.456493 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 86464.137214 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 78311.895891 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 85469.251788 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134729.425703 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 109056.054139 # average overall mshr miss latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162146.824876 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 65389.705882 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 149138.789590 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 122053.187311 # average ReadReq mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 77125.713494 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 65389.705882 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77908.870645 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 74383.639767 # average overall mshr uncacheable latency
< system.membus.snoop_filter.tot_requests 3980803 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 2353726 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.membus.snoop_filter.hit_multi_requests 3243 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
---
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.107586 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.125299 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.115771 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.011449 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016031 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.013612 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.638758 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.459123 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.564225 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.223410 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.415837 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.101930 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.224199 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.549761 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.141641 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.226089 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.095728 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.166057 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.446489 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260318 # mshr miss rate for ReadSharedReq accesses
> system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.781516 # mshr miss rate for InvalidateReq accesses
> system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.457585 # mshr miss rate for InvalidateReq accesses
> system.l2c.InvalidateReq_mshr_miss_rate::total 0.688886 # mshr miss rate for InvalidateReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.223410 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.415837 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.101930 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.286942 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.549761 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.141641 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.226089 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.095728 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.203895 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.446489 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.278758 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.223410 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.415837 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.101930 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.286942 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.549761 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.141641 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.226089 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.095728 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.203895 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.446489 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.278758 # mshr miss rate for overall accesses
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20295.679445 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20793.680153 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20544.742838 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24188.080495 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24720.642769 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24484.192440 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98536.210915 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99453.454152 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 98845.895687 # average ReadExReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90905.410365 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 92233.929654 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99892.068119 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101990.786172 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142730.561361 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 95745.517208 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93767.141009 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 102513.984272 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 108368.427426 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143203.684077 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126261.676330 # average ReadSharedReq mshr miss latency
> system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24695.536494 # average InvalidateReq mshr miss latency
> system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20746.752089 # average InvalidateReq mshr miss latency
> system.l2c.InvalidateReq_avg_mshr_miss_latency::total 23945.493776 # average InvalidateReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90905.410365 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 92233.929654 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99892.068119 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 100826.884185 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142730.561361 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 95745.517208 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93767.141009 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 102513.984272 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 105776.617110 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143203.684077 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 122894.565469 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90905.410365 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 92233.929654 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99892.068119 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 100826.884185 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142730.561361 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 95745.517208 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93767.141009 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 102513.984272 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 105776.617110 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143203.684077 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 122894.565469 # average overall mshr miss latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158502.709069 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 80119.402985 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152366.950068 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 124514.405742 # average ReadReq mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 75218.020737 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 80119.402985 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 79700.729748 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 75885.828904 # average overall mshr uncacheable latency
> system.membus.snoop_filter.tot_requests 4262418 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 2509154 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 3063 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3797,3812c3775,3789
< system.membus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadReq 59676 # Transaction distribution
< system.membus.trans_dist::ReadResp 985495 # Transaction distribution
< system.membus.trans_dist::WriteReq 38244 # Transaction distribution
< system.membus.trans_dist::WriteResp 38244 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 1315010 # Transaction distribution
< system.membus.trans_dist::CleanEvict 256715 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 339680 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 271581 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 24 # Transaction distribution
< system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
< system.membus.trans_dist::ReadExReq 147332 # Transaction distribution
< system.membus.trans_dist::ReadExResp 134542 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 925819 # Transaction distribution
< system.membus.trans_dist::InvalidateReq 674453 # Transaction distribution
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122580 # Packet count per connected master and slave (bytes)
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadReq 59629 # Transaction distribution
> system.membus.trans_dist::ReadResp 1085265 # Transaction distribution
> system.membus.trans_dist::WriteReq 38211 # Transaction distribution
> system.membus.trans_dist::WriteResp 38211 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 1413261 # Transaction distribution
> system.membus.trans_dist::CleanEvict 284296 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 353595 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 284030 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 23 # Transaction distribution
> system.membus.trans_dist::ReadExReq 155418 # Transaction distribution
> system.membus.trans_dist::ReadExResp 141619 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 1025636 # Transaction distribution
> system.membus.trans_dist::InvalidateReq 695069 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes)
3814,3820c3791,3797
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25318 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4797896 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 4945870 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237932 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 237932 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 5183802 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155710 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25156 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5185454 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 5333270 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238137 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 238137 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 5571407 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155691 # Cumulative packet size per connected master and slave (bytes)
3822,3832c3799,3809
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50636 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 144939472 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 145146374 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7255040 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 7255040 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 152401414 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 572055 # Total snoops (count)
< system.membus.snoopTraffic 191360 # Total snoop traffic (bytes)
< system.membus.snoop_fanout::samples 2456788 # Request fanout histogram
< system.membus.snoop_fanout::mean 0.015156 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0.122173 # Request fanout histogram
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50312 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 158067712 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 158274271 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7266112 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 7266112 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 165540383 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 598647 # Total snoops (count)
> system.membus.snoopTraffic 181312 # Total snoop traffic (bytes)
> system.membus.snoop_fanout::samples 2611590 # Request fanout histogram
> system.membus.snoop_fanout::mean 0.013385 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.114916 # Request fanout histogram
3834,3835c3811,3812
< system.membus.snoop_fanout::0 2419553 98.48% 98.48% # Request fanout histogram
< system.membus.snoop_fanout::1 37235 1.52% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 2576634 98.66% 98.66% # Request fanout histogram
> system.membus.snoop_fanout::1 34956 1.34% 100.00% # Request fanout histogram
3840,3841c3817,3818
< system.membus.snoop_fanout::total 2456788 # Request fanout histogram
< system.membus.reqLayer0.occupancy 98064494 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 2611590 # Request fanout histogram
> system.membus.reqLayer0.occupancy 98274995 # Layer occupancy (ticks)
3845c3822
< system.membus.reqLayer2.occupancy 21142497 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 20993495 # Layer occupancy (ticks)
3847c3824
< system.membus.reqLayer5.occupancy 9055699898 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 9731390131 # Layer occupancy (ticks)
3849c3826
< system.membus.respLayer2.occupancy 5680392120 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 6232103011 # Layer occupancy (ticks)
3851c3828
< system.membus.respLayer3.occupancy 45554532 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 45620246 # Layer occupancy (ticks)
3853,3859c3830,3836
< system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
---
> system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
3866,3867c3843,3844
< system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
---
> system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
3910,3916c3887,3893
< system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
---
> system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
3921,3967c3898,3943
< system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.toL2Bus.snoop_filter.tot_requests 11893981 # Total number of requests made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_requests 6468498 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_requests 1904661 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.snoop_filter.tot_snoops 211231 # Total number of snoops made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_snoops 193743 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_snoops 17488 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
< system.toL2Bus.trans_dist::ReadReq 59678 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 4527289 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 38244 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 38244 # Transaction distribution
< system.toL2Bus.trans_dist::WritebackDirty 4050158 # Transaction distribution
< system.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 2718586 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 717362 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 373497 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 1090859 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 125 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 293033 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 293033 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 4468431 # Transaction distribution
< system.toL2Bus.trans_dist::InvalidateReq 869390 # Transaction distribution
< system.toL2Bus.trans_dist::InvalidateResp 835427 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9945746 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7459601 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 17405347 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 252717925 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 183230753 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 435948678 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 2969827 # Total snoops (count)
< system.toL2Bus.snoopTraffic 128627856 # Total snoop traffic (bytes)
< system.toL2Bus.snoop_fanout::samples 8396274 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 0.355668 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.483046 # Request fanout histogram
---
> system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.toL2Bus.snoop_filter.tot_requests 12430379 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 6756092 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 1976828 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.snoop_filter.tot_snoops 231635 # Total number of snoops made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_snoops 213178 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_snoops 18457 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states
> system.toL2Bus.trans_dist::ReadReq 59631 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 4752657 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 38211 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 38211 # Transaction distribution
> system.toL2Bus.trans_dist::WritebackDirty 4279629 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 2861492 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 742959 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 389463 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 1132422 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 133 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 304770 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 304770 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 4693673 # Transaction distribution
> system.toL2Bus.trans_dist::InvalidateReq 888953 # Transaction distribution
> system.toL2Bus.trans_dist::InvalidateResp 857088 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10167135 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8009990 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 18177125 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 258318649 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 198738470 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 457057119 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 3168754 # Total snoops (count)
> system.toL2Bus.snoopTraffic 137382864 # Total snoop traffic (bytes)
> system.toL2Bus.snoop_fanout::samples 8831298 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 0.353414 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.482382 # Request fanout histogram
3969,3971c3945,3947
< system.toL2Bus.snoop_fanout::0 5427479 64.64% 64.64% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 2951307 35.15% 99.79% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 17488 0.21% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 5728650 64.87% 64.87% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 3084191 34.92% 99.79% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 18457 0.21% 100.00% # Request fanout histogram
3975,3976c3951,3952
< system.toL2Bus.snoop_fanout::total 8396274 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 9289434840 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 8831298 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 9716591105 # Layer occupancy (ticks)
3978c3954
< system.toL2Bus.snoopLayer0.occupancy 2606647 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 2596400 # Layer occupancy (ticks)
3980c3956
< system.toL2Bus.respLayer0.occupancy 4518737086 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 4626263938 # Layer occupancy (ticks)
3982c3958
< system.toL2Bus.respLayer1.occupancy 3678115853 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 3958447661 # Layer occupancy (ticks)
3985c3961
< system.cpu0.kern.inst.quiesce 5420 # number of quiesce instructions executed
---
> system.cpu0.kern.inst.quiesce 5035 # number of quiesce instructions executed
3987c3963
< system.cpu1.kern.inst.quiesce 13392 # number of quiesce instructions executed
---
> system.cpu1.kern.inst.quiesce 13834 # number of quiesce instructions executed