Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt

Deleted Added

sdiff udiff text old ( 11336:b318499f676c ) new ( 11353:31c5786945b4 )

full compact

3,5c3,5
< sim_seconds 47.354243 # Number of seconds simulated
< sim_ticks 47354242877000 # Number of ticks simulated
< final_tick 47354242877000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 47.389788 # Number of seconds simulated
> sim_ticks 47389787812000 # Number of ticks simulated
> final_tick 47389787812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 195342 # Simulator instruction rate (inst/s)
< host_op_rate 229691 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 10034841905 # Simulator tick rate (ticks/s)
< host_mem_usage 778832 # Number of bytes of host memory used
< host_seconds 4718.98 # Real time elapsed on the host
< sim_insts 921815819 # Number of instructions simulated
< sim_ops 1083910027 # Number of ops (including micro ops) simulated
---
> host_inst_rate 198747 # Simulator instruction rate (inst/s)
> host_op_rate 233711 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 10002045644 # Simulator tick rate (ticks/s)
> host_mem_usage 770464 # Number of bytes of host memory used
> host_seconds 4738.01 # Real time elapsed on the host
> sim_insts 941666991 # Number of instructions simulated
> sim_ops 1107326086 # Number of ops (including micro ops) simulated
16,31c16,31
< system.physmem.bytes_read::cpu0.dtb.walker 202368 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.itb.walker 196224 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.inst 4450144 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 45350984 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 22283904 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 113792 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.itb.walker 85504 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 2862048 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 13865872 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 12452160 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 439808 # Number of bytes read from this memory
< system.physmem.bytes_read::total 102302808 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 4450144 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 2862048 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 7312192 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 85371072 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu0.dtb.walker 242048 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.itb.walker 235072 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.inst 4481952 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 17644744 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 24714560 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 130176 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.itb.walker 100480 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 2927520 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 10373200 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 13817664 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 418560 # Number of bytes read from this memory
> system.physmem.bytes_read::total 75085976 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 4481952 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 2927520 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 7409472 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 91336640 # Number of bytes written to this memory
34,47c34,47
< system.physmem.bytes_written::total 85391656 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.dtb.walker 3162 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.itb.walker 3066 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.inst 85486 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 708622 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 348186 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 1778 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.itb.walker 1336 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 44763 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 216667 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 194565 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6872 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1614503 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1333923 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 91357224 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.dtb.walker 3782 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.itb.walker 3673 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.inst 85983 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 275712 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 386165 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 2034 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.itb.walker 1570 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 45786 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 162094 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 215901 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6540 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1189240 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1427135 # Number of write requests responded to by this memory
50,67c50,67
< system.physmem.num_writes::total 1336497 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 4273 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.itb.walker 4144 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.inst 93976 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 957696 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 470579 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 2403 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.itb.walker 1806 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 60439 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 292812 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 262958 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 9288 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2160373 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 93976 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 60439 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 154415 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1802818 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 1429709 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 5108 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.itb.walker 4960 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.inst 94576 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 372332 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 521517 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 2747 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.itb.walker 2120 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 61775 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 218891 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 291575 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 8832 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1584434 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 94576 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 61775 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 156352 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1927349 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
69,92c69,92
< system.physmem.bw_write::total 1803252 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1802818 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 4273 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.itb.walker 4144 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 93976 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 958131 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 470579 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 2403 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.itb.walker 1806 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 60439 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 292812 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 262958 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 9288 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 3963625 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 1614503 # Number of read requests accepted
< system.physmem.writeReqs 1336497 # Number of write requests accepted
< system.physmem.readBursts 1614503 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1336497 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 103293760 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 34432 # Total number of bytes read from write queue
< system.physmem.bytesWritten 85390720 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 102302808 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 85391656 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 538 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_write::total 1927783 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1927349 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 5108 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.itb.walker 4960 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 94576 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 372766 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 521517 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 2747 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.itb.walker 2120 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 61775 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 218891 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 291575 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 8832 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3512217 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 1189240 # Number of read requests accepted
> system.physmem.writeReqs 1429709 # Number of write requests accepted
> system.physmem.readBursts 1189240 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1429709 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 76085248 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 26112 # Total number of bytes read from write queue
> system.physmem.bytesWritten 91355968 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 75085976 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 91357224 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 408 # Number of DRAM read bursts serviced by the write queue
95,126c95,126
< system.physmem.perBankRdBursts::0 97103 # Per bank write bursts
< system.physmem.perBankRdBursts::1 99552 # Per bank write bursts
< system.physmem.perBankRdBursts::2 98906 # Per bank write bursts
< system.physmem.perBankRdBursts::3 103577 # Per bank write bursts
< system.physmem.perBankRdBursts::4 99773 # Per bank write bursts
< system.physmem.perBankRdBursts::5 105983 # Per bank write bursts
< system.physmem.perBankRdBursts::6 104785 # Per bank write bursts
< system.physmem.perBankRdBursts::7 101396 # Per bank write bursts
< system.physmem.perBankRdBursts::8 95400 # Per bank write bursts
< system.physmem.perBankRdBursts::9 122614 # Per bank write bursts
< system.physmem.perBankRdBursts::10 95999 # Per bank write bursts
< system.physmem.perBankRdBursts::11 101585 # Per bank write bursts
< system.physmem.perBankRdBursts::12 99838 # Per bank write bursts
< system.physmem.perBankRdBursts::13 98462 # Per bank write bursts
< system.physmem.perBankRdBursts::14 93633 # Per bank write bursts
< system.physmem.perBankRdBursts::15 95359 # Per bank write bursts
< system.physmem.perBankWrBursts::0 80772 # Per bank write bursts
< system.physmem.perBankWrBursts::1 85062 # Per bank write bursts
< system.physmem.perBankWrBursts::2 82679 # Per bank write bursts
< system.physmem.perBankWrBursts::3 85393 # Per bank write bursts
< system.physmem.perBankWrBursts::4 84018 # Per bank write bursts
< system.physmem.perBankWrBursts::5 87943 # Per bank write bursts
< system.physmem.perBankWrBursts::6 87092 # Per bank write bursts
< system.physmem.perBankWrBursts::7 86427 # Per bank write bursts
< system.physmem.perBankWrBursts::8 80096 # Per bank write bursts
< system.physmem.perBankWrBursts::9 84617 # Per bank write bursts
< system.physmem.perBankWrBursts::10 79653 # Per bank write bursts
< system.physmem.perBankWrBursts::11 85236 # Per bank write bursts
< system.physmem.perBankWrBursts::12 82895 # Per bank write bursts
< system.physmem.perBankWrBursts::13 82853 # Per bank write bursts
< system.physmem.perBankWrBursts::14 78695 # Per bank write bursts
< system.physmem.perBankWrBursts::15 80799 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 75559 # Per bank write bursts
> system.physmem.perBankRdBursts::1 80347 # Per bank write bursts
> system.physmem.perBankRdBursts::2 72779 # Per bank write bursts
> system.physmem.perBankRdBursts::3 76774 # Per bank write bursts
> system.physmem.perBankRdBursts::4 67339 # Per bank write bursts
> system.physmem.perBankRdBursts::5 74455 # Per bank write bursts
> system.physmem.perBankRdBursts::6 73080 # Per bank write bursts
> system.physmem.perBankRdBursts::7 76470 # Per bank write bursts
> system.physmem.perBankRdBursts::8 66258 # Per bank write bursts
> system.physmem.perBankRdBursts::9 90024 # Per bank write bursts
> system.physmem.perBankRdBursts::10 66637 # Per bank write bursts
> system.physmem.perBankRdBursts::11 75253 # Per bank write bursts
> system.physmem.perBankRdBursts::12 70442 # Per bank write bursts
> system.physmem.perBankRdBursts::13 75330 # Per bank write bursts
> system.physmem.perBankRdBursts::14 75010 # Per bank write bursts
> system.physmem.perBankRdBursts::15 73075 # Per bank write bursts
> system.physmem.perBankWrBursts::0 90501 # Per bank write bursts
> system.physmem.perBankWrBursts::1 95401 # Per bank write bursts
> system.physmem.perBankWrBursts::2 90023 # Per bank write bursts
> system.physmem.perBankWrBursts::3 92589 # Per bank write bursts
> system.physmem.perBankWrBursts::4 84855 # Per bank write bursts
> system.physmem.perBankWrBursts::5 90903 # Per bank write bursts
> system.physmem.perBankWrBursts::6 89246 # Per bank write bursts
> system.physmem.perBankWrBursts::7 91287 # Per bank write bursts
> system.physmem.perBankWrBursts::8 85201 # Per bank write bursts
> system.physmem.perBankWrBursts::9 88427 # Per bank write bursts
> system.physmem.perBankWrBursts::10 83204 # Per bank write bursts
> system.physmem.perBankWrBursts::11 90055 # Per bank write bursts
> system.physmem.perBankWrBursts::12 88087 # Per bank write bursts
> system.physmem.perBankWrBursts::13 89545 # Per bank write bursts
> system.physmem.perBankWrBursts::14 89641 # Per bank write bursts
> system.physmem.perBankWrBursts::15 88472 # Per bank write bursts
128,129c128,129
< system.physmem.numWrRetry 46 # Number of times write queue was full causing retry
< system.physmem.totGap 47354241269500 # Total gap between requests
---
> system.physmem.numWrRetry 54 # Number of times write queue was full causing retry
> system.physmem.totGap 47389786204500 # Total gap between requests
136c136
< system.physmem.readPktSize::6 1593145 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 1167882 # Read request sizes (log2)
143,169c143,169
< system.physmem.writePktSize::6 1333923 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 609512 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 408742 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 165543 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 158385 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 99064 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 61330 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 32974 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 30716 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 27120 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 7850 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 4295 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 2710 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 1710 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 1391 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 869 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 607 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 497 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 363 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 155 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 94 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 10 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::22 7 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::23 4 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::25 1 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1427135 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 517223 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 309889 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 86868 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 62308 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 44912 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 40171 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 37097 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 35200 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 31021 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 8620 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 4820 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 3062 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 2092 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 1731 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 1164 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 973 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 801 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 612 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 168 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 91 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
191,305c191,299
< system.physmem.wrQLenPdf::15 21385 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 25204 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 37704 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 44061 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 53566 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 60840 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 68935 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 76299 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 82207 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 85573 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 89148 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 94653 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 94373 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 98828 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 112387 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 98640 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 87955 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 82141 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 5308 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 2603 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 1767 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 1210 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 957 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 756 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 659 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 496 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 462 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 446 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 410 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 443 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 472 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 377 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 359 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 312 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 324 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 337 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 280 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 310 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 246 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 222 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 215 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 217 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 151 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 167 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 184 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 234 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 109 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 1039142 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 181.576816 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 111.689088 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 241.244363 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 644376 62.01% 62.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 193180 18.59% 80.60% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 61698 5.94% 86.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 33929 3.27% 89.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 24382 2.35% 92.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 13748 1.32% 93.47% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 13846 1.33% 94.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 7628 0.73% 95.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 46355 4.46% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1039142 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 75311 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 21.430349 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 250.668355 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-4095 75308 100.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::65536-69631 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 75311 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 75311 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.716270 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.189166 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 7.091364 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 70052 93.02% 93.02% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 3029 4.02% 97.04% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 423 0.56% 97.60% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 178 0.24% 97.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 138 0.18% 98.02% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 118 0.16% 98.18% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 205 0.27% 98.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 81 0.11% 98.56% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 292 0.39% 98.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 59 0.08% 99.02% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 23 0.03% 99.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 57 0.08% 99.13% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 240 0.32% 99.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 44 0.06% 99.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 27 0.04% 99.54% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 108 0.14% 99.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 169 0.22% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 3 0.00% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 2 0.00% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 3 0.00% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 3 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 1 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 2 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 14 0.02% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 2 0.00% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 4 0.01% 99.96% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 5 0.01% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::172-175 3 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-179 3 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::192-195 3 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 75311 # Writes before turning the bus around for reads
< system.physmem.totQLat 70116127057 # Total ticks spent queuing
< system.physmem.totMemAccLat 100377970807 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 8069825000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 43443.40 # Average queueing delay per DRAM burst
---
> system.physmem.wrQLenPdf::15 27129 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 32204 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 45048 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 50289 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 57286 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 61809 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 67754 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 74659 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 80821 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 85044 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 90854 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 96241 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 95504 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 100014 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 112663 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 99616 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 90045 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 84036 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 13635 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 10081 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 8296 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 6959 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 5731 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 4894 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 4062 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 3275 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 2801 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 2368 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 2057 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 1806 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 1553 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 1352 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 1254 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 1017 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 979 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 831 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 620 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 596 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 417 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 389 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 296 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 250 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 175 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 141 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 152 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 108 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 118 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 65 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 154 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 1166319 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 143.563495 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 97.562003 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 190.410734 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 788306 67.59% 67.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 223066 19.13% 86.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 56490 4.84% 91.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 24874 2.13% 93.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 21482 1.84% 95.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 12177 1.04% 96.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 8088 0.69% 97.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 4845 0.42% 97.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 26991 2.31% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1166319 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 68435 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 17.371564 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 68.388871 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-511 68432 100.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::512-1023 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 68435 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 68435 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 20.858289 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.984573 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 74.928718 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::0-127 68190 99.64% 99.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-255 151 0.22% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::256-383 21 0.03% 99.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::384-511 14 0.02% 99.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::512-639 8 0.01% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::640-767 2 0.00% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::768-895 5 0.01% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::896-1023 6 0.01% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::1024-1151 3 0.00% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::1152-1279 2 0.00% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::1280-1407 2 0.00% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::1536-1663 2 0.00% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::1664-1791 4 0.01% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::1792-1919 2 0.00% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::2304-2431 4 0.01% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::2432-2559 5 0.01% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::2560-2687 1 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::2688-2815 1 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::2816-2943 1 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::2944-3071 2 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::3072-3199 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::3584-3711 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::3712-3839 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::4096-4223 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::4224-4351 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::4864-4991 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::5504-5631 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::6656-6783 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::7680-7807 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 68435 # Writes before turning the bus around for reads
> system.physmem.totQLat 53856464568 # Total ticks spent queuing
> system.physmem.totMemAccLat 76147064568 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 5944160000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 45302.00 # Average queueing delay per DRAM burst
307,311c301,305
< system.physmem.avgMemAccLat 62193.40 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 2.18 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 1.80 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 1.80 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 64052.00 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1.61 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 1.93 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 1.58 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 1.93 # Average system write bandwidth in MiByte/s
314,334c308,328
< system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
< system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
< system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 25.55 # Average write queue length when enqueuing
< system.physmem.readRowHits 1298803 # Number of row buffer hits during reads
< system.physmem.writeRowHits 610248 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 45.74 # Row buffer hit rate for writes
< system.physmem.avgGap 16046845.57 # Average gap between requests
< system.physmem.pageHitRate 64.75 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 4027930200 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 2197779375 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 6326346000 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 4402421280 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 3092948511120 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 1180978829595 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 27376595514000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 31667477331570 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.735888 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 45543196260914 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1581262020000 # Time in different power states
---
> system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
> system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
> system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 23.02 # Average write queue length when enqueuing
> system.physmem.readRowHits 898304 # Number of row buffer hits during reads
> system.physmem.writeRowHits 551645 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 75.56 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 38.65 # Row buffer hit rate for writes
> system.physmem.avgGap 18094963.36 # Average gap between requests
> system.physmem.pageHitRate 55.42 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 4527963720 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 2470615125 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 4655063400 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 4696736400 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 3095270087520 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 1182204826065 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 27396846617250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 31690671909480 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.723752 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 45576929865903 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1582448920000 # Time in different power states
336c330
< system.physmem_0.memoryStateTime::ACT 229783905086 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 230401885347 # Time in different power states
338,348c332,342
< system.physmem_1.actEnergy 3827983320 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 2088681375 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 6262534200 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 4243389120 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 3092948511120 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 1177720349355 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 27379453830000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 31666545278490 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.716205 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 45547950580913 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1581262020000 # Time in different power states
---
> system.physmem_1.actEnergy 4289407920 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 2340450750 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 4617779400 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 4553055360 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 3095270087520 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 1179475938810 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 27399240378000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 31689787097760 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.705081 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 45580905738073 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1582448920000 # Time in different power states
350c344
< system.physmem_1.memoryStateTime::ACT 225030017087 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 226432462927 # Time in different power states
384,388c378,382
< system.cpu0.branchPred.lookups 149665852 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 99294558 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 7394871 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 104737280 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 69525721 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 148316317 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 98700135 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 7173487 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 104790534 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 69246034 # Number of BTB hits
390,392c384,386
< system.cpu0.branchPred.BTBHitPct 66.381064 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 20507496 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 218312 # Number of incorrect RAS predictions.
---
> system.cpu0.branchPred.BTBHitPct 66.080429 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 20257126 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 200970 # Number of incorrect RAS predictions.
423,439c417,432
< system.cpu0.dtb.walker.walks 634428 # Table walker walks requested
< system.cpu0.dtb.walker.walksLong 634428 # Table walker walks initiated with long descriptors
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 14162 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 100318 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walksSquashedBefore 297022 # Table walks squashed before starting
< system.cpu0.dtb.walker.walkWaitTime::samples 337406 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::mean 2383.727616 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::stdev 14932.270093 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0-65535 334700 99.20% 99.20% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::65536-131071 1380 0.41% 99.61% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::131072-196607 1061 0.31% 99.92% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::196608-262143 114 0.03% 99.96% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::262144-327679 46 0.01% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::327680-393215 68 0.02% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::393216-458751 21 0.01% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::458752-524287 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::524288-589823 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency
---
> system.cpu0.dtb.walker.walks 656451 # Table walker walks requested
> system.cpu0.dtb.walker.walksLong 656451 # Table walker walks initiated with long descriptors
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 15175 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 105539 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walksSquashedBefore 311743 # Table walks squashed before starting
> system.cpu0.dtb.walker.walkWaitTime::samples 344708 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::mean 2528.499484 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::stdev 15542.861274 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0-65535 341657 99.11% 99.11% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::65536-131071 1528 0.44% 99.56% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::131072-196607 1197 0.35% 99.91% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::196608-262143 153 0.04% 99.95% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::262144-327679 49 0.01% 99.96% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::327680-393215 98 0.03% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::393216-458751 19 0.01% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
442,452c435,445
< system.cpu0.dtb.walker.walkWaitTime::total 337406 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkCompletionTime::samples 331422 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::mean 21257.229454 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::gmean 17843.462773 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::stdev 23121.353715 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::0-65535 326855 98.62% 98.62% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1016 0.31% 98.93% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::131072-196607 2453 0.74% 99.67% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::196608-262143 165 0.05% 99.72% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::262144-327679 627 0.19% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::327680-393215 136 0.04% 99.95% # Table walker service (enqueue to completion) latency
---
> system.cpu0.dtb.walker.walkWaitTime::total 344708 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkCompletionTime::samples 348998 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::mean 21459.124408 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::gmean 17964.910208 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::stdev 23694.067201 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::0-65535 343876 98.53% 98.53% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1141 0.33% 98.86% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::131072-196607 2753 0.79% 99.65% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::196608-262143 227 0.07% 99.71% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::262144-327679 627 0.18% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::327680-393215 192 0.06% 99.95% # Table walker service (enqueue to completion) latency
454,475c447,475
< system.cpu0.dtb.walker.walkCompletionTime::458752-524287 36 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::524288-589823 24 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::total 331422 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walksPending::samples 582048251060 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::mean 0.606269 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::stdev 0.543146 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::0-1 580572178560 99.75% 99.75% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::2-3 833055500 0.14% 99.89% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::4-5 305294500 0.05% 99.94% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::6-7 135391000 0.02% 99.97% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::8-9 101845000 0.02% 99.98% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::10-11 57765000 0.01% 99.99% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::12-13 18306500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::14-15 23753000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::16-17 653000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::18-19 9000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::total 582048251060 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walkPageSizes::4K 100318 87.63% 87.63% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::2M 14162 12.37% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 114480 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 634428 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkCompletionTime::458752-524287 60 0.02% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::524288-589823 15 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::total 348998 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walksPending::samples 578933652396 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::mean 0.598699 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::stdev 0.548790 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::0-1 577357711896 99.73% 99.73% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::2-3 896498000 0.15% 99.88% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::4-5 316445000 0.05% 99.94% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::6-7 146967500 0.03% 99.96% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::8-9 111299500 0.02% 99.98% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::10-11 56334000 0.01% 99.99% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::12-13 19702000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::14-15 27806500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::16-17 847500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::18-19 17500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::20-21 1000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::22-23 1500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::24-25 1500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::26-27 2500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::28-29 1500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::30-31 15000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::total 578933652396 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walkPageSizes::4K 105540 87.43% 87.43% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::2M 15175 12.57% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 120715 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 656451 # Table walker requests started/completed, data/inst
477,478c477,478
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 634428 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 114480 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 656451 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 120715 # Table walker requests started/completed, data/inst
480,481c480,481
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 114480 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 748908 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 120715 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 777166 # Table walker requests started/completed, data/inst
484,488c484,488
< system.cpu0.dtb.read_hits 109416332 # DTB read hits
< system.cpu0.dtb.read_misses 460008 # DTB read misses
< system.cpu0.dtb.write_hits 89314742 # DTB write hits
< system.cpu0.dtb.write_misses 174420 # DTB write misses
< system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
---
> system.cpu0.dtb.read_hits 108931388 # DTB read hits
> system.cpu0.dtb.read_misses 471682 # DTB read misses
> system.cpu0.dtb.write_hits 89197418 # DTB write hits
> system.cpu0.dtb.write_misses 184769 # DTB write misses
> system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
490,494c490,494
< system.cpu0.dtb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
< system.cpu0.dtb.flush_entries 43796 # Number of entries that have been flushed from TLB
< system.cpu0.dtb.align_faults 708 # Number of TLB faults due to alignment restrictions
< system.cpu0.dtb.prefetch_faults 7923 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.flush_tlb_mva_asid 46180 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID
> system.cpu0.dtb.flush_entries 44365 # Number of entries that have been flushed from TLB
> system.cpu0.dtb.align_faults 621 # Number of TLB faults due to alignment restrictions
> system.cpu0.dtb.prefetch_faults 7762 # Number of TLB faults due to prefetch
496,498c496,498
< system.cpu0.dtb.perms_faults 42753 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 109876340 # DTB read accesses
< system.cpu0.dtb.write_accesses 89489162 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 42293 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 109403070 # DTB read accesses
> system.cpu0.dtb.write_accesses 89382187 # DTB write accesses
500,502c500,502
< system.cpu0.dtb.hits 198731074 # DTB hits
< system.cpu0.dtb.misses 634428 # DTB misses
< system.cpu0.dtb.accesses 199365502 # DTB accesses
---
> system.cpu0.dtb.hits 198128806 # DTB hits
> system.cpu0.dtb.misses 656451 # DTB misses
> system.cpu0.dtb.accesses 198785257 # DTB accesses
532,577c532,584
< system.cpu0.itb.walker.walks 91298 # Table walker walks requested
< system.cpu0.itb.walker.walksLong 91298 # Table walker walks initiated with long descriptors
< system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1125 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walksLongTerminationLevel::Level3 66671 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walksSquashedBefore 10542 # Table walks squashed before starting
< system.cpu0.itb.walker.walkWaitTime::samples 80756 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::mean 1599.144336 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::stdev 12482.430449 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::0-65535 80336 99.48% 99.48% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::65536-131071 92 0.11% 99.59% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::131072-196607 294 0.36% 99.96% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::196608-262143 14 0.02% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::262144-327679 11 0.01% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::327680-393215 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::total 80756 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkCompletionTime::samples 78338 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::mean 27568.581021 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::gmean 23319.178868 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::stdev 29698.501423 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::0-65535 76052 97.08% 97.08% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::65536-131071 130 0.17% 97.25% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::131072-196607 1833 2.34% 99.59% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::196608-262143 110 0.14% 99.73% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::262144-327679 108 0.14% 99.87% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::327680-393215 41 0.05% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::393216-458751 39 0.05% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::458752-524287 15 0.02% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::589824-655359 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::917504-983039 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::total 78338 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walksPending::samples 423131286608 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::mean 0.845297 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::stdev 0.361834 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::0 65489609660 15.48% 15.48% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::1 357613926448 84.52% 99.99% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::2 25558000 0.01% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::3 2033000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::4 159500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::total 423131286608 # Table walker pending requests distribution
< system.cpu0.itb.walker.walkPageSizes::4K 66671 98.34% 98.34% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::2M 1125 1.66% 100.00% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::total 67796 # Table walker page sizes translated
---
> system.cpu0.itb.walker.walks 90363 # Table walker walks requested
> system.cpu0.itb.walker.walksLong 90363 # Table walker walks initiated with long descriptors
> system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1091 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walksLongTerminationLevel::Level3 64708 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walksSquashedBefore 10655 # Table walks squashed before starting
> system.cpu0.itb.walker.walkWaitTime::samples 79708 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::mean 1706.014453 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::stdev 13195.811582 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::0-32767 78781 98.84% 98.84% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::32768-65535 448 0.56% 99.40% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::65536-98303 48 0.06% 99.46% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::98304-131071 68 0.09% 99.54% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::131072-163839 262 0.33% 99.87% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::163840-196607 71 0.09% 99.96% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::196608-229375 3 0.00% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::294912-327679 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::327680-360447 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::360448-393215 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::393216-425983 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::total 79708 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkCompletionTime::samples 76454 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::mean 28396.329819 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::gmean 23477.172430 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::stdev 32204.710724 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::0-65535 73773 96.49% 96.49% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::65536-131071 162 0.21% 96.71% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::131072-196607 2119 2.77% 99.48% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::196608-262143 153 0.20% 99.68% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::262144-327679 135 0.18% 99.85% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::327680-393215 40 0.05% 99.91% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::393216-458751 46 0.06% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::458752-524287 11 0.01% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::524288-589823 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::589824-655359 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::total 76454 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walksPending::samples 441465071924 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::mean 0.843066 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::stdev 0.363947 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::0 69311314608 15.70% 15.70% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::1 372126528316 84.29% 99.99% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::2 24340500 0.01% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::3 2776500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::4 112000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::total 441465071924 # Table walker pending requests distribution
> system.cpu0.itb.walker.walkPageSizes::4K 64708 98.34% 98.34% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::2M 1091 1.66% 100.00% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::total 65799 # Table walker page sizes translated
579,580c586,587
< system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 91298 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Requested::total 91298 # Table walker requests started/completed, data/inst
---
> system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 90363 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Requested::total 90363 # Table walker requests started/completed, data/inst
582,586c589,593
< system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 67796 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Completed::total 67796 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin::total 159094 # Table walker requests started/completed, data/inst
< system.cpu0.itb.inst_hits 236080263 # ITB inst hits
< system.cpu0.itb.inst_misses 91298 # ITB inst misses
---
> system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 65799 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Completed::total 65799 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin::total 156162 # Table walker requests started/completed, data/inst
> system.cpu0.itb.inst_hits 234328898 # ITB inst hits
> system.cpu0.itb.inst_misses 90363 # ITB inst misses
591c598
< system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
---
> system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
593,595c600,602
< system.cpu0.itb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
< system.cpu0.itb.flush_entries 31862 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_tlb_mva_asid 46180 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID
> system.cpu0.itb.flush_entries 32417 # Number of entries that have been flushed from TLB
599c606
< system.cpu0.itb.perms_faults 229508 # Number of TLB faults due to permissions restrictions
---
> system.cpu0.itb.perms_faults 232055 # Number of TLB faults due to permissions restrictions
602,606c609,613
< system.cpu0.itb.inst_accesses 236171561 # ITB inst accesses
< system.cpu0.itb.hits 236080263 # DTB hits
< system.cpu0.itb.misses 91298 # DTB misses
< system.cpu0.itb.accesses 236171561 # DTB accesses
< system.cpu0.numCycles 875332831 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 234419261 # ITB inst accesses
> system.cpu0.itb.hits 234328898 # DTB hits
> system.cpu0.itb.misses 90363 # DTB misses
> system.cpu0.itb.accesses 234419261 # DTB accesses
> system.cpu0.numCycles 866695747 # number of cpu cycles simulated
609,625c616,632
< system.cpu0.fetch.icacheStallCycles 98502478 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 662547160 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 149665852 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 90033217 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 725278481 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu0.fetch.SquashCycles 15926346 # Number of cycles fetch has spent squashing
< system.cpu0.fetch.TlbCycles 2210942 # Number of cycles fetch has spent waiting for tlb
< system.cpu0.fetch.MiscStallCycles 343253 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu0.fetch.PendingTrapStallCycles 6644206 # Number of stall cycles due to pending traps
< system.cpu0.fetch.PendingQuiesceStallCycles 843353 # Number of stall cycles due to pending quiesce instructions
< system.cpu0.fetch.IcacheWaitRetryStallCycles 921483 # Number of stall cycles due to full MSHR
< system.cpu0.fetch.CacheLines 235849038 # Number of cache lines fetched
< system.cpu0.fetch.IcacheSquashes 1874950 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.ItlbSquashes 30072 # Number of outstanding ITLB misses that were squashed
< system.cpu0.fetch.rateDist::samples 842707369 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 0.920891 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 1.205357 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.icacheStallCycles 96427999 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 657049317 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 148316317 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 89503160 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 718043211 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu0.fetch.SquashCycles 15454228 # Number of cycles fetch has spent squashing
> system.cpu0.fetch.TlbCycles 2249933 # Number of cycles fetch has spent waiting for tlb
> system.cpu0.fetch.MiscStallCycles 346517 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu0.fetch.PendingTrapStallCycles 6840136 # Number of stall cycles due to pending traps
> system.cpu0.fetch.PendingQuiesceStallCycles 871998 # Number of stall cycles due to pending quiesce instructions
> system.cpu0.fetch.IcacheWaitRetryStallCycles 916038 # Number of stall cycles due to full MSHR
> system.cpu0.fetch.CacheLines 234095625 # Number of cache lines fetched
> system.cpu0.fetch.IcacheSquashes 1822748 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.ItlbSquashes 30173 # Number of outstanding ITLB misses that were squashed
> system.cpu0.fetch.rateDist::samples 833422946 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 0.924189 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 1.205964 # Number of instructions fetched each cycle (Total)
627,630c634,637
< system.cpu0.fetch.rateDist::0 471086256 55.90% 55.90% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 144263495 17.12% 73.02% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 50294842 5.97% 78.99% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 177062776 21.01% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 464359111 55.72% 55.72% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 143558418 17.23% 72.94% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 49834021 5.98% 78.92% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 175671396 21.08% 100.00% # Number of instructions fetched each cycle (Total)
634,681c641,688
< system.cpu0.fetch.rateDist::total 842707369 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.170982 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 0.756909 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 117017992 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 431286061 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 248304840 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 40439583 # Number of cycles decode is unblocking
< system.cpu0.decode.SquashCycles 5658893 # Number of cycles decode is squashing
< system.cpu0.decode.BranchResolved 21552813 # Number of times decode resolved a branch
< system.cpu0.decode.BranchMispred 2348874 # Number of times decode detected a branch misprediction
< system.cpu0.decode.DecodedInsts 685973615 # Number of instructions handled by decode
< system.cpu0.decode.SquashedInsts 25548756 # Number of squashed instructions handled by decode
< system.cpu0.rename.SquashCycles 5658893 # Number of cycles rename is squashing
< system.cpu0.rename.IdleCycles 155339909 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 68898576 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 270709645 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 249775497 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 92324849 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 667175567 # Number of instructions processed by rename
< system.cpu0.rename.SquashedInsts 6553348 # Number of squashed instructions processed by rename
< system.cpu0.rename.ROBFullEvents 11928405 # Number of times rename has blocked due to ROB full
< system.cpu0.rename.IQFullEvents 414386 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LQFullEvents 932685 # Number of times rename has blocked due to LQ full
< system.cpu0.rename.SQFullEvents 54388046 # Number of times rename has blocked due to SQ full
< system.cpu0.rename.FullRegisterEvents 11955 # Number of times there has been no free registers
< system.cpu0.rename.RenamedOperands 637281036 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 1029527825 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 787757309 # Number of integer rename lookups
< system.cpu0.rename.fp_rename_lookups 900744 # Number of floating rename lookups
< system.cpu0.rename.CommittedMaps 574091859 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 63189171 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 16646916 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 14438257 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 81666616 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 109512073 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 93001551 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 9792967 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 8489048 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 643441375 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu0.iq.iqNonSpecInstsAdded 16650008 # Number of non-speculative instructions added to the IQ
< system.cpu0.iq.iqInstsIssued 647817648 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 2959555 # Number of squashed instructions issued
< system.cpu0.iq.iqSquashedInstsExamined 59258512 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 38730764 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu0.iq.iqSquashedNonSpecRemoved 299230 # Number of squashed non-spec instructions that were removed
< system.cpu0.iq.issued_per_cycle::samples 842707369 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 0.768734 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.052616 # Number of insts issued each cycle
---
> system.cpu0.fetch.rateDist::total 833422946 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.171128 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 0.758108 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 115740257 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 426691474 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 243999178 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 41506758 # Number of cycles decode is unblocking
> system.cpu0.decode.SquashCycles 5485279 # Number of cycles decode is squashing
> system.cpu0.decode.BranchResolved 21281954 # Number of times decode resolved a branch
> system.cpu0.decode.BranchMispred 2285386 # Number of times decode detected a branch misprediction
> system.cpu0.decode.DecodedInsts 681861872 # Number of instructions handled by decode
> system.cpu0.decode.SquashedInsts 24692274 # Number of squashed instructions handled by decode
> system.cpu0.rename.SquashCycles 5485279 # Number of cycles rename is squashing
> system.cpu0.rename.IdleCycles 154051427 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 67882232 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 271801592 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 246639237 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 87563179 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 663764828 # Number of instructions processed by rename
> system.cpu0.rename.SquashedInsts 6318012 # Number of squashed instructions processed by rename
> system.cpu0.rename.ROBFullEvents 12552479 # Number of times rename has blocked due to ROB full
> system.cpu0.rename.IQFullEvents 452890 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LQFullEvents 885924 # Number of times rename has blocked due to LQ full
> system.cpu0.rename.SQFullEvents 48607179 # Number of times rename has blocked due to SQ full
> system.cpu0.rename.FullRegisterEvents 12032 # Number of times there has been no free registers
> system.cpu0.rename.RenamedOperands 634283684 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 1028589268 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 784350114 # Number of integer rename lookups
> system.cpu0.rename.fp_rename_lookups 810310 # Number of floating rename lookups
> system.cpu0.rename.CommittedMaps 573100551 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 61183133 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 17365169 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 15184195 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 83196676 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 108756528 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 92814116 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 10086189 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 8556855 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 639440304 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu0.iq.iqNonSpecInstsAdded 17486234 # Number of non-speculative instructions added to the IQ
> system.cpu0.iq.iqInstsIssued 645371130 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 2878587 # Number of squashed instructions issued
> system.cpu0.iq.iqSquashedInstsExamined 57563182 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 37565263 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu0.iq.iqSquashedNonSpecRemoved 301808 # Number of squashed non-spec instructions that were removed
> system.cpu0.iq.issued_per_cycle::samples 833422946 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 0.774362 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.052683 # Number of insts issued each cycle
683,688c690,695
< system.cpu0.iq.issued_per_cycle::0 489695832 58.11% 58.11% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 146908165 17.43% 75.54% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 125837037 14.93% 90.48% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 71836004 8.52% 99.00% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 8424258 1.00% 100.00% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 6073 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 480257343 57.62% 57.62% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 149217372 17.90% 75.53% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 124187121 14.90% 90.43% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 71270973 8.55% 98.98% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 8484088 1.02% 100.00% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 6049 0.00% 100.00% # Number of insts issued each cycle
695c702
< system.cpu0.iq.issued_per_cycle::total 842707369 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 833422946 # Number of insts issued each cycle
697,727c704,734
< system.cpu0.iq.fu_full::IntAlu 67261039 45.56% 45.56% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 66196 0.04% 45.60% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 15732 0.01% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 29 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.62% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 38768633 26.26% 71.88% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 41521295 28.12% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 66055625 45.01% 45.01% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 69293 0.05% 45.06% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 22404 0.02% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 17 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.08% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 38927283 26.53% 71.60% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 41671380 28.40% 100.00% # attempts to use FU when none available
730,761c737,768
< system.cpu0.iq.FU_type_0::No_OpClass 14 0.00% 0.00% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntAlu 442579425 68.32% 68.32% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 1577066 0.24% 68.56% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntDiv 84316 0.01% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.57% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMisc 83107 0.01% 68.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.59% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemRead 112773884 17.41% 86.00% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 90719836 14.00% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntAlu 440798988 68.30% 68.30% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 1592862 0.25% 68.55% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntDiv 83426 0.01% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.56% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMisc 82619 0.01% 68.57% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.57% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.57% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.57% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemRead 112232372 17.39% 85.96% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 90580861 14.04% 100.00% # Type of FU issued
764,776c771,783
< system.cpu0.iq.FU_type_0::total 647817648 # Type of FU issued
< system.cpu0.iq.rate 0.740082 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 147632924 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.227893 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 2287461115 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 718905040 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 629078745 # Number of integer instruction queue wakeup accesses
< system.cpu0.iq.fp_inst_queue_reads 1474027 # Number of floating instruction queue reads
< system.cpu0.iq.fp_inst_queue_writes 598009 # Number of floating instruction queue writes
< system.cpu0.iq.fp_inst_queue_wakeup_accesses 548346 # Number of floating instruction queue wakeup accesses
< system.cpu0.iq.int_alu_accesses 794539840 # Number of integer alu accesses
< system.cpu0.iq.fp_alu_accesses 910718 # Number of floating point alu accesses
< system.cpu0.iew.lsq.thread0.forwLoads 2963176 # Number of loads that had data forwarded from stores
---
> system.cpu0.iq.FU_type_0::total 645371130 # Type of FU issued
> system.cpu0.iq.rate 0.744634 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 146746002 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.227382 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 2272436054 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 714094331 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 626839047 # Number of integer instruction queue wakeup accesses
> system.cpu0.iq.fp_inst_queue_reads 1353741 # Number of floating instruction queue reads
> system.cpu0.iq.fp_inst_queue_writes 552796 # Number of floating instruction queue writes
> system.cpu0.iq.fp_inst_queue_wakeup_accesses 503202 # Number of floating instruction queue wakeup accesses
> system.cpu0.iq.int_alu_accesses 791281833 # Number of integer alu accesses
> system.cpu0.iq.fp_alu_accesses 835299 # Number of floating point alu accesses
> system.cpu0.iew.lsq.thread0.forwLoads 3004923 # Number of loads that had data forwarded from stores
778,781c785,788
< system.cpu0.iew.lsq.thread0.squashedLoads 13511879 # Number of loads squashed
< system.cpu0.iew.lsq.thread0.ignoredResponses 17808 # Number of memory responses ignored because the instruction is squashed
< system.cpu0.iew.lsq.thread0.memOrderViolation 154801 # Number of memory ordering violations
< system.cpu0.iew.lsq.thread0.squashedStores 6318307 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 13275769 # Number of loads squashed
> system.cpu0.iew.lsq.thread0.ignoredResponses 18782 # Number of memory responses ignored because the instruction is squashed
> system.cpu0.iew.lsq.thread0.memOrderViolation 159110 # Number of memory ordering violations
> system.cpu0.iew.lsq.thread0.squashedStores 6200623 # Number of stores squashed
784,785c791,792
< system.cpu0.iew.lsq.thread0.rescheduledLoads 2892844 # Number of loads that were rescheduled
< system.cpu0.iew.lsq.thread0.cacheBlocked 5122180 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.rescheduledLoads 2963562 # Number of loads that were rescheduled
> system.cpu0.iew.lsq.thread0.cacheBlocked 5149852 # Number of times an access to memory failed due to the cache being blocked
787,790c794,797
< system.cpu0.iew.iewSquashCycles 5658893 # Number of cycles IEW is squashing
< system.cpu0.iew.iewBlockCycles 8725604 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 7188731 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 660220960 # Number of instructions dispatched to IQ
---
> system.cpu0.iew.iewSquashCycles 5485279 # Number of cycles IEW is squashing
> system.cpu0.iew.iewBlockCycles 8917054 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 3122413 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 657057128 # Number of instructions dispatched to IQ
792,803c799,810
< system.cpu0.iew.iewDispLoadInsts 109512073 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 93001551 # Number of dispatched store instructions
< system.cpu0.iew.iewDispNonSpecInsts 14147683 # Number of dispatched non-speculative instructions
< system.cpu0.iew.iewIQFullEvents 61387 # Number of times the IQ has become full, causing a stall
< system.cpu0.iew.iewLSQFullEvents 7052032 # Number of times the LSQ has become full, causing a stall
< system.cpu0.iew.memOrderViolationEvents 154801 # Number of memory order violations
< system.cpu0.iew.predictedTakenIncorrect 2237378 # Number of branches that were predicted taken incorrectly
< system.cpu0.iew.predictedNotTakenIncorrect 3184169 # Number of branches that were predicted not taken incorrectly
< system.cpu0.iew.branchMispredicts 5421547 # Number of branch mispredicts detected at execute
< system.cpu0.iew.iewExecutedInsts 639276531 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 109409199 # Number of load instructions executed
< system.cpu0.iew.iewExecSquashedInsts 7914356 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewDispLoadInsts 108756528 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 92814116 # Number of dispatched store instructions
> system.cpu0.iew.iewDispNonSpecInsts 14923426 # Number of dispatched non-speculative instructions
> system.cpu0.iew.iewIQFullEvents 69667 # Number of times the IQ has become full, causing a stall
> system.cpu0.iew.iewLSQFullEvents 2968943 # Number of times the LSQ has become full, causing a stall
> system.cpu0.iew.memOrderViolationEvents 159110 # Number of memory order violations
> system.cpu0.iew.predictedTakenIncorrect 2170447 # Number of branches that were predicted taken incorrectly
> system.cpu0.iew.predictedNotTakenIncorrect 3075539 # Number of branches that were predicted not taken incorrectly
> system.cpu0.iew.branchMispredicts 5245986 # Number of branch mispredicts detected at execute
> system.cpu0.iew.iewExecutedInsts 637077586 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 108926469 # Number of load instructions executed
> system.cpu0.iew.iewExecSquashedInsts 7646279 # Number of squashed instructions skipped in execute
805,821c812,828
< system.cpu0.iew.exec_nop 129577 # number of nop insts executed
< system.cpu0.iew.exec_refs 198721456 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 120519027 # Number of branches executed
< system.cpu0.iew.exec_stores 89312257 # Number of stores executed
< system.cpu0.iew.exec_rate 0.730324 # Inst execution rate
< system.cpu0.iew.wb_sent 630467148 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 629627091 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 306648182 # num instructions producing a value
< system.cpu0.iew.wb_consumers 503078288 # num instructions consuming a value
< system.cpu0.iew.wb_rate 0.719300 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.609544 # average fanout of values written-back
< system.cpu0.commit.commitSquashedInsts 51710398 # The number of squashed insts skipped by commit
< system.cpu0.commit.commitNonSpecStalls 16350778 # The number of times commit has been forced to stall to communicate backwards
< system.cpu0.commit.branchMispredicts 5090591 # The number of times a branch was mispredicted
< system.cpu0.commit.committed_per_cycle::samples 832883786 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 0.721389 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 1.530255 # Number of insts commited each cycle
---
> system.cpu0.iew.exec_nop 130590 # number of nop insts executed
> system.cpu0.iew.exec_refs 198124159 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 119913450 # Number of branches executed
> system.cpu0.iew.exec_stores 89197690 # Number of stores executed
> system.cpu0.iew.exec_rate 0.735065 # Inst execution rate
> system.cpu0.iew.wb_sent 628157908 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 627342249 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 305063287 # num instructions producing a value
> system.cpu0.iew.wb_consumers 500478465 # num instructions consuming a value
> system.cpu0.iew.wb_rate 0.723832 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.609543 # average fanout of values written-back
> system.cpu0.commit.commitSquashedInsts 50300993 # The number of squashed insts skipped by commit
> system.cpu0.commit.commitNonSpecStalls 17184426 # The number of times commit has been forced to stall to communicate backwards
> system.cpu0.commit.branchMispredicts 4931652 # The number of times a branch was mispredicted
> system.cpu0.commit.committed_per_cycle::samples 823863885 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 0.727503 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 1.534838 # Number of insts commited each cycle
823,831c830,838
< system.cpu0.commit.committed_per_cycle::0 570514920 68.50% 68.50% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 134700149 16.17% 84.67% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 59058098 7.09% 91.76% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 19776256 2.37% 94.14% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 14036208 1.69% 95.82% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 9662272 1.16% 96.98% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 6431324 0.77% 97.75% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 3992857 0.48% 98.23% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 14711702 1.77% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 560826617 68.07% 68.07% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 136759290 16.60% 84.67% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 58156007 7.06% 91.73% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 19570368 2.38% 94.11% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 13861730 1.68% 95.79% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 9557005 1.16% 96.95% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 6407217 0.78% 97.73% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 3899508 0.47% 98.20% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 14826143 1.80% 100.00% # Number of insts commited each cycle
835,837c842,844
< system.cpu0.commit.committed_per_cycle::total 832883786 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 511876907 # Number of instructions committed
< system.cpu0.commit.committedOps 600832864 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 823863885 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 510319417 # Number of instructions committed
> system.cpu0.commit.committedOps 599363355 # Number of ops (including micro ops) committed
839,845c846,852
< system.cpu0.commit.refs 182683437 # Number of memory references committed
< system.cpu0.commit.loads 96000193 # Number of loads committed
< system.cpu0.commit.membars 3986424 # Number of memory barriers committed
< system.cpu0.commit.branches 114418082 # Number of branches committed
< system.cpu0.commit.fp_insts 535391 # Number of committed floating point instructions.
< system.cpu0.commit.int_insts 551244640 # Number of committed integer instructions.
< system.cpu0.commit.function_calls 15252520 # Number of function calls committed.
---
> system.cpu0.commit.refs 182094252 # Number of memory references committed
> system.cpu0.commit.loads 95480759 # Number of loads committed
> system.cpu0.commit.membars 4094698 # Number of memory barriers committed
> system.cpu0.commit.branches 113994539 # Number of branches committed
> system.cpu0.commit.fp_insts 490256 # Number of committed floating point instructions.
> system.cpu0.commit.int_insts 549724602 # Number of committed integer instructions.
> system.cpu0.commit.function_calls 15118537 # Number of function calls committed.
847,877c854,884
< system.cpu0.commit.op_class_0::IntAlu 416691372 69.35% 69.35% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntMult 1318004 0.22% 69.57% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntDiv 66523 0.01% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.58% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMisc 73528 0.01% 69.59% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.59% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.59% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.59% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemRead 96000193 15.98% 85.57% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemWrite 86683244 14.43% 100.00% # Class of committed instruction
---
> system.cpu0.commit.op_class_0::IntAlu 415786848 69.37% 69.37% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntMult 1342849 0.22% 69.60% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntDiv 66347 0.01% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMisc 73059 0.01% 69.62% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemRead 95480759 15.93% 85.55% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemWrite 86613493 14.45% 100.00% # Class of committed instruction
880,905c887,912
< system.cpu0.commit.op_class_0::total 600832864 # Class of committed instruction
< system.cpu0.commit.bw_lim_events 14711702 # number cycles where commit BW limit reached
< system.cpu0.rob.rob_reads 1466105636 # The number of ROB reads
< system.cpu0.rob.rob_writes 1314872451 # The number of ROB writes
< system.cpu0.timesIdled 1097159 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu0.idleCycles 32625462 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.quiesceCycles 93833152963 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.committedInsts 511876907 # Number of Instructions Simulated
< system.cpu0.committedOps 600832864 # Number of Ops (including micro ops) Simulated
< system.cpu0.cpi 1.710046 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 1.710046 # CPI: Total CPI of All Threads
< system.cpu0.ipc 0.584780 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 0.584780 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 754446272 # number of integer regfile reads
< system.cpu0.int_regfile_writes 448604038 # number of integer regfile writes
< system.cpu0.fp_regfile_reads 881646 # number of floating regfile reads
< system.cpu0.fp_regfile_writes 476304 # number of floating regfile writes
< system.cpu0.cc_regfile_reads 139793568 # number of cc regfile reads
< system.cpu0.cc_regfile_writes 140496633 # number of cc regfile writes
< system.cpu0.misc_regfile_reads 1470350924 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 16456285 # number of misc regfile writes
< system.cpu0.dcache.tags.replacements 6559473 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 490.326221 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 169584910 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 6559985 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 25.851417 # Average number of references to valid blocks.
---
> system.cpu0.commit.op_class_0::total 599363355 # Class of committed instruction
> system.cpu0.commit.bw_lim_events 14826143 # number cycles where commit BW limit reached
> system.cpu0.rob.rob_reads 1454251951 # The number of ROB reads
> system.cpu0.rob.rob_writes 1308847090 # The number of ROB writes
> system.cpu0.timesIdled 1090671 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu0.idleCycles 33272801 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.quiesceCycles 93912870328 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.committedInsts 510319417 # Number of Instructions Simulated
> system.cpu0.committedOps 599363355 # Number of Ops (including micro ops) Simulated
> system.cpu0.cpi 1.698340 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 1.698340 # CPI: Total CPI of All Threads
> system.cpu0.ipc 0.588810 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 0.588810 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 752522588 # number of integer regfile reads
> system.cpu0.int_regfile_writes 446228364 # number of integer regfile writes
> system.cpu0.fp_regfile_reads 791452 # number of floating regfile reads
> system.cpu0.fp_regfile_writes 475504 # number of floating regfile writes
> system.cpu0.cc_regfile_reads 139593627 # number of cc regfile reads
> system.cpu0.cc_regfile_writes 140336082 # number of cc regfile writes
> system.cpu0.misc_regfile_reads 1450242581 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 17300190 # number of misc regfile writes
> system.cpu0.dcache.tags.replacements 6628748 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 507.898673 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 168544062 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 6629257 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 25.424276 # Average number of references to valid blocks.
907,1006c914,1013
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 490.326221 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.957668 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.957668 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 382 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 36 # Occupied blocks per task id
< system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
< system.cpu0.dcache.tags.tag_accesses 379087602 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 379087602 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 89088742 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 89088742 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 75269986 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 75269986 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 228422 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 228422 # number of SoftPFReq hits
< system.cpu0.dcache.WriteLineReq_hits::cpu0.data 263534 # number of WriteLineReq hits
< system.cpu0.dcache.WriteLineReq_hits::total 263534 # number of WriteLineReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1920078 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 1920078 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1972778 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 1972778 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 164358728 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 164358728 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 164587150 # number of overall hits
< system.cpu0.dcache.overall_hits::total 164587150 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 7258058 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 7258058 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 8107301 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 8107301 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 768102 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 768102 # number of SoftPFReq misses
< system.cpu0.dcache.WriteLineReq_misses::cpu0.data 855425 # number of WriteLineReq misses
< system.cpu0.dcache.WriteLineReq_misses::total 855425 # number of WriteLineReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 287297 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 287297 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 193519 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 193519 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 15365359 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 15365359 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 16133461 # number of overall misses
< system.cpu0.dcache.overall_misses::total 16133461 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 123043131500 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 123043131500 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 187154125822 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 187154125822 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 92776135134 # number of WriteLineReq miss cycles
< system.cpu0.dcache.WriteLineReq_miss_latency::total 92776135134 # number of WriteLineReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4545100500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 4545100500 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5540857500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 5540857500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 7820000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 7820000 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 310197257322 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 310197257322 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 310197257322 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 310197257322 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 96346800 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 96346800 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 83377287 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 83377287 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 996524 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 996524 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1118959 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::total 1118959 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2207375 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 2207375 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2166297 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 2166297 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 179724087 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 179724087 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 180720611 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 180720611 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075333 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.075333 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.097236 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.097236 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770781 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770781 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.764483 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::total 0.764483 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.130153 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.130153 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089332 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089332 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.085494 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.085494 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.089273 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.089273 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16952.624449 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 16952.624449 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23084.640107 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 23084.640107 # average WriteReq miss latency
< system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 108456.188601 # average WriteLineReq miss latency
< system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 108456.188601 # average WriteLineReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15820.215665 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15820.215665 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28632.111059 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28632.111059 # average StoreCondReq miss latency
---
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.898673 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.991990 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.991990 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 381 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id
> system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
> system.cpu0.dcache.tags.tag_accesses 377708512 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 377708512 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 88226592 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 88226592 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 75029005 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 75029005 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 221757 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 221757 # number of SoftPFReq hits
> system.cpu0.dcache.WriteLineReq_hits::cpu0.data 177850 # number of WriteLineReq hits
> system.cpu0.dcache.WriteLineReq_hits::total 177850 # number of WriteLineReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1970217 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 1970217 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2022489 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 2022489 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 163255597 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 163255597 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 163477354 # number of overall hits
> system.cpu0.dcache.overall_hits::total 163477354 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 7367994 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 7367994 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 8340746 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 8340746 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 804684 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 804684 # number of SoftPFReq misses
> system.cpu0.dcache.WriteLineReq_misses::cpu0.data 826218 # number of WriteLineReq misses
> system.cpu0.dcache.WriteLineReq_misses::total 826218 # number of WriteLineReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 297937 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 297937 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 206643 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 206643 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 15708740 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 15708740 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 16513424 # number of overall misses
> system.cpu0.dcache.overall_misses::total 16513424 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 129957875000 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 129957875000 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 197611984656 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 197611984656 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 55152577242 # number of WriteLineReq miss cycles
> system.cpu0.dcache.WriteLineReq_miss_latency::total 55152577242 # number of WriteLineReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4832056500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 4832056500 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5849414000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 5849414000 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5216000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5216000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 327569859656 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 327569859656 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 327569859656 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 327569859656 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 95594586 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 95594586 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 83369751 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 83369751 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1026441 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 1026441 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1004068 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::total 1004068 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2268154 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 2268154 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2229132 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 2229132 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 178964337 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 178964337 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 179990778 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 179990778 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.077075 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.077075 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.100045 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.100045 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.783955 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.783955 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.822871 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::total 0.822871 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.131357 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.131357 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.092701 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.092701 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.087776 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.087776 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.091746 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.091746 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17638.162436 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 17638.162436 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23692.363328 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 23692.363328 # average WriteReq miss latency
> system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 66753.056992 # average WriteLineReq miss latency
> system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 66753.056992 # average WriteLineReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16218.383417 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16218.383417 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28306.857721 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28306.857721 # average StoreCondReq miss latency
1009,1018c1016,1025
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20188.090452 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 20188.090452 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19226.950579 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 19226.950579 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 29213495 # number of cycles access was blocked
< system.cpu0.dcache.blocked_cycles::no_targets 28830141 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_mshrs 790800 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_targets 799061 # number of cycles access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 36.941698 # average number of cycles each access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_targets 36.080025 # average number of cycles each access was blocked
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20852.713818 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 20852.713818 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19836.580206 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 19836.580206 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 17065024 # number of cycles access was blocked
> system.cpu0.dcache.blocked_cycles::no_targets 30777617 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_mshrs 770223 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_targets 827793 # number of cycles access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 22.155952 # average number of cycles each access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_targets 37.180330 # average number of cycles each access was blocked
1021,1108c1028,1115
< system.cpu0.dcache.writebacks::writebacks 6559531 # number of writebacks
< system.cpu0.dcache.writebacks::total 6559531 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3685333 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 3685333 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6510101 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 6510101 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4620 # number of WriteLineReq MSHR hits
< system.cpu0.dcache.WriteLineReq_mshr_hits::total 4620 # number of WriteLineReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 146516 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 146516 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 10195434 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 10195434 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 10195434 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 10195434 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3572725 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 3572725 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1597200 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 1597200 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 761247 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 761247 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 850805 # number of WriteLineReq MSHR misses
< system.cpu0.dcache.WriteLineReq_mshr_misses::total 850805 # number of WriteLineReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 140781 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 140781 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 193511 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 193511 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 5169925 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 5169925 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 5931172 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 5931172 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32878 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32878 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32941 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32941 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65819 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65819 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 56556979500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 56556979500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 42701336905 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 42701336905 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18998780500 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18998780500 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 91672230134 # number of WriteLineReq MSHR miss cycles
< system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 91672230134 # number of WriteLineReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2014552000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2014552000 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5347454500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5347454500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 7712000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 7712000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99258316405 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 99258316405 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 118257096905 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 118257096905 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6293183000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6293183000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 6230446500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6230446500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12523629500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12523629500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037082 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037082 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019156 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019156 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.763902 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.763902 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.760354 # mshr miss rate for WriteLineReq accesses
< system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.760354 # mshr miss rate for WriteLineReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063778 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063778 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089328 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089328 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028766 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.028766 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032820 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.032820 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15830.207895 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15830.207895 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26735.122029 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26735.122029 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24957.445481 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24957.445481 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 107747.639158 # average WriteLineReq mshr miss latency
< system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 107747.639158 # average WriteLineReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14309.828741 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14309.828741 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27633.852856 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27633.852856 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 6628874 # number of writebacks
> system.cpu0.dcache.writebacks::total 6628874 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3770079 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 3770079 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6700876 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 6700876 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4178 # number of WriteLineReq MSHR hits
> system.cpu0.dcache.WriteLineReq_mshr_hits::total 4178 # number of WriteLineReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 152938 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 152938 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 10470955 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 10470955 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 10470955 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 10470955 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3597915 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 3597915 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1639870 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 1639870 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 797671 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 797671 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 822040 # number of WriteLineReq MSHR misses
> system.cpu0.dcache.WriteLineReq_mshr_misses::total 822040 # number of WriteLineReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 144999 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 144999 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 206643 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 206643 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 5237785 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 5237785 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 6035456 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 6035456 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 19715 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 19715 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 21606 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 21606 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 41321 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 41321 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 58751059000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 58751059000 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 44752175448 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 44752175448 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 21047920500 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 21047920500 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 54096896242 # number of WriteLineReq MSHR miss cycles
> system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 54096896242 # number of WriteLineReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2128355000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2128355000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5642835000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5642835000 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5152000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5152000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 103503234448 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 103503234448 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 124551154948 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 124551154948 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3829698500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3829698500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4085083000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4085083000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7914781500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7914781500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037637 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037637 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019670 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019670 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.777123 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.777123 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.818709 # mshr miss rate for WriteLineReq accesses
> system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.818709 # mshr miss rate for WriteLineReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063928 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063928 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092701 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092701 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029267 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.029267 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.033532 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.033532 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16329.195937 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16329.195937 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27290.075096 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27290.075096 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26386.718961 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26386.718961 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 65808.106956 # average WriteLineReq mshr miss latency
> system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 65808.106956 # average WriteLineReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14678.411575 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14678.411575 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27307.167434 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27307.167434 # average StoreCondReq mshr miss latency
1111,1120c1118,1127
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19199.179177 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19199.179177 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19938.234282 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19938.234282 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191410.152686 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191410.152686 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189139.567712 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189139.567712 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190273.773530 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190273.773530 # average overall mshr uncacheable latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19760.878778 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19760.878778 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20636.577410 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20636.577410 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194253.030687 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194253.030687 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189071.693048 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189071.693048 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 191543.803393 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191543.803393 # average overall mshr uncacheable latency
1122,1130c1129,1137
< system.cpu0.icache.tags.replacements 6707377 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.936942 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 228724396 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 6707889 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 34.097821 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 21622819000 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.936942 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999877 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.999877 # Average percentage of cache occupancy
---
> system.cpu0.icache.tags.replacements 6540239 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.944561 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 227144563 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 6540751 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 34.727597 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 18012149000 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.944561 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999892 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.999892 # Average percentage of cache occupancy
1132,1134c1139,1141
< system.cpu0.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id
1136,1179c1143,1186
< system.cpu0.icache.tags.tag_accesses 478348155 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 478348155 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 228724396 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 228724396 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 228724396 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 228724396 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 228724396 # number of overall hits
< system.cpu0.icache.overall_hits::total 228724396 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 7095721 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 7095721 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 7095721 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 7095721 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 7095721 # number of overall misses
< system.cpu0.icache.overall_misses::total 7095721 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 79714633751 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 79714633751 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 79714633751 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 79714633751 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 79714633751 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 79714633751 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 235820117 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 235820117 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 235820117 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 235820117 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 235820117 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 235820117 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.030090 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.030090 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.030090 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.030090 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.030090 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.030090 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11234.183778 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 11234.183778 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11234.183778 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 11234.183778 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11234.183778 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 11234.183778 # average overall miss latency
< system.cpu0.icache.blocked_cycles::no_mshrs 12261513 # number of cycles access was blocked
< system.cpu0.icache.blocked_cycles::no_targets 1787 # number of cycles access was blocked
< system.cpu0.icache.blocked::no_mshrs 839174 # number of cycles access was blocked
< system.cpu0.icache.blocked::no_targets 14 # number of cycles access was blocked
< system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.611407 # average number of cycles each access was blocked
< system.cpu0.icache.avg_blocked_cycles::no_targets 127.642857 # average number of cycles each access was blocked
---
> system.cpu0.icache.tags.tag_accesses 474674738 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 474674738 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 227144563 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 227144563 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 227144563 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 227144563 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 227144563 # number of overall hits
> system.cpu0.icache.overall_hits::total 227144563 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 6922414 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 6922414 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 6922414 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 6922414 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 6922414 # number of overall misses
> system.cpu0.icache.overall_misses::total 6922414 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 78815703700 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 78815703700 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 78815703700 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 78815703700 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 78815703700 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 78815703700 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 234066977 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 234066977 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 234066977 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 234066977 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 234066977 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 234066977 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029575 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.029575 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029575 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.029575 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029575 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.029575 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11385.580767 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 11385.580767 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11385.580767 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 11385.580767 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11385.580767 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 11385.580767 # average overall miss latency
> system.cpu0.icache.blocked_cycles::no_mshrs 12205805 # number of cycles access was blocked
> system.cpu0.icache.blocked_cycles::no_targets 1929 # number of cycles access was blocked
> system.cpu0.icache.blocked::no_mshrs 815036 # number of cycles access was blocked
> system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked
> system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.975786 # average number of cycles each access was blocked
> system.cpu0.icache.avg_blocked_cycles::no_targets 148.384615 # average number of cycles each access was blocked
1182,1195c1189,1202
< system.cpu0.icache.writebacks::writebacks 6707377 # number of writebacks
< system.cpu0.icache.writebacks::total 6707377 # number of writebacks
< system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 387800 # number of ReadReq MSHR hits
< system.cpu0.icache.ReadReq_mshr_hits::total 387800 # number of ReadReq MSHR hits
< system.cpu0.icache.demand_mshr_hits::cpu0.inst 387800 # number of demand (read+write) MSHR hits
< system.cpu0.icache.demand_mshr_hits::total 387800 # number of demand (read+write) MSHR hits
< system.cpu0.icache.overall_mshr_hits::cpu0.inst 387800 # number of overall MSHR hits
< system.cpu0.icache.overall_mshr_hits::total 387800 # number of overall MSHR hits
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6707921 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 6707921 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 6707921 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 6707921 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 6707921 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 6707921 # number of overall MSHR misses
---
> system.cpu0.icache.writebacks::writebacks 6540239 # number of writebacks
> system.cpu0.icache.writebacks::total 6540239 # number of writebacks
> system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 381630 # number of ReadReq MSHR hits
> system.cpu0.icache.ReadReq_mshr_hits::total 381630 # number of ReadReq MSHR hits
> system.cpu0.icache.demand_mshr_hits::cpu0.inst 381630 # number of demand (read+write) MSHR hits
> system.cpu0.icache.demand_mshr_hits::total 381630 # number of demand (read+write) MSHR hits
> system.cpu0.icache.overall_mshr_hits::cpu0.inst 381630 # number of overall MSHR hits
> system.cpu0.icache.overall_mshr_hits::total 381630 # number of overall MSHR hits
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6540784 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 6540784 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 6540784 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 6540784 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 6540784 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 6540784 # number of overall MSHR misses
1200,1205c1207,1212
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 71756007072 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 71756007072 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 71756007072 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 71756007072 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 71756007072 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 71756007072 # number of overall MSHR miss cycles
---
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 70913768580 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 70913768580 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 70913768580 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 70913768580 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 70913768580 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 70913768580 # number of overall MSHR miss cycles
1210,1221c1217,1228
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028445 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028445 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028445 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.028445 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028445 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.028445 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10697.205151 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10697.205151 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10697.205151 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 10697.205151 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10697.205151 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 10697.205151 # average overall mshr miss latency
---
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027944 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027944 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027944 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.027944 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027944 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.027944 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10841.784193 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10841.784193 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10841.784193 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 10841.784193 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10841.784193 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 10841.784193 # average overall mshr miss latency
1227,1229c1234,1236
< system.cpu0.l2cache.prefetcher.num_hwpf_issued 8921966 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.pfIdentified 8932201 # number of prefetch candidates identified
< system.cpu0.l2cache.prefetcher.pfBufferHit 9178 # number of redundant prefetches already in prefetch queue
---
> system.cpu0.l2cache.prefetcher.num_hwpf_issued 9036202 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.pfIdentified 9047325 # number of prefetch candidates identified
> system.cpu0.l2cache.prefetcher.pfBufferHit 9983 # number of redundant prefetches already in prefetch queue
1232,1246c1239,1253
< system.cpu0.l2cache.prefetcher.pfSpanPage 1125087 # number of prefetches not generated due to page crossing
< system.cpu0.l2cache.tags.replacements 2909208 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16158.656650 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 19404404 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 2925253 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 6.633411 # Average number of references to valid blocks.
< system.cpu0.l2cache.tags.warmup_cycle 3536776000 # Cycle when the warmup percentage was hit.
< system.cpu0.l2cache.tags.occ_blocks::writebacks 15221.688116 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.041534 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 63.344722 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000040 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 812.582238 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.929058 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003726 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003866 # Average percentage of cache occupancy
---
> system.cpu0.l2cache.prefetcher.pfSpanPage 1166339 # number of prefetches not generated due to page crossing
> system.cpu0.l2cache.tags.replacements 3033682 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16193.393040 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 19026764 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 3049439 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 6.239431 # Average number of references to valid blocks.
> system.cpu0.l2cache.tags.warmup_cycle 3423113000 # Cycle when the warmup percentage was hit.
> system.cpu0.l2cache.tags.occ_blocks::writebacks 15201.196894 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 62.932138 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 78.683801 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000068 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 850.580138 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.927807 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003841 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004802 # Average percentage of cache occupancy
1248,1257c1255,1263
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.049596 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.986246 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1170 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 75 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14800 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 10 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 38 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 178 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 606 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 338 # Occupied blocks per task id
---
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.051915 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.988366 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1326 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 91 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14340 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 70 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 174 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 642 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 440 # Occupied blocks per task id
1259,1280c1265,1286
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1308 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5860 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4512 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3004 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.071411 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004578 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.903320 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 454144773 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 454144773 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 651189 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 209837 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 861026 # number of ReadReq hits
< system.cpu0.l2cache.WritebackDirty_hits::writebacks 4295929 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackDirty_hits::total 4295929 # number of WritebackDirty hits
< system.cpu0.l2cache.WritebackClean_hits::writebacks 8968573 # number of WritebackClean hits
< system.cpu0.l2cache.WritebackClean_hits::total 8968573 # number of WritebackClean hits
< system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 805 # number of UpgradeReq hits
< system.cpu0.l2cache.UpgradeReq_hits::total 805 # number of UpgradeReq hits
---
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 70 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 900 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4799 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4876 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3646 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.080933 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005554 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.875244 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 451755433 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 451755433 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 669148 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 205466 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 874614 # number of ReadReq hits
> system.cpu0.l2cache.WritebackDirty_hits::writebacks 4337694 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackDirty_hits::total 4337694 # number of WritebackDirty hits
> system.cpu0.l2cache.WritebackClean_hits::writebacks 8829361 # number of WritebackClean hits
> system.cpu0.l2cache.WritebackClean_hits::total 8829361 # number of WritebackClean hits
> system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1023 # number of UpgradeReq hits
> system.cpu0.l2cache.UpgradeReq_hits::total 1023 # number of UpgradeReq hits
1283,1305c1289,1311
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 980855 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 980855 # number of ReadExReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 6087853 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::total 6087853 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3397389 # number of ReadSharedReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::total 3397389 # number of ReadSharedReq hits
< system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 211269 # number of InvalidateReq hits
< system.cpu0.l2cache.InvalidateReq_hits::total 211269 # number of InvalidateReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 651189 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 209837 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 6087853 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 4378244 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 11327123 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 651189 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 209837 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 6087853 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 4378244 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 11327123 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13609 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10441 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 24050 # number of ReadReq misses
< system.cpu0.l2cache.WritebackDirty_misses::writebacks 4 # number of WritebackDirty misses
< system.cpu0.l2cache.WritebackDirty_misses::total 4 # number of WritebackDirty misses
---
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 1003467 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 1003467 # number of ReadExReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5907946 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::total 5907946 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3394515 # number of ReadSharedReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::total 3394515 # number of ReadSharedReq hits
> system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 175024 # number of InvalidateReq hits
> system.cpu0.l2cache.InvalidateReq_hits::total 175024 # number of InvalidateReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 669148 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 205466 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 5907946 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 4397982 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 11180542 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 669148 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 205466 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 5907946 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 4397982 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 11180542 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 14498 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10801 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 25299 # number of ReadReq misses
> system.cpu0.l2cache.WritebackDirty_misses::writebacks 6 # number of WritebackDirty misses
> system.cpu0.l2cache.WritebackDirty_misses::total 6 # number of WritebackDirty misses
1308,1392c1314,1398
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 266523 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 266523 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 193497 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 193497 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 13 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::total 13 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 359046 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 359046 # number of ReadExReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 620051 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::total 620051 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1074980 # number of ReadSharedReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::total 1074980 # number of ReadSharedReq misses
< system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 637513 # number of InvalidateReq misses
< system.cpu0.l2cache.InvalidateReq_misses::total 637513 # number of InvalidateReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13609 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10441 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 620051 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 1434026 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 2078127 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 13609 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10441 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 620051 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 1434026 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 2078127 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 731180000 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 642927000 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 1374107000 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3539737000 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 3539737000 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2018375000 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2018375000 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 7547996 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 7547996 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 23661492999 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 23661492999 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 24792926998 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::total 24792926998 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 48196505484 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::total 48196505484 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 87950874488 # number of InvalidateReq miss cycles
< system.cpu0.l2cache.InvalidateReq_miss_latency::total 87950874488 # number of InvalidateReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 731180000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 642927000 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 24792926998 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 71857998483 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 98025032481 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 731180000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 642927000 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 24792926998 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 71857998483 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 98025032481 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 664798 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 220278 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 885076 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4295933 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackDirty_accesses::total 4295933 # number of WritebackDirty accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::writebacks 8968575 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.WritebackClean_accesses::total 8968575 # number of WritebackClean accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 267328 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 267328 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 193498 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 193498 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 13 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 13 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1339901 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 1339901 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6707904 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::total 6707904 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4472369 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::total 4472369 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 848782 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::total 848782 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 664798 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 220278 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 6707904 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 5812270 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 13405250 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 664798 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 220278 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 6707904 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 5812270 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 13405250 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020471 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.047399 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.027173 # miss rate for ReadReq accesses
---
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 283162 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 283162 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 206636 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 206636 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 363386 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 363386 # number of ReadExReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 632821 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::total 632821 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1142961 # number of ReadSharedReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::total 1142961 # number of ReadSharedReq misses
> system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 644935 # number of InvalidateReq misses
> system.cpu0.l2cache.InvalidateReq_misses::total 644935 # number of InvalidateReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 14498 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10801 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 632821 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 1506347 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 2164467 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 14498 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10801 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 632821 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 1506347 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 2164467 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 831200000 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 735223500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 1566423500 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3616020000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 3616020000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2092116500 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2092116500 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 5056000 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 5056000 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 25090830000 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 25090830000 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 25302734498 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::total 25302734498 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 52461352979 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::total 52461352979 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 386032000 # number of InvalidateReq miss cycles
> system.cpu0.l2cache.InvalidateReq_miss_latency::total 386032000 # number of InvalidateReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 831200000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 735223500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 25302734498 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 77552182979 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 104421340977 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 831200000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 735223500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 25302734498 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 77552182979 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 104421340977 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 683646 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 216267 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 899913 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4337700 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackDirty_accesses::total 4337700 # number of WritebackDirty accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::writebacks 8829363 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.WritebackClean_accesses::total 8829363 # number of WritebackClean accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 284185 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 284185 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 206637 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 206637 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 6 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1366853 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 1366853 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6540767 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::total 6540767 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4537476 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::total 4537476 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 819959 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::total 819959 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 683646 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 216267 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 6540767 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 5904329 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 13345009 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 683646 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 216267 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 6540767 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 5904329 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 13345009 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021207 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.049943 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.028113 # miss rate for ReadReq accesses
1397,1398c1403,1404
< system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.996989 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.996989 # miss rate for UpgradeReq accesses
---
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.996400 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.996400 # miss rate for UpgradeReq accesses
1403,1448c1409,1454
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.267965 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.267965 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.092436 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.092436 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.240360 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.240360 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.751092 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.751092 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020471 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.047399 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.092436 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.246724 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.155023 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020471 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.047399 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.092436 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.246724 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.155023 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 53727.680212 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 61577.147783 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 57135.426195 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13281.168980 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13281.168980 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10431.040275 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10431.040275 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 580615.076923 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 580615.076923 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 65901.007111 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 65901.007111 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39985.302819 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39985.302819 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 44834.792725 # average ReadSharedReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 44834.792725 # average ReadSharedReq miss latency
< system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 137959.342771 # average InvalidateReq miss latency
< system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 137959.342771 # average InvalidateReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 53727.680212 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 61577.147783 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39985.302819 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 50109.271717 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 47169.895045 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 53727.680212 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 61577.147783 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39985.302819 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 50109.271717 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 47169.895045 # average overall miss latency
< system.cpu0.l2cache.blocked_cycles::no_mshrs 3672 # number of cycles access was blocked
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.265856 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.265856 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.096750 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.096750 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.251894 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.251894 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.786545 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.786545 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021207 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.049943 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.096750 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.255126 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.162193 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021207 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.049943 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.096750 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.255126 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.162193 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 57332.045799 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 68069.947227 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 61916.419621 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 12770.145712 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 12770.145712 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10124.646722 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10124.646722 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 842666.666667 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 842666.666667 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 69047.321581 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 69047.321581 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39984.031026 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39984.031026 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 45899.512738 # average ReadSharedReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 45899.512738 # average ReadSharedReq miss latency
> system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 598.559545 # average InvalidateReq miss latency
> system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 598.559545 # average InvalidateReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 57332.045799 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 68069.947227 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39984.031026 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 51483.611000 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 48243.443294 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 57332.045799 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 68069.947227 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39984.031026 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 51483.611000 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 48243.443294 # average overall miss latency
> system.cpu0.l2cache.blocked_cycles::no_mshrs 2497 # number of cycles access was blocked
1450c1456
< system.cpu0.l2cache.blocked::no_mshrs 25 # number of cycles access was blocked
---
> system.cpu0.l2cache.blocked::no_mshrs 23 # number of cycles access was blocked
1452c1458
< system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 146.880000 # average number of cycles each access was blocked
---
> system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 108.565217 # average number of cycles each access was blocked
1456,1457c1462,1463
< system.cpu0.l2cache.writebacks::writebacks 1813424 # number of writebacks
< system.cpu0.l2cache.writebacks::total 1813424 # number of writebacks
---
> system.cpu0.l2cache.writebacks::writebacks 1894575 # number of writebacks
> system.cpu0.l2cache.writebacks::total 1894575 # number of writebacks
1459,1468c1465,1474
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 178 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_hits::total 183 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 69322 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 69322 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 4 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 7219 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 7219 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 5 # number of InvalidateReq MSHR hits
< system.cpu0.l2cache.InvalidateReq_mshr_hits::total 5 # number of InvalidateReq MSHR hits
---
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 193 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::total 198 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 69860 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 69860 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 6 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 7488 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 7488 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 6 # number of InvalidateReq MSHR hits
> system.cpu0.l2cache.InvalidateReq_mshr_hits::total 6 # number of InvalidateReq MSHR hits
1470,1473c1476,1479
< system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 178 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 76541 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 76728 # number of demand (read+write) MSHR hits
---
> system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 193 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 77348 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 77552 # number of demand (read+write) MSHR hits
1475,1483c1481,1489
< system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 178 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 76541 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 76728 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 13604 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10263 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 23867 # number of ReadReq MSHR misses
< system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 4 # number of WritebackDirty MSHR misses
< system.cpu0.l2cache.WritebackDirty_mshr_misses::total 4 # number of WritebackDirty MSHR misses
---
> system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 193 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 77348 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 77552 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 14493 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10608 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 25101 # number of ReadReq MSHR misses
> system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 6 # number of WritebackDirty MSHR misses
> system.cpu0.l2cache.WritebackDirty_mshr_misses::total 6 # number of WritebackDirty MSHR misses
1486,1512c1492,1518
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 927565 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 927565 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 266523 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 266523 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 193497 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 193497 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 13 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 13 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 289724 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 289724 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 620047 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 620047 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1067761 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1067761 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 637508 # number of InvalidateReq MSHR misses
< system.cpu0.l2cache.InvalidateReq_mshr_misses::total 637508 # number of InvalidateReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 13604 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10263 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 620047 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1357485 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 2001399 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 13604 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10263 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 620047 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1357485 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 927565 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 2928964 # number of overall MSHR misses
---
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 934637 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 934637 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 283162 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 283162 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 206636 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 206636 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 293526 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 293526 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 632815 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 632815 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1135473 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1135473 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 644929 # number of InvalidateReq MSHR misses
> system.cpu0.l2cache.InvalidateReq_mshr_misses::total 644929 # number of InvalidateReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 14493 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10608 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 632815 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1428999 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 2086915 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 14493 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10608 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 632815 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1428999 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 934637 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 3021552 # number of overall MSHR misses
1514,1517c1520,1523
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32878 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 54171 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32941 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32941 # number of WriteReq MSHR uncacheable
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 19715 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 41008 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 21606 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 21606 # number of WriteReq MSHR uncacheable
1519,1550c1525,1556
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 65819 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 87112 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 649200000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 572348000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1221548000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 68343452519 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 68343452519 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7943943496 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7943943496 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3893295994 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3893295994 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 6899996 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6899996 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 17756340999 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 17756340999 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 21072592498 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 21072592498 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 41283242484 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 41283242484 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 84125646988 # number of InvalidateReq MSHR miss cycles
< system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 84125646988 # number of InvalidateReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 649200000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 572348000 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 21072592498 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 59039583483 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 81333723981 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 649200000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 572348000 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 21072592498 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 59039583483 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 68343452519 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 149677176500 # number of overall MSHR miss cycles
---
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 41321 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 62614 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 744149500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 659971500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1404121000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 78126139116 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 78126139116 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 8227819495 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 8227819495 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 4089973495 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 4089973495 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4672000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4672000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 18739186500 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 18739186500 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 21505748998 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 21505748998 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 45049566980 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 45049566980 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 46970391994 # number of InvalidateReq MSHR miss cycles
> system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 46970391994 # number of InvalidateReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 744149500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 659971500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 21505748998 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 63788753480 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 86698623478 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 744149500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 659971500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 21505748998 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 63788753480 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 78126139116 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 164824762594 # number of overall MSHR miss cycles
1552,1555c1558,1561
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6029953000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8810035500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5977560967 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5977560967 # number of WriteReq MSHR uncacheable cycles
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3671826500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6451909000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3917316467 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3917316467 # number of WriteReq MSHR uncacheable cycles
1557,1561c1563,1567
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 12007513967 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14787596467 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020463 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.046591 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.026966 # mshr miss rate for ReadReq accesses
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7589142967 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10369225467 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021200 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049050 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027893 # mshr miss rate for ReadReq accesses
1568,1569c1574,1575
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.996989 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.996989 # mshr miss rate for UpgradeReq accesses
---
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.996400 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.996400 # mshr miss rate for UpgradeReq accesses
1574,1590c1580,1596
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.216228 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.216228 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092435 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092435 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.238746 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.238746 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.751086 # mshr miss rate for InvalidateReq accesses
< system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.751086 # mshr miss rate for InvalidateReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.020463 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046591 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092435 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.233555 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.149300 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.020463 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046591 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092435 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.233555 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.214746 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.214746 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.096749 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096749 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.250243 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250243 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.786538 # mshr miss rate for InvalidateReq accesses
> system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.786538 # mshr miss rate for InvalidateReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021200 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049050 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.096749 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242026 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.156382 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021200 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049050 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.096749 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242026 # mshr miss rate for overall accesses
1592,1622c1598,1628
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.218494 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 47721.258453 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 55768.098996 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 51181.463946 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 73680.499500 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 73680.499500 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29805.846010 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29805.846010 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20120.704683 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20120.704683 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 530768.923077 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 530768.923077 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 61287.090469 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 61287.090469 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33985.476098 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33985.476098 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38663.373624 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38663.373624 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 131960.143226 # average InvalidateReq mshr miss latency
< system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 131960.143226 # average InvalidateReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 47721.258453 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 55768.098996 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33985.476098 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43491.886454 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40638.435405 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 47721.258453 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 55768.098996 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33985.476098 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43491.886454 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 73680.499500 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 51102.429562 # average overall mshr miss latency
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226418 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 51345.442627 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62214.507919 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 55938.847058 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83589.820557 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83589.820557 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29056.933822 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29056.933822 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19793.131376 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19793.131376 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 778666.666667 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 778666.666667 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 63841.657979 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 63841.657979 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33984.259220 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33984.259220 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39674.714397 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39674.714397 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 72830.330151 # average InvalidateReq mshr miss latency
> system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 72830.330151 # average InvalidateReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 51345.442627 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 62214.507919 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33984.259220 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 44638.767053 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 41543.916967 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 51345.442627 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 62214.507919 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33984.259220 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 44638.767053 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83589.820557 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 54549.702469 # average overall mshr miss latency
1624,1627c1630,1633
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183403.887098 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162633.798527 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181462.644334 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181462.644334 # average WriteReq mshr uncacheable latency
---
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186245.320822 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 157332.935037 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181306.880820 # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181306.880820 # average WriteReq mshr uncacheable latency
1629,1630c1635,1636
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 182432.336666 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 169753.839505 # average overall mshr uncacheable latency
---
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183663.100288 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 165605.542962 # average overall mshr uncacheable latency
1632,1671c1638,1678
< system.cpu0.toL2Bus.snoop_filter.tot_requests 27467007 # Total number of requests made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_requests 14098216 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2397 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.snoop_filter.tot_snoops 2174971 # Total number of snoops made to the snoop filter.
< system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2174417 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 554 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu0.toL2Bus.trans_dist::ReadReq 1027741 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 12311555 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 32941 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 32941 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackDirty 6114023 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WritebackClean 8970970 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::CleanEvict 2853143 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 1178619 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFResp 8 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 489036 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 343853 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 531725 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 106 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 201 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 1422561 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 1350501 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6707921 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5424362 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateReq 856015 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateResp 848782 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20165788 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21120167 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 459340 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1399304 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 43144599 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 858918672 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 799305801 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1762224 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5318384 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 1665305081 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 7537626 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 22154436 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 0.115021 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.319126 # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_filter.tot_requests 27325930 # Total number of requests made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_requests 14061042 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2043 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.snoop_filter.tot_snoops 2238708 # Total number of snoops made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2238208 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 500 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.trans_dist::ReadReq 1035490 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 12208665 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 21607 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 21606 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackDirty 6237038 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WritebackClean 8831409 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::CleanEvict 2977562 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 1194066 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 497340 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 368088 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 556890 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 118 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 1397051 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 1373685 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6540784 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5522441 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateReq 877204 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateResp 819959 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19664376 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21309678 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 452328 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1442065 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 42868447 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 837525072 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 808748037 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1730136 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5469168 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 1653472413 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 7780555 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 22331081 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 0.118319 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.323054 # Request fanout histogram
1673,1675c1680,1682
< system.cpu0.toL2Bus.snoop_fanout::0 19606761 88.50% 88.50% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::1 2547121 11.50% 100.00% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::2 554 0.00% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::0 19689398 88.17% 88.17% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::1 2641183 11.83% 100.00% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 500 0.00% 100.00% # Request fanout histogram
1679,1680c1686,1687
< system.cpu0.toL2Bus.snoop_fanout::total 22154436 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 27362140922 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 22331081 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 27171038408 # Layer occupancy (ticks)
1682c1689
< system.cpu0.toL2Bus.snoopLayer0.occupancy 207113536 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 185981894 # Layer occupancy (ticks)
1684c1691
< system.cpu0.toL2Bus.respLayer0.occupancy 10089828109 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 9839167037 # Layer occupancy (ticks)
1686c1693
< system.cpu0.toL2Bus.respLayer1.occupancy 9431575123 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 9551310776 # Layer occupancy (ticks)
1688c1695
< system.cpu0.toL2Bus.respLayer2.occupancy 239573965 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 236496624 # Layer occupancy (ticks)
1690c1697
< system.cpu0.toL2Bus.respLayer3.occupancy 735155181 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 759104112 # Layer occupancy (ticks)
1692,1696c1699,1703
< system.cpu1.branchPred.lookups 119891525 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 80198528 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 5904198 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 84182887 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 54925615 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 126248667 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 84543955 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 6151855 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 88859655 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 57842551 # Number of BTB hits
1698,1700c1705,1707
< system.cpu1.branchPred.BTBHitPct 65.245583 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 16054982 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 157154 # Number of incorrect RAS predictions.
---
> system.cpu1.branchPred.BTBHitPct 65.094278 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 16827370 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 172583 # Number of incorrect RAS predictions.
1730,1783c1737,1786
< system.cpu1.dtb.walker.walks 523591 # Table walker walks requested
< system.cpu1.dtb.walker.walksLong 523591 # Table walker walks initiated with long descriptors
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9887 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 82113 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walksSquashedBefore 242894 # Table walks squashed before starting
< system.cpu1.dtb.walker.walkWaitTime::samples 280697 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::mean 2503.193835 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::stdev 14937.525211 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0-65535 278494 99.22% 99.22% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::65536-131071 1255 0.45% 99.66% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::131072-196607 659 0.23% 99.90% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::196608-262143 166 0.06% 99.96% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::262144-327679 38 0.01% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::327680-393215 57 0.02% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::393216-458751 13 0.00% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::524288-589823 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::589824-655359 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::total 280697 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkCompletionTime::samples 263545 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::mean 19785.484452 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::gmean 17259.480271 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::stdev 16001.974136 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::0-65535 261738 99.31% 99.31% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::65536-131071 658 0.25% 99.56% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::131072-196607 820 0.31% 99.88% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::196608-262143 79 0.03% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::262144-327679 151 0.06% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::327680-393215 47 0.02% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::393216-458751 31 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::total 263545 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walksPending::samples 427419381904 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::mean 0.550644 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::stdev 0.560610 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::0-1 426298998404 99.74% 99.74% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::2-3 579725500 0.14% 99.87% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::4-5 235009500 0.05% 99.93% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::6-7 123480000 0.03% 99.96% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::8-9 88192000 0.02% 99.98% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::10-11 51481500 0.01% 99.99% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::12-13 16753000 0.00% 99.99% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::14-15 25205500 0.01% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::16-17 518000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::18-19 18500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::total 427419381904 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walkPageSizes::4K 82114 89.25% 89.25% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::2M 9887 10.75% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 92001 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 523591 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walks 548057 # Table walker walks requested
> system.cpu1.dtb.walker.walksLong 548057 # Table walker walks initiated with long descriptors
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11885 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 88263 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walksSquashedBefore 254796 # Table walks squashed before starting
> system.cpu1.dtb.walker.walkWaitTime::samples 293261 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::mean 2461.776370 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::stdev 15099.601662 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0-131071 292248 99.65% 99.65% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::131072-262143 874 0.30% 99.95% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::262144-393215 111 0.04% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::393216-524287 22 0.01% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::524288-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::655360-786431 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::917504-1.04858e+06 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::1.04858e+06-1.17965e+06 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::total 293261 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkCompletionTime::samples 284367 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::mean 20156.804411 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::gmean 17511.621467 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::stdev 17128.200610 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::0-65535 282098 99.20% 99.20% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::65536-131071 636 0.22% 99.43% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1232 0.43% 99.86% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::196608-262143 88 0.03% 99.89% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::262144-327679 184 0.06% 99.95% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::327680-393215 74 0.03% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::393216-458751 33 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::458752-524287 13 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::total 284367 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walksPending::samples 458679401608 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::mean 0.570209 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::stdev 0.555852 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::0-1 457501852108 99.74% 99.74% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::2-3 610883500 0.13% 99.88% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::4-5 255647500 0.06% 99.93% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::6-7 124159500 0.03% 99.96% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::8-9 89499500 0.02% 99.98% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::10-11 56037000 0.01% 99.99% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::12-13 17511000 0.00% 99.99% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::14-15 23464500 0.01% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::16-17 345500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::total 458679401608 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walkPageSizes::4K 88263 88.13% 88.13% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::2M 11885 11.87% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 100148 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 548057 # Table walker requests started/completed, data/inst
1785,1786c1788,1789
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 523591 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92001 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 548057 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 100148 # Table walker requests started/completed, data/inst
1788,1789c1791,1792
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92001 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 615592 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 100148 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 648205 # Table walker requests started/completed, data/inst
1792,1796c1795,1799
< system.cpu1.dtb.read_hits 88459625 # DTB read hits
< system.cpu1.dtb.read_misses 355289 # DTB read misses
< system.cpu1.dtb.write_hits 73058314 # DTB write hits
< system.cpu1.dtb.write_misses 168302 # DTB write misses
< system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
---
> system.cpu1.dtb.read_hits 92943696 # DTB read hits
> system.cpu1.dtb.read_misses 375200 # DTB read misses
> system.cpu1.dtb.write_hits 76575759 # DTB write hits
> system.cpu1.dtb.write_misses 172857 # DTB write misses
> system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
1798,1802c1801,1805
< system.cpu1.dtb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
< system.cpu1.dtb.flush_entries 34429 # Number of entries that have been flushed from TLB
< system.cpu1.dtb.align_faults 243 # Number of TLB faults due to alignment restrictions
< system.cpu1.dtb.prefetch_faults 5558 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.flush_tlb_mva_asid 46180 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID
> system.cpu1.dtb.flush_entries 35565 # Number of entries that have been flushed from TLB
> system.cpu1.dtb.align_faults 273 # Number of TLB faults due to alignment restrictions
> system.cpu1.dtb.prefetch_faults 6009 # Number of TLB faults due to prefetch
1804,1806c1807,1809
< system.cpu1.dtb.perms_faults 38457 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 88814914 # DTB read accesses
< system.cpu1.dtb.write_accesses 73226616 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 39938 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 93318896 # DTB read accesses
> system.cpu1.dtb.write_accesses 76748616 # DTB write accesses
1808,1810c1811,1813
< system.cpu1.dtb.hits 161517939 # DTB hits
< system.cpu1.dtb.misses 523591 # DTB misses
< system.cpu1.dtb.accesses 162041530 # DTB accesses
---
> system.cpu1.dtb.hits 169519455 # DTB hits
> system.cpu1.dtb.misses 548057 # DTB misses
> system.cpu1.dtb.accesses 170067512 # DTB accesses
1840,1858c1843,1861
< system.cpu1.itb.walker.walks 79238 # Table walker walks requested
< system.cpu1.itb.walker.walksLong 79238 # Table walker walks initiated with long descriptors
< system.cpu1.itb.walker.walksLongTerminationLevel::Level2 670 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55768 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walksSquashedBefore 9704 # Table walks squashed before starting
< system.cpu1.itb.walker.walkWaitTime::samples 69534 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::mean 1362.196911 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::stdev 10189.827482 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::0-32767 68875 99.05% 99.05% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::32768-65535 429 0.62% 99.67% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::65536-98303 22 0.03% 99.70% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::98304-131071 45 0.06% 99.77% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::131072-163839 97 0.14% 99.91% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::163840-196607 46 0.07% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::196608-229375 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::229376-262143 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::262144-294911 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
---
> system.cpu1.itb.walker.walks 81693 # Table walker walks requested
> system.cpu1.itb.walker.walksLong 81693 # Table walker walks initiated with long descriptors
> system.cpu1.itb.walker.walksLongTerminationLevel::Level2 804 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walksLongTerminationLevel::Level3 58754 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walksSquashedBefore 9814 # Table walks squashed before starting
> system.cpu1.itb.walker.walkWaitTime::samples 71879 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::mean 1351.430877 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::stdev 10594.939676 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::0-32767 71238 99.11% 99.11% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::32768-65535 384 0.53% 99.64% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::65536-98303 26 0.04% 99.68% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::98304-131071 48 0.07% 99.75% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::131072-163839 113 0.16% 99.90% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::163840-196607 53 0.07% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::196608-229375 3 0.00% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::262144-294911 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::294912-327679 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
1860,1889c1863,1893
< system.cpu1.itb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::total 69534 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkCompletionTime::samples 66142 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::mean 24972.294457 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::gmean 22450.763423 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::stdev 20128.243900 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::0-65535 65282 98.70% 98.70% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::65536-131071 106 0.16% 98.86% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::131072-196607 635 0.96% 99.82% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::196608-262143 41 0.06% 99.88% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::262144-327679 34 0.05% 99.93% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::327680-393215 18 0.03% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::393216-458751 18 0.03% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::total 66142 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walksPending::samples 405913969924 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::mean 0.852777 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::stdev 0.354498 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::0 59781305300 14.73% 14.73% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::1 346114009624 85.27% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::2 16127000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::3 2369500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::4 82500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::5 76000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::total 405913969924 # Table walker pending requests distribution
< system.cpu1.itb.walker.walkPageSizes::4K 55768 98.81% 98.81% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::2M 670 1.19% 100.00% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::total 56438 # Table walker page sizes translated
---
> system.cpu1.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::458752-491519 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::total 71879 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkCompletionTime::samples 69372 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::mean 25253.272214 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::gmean 22467.195437 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::stdev 22091.390725 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::0-65535 68357 98.54% 98.54% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::65536-131071 80 0.12% 98.65% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::131072-196607 757 1.09% 99.74% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::196608-262143 76 0.11% 99.85% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::262144-327679 55 0.08% 99.93% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::393216-458751 15 0.02% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::458752-524287 11 0.02% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::total 69372 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walksPending::samples 407136400556 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::mean 0.838375 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::stdev 0.368280 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::0 65826877124 16.17% 16.17% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::1 341288268432 83.83% 99.99% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::2 19212000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::3 1863000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::4 150500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::5 29500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::total 407136400556 # Table walker pending requests distribution
> system.cpu1.itb.walker.walkPageSizes::4K 58754 98.65% 98.65% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::2M 804 1.35% 100.00% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::total 59558 # Table walker page sizes translated
1891,1892c1895,1896
< system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 79238 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Requested::total 79238 # Table walker requests started/completed, data/inst
---
> system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 81693 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Requested::total 81693 # Table walker requests started/completed, data/inst
1894,1898c1898,1902
< system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56438 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56438 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin::total 135676 # Table walker requests started/completed, data/inst
< system.cpu1.itb.inst_hits 188743149 # ITB inst hits
< system.cpu1.itb.inst_misses 79238 # ITB inst misses
---
> system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 59558 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Completed::total 59558 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin::total 141251 # Table walker requests started/completed, data/inst
> system.cpu1.itb.inst_hits 198485673 # ITB inst hits
> system.cpu1.itb.inst_misses 81693 # ITB inst misses
1903c1907
< system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
---
> system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
1905,1907c1909,1911
< system.cpu1.itb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
< system.cpu1.itb.flush_entries 24595 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_tlb_mva_asid 46180 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID
> system.cpu1.itb.flush_entries 25168 # Number of entries that have been flushed from TLB
1911c1915
< system.cpu1.itb.perms_faults 203696 # Number of TLB faults due to permissions restrictions
---
> system.cpu1.itb.perms_faults 206844 # Number of TLB faults due to permissions restrictions
1914,1918c1918,1922
< system.cpu1.itb.inst_accesses 188822387 # ITB inst accesses
< system.cpu1.itb.hits 188743149 # DTB hits
< system.cpu1.itb.misses 79238 # DTB misses
< system.cpu1.itb.accesses 188822387 # DTB accesses
< system.cpu1.numCycles 668763369 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 198567366 # ITB inst accesses
> system.cpu1.itb.hits 198485673 # DTB hits
> system.cpu1.itb.misses 81693 # DTB misses
> system.cpu1.itb.accesses 198567366 # DTB accesses
> system.cpu1.numCycles 706357244 # number of cpu cycles simulated
1921,1937c1925,1941
< system.cpu1.fetch.icacheStallCycles 76762482 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 531105996 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 119891525 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 70980597 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 555217707 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 12731518 # Number of cycles fetch has spent squashing
< system.cpu1.fetch.TlbCycles 1797928 # Number of cycles fetch has spent waiting for tlb
< system.cpu1.fetch.MiscStallCycles 295013 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu1.fetch.PendingTrapStallCycles 5987179 # Number of stall cycles due to pending traps
< system.cpu1.fetch.PendingQuiesceStallCycles 752221 # Number of stall cycles due to pending quiesce instructions
< system.cpu1.fetch.IcacheWaitRetryStallCycles 763722 # Number of stall cycles due to full MSHR
< system.cpu1.fetch.CacheLines 188519405 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 1489379 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.ItlbSquashes 27517 # Number of outstanding ITLB misses that were squashed
< system.cpu1.fetch.rateDist::samples 647942011 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 0.963740 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 1.217002 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.icacheStallCycles 79757859 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 558826368 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 126248667 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 74669921 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 588203471 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 13287396 # Number of cycles fetch has spent squashing
> system.cpu1.fetch.TlbCycles 1859618 # Number of cycles fetch has spent waiting for tlb
> system.cpu1.fetch.MiscStallCycles 301703 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu1.fetch.PendingTrapStallCycles 6107940 # Number of stall cycles due to pending traps
> system.cpu1.fetch.PendingQuiesceStallCycles 765855 # Number of stall cycles due to pending quiesce instructions
> system.cpu1.fetch.IcacheWaitRetryStallCycles 800562 # Number of stall cycles due to full MSHR
> system.cpu1.fetch.CacheLines 198257766 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 1531728 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.ItlbSquashes 28220 # Number of outstanding ITLB misses that were squashed
> system.cpu1.fetch.rateDist::samples 684440706 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 0.958907 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 1.215902 # Number of instructions fetched each cycle (Total)
1939,1942c1943,1946
< system.cpu1.fetch.rateDist::0 349005233 53.86% 53.86% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 116425876 17.97% 71.83% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 39511198 6.10% 77.93% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 142999704 22.07% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 370240796 54.09% 54.09% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 122429423 17.89% 71.98% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 41426108 6.05% 78.03% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 150344379 21.97% 100.00% # Number of instructions fetched each cycle (Total)
1946,1993c1950,1997
< system.cpu1.fetch.rateDist::total 647942011 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.179273 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 0.794161 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 92682171 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 320350015 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 196661442 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 33741382 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 4507001 # Number of cycles decode is squashing
< system.cpu1.decode.BranchResolved 16971690 # Number of times decode resolved a branch
< system.cpu1.decode.BranchMispred 1895430 # Number of times decode detected a branch misprediction
< system.cpu1.decode.DecodedInsts 551371568 # Number of instructions handled by decode
< system.cpu1.decode.SquashedInsts 20348682 # Number of squashed instructions handled by decode
< system.cpu1.rename.SquashCycles 4507001 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 124070698 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 47114866 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 212074227 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 198637530 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 61537689 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 536563152 # Number of instructions processed by rename
< system.cpu1.rename.SquashedInsts 5145214 # Number of squashed instructions processed by rename
< system.cpu1.rename.ROBFullEvents 9840770 # Number of times rename has blocked due to ROB full
< system.cpu1.rename.IQFullEvents 223861 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LQFullEvents 282097 # Number of times rename has blocked due to LQ full
< system.cpu1.rename.SQFullEvents 29934469 # Number of times rename has blocked due to SQ full
< system.cpu1.rename.FullRegisterEvents 10810 # Number of times there has been no free registers
< system.cpu1.rename.RenamedOperands 509803663 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 829081125 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 634679636 # Number of integer rename lookups
< system.cpu1.rename.fp_rename_lookups 600803 # Number of floating rename lookups
< system.cpu1.rename.CommittedMaps 459431302 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 50372361 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 14562905 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 12854163 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 68041373 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 88476596 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 76035338 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 8565835 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 7285035 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 516079501 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 14870100 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 521291240 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 2377203 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 47872437 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 30743352 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 257935 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 647942011 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 0.804534 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 1.061029 # Number of insts issued each cycle
---
> system.cpu1.fetch.rateDist::total 684440706 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.178732 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 0.791138 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 96144629 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 340788757 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 207685438 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 35085697 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 4736185 # Number of cycles decode is squashing
> system.cpu1.decode.BranchResolved 17812454 # Number of times decode resolved a branch
> system.cpu1.decode.BranchMispred 1944962 # Number of times decode detected a branch misprediction
> system.cpu1.decode.DecodedInsts 579921351 # Number of instructions handled by decode
> system.cpu1.decode.SquashedInsts 21338656 # Number of squashed instructions handled by decode
> system.cpu1.rename.SquashCycles 4736185 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 128930138 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 49237812 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 228920665 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 209565208 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 63050698 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 564205236 # Number of instructions processed by rename
> system.cpu1.rename.SquashedInsts 5454916 # Number of squashed instructions processed by rename
> system.cpu1.rename.ROBFullEvents 10256691 # Number of times rename has blocked due to ROB full
> system.cpu1.rename.IQFullEvents 240677 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LQFullEvents 354262 # Number of times rename has blocked due to LQ full
> system.cpu1.rename.SQFullEvents 30213880 # Number of times rename has blocked due to SQ full
> system.cpu1.rename.FullRegisterEvents 11171 # Number of times there has been no free registers
> system.cpu1.rename.RenamedOperands 537096625 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 872562806 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 667157366 # Number of integer rename lookups
> system.cpu1.rename.fp_rename_lookups 686134 # Number of floating rename lookups
> system.cpu1.rename.CommittedMaps 483982102 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 53114517 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 15098547 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 13303136 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 70645723 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 92937642 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 79702799 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 8581032 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 7318731 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 542982721 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 15290733 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 547999845 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 2492376 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 50310716 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 32527030 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 258040 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 684440706 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 0.800653 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 1.060998 # Number of insts issued each cycle
1995,2000c1999,2004
< system.cpu1.iq.issued_per_cycle::0 361872507 55.85% 55.85% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 122353667 18.88% 74.73% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 99252241 15.32% 90.05% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 57424869 8.86% 98.91% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 7035151 1.09% 100.00% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 3576 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 384384408 56.16% 56.16% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 127393239 18.61% 74.77% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 104776738 15.31% 90.08% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 60496264 8.84% 98.92% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 7385947 1.08% 100.00% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 4110 0.00% 100.00% # Number of insts issued each cycle
2007c2011
< system.cpu1.iq.issued_per_cycle::total 647942011 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 684440706 # Number of insts issued each cycle
2009,2039c2013,2043
< system.cpu1.iq.fu_full::IntAlu 52040674 43.67% 43.67% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 50092 0.04% 43.71% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 18388 0.02% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 16 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 32200400 27.02% 70.74% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 34865580 29.26% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 55139379 44.00% 44.00% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 46977 0.04% 44.04% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 11488 0.01% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 7 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.05% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 33502933 26.74% 70.78% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 36611567 29.22% 100.00% # attempts to use FU when none available
2042,2073c2046,2077
< system.cpu1.iq.FU_type_0::No_OpClass 27 0.00% 0.00% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntAlu 354670500 68.04% 68.04% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 1183955 0.23% 68.26% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 65513 0.01% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMisc 42657 0.01% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.28% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemRead 91135432 17.48% 85.77% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 74193108 14.23% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntAlu 373183107 68.10% 68.10% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 1202540 0.22% 68.32% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 67362 0.01% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 2 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.33% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMisc 42387 0.01% 68.34% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemRead 95737452 17.47% 85.81% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 77766935 14.19% 100.00% # Type of FU issued
2076,2088c2080,2092
< system.cpu1.iq.FU_type_0::total 521291240 # Type of FU issued
< system.cpu1.iq.rate 0.779485 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 119175150 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.228615 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 1811086365 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 578565811 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 506287229 # Number of integer instruction queue wakeup accesses
< system.cpu1.iq.fp_inst_queue_reads 990479 # Number of floating instruction queue reads
< system.cpu1.iq.fp_inst_queue_writes 395514 # Number of floating instruction queue writes
< system.cpu1.iq.fp_inst_queue_wakeup_accesses 364516 # Number of floating instruction queue wakeup accesses
< system.cpu1.iq.int_alu_accesses 639849832 # Number of integer alu accesses
< system.cpu1.iq.fp_alu_accesses 616531 # Number of floating point alu accesses
< system.cpu1.iew.lsq.thread0.forwLoads 2398408 # Number of loads that had data forwarded from stores
---
> system.cpu1.iq.FU_type_0::total 547999845 # Type of FU issued
> system.cpu1.iq.rate 0.775811 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 125312351 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.228672 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 1907132649 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 608283649 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 532258075 # Number of integer instruction queue wakeup accesses
> system.cpu1.iq.fp_inst_queue_reads 1112472 # Number of floating instruction queue reads
> system.cpu1.iq.fp_inst_queue_writes 437179 # Number of floating instruction queue writes
> system.cpu1.iq.fp_inst_queue_wakeup_accesses 408398 # Number of floating instruction queue wakeup accesses
> system.cpu1.iq.int_alu_accesses 672616839 # Number of integer alu accesses
> system.cpu1.iq.fp_alu_accesses 695346 # Number of floating point alu accesses
> system.cpu1.iew.lsq.thread0.forwLoads 2459057 # Number of loads that had data forwarded from stores
2090,2093c2094,2097
< system.cpu1.iew.lsq.thread0.squashedLoads 11063470 # Number of loads squashed
< system.cpu1.iew.lsq.thread0.ignoredResponses 14436 # Number of memory responses ignored because the instruction is squashed
< system.cpu1.iew.lsq.thread0.memOrderViolation 140383 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 5257500 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 11465284 # Number of loads squashed
> system.cpu1.iew.lsq.thread0.ignoredResponses 14564 # Number of memory responses ignored because the instruction is squashed
> system.cpu1.iew.lsq.thread0.memOrderViolation 137615 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 5482962 # Number of stores squashed
2096,2097c2100,2101
< system.cpu1.iew.lsq.thread0.rescheduledLoads 2402216 # Number of loads that were rescheduled
< system.cpu1.iew.lsq.thread0.cacheBlocked 3864822 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu1.iew.lsq.thread0.rescheduledLoads 2463728 # Number of loads that were rescheduled
> system.cpu1.iew.lsq.thread0.cacheBlocked 4019009 # Number of times an access to memory failed due to the cache being blocked
2099,2102c2103,2106
< system.cpu1.iew.iewSquashCycles 4507001 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 5849706 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 2188326 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 531063111 # Number of instructions dispatched to IQ
---
> system.cpu1.iew.iewSquashCycles 4736185 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 6263173 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 2375395 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 558389408 # Number of instructions dispatched to IQ
2104,2115c2108,2119
< system.cpu1.iew.iewDispLoadInsts 88476596 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 76035338 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 12650539 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 60907 # Number of times the IQ has become full, causing a stall
< system.cpu1.iew.iewLSQFullEvents 2070757 # Number of times the LSQ has become full, causing a stall
< system.cpu1.iew.memOrderViolationEvents 140383 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 1813068 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 2483133 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 4296201 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 514538937 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 88454625 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 6240485 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.iewDispLoadInsts 92937642 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 79702799 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 13061254 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 63231 # Number of times the IQ has become full, causing a stall
> system.cpu1.iew.iewLSQFullEvents 2253383 # Number of times the LSQ has become full, causing a stall
> system.cpu1.iew.memOrderViolationEvents 137615 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 1902304 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 2611236 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 4513540 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 540870869 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 92937926 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 6592838 # Number of squashed instructions skipped in execute
2117,2133c2121,2137
< system.cpu1.iew.exec_nop 113510 # number of nop insts executed
< system.cpu1.iew.exec_refs 161513914 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 96416033 # Number of branches executed
< system.cpu1.iew.exec_stores 73059289 # Number of stores executed
< system.cpu1.iew.exec_rate 0.769389 # Inst execution rate
< system.cpu1.iew.wb_sent 507314383 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 506651745 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 244576343 # num instructions producing a value
< system.cpu1.iew.wb_consumers 400655745 # num instructions consuming a value
< system.cpu1.iew.wb_rate 0.757595 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.610440 # average fanout of values written-back
< system.cpu1.commit.commitSquashedInsts 41944033 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 14612165 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 4045440 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 639995571 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 0.754813 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.555930 # Number of insts commited each cycle
---
> system.cpu1.iew.exec_nop 115954 # number of nop insts executed
> system.cpu1.iew.exec_refs 169513519 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 101590895 # Number of branches executed
> system.cpu1.iew.exec_stores 76575593 # Number of stores executed
> system.cpu1.iew.exec_rate 0.765719 # Inst execution rate
> system.cpu1.iew.wb_sent 533377466 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 532666473 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 257434056 # num instructions producing a value
> system.cpu1.iew.wb_consumers 422362739 # num instructions consuming a value
> system.cpu1.iew.wb_rate 0.754104 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.609509 # average fanout of values written-back
> system.cpu1.commit.commitSquashedInsts 44033715 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 15032693 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 4244342 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 676109975 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 0.751302 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 1.553770 # Number of insts commited each cycle
2135,2143c2139,2147
< system.cpu1.commit.committed_per_cycle::0 426913272 66.71% 66.71% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 112061055 17.51% 84.22% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 46474767 7.26% 91.48% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 15512784 2.42% 93.90% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 11149430 1.74% 95.64% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 7505688 1.17% 96.82% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 5285555 0.83% 97.64% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 3055428 0.48% 98.12% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 12037592 1.88% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 452513238 66.93% 66.93% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 117033560 17.31% 84.24% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 49159205 7.27% 91.51% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 16297256 2.41% 93.92% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 11766410 1.74% 95.66% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 7925929 1.17% 96.83% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 5496145 0.81% 97.65% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 3299018 0.49% 98.13% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 12619214 1.87% 100.00% # Number of insts commited each cycle
2147,2149c2151,2153
< system.cpu1.commit.committed_per_cycle::total 639995571 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 409938912 # Number of instructions committed
< system.cpu1.commit.committedOps 483077163 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 676109975 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 431347574 # Number of instructions committed
> system.cpu1.commit.committedOps 507962731 # Number of ops (including micro ops) committed
2151,2157c2155,2161
< system.cpu1.commit.refs 148190964 # Number of memory references committed
< system.cpu1.commit.loads 77413126 # Number of loads committed
< system.cpu1.commit.membars 3553266 # Number of memory barriers committed
< system.cpu1.commit.branches 91478423 # Number of branches committed
< system.cpu1.commit.fp_insts 356192 # Number of committed floating point instructions.
< system.cpu1.commit.int_insts 443462583 # Number of committed integer instructions.
< system.cpu1.commit.function_calls 11919697 # Number of function calls committed.
---
> system.cpu1.commit.refs 155692194 # Number of memory references committed
> system.cpu1.commit.loads 81472357 # Number of loads committed
> system.cpu1.commit.membars 3613840 # Number of memory barriers committed
> system.cpu1.commit.branches 96395557 # Number of branches committed
> system.cpu1.commit.fp_insts 400161 # Number of committed floating point instructions.
> system.cpu1.commit.int_insts 466077725 # Number of committed integer instructions.
> system.cpu1.commit.function_calls 12507771 # Number of function calls committed.
2159,2189c2163,2193
< system.cpu1.commit.op_class_0::IntAlu 333838399 69.11% 69.11% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntMult 958189 0.20% 69.30% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntDiv 52064 0.01% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMisc 37505 0.01% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.32% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemRead 77413126 16.03% 85.35% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemWrite 70777838 14.65% 100.00% # Class of committed instruction
---
> system.cpu1.commit.op_class_0::IntAlu 351213617 69.14% 69.14% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntMult 966298 0.19% 69.33% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntDiv 53161 0.01% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.34% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMisc 37419 0.01% 69.35% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.35% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.35% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.35% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemRead 81472357 16.04% 85.39% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemWrite 74219837 14.61% 100.00% # Class of committed instruction
2192,2317c2196,2322
< system.cpu1.commit.op_class_0::total 483077163 # Class of committed instruction
< system.cpu1.commit.bw_lim_events 12037592 # number cycles where commit BW limit reached
< system.cpu1.rob.rob_reads 1149378464 # The number of ROB reads
< system.cpu1.rob.rob_writes 1057951201 # The number of ROB writes
< system.cpu1.timesIdled 862725 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 20821358 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 94039702456 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 409938912 # Number of Instructions Simulated
< system.cpu1.committedOps 483077163 # Number of Ops (including micro ops) Simulated
< system.cpu1.cpi 1.631373 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 1.631373 # CPI: Total CPI of All Threads
< system.cpu1.ipc 0.612981 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 0.612981 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 608507800 # number of integer regfile reads
< system.cpu1.int_regfile_writes 359700181 # number of integer regfile writes
< system.cpu1.fp_regfile_reads 588843 # number of floating regfile reads
< system.cpu1.fp_regfile_writes 298828 # number of floating regfile writes
< system.cpu1.cc_regfile_reads 110183943 # number of cc regfile reads
< system.cpu1.cc_regfile_writes 110950246 # number of cc regfile writes
< system.cpu1.misc_regfile_reads 1143200959 # number of misc regfile reads
< system.cpu1.misc_regfile_writes 14699928 # number of misc regfile writes
< system.cpu1.dcache.tags.replacements 4943818 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 455.490717 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 138046990 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 4944322 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 27.920307 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 8486298300000 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.490717 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.889630 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.889630 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 504 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::1 434 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 0.984375 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 307427480 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 307427480 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 71852716 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 71852716 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 61790747 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 61790747 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 162379 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 162379 # number of SoftPFReq hits
< system.cpu1.dcache.WriteLineReq_hits::cpu1.data 50057 # number of WriteLineReq hits
< system.cpu1.dcache.WriteLineReq_hits::total 50057 # number of WriteLineReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1706960 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 1706960 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1722622 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 1722622 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 133643463 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 133643463 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 133805842 # number of overall hits
< system.cpu1.dcache.overall_hits::total 133805842 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 5820950 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 5820950 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 6630483 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 6630483 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 628859 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 628859 # number of SoftPFReq misses
< system.cpu1.dcache.WriteLineReq_misses::cpu1.data 401328 # number of WriteLineReq misses
< system.cpu1.dcache.WriteLineReq_misses::total 401328 # number of WriteLineReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 243245 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 243245 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 186259 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 186259 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 12451433 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 12451433 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 13080292 # number of overall misses
< system.cpu1.dcache.overall_misses::total 13080292 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96708932500 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 96708932500 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 144491403356 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 144491403356 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16631824083 # number of WriteLineReq miss cycles
< system.cpu1.dcache.WriteLineReq_miss_latency::total 16631824083 # number of WriteLineReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3760760000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 3760760000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5141971500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 5141971500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6754500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 6754500 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 241200335856 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 241200335856 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 241200335856 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 241200335856 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 77673666 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 77673666 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 68421230 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 68421230 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 791238 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 791238 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 451385 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::total 451385 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1950205 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 1950205 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1908881 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 1908881 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 146094896 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 146094896 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 146886134 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 146886134 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074941 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.074941 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.096907 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.096907 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.794779 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.794779 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.889104 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::total 0.889104 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124728 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124728 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097575 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097575 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085228 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.085228 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089051 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.089051 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16613.943171 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 16613.943171 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21791.987606 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 21791.987606 # average WriteReq miss latency
< system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 41441.972858 # average WriteLineReq miss latency
< system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 41441.972858 # average WriteLineReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15460.790561 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15460.790561 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27606.566663 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27606.566663 # average StoreCondReq miss latency
---
> system.cpu1.commit.op_class_0::total 507962731 # Class of committed instruction
> system.cpu1.commit.bw_lim_events 12619214 # number cycles where commit BW limit reached
> system.cpu1.rob.rob_reads 1211577193 # The number of ROB reads
> system.cpu1.rob.rob_writes 1112287280 # The number of ROB writes
> system.cpu1.timesIdled 906823 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 21916538 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 94073218429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 431347574 # Number of Instructions Simulated
> system.cpu1.committedOps 507962731 # Number of Ops (including micro ops) Simulated
> system.cpu1.cpi 1.637559 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 1.637559 # CPI: Total CPI of All Threads
> system.cpu1.ipc 0.610665 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 0.610665 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 639350275 # number of integer regfile reads
> system.cpu1.int_regfile_writes 378298878 # number of integer regfile writes
> system.cpu1.fp_regfile_reads 675031 # number of floating regfile reads
> system.cpu1.fp_regfile_writes 302028 # number of floating regfile writes
> system.cpu1.cc_regfile_reads 116956107 # number of cc regfile reads
> system.cpu1.cc_regfile_writes 117682636 # number of cc regfile writes
> system.cpu1.misc_regfile_reads 1203449961 # number of misc regfile reads
> system.cpu1.misc_regfile_writes 15173732 # number of misc regfile writes
> system.cpu1.dcache.tags.replacements 5181385 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 448.144658 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 145015910 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 5181896 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 27.985106 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 8482612216500 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 448.144658 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.875283 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.875283 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 322931039 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 322931039 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 75698887 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 75698887 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 64698314 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 64698314 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 177630 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 177630 # number of SoftPFReq hits
> system.cpu1.dcache.WriteLineReq_hits::cpu1.data 137318 # number of WriteLineReq hits
> system.cpu1.dcache.WriteLineReq_hits::total 137318 # number of WriteLineReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1768516 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 1768516 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1769874 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 1769874 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 140397201 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 140397201 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 140574831 # number of overall hits
> system.cpu1.dcache.overall_hits::total 140574831 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 6071314 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 6071314 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 6974888 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 6974888 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 655927 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 655927 # number of SoftPFReq misses
> system.cpu1.dcache.WriteLineReq_misses::cpu1.data 434582 # number of WriteLineReq misses
> system.cpu1.dcache.WriteLineReq_misses::total 434582 # number of WriteLineReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 243161 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 243161 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 198274 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 198274 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 13046202 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 13046202 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 13702129 # number of overall misses
> system.cpu1.dcache.overall_misses::total 13702129 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 101097830500 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 101097830500 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 149656092437 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 149656092437 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16022463739 # number of WriteLineReq miss cycles
> system.cpu1.dcache.WriteLineReq_miss_latency::total 16022463739 # number of WriteLineReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3928870000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 3928870000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5496174000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 5496174000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4605500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4605500 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 250753922937 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 250753922937 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 250753922937 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 250753922937 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 81770201 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 81770201 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 71673202 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 71673202 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 833557 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 833557 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 571900 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::total 571900 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2011677 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 2011677 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1968148 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 1968148 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 153443403 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 153443403 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 154276960 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 154276960 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074248 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.074248 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.097315 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.097315 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.786901 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.786901 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.759892 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::total 0.759892 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120875 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120875 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100741 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100741 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085023 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.085023 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.088815 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.088815 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16651.721604 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 16651.721604 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21456.415133 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 21456.415133 # average WriteReq miss latency
> system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 36868.677808 # average WriteLineReq miss latency
> system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 36868.677808 # average WriteLineReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16157.484136 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16157.484136 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27720.094415 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27720.094415 # average StoreCondReq miss latency
2320,2329c2325,2334
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19371.291309 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 19371.291309 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18439.980992 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 18439.980992 # average overall miss latency
< system.cpu1.dcache.blocked_cycles::no_mshrs 4381553 # number of cycles access was blocked
< system.cpu1.dcache.blocked_cycles::no_targets 22968096 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_mshrs 326353 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_targets 670571 # number of cycles access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.425809 # average number of cycles each access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_targets 34.251550 # average number of cycles each access was blocked
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19220.453810 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 19220.453810 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18300.362151 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 18300.362151 # average overall miss latency
> system.cpu1.dcache.blocked_cycles::no_mshrs 4223664 # number of cycles access was blocked
> system.cpu1.dcache.blocked_cycles::no_targets 23883166 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_mshrs 349910 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_targets 702949 # number of cycles access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.070715 # average number of cycles each access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_targets 33.975674 # average number of cycles each access was blocked
2332,2419c2337,2424
< system.cpu1.dcache.writebacks::writebacks 4943833 # number of writebacks
< system.cpu1.dcache.writebacks::total 4943833 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 2977175 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 2977175 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5355618 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 5355618 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3078 # number of WriteLineReq MSHR hits
< system.cpu1.dcache.WriteLineReq_mshr_hits::total 3078 # number of WriteLineReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 125917 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 125917 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 8332793 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 8332793 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 8332793 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 8332793 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2843775 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 2843775 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1274865 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 1274865 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 628773 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 628773 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 398250 # number of WriteLineReq MSHR misses
< system.cpu1.dcache.WriteLineReq_mshr_misses::total 398250 # number of WriteLineReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 117328 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 117328 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 186249 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 186249 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 4118640 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 4118640 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 4747413 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 4747413 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5429 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5429 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5284 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5284 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10713 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10713 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43326231000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43326231000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 30961849442 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 30961849442 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15267610500 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15267610500 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 16078596583 # number of WriteLineReq MSHR miss cycles
< system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 16078596583 # number of WriteLineReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1709363500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1709363500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4955815500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4955815500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6661500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6661500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 74288080442 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 74288080442 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 89555690942 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 89555690942 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 604887500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 604887500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 670175500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 670175500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1275063000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1275063000 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036612 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036612 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018633 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018633 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.794670 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.794670 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.882285 # mshr miss rate for WriteLineReq accesses
< system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.882285 # mshr miss rate for WriteLineReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060162 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060162 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097570 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097570 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028192 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.028192 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032320 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.032320 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15235.463776 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15235.463776 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24286.374982 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24286.374982 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24281.593675 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24281.593675 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40373.123874 # average WriteLineReq mshr miss latency
< system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 40373.123874 # average WriteLineReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14569.101152 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14569.101152 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26608.548234 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26608.548234 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 5181409 # number of writebacks
> system.cpu1.dcache.writebacks::total 5181409 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3107506 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 3107506 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5642769 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 5642769 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3498 # number of WriteLineReq MSHR hits
> system.cpu1.dcache.WriteLineReq_mshr_hits::total 3498 # number of WriteLineReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 127094 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 127094 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 8750275 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 8750275 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 8750275 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 8750275 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2963808 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 2963808 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1332119 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 1332119 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 655846 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 655846 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 431084 # number of WriteLineReq MSHR misses
> system.cpu1.dcache.WriteLineReq_mshr_misses::total 431084 # number of WriteLineReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116067 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116067 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 198274 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 198274 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 4295927 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 4295927 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 4951773 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 4951773 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 18536 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 18536 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 16538 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 16538 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 35074 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 35074 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 45006607000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 45006607000 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 31827699093 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 31827699093 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16353139500 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16353139500 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 15385116239 # number of WriteLineReq MSHR miss cycles
> system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 15385116239 # number of WriteLineReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1766523500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1766523500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5297954000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5297954000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4551500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4551500 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 76834306093 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 76834306093 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 93187445593 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 93187445593 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3073252500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3073252500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2816431000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2816431000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5889683500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5889683500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036246 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036246 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018586 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018586 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.786804 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.786804 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.753775 # mshr miss rate for WriteLineReq accesses
> system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.753775 # mshr miss rate for WriteLineReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.057697 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.057697 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100741 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100741 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027997 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.027997 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032097 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.032097 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15185.398987 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15185.398987 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23892.534445 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23892.534445 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24934.419818 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24934.419818 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 35689.369680 # average WriteLineReq mshr miss latency
> system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 35689.369680 # average WriteLineReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15219.860081 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15219.860081 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26720.366765 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26720.366765 # average StoreCondReq mshr miss latency
2422,2431c2427,2436
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18037.041461 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18037.041461 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18864.103659 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18864.103659 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 111417.848591 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 111417.848591 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 126831.093868 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 126831.093868 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 119020.162419 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 119020.162419 # average overall mshr uncacheable latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17885.384480 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17885.384480 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18819.005959 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18819.005959 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165799.120630 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165799.120630 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 170300.580481 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170300.580481 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 167921.637110 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 167921.637110 # average overall mshr uncacheable latency
2433,2441c2438,2446
< system.cpu1.icache.tags.replacements 5253385 # number of replacements
< system.cpu1.icache.tags.tagsinuse 501.776230 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 182951519 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 5253897 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 34.822060 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 8525973531000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.776230 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980032 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.980032 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.replacements 5433139 # number of replacements
> system.cpu1.icache.tags.tagsinuse 501.652394 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 192499091 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 5433651 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 35.427209 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 8522355919000 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.652394 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979790 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.979790 # Average percentage of cache occupancy
2443,2444c2448,2450
< system.cpu1.icache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 104 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id
2446,2489c2452,2495
< system.cpu1.icache.tags.tag_accesses 382279380 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 382279380 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 182951519 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 182951519 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 182951519 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 182951519 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 182951519 # number of overall hits
< system.cpu1.icache.overall_hits::total 182951519 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 5561220 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 5561220 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 5561220 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 5561220 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 5561220 # number of overall misses
< system.cpu1.icache.overall_misses::total 5561220 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 62243274721 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 62243274721 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 62243274721 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 62243274721 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 62243274721 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 62243274721 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 188512739 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 188512739 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 188512739 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 188512739 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 188512739 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 188512739 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029500 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.029500 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029500 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.029500 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029500 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.029500 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11192.377701 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 11192.377701 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11192.377701 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 11192.377701 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11192.377701 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 11192.377701 # average overall miss latency
< system.cpu1.icache.blocked_cycles::no_mshrs 9679381 # number of cycles access was blocked
< system.cpu1.icache.blocked_cycles::no_targets 762 # number of cycles access was blocked
< system.cpu1.icache.blocked::no_mshrs 668024 # number of cycles access was blocked
< system.cpu1.icache.blocked::no_targets 6 # number of cycles access was blocked
< system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.489571 # average number of cycles each access was blocked
< system.cpu1.icache.avg_blocked_cycles::no_targets 127 # average number of cycles each access was blocked
---
> system.cpu1.icache.tags.tag_accesses 401935440 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 401935440 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 192499091 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 192499091 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 192499091 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 192499091 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 192499091 # number of overall hits
> system.cpu1.icache.overall_hits::total 192499091 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 5751797 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 5751797 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 5751797 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 5751797 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 5751797 # number of overall misses
> system.cpu1.icache.overall_misses::total 5751797 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 64772051533 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 64772051533 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 64772051533 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 64772051533 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 64772051533 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 64772051533 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 198250888 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 198250888 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 198250888 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 198250888 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 198250888 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 198250888 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029013 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.029013 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029013 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.029013 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029013 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.029013 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11261.185249 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 11261.185249 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11261.185249 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 11261.185249 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11261.185249 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 11261.185249 # average overall miss latency
> system.cpu1.icache.blocked_cycles::no_mshrs 9932539 # number of cycles access was blocked
> system.cpu1.icache.blocked_cycles::no_targets 584 # number of cycles access was blocked
> system.cpu1.icache.blocked::no_mshrs 679779 # number of cycles access was blocked
> system.cpu1.icache.blocked::no_targets 7 # number of cycles access was blocked
> system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.611424 # average number of cycles each access was blocked
> system.cpu1.icache.avg_blocked_cycles::no_targets 83.428571 # average number of cycles each access was blocked
2492,2505c2498,2511
< system.cpu1.icache.writebacks::writebacks 5253385 # number of writebacks
< system.cpu1.icache.writebacks::total 5253385 # number of writebacks
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 307318 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 307318 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 307318 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 307318 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 307318 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 307318 # number of overall MSHR hits
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5253902 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 5253902 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 5253902 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 5253902 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 5253902 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 5253902 # number of overall MSHR misses
---
> system.cpu1.icache.writebacks::writebacks 5433139 # number of writebacks
> system.cpu1.icache.writebacks::total 5433139 # number of writebacks
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 318133 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 318133 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 318133 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 318133 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 318133 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 318133 # number of overall MSHR hits
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5433664 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 5433664 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 5433664 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 5433664 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 5433664 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 5433664 # number of overall MSHR misses
2510,2535c2516,2541
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 56076616223 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 56076616223 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 56076616223 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 56076616223 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 56076616223 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 56076616223 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9266998 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9266998 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9266998 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 9266998 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027870 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027870 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027870 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.027870 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027870 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.027870 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10673.327409 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10673.327409 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10673.327409 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 10673.327409 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10673.327409 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 10673.327409 # average overall mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 138313.402985 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 138313.402985 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 138313.402985 # average overall mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 138313.402985 # average overall mshr uncacheable latency
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 58335043744 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 58335043744 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 58335043744 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 58335043744 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58335043744 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 58335043744 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9645998 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9645998 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9645998 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 9645998 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027408 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027408 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027408 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.027408 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027408 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.027408 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10735.857746 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10735.857746 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10735.857746 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 10735.857746 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10735.857746 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 10735.857746 # average overall mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 143970.119403 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 143970.119403 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 143970.119403 # average overall mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 143970.119403 # average overall mshr uncacheable latency
2537,2539c2543,2545
< system.cpu1.l2cache.prefetcher.num_hwpf_issued 6897065 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.pfIdentified 6901426 # number of prefetch candidates identified
< system.cpu1.l2cache.prefetcher.pfBufferHit 4002 # number of redundant prefetches already in prefetch queue
---
> system.cpu1.l2cache.prefetcher.num_hwpf_issued 7104582 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.pfIdentified 7110323 # number of prefetch candidates identified
> system.cpu1.l2cache.prefetcher.pfBufferHit 5229 # number of redundant prefetches already in prefetch queue
2542,2607c2548,2617
< system.cpu1.l2cache.prefetcher.pfSpanPage 806814 # number of prefetches not generated due to page crossing
< system.cpu1.l2cache.tags.replacements 2026565 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 13359.801047 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 15204091 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 2042184 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 7.445015 # Average number of references to valid blocks.
< system.cpu1.l2cache.tags.warmup_cycle 10003867799500 # Cycle when the warmup percentage was hit.
< system.cpu1.l2cache.tags.occ_blocks::writebacks 12523.198532 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 53.208861 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 55.513996 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 727.879658 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.764355 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003248 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003388 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.044426 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.815418 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1266 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 101 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14252 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 87 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 167 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 620 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 392 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 76 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 933 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4753 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4784 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3782 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.077271 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006165 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.869873 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 351102850 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 351102850 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 535016 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 179387 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 714403 # number of ReadReq hits
< system.cpu1.l2cache.WritebackDirty_hits::writebacks 3106842 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackDirty_hits::total 3106842 # number of WritebackDirty hits
< system.cpu1.l2cache.WritebackClean_hits::writebacks 7089221 # number of WritebackClean hits
< system.cpu1.l2cache.WritebackClean_hits::total 7089221 # number of WritebackClean hits
< system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 559 # number of UpgradeReq hits
< system.cpu1.l2cache.UpgradeReq_hits::total 559 # number of UpgradeReq hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 768937 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 768937 # number of ReadExReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4743157 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::total 4743157 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2644934 # number of ReadSharedReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::total 2644934 # number of ReadSharedReq hits
< system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 173458 # number of InvalidateReq hits
< system.cpu1.l2cache.InvalidateReq_hits::total 173458 # number of InvalidateReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 535016 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 179387 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 4743157 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 3413871 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 8871431 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 535016 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 179387 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 4743157 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 3413871 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 8871431 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11427 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8460 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 19887 # number of ReadReq misses
---
> system.cpu1.l2cache.prefetcher.pfSpanPage 868037 # number of prefetches not generated due to page crossing
> system.cpu1.l2cache.tags.replacements 2129197 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 13328.245122 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 15739911 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 2145331 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 7.336822 # Average number of references to valid blocks.
> system.cpu1.l2cache.tags.warmup_cycle 9958132586000 # Cycle when the warmup percentage was hit.
> system.cpu1.l2cache.tags.occ_blocks::writebacks 12434.905270 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 47.585138 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 48.632741 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.data 0.000002 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 797.121970 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.758966 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002904 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.002968 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.000000 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048652 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.813492 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1216 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 75 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14843 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 201 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 613 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 375 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 43 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1347 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6023 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4378 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2999 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.074219 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004578 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.905945 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 365454297 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 365454297 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 563276 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 186249 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 749525 # number of ReadReq hits
> system.cpu1.l2cache.WritebackDirty_hits::writebacks 3287486 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackDirty_hits::total 3287486 # number of WritebackDirty hits
> system.cpu1.l2cache.WritebackClean_hits::writebacks 7325630 # number of WritebackClean hits
> system.cpu1.l2cache.WritebackClean_hits::total 7325630 # number of WritebackClean hits
> system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 588 # number of UpgradeReq hits
> system.cpu1.l2cache.UpgradeReq_hits::total 588 # number of UpgradeReq hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 828832 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 828832 # number of ReadExReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4887396 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::total 4887396 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2758073 # number of ReadSharedReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::total 2758073 # number of ReadSharedReq hits
> system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 186873 # number of InvalidateReq hits
> system.cpu1.l2cache.InvalidateReq_hits::total 186873 # number of InvalidateReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 563276 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 186249 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 4887396 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 3586905 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 9223826 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 563276 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 186249 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 4887396 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 3586905 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 9223826 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11569 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8316 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 19885 # number of ReadReq misses
2610,2694c2620,2706
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 231672 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 231672 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 186238 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 186238 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 11 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::total 11 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 282579 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 282579 # number of ReadExReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 510739 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::total 510739 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 941159 # number of ReadSharedReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::total 941159 # number of ReadSharedReq misses
< system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 223115 # number of InvalidateReq misses
< system.cpu1.l2cache.InvalidateReq_misses::total 223115 # number of InvalidateReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11427 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8460 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 510739 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 1223738 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 1754364 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11427 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8460 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 510739 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 1223738 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 1754364 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 504816000 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 376201500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 881017500 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3395371000 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 3395371000 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1764127500 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1764127500 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 6519498 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 6519498 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 14960777499 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 14960777499 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 19472916000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::total 19472916000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 37255203986 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::total 37255203986 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 13917612499 # number of InvalidateReq miss cycles
< system.cpu1.l2cache.InvalidateReq_miss_latency::total 13917612499 # number of InvalidateReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 504816000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 376201500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 19472916000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 52215981485 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 72569914985 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 504816000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 376201500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 19472916000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 52215981485 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 72569914985 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 546443 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 187847 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 734290 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3106847 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackDirty_accesses::total 3106847 # number of WritebackDirty accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::writebacks 7089221 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.WritebackClean_accesses::total 7089221 # number of WritebackClean accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 232231 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 232231 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 186238 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 186238 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 11 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 11 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1051516 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 1051516 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5253896 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::total 5253896 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3586093 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::total 3586093 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 396573 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::total 396573 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 546443 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 187847 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 5253896 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 4637609 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 10625795 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 546443 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 187847 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 5253896 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 4637609 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 10625795 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020912 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.045037 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.027083 # miss rate for ReadReq accesses
---
> system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses
> system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 227542 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 227542 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 198269 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 198269 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 283901 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 283901 # number of ReadExReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 546263 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::total 546263 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 973715 # number of ReadSharedReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::total 973715 # number of ReadSharedReq misses
> system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 242230 # number of InvalidateReq misses
> system.cpu1.l2cache.InvalidateReq_misses::total 242230 # number of InvalidateReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11569 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8316 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 546263 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 1257616 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 1823764 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11569 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8316 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 546263 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 1257616 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 1823764 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 548560000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 408520000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 957080000 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3391225500 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 3391225500 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1846888500 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1846888500 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4469999 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4469999 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 15324598999 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 15324598999 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 20599116500 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::total 20599116500 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 39102280478 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::total 39102280478 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 513890000 # number of InvalidateReq miss cycles
> system.cpu1.l2cache.InvalidateReq_miss_latency::total 513890000 # number of InvalidateReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 548560000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 408520000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 20599116500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 54426879477 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 75983075977 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 548560000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 408520000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 20599116500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 54426879477 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 75983075977 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 574845 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 194565 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 769410 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3287491 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackDirty_accesses::total 3287491 # number of WritebackDirty accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::writebacks 7325631 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.WritebackClean_accesses::total 7325631 # number of WritebackClean accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 228130 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 228130 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 198269 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 198269 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1112733 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 1112733 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5433659 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::total 5433659 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3731788 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::total 3731788 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 429103 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::total 429103 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 574845 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 194565 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 5433659 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 4844521 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 11047590 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 574845 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 194565 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 5433659 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 4844521 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 11047590 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020125 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.042742 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.025844 # miss rate for ReadReq accesses
2697,2698c2709,2712
< system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.997593 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.997593 # miss rate for UpgradeReq accesses
---
> system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses
> system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.997423 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.997423 # miss rate for UpgradeReq accesses
2703,2748c2717,2762
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.268735 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.268735 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097211 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097211 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.262447 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.262447 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.562608 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.562608 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020912 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.045037 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097211 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.263873 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.165104 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020912 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.045037 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097211 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.263873 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.165104 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 44177.474403 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 44468.262411 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 44301.176648 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14655.940295 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14655.940295 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9472.435808 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9472.435808 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 592681.636364 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 592681.636364 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52943.698927 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52943.698927 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38126.941549 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38126.941549 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 39584.389020 # average ReadSharedReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 39584.389020 # average ReadSharedReq miss latency
< system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 62378.650019 # average InvalidateReq miss latency
< system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 62378.650019 # average InvalidateReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 44177.474403 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 44468.262411 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38126.941549 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 42669.249043 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 41365.369436 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 44177.474403 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 44468.262411 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38126.941549 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 42669.249043 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 41365.369436 # average overall miss latency
< system.cpu1.l2cache.blocked_cycles::no_mshrs 688 # number of cycles access was blocked
---
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.255138 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.255138 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.100533 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.100533 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.260925 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.260925 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.564503 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.564503 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020125 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.042742 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.100533 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.259596 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.165083 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020125 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.042742 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.100533 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.259596 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.165083 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 47416.371337 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 49124.579125 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 48130.751823 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14903.734256 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14903.734256 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9315.064382 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9315.064382 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 893999.800000 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 893999.800000 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53978.672139 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53978.672139 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37709.155663 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37709.155663 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 40157.829014 # average ReadSharedReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 40157.829014 # average ReadSharedReq miss latency
> system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 2121.496099 # average InvalidateReq miss latency
> system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 2121.496099 # average InvalidateReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 47416.371337 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 49124.579125 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37709.155663 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 43277.820477 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 41662.778724 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 47416.371337 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 49124.579125 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37709.155663 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 43277.820477 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 41662.778724 # average overall miss latency
> system.cpu1.l2cache.blocked_cycles::no_mshrs 699 # number of cycles access was blocked
2750c2764
< system.cpu1.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
---
> system.cpu1.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked
2752c2766
< system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 172 # average number of cycles each access was blocked
---
> system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 87.375000 # average number of cycles each access was blocked
2756,2777c2770,2795
< system.cpu1.l2cache.writebacks::writebacks 1085694 # number of writebacks
< system.cpu1.l2cache.writebacks::total 1085694 # number of writebacks
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 5 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 200 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::total 205 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 34736 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 34736 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4713 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4713 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 6 # number of InvalidateReq MSHR hits
< system.cpu1.l2cache.InvalidateReq_mshr_hits::total 6 # number of InvalidateReq MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 5 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 200 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 39449 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 39654 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 5 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 200 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 39449 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 39654 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11422 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8260 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 19682 # number of ReadReq MSHR misses
---
> system.cpu1.l2cache.writebacks::writebacks 1118169 # number of writebacks
> system.cpu1.l2cache.writebacks::total 1118169 # number of writebacks
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 4 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 196 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::total 200 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 38879 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 38879 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4580 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4580 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 9 # number of InvalidateReq MSHR hits
> system.cpu1.l2cache.InvalidateReq_mshr_hits::total 9 # number of InvalidateReq MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 4 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 196 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 43459 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 43660 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 4 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 196 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 43459 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 43660 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11565 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8120 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 19685 # number of ReadReq MSHR misses
2780,2806c2798,2826
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 718118 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 718118 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 231672 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 231672 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 186238 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 186238 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 11 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 11 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 247843 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 247843 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 510739 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 510739 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 936446 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 936446 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 223109 # number of InvalidateReq MSHR misses
< system.cpu1.l2cache.InvalidateReq_mshr_misses::total 223109 # number of InvalidateReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11422 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8260 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 510739 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1184289 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 1714710 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11422 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8260 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 510739 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1184289 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 718118 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 2432828 # number of overall MSHR misses
---
> system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses
> system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 735217 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 735217 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 227542 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 227542 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 198269 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 198269 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 245022 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 245022 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 546262 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 546262 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 969135 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 969135 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 242221 # number of InvalidateReq MSHR misses
> system.cpu1.l2cache.InvalidateReq_mshr_misses::total 242221 # number of InvalidateReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11565 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8120 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 546262 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1214157 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 1780104 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11565 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8120 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 546262 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1214157 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 735217 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 2515321 # number of overall MSHR misses
2808,2811c2828,2831
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5429 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5496 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5284 # number of WriteReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5284 # number of WriteReq MSHR uncacheable
---
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 18536 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 18603 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 16538 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 16538 # number of WriteReq MSHR uncacheable
2813,2855c2833,2875
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10713 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10780 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 436185000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 314747000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 750932000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 40592481689 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 40592481689 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7117149993 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7117149993 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3556198494 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3556198494 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 5961498 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 5961498 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11593238999 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11593238999 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 16408482000 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 16408482000 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 31352302486 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 31352302486 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 12578456999 # number of InvalidateReq MSHR miss cycles
< system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 12578456999 # number of InvalidateReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 436185000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 314747000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 16408482000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 42945541485 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 60104955485 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 436185000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 314747000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16408482000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 42945541485 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 40592481689 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 100697437174 # number of overall MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8763500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 561342500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 570106000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 630451500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 630451500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8763500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1191794000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1200557500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020902 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.043972 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.026804 # mshr miss rate for ReadReq accesses
---
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 35074 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 35141 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 479105500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 347671000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 826776500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 45381598688 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 45381598688 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7175483993 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7175483993 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3808164996 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3808164996 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4145999 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4145999 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11475367999 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11475367999 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 17321524000 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 17321524000 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 33026830978 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 33026830978 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 11580370998 # number of InvalidateReq MSHR miss cycles
> system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 11580370998 # number of InvalidateReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 479105500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 347671000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 17321524000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 44502198977 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 62650499477 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 479105500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 347671000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 17321524000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 44502198977 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 45381598688 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 108032098165 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9142500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2924847500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2933990000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2692324500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2692324500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9142500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5617172000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5626314500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020118 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.041734 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025585 # mshr miss rate for ReadReq accesses
2857a2878,2879
> system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
> system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
2860,2861c2882,2883
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997593 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997593 # mshr miss rate for UpgradeReq accesses
---
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997423 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997423 # mshr miss rate for UpgradeReq accesses
2866,2882c2888,2904
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.235701 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.235701 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.097211 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097211 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.261133 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.261133 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.562593 # mshr miss rate for InvalidateReq accesses
< system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.562593 # mshr miss rate for InvalidateReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020902 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.043972 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.097211 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.255366 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.161372 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020902 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.043972 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.097211 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.255366 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.220198 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.220198 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.100533 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.100533 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.259697 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.259697 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.564482 # mshr miss rate for InvalidateReq accesses
> system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.564482 # mshr miss rate for InvalidateReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020118 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.041734 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.100533 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.250625 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.161131 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020118 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.041734 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.100533 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.250625 # mshr miss rate for overall accesses
2884,2922c2906,2944
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.228955 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 38188.145684 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38104.963680 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38153.236460 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 56526.199996 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 56526.199996 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 30720.803520 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30720.803520 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19094.913466 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19094.913466 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 541954.363636 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 541954.363636 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46776.544018 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46776.544018 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32126.941549 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32126.941549 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33480.096542 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33480.096542 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 56378.079768 # average InvalidateReq mshr miss latency
< system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 56378.079768 # average InvalidateReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 38188.145684 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38104.963680 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32126.941549 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36262.720911 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35052.548527 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 38188.145684 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38104.963680 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32126.941549 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36262.720911 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 56526.199996 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 41391.104169 # average overall mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 130798.507463 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 103397.034445 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 103731.077147 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 119313.304315 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 119313.304315 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 130798.507463 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 111247.456361 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 111368.970315 # average overall mshr uncacheable latency
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.227681 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41427.194120 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 42816.625616 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 42000.330201 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 61725.447981 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 61725.447981 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31534.767177 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31534.767177 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19207.062102 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19207.062102 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 829199.800000 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 829199.800000 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46834.031226 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46834.031226 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31709.187167 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31709.187167 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 34078.669100 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34078.669100 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 47809.112331 # average InvalidateReq mshr miss latency
> system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 47809.112331 # average InvalidateReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41427.194120 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 42816.625616 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31709.187167 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36652.754938 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35194.853490 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41427.194120 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 42816.625616 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31709.187167 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36652.754938 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 61725.447981 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42949.626773 # average overall mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 136455.223881 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 157792.808589 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 157715.959791 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162796.257105 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162796.257105 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 136455.223881 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 160152.021440 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 160106.841012 # average overall mshr uncacheable latency
2924,2964c2946,2986
< system.cpu1.toL2Bus.snoop_filter.tot_requests 21246355 # Total number of requests made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10958434 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1131 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.snoop_filter.tot_snoops 1866438 # Total number of snoops made to the snoop filter.
< system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1866138 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 300 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu1.toL2Bus.trans_dist::ReadReq 825754 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 9752282 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 5284 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 5284 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackDirty 4201386 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WritebackClean 7090370 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::CleanEvict 2466487 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 905169 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 447608 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337242 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 479463 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 119 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 201 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 1130462 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 1058321 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5253902 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4579290 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateReq 402900 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateResp 396573 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15761317 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16025111 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 394044 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1160504 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 33340976 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 672467056 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 619232766 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1502776 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4371544 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 1297574142 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 6151657 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 17448758 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 0.126682 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.332668 # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_filter.tot_requests 22091106 # Total number of requests made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11384004 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1413 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.snoop_filter.tot_snoops 1936993 # Total number of snoops made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1936645 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 348 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.trans_dist::ReadReq 874786 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 10136227 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 16538 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 16538 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackDirty 4413805 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WritebackClean 7327056 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::CleanEvict 2612396 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 936034 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 441152 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 362021 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 491027 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 69 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 118 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 1142611 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 1118724 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5433664 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4777910 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateReq 490221 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateResp 429103 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16300596 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16818339 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 407716 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1217877 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 34744528 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 695476144 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 648316997 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1556520 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4598760 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 1349948421 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 6442205 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 18213720 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 0.125270 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.331082 # Request fanout histogram
2966,2968c2988,2990
< system.cpu1.toL2Bus.snoop_fanout::0 15238612 87.33% 87.33% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::1 2209846 12.66% 100.00% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::2 300 0.00% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::0 15932436 87.47% 87.47% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::1 2280936 12.52% 100.00% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 348 0.00% 100.00% # Request fanout histogram
2972,2973c2994,2995
< system.cpu1.toL2Bus.snoop_fanout::total 17448758 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 21067285470 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 18213720 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 21942621967 # Layer occupancy (ticks)
2975c2997
< system.cpu1.toL2Bus.snoopLayer0.occupancy 170823638 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 185589939 # Layer occupancy (ticks)
2977c2999
< system.cpu1.toL2Bus.respLayer0.occupancy 7886135987 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 8156255052 # Layer occupancy (ticks)
2979c3001
< system.cpu1.toL2Bus.respLayer1.occupancy 7380840948 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 7729530656 # Layer occupancy (ticks)
2981c3003
< system.cpu1.toL2Bus.respLayer2.occupancy 206620146 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer2.occupancy 213583628 # Layer occupancy (ticks)
2983c3005
< system.cpu1.toL2Bus.respLayer3.occupancy 614769571 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 643750548 # Layer occupancy (ticks)
2985,2989c3007,3011
< system.iobus.trans_dist::ReadReq 40283 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40283 # Transaction distribution
< system.iobus.trans_dist::WriteReq 136631 # Transaction distribution
< system.iobus.trans_dist::WriteResp 136631 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47650 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::ReadReq 40360 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40360 # Transaction distribution
> system.iobus.trans_dist::WriteReq 136653 # Transaction distribution
> system.iobus.trans_dist::WriteResp 136653 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47814 # Packet count per connected master and slave (bytes)
3000c3022
< system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
3002,3004c3024,3026
< system.iobus.pkt_count_system.bridge.master::total 122584 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231164 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 231164 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 122696 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231250 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 231250 # Packet count per connected master and slave (bytes)
3007,3008c3029,3030
< system.iobus.pkt_count::total 353828 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47670 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 354026 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47834 # Cumulative packet size per connected master and slave (bytes)
3019c3041
< system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
3021,3023c3043,3045
< system.iobus.pkt_size_system.bridge.master::total 155691 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338672 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7338672 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 155826 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339016 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7339016 # Cumulative packet size per connected master and slave (bytes)
3026,3027c3048,3049
< system.iobus.pkt_size::total 7496449 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 36944000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 7496928 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 37078503 # Layer occupancy (ticks)
3031c3053
< system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer2.occupancy 334500 # Layer occupancy (ticks)
3033c3055
< system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks)
3035c3057
< system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks)
3037c3059
< system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks)
3039c3061
< system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks)
3045c3067
< system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer16.occupancy 13500 # Layer occupancy (ticks)
3047c3069
< system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
---
> system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
3049c3071
< system.iobus.reqLayer23.occupancy 24787502 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 24630000 # Layer occupancy (ticks)
3051c3073
< system.iobus.reqLayer24.occupancy 36442000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer24.occupancy 36390000 # Layer occupancy (ticks)
3053c3075
< system.iobus.reqLayer25.occupancy 567400129 # Layer occupancy (ticks)
---
> system.iobus.reqLayer25.occupancy 567310169 # Layer occupancy (ticks)
3055c3077
< system.iobus.respLayer0.occupancy 92684000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 92774000 # Layer occupancy (ticks)
3057c3079
< system.iobus.respLayer3.occupancy 147860000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 147946000 # Layer occupancy (ticks)
3061,3062c3083,3084
< system.iocache.tags.replacements 115578 # number of replacements
< system.iocache.tags.tagsinuse 11.298905 # Cycle average of tags in use
---
> system.iocache.tags.replacements 115606 # number of replacements
> system.iocache.tags.tagsinuse 11.303294 # Cycle average of tags in use
3064c3086
< system.iocache.tags.sampled_refs 115594 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 115622 # Sample count of references to valid blocks.
3066,3071c3088,3093
< system.iocache.tags.warmup_cycle 9125697698000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ethernet 7.418105 # Average occupied blocks per requestor
< system.iocache.tags.occ_blocks::realview.ide 3.880800 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ethernet 0.463632 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::realview.ide 0.242550 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.706182 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 9121340835000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ethernet 3.838171 # Average occupied blocks per requestor
> system.iocache.tags.occ_blocks::realview.ide 7.465123 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ethernet 0.239886 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::realview.ide 0.466570 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.706456 # Average percentage of cache occupancy
3075,3076c3097,3098
< system.iocache.tags.tag_accesses 1040595 # Number of tag accesses
< system.iocache.tags.data_accesses 1040595 # Number of data accesses
---
> system.iocache.tags.tag_accesses 1040982 # Number of tag accesses
> system.iocache.tags.data_accesses 1040982 # Number of data accesses
3078,3079c3100,3101
< system.iocache.ReadReq_misses::realview.ide 8854 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8891 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8897 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8934 # number of ReadReq misses
3085,3086c3107,3108
< system.iocache.demand_misses::realview.ide 8854 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8894 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 8897 # number of demand (read+write) misses
> system.iocache.demand_misses::total 8937 # number of demand (read+write) misses
3088,3092c3110,3114
< system.iocache.overall_misses::realview.ide 8854 # number of overall misses
< system.iocache.overall_misses::total 8894 # number of overall misses
< system.iocache.ReadReq_miss_latency::realview.ethernet 5230500 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::realview.ide 1713293012 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 1718523512 # number of ReadReq miss cycles
---
> system.iocache.overall_misses::realview.ide 8897 # number of overall misses
> system.iocache.overall_misses::total 8937 # number of overall misses
> system.iocache.ReadReq_miss_latency::realview.ethernet 5248000 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::realview.ide 1663076066 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 1668324066 # number of ReadReq miss cycles
3095,3102c3117,3124
< system.iocache.WriteLineReq_miss_latency::realview.ide 13529785617 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 13529785617 # number of WriteLineReq miss cycles
< system.iocache.demand_miss_latency::realview.ethernet 5599500 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::realview.ide 1713293012 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1718892512 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::realview.ethernet 5599500 # number of overall miss cycles
< system.iocache.overall_miss_latency::realview.ide 1713293012 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1718892512 # number of overall miss cycles
---
> system.iocache.WriteLineReq_miss_latency::realview.ide 13545989103 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 13545989103 # number of WriteLineReq miss cycles
> system.iocache.demand_miss_latency::realview.ethernet 5617000 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::realview.ide 1663076066 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 1668693066 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::realview.ethernet 5617000 # number of overall miss cycles
> system.iocache.overall_miss_latency::realview.ide 1663076066 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 1668693066 # number of overall miss cycles
3104,3105c3126,3127
< system.iocache.ReadReq_accesses::realview.ide 8854 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8891 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8897 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8934 # number of ReadReq accesses(hits+misses)
3111,3112c3133,3134
< system.iocache.demand_accesses::realview.ide 8854 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8894 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 8897 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 8937 # number of demand (read+write) accesses
3114,3115c3136,3137
< system.iocache.overall_accesses::realview.ide 8854 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8894 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 8897 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 8937 # number of overall (read+write) accesses
3129,3131c3151,3153
< system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141364.864865 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::realview.ide 193504.970861 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 193287.989203 # average ReadReq miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141837.837838 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::realview.ide 186925.487917 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 186738.758227 # average ReadReq miss latency
3134,3142c3156,3164
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126768.848072 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 126768.848072 # average WriteLineReq miss latency
< system.iocache.demand_avg_miss_latency::realview.ethernet 139987.500000 # average overall miss latency
< system.iocache.demand_avg_miss_latency::realview.ide 193504.970861 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 193264.280639 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ethernet 139987.500000 # average overall miss latency
< system.iocache.overall_avg_miss_latency::realview.ide 193504.970861 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 193264.280639 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 34686 # number of cycles access was blocked
---
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126920.668456 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 126920.668456 # average WriteLineReq miss latency
> system.iocache.demand_avg_miss_latency::realview.ethernet 140425 # average overall miss latency
> system.iocache.demand_avg_miss_latency::realview.ide 186925.487917 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 186717.362202 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ethernet 140425 # average overall miss latency
> system.iocache.overall_avg_miss_latency::realview.ide 186925.487917 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 186717.362202 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 33278 # number of cycles access was blocked
3144c3166
< system.iocache.blocked::no_mshrs 3488 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3432 # number of cycles access was blocked
3146c3168
< system.iocache.avg_blocked_cycles::no_mshrs 9.944381 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 9.696387 # average number of cycles each access was blocked
3153,3154c3175,3176
< system.iocache.ReadReq_mshr_misses::realview.ide 8854 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 8891 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 8897 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 8934 # number of ReadReq MSHR misses
3160,3161c3182,3183
< system.iocache.demand_mshr_misses::realview.ide 8854 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8894 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 8897 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 8937 # number of demand (read+write) MSHR misses
3163,3167c3185,3189
< system.iocache.overall_mshr_misses::realview.ide 8854 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8894 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3380500 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 1270593012 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 1273973512 # number of ReadReq MSHR miss cycles
---
> system.iocache.overall_mshr_misses::realview.ide 8897 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 8937 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3398000 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 1218226066 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 1221624066 # number of ReadReq MSHR miss cycles
3170,3177c3192,3199
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8187257903 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 8187257903 # number of WriteLineReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ethernet 3599500 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::realview.ide 1270593012 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1274192512 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ethernet 3599500 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::realview.ide 1270593012 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1274192512 # number of overall MSHR miss cycles
---
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8203200483 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 8203200483 # number of WriteLineReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ethernet 3617000 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::realview.ide 1218226066 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 1221843066 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ethernet 3617000 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::realview.ide 1218226066 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 1221843066 # number of overall MSHR miss cycles
3191,3193c3213,3215
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91364.864865 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 143504.970861 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 143287.989203 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91837.837838 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136925.487917 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 136738.758227 # average ReadReq mshr miss latency
3196,3203c3218,3225
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76711.433766 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76711.433766 # average WriteLineReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89987.500000 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 143504.970861 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 143264.280639 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89987.500000 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 143504.970861 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 143264.280639 # average overall mshr miss latency
---
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76860.809563 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76860.809563 # average WriteLineReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90425 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 136925.487917 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 136717.362202 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90425 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 136925.487917 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 136717.362202 # average overall mshr miss latency
3205,3240c3227,3262
< system.l2c.tags.replacements 1550465 # number of replacements
< system.l2c.tags.tagsinuse 63029.233494 # Cycle average of tags in use
< system.l2c.tags.total_refs 6222316 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 1609843 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 3.865169 # Average number of references to valid blocks.
< system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.l2c.tags.occ_blocks::writebacks 21079.795710 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 246.485529 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 359.766358 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 4048.838393 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 9854.606144 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 15763.557433 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 96.147248 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 123.490081 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 3067.505167 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 4557.367994 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3831.673436 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.321652 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003761 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.005490 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.061780 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.150369 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.240533 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001467 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.itb.walker 0.001884 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.046806 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.069540 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.058467 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.961750 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 10787 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 260 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 48331 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::2 1394 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 453 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 8932 # Occupied blocks per task id
---
> system.l2c.tags.replacements 1667118 # number of replacements
> system.l2c.tags.tagsinuse 63361.638008 # Cycle average of tags in use
> system.l2c.tags.total_refs 6455366 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 1727204 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 3.737466 # Average number of references to valid blocks.
> system.l2c.tags.warmup_cycle 4891044000 # Cycle when the warmup percentage was hit.
> system.l2c.tags.occ_blocks::writebacks 22165.641734 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 239.050229 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 385.051566 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 4239.404809 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 8813.325361 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14013.639467 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 94.428510 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.itb.walker 121.397759 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 2981.044706 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 5621.582558 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4687.071308 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.338221 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003648 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.005875 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.064688 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.134481 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.213831 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001441 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.itb.walker 0.001852 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.045487 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.085779 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.071519 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.966822 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 9996 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 251 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 49839 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::2 1469 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 415 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 8111 # Occupied blocks per task id
3242,3513c3264,3553
< system.l2c.tags.age_task_id_blocks_1023::4 256 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 2970 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 5917 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 39033 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.164597 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.737473 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 79030194 # Number of tag accesses
< system.l2c.tags.data_accesses 79030194 # Number of data accesses
< system.l2c.WritebackDirty_hits::writebacks 2899125 # number of WritebackDirty hits
< system.l2c.WritebackDirty_hits::total 2899125 # number of WritebackDirty hits
< system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
< system.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits
< system.l2c.UpgradeReq_hits::cpu0.data 179542 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 131751 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 311293 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 44871 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 37587 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 82458 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 177447 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 158953 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 336400 # number of ReadExReq hits
< system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6841 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4759 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.inst 555678 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 657090 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 315358 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6220 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4455 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.inst 465798 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 550752 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 288275 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 2855226 # number of ReadSharedReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 6841 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 4759 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 555678 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 834537 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 315358 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 6220 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 4455 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 465798 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 709705 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 288275 # number of demand (read+write) hits
< system.l2c.demand_hits::total 3191626 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 6841 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 4759 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 555678 # number of overall hits
< system.l2c.overall_hits::cpu0.data 834537 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 315358 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 6220 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 4455 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 465798 # number of overall hits
< system.l2c.overall_hits::cpu1.data 709705 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 288275 # number of overall hits
< system.l2c.overall_hits::total 3191626 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 65170 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 60899 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 126069 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 13497 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 10880 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 24377 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 548373 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 111880 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 660253 # number of ReadExReq misses
< system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3162 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3066 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.inst 64369 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 165419 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 348485 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1778 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1336 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.inst 44941 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 109371 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 194769 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 936696 # number of ReadSharedReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 3162 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.itb.walker 3066 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.inst 64369 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 713792 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 348485 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 1778 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.itb.walker 1336 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 44941 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 221251 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 194769 # number of demand (read+write) misses
< system.l2c.demand_misses::total 1596949 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 3162 # number of overall misses
< system.l2c.overall_misses::cpu0.itb.walker 3066 # number of overall misses
< system.l2c.overall_misses::cpu0.inst 64369 # number of overall misses
< system.l2c.overall_misses::cpu0.data 713792 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 348485 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 1778 # number of overall misses
< system.l2c.overall_misses::cpu1.itb.walker 1336 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 44941 # number of overall misses
< system.l2c.overall_misses::cpu1.data 221251 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 194769 # number of overall misses
< system.l2c.overall_misses::total 1596949 # number of overall misses
< system.l2c.UpgradeReq_miss_latency::cpu0.data 1078165500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 1115927500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 2194093000 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 212502500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 171734000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 384236500 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 90582434499 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 16447344495 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 107029778994 # number of ReadExReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 446300000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 433489000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.inst 8809361002 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 23863415500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 62552488059 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 257684000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 192911000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6154592500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.data 15830077997 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 35289320152 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::total 153829639210 # number of ReadSharedReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 446300000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 433489000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 8809361002 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 114445849999 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 62552488059 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 257684000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.itb.walker 192911000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 6154592500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 32277422492 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 35289320152 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 260859418204 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 446300000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 433489000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 8809361002 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 114445849999 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 62552488059 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 257684000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.itb.walker 192911000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 6154592500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 32277422492 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 35289320152 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 260859418204 # number of overall miss cycles
< system.l2c.WritebackDirty_accesses::writebacks 2899125 # number of WritebackDirty accesses(hits+misses)
< system.l2c.WritebackDirty_accesses::total 2899125 # number of WritebackDirty accesses(hits+misses)
< system.l2c.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses)
< system.l2c.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 244712 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 192650 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 437362 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 58368 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 48467 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 106835 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 725820 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 270833 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 996653 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 10003 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7825 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.inst 620047 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 822509 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 663843 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 7998 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5791 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.inst 510739 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 660123 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 483044 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 3791922 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 10003 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 7825 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 620047 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 1548329 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 663843 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 7998 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 5791 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 510739 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 930956 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 483044 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 4788575 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 10003 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 7825 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 620047 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 1548329 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 663843 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 7998 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 5791 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 510739 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 930956 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 483044 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 4788575 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.266313 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.316112 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.288249 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.231240 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.224483 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.228174 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.755522 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.413096 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.662470 # miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.316105 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.391821 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.103813 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.201115 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.524951 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.222306 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.230703 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.087992 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.165683 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.403212 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.247024 # miss rate for ReadSharedReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.316105 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.391821 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.103813 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.461008 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.524951 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.222306 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.230703 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.087992 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.237660 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.403212 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.333491 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.316105 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.391821 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.103813 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.461008 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.524951 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.222306 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.230703 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.087992 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.237660 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.403212 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.333491 # miss rate for overall accesses
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16543.892896 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 18324.233567 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 17403.905798 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15744.424687 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15784.375000 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 15762.255405 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 165183.979698 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 147008.799562 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 162104.191869 # average ReadExReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 141144.845035 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141385.844749 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 136857.198372 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 144260.426553 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 179498.365953 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 144929.133858 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 144394.461078 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 136948.276629 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 144737.434942 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 181185.507714 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::total 164225.788527 # average ReadSharedReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 141144.845035 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 141385.844749 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 136857.198372 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 160335.013560 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 179498.365953 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 144929.133858 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.itb.walker 144394.461078 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 136948.276629 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 145885.995959 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 181185.507714 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 163348.621781 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 141144.845035 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141385.844749 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 136857.198372 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 160335.013560 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 179498.365953 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 144929.133858 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.itb.walker 144394.461078 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 136948.276629 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 145885.995959 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 181185.507714 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 163348.621781 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 8828 # number of cycles access was blocked
---
> system.l2c.tags.age_task_id_blocks_1023::4 247 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 2991 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 5625 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 40782 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.152527 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.003830 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.760483 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 82621731 # Number of tag accesses
> system.l2c.tags.data_accesses 82621731 # Number of data accesses
> system.l2c.WritebackDirty_hits::writebacks 3012753 # number of WritebackDirty hits
> system.l2c.WritebackDirty_hits::total 3012753 # number of WritebackDirty hits
> system.l2c.WritebackClean_hits::writebacks 2 # number of WritebackClean hits
> system.l2c.WritebackClean_hits::total 2 # number of WritebackClean hits
> system.l2c.UpgradeReq_hits::cpu0.data 188217 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 137513 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 325730 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 45011 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 38650 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 83661 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 56653 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 53670 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 110323 # number of ReadExReq hits
> system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6963 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4319 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.inst 567930 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 682126 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 295320 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6606 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4484 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.inst 500301 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 595581 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 300895 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 2964525 # number of ReadSharedReq hits
> system.l2c.InvalidateReq_hits::cpu0.data 123921 # number of InvalidateReq hits
> system.l2c.InvalidateReq_hits::cpu1.data 128483 # number of InvalidateReq hits
> system.l2c.InvalidateReq_hits::total 252404 # number of InvalidateReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 6963 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 4319 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 567930 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 738779 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 295320 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 6606 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 4484 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 500301 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 649251 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 300895 # number of demand (read+write) hits
> system.l2c.demand_hits::total 3074848 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 6963 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 4319 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 567930 # number of overall hits
> system.l2c.overall_hits::cpu0.data 738779 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 295320 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 6606 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 4484 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 500301 # number of overall hits
> system.l2c.overall_hits::cpu1.data 649251 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 300895 # number of overall hits
> system.l2c.overall_hits::total 3074848 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 63777 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 64352 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 128129 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 13748 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 11919 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 25667 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 97262 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 50904 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 148166 # number of ReadExReq misses
> system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3782 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3673 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.inst 64884 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 181110 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 386357 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2034 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1570 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.inst 45959 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 114229 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 215943 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 1019541 # number of ReadSharedReq misses
> system.l2c.InvalidateReq_misses::cpu0.data 509164 # number of InvalidateReq misses
> system.l2c.InvalidateReq_misses::cpu1.data 100519 # number of InvalidateReq misses
> system.l2c.InvalidateReq_misses::total 609683 # number of InvalidateReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 3782 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.itb.walker 3673 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.inst 64884 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 278372 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 386357 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 2034 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.itb.walker 1570 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 45959 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 165133 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 215943 # number of demand (read+write) misses
> system.l2c.demand_misses::total 1167707 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 3782 # number of overall misses
> system.l2c.overall_misses::cpu0.itb.walker 3673 # number of overall misses
> system.l2c.overall_misses::cpu0.inst 64884 # number of overall misses
> system.l2c.overall_misses::cpu0.data 278372 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 386357 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 2034 # number of overall misses
> system.l2c.overall_misses::cpu1.itb.walker 1570 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 45959 # number of overall misses
> system.l2c.overall_misses::cpu1.data 165133 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 215943 # number of overall misses
> system.l2c.overall_misses::total 1167707 # number of overall misses
> system.l2c.UpgradeReq_miss_latency::cpu0.data 1085442500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 1077777500 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 2163220000 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 211973500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 184474000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 396447500 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 13946644494 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 6989170497 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 20935814991 # number of ReadExReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 531173000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 521770500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.inst 8947284001 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 26625748999 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 72546834291 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 297030000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 228999000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6329750999 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.data 16747831000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 39888708640 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::total 172665130430 # number of ReadSharedReq miss cycles
> system.l2c.InvalidateReq_miss_latency::cpu0.data 156554500 # number of InvalidateReq miss cycles
> system.l2c.InvalidateReq_miss_latency::cpu1.data 157821500 # number of InvalidateReq miss cycles
> system.l2c.InvalidateReq_miss_latency::total 314376000 # number of InvalidateReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 531173000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 521770500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 8947284001 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 40572393493 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 72546834291 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 297030000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.itb.walker 228999000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 6329750999 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 23737001497 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 39888708640 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 193600945421 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 531173000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 521770500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 8947284001 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 40572393493 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 72546834291 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 297030000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.itb.walker 228999000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 6329750999 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 23737001497 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 39888708640 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 193600945421 # number of overall miss cycles
> system.l2c.WritebackDirty_accesses::writebacks 3012753 # number of WritebackDirty accesses(hits+misses)
> system.l2c.WritebackDirty_accesses::total 3012753 # number of WritebackDirty accesses(hits+misses)
> system.l2c.WritebackClean_accesses::writebacks 2 # number of WritebackClean accesses(hits+misses)
> system.l2c.WritebackClean_accesses::total 2 # number of WritebackClean accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 251994 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 201865 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 453859 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 58759 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 50569 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 109328 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 153915 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 104574 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 258489 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 10745 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7992 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.inst 632814 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 863236 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 681677 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8640 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6054 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.inst 546260 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 709810 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 516838 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 3984066 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.InvalidateReq_accesses::cpu0.data 633085 # number of InvalidateReq accesses(hits+misses)
> system.l2c.InvalidateReq_accesses::cpu1.data 229002 # number of InvalidateReq accesses(hits+misses)
> system.l2c.InvalidateReq_accesses::total 862087 # number of InvalidateReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 10745 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 7992 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 632814 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 1017151 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 681677 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 8640 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 6054 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 546260 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 814384 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 516838 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 4242555 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 10745 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 7992 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 632814 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 1017151 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 681677 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 8640 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 6054 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 546260 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 814384 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 516838 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 4242555 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.253089 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.318787 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.282310 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.233973 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.235698 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.234771 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.631920 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.486775 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.573200 # miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.351978 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.459585 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.102532 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.209804 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.566774 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.235417 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.259333 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.084134 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.160929 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.417816 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.255905 # miss rate for ReadSharedReq accesses
> system.l2c.InvalidateReq_miss_rate::cpu0.data 0.804259 # miss rate for InvalidateReq accesses
> system.l2c.InvalidateReq_miss_rate::cpu1.data 0.438944 # miss rate for InvalidateReq accesses
> system.l2c.InvalidateReq_miss_rate::total 0.707217 # miss rate for InvalidateReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.351978 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.459585 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.102532 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.273678 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.566774 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.235417 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.259333 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.084134 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.202770 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.417816 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.275237 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.351978 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.459585 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.102532 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.273678 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.566774 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.235417 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.259333 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.084134 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.202770 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.417816 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.275237 # miss rate for overall accesses
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17019.340828 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16748.158565 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 16883.141209 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15418.497236 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15477.305143 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 15445.805899 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 143392.532479 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 137301.007720 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 141299.724572 # average ReadExReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140447.646748 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 142055.676559 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 137896.615514 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 147014.239959 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 187771.502240 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 146032.448378 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 145859.235669 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137726.038404 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 146616.279579 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 184718.692618 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::total 169355.749725 # average ReadSharedReq miss latency
> system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 307.473623 # average InvalidateReq miss latency
> system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 1570.066356 # average InvalidateReq miss latency
> system.l2c.InvalidateReq_avg_miss_latency::total 515.638455 # average InvalidateReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140447.646748 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 142055.676559 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 137896.615514 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 145748.830676 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 187771.502240 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 146032.448378 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.itb.walker 145859.235669 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 137726.038404 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 143744.748155 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 184718.692618 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 165795.824998 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140447.646748 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 142055.676559 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 137896.615514 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 145748.830676 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 187771.502240 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 146032.448378 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.itb.walker 145859.235669 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 137726.038404 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 143744.748155 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 184718.692618 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 165795.824998 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 16571 # number of cycles access was blocked
3515c3555
< system.l2c.blocked::no_mshrs 81 # number of cycles access was blocked
---
> system.l2c.blocked::no_mshrs 157 # number of cycles access was blocked
3517c3557
< system.l2c.avg_blocked_cycles::no_mshrs 108.987654 # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs 105.547771 # average number of cycles each access was blocked
3521,3587c3561,3627
< system.l2c.writebacks::writebacks 1227229 # number of writebacks
< system.l2c.writebacks::total 1227229 # number of writebacks
< system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 139 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu0.data 160 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 80 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 236 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.data 179 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 178 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::total 972 # number of ReadSharedReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 139 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu0.data 160 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 80 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 236 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.data 179 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 178 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 972 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 139 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu0.data 160 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 80 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 236 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.data 179 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 178 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 972 # number of overall MSHR hits
< system.l2c.CleanEvict_mshr_misses::writebacks 61997 # number of CleanEvict MSHR misses
< system.l2c.CleanEvict_mshr_misses::total 61997 # number of CleanEvict MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 65170 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 60899 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 126069 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 13497 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 10880 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 24377 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 548373 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 111880 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 660253 # number of ReadExReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 3162 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3066 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 64230 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.data 165259 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 348405 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1778 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1336 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 44705 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.data 109192 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 194591 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::total 935724 # number of ReadSharedReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 3162 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.itb.walker 3066 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 64230 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 713632 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 348405 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 1778 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.itb.walker 1336 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 44705 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 221072 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 194591 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 1595977 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 3162 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.itb.walker 3066 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 64230 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 713632 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 348405 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 1778 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.itb.walker 1336 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 44705 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 221072 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 194591 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 1595977 # number of overall MSHR misses
---
> system.l2c.writebacks::writebacks 1320441 # number of writebacks
> system.l2c.writebacks::total 1320441 # number of writebacks
> system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 157 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu0.data 33 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 2 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 231 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.data 20 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::total 443 # number of ReadSharedReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 157 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu0.data 33 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 2 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 231 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.data 20 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 443 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 157 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu0.data 33 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 2 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 231 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.data 20 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 443 # number of overall MSHR hits
> system.l2c.CleanEvict_mshr_misses::writebacks 61724 # number of CleanEvict MSHR misses
> system.l2c.CleanEvict_mshr_misses::total 61724 # number of CleanEvict MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 63777 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 64352 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 128129 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 13748 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11919 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 25667 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 97262 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 50904 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 148166 # number of ReadExReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 3782 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3673 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 64727 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.data 181077 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 386355 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2034 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1570 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 45728 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.data 114209 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 215943 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::total 1019098 # number of ReadSharedReq MSHR misses
> system.l2c.InvalidateReq_mshr_misses::cpu0.data 509164 # number of InvalidateReq MSHR misses
> system.l2c.InvalidateReq_mshr_misses::cpu1.data 100519 # number of InvalidateReq MSHR misses
> system.l2c.InvalidateReq_mshr_misses::total 609683 # number of InvalidateReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 3782 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.itb.walker 3673 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 64727 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 278339 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 386355 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 2034 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.itb.walker 1570 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 45728 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 165113 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 215943 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 1167264 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 3782 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.itb.walker 3673 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 64727 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 278339 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 386355 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 2034 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.itb.walker 1570 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 45728 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 165113 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 215943 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 1167264 # number of overall MSHR misses
3589c3629
< system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32878 # number of ReadReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 19715 # number of ReadReq MSHR uncacheable
3591,3595c3631,3635
< system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5427 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::total 59665 # number of ReadReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu0.data 32941 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5284 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::total 38225 # number of WriteReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 18534 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 59609 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 21606 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 16538 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 38144 # number of WriteReq MSHR uncacheable
3597c3637
< system.l2c.overall_mshr_uncacheable_misses::cpu0.data 65819 # number of overall MSHR uncacheable misses
---
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 41321 # number of overall MSHR uncacheable misses
3599,3642c3639,3685
< system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10711 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::total 97890 # number of overall MSHR uncacheable misses
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4609555998 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4294868996 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 8904424994 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 994851497 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 800175997 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 1795027494 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 85098254939 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 15328209809 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 100426464748 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 414677007 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 402825012 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 8150526337 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 22190089460 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 59056286181 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 239897519 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 179549008 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5679666806 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 14716146780 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 33314353434 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::total 144344017544 # number of ReadSharedReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 414677007 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 402825012 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 8150526337 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 107288344399 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 59056286181 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 239897519 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 179549008 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 5679666806 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 30044356589 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 33314353434 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 244770482292 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 414677007 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 402825012 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 8150526337 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 107288344399 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 59056286181 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 239897519 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 179549008 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 5679666806 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 30044356589 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 33314353434 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 244770482292 # number of overall MSHR miss cycles
---
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 35072 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 97753 # number of overall MSHR uncacheable misses
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4492995997 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4553517493 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 9046513490 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1012323996 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 878323498 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 1890647494 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 12973565718 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 6479663163 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 19453228881 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 493342025 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 485033021 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 8280831088 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 24810050267 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 68681605136 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 276676038 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 213289522 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5842963029 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 15602405986 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 37727707488 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::total 162413903600 # number of ReadSharedReq MSHR miss cycles
> system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 35699174001 # number of InvalidateReq MSHR miss cycles
> system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 7062172000 # number of InvalidateReq MSHR miss cycles
> system.l2c.InvalidateReq_mshr_miss_latency::total 42761346001 # number of InvalidateReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 493342025 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 485033021 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 8280831088 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 37783615985 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 68681605136 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 276676038 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 213289522 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 5842963029 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 22082069149 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 37727707488 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 181867132481 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 493342025 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 485033021 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 8280831088 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 37783615985 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 68681605136 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 276676038 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 213289522 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 5842963029 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 22082069149 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 37727707488 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 181867132481 # number of overall MSHR miss cycles
3644,3650c3687,3693
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5437993027 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7557000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 463514024 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 8305872051 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 5417020065 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 540285518 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 5957305583 # number of WriteReq MSHR uncacheable cycles
---
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3316765536 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7936000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2591094528 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 8312604064 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3549490576 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2410843031 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 5960333607 # number of WriteReq MSHR uncacheable cycles
3652,3655c3695,3698
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10855013092 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7557000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1003799542 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 14263177634 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6866256112 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7936000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5001937559 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 14272937671 # number of overall MSHR uncacheable cycles
3658,3741c3701,3790
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.266313 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.316112 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.288249 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.231240 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.224483 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.228174 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.755522 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.413096 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.662470 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.316105 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.391821 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.103589 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.200921 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.524830 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.222306 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.230703 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.087530 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.165412 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402843 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::total 0.246768 # mshr miss rate for ReadSharedReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.316105 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.391821 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.103589 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.460905 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.524830 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.222306 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.230703 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.087530 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.237468 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402843 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.333289 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.316105 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.391821 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.103589 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.460905 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.524830 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.222306 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.230703 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.087530 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.237468 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402843 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.333289 # mshr miss rate for overall accesses
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70731.256683 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70524.458464 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70631.360557 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73709.083278 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73545.587960 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73636.111663 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 155183.159891 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 137005.808089 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 152103.004073 # average ReadExReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 131143.898482 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131384.544031 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 126895.941725 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 134274.620202 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169504.703380 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 134925.488751 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 134392.970060 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127047.686075 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 134773.122390 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171201.923182 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 154259.180639 # average ReadSharedReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 131143.898482 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131384.544031 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 126895.941725 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 150341.274493 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169504.703380 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 134925.488751 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 134392.970060 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127047.686075 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 135903.038779 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171201.923182 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 153367.174021 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131143.898482 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131384.544031 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 126895.941725 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 150341.274493 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169504.703380 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 134925.488751 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 134392.970060 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127047.686075 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 135903.038779 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171201.923182 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 153367.174021 # average overall mshr miss latency
---
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.253089 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.318787 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.282310 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.233973 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.235698 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.234771 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.631920 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.486775 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.573200 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.351978 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.459585 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.102284 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.209765 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.566771 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.235417 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.259333 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.083711 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.160901 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.417816 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::total 0.255793 # mshr miss rate for ReadSharedReq accesses
> system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.804259 # mshr miss rate for InvalidateReq accesses
> system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.438944 # mshr miss rate for InvalidateReq accesses
> system.l2c.InvalidateReq_mshr_miss_rate::total 0.707217 # mshr miss rate for InvalidateReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.351978 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.459585 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102284 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.273646 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.566771 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.235417 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.259333 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.083711 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.202746 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.417816 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.275132 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.351978 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.459585 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102284 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.273646 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.566771 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.235417 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.259333 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.083711 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.202746 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.417816 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.275132 # mshr miss rate for overall accesses
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70448.531555 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70759.533394 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70604.730311 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73634.273785 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73691.039349 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73660.634044 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 133387.815570 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 127291.827027 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 131293.474083 # average ReadExReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130444.744844 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 132053.640348 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127934.727208 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 137013.813278 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177768.128110 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 136025.584071 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 135853.198726 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127776.483314 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 136612.753688 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174711.416846 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 159370.250555 # average ReadSharedReq mshr miss latency
> system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70113.311234 # average InvalidateReq mshr miss latency
> system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 70257.085725 # average InvalidateReq mshr miss latency
> system.l2c.InvalidateReq_avg_mshr_miss_latency::total 70137.015467 # average InvalidateReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130444.744844 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 132053.640348 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127934.727208 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135746.754803 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177768.128110 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 136025.584071 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 135853.198726 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127776.483314 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 133739.131074 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174711.416846 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 155806.340709 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130444.744844 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 132053.640348 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127934.727208 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135746.754803 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177768.128110 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 136025.584071 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 135853.198726 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127776.483314 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 133739.131074 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174711.416846 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 155806.340709 # average overall mshr miss latency
3743,3749c3792,3798
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165399.143105 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112791.044776 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 85408.885941 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 139208.448018 # average ReadReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164446.132935 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 102249.341030 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155848.412897 # average WriteReq mshr uncacheable latency
---
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168235.634593 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 118447.761194 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 139802.229848 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 139452.164338 # average ReadReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164282.633343 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145775.972367 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156258.745989 # average WriteReq mshr uncacheable latency
3751,3754c3800,3803
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164922.181923 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112791.044776 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 93716.697040 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 145706.176668 # average overall mshr uncacheable latency
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 166168.682074 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 118447.761194 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 142619.113794 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 146010.226499 # average overall mshr uncacheable latency
3756,3763c3805,3812
< system.membus.trans_dist::ReadReq 59665 # Transaction distribution
< system.membus.trans_dist::ReadResp 1004280 # Transaction distribution
< system.membus.trans_dist::WriteReq 38225 # Transaction distribution
< system.membus.trans_dist::WriteResp 38225 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 1333923 # Transaction distribution
< system.membus.trans_dist::CleanEvict 260984 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 453995 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 297100 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 59609 # Transaction distribution
> system.membus.trans_dist::ReadResp 1087641 # Transaction distribution
> system.membus.trans_dist::WriteReq 38144 # Transaction distribution
> system.membus.trans_dist::WriteResp 38144 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 1427135 # Transaction distribution
> system.membus.trans_dist::CleanEvict 277667 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 445891 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 321137 # Transaction distribution
3765,3770c3814,3819
< system.membus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution
< system.membus.trans_dist::ReadExReq 671706 # Transaction distribution
< system.membus.trans_dist::ReadExResp 651282 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 944615 # Transaction distribution
< system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes)
---
> system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
> system.membus.trans_dist::ReadExReq 156981 # Transaction distribution
> system.membus.trans_dist::ReadExResp 142959 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 1028032 # Transaction distribution
> system.membus.trans_dist::InvalidateReq 712467 # Transaction distribution
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122696 # Packet count per connected master and slave (bytes)
3772,3778c3821,3827
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25256 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5471994 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 5619910 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238072 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 238072 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 5857982 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155691 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24870 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5347246 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 5494888 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237811 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 237811 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 5732699 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155826 # Cumulative packet size per connected master and slave (bytes)
3780,3787c3829,3836
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50512 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 180426240 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 180632999 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7268224 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 7268224 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 187901223 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 614880 # Total snoops (count)
< system.membus.snoop_fanout::samples 4166995 # Request fanout histogram
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49740 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159196224 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 159402346 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7246976 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 7246976 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 166649322 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 621233 # Total snoops (count)
> system.membus.snoop_fanout::samples 4467120 # Request fanout histogram
3792c3841
< system.membus.snoop_fanout::1 4166995 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 4467120 100.00% 100.00% # Request fanout histogram
3797,3798c3846,3847
< system.membus.snoop_fanout::total 4166995 # Request fanout histogram
< system.membus.reqLayer0.occupancy 98592998 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 4467120 # Request fanout histogram
> system.membus.reqLayer0.occupancy 98530997 # Layer occupancy (ticks)
3802c3851
< system.membus.reqLayer2.occupancy 21315973 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 20867984 # Layer occupancy (ticks)
3804c3853
< system.membus.reqLayer5.occupancy 9342770498 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 9912231208 # Layer occupancy (ticks)
3806c3855
< system.membus.respLayer2.occupancy 8446463151 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 6259994034 # Layer occupancy (ticks)
3808c3857
< system.membus.respLayer3.occupancy 45344986 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 45597361 # Layer occupancy (ticks)
3862,3893c3911,3943
< system.toL2Bus.snoop_filter.tot_requests 12162467 # Total number of requests made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_requests 6606326 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_requests 1941011 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.snoop_filter.tot_snoops 162574 # Total number of snoops made to the snoop filter.
< system.toL2Bus.snoop_filter.hit_single_snoops 148386 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.toL2Bus.snoop_filter.hit_multi_snoops 14188 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.toL2Bus.trans_dist::ReadReq 59667 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 4643440 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 38225 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 38225 # Transaction distribution
< system.toL2Bus.trans_dist::WritebackDirty 4233094 # Transaction distribution
< system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 2736996 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 756317 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 379558 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 1135875 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 201 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 201 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 1140134 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 1140134 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 4591007 # Transaction distribution
< system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10341744 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7350795 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 17692539 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 299067465 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 193620382 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 492687847 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 3308925 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 8737988 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 0.345814 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.479035 # Request fanout histogram
---
> system.toL2Bus.snoop_filter.tot_requests 12663754 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 6874752 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 2026071 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.snoop_filter.tot_snoops 169438 # Total number of snoops made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_snoops 153466 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_snoops 15972 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.trans_dist::ReadReq 59611 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 4844529 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 38144 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 38144 # Transaction distribution
> system.toL2Bus.trans_dist::WritebackDirty 4439938 # Transaction distribution
> system.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 2880952 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 762470 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 404798 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 1167268 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 118 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 118 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 311901 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 311901 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 4792157 # Transaction distribution
> system.toL2Bus.trans_dist::InvalidateReq 968815 # Transaction distribution
> system.toL2Bus.trans_dist::InvalidateResp 862087 # Transaction distribution
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10699681 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7828066 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 18527747 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 272166853 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 192849765 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 465016618 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 3356905 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 9121086 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 0.343228 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.478461 # Request fanout histogram
3895,3897c3945,3947
< system.toL2Bus.snoop_fanout::0 5730454 65.58% 65.58% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 2993346 34.26% 99.84% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 14188 0.16% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 6006442 65.85% 65.85% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 3098672 33.97% 99.82% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 15972 0.18% 100.00% # Request fanout histogram
3901,3902c3951,3952
< system.toL2Bus.snoop_fanout::total 8737988 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 9497901955 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 9121086 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 9875342461 # Layer occupancy (ticks)
3904c3954
< system.toL2Bus.snoopLayer0.occupancy 2589298 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 2628126 # Layer occupancy (ticks)
3906c3956
< system.toL2Bus.respLayer0.occupancy 5324917465 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 4863215068 # Layer occupancy (ticks)
3908c3958
< system.toL2Bus.respLayer1.occupancy 3923923162 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 3891669395 # Layer occupancy (ticks)
3911c3961
< system.cpu0.kern.inst.quiesce 12950 # number of quiesce instructions executed
---
> system.cpu0.kern.inst.quiesce 5261 # number of quiesce instructions executed
3913c3963
< system.cpu1.kern.inst.quiesce 5465 # number of quiesce instructions executed
---
> system.cpu1.kern.inst.quiesce 13576 # number of quiesce instructions executed