Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt

Deleted Added

sdiff udiff text old ( 11103:38f6188421e0 ) new ( 11138:a611a23c8cc2 )

full compact

3,5c3,5
< sim_seconds 47.309815 # Number of seconds simulated
< sim_ticks 47309815475000 # Number of ticks simulated
< final_tick 47309815475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 47.434893 # Number of seconds simulated
> sim_ticks 47434893411000 # Number of ticks simulated
> final_tick 47434893411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 80227 # Simulator instruction rate (inst/s)
< host_op_rate 94350 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 4125416978 # Simulator tick rate (ticks/s)
< host_mem_usage 770696 # Number of bytes of host memory used
< host_seconds 11467.89 # Real time elapsed on the host
< sim_insts 920033396 # Number of instructions simulated
< sim_ops 1081995375 # Number of ops (including micro ops) simulated
---
> host_inst_rate 99639 # Simulator instruction rate (inst/s)
> host_op_rate 117176 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 5152463712 # Simulator tick rate (ticks/s)
> host_mem_usage 784704 # Number of bytes of host memory used
> host_seconds 9206.25 # Real time elapsed on the host
> sim_insts 917301737 # Number of instructions simulated
> sim_ops 1078753903 # Number of ops (including micro ops) simulated
16,31c16,31
< system.physmem.bytes_read::cpu0.dtb.walker 174848 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.itb.walker 152512 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.inst 4545760 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.data 43325128 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu0.l2cache.prefetcher 19040640 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.dtb.walker 136192 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.itb.walker 127232 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.inst 2550688 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.data 17518992 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu1.l2cache.prefetcher 15564544 # Number of bytes read from this memory
< system.physmem.bytes_read::realview.ide 439744 # Number of bytes read from this memory
< system.physmem.bytes_read::total 103576280 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu0.inst 4545760 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::cpu1.inst 2550688 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 7096448 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 86607680 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu0.dtb.walker 208192 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.itb.walker 203648 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.inst 4658336 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.data 45847432 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu0.l2cache.prefetcher 22095168 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.dtb.walker 91328 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.itb.walker 66368 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.inst 2323808 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.data 12264528 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu1.l2cache.prefetcher 10934912 # Number of bytes read from this memory
> system.physmem.bytes_read::realview.ide 422080 # Number of bytes read from this memory
> system.physmem.bytes_read::total 99115800 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu0.inst 4658336 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::cpu1.inst 2323808 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 6982144 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 83002560 # Number of bytes written to this memory
34,47c34,47
< system.physmem.bytes_written::total 86628264 # Number of bytes written to this memory
< system.physmem.num_reads::cpu0.dtb.walker 2732 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.itb.walker 2383 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.inst 86980 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.data 676968 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu0.l2cache.prefetcher 297510 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.dtb.walker 2128 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.itb.walker 1988 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.inst 39898 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.data 273747 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu1.l2cache.prefetcher 243196 # Number of read requests responded to by this memory
< system.physmem.num_reads::realview.ide 6871 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1634401 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1353245 # Number of write requests responded to by this memory
---
> system.physmem.bytes_written::total 83023144 # Number of bytes written to this memory
> system.physmem.num_reads::cpu0.dtb.walker 3253 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.itb.walker 3182 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.inst 88739 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.data 716379 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu0.l2cache.prefetcher 345237 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.dtb.walker 1427 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.itb.walker 1037 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.inst 36353 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.data 191646 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu1.l2cache.prefetcher 170858 # Number of read requests responded to by this memory
> system.physmem.num_reads::realview.ide 6595 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 1564706 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1296915 # Number of write requests responded to by this memory
50,67c50,67
< system.physmem.num_writes::total 1355819 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu0.dtb.walker 3696 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.itb.walker 3224 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.inst 96085 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.data 915775 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu0.l2cache.prefetcher 402467 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.dtb.walker 2879 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.itb.walker 2689 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.inst 53915 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.data 370304 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu1.l2cache.prefetcher 328992 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::realview.ide 9295 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2189319 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu0.inst 96085 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu1.inst 53915 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 149999 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1830649 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
---
> system.physmem.num_writes::total 1299489 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu0.dtb.walker 4389 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.itb.walker 4293 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.inst 98205 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.data 966534 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu0.l2cache.prefetcher 465800 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.dtb.walker 1925 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.itb.walker 1399 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.inst 48989 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.data 258555 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu1.l2cache.prefetcher 230525 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::realview.ide 8898 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2089512 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu0.inst 98205 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu1.inst 48989 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 147194 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1749821 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
69,92c69,92
< system.physmem.bw_write::total 1831084 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1830649 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.dtb.walker 3696 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.itb.walker 3224 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.inst 96085 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.data 916210 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu0.l2cache.prefetcher 402467 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.dtb.walker 2879 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.itb.walker 2689 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.inst 53915 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.data 370304 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu1.l2cache.prefetcher 328992 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::realview.ide 9295 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 4020403 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 1634401 # Number of read requests accepted
< system.physmem.writeReqs 1355819 # Number of write requests accepted
< system.physmem.readBursts 1634401 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1355819 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 104570688 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 30976 # Total number of bytes read from write queue
< system.physmem.bytesWritten 86627008 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 103576280 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 86628264 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 484 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_write::total 1750255 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1749821 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.dtb.walker 4389 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.itb.walker 4293 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.inst 98205 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.data 966968 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu0.l2cache.prefetcher 465800 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.dtb.walker 1925 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.itb.walker 1399 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.inst 48989 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.data 258555 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu1.l2cache.prefetcher 230525 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::realview.ide 8898 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3839767 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 1564706 # Number of read requests accepted
> system.physmem.writeReqs 1299489 # Number of write requests accepted
> system.physmem.readBursts 1564706 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1299489 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 100111296 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 29888 # Total number of bytes read from write queue
> system.physmem.bytesWritten 83021568 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 99115800 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 83023144 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 467 # Number of DRAM read bursts serviced by the write queue
94,126c94,126
< system.physmem.neitherReadNorWriteReqs 224542 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 101664 # Per bank write bursts
< system.physmem.perBankRdBursts::1 108898 # Per bank write bursts
< system.physmem.perBankRdBursts::2 93497 # Per bank write bursts
< system.physmem.perBankRdBursts::3 100406 # Per bank write bursts
< system.physmem.perBankRdBursts::4 99202 # Per bank write bursts
< system.physmem.perBankRdBursts::5 111502 # Per bank write bursts
< system.physmem.perBankRdBursts::6 102695 # Per bank write bursts
< system.physmem.perBankRdBursts::7 105017 # Per bank write bursts
< system.physmem.perBankRdBursts::8 95660 # Per bank write bursts
< system.physmem.perBankRdBursts::9 119055 # Per bank write bursts
< system.physmem.perBankRdBursts::10 95976 # Per bank write bursts
< system.physmem.perBankRdBursts::11 99461 # Per bank write bursts
< system.physmem.perBankRdBursts::12 97685 # Per bank write bursts
< system.physmem.perBankRdBursts::13 98791 # Per bank write bursts
< system.physmem.perBankRdBursts::14 102404 # Per bank write bursts
< system.physmem.perBankRdBursts::15 102004 # Per bank write bursts
< system.physmem.perBankWrBursts::0 83138 # Per bank write bursts
< system.physmem.perBankWrBursts::1 88505 # Per bank write bursts
< system.physmem.perBankWrBursts::2 79517 # Per bank write bursts
< system.physmem.perBankWrBursts::3 83751 # Per bank write bursts
< system.physmem.perBankWrBursts::4 82730 # Per bank write bursts
< system.physmem.perBankWrBursts::5 91993 # Per bank write bursts
< system.physmem.perBankWrBursts::6 85763 # Per bank write bursts
< system.physmem.perBankWrBursts::7 87476 # Per bank write bursts
< system.physmem.perBankWrBursts::8 80354 # Per bank write bursts
< system.physmem.perBankWrBursts::9 84626 # Per bank write bursts
< system.physmem.perBankWrBursts::10 82451 # Per bank write bursts
< system.physmem.perBankWrBursts::11 83951 # Per bank write bursts
< system.physmem.perBankWrBursts::12 82076 # Per bank write bursts
< system.physmem.perBankWrBursts::13 85332 # Per bank write bursts
< system.physmem.perBankWrBursts::14 85178 # Per bank write bursts
< system.physmem.perBankWrBursts::15 86706 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 228681 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 96105 # Per bank write bursts
> system.physmem.perBankRdBursts::1 104079 # Per bank write bursts
> system.physmem.perBankRdBursts::2 99076 # Per bank write bursts
> system.physmem.perBankRdBursts::3 102555 # Per bank write bursts
> system.physmem.perBankRdBursts::4 95026 # Per bank write bursts
> system.physmem.perBankRdBursts::5 98411 # Per bank write bursts
> system.physmem.perBankRdBursts::6 98571 # Per bank write bursts
> system.physmem.perBankRdBursts::7 95349 # Per bank write bursts
> system.physmem.perBankRdBursts::8 90083 # Per bank write bursts
> system.physmem.perBankRdBursts::9 124090 # Per bank write bursts
> system.physmem.perBankRdBursts::10 93867 # Per bank write bursts
> system.physmem.perBankRdBursts::11 97434 # Per bank write bursts
> system.physmem.perBankRdBursts::12 91060 # Per bank write bursts
> system.physmem.perBankRdBursts::13 95554 # Per bank write bursts
> system.physmem.perBankRdBursts::14 90000 # Per bank write bursts
> system.physmem.perBankRdBursts::15 92979 # Per bank write bursts
> system.physmem.perBankWrBursts::0 80467 # Per bank write bursts
> system.physmem.perBankWrBursts::1 87240 # Per bank write bursts
> system.physmem.perBankWrBursts::2 82424 # Per bank write bursts
> system.physmem.perBankWrBursts::3 84720 # Per bank write bursts
> system.physmem.perBankWrBursts::4 78521 # Per bank write bursts
> system.physmem.perBankWrBursts::5 82917 # Per bank write bursts
> system.physmem.perBankWrBursts::6 81751 # Per bank write bursts
> system.physmem.perBankWrBursts::7 80612 # Per bank write bursts
> system.physmem.perBankWrBursts::8 77294 # Per bank write bursts
> system.physmem.perBankWrBursts::9 85251 # Per bank write bursts
> system.physmem.perBankWrBursts::10 78271 # Per bank write bursts
> system.physmem.perBankWrBursts::11 81127 # Per bank write bursts
> system.physmem.perBankWrBursts::12 78007 # Per bank write bursts
> system.physmem.perBankWrBursts::13 81137 # Per bank write bursts
> system.physmem.perBankWrBursts::14 77706 # Per bank write bursts
> system.physmem.perBankWrBursts::15 79767 # Per bank write bursts
128,129c128,129
< system.physmem.numWrRetry 54 # Number of times write queue was full causing retry
< system.physmem.totGap 47309813973500 # Total gap between requests
---
> system.physmem.numWrRetry 33 # Number of times write queue was full causing retry
> system.physmem.totGap 47434891912500 # Total gap between requests
136c136
< system.physmem.readPktSize::6 1613043 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 1543348 # Read request sizes (log2)
143,155c143,155
< system.physmem.writePktSize::6 1353245 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 578892 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 412924 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 179105 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 178845 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 107013 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 63608 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 33748 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 30706 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 27701 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 8546 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 4578 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 2741 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1296915 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 588411 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 392193 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 156445 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 159831 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 99518 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 60251 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 31814 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 29617 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 26249 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 7312 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 4196 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 2603 # What read queue length does an incoming req see
157,166c157,166
< system.physmem.rdQLenPdf::13 1308 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 831 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 574 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 473 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 388 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 147 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 94 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 12 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::13 1352 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 882 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 666 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 550 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 422 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 135 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 91 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see
191,257c191,258
< system.physmem.wrQLenPdf::15 19221 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 22339 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 35019 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 41881 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 50025 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 59082 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 67725 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 77253 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 82334 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 88348 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 89969 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 94025 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 94875 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 99373 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 112446 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 104983 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 99994 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 89665 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 6823 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 3907 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 2408 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 1575 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 1140 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 893 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 774 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 745 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 621 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 501 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 484 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 393 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 396 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 376 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 359 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 315 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 321 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 285 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 333 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 272 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 303 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 294 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 305 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 202 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 154 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 161 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 136 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 118 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 151 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 110 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 146 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 1028414 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 185.914855 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 114.442896 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 243.413322 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 618503 60.14% 60.14% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 202037 19.65% 79.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 65034 6.32% 86.11% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 35244 3.43% 89.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 24806 2.41% 91.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 13355 1.30% 93.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 14362 1.40% 94.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 8867 0.86% 95.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 46206 4.49% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1028414 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 77347 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 21.124284 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 260.957500 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-4095 77345 100.00% 100.00% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 18951 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 21518 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 33036 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 40734 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 49908 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 58222 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 67476 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 73957 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 80711 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 84361 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 87259 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 93166 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 91933 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 94699 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 106371 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 99156 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 93223 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 82575 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 5494 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 3221 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 1939 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 1368 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 895 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 681 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 468 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 468 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 374 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 431 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 286 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 340 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 277 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 294 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 350 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 319 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 389 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 266 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 263 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 246 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 271 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 255 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 225 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 177 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 138 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 101 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 113 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 78 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 101 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 75 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 69 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 977888 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 187.273406 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 115.248079 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 243.900483 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 583799 59.70% 59.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 193375 19.77% 79.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 62560 6.40% 85.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 34177 3.49% 89.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 24599 2.52% 91.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 13672 1.40% 93.28% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 13781 1.41% 94.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 7457 0.76% 95.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 44468 4.55% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 977888 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 73621 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 21.246927 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 254.221432 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-4095 73618 100.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
259,296c260,296
< system.physmem.rdPerTurnAround::69632-73727 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 77347 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 77347 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.499670 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.056595 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 6.288618 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 72278 93.45% 93.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 2489 3.22% 96.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 567 0.73% 97.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 275 0.36% 97.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 300 0.39% 98.14% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 491 0.63% 98.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 126 0.16% 98.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 49 0.06% 99.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 40 0.05% 99.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 44 0.06% 99.11% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 35 0.05% 99.16% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 27 0.03% 99.19% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 405 0.52% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 43 0.06% 99.77% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 50 0.06% 99.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 52 0.07% 99.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 16 0.02% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 1 0.00% 99.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 3 0.00% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 4 0.01% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 23 0.03% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::136-139 2 0.00% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::148-151 8 0.01% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::164-167 5 0.01% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::176-179 3 0.00% 100.00% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::65536-69631 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 73621 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 73621 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.620136 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.126079 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 6.628572 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 68415 92.93% 92.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 2834 3.85% 96.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 416 0.57% 97.34% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 328 0.45% 97.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 84 0.11% 97.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 303 0.41% 98.31% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 179 0.24% 98.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 107 0.15% 98.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 91 0.12% 98.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 122 0.17% 98.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 36 0.05% 99.04% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 46 0.06% 99.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 419 0.57% 99.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 29 0.04% 99.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 25 0.03% 99.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 117 0.16% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 10 0.01% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 2 0.00% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 4 0.01% 99.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 5 0.01% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 3 0.00% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 2 0.00% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 27 0.04% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 3 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 3 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::164-167 3 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads
298,302c298,302
< system.physmem.wrPerTurnAround::total 77347 # Writes before turning the bus around for reads
< system.physmem.totQLat 84737173288 # Total ticks spent queuing
< system.physmem.totMemAccLat 115373117038 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 8169585000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 51861.37 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::total 73621 # Writes before turning the bus around for reads
> system.physmem.totQLat 78457411069 # Total ticks spent queuing
> system.physmem.totMemAccLat 107786892319 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 7821195000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 50156.92 # Average queueing delay per DRAM burst
304,308c304,308
< system.physmem.avgMemAccLat 70611.37 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 2.21 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 1.83 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 2.19 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 1.83 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 68906.92 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 1.75 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 2.09 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 1.75 # Average system write bandwidth in MiByte/s
313,331c313,331
< system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 25.70 # Average write queue length when enqueuing
< system.physmem.readRowHits 1319893 # Number of row buffer hits during reads
< system.physmem.writeRowHits 639153 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 80.78 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 47.22 # Row buffer hit rate for writes
< system.physmem.avgGap 15821516.13 # Average gap between requests
< system.physmem.pageHitRate 65.57 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 3982161960 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 2172806625 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 6418448400 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 4425017040 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 3090046667760 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 1165891095180 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 27363173363250 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 31636109560215 # Total energy per rank (pJ)
< system.physmem_0.averagePower 668.700864 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 45520771842112 # Time in different power states
< system.physmem_0.memoryStateTime::REF 1579778460000 # Time in different power states
---
> system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 26.14 # Average write queue length when enqueuing
> system.physmem.readRowHits 1261076 # Number of row buffer hits during reads
> system.physmem.writeRowHits 622485 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 80.62 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 47.99 # Row buffer hit rate for writes
> system.physmem.avgGap 16561334.66 # Average gap between requests
> system.physmem.pageHitRate 65.82 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 3784611600 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 2065016250 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 6155541600 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 4268064960 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 3098216175600 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 1175166619965 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 27430083930000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 31719739959975 # Total energy per rank (pJ)
> system.physmem_0.averagePower 668.700662 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 45632003284876 # Time in different power states
> system.physmem_0.memoryStateTime::REF 1583955100000 # Time in different power states
333c333
< system.physmem_0.memoryStateTime::ACT 209258446888 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 218928032624 # Time in different power states
335,345c335,345
< system.physmem_1.actEnergy 3792625200 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 2069388750 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 6326026200 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 4345967520 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 3090046667760 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 1161508413915 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 27367017820500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 31635106909845 # Total energy per rank (pJ)
< system.physmem_1.averagePower 668.679671 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 45527169156111 # Time in different power states
< system.physmem_1.memoryStateTime::REF 1579778460000 # Time in different power states
---
> system.physmem_1.actEnergy 3608221680 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 1968771750 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 6045468000 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 4137868800 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 3098216175600 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 1172302278480 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 27432596510250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 31718875294560 # Total energy per rank (pJ)
> system.physmem_1.averagePower 668.682434 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 45636187348814 # Time in different power states
> system.physmem_1.memoryStateTime::REF 1583955100000 # Time in different power states
347c347
< system.physmem_1.memoryStateTime::ACT 202865647889 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 214746668686 # Time in different power states
381,385c381,385
< system.cpu0.branchPred.lookups 147707110 # Number of BP lookups
< system.cpu0.branchPred.condPredicted 98263896 # Number of conditional branches predicted
< system.cpu0.branchPred.condIncorrect 7114286 # Number of conditional branches incorrect
< system.cpu0.branchPred.BTBLookups 103765470 # Number of BTB lookups
< system.cpu0.branchPred.BTBHits 67713845 # Number of BTB hits
---
> system.cpu0.branchPred.lookups 146144434 # Number of BP lookups
> system.cpu0.branchPred.condPredicted 97047776 # Number of conditional branches predicted
> system.cpu0.branchPred.condIncorrect 7141884 # Number of conditional branches incorrect
> system.cpu0.branchPred.BTBLookups 102585049 # Number of BTB lookups
> system.cpu0.branchPred.BTBHits 68142392 # Number of BTB hits
387,389c387,389
< system.cpu0.branchPred.BTBHitPct 65.256626 # BTB Hit Percentage
< system.cpu0.branchPred.usedRAS 20037326 # Number of times the RAS was used to get a target.
< system.cpu0.branchPred.RASInCorrect 200169 # Number of incorrect RAS predictions.
---
> system.cpu0.branchPred.BTBHitPct 66.425266 # BTB Hit Percentage
> system.cpu0.branchPred.usedRAS 20061645 # Number of times the RAS was used to get a target.
> system.cpu0.branchPred.RASInCorrect 208019 # Number of incorrect RAS predictions.
420,476c420,471
< system.cpu0.dtb.walker.walks 575296 # Table walker walks requested
< system.cpu0.dtb.walker.walksLong 575296 # Table walker walks initiated with long descriptors
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12884 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88904 # Level at which table walker walks with long descriptors terminate
< system.cpu0.dtb.walker.walksSquashedBefore 257665 # Table walks squashed before starting
< system.cpu0.dtb.walker.walkWaitTime::samples 317631 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::mean 2022.074357 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::stdev 12176.572384 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::0-65535 315561 99.35% 99.35% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::65536-131071 1443 0.45% 99.80% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::131072-196607 466 0.15% 99.95% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::196608-262143 74 0.02% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::262144-327679 64 0.02% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::327680-393215 16 0.01% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkWaitTime::total 317631 # Table walker wait (enqueue to first request) latency
< system.cpu0.dtb.walker.walkCompletionTime::samples 284896 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::mean 18154.968831 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::gmean 15325.984047 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::stdev 16062.585690 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::0-32767 269179 94.48% 94.48% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::32768-65535 12793 4.49% 98.97% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::65536-98303 1124 0.39% 99.37% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::98304-131071 999 0.35% 99.72% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::131072-163839 121 0.04% 99.76% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::163840-196607 154 0.05% 99.82% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::196608-229375 275 0.10% 99.91% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::229376-262143 60 0.02% 99.93% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::262144-294911 49 0.02% 99.95% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::294912-327679 59 0.02% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::327680-360447 25 0.01% 99.98% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::360448-393215 23 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::393216-425983 18 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::425984-458751 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::491520-524287 9 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walkCompletionTime::total 284896 # Table walker service (enqueue to completion) latency
< system.cpu0.dtb.walker.walksPending::samples 550505269948 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::mean 0.606717 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::stdev 0.533946 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::0-1 549425097448 99.80% 99.80% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::2-3 576911000 0.10% 99.91% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::4-5 232215500 0.04% 99.95% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::6-7 109337500 0.02% 99.97% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::8-9 81684000 0.01% 99.99% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::10-11 43624500 0.01% 99.99% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::12-13 15920500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::14-15 20013500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::16-17 440500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::18-19 25500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.dtb.walker.walksPending::total 550505269948 # Table walker pending requests distribution
< system.cpu0.dtb.walker.walkPageSizes::4K 88905 87.34% 87.34% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::2M 12884 12.66% 100.00% # Table walker page sizes translated
< system.cpu0.dtb.walker.walkPageSizes::total 101789 # Table walker page sizes translated
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 575296 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walks 627056 # Table walker walks requested
> system.cpu0.dtb.walker.walksLong 627056 # Table walker walks initiated with long descriptors
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13350 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 99805 # Level at which table walker walks with long descriptors terminate
> system.cpu0.dtb.walker.walksSquashedBefore 293358 # Table walks squashed before starting
> system.cpu0.dtb.walker.walkWaitTime::samples 333698 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::mean 2422.801455 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::stdev 15109.123610 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::0-65535 330908 99.16% 99.16% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::65536-131071 1425 0.43% 99.59% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::131072-196607 1094 0.33% 99.92% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::196608-262143 126 0.04% 99.96% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::262144-327679 36 0.01% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::327680-393215 71 0.02% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::393216-458751 25 0.01% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::524288-589823 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkWaitTime::total 333698 # Table walker wait (enqueue to first request) latency
> system.cpu0.dtb.walker.walkCompletionTime::samples 325671 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::mean 20358.917435 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::gmean 16786.442146 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::stdev 23186.053079 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::0-65535 321319 98.66% 98.66% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::65536-131071 949 0.29% 98.96% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::131072-196607 2404 0.74% 99.69% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::196608-262143 140 0.04% 99.74% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::262144-327679 546 0.17% 99.90% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::327680-393215 110 0.03% 99.94% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::393216-458751 121 0.04% 99.97% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::458752-524287 45 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::524288-589823 26 0.01% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::589824-655359 11 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walkCompletionTime::total 325671 # Table walker service (enqueue to completion) latency
> system.cpu0.dtb.walker.walksPending::samples 568195090048 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::mean 0.606171 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::stdev 0.541778 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::0-1 566772056048 99.75% 99.75% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::2-3 811255500 0.14% 99.89% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::4-5 288193500 0.05% 99.94% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::6-7 133409000 0.02% 99.97% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::8-9 101036500 0.02% 99.98% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::10-11 47966000 0.01% 99.99% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::12-13 17568000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::14-15 22933000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::16-17 641000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::18-19 31500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.dtb.walker.walksPending::total 568195090048 # Table walker pending requests distribution
> system.cpu0.dtb.walker.walkPageSizes::4K 99806 88.20% 88.20% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::2M 13350 11.80% 100.00% # Table walker page sizes translated
> system.cpu0.dtb.walker.walkPageSizes::total 113156 # Table walker page sizes translated
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 627056 # Table walker requests started/completed, data/inst
478,479c473,474
< system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 575296 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101789 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 627056 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 113156 # Table walker requests started/completed, data/inst
481,482c476,477
< system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101789 # Table walker requests started/completed, data/inst
< system.cpu0.dtb.walker.walkRequestOrigin::total 677085 # Table walker requests started/completed, data/inst
---
> system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 113156 # Table walker requests started/completed, data/inst
> system.cpu0.dtb.walker.walkRequestOrigin::total 740212 # Table walker requests started/completed, data/inst
485,488c480,483
< system.cpu0.dtb.read_hits 107498760 # DTB read hits
< system.cpu0.dtb.read_misses 398450 # DTB read misses
< system.cpu0.dtb.write_hits 89911233 # DTB write hits
< system.cpu0.dtb.write_misses 176846 # DTB write misses
---
> system.cpu0.dtb.read_hits 106442927 # DTB read hits
> system.cpu0.dtb.read_misses 452572 # DTB read misses
> system.cpu0.dtb.write_hits 87367482 # DTB write hits
> system.cpu0.dtb.write_misses 174484 # DTB write misses
491,495c486,490
< system.cpu0.dtb.flush_tlb_mva_asid 44378 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.dtb.flush_tlb_asid 1065 # Number of times TLB was flushed by ASID
< system.cpu0.dtb.flush_entries 36343 # Number of entries that have been flushed from TLB
< system.cpu0.dtb.align_faults 314 # Number of TLB faults due to alignment restrictions
< system.cpu0.dtb.prefetch_faults 6513 # Number of TLB faults due to prefetch
---
> system.cpu0.dtb.flush_tlb_mva_asid 44087 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
> system.cpu0.dtb.flush_entries 43076 # Number of entries that have been flushed from TLB
> system.cpu0.dtb.align_faults 336 # Number of TLB faults due to alignment restrictions
> system.cpu0.dtb.prefetch_faults 7862 # Number of TLB faults due to prefetch
497,499c492,494
< system.cpu0.dtb.perms_faults 39209 # Number of TLB faults due to permissions restrictions
< system.cpu0.dtb.read_accesses 107897210 # DTB read accesses
< system.cpu0.dtb.write_accesses 90088079 # DTB write accesses
---
> system.cpu0.dtb.perms_faults 41749 # Number of TLB faults due to permissions restrictions
> system.cpu0.dtb.read_accesses 106895499 # DTB read accesses
> system.cpu0.dtb.write_accesses 87541966 # DTB write accesses
501,503c496,498
< system.cpu0.dtb.hits 197409993 # DTB hits
< system.cpu0.dtb.misses 575296 # DTB misses
< system.cpu0.dtb.accesses 197985289 # DTB accesses
---
> system.cpu0.dtb.hits 193810409 # DTB hits
> system.cpu0.dtb.misses 627056 # DTB misses
> system.cpu0.dtb.accesses 194437465 # DTB accesses
533,584c528,580
< system.cpu0.itb.walker.walks 88373 # Table walker walks requested
< system.cpu0.itb.walker.walksLong 88373 # Table walker walks initiated with long descriptors
< system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1010 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walksLongTerminationLevel::Level3 63733 # Level at which table walker walks with long descriptors terminate
< system.cpu0.itb.walker.walksSquashedBefore 10354 # Table walks squashed before starting
< system.cpu0.itb.walker.walkWaitTime::samples 78019 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::mean 1154.635409 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::stdev 8302.318133 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::0-32767 77325 99.11% 99.11% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::32768-65535 373 0.48% 99.59% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::65536-98303 149 0.19% 99.78% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::98304-131071 144 0.18% 99.96% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::131072-163839 7 0.01% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::163840-196607 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::262144-294911 7 0.01% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkWaitTime::total 78019 # Table walker wait (enqueue to first request) latency
< system.cpu0.itb.walker.walkCompletionTime::samples 75097 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::mean 22974.939079 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::gmean 20231.234781 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::stdev 18518.097642 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::0-32767 68416 91.10% 91.10% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::32768-65535 5120 6.82% 97.92% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::65536-98303 490 0.65% 98.57% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::98304-131071 809 1.08% 99.65% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::131072-163839 63 0.08% 99.74% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::163840-196607 55 0.07% 99.81% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::196608-229375 56 0.07% 99.88% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::229376-262143 27 0.04% 99.92% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::262144-294911 16 0.02% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::294912-327679 17 0.02% 99.96% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::360448-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::393216-425983 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walkCompletionTime::total 75097 # Table walker service (enqueue to completion) latency
< system.cpu0.itb.walker.walksPending::samples 413042823976 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::mean 0.838558 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::stdev 0.368059 # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::0 66699023100 16.15% 16.15% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::1 346328877376 83.85% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::2 13315500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::3 1543000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::4 65000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu0.itb.walker.walksPending::total 413042823976 # Table walker pending requests distribution
< system.cpu0.itb.walker.walkPageSizes::4K 63733 98.44% 98.44% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::2M 1010 1.56% 100.00% # Table walker page sizes translated
< system.cpu0.itb.walker.walkPageSizes::total 64743 # Table walker page sizes translated
---
> system.cpu0.itb.walker.walks 89572 # Table walker walks requested
> system.cpu0.itb.walker.walksLong 89572 # Table walker walks initiated with long descriptors
> system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1024 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walksLongTerminationLevel::Level3 63745 # Level at which table walker walks with long descriptors terminate
> system.cpu0.itb.walker.walksSquashedBefore 10456 # Table walks squashed before starting
> system.cpu0.itb.walker.walkWaitTime::samples 79116 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::mean 1699.586683 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::stdev 13044.450560 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::0-32767 78197 98.84% 98.84% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::32768-65535 434 0.55% 99.39% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::65536-98303 37 0.05% 99.43% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::98304-131071 79 0.10% 99.53% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::131072-163839 275 0.35% 99.88% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::163840-196607 59 0.07% 99.96% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::229376-262143 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::262144-294911 7 0.01% 99.98% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::294912-327679 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkWaitTime::total 79116 # Table walker wait (enqueue to first request) latency
> system.cpu0.itb.walker.walkCompletionTime::samples 75225 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::mean 26620.711200 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::gmean 21926.293248 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::stdev 30000.304563 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::0-65535 72890 96.90% 96.90% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::65536-131071 127 0.17% 97.06% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::131072-196607 1867 2.48% 99.55% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::196608-262143 130 0.17% 99.72% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::262144-327679 117 0.16% 99.88% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::327680-393215 47 0.06% 99.94% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::393216-458751 31 0.04% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walkCompletionTime::total 75225 # Table walker service (enqueue to completion) latency
> system.cpu0.itb.walker.walksPending::samples 417841685688 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::mean 0.859653 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::stdev 0.347613 # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::0 58676119976 14.04% 14.04% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::1 359136359212 85.95% 99.99% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::2 25573000 0.01% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::3 3283500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::4 186000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::5 60000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::6 104000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu0.itb.walker.walksPending::total 417841685688 # Table walker pending requests distribution
> system.cpu0.itb.walker.walkPageSizes::4K 63745 98.42% 98.42% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::2M 1024 1.58% 100.00% # Table walker page sizes translated
> system.cpu0.itb.walker.walkPageSizes::total 64769 # Table walker page sizes translated
586,587c582,583
< system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 88373 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Requested::total 88373 # Table walker requests started/completed, data/inst
---
> system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 89572 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Requested::total 89572 # Table walker requests started/completed, data/inst
589,593c585,589
< system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64743 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64743 # Table walker requests started/completed, data/inst
< system.cpu0.itb.walker.walkRequestOrigin::total 153116 # Table walker requests started/completed, data/inst
< system.cpu0.itb.inst_hits 231997623 # ITB inst hits
< system.cpu0.itb.inst_misses 88373 # ITB inst misses
---
> system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64769 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64769 # Table walker requests started/completed, data/inst
> system.cpu0.itb.walker.walkRequestOrigin::total 154341 # Table walker requests started/completed, data/inst
> system.cpu0.itb.inst_hits 230754760 # ITB inst hits
> system.cpu0.itb.inst_misses 89572 # ITB inst misses
600,602c596,598
< system.cpu0.itb.flush_tlb_mva_asid 44378 # Number of times TLB was flushed by MVA & ASID
< system.cpu0.itb.flush_tlb_asid 1065 # Number of times TLB was flushed by ASID
< system.cpu0.itb.flush_entries 26272 # Number of entries that have been flushed from TLB
---
> system.cpu0.itb.flush_tlb_mva_asid 44087 # Number of times TLB was flushed by MVA & ASID
> system.cpu0.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
> system.cpu0.itb.flush_entries 31365 # Number of entries that have been flushed from TLB
606c602
< system.cpu0.itb.perms_faults 223051 # Number of TLB faults due to permissions restrictions
---
> system.cpu0.itb.perms_faults 227814 # Number of TLB faults due to permissions restrictions
609,613c605,609
< system.cpu0.itb.inst_accesses 232085996 # ITB inst accesses
< system.cpu0.itb.hits 231997623 # DTB hits
< system.cpu0.itb.misses 88373 # DTB misses
< system.cpu0.itb.accesses 232085996 # DTB accesses
< system.cpu0.numCycles 807086065 # number of cpu cycles simulated
---
> system.cpu0.itb.inst_accesses 230844332 # ITB inst accesses
> system.cpu0.itb.hits 230754760 # DTB hits
> system.cpu0.itb.misses 89572 # DTB misses
> system.cpu0.itb.accesses 230844332 # DTB accesses
> system.cpu0.numCycles 860058385 # number of cpu cycles simulated
616,632c612,628
< system.cpu0.fetch.icacheStallCycles 93861008 # Number of cycles fetch is stalled on an Icache miss
< system.cpu0.fetch.Insts 652896475 # Number of instructions fetch has processed
< system.cpu0.fetch.Branches 147707110 # Number of branches that fetch encountered
< system.cpu0.fetch.predictedBranches 87751171 # Number of branches that fetch has predicted taken
< system.cpu0.fetch.Cycles 672171434 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu0.fetch.SquashCycles 15342460 # Number of cycles fetch has spent squashing
< system.cpu0.fetch.TlbCycles 1905506 # Number of cycles fetch has spent waiting for tlb
< system.cpu0.fetch.MiscStallCycles 292447 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu0.fetch.PendingTrapStallCycles 6425780 # Number of stall cycles due to pending traps
< system.cpu0.fetch.PendingQuiesceStallCycles 696882 # Number of stall cycles due to pending quiesce instructions
< system.cpu0.fetch.IcacheWaitRetryStallCycles 817665 # Number of stall cycles due to full MSHR
< system.cpu0.fetch.CacheLines 231773404 # Number of cache lines fetched
< system.cpu0.fetch.IcacheSquashes 1782410 # Number of outstanding Icache misses that were squashed
< system.cpu0.fetch.ItlbSquashes 29765 # Number of outstanding ITLB misses that were squashed
< system.cpu0.fetch.rateDist::samples 783841952 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::mean 0.977378 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::stdev 1.220143 # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.icacheStallCycles 93823767 # Number of cycles fetch is stalled on an Icache miss
> system.cpu0.fetch.Insts 647034006 # Number of instructions fetch has processed
> system.cpu0.fetch.Branches 146144434 # Number of branches that fetch encountered
> system.cpu0.fetch.predictedBranches 88204037 # Number of branches that fetch has predicted taken
> system.cpu0.fetch.Cycles 713428063 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu0.fetch.SquashCycles 15421284 # Number of cycles fetch has spent squashing
> system.cpu0.fetch.TlbCycles 2142608 # Number of cycles fetch has spent waiting for tlb
> system.cpu0.fetch.MiscStallCycles 370377 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu0.fetch.PendingTrapStallCycles 6662477 # Number of stall cycles due to pending traps
> system.cpu0.fetch.PendingQuiesceStallCycles 811703 # Number of stall cycles due to pending quiesce instructions
> system.cpu0.fetch.IcacheWaitRetryStallCycles 935488 # Number of stall cycles due to full MSHR
> system.cpu0.fetch.CacheLines 230526197 # Number of cache lines fetched
> system.cpu0.fetch.IcacheSquashes 1802314 # Number of outstanding Icache misses that were squashed
> system.cpu0.fetch.ItlbSquashes 29828 # Number of outstanding ITLB misses that were squashed
> system.cpu0.fetch.rateDist::samples 825885125 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::mean 0.917836 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::stdev 1.204243 # Number of instructions fetched each cycle (Total)
634,637c630,633
< system.cpu0.fetch.rateDist::0 417241550 53.23% 53.23% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::1 142387565 18.17% 71.40% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::2 48916006 6.24% 77.64% # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.rateDist::3 175296831 22.36% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu0.fetch.rateDist::0 462725297 56.03% 56.03% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::1 141134334 17.09% 73.12% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::2 49183945 5.96% 79.07% # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.rateDist::3 172841549 20.93% 100.00% # Number of instructions fetched each cycle (Total)
641,688c637,684
< system.cpu0.fetch.rateDist::total 783841952 # Number of instructions fetched each cycle (Total)
< system.cpu0.fetch.branchRate 0.183013 # Number of branch fetches per cycle
< system.cpu0.fetch.rate 0.808955 # Number of inst fetches per cycle
< system.cpu0.decode.IdleCycles 111750908 # Number of cycles decode is idle
< system.cpu0.decode.BlockedCycles 381172853 # Number of cycles decode is blocked
< system.cpu0.decode.RunCycles 246402586 # Number of cycles decode is running
< system.cpu0.decode.UnblockCycles 39053255 # Number of cycles decode is unblocking
< system.cpu0.decode.SquashCycles 5462350 # Number of cycles decode is squashing
< system.cpu0.decode.BranchResolved 21288781 # Number of times decode resolved a branch
< system.cpu0.decode.BranchMispred 2252861 # Number of times decode detected a branch misprediction
< system.cpu0.decode.DecodedInsts 678905918 # Number of instructions handled by decode
< system.cpu0.decode.SquashedInsts 24756446 # Number of squashed instructions handled by decode
< system.cpu0.rename.SquashCycles 5462350 # Number of cycles rename is squashing
< system.cpu0.rename.IdleCycles 148938841 # Number of cycles rename is idle
< system.cpu0.rename.BlockCycles 55630896 # Number of cycles rename is blocking
< system.cpu0.rename.serializeStallCycles 250198036 # count of cycles rename stalled for serializing inst
< system.cpu0.rename.RunCycles 247704695 # Number of cycles rename is running
< system.cpu0.rename.UnblockCycles 75907134 # Number of cycles rename is unblocking
< system.cpu0.rename.RenamedInsts 660737654 # Number of instructions processed by rename
< system.cpu0.rename.SquashedInsts 6369939 # Number of squashed instructions processed by rename
< system.cpu0.rename.ROBFullEvents 10029778 # Number of times rename has blocked due to ROB full
< system.cpu0.rename.IQFullEvents 264844 # Number of times rename has blocked due to IQ full
< system.cpu0.rename.LQFullEvents 301380 # Number of times rename has blocked due to LQ full
< system.cpu0.rename.SQFullEvents 39545548 # Number of times rename has blocked due to SQ full
< system.cpu0.rename.FullRegisterEvents 11804 # Number of times there has been no free registers
< system.cpu0.rename.RenamedOperands 629064095 # Number of destination operands rename has renamed
< system.cpu0.rename.RenameLookups 1015658028 # Number of register rename lookups that rename has made
< system.cpu0.rename.int_rename_lookups 780465434 # Number of integer rename lookups
< system.cpu0.rename.fp_rename_lookups 875541 # Number of floating rename lookups
< system.cpu0.rename.CommittedMaps 567964584 # Number of HB maps that are committed
< system.cpu0.rename.UndoneMaps 61099508 # Number of HB maps that are undone due to squashing
< system.cpu0.rename.serializingInsts 16110257 # count of serializing insts renamed
< system.cpu0.rename.tempSerializingInsts 14023115 # count of temporary serializing insts renamed
< system.cpu0.rename.skidInsts 79266160 # count of insts added to the skid buffer
< system.cpu0.memDep0.insertedLoads 107669777 # Number of loads inserted to the mem dependence unit.
< system.cpu0.memDep0.insertedStores 93504359 # Number of stores inserted to the mem dependence unit.
< system.cpu0.memDep0.conflictingLoads 9663954 # Number of conflicting loads.
< system.cpu0.memDep0.conflictingStores 8219387 # Number of conflicting stores.
< system.cpu0.iq.iqInstsAdded 637670623 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu0.iq.iqNonSpecInstsAdded 16186083 # Number of non-speculative instructions added to the IQ
< system.cpu0.iq.iqInstsIssued 641968825 # Number of instructions issued
< system.cpu0.iq.iqSquashedInstsIssued 2865871 # Number of squashed instructions issued
< system.cpu0.iq.iqSquashedInstsExamined 57572234 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu0.iq.iqSquashedOperandsExamined 37073972 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu0.iq.iqSquashedNonSpecRemoved 286236 # Number of squashed non-spec instructions that were removed
< system.cpu0.iq.issued_per_cycle::samples 783841952 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::mean 0.819003 # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::stdev 1.071442 # Number of insts issued each cycle
---
> system.cpu0.fetch.rateDist::total 825885125 # Number of instructions fetched each cycle (Total)
> system.cpu0.fetch.branchRate 0.169924 # Number of branch fetches per cycle
> system.cpu0.fetch.rate 0.752314 # Number of inst fetches per cycle
> system.cpu0.decode.IdleCycles 112769742 # Number of cycles decode is idle
> system.cpu0.decode.BlockedCycles 426082666 # Number of cycles decode is blocked
> system.cpu0.decode.RunCycles 241448796 # Number of cycles decode is running
> system.cpu0.decode.UnblockCycles 40086734 # Number of cycles decode is unblocking
> system.cpu0.decode.SquashCycles 5497187 # Number of cycles decode is squashing
> system.cpu0.decode.BranchResolved 21049410 # Number of times decode resolved a branch
> system.cpu0.decode.BranchMispred 2256773 # Number of times decode detected a branch misprediction
> system.cpu0.decode.DecodedInsts 670218998 # Number of instructions handled by decode
> system.cpu0.decode.SquashedInsts 24585217 # Number of squashed instructions handled by decode
> system.cpu0.rename.SquashCycles 5497187 # Number of cycles rename is squashing
> system.cpu0.rename.IdleCycles 150343342 # Number of cycles rename is idle
> system.cpu0.rename.BlockCycles 70257974 # Number of cycles rename is blocking
> system.cpu0.rename.serializeStallCycles 265091659 # count of cycles rename stalled for serializing inst
> system.cpu0.rename.RunCycles 243360217 # Number of cycles rename is running
> system.cpu0.rename.UnblockCycles 91334746 # Number of cycles rename is unblocking
> system.cpu0.rename.RenamedInsts 651968055 # Number of instructions processed by rename
> system.cpu0.rename.SquashedInsts 6322268 # Number of squashed instructions processed by rename
> system.cpu0.rename.ROBFullEvents 11333163 # Number of times rename has blocked due to ROB full
> system.cpu0.rename.IQFullEvents 398238 # Number of times rename has blocked due to IQ full
> system.cpu0.rename.LQFullEvents 892987 # Number of times rename has blocked due to LQ full
> system.cpu0.rename.SQFullEvents 53687870 # Number of times rename has blocked due to SQ full
> system.cpu0.rename.FullRegisterEvents 12055 # Number of times there has been no free registers
> system.cpu0.rename.RenamedOperands 623161441 # Number of destination operands rename has renamed
> system.cpu0.rename.RenameLookups 1008090615 # Number of register rename lookups that rename has made
> system.cpu0.rename.int_rename_lookups 769730678 # Number of integer rename lookups
> system.cpu0.rename.fp_rename_lookups 803084 # Number of floating rename lookups
> system.cpu0.rename.CommittedMaps 561865875 # Number of HB maps that are committed
> system.cpu0.rename.UndoneMaps 61295566 # Number of HB maps that are undone due to squashing
> system.cpu0.rename.serializingInsts 16618595 # count of serializing insts renamed
> system.cpu0.rename.tempSerializingInsts 14448752 # count of temporary serializing insts renamed
> system.cpu0.rename.skidInsts 81009207 # count of insts added to the skid buffer
> system.cpu0.memDep0.insertedLoads 106588320 # Number of loads inserted to the mem dependence unit.
> system.cpu0.memDep0.insertedStores 90921259 # Number of stores inserted to the mem dependence unit.
> system.cpu0.memDep0.conflictingLoads 9791542 # Number of conflicting loads.
> system.cpu0.memDep0.conflictingStores 8386441 # Number of conflicting stores.
> system.cpu0.iq.iqInstsAdded 628410475 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu0.iq.iqNonSpecInstsAdded 16690332 # Number of non-speculative instructions added to the IQ
> system.cpu0.iq.iqInstsIssued 633219394 # Number of instructions issued
> system.cpu0.iq.iqSquashedInstsIssued 2873840 # Number of squashed instructions issued
> system.cpu0.iq.iqSquashedInstsExamined 57472988 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu0.iq.iqSquashedOperandsExamined 37517559 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu0.iq.iqSquashedNonSpecRemoved 288712 # Number of squashed non-spec instructions that were removed
> system.cpu0.iq.issued_per_cycle::samples 825885125 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::mean 0.766716 # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::stdev 1.051496 # Number of insts issued each cycle
690,695c686,691
< system.cpu0.iq.issued_per_cycle::0 436124999 55.64% 55.64% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::1 142425457 18.17% 73.81% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::2 124936152 15.94% 89.75% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::3 71756087 9.15% 98.90% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::4 8593482 1.10% 100.00% # Number of insts issued each cycle
< system.cpu0.iq.issued_per_cycle::5 5775 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::0 480372364 58.16% 58.16% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::1 144500445 17.50% 75.66% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::2 122618774 14.85% 90.51% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::3 70098834 8.49% 99.00% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::4 8288641 1.00% 100.00% # Number of insts issued each cycle
> system.cpu0.iq.issued_per_cycle::5 6067 0.00% 100.00% # Number of insts issued each cycle
702c698
< system.cpu0.iq.issued_per_cycle::total 783841952 # Number of insts issued each cycle
---
> system.cpu0.iq.issued_per_cycle::total 825885125 # Number of insts issued each cycle
704,734c700,730
< system.cpu0.iq.fu_full::IntAlu 67185359 45.52% 45.52% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntMult 54880 0.04% 45.56% # attempts to use FU when none available
< system.cpu0.iq.fu_full::IntDiv 27644 0.02% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMisc 23 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.58% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemRead 37910313 25.69% 71.26% # attempts to use FU when none available
< system.cpu0.iq.fu_full::MemWrite 42413379 28.74% 100.00% # attempts to use FU when none available
---
> system.cpu0.iq.fu_full::IntAlu 65372240 45.40% 45.40% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntMult 70238 0.05% 45.45% # attempts to use FU when none available
> system.cpu0.iq.fu_full::IntDiv 24747 0.02% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMisc 29 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.46% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemRead 37918627 26.33% 71.79% # attempts to use FU when none available
> system.cpu0.iq.fu_full::MemWrite 40615883 28.21% 100.00% # attempts to use FU when none available
738,768c734,764
< system.cpu0.iq.FU_type_0::IntAlu 438393066 68.29% 68.29% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntMult 1458143 0.23% 68.52% # Type of FU issued
< system.cpu0.iq.FU_type_0::IntDiv 76119 0.01% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatAdd 8 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.53% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMisc 85008 0.01% 68.54% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.54% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.54% # Type of FU issued
< system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.54% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemRead 110671978 17.24% 85.78% # Type of FU issued
< system.cpu0.iq.FU_type_0::MemWrite 91284446 14.22% 100.00% # Type of FU issued
---
> system.cpu0.iq.FU_type_0::IntAlu 433018605 68.38% 68.38% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntMult 1583156 0.25% 68.63% # Type of FU issued
> system.cpu0.iq.FU_type_0::IntDiv 81666 0.01% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.65% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMisc 80947 0.01% 68.66% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.66% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.66% # Type of FU issued
> system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.66% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemRead 109728452 17.33% 85.99% # Type of FU issued
> system.cpu0.iq.FU_type_0::MemWrite 88726558 14.01% 100.00% # Type of FU issued
771,783c767,779
< system.cpu0.iq.FU_type_0::total 641968825 # Type of FU issued
< system.cpu0.iq.rate 0.795416 # Inst issue rate
< system.cpu0.iq.fu_busy_cnt 147591598 # FU busy when requested
< system.cpu0.iq.fu_busy_rate 0.229905 # FU busy rate (busy events/executed inst)
< system.cpu0.iq.int_inst_queue_reads 2216794106 # Number of integer instruction queue reads
< system.cpu0.iq.int_inst_queue_writes 710999195 # Number of integer instruction queue writes
< system.cpu0.iq.int_inst_queue_wakeup_accesses 623995458 # Number of integer instruction queue wakeup accesses
< system.cpu0.iq.fp_inst_queue_reads 1442965 # Number of floating instruction queue reads
< system.cpu0.iq.fp_inst_queue_writes 583548 # Number of floating instruction queue writes
< system.cpu0.iq.fp_inst_queue_wakeup_accesses 537913 # Number of floating instruction queue wakeup accesses
< system.cpu0.iq.int_alu_accesses 788669354 # Number of integer alu accesses
< system.cpu0.iq.fp_alu_accesses 891059 # Number of floating point alu accesses
< system.cpu0.iew.lsq.thread0.forwLoads 2946784 # Number of loads that had data forwarded from stores
---
> system.cpu0.iq.FU_type_0::total 633219394 # Type of FU issued
> system.cpu0.iq.rate 0.736252 # Inst issue rate
> system.cpu0.iq.fu_busy_cnt 144001764 # FU busy when requested
> system.cpu0.iq.fu_busy_rate 0.227412 # FU busy rate (busy events/executed inst)
> system.cpu0.iq.int_inst_queue_reads 2237858803 # Number of integer instruction queue reads
> system.cpu0.iq.int_inst_queue_writes 702176142 # Number of integer instruction queue writes
> system.cpu0.iq.int_inst_queue_wakeup_accesses 615023589 # Number of integer instruction queue wakeup accesses
> system.cpu0.iq.fp_inst_queue_reads 1340714 # Number of floating instruction queue reads
> system.cpu0.iq.fp_inst_queue_writes 546565 # Number of floating instruction queue writes
> system.cpu0.iq.fp_inst_queue_wakeup_accesses 499647 # Number of floating instruction queue wakeup accesses
> system.cpu0.iq.int_alu_accesses 776393889 # Number of integer alu accesses
> system.cpu0.iq.fp_alu_accesses 827259 # Number of floating point alu accesses
> system.cpu0.iew.lsq.thread0.forwLoads 2940154 # Number of loads that had data forwarded from stores
785,788c781,784
< system.cpu0.iew.lsq.thread0.squashedLoads 13030035 # Number of loads squashed
< system.cpu0.iew.lsq.thread0.ignoredResponses 16500 # Number of memory responses ignored because the instruction is squashed
< system.cpu0.iew.lsq.thread0.memOrderViolation 154978 # Number of memory ordering violations
< system.cpu0.iew.lsq.thread0.squashedStores 6224286 # Number of stores squashed
---
> system.cpu0.iew.lsq.thread0.squashedLoads 13228982 # Number of loads squashed
> system.cpu0.iew.lsq.thread0.ignoredResponses 17998 # Number of memory responses ignored because the instruction is squashed
> system.cpu0.iew.lsq.thread0.memOrderViolation 150420 # Number of memory ordering violations
> system.cpu0.iew.lsq.thread0.squashedStores 6097724 # Number of stores squashed
791,792c787,788
< system.cpu0.iew.lsq.thread0.rescheduledLoads 2912970 # Number of loads that were rescheduled
< system.cpu0.iew.lsq.thread0.cacheBlocked 4614756 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu0.iew.lsq.thread0.rescheduledLoads 2855732 # Number of loads that were rescheduled
> system.cpu0.iew.lsq.thread0.cacheBlocked 4944067 # Number of times an access to memory failed due to the cache being blocked
794,797c790,793
< system.cpu0.iew.iewSquashCycles 5462350 # Number of cycles IEW is squashing
< system.cpu0.iew.iewBlockCycles 6648440 # Number of cycles IEW is blocking
< system.cpu0.iew.iewUnblockCycles 5673367 # Number of cycles IEW is unblocking
< system.cpu0.iew.iewDispatchedInsts 653983600 # Number of instructions dispatched to IQ
---
> system.cpu0.iew.iewSquashCycles 5497187 # Number of cycles IEW is squashing
> system.cpu0.iew.iewBlockCycles 8555370 # Number of cycles IEW is blocking
> system.cpu0.iew.iewUnblockCycles 7804154 # Number of cycles IEW is unblocking
> system.cpu0.iew.iewDispatchedInsts 645228891 # Number of instructions dispatched to IQ
799,810c795,806
< system.cpu0.iew.iewDispLoadInsts 107669777 # Number of dispatched load instructions
< system.cpu0.iew.iewDispStoreInsts 93504359 # Number of dispatched store instructions
< system.cpu0.iew.iewDispNonSpecInsts 13738155 # Number of dispatched non-speculative instructions
< system.cpu0.iew.iewIQFullEvents 65760 # Number of times the IQ has become full, causing a stall
< system.cpu0.iew.iewLSQFullEvents 5541873 # Number of times the LSQ has become full, causing a stall
< system.cpu0.iew.memOrderViolationEvents 154978 # Number of memory order violations
< system.cpu0.iew.predictedTakenIncorrect 2183890 # Number of branches that were predicted taken incorrectly
< system.cpu0.iew.predictedNotTakenIncorrect 3035421 # Number of branches that were predicted not taken incorrectly
< system.cpu0.iew.branchMispredicts 5219311 # Number of branch mispredicts detected at execute
< system.cpu0.iew.iewExecutedInsts 633716914 # Number of executed instructions
< system.cpu0.iew.iewExecLoadInsts 107489609 # Number of load instructions executed
< system.cpu0.iew.iewExecSquashedInsts 7688831 # Number of squashed instructions skipped in execute
---
> system.cpu0.iew.iewDispLoadInsts 106588320 # Number of dispatched load instructions
> system.cpu0.iew.iewDispStoreInsts 90921259 # Number of dispatched store instructions
> system.cpu0.iew.iewDispNonSpecInsts 14154267 # Number of dispatched non-speculative instructions
> system.cpu0.iew.iewIQFullEvents 60797 # Number of times the IQ has become full, causing a stall
> system.cpu0.iew.iewLSQFullEvents 7667643 # Number of times the LSQ has become full, causing a stall
> system.cpu0.iew.memOrderViolationEvents 150420 # Number of memory order violations
> system.cpu0.iew.predictedTakenIncorrect 2190803 # Number of branches that were predicted taken incorrectly
> system.cpu0.iew.predictedNotTakenIncorrect 3056972 # Number of branches that were predicted not taken incorrectly
> system.cpu0.iew.branchMispredicts 5247775 # Number of branch mispredicts detected at execute
> system.cpu0.iew.iewExecutedInsts 624930976 # Number of executed instructions
> system.cpu0.iew.iewExecLoadInsts 106438227 # Number of load instructions executed
> system.cpu0.iew.iewExecSquashedInsts 7669606 # Number of squashed instructions skipped in execute
812,820c808,816
< system.cpu0.iew.exec_nop 126894 # number of nop insts executed
< system.cpu0.iew.exec_refs 197402015 # number of memory reference insts executed
< system.cpu0.iew.exec_branches 119462239 # Number of branches executed
< system.cpu0.iew.exec_stores 89912406 # Number of stores executed
< system.cpu0.iew.exec_rate 0.785191 # Inst execution rate
< system.cpu0.iew.wb_sent 625355277 # cumulative count of insts sent to commit
< system.cpu0.iew.wb_count 624533371 # cumulative count of insts written-back
< system.cpu0.iew.wb_producers 303033924 # num instructions producing a value
< system.cpu0.iew.wb_consumers 497197749 # num instructions consuming a value
---
> system.cpu0.iew.exec_nop 128084 # number of nop insts executed
> system.cpu0.iew.exec_refs 193805308 # number of memory reference insts executed
> system.cpu0.iew.exec_branches 117788400 # Number of branches executed
> system.cpu0.iew.exec_stores 87367081 # Number of stores executed
> system.cpu0.iew.exec_rate 0.726615 # Inst execution rate
> system.cpu0.iew.wb_sent 616360773 # cumulative count of insts sent to commit
> system.cpu0.iew.wb_count 615523236 # cumulative count of insts written-back
> system.cpu0.iew.wb_producers 299533919 # num instructions producing a value
> system.cpu0.iew.wb_consumers 491459888 # num instructions consuming a value
822,823c818,819
< system.cpu0.iew.wb_rate 0.773813 # insts written-back per cycle
< system.cpu0.iew.wb_fanout 0.609484 # average fanout of values written-back
---
> system.cpu0.iew.wb_rate 0.715676 # insts written-back per cycle
> system.cpu0.iew.wb_fanout 0.609478 # average fanout of values written-back
825,830c821,826
< system.cpu0.commit.commitSquashedInsts 50242588 # The number of squashed insts skipped by commit
< system.cpu0.commit.commitNonSpecStalls 15899847 # The number of times commit has been forced to stall to communicate backwards
< system.cpu0.commit.branchMispredicts 4905406 # The number of times a branch was mispredicted
< system.cpu0.commit.committed_per_cycle::samples 774311548 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::mean 0.770083 # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::stdev 1.572660 # Number of insts commited each cycle
---
> system.cpu0.commit.commitSquashedInsts 50152735 # The number of squashed insts skipped by commit
> system.cpu0.commit.commitNonSpecStalls 16401620 # The number of times commit has been forced to stall to communicate backwards
> system.cpu0.commit.branchMispredicts 4928429 # The number of times a branch was mispredicted
> system.cpu0.commit.committed_per_cycle::samples 816336878 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::mean 0.719835 # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::stdev 1.528210 # Number of insts commited each cycle
832,840c828,836
< system.cpu0.commit.committed_per_cycle::0 515220918 66.54% 66.54% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::1 132191074 17.07% 83.61% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::2 58451829 7.55% 91.16% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::3 19702970 2.54% 93.70% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::4 14118724 1.82% 95.53% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::5 9514083 1.23% 96.76% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::6 6460440 0.83% 97.59% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::7 3939203 0.51% 98.10% # Number of insts commited each cycle
< system.cpu0.commit.committed_per_cycle::8 14712307 1.90% 100.00% # Number of insts commited each cycle
---
> system.cpu0.commit.committed_per_cycle::0 559210939 68.50% 68.50% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::1 132620550 16.25% 84.75% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::2 57447612 7.04% 91.79% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::3 19359516 2.37% 94.16% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::4 13667086 1.67% 95.83% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::5 9472900 1.16% 96.99% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::6 6300261 0.77% 97.76% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::7 3865026 0.47% 98.24% # Number of insts commited each cycle
> system.cpu0.commit.committed_per_cycle::8 14392988 1.76% 100.00% # Number of insts commited each cycle
844,846c840,842
< system.cpu0.commit.committed_per_cycle::total 774311548 # Number of insts commited each cycle
< system.cpu0.commit.committedInsts 507069048 # Number of instructions committed
< system.cpu0.commit.committedOps 596284470 # Number of ops (including micro ops) committed
---
> system.cpu0.commit.committed_per_cycle::total 816336878 # Number of insts commited each cycle
> system.cpu0.commit.committedInsts 500561663 # Number of instructions committed
> system.cpu0.commit.committedOps 587627818 # Number of ops (including micro ops) committed
848,854c844,850
< system.cpu0.commit.refs 181919815 # Number of memory references committed
< system.cpu0.commit.loads 94639742 # Number of loads committed
< system.cpu0.commit.membars 4012038 # Number of memory barriers committed
< system.cpu0.commit.branches 113466884 # Number of branches committed
< system.cpu0.commit.fp_insts 524978 # Number of committed floating point instructions.
< system.cpu0.commit.int_insts 547272509 # Number of committed integer instructions.
< system.cpu0.commit.function_calls 14945710 # Number of function calls committed.
---
> system.cpu0.commit.refs 178182873 # Number of memory references committed
> system.cpu0.commit.loads 93359338 # Number of loads committed
> system.cpu0.commit.membars 3999106 # Number of memory barriers committed
> system.cpu0.commit.branches 111869987 # Number of branches committed
> system.cpu0.commit.fp_insts 487433 # Number of committed floating point instructions.
> system.cpu0.commit.int_insts 538915028 # Number of committed integer instructions.
> system.cpu0.commit.function_calls 14906557 # Number of function calls committed.
856,886c852,882
< system.cpu0.commit.op_class_0::IntAlu 413008446 69.26% 69.26% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntMult 1219700 0.20% 69.47% # Class of committed instruction
< system.cpu0.commit.op_class_0::IntDiv 60724 0.01% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.48% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMisc 75743 0.01% 69.49% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.49% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.49% # Class of committed instruction
< system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.49% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemRead 94639742 15.87% 85.36% # Class of committed instruction
< system.cpu0.commit.op_class_0::MemWrite 87280073 14.64% 100.00% # Class of committed instruction
---
> system.cpu0.commit.op_class_0::IntAlu 407981366 69.43% 69.43% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntMult 1327807 0.23% 69.65% # Class of committed instruction
> system.cpu0.commit.op_class_0::IntDiv 64470 0.01% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.67% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMisc 71302 0.01% 69.68% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.68% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.68% # Class of committed instruction
> system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.68% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemRead 93359338 15.89% 85.57% # Class of committed instruction
> system.cpu0.commit.op_class_0::MemWrite 84823535 14.43% 100.00% # Class of committed instruction
889,1015c885,1010
< system.cpu0.commit.op_class_0::total 596284470 # Class of committed instruction
< system.cpu0.commit.bw_lim_events 14712307 # number cycles where commit BW limit reached
< system.cpu0.rob.rob_reads 1401646047 # The number of ROB reads
< system.cpu0.rob.rob_writes 1302545204 # The number of ROB writes
< system.cpu0.timesIdled 1046717 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu0.idleCycles 23244113 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu0.quiesceCycles 93812546108 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu0.committedInsts 507069048 # Number of Instructions Simulated
< system.cpu0.committedOps 596284470 # Number of Ops (including micro ops) Simulated
< system.cpu0.cpi 1.591669 # CPI: Cycles Per Instruction
< system.cpu0.cpi_total 1.591669 # CPI: Total CPI of All Threads
< system.cpu0.ipc 0.628271 # IPC: Instructions Per Cycle
< system.cpu0.ipc_total 0.628271 # IPC: Total IPC of All Threads
< system.cpu0.int_regfile_reads 748239233 # number of integer regfile reads
< system.cpu0.int_regfile_writes 444460602 # number of integer regfile writes
< system.cpu0.fp_regfile_reads 860614 # number of floating regfile reads
< system.cpu0.fp_regfile_writes 470540 # number of floating regfile writes
< system.cpu0.cc_regfile_reads 137535879 # number of cc regfile reads
< system.cpu0.cc_regfile_writes 138377705 # number of cc regfile writes
< system.cpu0.misc_regfile_reads 1393834331 # number of misc regfile reads
< system.cpu0.misc_regfile_writes 16112974 # number of misc regfile writes
< system.cpu0.dcache.tags.replacements 6187008 # number of replacements
< system.cpu0.dcache.tags.tagsinuse 505.050028 # Cycle average of tags in use
< system.cpu0.dcache.tags.total_refs 169602823 # Total number of references to valid blocks.
< system.cpu0.dcache.tags.sampled_refs 6187519 # Sample count of references to valid blocks.
< system.cpu0.dcache.tags.avg_refs 27.410473 # Average number of references to valid blocks.
< system.cpu0.dcache.tags.warmup_cycle 1887138000 # Cycle when the warmup percentage was hit.
< system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.050028 # Average occupied blocks per requestor
< system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986426 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_percent::total 0.986426 # Average percentage of cache occupancy
< system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id
< system.cpu0.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id
< system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
< system.cpu0.dcache.tags.tag_accesses 376921548 # Number of tag accesses
< system.cpu0.dcache.tags.data_accesses 376921548 # Number of data accesses
< system.cpu0.dcache.ReadReq_hits::cpu0.data 87937173 # number of ReadReq hits
< system.cpu0.dcache.ReadReq_hits::total 87937173 # number of ReadReq hits
< system.cpu0.dcache.WriteReq_hits::cpu0.data 76339825 # number of WriteReq hits
< system.cpu0.dcache.WriteReq_hits::total 76339825 # number of WriteReq hits
< system.cpu0.dcache.SoftPFReq_hits::cpu0.data 228046 # number of SoftPFReq hits
< system.cpu0.dcache.SoftPFReq_hits::total 228046 # number of SoftPFReq hits
< system.cpu0.dcache.WriteLineReq_hits::cpu0.data 267132 # number of WriteLineReq hits
< system.cpu0.dcache.WriteLineReq_hits::total 267132 # number of WriteLineReq hits
< system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1986809 # number of LoadLockedReq hits
< system.cpu0.dcache.LoadLockedReq_hits::total 1986809 # number of LoadLockedReq hits
< system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2024617 # number of StoreCondReq hits
< system.cpu0.dcache.StoreCondReq_hits::total 2024617 # number of StoreCondReq hits
< system.cpu0.dcache.demand_hits::cpu0.data 164276998 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 164276998 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 164505044 # number of overall hits
< system.cpu0.dcache.overall_hits::total 164505044 # number of overall hits
< system.cpu0.dcache.ReadReq_misses::cpu0.data 6895567 # number of ReadReq misses
< system.cpu0.dcache.ReadReq_misses::total 6895567 # number of ReadReq misses
< system.cpu0.dcache.WriteReq_misses::cpu0.data 7624089 # number of WriteReq misses
< system.cpu0.dcache.WriteReq_misses::total 7624089 # number of WriteReq misses
< system.cpu0.dcache.SoftPFReq_misses::cpu0.data 725854 # number of SoftPFReq misses
< system.cpu0.dcache.SoftPFReq_misses::total 725854 # number of SoftPFReq misses
< system.cpu0.dcache.WriteLineReq_misses::cpu0.data 804065 # number of WriteLineReq misses
< system.cpu0.dcache.WriteLineReq_misses::total 804065 # number of WriteLineReq misses
< system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 277240 # number of LoadLockedReq misses
< system.cpu0.dcache.LoadLockedReq_misses::total 277240 # number of LoadLockedReq misses
< system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200055 # number of StoreCondReq misses
< system.cpu0.dcache.StoreCondReq_misses::total 200055 # number of StoreCondReq misses
< system.cpu0.dcache.demand_misses::cpu0.data 14519656 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 14519656 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 15245510 # number of overall misses
< system.cpu0.dcache.overall_misses::total 15245510 # number of overall misses
< system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 102037717000 # number of ReadReq miss cycles
< system.cpu0.dcache.ReadReq_miss_latency::total 102037717000 # number of ReadReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 136358862160 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteReq_miss_latency::total 136358862160 # number of WriteReq miss cycles
< system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 72398693034 # number of WriteLineReq miss cycles
< system.cpu0.dcache.WriteLineReq_miss_latency::total 72398693034 # number of WriteLineReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4092900000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.LoadLockedReq_miss_latency::total 4092900000 # number of LoadLockedReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4230014500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondReq_miss_latency::total 4230014500 # number of StoreCondReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5283500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5283500 # number of StoreCondFailReq miss cycles
< system.cpu0.dcache.demand_miss_latency::cpu0.data 238396579160 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 238396579160 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 238396579160 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 238396579160 # number of overall miss cycles
< system.cpu0.dcache.ReadReq_accesses::cpu0.data 94832740 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.ReadReq_accesses::total 94832740 # number of ReadReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::cpu0.data 83963914 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.WriteReq_accesses::total 83963914 # number of WriteReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 953900 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.SoftPFReq_accesses::total 953900 # number of SoftPFReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1071197 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.WriteLineReq_accesses::total 1071197 # number of WriteLineReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2264049 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.LoadLockedReq_accesses::total 2264049 # number of LoadLockedReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2224672 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.StoreCondReq_accesses::total 2224672 # number of StoreCondReq accesses(hits+misses)
< system.cpu0.dcache.demand_accesses::cpu0.data 178796654 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 178796654 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 179750554 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 179750554 # number of overall (read+write) accesses
< system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.072713 # miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_miss_rate::total 0.072713 # miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.090802 # miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_miss_rate::total 0.090802 # miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760933 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760933 # miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.750623 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.WriteLineReq_miss_rate::total 0.750623 # miss rate for WriteLineReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.122453 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.122453 # miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089926 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089926 # miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081208 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.081208 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.084815 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.084815 # miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14797.581838 # average ReadReq miss latency
< system.cpu0.dcache.ReadReq_avg_miss_latency::total 14797.581838 # average ReadReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17885.266313 # average WriteReq miss latency
< system.cpu0.dcache.WriteReq_avg_miss_latency::total 17885.266313 # average WriteReq miss latency
< system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 90040.846243 # average WriteLineReq miss latency
< system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 90040.846243 # average WriteLineReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14763.021209 # average LoadLockedReq miss latency
< system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14763.021209 # average LoadLockedReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21144.257829 # average StoreCondReq miss latency
< system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21144.257829 # average StoreCondReq miss latency
---
> system.cpu0.commit.op_class_0::total 587627818 # Class of committed instruction
> system.cpu0.commit.bw_lim_events 14392988 # number cycles where commit BW limit reached
> system.cpu0.rob.rob_reads 1435053387 # The number of ROB reads
> system.cpu0.rob.rob_writes 1285071513 # The number of ROB writes
> system.cpu0.timesIdled 1102508 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu0.idleCycles 34173260 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu0.quiesceCycles 94009700955 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu0.committedInsts 500561663 # Number of Instructions Simulated
> system.cpu0.committedOps 587627818 # Number of Ops (including micro ops) Simulated
> system.cpu0.cpi 1.718187 # CPI: Cycles Per Instruction
> system.cpu0.cpi_total 1.718187 # CPI: Total CPI of All Threads
> system.cpu0.ipc 0.582009 # IPC: Instructions Per Cycle
> system.cpu0.ipc_total 0.582009 # IPC: Total IPC of All Threads
> system.cpu0.int_regfile_reads 737541509 # number of integer regfile reads
> system.cpu0.int_regfile_writes 438217894 # number of integer regfile writes
> system.cpu0.fp_regfile_reads 788412 # number of floating regfile reads
> system.cpu0.fp_regfile_writes 466436 # number of floating regfile writes
> system.cpu0.cc_regfile_reads 137084844 # number of cc regfile reads
> system.cpu0.cc_regfile_writes 137795028 # number of cc regfile writes
> system.cpu0.misc_regfile_reads 1439828550 # number of misc regfile reads
> system.cpu0.misc_regfile_writes 16463907 # number of misc regfile writes
> system.cpu0.dcache.tags.replacements 6421526 # number of replacements
> system.cpu0.dcache.tags.tagsinuse 508.135251 # Cycle average of tags in use
> system.cpu0.dcache.tags.total_refs 165251545 # Total number of references to valid blocks.
> system.cpu0.dcache.tags.sampled_refs 6422031 # Sample count of references to valid blocks.
> system.cpu0.dcache.tags.avg_refs 25.731976 # Average number of references to valid blocks.
> system.cpu0.dcache.tags.warmup_cycle 2962355000 # Cycle when the warmup percentage was hit.
> system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.135251 # Average occupied blocks per requestor
> system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992452 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_percent::total 0.992452 # Average percentage of cache occupancy
> system.cpu0.dcache.tags.occ_task_id_blocks::1024 505 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::1 452 # Occupied blocks per task id
> system.cpu0.dcache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id
> system.cpu0.dcache.tags.occ_task_id_percent::1024 0.986328 # Percentage of cache occupancy per task id
> system.cpu0.dcache.tags.tag_accesses 369713036 # Number of tag accesses
> system.cpu0.dcache.tags.data_accesses 369713036 # Number of data accesses
> system.cpu0.dcache.ReadReq_hits::cpu0.data 86498014 # number of ReadReq hits
> system.cpu0.dcache.ReadReq_hits::total 86498014 # number of ReadReq hits
> system.cpu0.dcache.WriteReq_hits::cpu0.data 73594824 # number of WriteReq hits
> system.cpu0.dcache.WriteReq_hits::total 73594824 # number of WriteReq hits
> system.cpu0.dcache.SoftPFReq_hits::cpu0.data 223952 # number of SoftPFReq hits
> system.cpu0.dcache.SoftPFReq_hits::total 223952 # number of SoftPFReq hits
> system.cpu0.dcache.WriteLineReq_hits::cpu0.data 261481 # number of WriteLineReq hits
> system.cpu0.dcache.WriteLineReq_hits::total 261481 # number of WriteLineReq hits
> system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1906554 # number of LoadLockedReq hits
> system.cpu0.dcache.LoadLockedReq_hits::total 1906554 # number of LoadLockedReq hits
> system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1959919 # number of StoreCondReq hits
> system.cpu0.dcache.StoreCondReq_hits::total 1959919 # number of StoreCondReq hits
> system.cpu0.dcache.demand_hits::cpu0.data 160092838 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 160092838 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 160316790 # number of overall hits
> system.cpu0.dcache.overall_hits::total 160316790 # number of overall hits
> system.cpu0.dcache.ReadReq_misses::cpu0.data 7115044 # number of ReadReq misses
> system.cpu0.dcache.ReadReq_misses::total 7115044 # number of ReadReq misses
> system.cpu0.dcache.WriteReq_misses::cpu0.data 7950326 # number of WriteReq misses
> system.cpu0.dcache.WriteReq_misses::total 7950326 # number of WriteReq misses
> system.cpu0.dcache.SoftPFReq_misses::cpu0.data 760555 # number of SoftPFReq misses
> system.cpu0.dcache.SoftPFReq_misses::total 760555 # number of SoftPFReq misses
> system.cpu0.dcache.WriteLineReq_misses::cpu0.data 841390 # number of WriteLineReq misses
> system.cpu0.dcache.WriteLineReq_misses::total 841390 # number of WriteLineReq misses
> system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 287295 # number of LoadLockedReq misses
> system.cpu0.dcache.LoadLockedReq_misses::total 287295 # number of LoadLockedReq misses
> system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195310 # number of StoreCondReq misses
> system.cpu0.dcache.StoreCondReq_misses::total 195310 # number of StoreCondReq misses
> system.cpu0.dcache.demand_misses::cpu0.data 15065370 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 15065370 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 15825925 # number of overall misses
> system.cpu0.dcache.overall_misses::total 15825925 # number of overall misses
> system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 123619441500 # number of ReadReq miss cycles
> system.cpu0.dcache.ReadReq_miss_latency::total 123619441500 # number of ReadReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 174765170319 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteReq_miss_latency::total 174765170319 # number of WriteReq miss cycles
> system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 99329075406 # number of WriteLineReq miss cycles
> system.cpu0.dcache.WriteLineReq_miss_latency::total 99329075406 # number of WriteLineReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4513560000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.LoadLockedReq_miss_latency::total 4513560000 # number of LoadLockedReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4763112500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondReq_miss_latency::total 4763112500 # number of StoreCondReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4991000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4991000 # number of StoreCondFailReq miss cycles
> system.cpu0.dcache.demand_miss_latency::cpu0.data 298384611819 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 298384611819 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 298384611819 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 298384611819 # number of overall miss cycles
> system.cpu0.dcache.ReadReq_accesses::cpu0.data 93613058 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.ReadReq_accesses::total 93613058 # number of ReadReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::cpu0.data 81545150 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.WriteReq_accesses::total 81545150 # number of WriteReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 984507 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.SoftPFReq_accesses::total 984507 # number of SoftPFReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1102871 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.WriteLineReq_accesses::total 1102871 # number of WriteLineReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2193849 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.LoadLockedReq_accesses::total 2193849 # number of LoadLockedReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2155229 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.StoreCondReq_accesses::total 2155229 # number of StoreCondReq accesses(hits+misses)
> system.cpu0.dcache.demand_accesses::cpu0.data 175158208 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 175158208 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 176142715 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 176142715 # number of overall (read+write) accesses
> system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.076005 # miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_miss_rate::total 0.076005 # miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.097496 # miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_miss_rate::total 0.097496 # miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.772524 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_miss_rate::total 0.772524 # miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.762909 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.WriteLineReq_miss_rate::total 0.762909 # miss rate for WriteLineReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.130955 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.130955 # miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.090621 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_miss_rate::total 0.090621 # miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086010 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.086010 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.089847 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.089847 # miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17374.374846 # average ReadReq miss latency
> system.cpu0.dcache.ReadReq_avg_miss_latency::total 17374.374846 # average ReadReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21982.138886 # average WriteReq miss latency
> system.cpu0.dcache.WriteReq_avg_miss_latency::total 21982.138886 # average WriteReq miss latency
> system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 118053.548778 # average WriteLineReq miss latency
> system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 118053.548778 # average WriteLineReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15710.541430 # average LoadLockedReq miss latency
> system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15710.541430 # average LoadLockedReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24387.448159 # average StoreCondReq miss latency
> system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24387.448159 # average StoreCondReq miss latency
1018,1027c1013,1022
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16418.886175 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 16418.886175 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15637.166560 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 15637.166560 # average overall miss latency
< system.cpu0.dcache.blocked_cycles::no_mshrs 22487796 # number of cycles access was blocked
< system.cpu0.dcache.blocked_cycles::no_targets 20190626 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_mshrs 731543 # number of cycles access was blocked
< system.cpu0.dcache.blocked::no_targets 741822 # number of cycles access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_mshrs 30.740224 # average number of cycles each access was blocked
< system.cpu0.dcache.avg_blocked_cycles::no_targets 27.217616 # average number of cycles each access was blocked
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19805.992937 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 19805.992937 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18854.165669 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 18854.165669 # average overall miss latency
> system.cpu0.dcache.blocked_cycles::no_mshrs 31101776 # number of cycles access was blocked
> system.cpu0.dcache.blocked_cycles::no_targets 27008277 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_mshrs 772694 # number of cycles access was blocked
> system.cpu0.dcache.blocked::no_targets 787427 # number of cycles access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.251090 # average number of cycles each access was blocked
> system.cpu0.dcache.avg_blocked_cycles::no_targets 34.299404 # average number of cycles each access was blocked
1030,1117c1025,1112
< system.cpu0.dcache.writebacks::writebacks 4210788 # number of writebacks
< system.cpu0.dcache.writebacks::total 4210788 # number of writebacks
< system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3513002 # number of ReadReq MSHR hits
< system.cpu0.dcache.ReadReq_mshr_hits::total 3513002 # number of ReadReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6114706 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteReq_mshr_hits::total 6114706 # number of WriteReq MSHR hits
< system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4602 # number of WriteLineReq MSHR hits
< system.cpu0.dcache.WriteLineReq_mshr_hits::total 4602 # number of WriteLineReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 143782 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.LoadLockedReq_mshr_hits::total 143782 # number of LoadLockedReq MSHR hits
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 9627708 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 9627708 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 9627708 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 9627708 # number of overall MSHR hits
< system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3382565 # number of ReadReq MSHR misses
< system.cpu0.dcache.ReadReq_mshr_misses::total 3382565 # number of ReadReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1509383 # number of WriteReq MSHR misses
< system.cpu0.dcache.WriteReq_mshr_misses::total 1509383 # number of WriteReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 718663 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.SoftPFReq_mshr_misses::total 718663 # number of SoftPFReq MSHR misses
< system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 799463 # number of WriteLineReq MSHR misses
< system.cpu0.dcache.WriteLineReq_mshr_misses::total 799463 # number of WriteLineReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 133458 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.LoadLockedReq_mshr_misses::total 133458 # number of LoadLockedReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200041 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.StoreCondReq_mshr_misses::total 200041 # number of StoreCondReq MSHR misses
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 4891948 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 4891948 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 5610611 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 5610611 # number of overall MSHR misses
< system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32342 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32342 # number of ReadReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31823 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31823 # number of WriteReq MSHR uncacheable
< system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 64165 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.overall_mshr_uncacheable_misses::total 64165 # number of overall MSHR uncacheable misses
< system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 48415097500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_miss_latency::total 48415097500 # number of ReadReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29340240291 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29340240291 # number of WriteReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16426692500 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16426692500 # number of SoftPFReq MSHR miss cycles
< system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 71393732534 # number of WriteLineReq MSHR miss cycles
< system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 71393732534 # number of WriteLineReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1844525500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1844525500 # number of LoadLockedReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4030091500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4030091500 # number of StoreCondReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5165500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5165500 # number of StoreCondFailReq MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 77755337791 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 77755337791 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94182030291 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 94182030291 # number of overall MSHR miss cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5817539000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5817539000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5518707000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5518707000 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11336246000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11336246000 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035669 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035669 # mshr miss rate for ReadReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017977 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017977 # mshr miss rate for WriteReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.753394 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.753394 # mshr miss rate for SoftPFReq accesses
< system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746327 # mshr miss rate for WriteLineReq accesses
< system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746327 # mshr miss rate for WriteLineReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058947 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058947 # mshr miss rate for LoadLockedReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089919 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089919 # mshr miss rate for StoreCondReq accesses
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027360 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.027360 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031213 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.031213 # mshr miss rate for overall accesses
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14313.131455 # average ReadReq mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14313.131455 # average ReadReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19438.565487 # average WriteReq mshr miss latency
< system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19438.565487 # average WriteReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22857.295422 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22857.295422 # average SoftPFReq mshr miss latency
< system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 89302.109709 # average WriteLineReq mshr miss latency
< system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 89302.109709 # average WriteLineReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13821.018598 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13821.018598 # average LoadLockedReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20146.327503 # average StoreCondReq mshr miss latency
< system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20146.327503 # average StoreCondReq mshr miss latency
---
> system.cpu0.dcache.writebacks::writebacks 4324525 # number of writebacks
> system.cpu0.dcache.writebacks::total 4324525 # number of writebacks
> system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3632070 # number of ReadReq MSHR hits
> system.cpu0.dcache.ReadReq_mshr_hits::total 3632070 # number of ReadReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6394266 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteReq_mshr_hits::total 6394266 # number of WriteReq MSHR hits
> system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4384 # number of WriteLineReq MSHR hits
> system.cpu0.dcache.WriteLineReq_mshr_hits::total 4384 # number of WriteLineReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 147311 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.LoadLockedReq_mshr_hits::total 147311 # number of LoadLockedReq MSHR hits
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 10026336 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 10026336 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 10026336 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 10026336 # number of overall MSHR hits
> system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3482974 # number of ReadReq MSHR misses
> system.cpu0.dcache.ReadReq_mshr_misses::total 3482974 # number of ReadReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1556060 # number of WriteReq MSHR misses
> system.cpu0.dcache.WriteReq_mshr_misses::total 1556060 # number of WriteReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 753575 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.SoftPFReq_mshr_misses::total 753575 # number of SoftPFReq MSHR misses
> system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 837006 # number of WriteLineReq MSHR misses
> system.cpu0.dcache.WriteLineReq_mshr_misses::total 837006 # number of WriteLineReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 139984 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.LoadLockedReq_mshr_misses::total 139984 # number of LoadLockedReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195309 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.StoreCondReq_mshr_misses::total 195309 # number of StoreCondReq MSHR misses
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 5039034 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 5039034 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 5792609 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 5792609 # number of overall MSHR misses
> system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31951 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31951 # number of ReadReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31485 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31485 # number of WriteReq MSHR uncacheable
> system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 63436 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.overall_mshr_uncacheable_misses::total 63436 # number of overall MSHR uncacheable misses
> system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 56753773500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_miss_latency::total 56753773500 # number of ReadReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 38838935578 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.WriteReq_mshr_miss_latency::total 38838935578 # number of WriteReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 19682576500 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 19682576500 # number of SoftPFReq MSHR miss cycles
> system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 98248508406 # number of WriteLineReq MSHR miss cycles
> system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 98248508406 # number of WriteLineReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1973900000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1973900000 # number of LoadLockedReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4567861500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4567861500 # number of StoreCondReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4933000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4933000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95592709078 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 95592709078 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115275285578 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 115275285578 # number of overall MSHR miss cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5771319500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5771319500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5597630000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5597630000 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11368949500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11368949500 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037206 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037206 # mshr miss rate for ReadReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019082 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019082 # mshr miss rate for WriteReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.765434 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.765434 # mshr miss rate for SoftPFReq accesses
> system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.758934 # mshr miss rate for WriteLineReq accesses
> system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.758934 # mshr miss rate for WriteLineReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063807 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063807 # mshr miss rate for LoadLockedReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.090621 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.090621 # mshr miss rate for StoreCondReq accesses
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028768 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.028768 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032886 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.032886 # mshr miss rate for overall accesses
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16294.630250 # average ReadReq mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16294.630250 # average ReadReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24959.793053 # average WriteReq mshr miss latency
> system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24959.793053 # average WriteReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26118.935076 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26118.935076 # average SoftPFReq mshr miss latency
> system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 117380.889033 # average WriteLineReq mshr miss latency
> system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 117380.889033 # average WriteLineReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14100.897245 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14100.897245 # average LoadLockedReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23387.869991 # average StoreCondReq mshr miss latency
> system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23387.869991 # average StoreCondReq mshr miss latency
1120,1129c1115,1124
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15894.555255 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15894.555255 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16786.412441 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16786.412441 # average overall mshr miss latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 179875.672500 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 179875.672500 # average ReadReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173418.816579 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173418.816579 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 176673.357750 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176673.357750 # average overall mshr uncacheable latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18970.443358 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18970.443358 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19900.408534 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19900.408534 # average overall mshr miss latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180630.324559 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180630.324559 # average ReadReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 177787.200254 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 177787.200254 # average WriteReq mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179219.205183 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179219.205183 # average overall mshr uncacheable latency
1131,1139c1126,1134
< system.cpu0.icache.tags.replacements 6407339 # number of replacements
< system.cpu0.icache.tags.tagsinuse 511.955601 # Cycle average of tags in use
< system.cpu0.icache.tags.total_refs 224970066 # Total number of references to valid blocks.
< system.cpu0.icache.tags.sampled_refs 6407851 # Sample count of references to valid blocks.
< system.cpu0.icache.tags.avg_refs 35.108505 # Average number of references to valid blocks.
< system.cpu0.icache.tags.warmup_cycle 17322639000 # Cycle when the warmup percentage was hit.
< system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.955601 # Average occupied blocks per requestor
< system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999913 # Average percentage of cache occupancy
< system.cpu0.icache.tags.occ_percent::total 0.999913 # Average percentage of cache occupancy
---
> system.cpu0.icache.tags.replacements 6358728 # number of replacements
> system.cpu0.icache.tags.tagsinuse 511.935177 # Cycle average of tags in use
> system.cpu0.icache.tags.total_refs 223756411 # Total number of references to valid blocks.
> system.cpu0.icache.tags.sampled_refs 6359240 # Sample count of references to valid blocks.
> system.cpu0.icache.tags.avg_refs 35.186030 # Average number of references to valid blocks.
> system.cpu0.icache.tags.warmup_cycle 22852216000 # Cycle when the warmup percentage was hit.
> system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.935177 # Average occupied blocks per requestor
> system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999873 # Average percentage of cache occupancy
> system.cpu0.icache.tags.occ_percent::total 0.999873 # Average percentage of cache occupancy
1141,1143c1136,1137
< system.cpu0.icache.tags.age_task_id_blocks_1024::0 330 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::1 45 # Occupied blocks per task id
< system.cpu0.icache.tags.age_task_id_blocks_1024::2 137 # Occupied blocks per task id
---
> system.cpu0.icache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id
> system.cpu0.icache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id
1145,1188c1139,1182
< system.cpu0.icache.tags.tag_accesses 469899085 # Number of tag accesses
< system.cpu0.icache.tags.data_accesses 469899085 # Number of data accesses
< system.cpu0.icache.ReadReq_hits::cpu0.inst 224970066 # number of ReadReq hits
< system.cpu0.icache.ReadReq_hits::total 224970066 # number of ReadReq hits
< system.cpu0.icache.demand_hits::cpu0.inst 224970066 # number of demand (read+write) hits
< system.cpu0.icache.demand_hits::total 224970066 # number of demand (read+write) hits
< system.cpu0.icache.overall_hits::cpu0.inst 224970066 # number of overall hits
< system.cpu0.icache.overall_hits::total 224970066 # number of overall hits
< system.cpu0.icache.ReadReq_misses::cpu0.inst 6775541 # number of ReadReq misses
< system.cpu0.icache.ReadReq_misses::total 6775541 # number of ReadReq misses
< system.cpu0.icache.demand_misses::cpu0.inst 6775541 # number of demand (read+write) misses
< system.cpu0.icache.demand_misses::total 6775541 # number of demand (read+write) misses
< system.cpu0.icache.overall_misses::cpu0.inst 6775541 # number of overall misses
< system.cpu0.icache.overall_misses::total 6775541 # number of overall misses
< system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 71079582898 # number of ReadReq miss cycles
< system.cpu0.icache.ReadReq_miss_latency::total 71079582898 # number of ReadReq miss cycles
< system.cpu0.icache.demand_miss_latency::cpu0.inst 71079582898 # number of demand (read+write) miss cycles
< system.cpu0.icache.demand_miss_latency::total 71079582898 # number of demand (read+write) miss cycles
< system.cpu0.icache.overall_miss_latency::cpu0.inst 71079582898 # number of overall miss cycles
< system.cpu0.icache.overall_miss_latency::total 71079582898 # number of overall miss cycles
< system.cpu0.icache.ReadReq_accesses::cpu0.inst 231745607 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.ReadReq_accesses::total 231745607 # number of ReadReq accesses(hits+misses)
< system.cpu0.icache.demand_accesses::cpu0.inst 231745607 # number of demand (read+write) accesses
< system.cpu0.icache.demand_accesses::total 231745607 # number of demand (read+write) accesses
< system.cpu0.icache.overall_accesses::cpu0.inst 231745607 # number of overall (read+write) accesses
< system.cpu0.icache.overall_accesses::total 231745607 # number of overall (read+write) accesses
< system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029237 # miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_miss_rate::total 0.029237 # miss rate for ReadReq accesses
< system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029237 # miss rate for demand accesses
< system.cpu0.icache.demand_miss_rate::total 0.029237 # miss rate for demand accesses
< system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029237 # miss rate for overall accesses
< system.cpu0.icache.overall_miss_rate::total 0.029237 # miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10490.613650 # average ReadReq miss latency
< system.cpu0.icache.ReadReq_avg_miss_latency::total 10490.613650 # average ReadReq miss latency
< system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10490.613650 # average overall miss latency
< system.cpu0.icache.demand_avg_miss_latency::total 10490.613650 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10490.613650 # average overall miss latency
< system.cpu0.icache.overall_avg_miss_latency::total 10490.613650 # average overall miss latency
< system.cpu0.icache.blocked_cycles::no_mshrs 10215206 # number of cycles access was blocked
< system.cpu0.icache.blocked_cycles::no_targets 732 # number of cycles access was blocked
< system.cpu0.icache.blocked::no_mshrs 767906 # number of cycles access was blocked
< system.cpu0.icache.blocked::no_targets 9 # number of cycles access was blocked
< system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.302678 # average number of cycles each access was blocked
< system.cpu0.icache.avg_blocked_cycles::no_targets 81.333333 # average number of cycles each access was blocked
---
> system.cpu0.icache.tags.tag_accesses 467353436 # Number of tag accesses
> system.cpu0.icache.tags.data_accesses 467353436 # Number of data accesses
> system.cpu0.icache.ReadReq_hits::cpu0.inst 223756411 # number of ReadReq hits
> system.cpu0.icache.ReadReq_hits::total 223756411 # number of ReadReq hits
> system.cpu0.icache.demand_hits::cpu0.inst 223756411 # number of demand (read+write) hits
> system.cpu0.icache.demand_hits::total 223756411 # number of demand (read+write) hits
> system.cpu0.icache.overall_hits::cpu0.inst 223756411 # number of overall hits
> system.cpu0.icache.overall_hits::total 223756411 # number of overall hits
> system.cpu0.icache.ReadReq_misses::cpu0.inst 6740667 # number of ReadReq misses
> system.cpu0.icache.ReadReq_misses::total 6740667 # number of ReadReq misses
> system.cpu0.icache.demand_misses::cpu0.inst 6740667 # number of demand (read+write) misses
> system.cpu0.icache.demand_misses::total 6740667 # number of demand (read+write) misses
> system.cpu0.icache.overall_misses::cpu0.inst 6740667 # number of overall misses
> system.cpu0.icache.overall_misses::total 6740667 # number of overall misses
> system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 78361220616 # number of ReadReq miss cycles
> system.cpu0.icache.ReadReq_miss_latency::total 78361220616 # number of ReadReq miss cycles
> system.cpu0.icache.demand_miss_latency::cpu0.inst 78361220616 # number of demand (read+write) miss cycles
> system.cpu0.icache.demand_miss_latency::total 78361220616 # number of demand (read+write) miss cycles
> system.cpu0.icache.overall_miss_latency::cpu0.inst 78361220616 # number of overall miss cycles
> system.cpu0.icache.overall_miss_latency::total 78361220616 # number of overall miss cycles
> system.cpu0.icache.ReadReq_accesses::cpu0.inst 230497078 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.ReadReq_accesses::total 230497078 # number of ReadReq accesses(hits+misses)
> system.cpu0.icache.demand_accesses::cpu0.inst 230497078 # number of demand (read+write) accesses
> system.cpu0.icache.demand_accesses::total 230497078 # number of demand (read+write) accesses
> system.cpu0.icache.overall_accesses::cpu0.inst 230497078 # number of overall (read+write) accesses
> system.cpu0.icache.overall_accesses::total 230497078 # number of overall (read+write) accesses
> system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029244 # miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_miss_rate::total 0.029244 # miss rate for ReadReq accesses
> system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029244 # miss rate for demand accesses
> system.cpu0.icache.demand_miss_rate::total 0.029244 # miss rate for demand accesses
> system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029244 # miss rate for overall accesses
> system.cpu0.icache.overall_miss_rate::total 0.029244 # miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11625.143419 # average ReadReq miss latency
> system.cpu0.icache.ReadReq_avg_miss_latency::total 11625.143419 # average ReadReq miss latency
> system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11625.143419 # average overall miss latency
> system.cpu0.icache.demand_avg_miss_latency::total 11625.143419 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11625.143419 # average overall miss latency
> system.cpu0.icache.overall_avg_miss_latency::total 11625.143419 # average overall miss latency
> system.cpu0.icache.blocked_cycles::no_mshrs 12527067 # number of cycles access was blocked
> system.cpu0.icache.blocked_cycles::no_targets 1547 # number of cycles access was blocked
> system.cpu0.icache.blocked::no_mshrs 814769 # number of cycles access was blocked
> system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked
> system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.374992 # average number of cycles each access was blocked
> system.cpu0.icache.avg_blocked_cycles::no_targets 119 # average number of cycles each access was blocked
1191,1202c1185,1196
< system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 367670 # number of ReadReq MSHR hits
< system.cpu0.icache.ReadReq_mshr_hits::total 367670 # number of ReadReq MSHR hits
< system.cpu0.icache.demand_mshr_hits::cpu0.inst 367670 # number of demand (read+write) MSHR hits
< system.cpu0.icache.demand_mshr_hits::total 367670 # number of demand (read+write) MSHR hits
< system.cpu0.icache.overall_mshr_hits::cpu0.inst 367670 # number of overall MSHR hits
< system.cpu0.icache.overall_mshr_hits::total 367670 # number of overall MSHR hits
< system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6407871 # number of ReadReq MSHR misses
< system.cpu0.icache.ReadReq_mshr_misses::total 6407871 # number of ReadReq MSHR misses
< system.cpu0.icache.demand_mshr_misses::cpu0.inst 6407871 # number of demand (read+write) MSHR misses
< system.cpu0.icache.demand_mshr_misses::total 6407871 # number of demand (read+write) MSHR misses
< system.cpu0.icache.overall_mshr_misses::cpu0.inst 6407871 # number of overall MSHR misses
< system.cpu0.icache.overall_mshr_misses::total 6407871 # number of overall MSHR misses
---
> system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 381387 # number of ReadReq MSHR hits
> system.cpu0.icache.ReadReq_mshr_hits::total 381387 # number of ReadReq MSHR hits
> system.cpu0.icache.demand_mshr_hits::cpu0.inst 381387 # number of demand (read+write) MSHR hits
> system.cpu0.icache.demand_mshr_hits::total 381387 # number of demand (read+write) MSHR hits
> system.cpu0.icache.overall_mshr_hits::cpu0.inst 381387 # number of overall MSHR hits
> system.cpu0.icache.overall_mshr_hits::total 381387 # number of overall MSHR hits
> system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6359280 # number of ReadReq MSHR misses
> system.cpu0.icache.ReadReq_mshr_misses::total 6359280 # number of ReadReq MSHR misses
> system.cpu0.icache.demand_mshr_misses::cpu0.inst 6359280 # number of demand (read+write) MSHR misses
> system.cpu0.icache.demand_mshr_misses::total 6359280 # number of demand (read+write) MSHR misses
> system.cpu0.icache.overall_mshr_misses::cpu0.inst 6359280 # number of overall MSHR misses
> system.cpu0.icache.overall_mshr_misses::total 6359280 # number of overall MSHR misses
1207,1232c1201,1226
< system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64388034562 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_miss_latency::total 64388034562 # number of ReadReq MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64388034562 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.demand_mshr_miss_latency::total 64388034562 # number of demand (read+write) MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64388034562 # number of overall MSHR miss cycles
< system.cpu0.icache.overall_mshr_miss_latency::total 64388034562 # number of overall MSHR miss cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1863746498 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1863746498 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1863746498 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.overall_mshr_uncacheable_latency::total 1863746498 # number of overall MSHR uncacheable cycles
< system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027650 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027650 # mshr miss rate for ReadReq accesses
< system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027650 # mshr miss rate for demand accesses
< system.cpu0.icache.demand_mshr_miss_rate::total 0.027650 # mshr miss rate for demand accesses
< system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027650 # mshr miss rate for overall accesses
< system.cpu0.icache.overall_mshr_miss_rate::total 0.027650 # mshr miss rate for overall accesses
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10048.272595 # average ReadReq mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10048.272595 # average ReadReq mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10048.272595 # average overall mshr miss latency
< system.cpu0.icache.demand_avg_mshr_miss_latency::total 10048.272595 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10048.272595 # average overall mshr miss latency
< system.cpu0.icache.overall_avg_mshr_miss_latency::total 10048.272595 # average overall mshr miss latency
< system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373 # average ReadReq mshr uncacheable latency
< system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87524.490373 # average ReadReq mshr uncacheable latency
< system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373 # average overall mshr uncacheable latency
< system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87524.490373 # average overall mshr uncacheable latency
---
> system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 70398317173 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_miss_latency::total 70398317173 # number of ReadReq MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 70398317173 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.demand_mshr_miss_latency::total 70398317173 # number of demand (read+write) MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 70398317173 # number of overall MSHR miss cycles
> system.cpu0.icache.overall_mshr_miss_latency::total 70398317173 # number of overall MSHR miss cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939725498 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939725498 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939725498 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939725498 # number of overall MSHR uncacheable cycles
> system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027589 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027589 # mshr miss rate for ReadReq accesses
> system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027589 # mshr miss rate for demand accesses
> system.cpu0.icache.demand_mshr_miss_rate::total 0.027589 # mshr miss rate for demand accesses
> system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027589 # mshr miss rate for overall accesses
> system.cpu0.icache.overall_mshr_miss_rate::total 0.027589 # mshr miss rate for overall accesses
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11070.171021 # average ReadReq mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11070.171021 # average ReadReq mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11070.171021 # average overall mshr miss latency
> system.cpu0.icache.demand_avg_mshr_miss_latency::total 11070.171021 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11070.171021 # average overall mshr miss latency
> system.cpu0.icache.overall_avg_mshr_miss_latency::total 11070.171021 # average overall mshr miss latency
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138054.170095 # average ReadReq mshr uncacheable latency
> system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138054.170095 # average ReadReq mshr uncacheable latency
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138054.170095 # average overall mshr uncacheable latency
> system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138054.170095 # average overall mshr uncacheable latency
1234,1236c1228,1230
< system.cpu0.l2cache.prefetcher.num_hwpf_issued 8228747 # number of hwpf issued
< system.cpu0.l2cache.prefetcher.pfIdentified 8235731 # number of prefetch candidates identified
< system.cpu0.l2cache.prefetcher.pfBufferHit 6331 # number of redundant prefetches already in prefetch queue
---
> system.cpu0.l2cache.prefetcher.num_hwpf_issued 8863203 # number of hwpf issued
> system.cpu0.l2cache.prefetcher.pfIdentified 8872058 # number of prefetch candidates identified
> system.cpu0.l2cache.prefetcher.pfBufferHit 7949 # number of redundant prefetches already in prefetch queue
1239,1261c1233,1255
< system.cpu0.l2cache.prefetcher.pfSpanPage 1065389 # number of prefetches not generated due to page crossing
< system.cpu0.l2cache.tags.replacements 2775717 # number of replacements
< system.cpu0.l2cache.tags.tagsinuse 16223.891094 # Cycle average of tags in use
< system.cpu0.l2cache.tags.total_refs 21402394 # Total number of references to valid blocks.
< system.cpu0.l2cache.tags.sampled_refs 2791423 # Sample count of references to valid blocks.
< system.cpu0.l2cache.tags.avg_refs 7.667198 # Average number of references to valid blocks.
< system.cpu0.l2cache.tags.warmup_cycle 16000650500 # Cycle when the warmup percentage was hit.
< system.cpu0.l2cache.tags.occ_blocks::writebacks 7115.603862 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 78.900810 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 84.351377 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4177.499611 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3867.898858 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 899.636576 # Average occupied blocks per requestor
< system.cpu0.l2cache.tags.occ_percent::writebacks 0.434302 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004816 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005148 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.254974 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.236078 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.054909 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_percent::total 0.990228 # Average percentage of cache occupancy
< system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1370 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1023 105 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14231 # Occupied blocks per task id
---
> system.cpu0.l2cache.prefetcher.pfSpanPage 1112734 # number of prefetches not generated due to page crossing
> system.cpu0.l2cache.tags.replacements 2914685 # number of replacements
> system.cpu0.l2cache.tags.tagsinuse 16233.717637 # Cycle average of tags in use
> system.cpu0.l2cache.tags.total_refs 21584031 # Total number of references to valid blocks.
> system.cpu0.l2cache.tags.sampled_refs 2930348 # Sample count of references to valid blocks.
> system.cpu0.l2cache.tags.avg_refs 7.365689 # Average number of references to valid blocks.
> system.cpu0.l2cache.tags.warmup_cycle 21271828500 # Cycle when the warmup percentage was hit.
> system.cpu0.l2cache.tags.occ_blocks::writebacks 7511.186177 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 88.364339 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 96.668630 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4222.815045 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3387.843530 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 926.839916 # Average occupied blocks per requestor
> system.cpu0.l2cache.tags.occ_percent::writebacks 0.458446 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.005393 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005900 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.257740 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.206778 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056570 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_percent::total 0.990827 # Average percentage of cache occupancy
> system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1335 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1023 99 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14229 # Occupied blocks per task id
1263,1266c1257,1259
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 230 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 633 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 412 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
---
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 255 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 575 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 410 # Occupied blocks per task id
1268,1310c1261,1302
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 79 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 219 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 777 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4691 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4874 # Occupied blocks per task id
< system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3670 # Occupied blocks per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.083618 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006409 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.868591 # Percentage of cache occupancy per task id
< system.cpu0.l2cache.tags.tag_accesses 429969971 # Number of tag accesses
< system.cpu0.l2cache.tags.data_accesses 429969971 # Number of data accesses
< system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 556706 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 187543 # number of ReadReq hits
< system.cpu0.l2cache.ReadReq_hits::total 744249 # number of ReadReq hits
< system.cpu0.l2cache.Writeback_hits::writebacks 4210780 # number of Writeback hits
< system.cpu0.l2cache.Writeback_hits::total 4210780 # number of Writeback hits
< system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 112692 # number of UpgradeReq hits
< system.cpu0.l2cache.UpgradeReq_hits::total 112692 # number of UpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 36481 # number of SCUpgradeReq hits
< system.cpu0.l2cache.SCUpgradeReq_hits::total 36481 # number of SCUpgradeReq hits
< system.cpu0.l2cache.ReadExReq_hits::cpu0.data 982818 # number of ReadExReq hits
< system.cpu0.l2cache.ReadExReq_hits::total 982818 # number of ReadExReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5746953 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadCleanReq_hits::total 5746953 # number of ReadCleanReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3150457 # number of ReadSharedReq hits
< system.cpu0.l2cache.ReadSharedReq_hits::total 3150457 # number of ReadSharedReq hits
< system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 210597 # number of InvalidateReq hits
< system.cpu0.l2cache.InvalidateReq_hits::total 210597 # number of InvalidateReq hits
< system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 556706 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.itb.walker 187543 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.inst 5746953 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::cpu0.data 4133275 # number of demand (read+write) hits
< system.cpu0.l2cache.demand_hits::total 10624477 # number of demand (read+write) hits
< system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 556706 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.itb.walker 187543 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.inst 5746953 # number of overall hits
< system.cpu0.l2cache.overall_hits::cpu0.data 4133275 # number of overall hits
< system.cpu0.l2cache.overall_hits::total 10624477 # number of overall hits
< system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12834 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9490 # number of ReadReq misses
< system.cpu0.l2cache.ReadReq_misses::total 22324 # number of ReadReq misses
---
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 74 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 796 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4905 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4871 # Occupied blocks per task id
> system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3657 # Occupied blocks per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.081482 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006042 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.868469 # Percentage of cache occupancy per task id
> system.cpu0.l2cache.tags.tag_accesses 436831326 # Number of tag accesses
> system.cpu0.l2cache.tags.data_accesses 436831326 # Number of data accesses
> system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 607592 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 191548 # number of ReadReq hits
> system.cpu0.l2cache.ReadReq_hits::total 799140 # number of ReadReq hits
> system.cpu0.l2cache.Writeback_hits::writebacks 4324517 # number of Writeback hits
> system.cpu0.l2cache.Writeback_hits::total 4324517 # number of Writeback hits
> system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 114203 # number of UpgradeReq hits
> system.cpu0.l2cache.UpgradeReq_hits::total 114203 # number of UpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 36958 # number of SCUpgradeReq hits
> system.cpu0.l2cache.SCUpgradeReq_hits::total 36958 # number of SCUpgradeReq hits
> system.cpu0.l2cache.ReadExReq_hits::cpu0.data 970189 # number of ReadExReq hits
> system.cpu0.l2cache.ReadExReq_hits::total 970189 # number of ReadExReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5673182 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadCleanReq_hits::total 5673182 # number of ReadCleanReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3273926 # number of ReadSharedReq hits
> system.cpu0.l2cache.ReadSharedReq_hits::total 3273926 # number of ReadSharedReq hits
> system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 211331 # number of InvalidateReq hits
> system.cpu0.l2cache.InvalidateReq_hits::total 211331 # number of InvalidateReq hits
> system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 607592 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.itb.walker 191548 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.inst 5673182 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::cpu0.data 4244115 # number of demand (read+write) hits
> system.cpu0.l2cache.demand_hits::total 10716437 # number of demand (read+write) hits
> system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 607592 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.itb.walker 191548 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.inst 5673182 # number of overall hits
> system.cpu0.l2cache.overall_hits::cpu0.data 4244115 # number of overall hits
> system.cpu0.l2cache.overall_hits::total 10716437 # number of overall hits
> system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13844 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10570 # number of ReadReq misses
> system.cpu0.l2cache.ReadReq_misses::total 24414 # number of ReadReq misses
1313,1395c1305,1387
< system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 137568 # number of UpgradeReq misses
< system.cpu0.l2cache.UpgradeReq_misses::total 137568 # number of UpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 163550 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeReq_misses::total 163550 # number of SCUpgradeReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 10 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.SCUpgradeFailReq_misses::total 10 # number of SCUpgradeFailReq misses
< system.cpu0.l2cache.ReadExReq_misses::cpu0.data 289201 # number of ReadExReq misses
< system.cpu0.l2cache.ReadExReq_misses::total 289201 # number of ReadExReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 660894 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadCleanReq_misses::total 660894 # number of ReadCleanReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1080002 # number of ReadSharedReq misses
< system.cpu0.l2cache.ReadSharedReq_misses::total 1080002 # number of ReadSharedReq misses
< system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 587441 # number of InvalidateReq misses
< system.cpu0.l2cache.InvalidateReq_misses::total 587441 # number of InvalidateReq misses
< system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12834 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9490 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.inst 660894 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::cpu0.data 1369203 # number of demand (read+write) misses
< system.cpu0.l2cache.demand_misses::total 2052421 # number of demand (read+write) misses
< system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12834 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9490 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.inst 660894 # number of overall misses
< system.cpu0.l2cache.overall_misses::cpu0.data 1369203 # number of overall misses
< system.cpu0.l2cache.overall_misses::total 2052421 # number of overall misses
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 512484500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 411800500 # number of ReadReq miss cycles
< system.cpu0.l2cache.ReadReq_miss_latency::total 924285000 # number of ReadReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2995269498 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.UpgradeReq_miss_latency::total 2995269498 # number of UpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3391228500 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3391228500 # number of SCUpgradeReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4985998 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4985998 # number of SCUpgradeFailReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15723716499 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadExReq_miss_latency::total 15723716499 # number of ReadExReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 20507752998 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadCleanReq_miss_latency::total 20507752998 # number of ReadCleanReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 39428872479 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.ReadSharedReq_miss_latency::total 39428872479 # number of ReadSharedReq miss cycles
< system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 67940497999 # number of InvalidateReq miss cycles
< system.cpu0.l2cache.InvalidateReq_miss_latency::total 67940497999 # number of InvalidateReq miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 512484500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 411800500 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.inst 20507752998 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::cpu0.data 55152588978 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.demand_miss_latency::total 76584626976 # number of demand (read+write) miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 512484500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 411800500 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.inst 20507752998 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::cpu0.data 55152588978 # number of overall miss cycles
< system.cpu0.l2cache.overall_miss_latency::total 76584626976 # number of overall miss cycles
< system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 569540 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 197033 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.ReadReq_accesses::total 766573 # number of ReadReq accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::writebacks 4210782 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.Writeback_accesses::total 4210782 # number of Writeback accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 250260 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.UpgradeReq_accesses::total 250260 # number of UpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 200031 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeReq_accesses::total 200031 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 10 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1272019 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadExReq_accesses::total 1272019 # number of ReadExReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6407847 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadCleanReq_accesses::total 6407847 # number of ReadCleanReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4230459 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.ReadSharedReq_accesses::total 4230459 # number of ReadSharedReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 798038 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.InvalidateReq_accesses::total 798038 # number of InvalidateReq accesses(hits+misses)
< system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 569540 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 197033 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.inst 6407847 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::cpu0.data 5502478 # number of demand (read+write) accesses
< system.cpu0.l2cache.demand_accesses::total 12676898 # number of demand (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 569540 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 197033 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.inst 6407847 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::cpu0.data 5502478 # number of overall (read+write) accesses
< system.cpu0.l2cache.overall_accesses::total 12676898 # number of overall (read+write) accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.022534 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.048165 # miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_miss_rate::total 0.029122 # miss rate for ReadReq accesses
---
> system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 138430 # number of UpgradeReq misses
> system.cpu0.l2cache.UpgradeReq_misses::total 138430 # number of UpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158345 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeReq_misses::total 158345 # number of SCUpgradeReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
> system.cpu0.l2cache.ReadExReq_misses::cpu0.data 344034 # number of ReadExReq misses
> system.cpu0.l2cache.ReadExReq_misses::total 344034 # number of ReadExReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 686063 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadCleanReq_misses::total 686063 # number of ReadCleanReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1100006 # number of ReadSharedReq misses
> system.cpu0.l2cache.ReadSharedReq_misses::total 1100006 # number of ReadSharedReq misses
> system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 624163 # number of InvalidateReq misses
> system.cpu0.l2cache.InvalidateReq_misses::total 624163 # number of InvalidateReq misses
> system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13844 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10570 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.inst 686063 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::cpu0.data 1444040 # number of demand (read+write) misses
> system.cpu0.l2cache.demand_misses::total 2154517 # number of demand (read+write) misses
> system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 13844 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10570 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.inst 686063 # number of overall misses
> system.cpu0.l2cache.overall_misses::cpu0.data 1444040 # number of overall misses
> system.cpu0.l2cache.overall_misses::total 2154517 # number of overall misses
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 747131500 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 657491000 # number of ReadReq miss cycles
> system.cpu0.l2cache.ReadReq_miss_latency::total 1404622500 # number of ReadReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 4320468000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.UpgradeReq_miss_latency::total 4320468000 # number of UpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3850233000 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3850233000 # number of SCUpgradeReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4846000 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4846000 # number of SCUpgradeFailReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 23100204997 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadExReq_miss_latency::total 23100204997 # number of ReadExReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 27039967498 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadCleanReq_miss_latency::total 27039967498 # number of ReadCleanReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 50121323488 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.ReadSharedReq_miss_latency::total 50121323488 # number of ReadSharedReq miss cycles
> system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 94690450497 # number of InvalidateReq miss cycles
> system.cpu0.l2cache.InvalidateReq_miss_latency::total 94690450497 # number of InvalidateReq miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 747131500 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 657491000 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.inst 27039967498 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::cpu0.data 73221528485 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.demand_miss_latency::total 101666118483 # number of demand (read+write) miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 747131500 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 657491000 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.inst 27039967498 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::cpu0.data 73221528485 # number of overall miss cycles
> system.cpu0.l2cache.overall_miss_latency::total 101666118483 # number of overall miss cycles
> system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 621436 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 202118 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.ReadReq_accesses::total 823554 # number of ReadReq accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::writebacks 4324519 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.Writeback_accesses::total 4324519 # number of Writeback accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 252633 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.UpgradeReq_accesses::total 252633 # number of UpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 195303 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeReq_accesses::total 195303 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 6 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1314223 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadExReq_accesses::total 1314223 # number of ReadExReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6359245 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadCleanReq_accesses::total 6359245 # number of ReadCleanReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4373932 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.ReadSharedReq_accesses::total 4373932 # number of ReadSharedReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 835494 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.InvalidateReq_accesses::total 835494 # number of InvalidateReq accesses(hits+misses)
> system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 621436 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 202118 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.inst 6359245 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::cpu0.data 5688155 # number of demand (read+write) accesses
> system.cpu0.l2cache.demand_accesses::total 12870954 # number of demand (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 621436 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 202118 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.inst 6359245 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::cpu0.data 5688155 # number of overall (read+write) accesses
> system.cpu0.l2cache.overall_accesses::total 12870954 # number of overall (read+write) accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.022277 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052296 # miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_miss_rate::total 0.029645 # miss rate for ReadReq accesses
1398,1401c1390,1393
< system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.549700 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.549700 # miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.817623 # miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.817623 # miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.547949 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.547949 # miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.810766 # miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.810766 # miss rate for SCUpgradeReq accesses
1404,1449c1396,1441
< system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.227356 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_miss_rate::total 0.227356 # miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.103138 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.103138 # miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.255292 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.255292 # miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.736107 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.736107 # miss rate for InvalidateReq accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022534 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.048165 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.103138 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.248834 # miss rate for demand accesses
< system.cpu0.l2cache.demand_miss_rate::total 0.161902 # miss rate for demand accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022534 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.048165 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.103138 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.248834 # miss rate for overall accesses
< system.cpu0.l2cache.overall_miss_rate::total 0.161902 # miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 39931.782765 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 43393.097998 # average ReadReq miss latency
< system.cpu0.l2cache.ReadReq_avg_miss_latency::total 41403.198352 # average ReadReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21773.010424 # average UpgradeReq miss latency
< system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21773.010424 # average UpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20735.117701 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20735.117701 # average SCUpgradeReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 498599.800000 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 498599.800000 # average SCUpgradeFailReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54369.509438 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54369.509438 # average ReadExReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 31030.321047 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 31030.321047 # average ReadCleanReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 36508.147651 # average ReadSharedReq miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 36508.147651 # average ReadSharedReq miss latency
< system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 115655.015566 # average InvalidateReq miss latency
< system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 115655.015566 # average InvalidateReq miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 39931.782765 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 43393.097998 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31030.321047 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 40280.797645 # average overall miss latency
< system.cpu0.l2cache.demand_avg_miss_latency::total 37314.287359 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 39931.782765 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 43393.097998 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31030.321047 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 40280.797645 # average overall miss latency
< system.cpu0.l2cache.overall_avg_miss_latency::total 37314.287359 # average overall miss latency
< system.cpu0.l2cache.blocked_cycles::no_mshrs 1981 # number of cycles access was blocked
---
> system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.261777 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_miss_rate::total 0.261777 # miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.107884 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.107884 # miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.251491 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.251491 # miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.747059 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.747059 # miss rate for InvalidateReq accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022277 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052296 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.107884 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.253868 # miss rate for demand accesses
> system.cpu0.l2cache.demand_miss_rate::total 0.167394 # miss rate for demand accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022277 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052296 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.107884 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.253868 # miss rate for overall accesses
> system.cpu0.l2cache.overall_miss_rate::total 0.167394 # miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 53967.892228 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 62203.500473 # average ReadReq miss latency
> system.cpu0.l2cache.ReadReq_avg_miss_latency::total 57533.484886 # average ReadReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 31210.489056 # average UpgradeReq miss latency
> system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 31210.489056 # average UpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 24315.469386 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 24315.469386 # average SCUpgradeReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 807666.666667 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 807666.666667 # average SCUpgradeFailReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 67145.122276 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 67145.122276 # average ReadExReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39413.242658 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39413.242658 # average ReadCleanReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 45564.591000 # average ReadSharedReq miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 45564.591000 # average ReadSharedReq miss latency
> system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 151707.887999 # average InvalidateReq miss latency
> system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 151707.887999 # average InvalidateReq miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 53967.892228 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 62203.500473 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39413.242658 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 50706.025100 # average overall miss latency
> system.cpu0.l2cache.demand_avg_miss_latency::total 47187.429240 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 53967.892228 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 62203.500473 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39413.242658 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 50706.025100 # average overall miss latency
> system.cpu0.l2cache.overall_avg_miss_latency::total 47187.429240 # average overall miss latency
> system.cpu0.l2cache.blocked_cycles::no_mshrs 4612 # number of cycles access was blocked
1451c1443
< system.cpu0.l2cache.blocked::no_mshrs 13 # number of cycles access was blocked
---
> system.cpu0.l2cache.blocked::no_mshrs 22 # number of cycles access was blocked
1453c1445
< system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 152.384615 # average number of cycles each access was blocked
---
> system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 209.636364 # average number of cycles each access was blocked
1457,1458c1449,1450
< system.cpu0.l2cache.writebacks::writebacks 1508833 # number of writebacks
< system.cpu0.l2cache.writebacks::total 1508833 # number of writebacks
---
> system.cpu0.l2cache.writebacks::writebacks 1594853 # number of writebacks
> system.cpu0.l2cache.writebacks::total 1594853 # number of writebacks
1460,1469c1452,1461
< system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 199 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_hits::total 206 # number of ReadReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 18287 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadExReq_mshr_hits::total 18287 # number of ReadExReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 9 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 5427 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 5427 # number of ReadSharedReq MSHR hits
< system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 6 # number of InvalidateReq MSHR hits
< system.cpu0.l2cache.InvalidateReq_mshr_hits::total 6 # number of InvalidateReq MSHR hits
---
> system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 173 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_hits::total 180 # number of ReadReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 69770 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadExReq_mshr_hits::total 69770 # number of ReadExReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 3 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 7585 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 7585 # number of ReadSharedReq MSHR hits
> system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 3 # number of InvalidateReq MSHR hits
> system.cpu0.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits
1471,1474c1463,1466
< system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 199 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::cpu0.data 23714 # number of demand (read+write) MSHR hits
< system.cpu0.l2cache.demand_mshr_hits::total 23929 # number of demand (read+write) MSHR hits
---
> system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 173 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::cpu0.data 77355 # number of demand (read+write) MSHR hits
> system.cpu0.l2cache.demand_mshr_hits::total 77538 # number of demand (read+write) MSHR hits
1476,1482c1468,1474
< system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 199 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::cpu0.data 23714 # number of overall MSHR hits
< system.cpu0.l2cache.overall_mshr_hits::total 23929 # number of overall MSHR hits
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12827 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9291 # number of ReadReq MSHR misses
< system.cpu0.l2cache.ReadReq_mshr_misses::total 22118 # number of ReadReq MSHR misses
---
> system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 173 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::cpu0.data 77355 # number of overall MSHR hits
> system.cpu0.l2cache.overall_mshr_hits::total 77538 # number of overall MSHR hits
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 13837 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10397 # number of ReadReq MSHR misses
> system.cpu0.l2cache.ReadReq_mshr_misses::total 24234 # number of ReadReq MSHR misses
1485,1513c1477,1505
< system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 112445 # number of CleanEvict MSHR misses
< system.cpu0.l2cache.CleanEvict_mshr_misses::total 112445 # number of CleanEvict MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 792314 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.HardPFReq_mshr_misses::total 792314 # number of HardPFReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 137568 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.UpgradeReq_mshr_misses::total 137568 # number of UpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 163550 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 163550 # number of SCUpgradeReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 10 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 10 # number of SCUpgradeFailReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 270914 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadExReq_mshr_misses::total 270914 # number of ReadExReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 660885 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 660885 # number of ReadCleanReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1074575 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1074575 # number of ReadSharedReq MSHR misses
< system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 587435 # number of InvalidateReq MSHR misses
< system.cpu0.l2cache.InvalidateReq_mshr_misses::total 587435 # number of InvalidateReq MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12827 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9291 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 660885 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1345489 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.demand_mshr_misses::total 2028492 # number of demand (read+write) MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12827 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9291 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 660885 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1345489 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 792314 # number of overall MSHR misses
< system.cpu0.l2cache.overall_mshr_misses::total 2820806 # number of overall MSHR misses
---
> system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 119189 # number of CleanEvict MSHR misses
> system.cpu0.l2cache.CleanEvict_mshr_misses::total 119189 # number of CleanEvict MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 853540 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.HardPFReq_mshr_misses::total 853540 # number of HardPFReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 138430 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.UpgradeReq_mshr_misses::total 138430 # number of UpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 158345 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 158345 # number of SCUpgradeReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 274264 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadExReq_mshr_misses::total 274264 # number of ReadExReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 686060 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 686060 # number of ReadCleanReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1092421 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1092421 # number of ReadSharedReq MSHR misses
> system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 624160 # number of InvalidateReq MSHR misses
> system.cpu0.l2cache.InvalidateReq_mshr_misses::total 624160 # number of InvalidateReq MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 13837 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10397 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 686060 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1366685 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.demand_mshr_misses::total 2076979 # number of demand (read+write) MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 13837 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10397 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 686060 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1366685 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 853540 # number of overall MSHR misses
> system.cpu0.l2cache.overall_mshr_misses::total 2930519 # number of overall MSHR misses
1515,1518c1507,1510
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32342 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 53636 # number of ReadReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31823 # number of WriteReq MSHR uncacheable
< system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31823 # number of WriteReq MSHR uncacheable
---
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31951 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 53245 # number of ReadReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31485 # number of WriteReq MSHR uncacheable
> system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31485 # number of WriteReq MSHR uncacheable
1520,1562c1512,1554
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 64165 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 85459 # number of overall MSHR uncacheable misses
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 435391500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 348114500 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 783506000 # number of ReadReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 46187185788 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 46187185788 # number of HardPFReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2827746492 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2827746492 # number of UpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2511676494 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2511676494 # number of SCUpgradeReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4277998 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4277998 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11675388499 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11675388499 # number of ReadExReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 16542258498 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 16542258498 # number of ReadCleanReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 32603545979 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 32603545979 # number of ReadSharedReq MSHR miss cycles
< system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 64414833499 # number of InvalidateReq MSHR miss cycles
< system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 64414833499 # number of InvalidateReq MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 435391500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 348114500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 16542258498 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 44278934478 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.demand_mshr_miss_latency::total 61604698976 # number of demand (read+write) MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 435391500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 348114500 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 16542258498 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 44278934478 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 46187185788 # number of overall MSHR miss cycles
< system.cpu0.l2cache.overall_mshr_miss_latency::total 107791884764 # number of overall MSHR miss cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1704040500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5558674000 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7262714500 # number of ReadReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5274604967 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5274604967 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1704040500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10833278967 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12537319467 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022522 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.047155 # mshr miss rate for ReadReq accesses
< system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028853 # mshr miss rate for ReadReq accesses
---
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 63436 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 84730 # number of overall MSHR uncacheable misses
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 663983000 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 585367500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1249350500 # number of ReadReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 68949295019 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 68949295019 # number of HardPFReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4907856994 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4907856994 # number of UpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3084199996 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3084199996 # number of SCUpgradeReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4498000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4498000 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 17239432497 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 17239432497 # number of ReadExReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 22923448498 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 22923448498 # number of ReadCleanReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 43011997988 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 43011997988 # number of ReadSharedReq MSHR miss cycles
> system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 90945024497 # number of InvalidateReq MSHR miss cycles
> system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 90945024497 # number of InvalidateReq MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 663983000 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 585367500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 22923448498 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 60251430485 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.demand_mshr_miss_latency::total 84424229483 # number of demand (read+write) MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 663983000 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 585367500 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 22923448498 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 60251430485 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 68949295019 # number of overall MSHR miss cycles
> system.cpu0.l2cache.overall_mshr_miss_latency::total 153373524502 # number of overall MSHR miss cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780019500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5515655500 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8295675000 # number of ReadReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5356039467 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5356039467 # number of WriteReq MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 2780019500 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10871694967 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 13651714467 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022266 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.051440 # mshr miss rate for ReadReq accesses
> system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.029426 # mshr miss rate for ReadReq accesses
1569,1572c1561,1564
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.549700 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.549700 # mshr miss rate for UpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.817623 # mshr miss rate for SCUpgradeReq accesses
< system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.817623 # mshr miss rate for SCUpgradeReq accesses
---
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.547949 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.547949 # mshr miss rate for UpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.810766 # mshr miss rate for SCUpgradeReq accesses
> system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.810766 # mshr miss rate for SCUpgradeReq accesses
1575,1591c1567,1583
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.212980 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.212980 # mshr miss rate for ReadExReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.103137 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.103137 # mshr miss rate for ReadCleanReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.254009 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254009 # mshr miss rate for ReadSharedReq accesses
< system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.736099 # mshr miss rate for InvalidateReq accesses
< system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.736099 # mshr miss rate for InvalidateReq accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022522 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.047155 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.103137 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.244524 # mshr miss rate for demand accesses
< system.cpu0.l2cache.demand_mshr_miss_rate::total 0.160015 # mshr miss rate for demand accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022522 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.047155 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.103137 # mshr miss rate for overall accesses
< system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.244524 # mshr miss rate for overall accesses
---
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.208689 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.208689 # mshr miss rate for ReadExReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.107884 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.107884 # mshr miss rate for ReadCleanReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.249757 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249757 # mshr miss rate for ReadSharedReq accesses
> system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.747055 # mshr miss rate for InvalidateReq accesses
> system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.747055 # mshr miss rate for InvalidateReq accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022266 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.051440 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.107884 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240269 # mshr miss rate for demand accesses
> system.cpu0.l2cache.demand_mshr_miss_rate::total 0.161369 # mshr miss rate for demand accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022266 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.051440 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.107884 # mshr miss rate for overall accesses
> system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240269 # mshr miss rate for overall accesses
1593,1631c1585,1623
< system.cpu0.l2cache.overall_mshr_miss_rate::total 0.222515 # mshr miss rate for overall accesses
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 33943.361659 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 37467.925950 # average ReadReq mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35423.908129 # average ReadReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58294.042246 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58294.042246 # average HardPFReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20555.263521 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20555.263521 # average UpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15357.239340 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15357.239340 # average SCUpgradeReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 427799.800000 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 427799.800000 # average SCUpgradeFailReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43096.290701 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43096.290701 # average ReadExReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 25030.464450 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 25030.464450 # average ReadCleanReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30340.875210 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30340.875210 # average ReadSharedReq mshr miss latency
< system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 109654.401762 # average InvalidateReq mshr miss latency
< system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 109654.401762 # average InvalidateReq mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 33943.361659 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 37467.925950 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25030.464450 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32909.176127 # average overall mshr miss latency
< system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30369.702703 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 33943.361659 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 37467.925950 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25030.464450 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32909.176127 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58294.042246 # average overall mshr miss latency
< system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38213.150697 # average overall mshr miss latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 171871.683879 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 135407.459542 # average ReadReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165748.199950 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165748.199950 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 168834.706881 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 146705.665489 # average overall mshr uncacheable latency
---
> system.cpu0.l2cache.overall_mshr_miss_rate::total 0.227685 # mshr miss rate for overall accesses
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 47986.051890 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 56301.577378 # average ReadReq mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 51553.623009 # average ReadReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80780.391099 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 80780.391099 # average HardPFReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35453.709413 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35453.709413 # average UpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19477.722669 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19477.722669 # average SCUpgradeReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 749666.666667 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 749666.666667 # average SCUpgradeFailReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62857.073830 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62857.073830 # average ReadExReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33413.183246 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33413.183246 # average ReadCleanReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39373.096991 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39373.096991 # average ReadSharedReq mshr miss latency
> system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145707.870573 # average InvalidateReq mshr miss latency
> system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145707.870573 # average InvalidateReq mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 47986.051890 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 56301.577378 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33413.183246 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 44085.821155 # average overall mshr miss latency
> system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40647.608610 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 47986.051890 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 56301.577378 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33413.183246 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 44085.821155 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80780.391099 # average overall mshr miss latency
> system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52336.642247 # average overall mshr miss latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130554.123227 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172628.571876 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 155801.953235 # average ReadReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170114.005622 # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 170114.005622 # average WriteReq mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130554.123227 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 171380.524734 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 161120.199068 # average overall mshr uncacheable latency
1633,1666c1625,1663
< system.cpu0.toL2Bus.trans_dist::ReadReq 972246 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadResp 11719640 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteReq 38676 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::WriteResp 31823 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::Writeback 8100286 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::CleanEvict 11177309 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFReq 1018919 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeReq 495790 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 366670 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeResp 532232 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 139 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 247 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExReq 1670081 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadExResp 1283370 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6407871 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::ReadSharedReq 6502663 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateReq 904766 # Transaction distribution
< system.cpu0.toL2Bus.trans_dist::InvalidateResp 798038 # Transaction distribution
< system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19264194 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20025393 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 428101 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1250579 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_count::total 40968267 # Packet count per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 410442912 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 629983858 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1576264 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4556320 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.pkt_size::total 1046559354 # Cumulative packet size per connected master and slave (bytes)
< system.cpu0.toL2Bus.snoops 11261603 # Total snoops (count)
< system.cpu0.toL2Bus.snoop_fanout::samples 37657626 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::mean 1.313855 # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::stdev 0.464058 # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_filter.tot_requests 26498119 # Total number of requests made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13615382 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2337 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.snoop_filter.tot_snoops 550917 # Total number of snoops made to the snoop filter.
> system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 550892 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 25 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu0.toL2Bus.trans_dist::ReadReq 1014324 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadResp 11851775 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteReq 31486 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::WriteResp 31485 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::Writeback 5956604 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::CleanEvict 10410037 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFReq 1088232 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeReq 474368 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 351600 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeResp 519661 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExReq 1396851 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadExResp 1324661 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6359280 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5366614 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateReq 842272 # Transaction distribution
> system.cpu0.toL2Bus.trans_dist::InvalidateResp 835494 # Transaction distribution
> system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19118379 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20677259 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 436050 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1348581 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_count::total 41580269 # Packet count per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 407332384 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 648350241 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1616944 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4971488 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.pkt_size::total 1062271057 # Cumulative packet size per connected master and slave (bytes)
> system.cpu0.toL2Bus.snoops 6461178 # Total snoops (count)
> system.cpu0.toL2Bus.snoop_fanout::samples 33294085 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::mean 0.028312 # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::stdev 0.165866 # Request fanout histogram
1668,1670c1665,1667
< system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::1 25838573 68.61% 68.61% # Request fanout histogram
< system.cpu0.toL2Bus.snoop_fanout::2 11819053 31.39% 100.00% # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::0 32351497 97.17% 97.17% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::1 942563 2.83% 100.00% # Request fanout histogram
> system.cpu0.toL2Bus.snoop_fanout::2 25 0.00% 100.00% # Request fanout histogram
1672c1669
< system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1674,1675c1671,1672
< system.cpu0.toL2Bus.snoop_fanout::total 37657626 # Request fanout histogram
< system.cpu0.toL2Bus.reqLayer0.occupancy 17602075916 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoop_fanout::total 33294085 # Request fanout histogram
> system.cpu0.toL2Bus.reqLayer0.occupancy 17918792438 # Layer occupancy (ticks)
1677c1674
< system.cpu0.toL2Bus.snoopLayer0.occupancy 231593980 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.snoopLayer0.occupancy 208202715 # Layer occupancy (ticks)
1679c1676
< system.cpu0.toL2Bus.respLayer0.occupancy 9637654372 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer0.occupancy 9565441520 # Layer occupancy (ticks)
1681c1678
< system.cpu0.toL2Bus.respLayer1.occupancy 8931019988 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer1.occupancy 9227310290 # Layer occupancy (ticks)
1683c1680
< system.cpu0.toL2Bus.respLayer2.occupancy 231432265 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer2.occupancy 234328206 # Layer occupancy (ticks)
1685c1682
< system.cpu0.toL2Bus.respLayer3.occupancy 681669728 # Layer occupancy (ticks)
---
> system.cpu0.toL2Bus.respLayer3.occupancy 727701378 # Layer occupancy (ticks)
1687,1691c1684,1688
< system.cpu1.branchPred.lookups 121094303 # Number of BP lookups
< system.cpu1.branchPred.condPredicted 80706133 # Number of conditional branches predicted
< system.cpu1.branchPred.condIncorrect 6142160 # Number of conditional branches incorrect
< system.cpu1.branchPred.BTBLookups 84960891 # Number of BTB lookups
< system.cpu1.branchPred.BTBHits 56341743 # Number of BTB hits
---
> system.cpu1.branchPred.lookups 122053066 # Number of BP lookups
> system.cpu1.branchPred.condPredicted 81331643 # Number of conditional branches predicted
> system.cpu1.branchPred.condIncorrect 6140345 # Number of conditional branches incorrect
> system.cpu1.branchPred.BTBLookups 85523370 # Number of BTB lookups
> system.cpu1.branchPred.BTBHits 55672017 # Number of BTB hits
1693,1695c1690,1692
< system.cpu1.branchPred.BTBHitPct 66.314915 # BTB Hit Percentage
< system.cpu1.branchPred.usedRAS 16429988 # Number of times the RAS was used to get a target.
< system.cpu1.branchPred.RASInCorrect 173246 # Number of incorrect RAS predictions.
---
> system.cpu1.branchPred.BTBHitPct 65.095677 # BTB Hit Percentage
> system.cpu1.branchPred.usedRAS 16431061 # Number of times the RAS was used to get a target.
> system.cpu1.branchPred.RASInCorrect 166790 # Number of incorrect RAS predictions.
1725,1781c1722,1774
< system.cpu1.dtb.walker.walks 582230 # Table walker walks requested
< system.cpu1.dtb.walker.walksLong 582230 # Table walker walks initiated with long descriptors
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 14388 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94420 # Level at which table walker walks with long descriptors terminate
< system.cpu1.dtb.walker.walksSquashedBefore 278308 # Table walks squashed before starting
< system.cpu1.dtb.walker.walkWaitTime::samples 303922 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::mean 1994.445943 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::stdev 12173.491739 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::0-32767 299685 98.61% 98.61% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::32768-65535 2211 0.73% 99.33% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::65536-98303 696 0.23% 99.56% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::98304-131071 740 0.24% 99.81% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::131072-163839 294 0.10% 99.90% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::163840-196607 141 0.05% 99.95% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::196608-229375 47 0.02% 99.96% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::229376-262143 22 0.01% 99.97% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::262144-294911 14 0.00% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::294912-327679 44 0.01% 99.99% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::327680-360447 15 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::360448-393215 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::491520-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkWaitTime::total 303922 # Table walker wait (enqueue to first request) latency
< system.cpu1.dtb.walker.walkCompletionTime::samples 314895 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::mean 18136.229537 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::gmean 15585.359240 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::stdev 14753.917468 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::0-65535 312363 99.20% 99.20% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1838 0.58% 99.78% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::131072-196607 299 0.09% 99.87% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::196608-262143 215 0.07% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::262144-327679 97 0.03% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::327680-393215 46 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::393216-458751 18 0.01% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::589824-655359 8 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walkCompletionTime::total 314895 # Table walker service (enqueue to completion) latency
< system.cpu1.dtb.walker.walksPending::samples 417361955272 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::mean 0.556480 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::stdev 0.556703 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::0-1 416192825272 99.72% 99.72% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::2-3 674141500 0.16% 99.88% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::4-5 223425500 0.05% 99.93% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::6-7 105228000 0.03% 99.96% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::8-9 86739500 0.02% 99.98% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::10-11 43806500 0.01% 99.99% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::12-13 16133000 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::14-15 19234500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::16-17 421500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.dtb.walker.walksPending::total 417361955272 # Table walker pending requests distribution
< system.cpu1.dtb.walker.walkPageSizes::4K 94420 86.78% 86.78% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::2M 14388 13.22% 100.00% # Table walker page sizes translated
< system.cpu1.dtb.walker.walkPageSizes::total 108808 # Table walker page sizes translated
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 582230 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walks 513343 # Table walker walks requested
> system.cpu1.dtb.walker.walksLong 513343 # Table walker walks initiated with long descriptors
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10145 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80504 # Level at which table walker walks with long descriptors terminate
> system.cpu1.dtb.walker.walksSquashedBefore 231589 # Table walks squashed before starting
> system.cpu1.dtb.walker.walkWaitTime::samples 281754 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::mean 2191.677847 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::stdev 13834.020871 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::0-65535 279857 99.33% 99.33% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::65536-131071 1045 0.37% 99.70% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::131072-196607 593 0.21% 99.91% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::196608-262143 154 0.05% 99.96% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::262144-327679 32 0.01% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::327680-393215 54 0.02% 99.99% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::393216-458751 12 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkWaitTime::total 281754 # Table walker wait (enqueue to first request) latency
> system.cpu1.dtb.walker.walkCompletionTime::samples 256242 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::mean 18411.043076 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::gmean 15820.375131 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::stdev 14815.596994 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::0-65535 254819 99.44% 99.44% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::65536-131071 556 0.22% 99.66% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::131072-196607 633 0.25% 99.91% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::196608-262143 56 0.02% 99.93% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::262144-327679 78 0.03% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::327680-393215 63 0.02% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::393216-458751 21 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::458752-524287 9 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::983040-1.04858e+06 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walkCompletionTime::total 256242 # Table walker service (enqueue to completion) latency
> system.cpu1.dtb.walker.walksPending::samples 430767474576 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::mean 0.581742 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::stdev 0.547950 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::0-1 429773436576 99.77% 99.77% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::2-3 519356000 0.12% 99.89% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::4-5 211618500 0.05% 99.94% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::6-7 107822000 0.03% 99.96% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::8-9 75775500 0.02% 99.98% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::10-11 45293000 0.01% 99.99% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::12-13 13801500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::14-15 19976000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::16-17 394000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.dtb.walker.walksPending::total 430767474576 # Table walker pending requests distribution
> system.cpu1.dtb.walker.walkPageSizes::4K 80504 88.81% 88.81% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::2M 10145 11.19% 100.00% # Table walker page sizes translated
> system.cpu1.dtb.walker.walkPageSizes::total 90649 # Table walker page sizes translated
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 513343 # Table walker requests started/completed, data/inst
1783,1784c1776,1777
< system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 582230 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 108808 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 513343 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90649 # Table walker requests started/completed, data/inst
1786,1787c1779,1780
< system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 108808 # Table walker requests started/completed, data/inst
< system.cpu1.dtb.walker.walkRequestOrigin::total 691038 # Table walker requests started/completed, data/inst
---
> system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90649 # Table walker requests started/completed, data/inst
> system.cpu1.dtb.walker.walkRequestOrigin::total 603992 # Table walker requests started/completed, data/inst
1790,1793c1783,1786
< system.cpu1.dtb.read_hits 89807249 # DTB read hits
< system.cpu1.dtb.read_misses 419450 # DTB read misses
< system.cpu1.dtb.write_hits 72180592 # DTB write hits
< system.cpu1.dtb.write_misses 162780 # DTB write misses
---
> system.cpu1.dtb.read_hits 90392235 # DTB read hits
> system.cpu1.dtb.read_misses 355030 # DTB read misses
> system.cpu1.dtb.write_hits 74292452 # DTB write hits
> system.cpu1.dtb.write_misses 158313 # DTB write misses
1796,1800c1789,1793
< system.cpu1.dtb.flush_tlb_mva_asid 44378 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.dtb.flush_tlb_asid 1065 # Number of times TLB was flushed by ASID
< system.cpu1.dtb.flush_entries 41875 # Number of entries that have been flushed from TLB
< system.cpu1.dtb.align_faults 370 # Number of TLB faults due to alignment restrictions
< system.cpu1.dtb.prefetch_faults 6410 # Number of TLB faults due to prefetch
---
> system.cpu1.dtb.flush_tlb_mva_asid 44087 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
> system.cpu1.dtb.flush_entries 34737 # Number of entries that have been flushed from TLB
> system.cpu1.dtb.align_faults 572 # Number of TLB faults due to alignment restrictions
> system.cpu1.dtb.prefetch_faults 5833 # Number of TLB faults due to prefetch
1802,1804c1795,1797
< system.cpu1.dtb.perms_faults 41502 # Number of TLB faults due to permissions restrictions
< system.cpu1.dtb.read_accesses 90226699 # DTB read accesses
< system.cpu1.dtb.write_accesses 72343372 # DTB write accesses
---
> system.cpu1.dtb.perms_faults 38175 # Number of TLB faults due to permissions restrictions
> system.cpu1.dtb.read_accesses 90747265 # DTB read accesses
> system.cpu1.dtb.write_accesses 74450765 # DTB write accesses
1806,1808c1799,1801
< system.cpu1.dtb.hits 161987841 # DTB hits
< system.cpu1.dtb.misses 582230 # DTB misses
< system.cpu1.dtb.accesses 162570071 # DTB accesses
---
> system.cpu1.dtb.hits 164684687 # DTB hits
> system.cpu1.dtb.misses 513343 # DTB misses
> system.cpu1.dtb.accesses 165198030 # DTB accesses
1838,1849c1831,1842
< system.cpu1.itb.walker.walks 81350 # Table walker walks requested
< system.cpu1.itb.walker.walksLong 81350 # Table walker walks initiated with long descriptors
< system.cpu1.itb.walker.walksLongTerminationLevel::Level2 844 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walksLongTerminationLevel::Level3 59039 # Level at which table walker walks with long descriptors terminate
< system.cpu1.itb.walker.walksSquashedBefore 9413 # Table walks squashed before starting
< system.cpu1.itb.walker.walkWaitTime::samples 71937 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::mean 1124.310160 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::stdev 8422.739912 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::0-65535 71675 99.64% 99.64% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::65536-131071 232 0.32% 99.96% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::131072-196607 13 0.02% 99.98% # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkWaitTime::196608-262143 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency
---
> system.cpu1.itb.walker.walks 79836 # Table walker walks requested
> system.cpu1.itb.walker.walksLong 79836 # Table walker walks initiated with long descriptors
> system.cpu1.itb.walker.walksLongTerminationLevel::Level2 812 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57876 # Level at which table walker walks with long descriptors terminate
> system.cpu1.itb.walker.walksSquashedBefore 9466 # Table walks squashed before starting
> system.cpu1.itb.walker.walkWaitTime::samples 70370 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::mean 1202.877647 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::stdev 9654.881733 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::0-65535 70178 99.73% 99.73% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::65536-131071 41 0.06% 99.79% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::131072-196607 131 0.19% 99.97% # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkWaitTime::196608-262143 11 0.02% 99.99% # Table walker wait (enqueue to first request) latency
1853,1865c1846,1858
< system.cpu1.itb.walker.walkWaitTime::total 71937 # Table walker wait (enqueue to first request) latency
< system.cpu1.itb.walker.walkCompletionTime::samples 69296 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::mean 22634.596514 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::gmean 19851.891028 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::stdev 18070.710028 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::0-65535 67837 97.89% 97.89% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::65536-131071 1226 1.77% 99.66% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::131072-196607 116 0.17% 99.83% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::196608-262143 77 0.11% 99.94% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::262144-327679 19 0.03% 99.97% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.99% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
---
> system.cpu1.itb.walker.walkWaitTime::total 70370 # Table walker wait (enqueue to first request) latency
> system.cpu1.itb.walker.walkCompletionTime::samples 68154 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::mean 22918.860228 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::gmean 20570.604774 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::stdev 17513.278330 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::0-65535 67528 99.08% 99.08% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::65536-131071 75 0.11% 99.19% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::131072-196607 455 0.67% 99.86% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::196608-262143 42 0.06% 99.92% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::262144-327679 28 0.04% 99.96% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.98% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1867,1879c1860,1874
< system.cpu1.itb.walker.walkCompletionTime::total 69296 # Table walker service (enqueue to completion) latency
< system.cpu1.itb.walker.walksPending::samples 391589144496 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::mean 0.846934 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::stdev 0.360225 # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::0 59961618480 15.31% 15.31% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::1 331606536516 84.68% 99.99% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::2 19274500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::3 1690500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::4 24500 0.00% 100.00% # Table walker pending requests distribution
< system.cpu1.itb.walker.walksPending::total 391589144496 # Table walker pending requests distribution
< system.cpu1.itb.walker.walkPageSizes::4K 59039 98.59% 98.59% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::2M 844 1.41% 100.00% # Table walker page sizes translated
< system.cpu1.itb.walker.walkPageSizes::total 59883 # Table walker page sizes translated
---
> system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walkCompletionTime::total 68154 # Table walker service (enqueue to completion) latency
> system.cpu1.itb.walker.walksPending::samples 396407660708 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::mean 0.833666 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::stdev 0.372525 # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::0 65955607768 16.64% 16.64% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::1 330434317940 83.36% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::2 16293000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::3 1234500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::4 163500 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::5 44000 0.00% 100.00% # Table walker pending requests distribution
> system.cpu1.itb.walker.walksPending::total 396407660708 # Table walker pending requests distribution
> system.cpu1.itb.walker.walkPageSizes::4K 57876 98.62% 98.62% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::2M 812 1.38% 100.00% # Table walker page sizes translated
> system.cpu1.itb.walker.walkPageSizes::total 58688 # Table walker page sizes translated
1881,1882c1876,1877
< system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 81350 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Requested::total 81350 # Table walker requests started/completed, data/inst
---
> system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 79836 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Requested::total 79836 # Table walker requests started/completed, data/inst
1884,1888c1879,1883
< system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 59883 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin_Completed::total 59883 # Table walker requests started/completed, data/inst
< system.cpu1.itb.walker.walkRequestOrigin::total 141233 # Table walker requests started/completed, data/inst
< system.cpu1.itb.inst_hits 191639831 # ITB inst hits
< system.cpu1.itb.inst_misses 81350 # ITB inst misses
---
> system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58688 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58688 # Table walker requests started/completed, data/inst
> system.cpu1.itb.walker.walkRequestOrigin::total 138524 # Table walker requests started/completed, data/inst
> system.cpu1.itb.inst_hits 192024896 # ITB inst hits
> system.cpu1.itb.inst_misses 79836 # ITB inst misses
1895,1897c1890,1892
< system.cpu1.itb.flush_tlb_mva_asid 44378 # Number of times TLB was flushed by MVA & ASID
< system.cpu1.itb.flush_tlb_asid 1065 # Number of times TLB was flushed by ASID
< system.cpu1.itb.flush_entries 29949 # Number of entries that have been flushed from TLB
---
> system.cpu1.itb.flush_tlb_mva_asid 44087 # Number of times TLB was flushed by MVA & ASID
> system.cpu1.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
> system.cpu1.itb.flush_entries 24498 # Number of entries that have been flushed from TLB
1901c1896
< system.cpu1.itb.perms_faults 209776 # Number of TLB faults due to permissions restrictions
---
> system.cpu1.itb.perms_faults 203556 # Number of TLB faults due to permissions restrictions
1904,1908c1899,1903
< system.cpu1.itb.inst_accesses 191721181 # ITB inst accesses
< system.cpu1.itb.hits 191639831 # DTB hits
< system.cpu1.itb.misses 81350 # DTB misses
< system.cpu1.itb.accesses 191721181 # DTB accesses
< system.cpu1.numCycles 657106376 # number of cpu cycles simulated
---
> system.cpu1.itb.inst_accesses 192104732 # ITB inst accesses
> system.cpu1.itb.hits 192024896 # DTB hits
> system.cpu1.itb.misses 79836 # DTB misses
> system.cpu1.itb.accesses 192104732 # DTB accesses
> system.cpu1.numCycles 663967264 # number of cpu cycles simulated
1911,1927c1906,1922
< system.cpu1.fetch.icacheStallCycles 80139865 # Number of cycles fetch is stalled on an Icache miss
< system.cpu1.fetch.Insts 537547218 # Number of instructions fetch has processed
< system.cpu1.fetch.Branches 121094303 # Number of branches that fetch encountered
< system.cpu1.fetch.predictedBranches 72771731 # Number of branches that fetch has predicted taken
< system.cpu1.fetch.Cycles 544595085 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu1.fetch.SquashCycles 13230640 # Number of cycles fetch has spent squashing
< system.cpu1.fetch.TlbCycles 1750818 # Number of cycles fetch has spent waiting for tlb
< system.cpu1.fetch.MiscStallCycles 245014 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu1.fetch.PendingTrapStallCycles 5964311 # Number of stall cycles due to pending traps
< system.cpu1.fetch.PendingQuiesceStallCycles 783127 # Number of stall cycles due to pending quiesce instructions
< system.cpu1.fetch.IcacheWaitRetryStallCycles 735374 # Number of stall cycles due to full MSHR
< system.cpu1.fetch.CacheLines 191409476 # Number of cache lines fetched
< system.cpu1.fetch.IcacheSquashes 1578665 # Number of outstanding Icache misses that were squashed
< system.cpu1.fetch.ItlbSquashes 27162 # Number of outstanding ITLB misses that were squashed
< system.cpu1.fetch.rateDist::samples 640828914 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::mean 0.984123 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::stdev 1.220773 # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.icacheStallCycles 80600357 # Number of cycles fetch is stalled on an Icache miss
> system.cpu1.fetch.Insts 540678400 # Number of instructions fetch has processed
> system.cpu1.fetch.Branches 122053066 # Number of branches that fetch encountered
> system.cpu1.fetch.predictedBranches 72103078 # Number of branches that fetch has predicted taken
> system.cpu1.fetch.Cycles 547218750 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu1.fetch.SquashCycles 13194102 # Number of cycles fetch has spent squashing
> system.cpu1.fetch.TlbCycles 1722175 # Number of cycles fetch has spent waiting for tlb
> system.cpu1.fetch.MiscStallCycles 292741 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu1.fetch.PendingTrapStallCycles 5852987 # Number of stall cycles due to pending traps
> system.cpu1.fetch.PendingQuiesceStallCycles 747163 # Number of stall cycles due to pending quiesce instructions
> system.cpu1.fetch.IcacheWaitRetryStallCycles 786410 # Number of stall cycles due to full MSHR
> system.cpu1.fetch.CacheLines 191800841 # Number of cache lines fetched
> system.cpu1.fetch.IcacheSquashes 1580435 # Number of outstanding Icache misses that were squashed
> system.cpu1.fetch.ItlbSquashes 27130 # Number of outstanding ITLB misses that were squashed
> system.cpu1.fetch.rateDist::samples 643817634 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::mean 0.987423 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::stdev 1.222838 # Number of instructions fetched each cycle (Total)
1929,1932c1924,1927
< system.cpu1.fetch.rateDist::0 338710091 52.85% 52.85% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::1 117550572 18.34% 71.20% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::2 40600676 6.34% 77.53% # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.rateDist::3 143967575 22.47% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu1.fetch.rateDist::0 339738489 52.77% 52.77% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::1 118160249 18.35% 71.12% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::2 40196713 6.24% 77.37% # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.rateDist::3 145722183 22.63% 100.00% # Number of instructions fetched each cycle (Total)
1936,1983c1931,1978
< system.cpu1.fetch.rateDist::total 640828914 # Number of instructions fetched each cycle (Total)
< system.cpu1.fetch.branchRate 0.184284 # Number of branch fetches per cycle
< system.cpu1.fetch.rate 0.818052 # Number of inst fetches per cycle
< system.cpu1.decode.IdleCycles 96524622 # Number of cycles decode is idle
< system.cpu1.decode.BlockedCycles 306596217 # Number of cycles decode is blocked
< system.cpu1.decode.RunCycles 198367702 # Number of cycles decode is running
< system.cpu1.decode.UnblockCycles 34666699 # Number of cycles decode is unblocking
< system.cpu1.decode.SquashCycles 4673674 # Number of cycles decode is squashing
< system.cpu1.decode.BranchResolved 17189225 # Number of times decode resolved a branch
< system.cpu1.decode.BranchMispred 1979171 # Number of times decode detected a branch misprediction
< system.cpu1.decode.DecodedInsts 555902892 # Number of instructions handled by decode
< system.cpu1.decode.SquashedInsts 21032284 # Number of squashed instructions handled by decode
< system.cpu1.rename.SquashCycles 4673674 # Number of cycles rename is squashing
< system.cpu1.rename.IdleCycles 128741707 # Number of cycles rename is idle
< system.cpu1.rename.BlockCycles 40944507 # Number of cycles rename is blocking
< system.cpu1.rename.serializeStallCycles 207984500 # count of cycles rename stalled for serializing inst
< system.cpu1.rename.RunCycles 200380023 # Number of cycles rename is running
< system.cpu1.rename.UnblockCycles 58104503 # Number of cycles rename is unblocking
< system.cpu1.rename.RenamedInsts 540647070 # Number of instructions processed by rename
< system.cpu1.rename.SquashedInsts 5273833 # Number of squashed instructions processed by rename
< system.cpu1.rename.ROBFullEvents 8920508 # Number of times rename has blocked due to ROB full
< system.cpu1.rename.IQFullEvents 357666 # Number of times rename has blocked due to IQ full
< system.cpu1.rename.LQFullEvents 869250 # Number of times rename has blocked due to LQ full
< system.cpu1.rename.SQFullEvents 25304278 # Number of times rename has blocked due to SQ full
< system.cpu1.rename.FullRegisterEvents 12220 # Number of times there has been no free registers
< system.cpu1.rename.RenamedOperands 515542885 # Number of destination operands rename has renamed
< system.cpu1.rename.RenameLookups 838360476 # Number of register rename lookups that rename has made
< system.cpu1.rename.int_rename_lookups 639083471 # Number of integer rename lookups
< system.cpu1.rename.fp_rename_lookups 635892 # Number of floating rename lookups
< system.cpu1.rename.CommittedMaps 463444914 # Number of HB maps that are committed
< system.cpu1.rename.UndoneMaps 52097965 # Number of HB maps that are undone due to squashing
< system.cpu1.rename.serializingInsts 14931648 # count of serializing insts renamed
< system.cpu1.rename.tempSerializingInsts 13102843 # count of temporary serializing insts renamed
< system.cpu1.rename.skidInsts 69578208 # count of insts added to the skid buffer
< system.cpu1.memDep0.insertedLoads 89907304 # Number of loads inserted to the mem dependence unit.
< system.cpu1.memDep0.insertedStores 75221964 # Number of stores inserted to the mem dependence unit.
< system.cpu1.memDep0.conflictingLoads 8553187 # Number of conflicting loads.
< system.cpu1.memDep0.conflictingStores 7364919 # Number of conflicting stores.
< system.cpu1.iq.iqInstsAdded 519731744 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu1.iq.iqNonSpecInstsAdded 15160501 # Number of non-speculative instructions added to the IQ
< system.cpu1.iq.iqInstsIssued 524719232 # Number of instructions issued
< system.cpu1.iq.iqSquashedInstsIssued 2440222 # Number of squashed instructions issued
< system.cpu1.iq.iqSquashedInstsExamined 49181333 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu1.iq.iqSquashedOperandsExamined 32199370 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu1.iq.iqSquashedNonSpecRemoved 264903 # Number of squashed non-spec instructions that were removed
< system.cpu1.iq.issued_per_cycle::samples 640828914 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::mean 0.818813 # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::stdev 1.060738 # Number of insts issued each cycle
---
> system.cpu1.fetch.rateDist::total 643817634 # Number of instructions fetched each cycle (Total)
> system.cpu1.fetch.branchRate 0.183824 # Number of branch fetches per cycle
> system.cpu1.fetch.rate 0.814315 # Number of inst fetches per cycle
> system.cpu1.decode.IdleCycles 95925032 # Number of cycles decode is idle
> system.cpu1.decode.BlockedCycles 307565159 # Number of cycles decode is blocked
> system.cpu1.decode.RunCycles 202328162 # Number of cycles decode is running
> system.cpu1.decode.UnblockCycles 33349835 # Number of cycles decode is unblocking
> system.cpu1.decode.SquashCycles 4649446 # Number of cycles decode is squashing
> system.cpu1.decode.BranchResolved 17381659 # Number of times decode resolved a branch
> system.cpu1.decode.BranchMispred 1984856 # Number of times decode detected a branch misprediction
> system.cpu1.decode.DecodedInsts 561624259 # Number of instructions handled by decode
> system.cpu1.decode.SquashedInsts 21210320 # Number of squashed instructions handled by decode
> system.cpu1.rename.SquashCycles 4649446 # Number of cycles rename is squashing
> system.cpu1.rename.IdleCycles 127605464 # Number of cycles rename is idle
> system.cpu1.rename.BlockCycles 43917048 # Number of cycles rename is blocking
> system.cpu1.rename.serializeStallCycles 205458777 # count of cycles rename stalled for serializing inst
> system.cpu1.rename.RunCycles 203595973 # Number of cycles rename is running
> system.cpu1.rename.UnblockCycles 58590926 # Number of cycles rename is unblocking
> system.cpu1.rename.RenamedInsts 546425758 # Number of instructions processed by rename
> system.cpu1.rename.SquashedInsts 5335623 # Number of squashed instructions processed by rename
> system.cpu1.rename.ROBFullEvents 9251054 # Number of times rename has blocked due to ROB full
> system.cpu1.rename.IQFullEvents 227617 # Number of times rename has blocked due to IQ full
> system.cpu1.rename.LQFullEvents 291872 # Number of times rename has blocked due to LQ full
> system.cpu1.rename.SQFullEvents 27374536 # Number of times rename has blocked due to SQ full
> system.cpu1.rename.FullRegisterEvents 10500 # Number of times there has been no free registers
> system.cpu1.rename.RenamedOperands 518347442 # Number of destination operands rename has renamed
> system.cpu1.rename.RenameLookups 840457464 # Number of register rename lookups that rename has made
> system.cpu1.rename.int_rename_lookups 646223551 # Number of integer rename lookups
> system.cpu1.rename.fp_rename_lookups 691924 # Number of floating rename lookups
> system.cpu1.rename.CommittedMaps 466279930 # Number of HB maps that are committed
> system.cpu1.rename.UndoneMaps 52067506 # Number of HB maps that are undone due to squashing
> system.cpu1.rename.serializingInsts 14268129 # count of serializing insts renamed
> system.cpu1.rename.tempSerializingInsts 12524757 # count of temporary serializing insts renamed
> system.cpu1.rename.skidInsts 67234415 # count of insts added to the skid buffer
> system.cpu1.memDep0.insertedLoads 90658674 # Number of loads inserted to the mem dependence unit.
> system.cpu1.memDep0.insertedStores 77385188 # Number of stores inserted to the mem dependence unit.
> system.cpu1.memDep0.conflictingLoads 8528695 # Number of conflicting loads.
> system.cpu1.memDep0.conflictingStores 7392702 # Number of conflicting stores.
> system.cpu1.iq.iqInstsAdded 526120257 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu1.iq.iqNonSpecInstsAdded 14498185 # Number of non-speculative instructions added to the IQ
> system.cpu1.iq.iqInstsIssued 530312729 # Number of instructions issued
> system.cpu1.iq.iqSquashedInstsIssued 2450487 # Number of squashed instructions issued
> system.cpu1.iq.iqSquashedInstsExamined 49492350 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu1.iq.iqSquashedOperandsExamined 31830796 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu1.iq.iqSquashedNonSpecRemoved 264307 # Number of squashed non-spec instructions that were removed
> system.cpu1.iq.issued_per_cycle::samples 643817634 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::mean 0.823700 # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::stdev 1.068099 # Number of insts issued each cycle
1985,1990c1980,1985
< system.cpu1.iq.issued_per_cycle::0 351184657 54.80% 54.80% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::1 125580577 19.60% 74.40% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::2 99945390 15.60% 89.99% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::3 57229371 8.93% 98.92% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::4 6884833 1.07% 100.00% # Number of insts issued each cycle
< system.cpu1.iq.issued_per_cycle::5 4086 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::0 353942401 54.98% 54.98% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::1 122398683 19.01% 73.99% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::2 101611501 15.78% 89.77% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::3 58772797 9.13% 98.90% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::4 7088607 1.10% 100.00% # Number of insts issued each cycle
> system.cpu1.iq.issued_per_cycle::5 3645 0.00% 100.00% # Number of insts issued each cycle
1997c1992
< system.cpu1.iq.issued_per_cycle::total 640828914 # Number of insts issued each cycle
---
> system.cpu1.iq.issued_per_cycle::total 643817634 # Number of insts issued each cycle
1999,2029c1994,2024
< system.cpu1.iq.fu_full::IntAlu 51884545 43.66% 43.66% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntMult 60325 0.05% 43.71% # attempts to use FU when none available
< system.cpu1.iq.fu_full::IntDiv 6398 0.01% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMisc 22 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.72% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemRead 32949736 27.73% 71.45% # attempts to use FU when none available
< system.cpu1.iq.fu_full::MemWrite 33928397 28.55% 100.00% # attempts to use FU when none available
---
> system.cpu1.iq.fu_full::IntAlu 53425749 43.94% 43.94% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntMult 46790 0.04% 43.97% # attempts to use FU when none available
> system.cpu1.iq.fu_full::IntDiv 9685 0.01% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMisc 19 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.98% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemRead 32795787 26.97% 70.95% # attempts to use FU when none available
> system.cpu1.iq.fu_full::MemWrite 35319606 29.05% 100.00% # attempts to use FU when none available
2032,2063c2027,2058
< system.cpu1.iq.FU_type_0::No_OpClass 22 0.00% 0.00% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntAlu 357316080 68.10% 68.10% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntMult 1302107 0.25% 68.34% # Type of FU issued
< system.cpu1.iq.FU_type_0::IntDiv 73183 0.01% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMisc 41368 0.01% 68.37% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.37% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.37% # Type of FU issued
< system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.37% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemRead 92637950 17.65% 86.02% # Type of FU issued
< system.cpu1.iq.FU_type_0::MemWrite 73348522 13.98% 100.00% # Type of FU issued
---
> system.cpu1.iq.FU_type_0::No_OpClass 84 0.00% 0.00% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntAlu 360430820 67.97% 67.97% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntMult 1171247 0.22% 68.19% # Type of FU issued
> system.cpu1.iq.FU_type_0::IntDiv 68672 0.01% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.20% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMisc 45220 0.01% 68.21% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.21% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.21% # Type of FU issued
> system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.21% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemRead 93137728 17.56% 85.77% # Type of FU issued
> system.cpu1.iq.FU_type_0::MemWrite 75458910 14.23% 100.00% # Type of FU issued
2066,2078c2061,2073
< system.cpu1.iq.FU_type_0::total 524719232 # Type of FU issued
< system.cpu1.iq.rate 0.798530 # Inst issue rate
< system.cpu1.iq.fu_busy_cnt 118829423 # FU busy when requested
< system.cpu1.iq.fu_busy_rate 0.226463 # FU busy rate (busy events/executed inst)
< system.cpu1.iq.int_inst_queue_reads 1810487568 # Number of integer instruction queue reads
< system.cpu1.iq.int_inst_queue_writes 583794764 # Number of integer instruction queue writes
< system.cpu1.iq.int_inst_queue_wakeup_accesses 509259381 # Number of integer instruction queue wakeup accesses
< system.cpu1.iq.fp_inst_queue_reads 1049453 # Number of floating instruction queue reads
< system.cpu1.iq.fp_inst_queue_writes 417103 # Number of floating instruction queue writes
< system.cpu1.iq.fp_inst_queue_wakeup_accesses 385439 # Number of floating instruction queue wakeup accesses
< system.cpu1.iq.int_alu_accesses 642894662 # Number of integer alu accesses
< system.cpu1.iq.fp_alu_accesses 653971 # Number of floating point alu accesses
< system.cpu1.iew.lsq.thread0.forwLoads 2364683 # Number of loads that had data forwarded from stores
---
> system.cpu1.iq.FU_type_0::total 530312729 # Type of FU issued
> system.cpu1.iq.rate 0.798703 # Inst issue rate
> system.cpu1.iq.fu_busy_cnt 121597636 # FU busy when requested
> system.cpu1.iq.fu_busy_rate 0.229294 # FU busy rate (busy events/executed inst)
> system.cpu1.iq.int_inst_queue_reads 1827371450 # Number of integer instruction queue reads
> system.cpu1.iq.int_inst_queue_writes 589808611 # Number of integer instruction queue writes
> system.cpu1.iq.int_inst_queue_wakeup_accesses 515064806 # Number of integer instruction queue wakeup accesses
> system.cpu1.iq.fp_inst_queue_reads 1119763 # Number of floating instruction queue reads
> system.cpu1.iq.fp_inst_queue_writes 442884 # Number of floating instruction queue writes
> system.cpu1.iq.fp_inst_queue_wakeup_accesses 412109 # Number of floating instruction queue wakeup accesses
> system.cpu1.iq.int_alu_accesses 651211996 # Number of integer alu accesses
> system.cpu1.iq.fp_alu_accesses 698285 # Number of floating point alu accesses
> system.cpu1.iew.lsq.thread0.forwLoads 2417067 # Number of loads that had data forwarded from stores
2080,2083c2075,2078
< system.cpu1.iew.lsq.thread0.squashedLoads 11367007 # Number of loads squashed
< system.cpu1.iew.lsq.thread0.ignoredResponses 15961 # Number of memory responses ignored because the instruction is squashed
< system.cpu1.iew.lsq.thread0.memOrderViolation 139264 # Number of memory ordering violations
< system.cpu1.iew.lsq.thread0.squashedStores 5290675 # Number of stores squashed
---
> system.cpu1.iew.lsq.thread0.squashedLoads 11379314 # Number of loads squashed
> system.cpu1.iew.lsq.thread0.ignoredResponses 14413 # Number of memory responses ignored because the instruction is squashed
> system.cpu1.iew.lsq.thread0.memOrderViolation 141714 # Number of memory ordering violations
> system.cpu1.iew.lsq.thread0.squashedStores 5438356 # Number of stores squashed
2086,2087c2081,2082
< system.cpu1.iew.lsq.thread0.rescheduledLoads 2384785 # Number of loads that were rescheduled
< system.cpu1.iew.lsq.thread0.cacheBlocked 4103064 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu1.iew.lsq.thread0.rescheduledLoads 2432171 # Number of loads that were rescheduled
> system.cpu1.iew.lsq.thread0.cacheBlocked 3747564 # Number of times an access to memory failed due to the cache being blocked
2089,2092c2084,2087
< system.cpu1.iew.iewSquashCycles 4673674 # Number of cycles IEW is squashing
< system.cpu1.iew.iewBlockCycles 6987028 # Number of cycles IEW is blocking
< system.cpu1.iew.iewUnblockCycles 1738087 # Number of cycles IEW is unblocking
< system.cpu1.iew.iewDispatchedInsts 535009487 # Number of instructions dispatched to IQ
---
> system.cpu1.iew.iewSquashCycles 4649446 # Number of cycles IEW is squashing
> system.cpu1.iew.iewBlockCycles 5786949 # Number of cycles IEW is blocking
> system.cpu1.iew.iewUnblockCycles 2152685 # Number of cycles IEW is unblocking
> system.cpu1.iew.iewDispatchedInsts 540731877 # Number of instructions dispatched to IQ
2094,2105c2089,2100
< system.cpu1.iew.iewDispLoadInsts 89907304 # Number of dispatched load instructions
< system.cpu1.iew.iewDispStoreInsts 75221964 # Number of dispatched store instructions
< system.cpu1.iew.iewDispNonSpecInsts 12892176 # Number of dispatched non-speculative instructions
< system.cpu1.iew.iewIQFullEvents 53410 # Number of times the IQ has become full, causing a stall
< system.cpu1.iew.iewLSQFullEvents 1616074 # Number of times the LSQ has become full, causing a stall
< system.cpu1.iew.memOrderViolationEvents 139264 # Number of memory order violations
< system.cpu1.iew.predictedTakenIncorrect 1829419 # Number of branches that were predicted taken incorrectly
< system.cpu1.iew.predictedNotTakenIncorrect 2640296 # Number of branches that were predicted not taken incorrectly
< system.cpu1.iew.branchMispredicts 4469715 # Number of branch mispredicts detected at execute
< system.cpu1.iew.iewExecutedInsts 517720791 # Number of executed instructions
< system.cpu1.iew.iewExecLoadInsts 89804186 # Number of load instructions executed
< system.cpu1.iew.iewExecSquashedInsts 6423141 # Number of squashed instructions skipped in execute
---
> system.cpu1.iew.iewDispLoadInsts 90658674 # Number of dispatched load instructions
> system.cpu1.iew.iewDispStoreInsts 77385188 # Number of dispatched store instructions
> system.cpu1.iew.iewDispNonSpecInsts 12325629 # Number of dispatched non-speculative instructions
> system.cpu1.iew.iewIQFullEvents 58000 # Number of times the IQ has become full, causing a stall
> system.cpu1.iew.iewLSQFullEvents 2039251 # Number of times the LSQ has become full, causing a stall
> system.cpu1.iew.memOrderViolationEvents 141714 # Number of memory order violations
> system.cpu1.iew.predictedTakenIncorrect 1867697 # Number of branches that were predicted taken incorrectly
> system.cpu1.iew.predictedNotTakenIncorrect 2587615 # Number of branches that were predicted not taken incorrectly
> system.cpu1.iew.branchMispredicts 4455312 # Number of branch mispredicts detected at execute
> system.cpu1.iew.iewExecutedInsts 523333067 # Number of executed instructions
> system.cpu1.iew.iewExecLoadInsts 90385914 # Number of load instructions executed
> system.cpu1.iew.iewExecSquashedInsts 6476972 # Number of squashed instructions skipped in execute
2107,2115c2102,2110
< system.cpu1.iew.exec_nop 117242 # number of nop insts executed
< system.cpu1.iew.exec_refs 161982461 # number of memory reference insts executed
< system.cpu1.iew.exec_branches 97046647 # Number of branches executed
< system.cpu1.iew.exec_stores 72178275 # Number of stores executed
< system.cpu1.iew.exec_rate 0.787880 # Inst execution rate
< system.cpu1.iew.wb_sent 510319956 # cumulative count of insts sent to commit
< system.cpu1.iew.wb_count 509644820 # cumulative count of insts written-back
< system.cpu1.iew.wb_producers 247330259 # num instructions producing a value
< system.cpu1.iew.wb_consumers 405058762 # num instructions consuming a value
---
> system.cpu1.iew.exec_nop 113435 # number of nop insts executed
> system.cpu1.iew.exec_refs 164677509 # number of memory reference insts executed
> system.cpu1.iew.exec_branches 98047931 # Number of branches executed
> system.cpu1.iew.exec_stores 74291595 # Number of stores executed
> system.cpu1.iew.exec_rate 0.788191 # Inst execution rate
> system.cpu1.iew.wb_sent 516143321 # cumulative count of insts sent to commit
> system.cpu1.iew.wb_count 515476915 # cumulative count of insts written-back
> system.cpu1.iew.wb_producers 249234254 # num instructions producing a value
> system.cpu1.iew.wb_consumers 407965513 # num instructions consuming a value
2117,2118c2112,2113
< system.cpu1.iew.wb_rate 0.775590 # insts written-back per cycle
< system.cpu1.iew.wb_fanout 0.610603 # average fanout of values written-back
---
> system.cpu1.iew.wb_rate 0.776359 # insts written-back per cycle
> system.cpu1.iew.wb_fanout 0.610920 # average fanout of values written-back
2120,2125c2115,2120
< system.cpu1.commit.commitSquashedInsts 43050408 # The number of squashed insts skipped by commit
< system.cpu1.commit.commitNonSpecStalls 14895598 # The number of times commit has been forced to stall to communicate backwards
< system.cpu1.commit.branchMispredicts 4200514 # The number of times a branch was mispredicted
< system.cpu1.commit.committed_per_cycle::samples 632658676 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::mean 0.767730 # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::stdev 1.562752 # Number of insts commited each cycle
---
> system.cpu1.commit.commitSquashedInsts 43327267 # The number of squashed insts skipped by commit
> system.cpu1.commit.commitNonSpecStalls 14233878 # The number of times commit has been forced to stall to communicate backwards
> system.cpu1.commit.branchMispredicts 4192740 # The number of times a branch was mispredicted
> system.cpu1.commit.committed_per_cycle::samples 635627275 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::mean 0.772664 # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::stdev 1.570415 # Number of insts commited each cycle
2127,2135c2122,2130
< system.cpu1.commit.committed_per_cycle::0 417403815 65.98% 65.98% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::1 113799591 17.99% 83.96% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::2 46934435 7.42% 91.38% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::3 15547292 2.46% 93.84% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::4 10981139 1.74% 95.58% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::5 7643765 1.21% 96.78% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::6 5190686 0.82% 97.60% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::7 3150553 0.50% 98.10% # Number of insts commited each cycle
< system.cpu1.commit.committed_per_cycle::8 12007400 1.90% 100.00% # Number of insts commited each cycle
---
> system.cpu1.commit.committed_per_cycle::0 419865335 66.06% 66.06% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::1 112371204 17.68% 83.73% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::2 47717309 7.51% 91.24% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::3 15913228 2.50% 93.74% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::4 11392527 1.79% 95.54% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::5 7668933 1.21% 96.74% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::6 5369975 0.84% 97.59% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::7 3184156 0.50% 98.09% # Number of insts commited each cycle
> system.cpu1.commit.committed_per_cycle::8 12144608 1.91% 100.00% # Number of insts commited each cycle
2139,2141c2134,2136
< system.cpu1.commit.committed_per_cycle::total 632658676 # Number of insts commited each cycle
< system.cpu1.commit.committedInsts 412964348 # Number of instructions committed
< system.cpu1.commit.committedOps 485710905 # Number of ops (including micro ops) committed
---
> system.cpu1.commit.committed_per_cycle::total 635627275 # Number of insts commited each cycle
> system.cpu1.commit.committedInsts 416740074 # Number of instructions committed
> system.cpu1.commit.committedOps 491126085 # Number of ops (including micro ops) committed
2143,2149c2138,2144
< system.cpu1.commit.refs 148471585 # Number of memory references committed
< system.cpu1.commit.loads 78540296 # Number of loads committed
< system.cpu1.commit.membars 3510647 # Number of memory barriers committed
< system.cpu1.commit.branches 92021861 # Number of branches committed
< system.cpu1.commit.fp_insts 377145 # Number of committed floating point instructions.
< system.cpu1.commit.int_insts 445805015 # Number of committed integer instructions.
< system.cpu1.commit.function_calls 12220081 # Number of function calls committed.
---
> system.cpu1.commit.refs 151226191 # Number of memory references committed
> system.cpu1.commit.loads 79279359 # Number of loads committed
> system.cpu1.commit.membars 3502305 # Number of memory barriers committed
> system.cpu1.commit.branches 92953281 # Number of branches committed
> system.cpu1.commit.fp_insts 403468 # Number of committed floating point instructions.
> system.cpu1.commit.int_insts 451237639 # Number of committed integer instructions.
> system.cpu1.commit.function_calls 12195676 # Number of function calls committed.
2151,2181c2146,2176
< system.cpu1.commit.op_class_0::IntAlu 336089825 69.20% 69.20% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntMult 1056611 0.22% 69.41% # Class of committed instruction
< system.cpu1.commit.op_class_0::IntDiv 57564 0.01% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMisc 35320 0.01% 69.43% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction
< system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemRead 78540296 16.17% 85.60% # Class of committed instruction
< system.cpu1.commit.op_class_0::MemWrite 69931289 14.40% 100.00% # Class of committed instruction
---
> system.cpu1.commit.op_class_0::IntAlu 338863536 69.00% 69.00% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntMult 941904 0.19% 69.19% # Class of committed instruction
> system.cpu1.commit.op_class_0::IntDiv 54586 0.01% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.20% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMisc 39826 0.01% 69.21% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.21% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.21% # Class of committed instruction
> system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.21% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemRead 79279359 16.14% 85.35% # Class of committed instruction
> system.cpu1.commit.op_class_0::MemWrite 71946832 14.65% 100.00% # Class of committed instruction
2184,2310c2179,2305
< system.cpu1.commit.op_class_0::total 485710905 # Class of committed instruction
< system.cpu1.commit.bw_lim_events 12007400 # number cycles where commit BW limit reached
< system.cpu1.rob.rob_reads 1145678392 # The number of ROB reads
< system.cpu1.rob.rob_writes 1065656273 # The number of ROB writes
< system.cpu1.timesIdled 931363 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu1.idleCycles 16277462 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu1.quiesceCycles 93962526294 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
< system.cpu1.committedInsts 412964348 # Number of Instructions Simulated
< system.cpu1.committedOps 485710905 # Number of Ops (including micro ops) Simulated
< system.cpu1.cpi 1.591194 # CPI: Cycles Per Instruction
< system.cpu1.cpi_total 1.591194 # CPI: Total CPI of All Threads
< system.cpu1.ipc 0.628459 # IPC: Instructions Per Cycle
< system.cpu1.ipc_total 0.628459 # IPC: Total IPC of All Threads
< system.cpu1.int_regfile_reads 611833579 # number of integer regfile reads
< system.cpu1.int_regfile_writes 362533704 # number of integer regfile writes
< system.cpu1.fp_regfile_reads 622107 # number of floating regfile reads
< system.cpu1.fp_regfile_writes 321740 # number of floating regfile writes
< system.cpu1.cc_regfile_reads 111613116 # number of cc regfile reads
< system.cpu1.cc_regfile_writes 112230966 # number of cc regfile writes
< system.cpu1.misc_regfile_reads 1145938750 # number of misc regfile reads
< system.cpu1.misc_regfile_writes 14868837 # number of misc regfile writes
< system.cpu1.dcache.tags.replacements 5274603 # number of replacements
< system.cpu1.dcache.tags.tagsinuse 426.947513 # Cycle average of tags in use
< system.cpu1.dcache.tags.total_refs 137535053 # Total number of references to valid blocks.
< system.cpu1.dcache.tags.sampled_refs 5275114 # Sample count of references to valid blocks.
< system.cpu1.dcache.tags.avg_refs 26.072432 # Average number of references to valid blocks.
< system.cpu1.dcache.tags.warmup_cycle 8485200468500 # Cycle when the warmup percentage was hit.
< system.cpu1.dcache.tags.occ_blocks::cpu1.data 426.947513 # Average occupied blocks per requestor
< system.cpu1.dcache.tags.occ_percent::cpu1.data 0.833882 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_percent::total 0.833882 # Average percentage of cache occupancy
< system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id
< system.cpu1.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id
< system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
< system.cpu1.dcache.tags.tag_accesses 308540922 # Number of tag accesses
< system.cpu1.dcache.tags.data_accesses 308540922 # Number of data accesses
< system.cpu1.dcache.ReadReq_hits::cpu1.data 72744707 # number of ReadReq hits
< system.cpu1.dcache.ReadReq_hits::total 72744707 # number of ReadReq hits
< system.cpu1.dcache.WriteReq_hits::cpu1.data 60628902 # number of WriteReq hits
< system.cpu1.dcache.WriteReq_hits::total 60628902 # number of WriteReq hits
< system.cpu1.dcache.SoftPFReq_hits::cpu1.data 161948 # number of SoftPFReq hits
< system.cpu1.dcache.SoftPFReq_hits::total 161948 # number of SoftPFReq hits
< system.cpu1.dcache.WriteLineReq_hits::cpu1.data 50338 # number of WriteLineReq hits
< system.cpu1.dcache.WriteLineReq_hits::total 50338 # number of WriteLineReq hits
< system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1624470 # number of LoadLockedReq hits
< system.cpu1.dcache.LoadLockedReq_hits::total 1624470 # number of LoadLockedReq hits
< system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1636906 # number of StoreCondReq hits
< system.cpu1.dcache.StoreCondReq_hits::total 1636906 # number of StoreCondReq hits
< system.cpu1.dcache.demand_hits::cpu1.data 133373609 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 133373609 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 133535557 # number of overall hits
< system.cpu1.dcache.overall_hits::total 133535557 # number of overall hits
< system.cpu1.dcache.ReadReq_misses::cpu1.data 6201374 # number of ReadReq misses
< system.cpu1.dcache.ReadReq_misses::total 6201374 # number of ReadReq misses
< system.cpu1.dcache.WriteReq_misses::cpu1.data 6969409 # number of WriteReq misses
< system.cpu1.dcache.WriteReq_misses::total 6969409 # number of WriteReq misses
< system.cpu1.dcache.SoftPFReq_misses::cpu1.data 662990 # number of SoftPFReq misses
< system.cpu1.dcache.SoftPFReq_misses::total 662990 # number of SoftPFReq misses
< system.cpu1.dcache.WriteLineReq_misses::cpu1.data 447840 # number of WriteLineReq misses
< system.cpu1.dcache.WriteLineReq_misses::total 447840 # number of WriteLineReq misses
< system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 255439 # number of LoadLockedReq misses
< system.cpu1.dcache.LoadLockedReq_misses::total 255439 # number of LoadLockedReq misses
< system.cpu1.dcache.StoreCondReq_misses::cpu1.data 200646 # number of StoreCondReq misses
< system.cpu1.dcache.StoreCondReq_misses::total 200646 # number of StoreCondReq misses
< system.cpu1.dcache.demand_misses::cpu1.data 13170783 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 13170783 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 13833773 # number of overall misses
< system.cpu1.dcache.overall_misses::total 13833773 # number of overall misses
< system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 88228717500 # number of ReadReq miss cycles
< system.cpu1.dcache.ReadReq_miss_latency::total 88228717500 # number of ReadReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 123237994379 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteReq_miss_latency::total 123237994379 # number of WriteReq miss cycles
< system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20350455489 # number of WriteLineReq miss cycles
< system.cpu1.dcache.WriteLineReq_miss_latency::total 20350455489 # number of WriteLineReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3706894000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.LoadLockedReq_miss_latency::total 3706894000 # number of LoadLockedReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4288443500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondReq_miss_latency::total 4288443500 # number of StoreCondReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6003000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.StoreCondFailReq_miss_latency::total 6003000 # number of StoreCondFailReq miss cycles
< system.cpu1.dcache.demand_miss_latency::cpu1.data 211466711879 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 211466711879 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 211466711879 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 211466711879 # number of overall miss cycles
< system.cpu1.dcache.ReadReq_accesses::cpu1.data 78946081 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.ReadReq_accesses::total 78946081 # number of ReadReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::cpu1.data 67598311 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.WriteReq_accesses::total 67598311 # number of WriteReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 824938 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.SoftPFReq_accesses::total 824938 # number of SoftPFReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 498178 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.WriteLineReq_accesses::total 498178 # number of WriteLineReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1879909 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.LoadLockedReq_accesses::total 1879909 # number of LoadLockedReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1837552 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.StoreCondReq_accesses::total 1837552 # number of StoreCondReq accesses(hits+misses)
< system.cpu1.dcache.demand_accesses::cpu1.data 146544392 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 146544392 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 147369330 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 147369330 # number of overall (read+write) accesses
< system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.078552 # miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_miss_rate::total 0.078552 # miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.103100 # miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_miss_rate::total 0.103100 # miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.803685 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_miss_rate::total 0.803685 # miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.898956 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.WriteLineReq_miss_rate::total 0.898956 # miss rate for WriteLineReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135878 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135878 # miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.109192 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_miss_rate::total 0.109192 # miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.089876 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.089876 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.093871 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.093871 # miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14227.285356 # average ReadReq miss latency
< system.cpu1.dcache.ReadReq_avg_miss_latency::total 14227.285356 # average ReadReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17682.703710 # average WriteReq miss latency
< system.cpu1.dcache.WriteReq_avg_miss_latency::total 17682.703710 # average WriteReq miss latency
< system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45441.352914 # average WriteLineReq miss latency
< system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45441.352914 # average WriteLineReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14511.856060 # average LoadLockedReq miss latency
< system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14511.856060 # average LoadLockedReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21373.182122 # average StoreCondReq miss latency
< system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21373.182122 # average StoreCondReq miss latency
---
> system.cpu1.commit.op_class_0::total 491126085 # Class of committed instruction
> system.cpu1.commit.bw_lim_events 12144608 # number cycles where commit BW limit reached
> system.cpu1.rob.rob_reads 1154417922 # The number of ROB reads
> system.cpu1.rob.rob_writes 1077060232 # The number of ROB writes
> system.cpu1.timesIdled 910594 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu1.idleCycles 20149630 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu1.quiesceCycles 94205821171 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
> system.cpu1.committedInsts 416740074 # Number of Instructions Simulated
> system.cpu1.committedOps 491126085 # Number of Ops (including micro ops) Simulated
> system.cpu1.cpi 1.593241 # CPI: Cycles Per Instruction
> system.cpu1.cpi_total 1.593241 # CPI: Total CPI of All Threads
> system.cpu1.ipc 0.627652 # IPC: Instructions Per Cycle
> system.cpu1.ipc_total 0.627652 # IPC: Total IPC of All Threads
> system.cpu1.int_regfile_reads 618723699 # number of integer regfile reads
> system.cpu1.int_regfile_writes 366638237 # number of integer regfile writes
> system.cpu1.fp_regfile_reads 681038 # number of floating regfile reads
> system.cpu1.fp_regfile_writes 305796 # number of floating regfile writes
> system.cpu1.cc_regfile_reads 111144597 # number of cc regfile reads
> system.cpu1.cc_regfile_writes 111901561 # number of cc regfile writes
> system.cpu1.misc_regfile_reads 1146158029 # number of misc regfile reads
> system.cpu1.misc_regfile_writes 14345264 # number of misc regfile writes
> system.cpu1.dcache.tags.replacements 5008277 # number of replacements
> system.cpu1.dcache.tags.tagsinuse 444.234833 # Cycle average of tags in use
> system.cpu1.dcache.tags.total_refs 141116395 # Total number of references to valid blocks.
> system.cpu1.dcache.tags.sampled_refs 5008789 # Sample count of references to valid blocks.
> system.cpu1.dcache.tags.avg_refs 28.173755 # Average number of references to valid blocks.
> system.cpu1.dcache.tags.warmup_cycle 8487531137500 # Cycle when the warmup percentage was hit.
> system.cpu1.dcache.tags.occ_blocks::cpu1.data 444.234833 # Average occupied blocks per requestor
> system.cpu1.dcache.tags.occ_percent::cpu1.data 0.867646 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_percent::total 0.867646 # Average percentage of cache occupancy
> system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id
> system.cpu1.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
> system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu1.dcache.tags.tag_accesses 313835409 # Number of tag accesses
> system.cpu1.dcache.tags.data_accesses 313835409 # Number of data accesses
> system.cpu1.dcache.ReadReq_hits::cpu1.data 73808968 # number of ReadReq hits
> system.cpu1.dcache.ReadReq_hits::total 73808968 # number of ReadReq hits
> system.cpu1.dcache.WriteReq_hits::cpu1.data 63012404 # number of WriteReq hits
> system.cpu1.dcache.WriteReq_hits::total 63012404 # number of WriteReq hits
> system.cpu1.dcache.SoftPFReq_hits::cpu1.data 166300 # number of SoftPFReq hits
> system.cpu1.dcache.SoftPFReq_hits::total 166300 # number of SoftPFReq hits
> system.cpu1.dcache.WriteLineReq_hits::cpu1.data 49799 # number of WriteLineReq hits
> system.cpu1.dcache.WriteLineReq_hits::total 49799 # number of WriteLineReq hits
> system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1689842 # number of LoadLockedReq hits
> system.cpu1.dcache.LoadLockedReq_hits::total 1689842 # number of LoadLockedReq hits
> system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1700596 # number of StoreCondReq hits
> system.cpu1.dcache.StoreCondReq_hits::total 1700596 # number of StoreCondReq hits
> system.cpu1.dcache.demand_hits::cpu1.data 136821372 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 136821372 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 136987672 # number of overall hits
> system.cpu1.dcache.overall_hits::total 136987672 # number of overall hits
> system.cpu1.dcache.ReadReq_misses::cpu1.data 5891473 # number of ReadReq misses
> system.cpu1.dcache.ReadReq_misses::total 5891473 # number of ReadReq misses
> system.cpu1.dcache.WriteReq_misses::cpu1.data 6580040 # number of WriteReq misses
> system.cpu1.dcache.WriteReq_misses::total 6580040 # number of WriteReq misses
> system.cpu1.dcache.SoftPFReq_misses::cpu1.data 617645 # number of SoftPFReq misses
> system.cpu1.dcache.SoftPFReq_misses::total 617645 # number of SoftPFReq misses
> system.cpu1.dcache.WriteLineReq_misses::cpu1.data 417038 # number of WriteLineReq misses
> system.cpu1.dcache.WriteLineReq_misses::total 417038 # number of WriteLineReq misses
> system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 243108 # number of LoadLockedReq misses
> system.cpu1.dcache.LoadLockedReq_misses::total 243108 # number of LoadLockedReq misses
> system.cpu1.dcache.StoreCondReq_misses::cpu1.data 189778 # number of StoreCondReq misses
> system.cpu1.dcache.StoreCondReq_misses::total 189778 # number of StoreCondReq misses
> system.cpu1.dcache.demand_misses::cpu1.data 12471513 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 12471513 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 13089158 # number of overall misses
> system.cpu1.dcache.overall_misses::total 13089158 # number of overall misses
> system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 92058874500 # number of ReadReq miss cycles
> system.cpu1.dcache.ReadReq_miss_latency::total 92058874500 # number of ReadReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 133118807489 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteReq_miss_latency::total 133118807489 # number of WriteReq miss cycles
> system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16001999882 # number of WriteLineReq miss cycles
> system.cpu1.dcache.WriteLineReq_miss_latency::total 16001999882 # number of WriteLineReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3690480000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.LoadLockedReq_miss_latency::total 3690480000 # number of LoadLockedReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4542175000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondReq_miss_latency::total 4542175000 # number of StoreCondReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4462000 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4462000 # number of StoreCondFailReq miss cycles
> system.cpu1.dcache.demand_miss_latency::cpu1.data 225177681989 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 225177681989 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 225177681989 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 225177681989 # number of overall miss cycles
> system.cpu1.dcache.ReadReq_accesses::cpu1.data 79700441 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.ReadReq_accesses::total 79700441 # number of ReadReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::cpu1.data 69592444 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.WriteReq_accesses::total 69592444 # number of WriteReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 783945 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.SoftPFReq_accesses::total 783945 # number of SoftPFReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 466837 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.WriteLineReq_accesses::total 466837 # number of WriteLineReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1932950 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.LoadLockedReq_accesses::total 1932950 # number of LoadLockedReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1890374 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.StoreCondReq_accesses::total 1890374 # number of StoreCondReq accesses(hits+misses)
> system.cpu1.dcache.demand_accesses::cpu1.data 149292885 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 149292885 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 150076830 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 150076830 # number of overall (read+write) accesses
> system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.073920 # miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_miss_rate::total 0.073920 # miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.094551 # miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_miss_rate::total 0.094551 # miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.787868 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_miss_rate::total 0.787868 # miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.893327 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.WriteLineReq_miss_rate::total 0.893327 # miss rate for WriteLineReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125770 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125770 # miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100392 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100392 # miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083537 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.083537 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087216 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.087216 # miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15625.782296 # average ReadReq miss latency
> system.cpu1.dcache.ReadReq_avg_miss_latency::total 15625.782296 # average ReadReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20230.698824 # average WriteReq miss latency
> system.cpu1.dcache.WriteReq_avg_miss_latency::total 20230.698824 # average WriteReq miss latency
> system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 38370.603835 # average WriteLineReq miss latency
> system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 38370.603835 # average WriteLineReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15180.413643 # average LoadLockedReq miss latency
> system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15180.413643 # average LoadLockedReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23934.149375 # average StoreCondReq miss latency
> system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23934.149375 # average StoreCondReq miss latency
2313,2322c2308,2317
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16055.743374 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 16055.743374 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15286.264411 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 15286.264411 # average overall miss latency
< system.cpu1.dcache.blocked_cycles::no_mshrs 5662057 # number of cycles access was blocked
< system.cpu1.dcache.blocked_cycles::no_targets 20000375 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_mshrs 377912 # number of cycles access was blocked
< system.cpu1.dcache.blocked::no_targets 710012 # number of cycles access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_mshrs 14.982475 # average number of cycles each access was blocked
< system.cpu1.dcache.avg_blocked_cycles::no_targets 28.169066 # average number of cycles each access was blocked
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18055.362007 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 18055.362007 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17203.374120 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 17203.374120 # average overall miss latency
> system.cpu1.dcache.blocked_cycles::no_mshrs 4151520 # number of cycles access was blocked
> system.cpu1.dcache.blocked_cycles::no_targets 21118604 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_mshrs 339495 # number of cycles access was blocked
> system.cpu1.dcache.blocked::no_targets 658226 # number of cycles access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.228516 # average number of cycles each access was blocked
> system.cpu1.dcache.avg_blocked_cycles::no_targets 32.084123 # average number of cycles each access was blocked
2325,2412c2320,2407
< system.cpu1.dcache.writebacks::writebacks 3411546 # number of writebacks
< system.cpu1.dcache.writebacks::total 3411546 # number of writebacks
< system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3176462 # number of ReadReq MSHR hits
< system.cpu1.dcache.ReadReq_mshr_hits::total 3176462 # number of ReadReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5650771 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteReq_mshr_hits::total 5650771 # number of WriteReq MSHR hits
< system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3283 # number of WriteLineReq MSHR hits
< system.cpu1.dcache.WriteLineReq_mshr_hits::total 3283 # number of WriteLineReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 129585 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.LoadLockedReq_mshr_hits::total 129585 # number of LoadLockedReq MSHR hits
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 8827233 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 8827233 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 8827233 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 8827233 # number of overall MSHR hits
< system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3024912 # number of ReadReq MSHR misses
< system.cpu1.dcache.ReadReq_mshr_misses::total 3024912 # number of ReadReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1318638 # number of WriteReq MSHR misses
< system.cpu1.dcache.WriteReq_mshr_misses::total 1318638 # number of WriteReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 662904 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.SoftPFReq_mshr_misses::total 662904 # number of SoftPFReq MSHR misses
< system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 444557 # number of WriteLineReq MSHR misses
< system.cpu1.dcache.WriteLineReq_mshr_misses::total 444557 # number of WriteLineReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 125854 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.LoadLockedReq_mshr_misses::total 125854 # number of LoadLockedReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 200639 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.StoreCondReq_mshr_misses::total 200639 # number of StoreCondReq MSHR misses
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 4343550 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 4343550 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 5006454 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 5006454 # number of overall MSHR misses
< system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6436 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6436 # number of ReadReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 6853 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.WriteReq_mshr_uncacheable::total 6853 # number of WriteReq MSHR uncacheable
< system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 13289 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.overall_mshr_uncacheable_misses::total 13289 # number of overall MSHR uncacheable misses
< system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40779010000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40779010000 # number of ReadReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24146673124 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24146673124 # number of WriteReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13797097500 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13797097500 # number of SoftPFReq MSHR miss cycles
< system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 19809664989 # number of WriteLineReq MSHR miss cycles
< system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 19809664989 # number of WriteLineReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1736527500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1736527500 # number of LoadLockedReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4087933500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4087933500 # number of StoreCondReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5874000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5874000 # number of StoreCondFailReq MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 64925683124 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 64925683124 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 78722780624 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 78722780624 # number of overall MSHR miss cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 710484000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 710484000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 859770500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 859770500 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1570254500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1570254500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.038316 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.038316 # mshr miss rate for ReadReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019507 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019507 # mshr miss rate for WriteReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.803580 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.803580 # mshr miss rate for SoftPFReq accesses
< system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.892366 # mshr miss rate for WriteLineReq accesses
< system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.892366 # mshr miss rate for WriteLineReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066947 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066947 # mshr miss rate for LoadLockedReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.109188 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.109188 # mshr miss rate for StoreCondReq accesses
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029640 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.029640 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033972 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.033972 # mshr miss rate for overall accesses
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13481.056639 # average ReadReq mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13481.056639 # average ReadReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18311.828663 # average WriteReq mshr miss latency
< system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18311.828663 # average WriteReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20813.115474 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20813.115474 # average SoftPFReq mshr miss latency
< system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 44560.461288 # average WriteLineReq mshr miss latency
< system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 44560.461288 # average WriteLineReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13797.952389 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13797.952389 # average LoadLockedReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20374.570746 # average StoreCondReq mshr miss latency
< system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20374.570746 # average StoreCondReq mshr miss latency
---
> system.cpu1.dcache.writebacks::writebacks 3259663 # number of writebacks
> system.cpu1.dcache.writebacks::total 3259663 # number of writebacks
> system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 2995366 # number of ReadReq MSHR hits
> system.cpu1.dcache.ReadReq_mshr_hits::total 2995366 # number of ReadReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5317058 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteReq_mshr_hits::total 5317058 # number of WriteReq MSHR hits
> system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3866 # number of WriteLineReq MSHR hits
> system.cpu1.dcache.WriteLineReq_mshr_hits::total 3866 # number of WriteLineReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 125871 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.LoadLockedReq_mshr_hits::total 125871 # number of LoadLockedReq MSHR hits
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 8312424 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 8312424 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 8312424 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 8312424 # number of overall MSHR hits
> system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2896107 # number of ReadReq MSHR misses
> system.cpu1.dcache.ReadReq_mshr_misses::total 2896107 # number of ReadReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1262982 # number of WriteReq MSHR misses
> system.cpu1.dcache.WriteReq_mshr_misses::total 1262982 # number of WriteReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 617580 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.SoftPFReq_mshr_misses::total 617580 # number of SoftPFReq MSHR misses
> system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 413172 # number of WriteLineReq MSHR misses
> system.cpu1.dcache.WriteLineReq_mshr_misses::total 413172 # number of WriteLineReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 117237 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.LoadLockedReq_mshr_misses::total 117237 # number of LoadLockedReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 189777 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.StoreCondReq_mshr_misses::total 189777 # number of StoreCondReq MSHR misses
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 4159089 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 4159089 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 4776669 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 4776669 # number of overall MSHR misses
> system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6826 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6826 # number of ReadReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7171 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7171 # number of WriteReq MSHR uncacheable
> system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 13997 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.overall_mshr_uncacheable_misses::total 13997 # number of overall MSHR uncacheable misses
> system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41972381500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41972381500 # number of ReadReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 27436414661 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.WriteReq_mshr_miss_latency::total 27436414661 # number of WriteReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14179581000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14179581000 # number of SoftPFReq MSHR miss cycles
> system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 15426665382 # number of WriteLineReq MSHR miss cycles
> system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 15426665382 # number of WriteLineReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1682703500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1682703500 # number of LoadLockedReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4352455000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4352455000 # number of StoreCondReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4405000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4405000 # number of StoreCondFailReq MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69408796161 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 69408796161 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83588377161 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 83588377161 # number of overall MSHR miss cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 764918000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 764918000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 914224500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 914224500 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1679142500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1679142500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036337 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036337 # mshr miss rate for ReadReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018148 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018148 # mshr miss rate for WriteReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.787785 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.787785 # mshr miss rate for SoftPFReq accesses
> system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.885046 # mshr miss rate for WriteLineReq accesses
> system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.885046 # mshr miss rate for WriteLineReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060652 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060652 # mshr miss rate for LoadLockedReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100391 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100391 # mshr miss rate for StoreCondReq accesses
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027859 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.027859 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031828 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.031828 # mshr miss rate for overall accesses
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14492.690187 # average ReadReq mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14492.690187 # average ReadReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21723.519940 # average WriteReq mshr miss latency
> system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21723.519940 # average WriteReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22959.909647 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22959.909647 # average SoftPFReq mshr miss latency
> system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 37337.151070 # average WriteLineReq mshr miss latency
> system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 37337.151070 # average WriteLineReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14353.007156 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14353.007156 # average LoadLockedReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22934.575844 # average StoreCondReq mshr miss latency
> system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22934.575844 # average StoreCondReq mshr miss latency
2415,2424c2410,2419
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14947.608091 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14947.608091 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15724.259251 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15724.259251 # average overall mshr miss latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 110392.169049 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 110392.169049 # average ReadReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 125458.996060 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 125458.996060 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 118161.976070 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 118161.976070 # average overall mshr uncacheable latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16688.461382 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16688.461382 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17499.302791 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17499.302791 # average overall mshr miss latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112059.478465 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 112059.478465 # average ReadReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 127489.122856 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 127489.122856 # average WriteReq mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 119964.456669 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 119964.456669 # average overall mshr uncacheable latency
2426,2434c2421,2429
< system.cpu1.icache.tags.replacements 5512111 # number of replacements
< system.cpu1.icache.tags.tagsinuse 501.811781 # Cycle average of tags in use
< system.cpu1.icache.tags.total_refs 185560716 # Total number of references to valid blocks.
< system.cpu1.icache.tags.sampled_refs 5512623 # Sample count of references to valid blocks.
< system.cpu1.icache.tags.avg_refs 33.661057 # Average number of references to valid blocks.
< system.cpu1.icache.tags.warmup_cycle 8495886874000 # Cycle when the warmup percentage was hit.
< system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.811781 # Average occupied blocks per requestor
< system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980101 # Average percentage of cache occupancy
< system.cpu1.icache.tags.occ_percent::total 0.980101 # Average percentage of cache occupancy
---
> system.cpu1.icache.tags.replacements 5544230 # number of replacements
> system.cpu1.icache.tags.tagsinuse 501.780204 # Cycle average of tags in use
> system.cpu1.icache.tags.total_refs 185921865 # Total number of references to valid blocks.
> system.cpu1.icache.tags.sampled_refs 5544742 # Sample count of references to valid blocks.
> system.cpu1.icache.tags.avg_refs 33.531202 # Average number of references to valid blocks.
> system.cpu1.icache.tags.warmup_cycle 8527218243000 # Cycle when the warmup percentage was hit.
> system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.780204 # Average occupied blocks per requestor
> system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980039 # Average percentage of cache occupancy
> system.cpu1.icache.tags.occ_percent::total 0.980039 # Average percentage of cache occupancy
2436,2438c2431,2433
< system.cpu1.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id
< system.cpu1.icache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id
---
> system.cpu1.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id
> system.cpu1.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id
2440,2483c2435,2478
< system.cpu1.icache.tags.tag_accesses 388319278 # Number of tag accesses
< system.cpu1.icache.tags.data_accesses 388319278 # Number of data accesses
< system.cpu1.icache.ReadReq_hits::cpu1.inst 185560716 # number of ReadReq hits
< system.cpu1.icache.ReadReq_hits::total 185560716 # number of ReadReq hits
< system.cpu1.icache.demand_hits::cpu1.inst 185560716 # number of demand (read+write) hits
< system.cpu1.icache.demand_hits::total 185560716 # number of demand (read+write) hits
< system.cpu1.icache.overall_hits::cpu1.inst 185560716 # number of overall hits
< system.cpu1.icache.overall_hits::total 185560716 # number of overall hits
< system.cpu1.icache.ReadReq_misses::cpu1.inst 5842603 # number of ReadReq misses
< system.cpu1.icache.ReadReq_misses::total 5842603 # number of ReadReq misses
< system.cpu1.icache.demand_misses::cpu1.inst 5842603 # number of demand (read+write) misses
< system.cpu1.icache.demand_misses::total 5842603 # number of demand (read+write) misses
< system.cpu1.icache.overall_misses::cpu1.inst 5842603 # number of overall misses
< system.cpu1.icache.overall_misses::total 5842603 # number of overall misses
< system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 60453928731 # number of ReadReq miss cycles
< system.cpu1.icache.ReadReq_miss_latency::total 60453928731 # number of ReadReq miss cycles
< system.cpu1.icache.demand_miss_latency::cpu1.inst 60453928731 # number of demand (read+write) miss cycles
< system.cpu1.icache.demand_miss_latency::total 60453928731 # number of demand (read+write) miss cycles
< system.cpu1.icache.overall_miss_latency::cpu1.inst 60453928731 # number of overall miss cycles
< system.cpu1.icache.overall_miss_latency::total 60453928731 # number of overall miss cycles
< system.cpu1.icache.ReadReq_accesses::cpu1.inst 191403319 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.ReadReq_accesses::total 191403319 # number of ReadReq accesses(hits+misses)
< system.cpu1.icache.demand_accesses::cpu1.inst 191403319 # number of demand (read+write) accesses
< system.cpu1.icache.demand_accesses::total 191403319 # number of demand (read+write) accesses
< system.cpu1.icache.overall_accesses::cpu1.inst 191403319 # number of overall (read+write) accesses
< system.cpu1.icache.overall_accesses::total 191403319 # number of overall (read+write) accesses
< system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030525 # miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_miss_rate::total 0.030525 # miss rate for ReadReq accesses
< system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030525 # miss rate for demand accesses
< system.cpu1.icache.demand_miss_rate::total 0.030525 # miss rate for demand accesses
< system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030525 # miss rate for overall accesses
< system.cpu1.icache.overall_miss_rate::total 0.030525 # miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10347.088230 # average ReadReq miss latency
< system.cpu1.icache.ReadReq_avg_miss_latency::total 10347.088230 # average ReadReq miss latency
< system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10347.088230 # average overall miss latency
< system.cpu1.icache.demand_avg_miss_latency::total 10347.088230 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10347.088230 # average overall miss latency
< system.cpu1.icache.overall_avg_miss_latency::total 10347.088230 # average overall miss latency
< system.cpu1.icache.blocked_cycles::no_mshrs 8745745 # number of cycles access was blocked
< system.cpu1.icache.blocked_cycles::no_targets 74 # number of cycles access was blocked
< system.cpu1.icache.blocked::no_mshrs 694595 # number of cycles access was blocked
< system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
< system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.591143 # average number of cycles each access was blocked
< system.cpu1.icache.avg_blocked_cycles::no_targets 74 # average number of cycles each access was blocked
---
> system.cpu1.icache.tags.tag_accesses 389132386 # Number of tag accesses
> system.cpu1.icache.tags.data_accesses 389132386 # Number of data accesses
> system.cpu1.icache.ReadReq_hits::cpu1.inst 185921865 # number of ReadReq hits
> system.cpu1.icache.ReadReq_hits::total 185921865 # number of ReadReq hits
> system.cpu1.icache.demand_hits::cpu1.inst 185921865 # number of demand (read+write) hits
> system.cpu1.icache.demand_hits::total 185921865 # number of demand (read+write) hits
> system.cpu1.icache.overall_hits::cpu1.inst 185921865 # number of overall hits
> system.cpu1.icache.overall_hits::total 185921865 # number of overall hits
> system.cpu1.icache.ReadReq_misses::cpu1.inst 5871956 # number of ReadReq misses
> system.cpu1.icache.ReadReq_misses::total 5871956 # number of ReadReq misses
> system.cpu1.icache.demand_misses::cpu1.inst 5871956 # number of demand (read+write) misses
> system.cpu1.icache.demand_misses::total 5871956 # number of demand (read+write) misses
> system.cpu1.icache.overall_misses::cpu1.inst 5871956 # number of overall misses
> system.cpu1.icache.overall_misses::total 5871956 # number of overall misses
> system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 64156067699 # number of ReadReq miss cycles
> system.cpu1.icache.ReadReq_miss_latency::total 64156067699 # number of ReadReq miss cycles
> system.cpu1.icache.demand_miss_latency::cpu1.inst 64156067699 # number of demand (read+write) miss cycles
> system.cpu1.icache.demand_miss_latency::total 64156067699 # number of demand (read+write) miss cycles
> system.cpu1.icache.overall_miss_latency::cpu1.inst 64156067699 # number of overall miss cycles
> system.cpu1.icache.overall_miss_latency::total 64156067699 # number of overall miss cycles
> system.cpu1.icache.ReadReq_accesses::cpu1.inst 191793821 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.ReadReq_accesses::total 191793821 # number of ReadReq accesses(hits+misses)
> system.cpu1.icache.demand_accesses::cpu1.inst 191793821 # number of demand (read+write) accesses
> system.cpu1.icache.demand_accesses::total 191793821 # number of demand (read+write) accesses
> system.cpu1.icache.overall_accesses::cpu1.inst 191793821 # number of overall (read+write) accesses
> system.cpu1.icache.overall_accesses::total 191793821 # number of overall (read+write) accesses
> system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030616 # miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_miss_rate::total 0.030616 # miss rate for ReadReq accesses
> system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030616 # miss rate for demand accesses
> system.cpu1.icache.demand_miss_rate::total 0.030616 # miss rate for demand accesses
> system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030616 # miss rate for overall accesses
> system.cpu1.icache.overall_miss_rate::total 0.030616 # miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10925.842717 # average ReadReq miss latency
> system.cpu1.icache.ReadReq_avg_miss_latency::total 10925.842717 # average ReadReq miss latency
> system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10925.842717 # average overall miss latency
> system.cpu1.icache.demand_avg_miss_latency::total 10925.842717 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10925.842717 # average overall miss latency
> system.cpu1.icache.overall_avg_miss_latency::total 10925.842717 # average overall miss latency
> system.cpu1.icache.blocked_cycles::no_mshrs 9696468 # number of cycles access was blocked
> system.cpu1.icache.blocked_cycles::no_targets 348 # number of cycles access was blocked
> system.cpu1.icache.blocked::no_mshrs 701587 # number of cycles access was blocked
> system.cpu1.icache.blocked::no_targets 5 # number of cycles access was blocked
> system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.820763 # average number of cycles each access was blocked
> system.cpu1.icache.avg_blocked_cycles::no_targets 69.600000 # average number of cycles each access was blocked
2486,2497c2481,2492
< system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 329963 # number of ReadReq MSHR hits
< system.cpu1.icache.ReadReq_mshr_hits::total 329963 # number of ReadReq MSHR hits
< system.cpu1.icache.demand_mshr_hits::cpu1.inst 329963 # number of demand (read+write) MSHR hits
< system.cpu1.icache.demand_mshr_hits::total 329963 # number of demand (read+write) MSHR hits
< system.cpu1.icache.overall_mshr_hits::cpu1.inst 329963 # number of overall MSHR hits
< system.cpu1.icache.overall_mshr_hits::total 329963 # number of overall MSHR hits
< system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5512640 # number of ReadReq MSHR misses
< system.cpu1.icache.ReadReq_mshr_misses::total 5512640 # number of ReadReq MSHR misses
< system.cpu1.icache.demand_mshr_misses::cpu1.inst 5512640 # number of demand (read+write) MSHR misses
< system.cpu1.icache.demand_mshr_misses::total 5512640 # number of demand (read+write) MSHR misses
< system.cpu1.icache.overall_mshr_misses::cpu1.inst 5512640 # number of overall MSHR misses
< system.cpu1.icache.overall_mshr_misses::total 5512640 # number of overall MSHR misses
---
> system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 327212 # number of ReadReq MSHR hits
> system.cpu1.icache.ReadReq_mshr_hits::total 327212 # number of ReadReq MSHR hits
> system.cpu1.icache.demand_mshr_hits::cpu1.inst 327212 # number of demand (read+write) MSHR hits
> system.cpu1.icache.demand_mshr_hits::total 327212 # number of demand (read+write) MSHR hits
> system.cpu1.icache.overall_mshr_hits::cpu1.inst 327212 # number of overall MSHR hits
> system.cpu1.icache.overall_mshr_hits::total 327212 # number of overall MSHR hits
> system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5544744 # number of ReadReq MSHR misses
> system.cpu1.icache.ReadReq_mshr_misses::total 5544744 # number of ReadReq MSHR misses
> system.cpu1.icache.demand_mshr_misses::cpu1.inst 5544744 # number of demand (read+write) MSHR misses
> system.cpu1.icache.demand_mshr_misses::total 5544744 # number of demand (read+write) MSHR misses
> system.cpu1.icache.overall_mshr_misses::cpu1.inst 5544744 # number of overall MSHR misses
> system.cpu1.icache.overall_mshr_misses::total 5544744 # number of overall MSHR misses
2502,2527c2497,2522
< system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 54827935019 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_miss_latency::total 54827935019 # number of ReadReq MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 54827935019 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.demand_mshr_miss_latency::total 54827935019 # number of demand (read+write) MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 54827935019 # number of overall MSHR miss cycles
< system.cpu1.icache.overall_mshr_miss_latency::total 54827935019 # number of overall MSHR miss cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5791998 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5791998 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5791998 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.overall_mshr_uncacheable_latency::total 5791998 # number of overall MSHR uncacheable cycles
< system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028801 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028801 # mshr miss rate for ReadReq accesses
< system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028801 # mshr miss rate for demand accesses
< system.cpu1.icache.demand_mshr_miss_rate::total 0.028801 # mshr miss rate for demand accesses
< system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028801 # mshr miss rate for overall accesses
< system.cpu1.icache.overall_mshr_miss_rate::total 0.028801 # mshr miss rate for overall accesses
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9945.858068 # average ReadReq mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9945.858068 # average ReadReq mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9945.858068 # average overall mshr miss latency
< system.cpu1.icache.demand_avg_mshr_miss_latency::total 9945.858068 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9945.858068 # average overall mshr miss latency
< system.cpu1.icache.overall_avg_mshr_miss_latency::total 9945.858068 # average overall mshr miss latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86447.731343 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86447.731343 # average ReadReq mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86447.731343 # average overall mshr uncacheable latency
< system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86447.731343 # average overall mshr uncacheable latency
---
> system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 57863828928 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_miss_latency::total 57863828928 # number of ReadReq MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 57863828928 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.demand_mshr_miss_latency::total 57863828928 # number of demand (read+write) MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 57863828928 # number of overall MSHR miss cycles
> system.cpu1.icache.overall_mshr_miss_latency::total 57863828928 # number of overall MSHR miss cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8907998 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8907998 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8907998 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.overall_mshr_uncacheable_latency::total 8907998 # number of overall MSHR uncacheable cycles
> system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028910 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028910 # mshr miss rate for ReadReq accesses
> system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028910 # mshr miss rate for demand accesses
> system.cpu1.icache.demand_mshr_miss_rate::total 0.028910 # mshr miss rate for demand accesses
> system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028910 # mshr miss rate for overall accesses
> system.cpu1.icache.overall_mshr_miss_rate::total 0.028910 # mshr miss rate for overall accesses
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10435.798105 # average ReadReq mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10435.798105 # average ReadReq mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10435.798105 # average overall mshr miss latency
> system.cpu1.icache.demand_avg_mshr_miss_latency::total 10435.798105 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10435.798105 # average overall mshr miss latency
> system.cpu1.icache.overall_avg_mshr_miss_latency::total 10435.798105 # average overall mshr miss latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132955.194030 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132955.194030 # average ReadReq mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132955.194030 # average overall mshr uncacheable latency
> system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132955.194030 # average overall mshr uncacheable latency
2529,2531c2524,2526
< system.cpu1.l2cache.prefetcher.num_hwpf_issued 7331800 # number of hwpf issued
< system.cpu1.l2cache.prefetcher.pfIdentified 7336274 # number of prefetch candidates identified
< system.cpu1.l2cache.prefetcher.pfBufferHit 4099 # number of redundant prefetches already in prefetch queue
---
> system.cpu1.l2cache.prefetcher.num_hwpf_issued 6820164 # number of hwpf issued
> system.cpu1.l2cache.prefetcher.pfIdentified 6823757 # number of prefetch candidates identified
> system.cpu1.l2cache.prefetcher.pfBufferHit 3326 # number of redundant prefetches already in prefetch queue
2534,2688c2529,2685
< system.cpu1.l2cache.prefetcher.pfSpanPage 897950 # number of prefetches not generated due to page crossing
< system.cpu1.l2cache.tags.replacements 2207622 # number of replacements
< system.cpu1.l2cache.tags.tagsinuse 13131.101294 # Cycle average of tags in use
< system.cpu1.l2cache.tags.total_refs 18758807 # Total number of references to valid blocks.
< system.cpu1.l2cache.tags.sampled_refs 2223617 # Sample count of references to valid blocks.
< system.cpu1.l2cache.tags.avg_refs 8.436168 # Average number of references to valid blocks.
< system.cpu1.l2cache.tags.warmup_cycle 9687561014000 # Cycle when the warmup percentage was hit.
< system.cpu1.l2cache.tags.occ_blocks::writebacks 5032.423158 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 78.618743 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 86.333738 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3261.641393 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3759.864250 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 912.220012 # Average occupied blocks per requestor
< system.cpu1.l2cache.tags.occ_percent::writebacks 0.307155 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004799 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005269 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199075 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.229484 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055677 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_percent::total 0.801459 # Average percentage of cache occupancy
< system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1285 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1023 80 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14630 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 33 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 250 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 623 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 379 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 53 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1375 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5281 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4801 # Occupied blocks per task id
< system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3028 # Occupied blocks per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078430 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004883 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.892944 # Percentage of cache occupancy per task id
< system.cpu1.l2cache.tags.tag_accesses 369655582 # Number of tag accesses
< system.cpu1.l2cache.tags.data_accesses 369655582 # Number of data accesses
< system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 548671 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 168948 # number of ReadReq hits
< system.cpu1.l2cache.ReadReq_hits::total 717619 # number of ReadReq hits
< system.cpu1.l2cache.Writeback_hits::writebacks 3411534 # number of Writeback hits
< system.cpu1.l2cache.Writeback_hits::total 3411534 # number of Writeback hits
< system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 70189 # number of UpgradeReq hits
< system.cpu1.l2cache.UpgradeReq_hits::total 70189 # number of UpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 33871 # number of SCUpgradeReq hits
< system.cpu1.l2cache.SCUpgradeReq_hits::total 33871 # number of SCUpgradeReq hits
< system.cpu1.l2cache.ReadExReq_hits::cpu1.data 868044 # number of ReadExReq hits
< system.cpu1.l2cache.ReadExReq_hits::total 868044 # number of ReadExReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4905635 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadCleanReq_hits::total 4905635 # number of ReadCleanReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2835466 # number of ReadSharedReq hits
< system.cpu1.l2cache.ReadSharedReq_hits::total 2835466 # number of ReadSharedReq hits
< system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 174715 # number of InvalidateReq hits
< system.cpu1.l2cache.InvalidateReq_hits::total 174715 # number of InvalidateReq hits
< system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 548671 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.itb.walker 168948 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.inst 4905635 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::cpu1.data 3703510 # number of demand (read+write) hits
< system.cpu1.l2cache.demand_hits::total 9326764 # number of demand (read+write) hits
< system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 548671 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.itb.walker 168948 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.inst 4905635 # number of overall hits
< system.cpu1.l2cache.overall_hits::cpu1.data 3703510 # number of overall hits
< system.cpu1.l2cache.overall_hits::total 9326764 # number of overall hits
< system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11848 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8514 # number of ReadReq misses
< system.cpu1.l2cache.ReadReq_misses::total 20362 # number of ReadReq misses
< system.cpu1.l2cache.Writeback_misses::writebacks 12 # number of Writeback misses
< system.cpu1.l2cache.Writeback_misses::total 12 # number of Writeback misses
< system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 139128 # number of UpgradeReq misses
< system.cpu1.l2cache.UpgradeReq_misses::total 139128 # number of UpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 166752 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeReq_misses::total 166752 # number of SCUpgradeReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 16 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.SCUpgradeFailReq_misses::total 16 # number of SCUpgradeFailReq misses
< system.cpu1.l2cache.ReadExReq_misses::cpu1.data 247689 # number of ReadExReq misses
< system.cpu1.l2cache.ReadExReq_misses::total 247689 # number of ReadExReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 607002 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadCleanReq_misses::total 607002 # number of ReadCleanReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 976114 # number of ReadSharedReq misses
< system.cpu1.l2cache.ReadSharedReq_misses::total 976114 # number of ReadSharedReq misses
< system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 268832 # number of InvalidateReq misses
< system.cpu1.l2cache.InvalidateReq_misses::total 268832 # number of InvalidateReq misses
< system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11848 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8514 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.inst 607002 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::cpu1.data 1223803 # number of demand (read+write) misses
< system.cpu1.l2cache.demand_misses::total 1851167 # number of demand (read+write) misses
< system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11848 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8514 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.inst 607002 # number of overall misses
< system.cpu1.l2cache.overall_misses::cpu1.data 1223803 # number of overall misses
< system.cpu1.l2cache.overall_misses::total 1851167 # number of overall misses
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 446786000 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 357242500 # number of ReadReq miss cycles
< system.cpu1.l2cache.ReadReq_miss_latency::total 804028500 # number of ReadReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2996930500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.UpgradeReq_miss_latency::total 2996930500 # number of UpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3475655499 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3475655499 # number of SCUpgradeReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 5675991 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 5675991 # number of SCUpgradeFailReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11909522998 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadExReq_miss_latency::total 11909522998 # number of ReadExReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 17320734000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadCleanReq_miss_latency::total 17320734000 # number of ReadCleanReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31800458472 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.ReadSharedReq_miss_latency::total 31800458472 # number of ReadSharedReq miss cycles
< system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 17606608999 # number of InvalidateReq miss cycles
< system.cpu1.l2cache.InvalidateReq_miss_latency::total 17606608999 # number of InvalidateReq miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 446786000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 357242500 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.inst 17320734000 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::cpu1.data 43709981470 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.demand_miss_latency::total 61834743970 # number of demand (read+write) miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 446786000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 357242500 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.inst 17320734000 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::cpu1.data 43709981470 # number of overall miss cycles
< system.cpu1.l2cache.overall_miss_latency::total 61834743970 # number of overall miss cycles
< system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 560519 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 177462 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.ReadReq_accesses::total 737981 # number of ReadReq accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::writebacks 3411546 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.Writeback_accesses::total 3411546 # number of Writeback accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 209317 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.UpgradeReq_accesses::total 209317 # number of UpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 200623 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeReq_accesses::total 200623 # number of SCUpgradeReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 16 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 16 # number of SCUpgradeFailReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1115733 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadExReq_accesses::total 1115733 # number of ReadExReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5512637 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadCleanReq_accesses::total 5512637 # number of ReadCleanReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3811580 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.ReadSharedReq_accesses::total 3811580 # number of ReadSharedReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 443547 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.InvalidateReq_accesses::total 443547 # number of InvalidateReq accesses(hits+misses)
< system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 560519 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 177462 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.inst 5512637 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::cpu1.data 4927313 # number of demand (read+write) accesses
< system.cpu1.l2cache.demand_accesses::total 11177931 # number of demand (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 560519 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 177462 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.inst 5512637 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::cpu1.data 4927313 # number of overall (read+write) accesses
< system.cpu1.l2cache.overall_accesses::total 11177931 # number of overall (read+write) accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021138 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.047976 # miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_miss_rate::total 0.027591 # miss rate for ReadReq accesses
---
> system.cpu1.l2cache.prefetcher.pfSpanPage 803331 # number of prefetches not generated due to page crossing
> system.cpu1.l2cache.tags.replacements 1997658 # number of replacements
> system.cpu1.l2cache.tags.tagsinuse 13422.615868 # Cycle average of tags in use
> system.cpu1.l2cache.tags.total_refs 18456162 # Total number of references to valid blocks.
> system.cpu1.l2cache.tags.sampled_refs 2013697 # Sample count of references to valid blocks.
> system.cpu1.l2cache.tags.avg_refs 9.165312 # Average number of references to valid blocks.
> system.cpu1.l2cache.tags.warmup_cycle 9617415490500 # Cycle when the warmup percentage was hit.
> system.cpu1.l2cache.tags.occ_blocks::writebacks 3897.343042 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.015363 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 51.895680 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3723.378261 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.data 4768.192327 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 915.791195 # Average occupied blocks per requestor
> system.cpu1.l2cache.tags.occ_percent::writebacks 0.237875 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004029 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003167 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.227257 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.291027 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055895 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_percent::total 0.819251 # Average percentage of cache occupancy
> system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1310 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1023 85 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14644 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 29 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 243 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 653 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 377 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 38 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 23 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1361 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5328 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4585 # Occupied blocks per task id
> system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3240 # Occupied blocks per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.079956 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.893799 # Percentage of cache occupancy per task id
> system.cpu1.l2cache.tags.tag_accesses 360770404 # Number of tag accesses
> system.cpu1.l2cache.tags.data_accesses 360770404 # Number of data accesses
> system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 497732 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 168884 # number of ReadReq hits
> system.cpu1.l2cache.ReadReq_hits::total 666616 # number of ReadReq hits
> system.cpu1.l2cache.Writeback_hits::writebacks 3259650 # number of Writeback hits
> system.cpu1.l2cache.Writeback_hits::total 3259650 # number of Writeback hits
> system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 66819 # number of UpgradeReq hits
> system.cpu1.l2cache.UpgradeReq_hits::total 66819 # number of UpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 31621 # number of SCUpgradeReq hits
> system.cpu1.l2cache.SCUpgradeReq_hits::total 31621 # number of SCUpgradeReq hits
> system.cpu1.l2cache.ReadExReq_hits::cpu1.data 793791 # number of ReadExReq hits
> system.cpu1.l2cache.ReadExReq_hits::total 793791 # number of ReadExReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4983800 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadCleanReq_hits::total 4983800 # number of ReadCleanReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2698278 # number of ReadSharedReq hits
> system.cpu1.l2cache.ReadSharedReq_hits::total 2698278 # number of ReadSharedReq hits
> system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 190326 # number of InvalidateReq hits
> system.cpu1.l2cache.InvalidateReq_hits::total 190326 # number of InvalidateReq hits
> system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 497732 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.itb.walker 168884 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.inst 4983800 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::cpu1.data 3492069 # number of demand (read+write) hits
> system.cpu1.l2cache.demand_hits::total 9142485 # number of demand (read+write) hits
> system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 497732 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.itb.walker 168884 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.inst 4983800 # number of overall hits
> system.cpu1.l2cache.overall_hits::cpu1.data 3492069 # number of overall hits
> system.cpu1.l2cache.overall_hits::total 9142485 # number of overall hits
> system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10518 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7585 # number of ReadReq misses
> system.cpu1.l2cache.ReadReq_misses::total 18103 # number of ReadReq misses
> system.cpu1.l2cache.Writeback_misses::writebacks 13 # number of Writeback misses
> system.cpu1.l2cache.Writeback_misses::total 13 # number of Writeback misses
> system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 142287 # number of UpgradeReq misses
> system.cpu1.l2cache.UpgradeReq_misses::total 142287 # number of UpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158148 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeReq_misses::total 158148 # number of SCUpgradeReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 8 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses
> system.cpu1.l2cache.ReadExReq_misses::cpu1.data 268312 # number of ReadExReq misses
> system.cpu1.l2cache.ReadExReq_misses::total 268312 # number of ReadExReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 560943 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadCleanReq_misses::total 560943 # number of ReadCleanReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 929119 # number of ReadSharedReq misses
> system.cpu1.l2cache.ReadSharedReq_misses::total 929119 # number of ReadSharedReq misses
> system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 221533 # number of InvalidateReq misses
> system.cpu1.l2cache.InvalidateReq_misses::total 221533 # number of InvalidateReq misses
> system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10518 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7585 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.inst 560943 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::cpu1.data 1197431 # number of demand (read+write) misses
> system.cpu1.l2cache.demand_misses::total 1776477 # number of demand (read+write) misses
> system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10518 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7585 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.inst 560943 # number of overall misses
> system.cpu1.l2cache.overall_misses::cpu1.data 1197431 # number of overall misses
> system.cpu1.l2cache.overall_misses::total 1776477 # number of overall misses
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 440507000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 317156000 # number of ReadReq miss cycles
> system.cpu1.l2cache.ReadReq_miss_latency::total 757663000 # number of ReadReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 4278657000 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.UpgradeReq_miss_latency::total 4278657000 # number of UpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3704095999 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3704095999 # number of SCUpgradeReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4317497 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4317497 # number of SCUpgradeFailReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 13921759999 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadExReq_miss_latency::total 13921759999 # number of ReadExReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 19818008500 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadCleanReq_miss_latency::total 19818008500 # number of ReadCleanReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 34488387987 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.ReadSharedReq_miss_latency::total 34488387987 # number of ReadSharedReq miss cycles
> system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 13205591500 # number of InvalidateReq miss cycles
> system.cpu1.l2cache.InvalidateReq_miss_latency::total 13205591500 # number of InvalidateReq miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 440507000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 317156000 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.inst 19818008500 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::cpu1.data 48410147986 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.demand_miss_latency::total 68985819486 # number of demand (read+write) miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 440507000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 317156000 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.inst 19818008500 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::cpu1.data 48410147986 # number of overall miss cycles
> system.cpu1.l2cache.overall_miss_latency::total 68985819486 # number of overall miss cycles
> system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 508250 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 176469 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.ReadReq_accesses::total 684719 # number of ReadReq accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::writebacks 3259663 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.Writeback_accesses::total 3259663 # number of Writeback accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 209106 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.UpgradeReq_accesses::total 209106 # number of UpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 189769 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeReq_accesses::total 189769 # number of SCUpgradeReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 8 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1062103 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadExReq_accesses::total 1062103 # number of ReadExReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5544743 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadCleanReq_accesses::total 5544743 # number of ReadCleanReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3627397 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.ReadSharedReq_accesses::total 3627397 # number of ReadSharedReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 411859 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.InvalidateReq_accesses::total 411859 # number of InvalidateReq accesses(hits+misses)
> system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 508250 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 176469 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.inst 5544743 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::cpu1.data 4689500 # number of demand (read+write) accesses
> system.cpu1.l2cache.demand_accesses::total 10918962 # number of demand (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 508250 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 176469 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.inst 5544743 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::cpu1.data 4689500 # number of overall (read+write) accesses
> system.cpu1.l2cache.overall_accesses::total 10918962 # number of overall (read+write) accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020695 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.042982 # miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_miss_rate::total 0.026439 # miss rate for ReadReq accesses
2691,2694c2688,2691
< system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.664676 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.664676 # miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.831171 # miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.831171 # miss rate for SCUpgradeReq accesses
---
> system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.680454 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.680454 # miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.833371 # miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.833371 # miss rate for SCUpgradeReq accesses
2697,2742c2694,2739
< system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.221997 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_miss_rate::total 0.221997 # miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.110111 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.110111 # miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.256092 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.256092 # miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.606096 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.606096 # miss rate for InvalidateReq accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021138 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.047976 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110111 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.248371 # miss rate for demand accesses
< system.cpu1.l2cache.demand_miss_rate::total 0.165609 # miss rate for demand accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021138 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.047976 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110111 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.248371 # miss rate for overall accesses
< system.cpu1.l2cache.overall_miss_rate::total 0.165609 # miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 37709.824443 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41959.419779 # average ReadReq miss latency
< system.cpu1.l2cache.ReadReq_avg_miss_latency::total 39486.715450 # average ReadReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21540.814933 # average UpgradeReq miss latency
< system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21540.814933 # average UpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20843.261244 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20843.261244 # average SCUpgradeReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 354749.437500 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 354749.437500 # average SCUpgradeFailReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 48082.567244 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 48082.567244 # average ReadExReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 28534.887859 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 28534.887859 # average ReadCleanReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32578.631668 # average ReadSharedReq miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32578.631668 # average ReadSharedReq miss latency
< system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 65492.980743 # average InvalidateReq miss latency
< system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 65492.980743 # average InvalidateReq miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 37709.824443 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41959.419779 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28534.887859 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35716.517667 # average overall miss latency
< system.cpu1.l2cache.demand_avg_miss_latency::total 33403.114884 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 37709.824443 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41959.419779 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28534.887859 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35716.517667 # average overall miss latency
< system.cpu1.l2cache.overall_avg_miss_latency::total 33403.114884 # average overall miss latency
< system.cpu1.l2cache.blocked_cycles::no_mshrs 2210 # number of cycles access was blocked
---
> system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.252623 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_miss_rate::total 0.252623 # miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.101167 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.101167 # miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.256139 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.256139 # miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.537886 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.537886 # miss rate for InvalidateReq accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020695 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.042982 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.101167 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.255343 # miss rate for demand accesses
> system.cpu1.l2cache.demand_miss_rate::total 0.162697 # miss rate for demand accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020695 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.042982 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.101167 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.255343 # miss rate for overall accesses
> system.cpu1.l2cache.overall_miss_rate::total 0.162697 # miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 41881.251188 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41813.579433 # average ReadReq miss latency
> system.cpu1.l2cache.ReadReq_avg_miss_latency::total 41852.897310 # average ReadReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 30070.610808 # average UpgradeReq miss latency
> system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 30070.610808 # average UpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 23421.706244 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 23421.706244 # average SCUpgradeReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 539687.125000 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 539687.125000 # average SCUpgradeFailReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51886.460535 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51886.460535 # average ReadExReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35329.808020 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35329.808020 # average ReadCleanReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 37119.451854 # average ReadSharedReq miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 37119.451854 # average ReadSharedReq miss latency
> system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 59610.042296 # average InvalidateReq miss latency
> system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 59610.042296 # average InvalidateReq miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 41881.251188 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41813.579433 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35329.808020 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 40428.340327 # average overall miss latency
> system.cpu1.l2cache.demand_avg_miss_latency::total 38832.937035 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 41881.251188 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41813.579433 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35329.808020 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40428.340327 # average overall miss latency
> system.cpu1.l2cache.overall_avg_miss_latency::total 38832.937035 # average overall miss latency
> system.cpu1.l2cache.blocked_cycles::no_mshrs 1044 # number of cycles access was blocked
2744c2741
< system.cpu1.l2cache.blocked::no_mshrs 13 # number of cycles access was blocked
---
> system.cpu1.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked
2746c2743
< system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 170 # average number of cycles each access was blocked
---
> system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 348 # average number of cycles each access was blocked
2750,2802c2747,2799
< system.cpu1.l2cache.writebacks::writebacks 1027358 # number of writebacks
< system.cpu1.l2cache.writebacks::total 1027358 # number of writebacks
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 2 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 142 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_hits::total 144 # number of ReadReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 12070 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadExReq_mshr_hits::total 12070 # number of ReadExReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 3614 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 3614 # number of ReadSharedReq MSHR hits
< system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 3 # number of InvalidateReq MSHR hits
< system.cpu1.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 2 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 142 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::cpu1.data 15684 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.demand_mshr_hits::total 15828 # number of demand (read+write) MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 2 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 142 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::cpu1.data 15684 # number of overall MSHR hits
< system.cpu1.l2cache.overall_mshr_hits::total 15828 # number of overall MSHR hits
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11846 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8372 # number of ReadReq MSHR misses
< system.cpu1.l2cache.ReadReq_mshr_misses::total 20218 # number of ReadReq MSHR misses
< system.cpu1.l2cache.Writeback_mshr_misses::writebacks 12 # number of Writeback MSHR misses
< system.cpu1.l2cache.Writeback_mshr_misses::total 12 # number of Writeback MSHR misses
< system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 104589 # number of CleanEvict MSHR misses
< system.cpu1.l2cache.CleanEvict_mshr_misses::total 104589 # number of CleanEvict MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 722741 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.HardPFReq_mshr_misses::total 722741 # number of HardPFReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 139128 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.UpgradeReq_mshr_misses::total 139128 # number of UpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 166752 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 166752 # number of SCUpgradeReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 16 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 16 # number of SCUpgradeFailReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 235619 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadExReq_mshr_misses::total 235619 # number of ReadExReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 607002 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 607002 # number of ReadCleanReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 972500 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 972500 # number of ReadSharedReq MSHR misses
< system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 268829 # number of InvalidateReq MSHR misses
< system.cpu1.l2cache.InvalidateReq_mshr_misses::total 268829 # number of InvalidateReq MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11846 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8372 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 607002 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1208119 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.demand_mshr_misses::total 1835339 # number of demand (read+write) MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11846 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8372 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 607002 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1208119 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 722741 # number of overall MSHR misses
< system.cpu1.l2cache.overall_mshr_misses::total 2558080 # number of overall MSHR misses
---
> system.cpu1.l2cache.writebacks::writebacks 898326 # number of writebacks
> system.cpu1.l2cache.writebacks::total 898326 # number of writebacks
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 8 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 163 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_hits::total 171 # number of ReadReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 35372 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadExReq_mshr_hits::total 35372 # number of ReadExReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4249 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4249 # number of ReadSharedReq MSHR hits
> system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 14 # number of InvalidateReq MSHR hits
> system.cpu1.l2cache.InvalidateReq_mshr_hits::total 14 # number of InvalidateReq MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 8 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 163 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::cpu1.data 39621 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.demand_mshr_hits::total 39792 # number of demand (read+write) MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 8 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 163 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::cpu1.data 39621 # number of overall MSHR hits
> system.cpu1.l2cache.overall_mshr_hits::total 39792 # number of overall MSHR hits
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 10510 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7422 # number of ReadReq MSHR misses
> system.cpu1.l2cache.ReadReq_mshr_misses::total 17932 # number of ReadReq MSHR misses
> system.cpu1.l2cache.Writeback_mshr_misses::writebacks 13 # number of Writeback MSHR misses
> system.cpu1.l2cache.Writeback_mshr_misses::total 13 # number of Writeback MSHR misses
> system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 94515 # number of CleanEvict MSHR misses
> system.cpu1.l2cache.CleanEvict_mshr_misses::total 94515 # number of CleanEvict MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 663376 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.HardPFReq_mshr_misses::total 663376 # number of HardPFReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 142287 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.UpgradeReq_mshr_misses::total 142287 # number of UpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 158148 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 158148 # number of SCUpgradeReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 8 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 232940 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadExReq_mshr_misses::total 232940 # number of ReadExReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 560943 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 560943 # number of ReadCleanReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 924870 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 924870 # number of ReadSharedReq MSHR misses
> system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 221519 # number of InvalidateReq MSHR misses
> system.cpu1.l2cache.InvalidateReq_mshr_misses::total 221519 # number of InvalidateReq MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 10510 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7422 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 560943 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1157810 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.demand_mshr_misses::total 1736685 # number of demand (read+write) MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 10510 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7422 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 560943 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1157810 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 663376 # number of overall MSHR misses
> system.cpu1.l2cache.overall_mshr_misses::total 2400061 # number of overall MSHR misses
2804,2807c2801,2804
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6436 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 6503 # number of ReadReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 6853 # number of WriteReq MSHR uncacheable
< system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 6853 # number of WriteReq MSHR uncacheable
---
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6826 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 6893 # number of ReadReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7171 # number of WriteReq MSHR uncacheable
> system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7171 # number of WriteReq MSHR uncacheable
2809,2851c2806,2848
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 13289 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 13356 # number of overall MSHR uncacheable misses
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 375677000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 300105000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 675782000 # number of ReadReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 38256632769 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 38256632769 # number of HardPFReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2790814493 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2790814493 # number of UpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2566482493 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2566482493 # number of SCUpgradeReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4901991 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4901991 # number of SCUpgradeFailReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8739513998 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8739513998 # number of ReadExReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 13678722000 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 13678722000 # number of ReadCleanReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 25793385972 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 25793385972 # number of ReadSharedReq MSHR miss cycles
< system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 15993437499 # number of InvalidateReq MSHR miss cycles
< system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 15993437499 # number of InvalidateReq MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 375677000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 300105000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 13678722000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 34532899970 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.demand_mshr_miss_latency::total 48887403970 # number of demand (read+write) MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 375677000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 300105000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 13678722000 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 34532899970 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 38256632769 # number of overall MSHR miss cycles
< system.cpu1.l2cache.overall_mshr_miss_latency::total 87144036739 # number of overall MSHR miss cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5288500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 658981000 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 664269500 # number of ReadReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 808356000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 808356000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 5288500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1467337000 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1472625500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021134 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.047176 # mshr miss rate for ReadReq accesses
< system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027396 # mshr miss rate for ReadReq accesses
---
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 13997 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14064 # number of overall MSHR uncacheable misses
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 377290500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 262748000 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 640038500 # number of ReadReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 36936048403 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 36936048403 # number of HardPFReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4692578493 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4692578493 # number of UpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2913063996 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2913063996 # number of SCUpgradeReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3975497 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3975497 # number of SCUpgradeFailReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 10641963999 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 10641963999 # number of ReadExReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 16452350500 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 16452350500 # number of ReadCleanReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 28730541987 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 28730541987 # number of ReadSharedReq MSHR miss cycles
> system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 11875773000 # number of InvalidateReq MSHR miss cycles
> system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 11875773000 # number of InvalidateReq MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 377290500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 262748000 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 16452350500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 39372505986 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.demand_mshr_miss_latency::total 56464894986 # number of demand (read+write) MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 377290500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 262748000 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16452350500 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 39372505986 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 36936048403 # number of overall MSHR miss cycles
> system.cpu1.l2cache.overall_mshr_miss_latency::total 93400943389 # number of overall MSHR miss cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8404500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 710244000 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 718648500 # number of ReadReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 860387000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 860387000 # number of WriteReq MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8404500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1570631000 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1579035500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020679 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.042058 # mshr miss rate for ReadReq accesses
> system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.026189 # mshr miss rate for ReadReq accesses
2858,2861c2855,2858
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.664676 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.664676 # mshr miss rate for UpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.831171 # mshr miss rate for SCUpgradeReq accesses
< system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.831171 # mshr miss rate for SCUpgradeReq accesses
---
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.680454 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.680454 # mshr miss rate for UpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.833371 # mshr miss rate for SCUpgradeReq accesses
> system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.833371 # mshr miss rate for SCUpgradeReq accesses
2864,2880c2861,2877
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.211179 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.211179 # mshr miss rate for ReadExReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.110111 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110111 # mshr miss rate for ReadCleanReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.255144 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.255144 # mshr miss rate for ReadSharedReq accesses
< system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.606089 # mshr miss rate for InvalidateReq accesses
< system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.606089 # mshr miss rate for InvalidateReq accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021134 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.047176 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.110111 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245188 # mshr miss rate for demand accesses
< system.cpu1.l2cache.demand_mshr_miss_rate::total 0.164193 # mshr miss rate for demand accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021134 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.047176 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.110111 # mshr miss rate for overall accesses
< system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245188 # mshr miss rate for overall accesses
---
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.219320 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.219320 # mshr miss rate for ReadExReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.101167 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101167 # mshr miss rate for ReadCleanReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.254968 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254968 # mshr miss rate for ReadSharedReq accesses
> system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.537852 # mshr miss rate for InvalidateReq accesses
> system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.537852 # mshr miss rate for InvalidateReq accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020679 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.042058 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.101167 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.246894 # mshr miss rate for demand accesses
> system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159052 # mshr miss rate for demand accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020679 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.042058 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.101167 # mshr miss rate for overall accesses
> system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.246894 # mshr miss rate for overall accesses
2882,2920c2879,2917
< system.cpu1.l2cache.overall_mshr_miss_rate::total 0.228851 # mshr miss rate for overall accesses
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 31713.405369 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35846.273292 # average ReadReq mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 33424.770007 # average ReadReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52932.700330 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 52932.700330 # average HardPFReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20059.330207 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20059.330207 # average UpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15391.014758 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15391.014758 # average SCUpgradeReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 306374.437500 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 306374.437500 # average SCUpgradeFailReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37091.720099 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37091.720099 # average ReadExReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22534.887859 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22534.887859 # average ReadCleanReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26522.761925 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26522.761925 # average ReadSharedReq mshr miss latency
< system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 59492.976944 # average InvalidateReq mshr miss latency
< system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 59492.976944 # average InvalidateReq mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31713.405369 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35846.273292 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22534.887859 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28584.021913 # average overall mshr miss latency
< system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26636.716143 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31713.405369 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35846.273292 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22534.887859 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28584.021913 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52932.700330 # average overall mshr miss latency
< system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34066.188993 # average overall mshr miss latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78932.835821 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 102389.838409 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102148.162387 # average ReadReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117956.515395 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117956.515395 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78932.835821 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 110417.412898 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 110259.471399 # average overall mshr uncacheable latency
---
> system.cpu1.l2cache.overall_mshr_miss_rate::total 0.219807 # mshr miss rate for overall accesses
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 35898.239772 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35401.239558 # average ReadReq mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 35692.532902 # average ReadReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55678.903673 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55678.903673 # average HardPFReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32979.671319 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32979.671319 # average UpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18419.859853 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18419.859853 # average SCUpgradeReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 496937.125000 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 496937.125000 # average SCUpgradeFailReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45685.429720 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45685.429720 # average ReadExReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29329.808020 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29329.808020 # average ReadCleanReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31064.411200 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31064.411200 # average ReadSharedReq mshr miss latency
> system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 53610.629337 # average InvalidateReq mshr miss latency
> system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 53610.629337 # average InvalidateReq mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 35898.239772 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35401.239558 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29329.808020 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34006.016519 # average overall mshr miss latency
> system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32513.032004 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 35898.239772 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35401.239558 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29329.808020 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34006.016519 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55678.903673 # average overall mshr miss latency
> system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 38916.070629 # average overall mshr miss latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125440.298507 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 104049.809552 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 104257.725228 # average ReadReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 119981.453075 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 119981.453075 # average WriteReq mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125440.298507 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 112211.973994 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 112274.992890 # average overall mshr uncacheable latency
2922,2954c2919,2958
< system.cpu1.toL2Bus.trans_dist::ReadReq 950963 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadResp 10318053 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteReq 38676 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::WriteResp 6853 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::Writeback 7301053 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::CleanEvict 10168977 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFReq 922205 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeReq 460948 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 364065 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeResp 477238 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 134 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 247 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExReq 1860044 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadExResp 1122762 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5512640 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::ReadSharedReq 6310959 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateReq 550275 # Transaction distribution
< system.cpu1.toL2Bus.trans_dist::InvalidateResp 443547 # Transaction distribution
< system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16537003 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17033306 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 391276 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1237529 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_count::total 35199114 # Packet count per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 352809840 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 540363378 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1419696 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4484152 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.pkt_size::total 899077066 # Cumulative packet size per connected master and slave (bytes)
< system.cpu1.toL2Bus.snoops 11781593 # Total snoops (count)
< system.cpu1.toL2Bus.snoop_fanout::samples 34442064 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::mean 1.358530 # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::stdev 0.479569 # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_filter.tot_requests 21930537 # Total number of requests made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11284587 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1296 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.snoop_filter.tot_snoops 520648 # Total number of snoops made to the snoop filter.
> system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 520636 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 12 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu1.toL2Bus.trans_dist::ReadReq 828450 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadResp 10092423 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteReq 7171 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::WriteResp 7171 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::Writeback 4200793 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::CleanEvict 9135588 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFReq 838070 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeReq 423377 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 345989 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeResp 462829 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 66 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExReq 1138657 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadExResp 1069017 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5544744 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4688366 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateReq 419379 # Transaction distribution
> system.cpu1.toL2Bus.trans_dist::InvalidateResp 411859 # Transaction distribution
> system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16633313 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16198816 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 385145 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1121131 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_count::total 34338405 # Packet count per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 354864624 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 515112392 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1411752 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4066000 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.pkt_size::total 875454768 # Cumulative packet size per connected master and slave (bytes)
> system.cpu1.toL2Bus.snoops 5438478 # Total snoops (count)
> system.cpu1.toL2Bus.snoop_fanout::samples 27571945 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::mean 0.031057 # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::stdev 0.173474 # Request fanout histogram
2956,2958c2960,2962
< system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::1 22093559 64.15% 64.15% # Request fanout histogram
< system.cpu1.toL2Bus.snoop_fanout::2 12348505 35.85% 100.00% # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::0 26715663 96.89% 96.89% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::1 856270 3.11% 100.00% # Request fanout histogram
> system.cpu1.toL2Bus.snoop_fanout::2 12 0.00% 100.00% # Request fanout histogram
2960c2964
< system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2962,2963c2966,2967
< system.cpu1.toL2Bus.snoop_fanout::total 34442064 # Request fanout histogram
< system.cpu1.toL2Bus.reqLayer0.occupancy 14907193441 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoop_fanout::total 27571945 # Request fanout histogram
> system.cpu1.toL2Bus.reqLayer0.occupancy 14479823475 # Layer occupancy (ticks)
2965c2969
< system.cpu1.toL2Bus.snoopLayer0.occupancy 189176968 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.snoopLayer0.occupancy 180399406 # Layer occupancy (ticks)
2967c2971
< system.cpu1.toL2Bus.respLayer0.occupancy 8273171683 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer0.occupancy 8321735869 # Layer occupancy (ticks)
2969c2973
< system.cpu1.toL2Bus.respLayer1.occupancy 7832975507 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer1.occupancy 7455510168 # Layer occupancy (ticks)
2971c2975
< system.cpu1.toL2Bus.respLayer2.occupancy 214052518 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer2.occupancy 208987874 # Layer occupancy (ticks)
2973c2977
< system.cpu1.toL2Bus.respLayer3.occupancy 677527956 # Layer occupancy (ticks)
---
> system.cpu1.toL2Bus.respLayer3.occupancy 613445865 # Layer occupancy (ticks)
2975,2979c2979,2983
< system.iobus.trans_dist::ReadReq 40376 # Transaction distribution
< system.iobus.trans_dist::ReadResp 40376 # Transaction distribution
< system.iobus.trans_dist::WriteReq 136648 # Transaction distribution
< system.iobus.trans_dist::WriteResp 136648 # Transaction distribution
< system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47800 # Packet count per connected master and slave (bytes)
---
> system.iobus.trans_dist::ReadReq 40368 # Transaction distribution
> system.iobus.trans_dist::ReadResp 40368 # Transaction distribution
> system.iobus.trans_dist::WriteReq 136681 # Transaction distribution
> system.iobus.trans_dist::WriteResp 136681 # Transaction distribution
> system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47892 # Packet count per connected master and slave (bytes)
2989c2993
< system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
2994,2996c2998,3000
< system.iobus.pkt_count_system.bridge.master::total 122682 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231286 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.realview.ide.dma::total 231286 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.bridge.master::total 122826 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231192 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.realview.ide.dma::total 231192 # Packet count per connected master and slave (bytes)
2999,3000c3003,3004
< system.iobus.pkt_count::total 354048 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47820 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 354098 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47912 # Cumulative packet size per connected master and slave (bytes)
3010c3014
< system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
3015,3017c3019,3021
< system.iobus.pkt_size_system.bridge.master::total 155812 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339160 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.realview.ide.dma::total 7339160 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.bridge.master::total 155933 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338784 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.realview.ide.dma::total 7338784 # Cumulative packet size per connected master and slave (bytes)
3020,3021c3024,3025
< system.iobus.pkt_size::total 7497058 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.reqLayer0.occupancy 36303000 # Layer occupancy (ticks)
---
> system.iobus.pkt_size::total 7496803 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.reqLayer0.occupancy 36369000 # Layer occupancy (ticks)
3041c3045
< system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
---
> system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks)
3049c3053
< system.iobus.reqLayer27.occupancy 569813871 # Layer occupancy (ticks)
---
> system.iobus.reqLayer27.occupancy 565777885 # Layer occupancy (ticks)
3053c3057
< system.iobus.respLayer0.occupancy 92765000 # Layer occupancy (ticks)
---
> system.iobus.respLayer0.occupancy 92876000 # Layer occupancy (ticks)
3055c3059
< system.iobus.respLayer3.occupancy 147982000 # Layer occupancy (ticks)
---
> system.iobus.respLayer3.occupancy 147888000 # Layer occupancy (ticks)
3059,3060c3063,3064
< system.iocache.tags.replacements 115623 # number of replacements
< system.iocache.tags.tagsinuse 11.307008 # Cycle average of tags in use
---
> system.iocache.tags.replacements 115577 # number of replacements
> system.iocache.tags.tagsinuse 11.305567 # Cycle average of tags in use
3062c3066
< system.iocache.tags.sampled_refs 115639 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 115593 # Sample count of references to valid blocks.
3064,3069c3068,3073
< system.iocache.tags.warmup_cycle 9081350424000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::realview.ethernet 3.848834 # Average occupied blocks per requestor
< system.iocache.tags.occ_blocks::realview.ide 7.458174 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::realview.ethernet 0.240552 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::realview.ide 0.466136 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.706688 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 9126912991000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::realview.ethernet 3.834509 # Average occupied blocks per requestor
> system.iocache.tags.occ_blocks::realview.ide 7.471058 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::realview.ethernet 0.239657 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::realview.ide 0.466941 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.706598 # Average percentage of cache occupancy
3073,3074c3077,3078
< system.iocache.tags.tag_accesses 1041144 # Number of tag accesses
< system.iocache.tags.data_accesses 1041144 # Number of data accesses
---
> system.iocache.tags.tag_accesses 1040721 # Number of tag accesses
> system.iocache.tags.data_accesses 1040721 # Number of data accesses
3076,3077c3080,3081
< system.iocache.ReadReq_misses::realview.ide 8915 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 8952 # number of ReadReq misses
---
> system.iocache.ReadReq_misses::realview.ide 8868 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 8905 # number of ReadReq misses
3083,3084c3087,3088
< system.iocache.demand_misses::realview.ide 8915 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8955 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 8868 # number of demand (read+write) misses
> system.iocache.demand_misses::total 8908 # number of demand (read+write) misses
3086,3087c3090,3091
< system.iocache.overall_misses::realview.ide 8915 # number of overall misses
< system.iocache.overall_misses::total 8955 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 8868 # number of overall misses
> system.iocache.overall_misses::total 8908 # number of overall misses
3089,3090c3093,3094
< system.iocache.ReadReq_miss_latency::realview.ide 1625113033 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 1630308033 # number of ReadReq miss cycles
---
> system.iocache.ReadReq_miss_latency::realview.ide 1707562057 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 1712757057 # number of ReadReq miss cycles
3093,3094c3097,3098
< system.iocache.WriteLineReq_miss_latency::realview.ide 12635282838 # number of WriteLineReq miss cycles
< system.iocache.WriteLineReq_miss_latency::total 12635282838 # number of WriteLineReq miss cycles
---
> system.iocache.WriteLineReq_miss_latency::realview.ide 13922427828 # number of WriteLineReq miss cycles
> system.iocache.WriteLineReq_miss_latency::total 13922427828 # number of WriteLineReq miss cycles
3096,3097c3100,3101
< system.iocache.demand_miss_latency::realview.ide 1625113033 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1630677033 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 1707562057 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 1713126057 # number of demand (read+write) miss cycles
3099,3100c3103,3104
< system.iocache.overall_miss_latency::realview.ide 1625113033 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1630677033 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 1707562057 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 1713126057 # number of overall miss cycles
3102,3103c3106,3107
< system.iocache.ReadReq_accesses::realview.ide 8915 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 8952 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_accesses::realview.ide 8868 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 8905 # number of ReadReq accesses(hits+misses)
3109,3110c3113,3114
< system.iocache.demand_accesses::realview.ide 8915 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8955 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 8868 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 8908 # number of demand (read+write) accesses
3112,3113c3116,3117
< system.iocache.overall_accesses::realview.ide 8915 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8955 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 8868 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 8908 # number of overall (read+write) accesses
3128,3129c3132,3133
< system.iocache.ReadReq_avg_miss_latency::realview.ide 182289.740101 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 182116.625670 # average ReadReq miss latency
---
> system.iocache.ReadReq_avg_miss_latency::realview.ide 192553.231507 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 192336.558899 # average ReadReq miss latency
3132,3133c3136,3137
< system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118387.703677 # average WriteLineReq miss latency
< system.iocache.WriteLineReq_avg_miss_latency::total 118387.703677 # average WriteLineReq miss latency
---
> system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130447.753429 # average WriteLineReq miss latency
> system.iocache.WriteLineReq_avg_miss_latency::total 130447.753429 # average WriteLineReq miss latency
3135,3136c3139,3140
< system.iocache.demand_avg_miss_latency::realview.ide 182289.740101 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 182096.821106 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 192553.231507 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 192313.208015 # average overall miss latency
3138,3140c3142,3144
< system.iocache.overall_avg_miss_latency::realview.ide 182289.740101 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 182096.821106 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 30957 # number of cycles access was blocked
---
> system.iocache.overall_avg_miss_latency::realview.ide 192553.231507 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 192313.208015 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 35527 # number of cycles access was blocked
3142c3146
< system.iocache.blocked::no_mshrs 3475 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 3511 # number of cycles access was blocked
3144c3148
< system.iocache.avg_blocked_cycles::no_mshrs 8.908489 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 10.118770 # average number of cycles each access was blocked
3148,3149c3152,3153
< system.iocache.writebacks::writebacks 106693 # number of writebacks
< system.iocache.writebacks::total 106693 # number of writebacks
---
> system.iocache.writebacks::writebacks 106694 # number of writebacks
> system.iocache.writebacks::total 106694 # number of writebacks
3151,3152c3155,3156
< system.iocache.ReadReq_mshr_misses::realview.ide 8915 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 8952 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::realview.ide 8868 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 8905 # number of ReadReq MSHR misses
3158,3159c3162,3163
< system.iocache.demand_mshr_misses::realview.ide 8915 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8955 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 8868 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 8908 # number of demand (read+write) MSHR misses
3161,3162c3165,3166
< system.iocache.overall_mshr_misses::realview.ide 8915 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8955 # number of overall MSHR misses
---
> system.iocache.overall_mshr_misses::realview.ide 8868 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 8908 # number of overall MSHR misses
3164,3165c3168,3169
< system.iocache.ReadReq_mshr_miss_latency::realview.ide 1179363033 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 1182708033 # number of ReadReq MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::realview.ide 1264162057 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 1267507057 # number of ReadReq MSHR miss cycles
3168,3169c3172,3173
< system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7298882838 # number of WriteLineReq MSHR miss cycles
< system.iocache.WriteLineReq_mshr_miss_latency::total 7298882838 # number of WriteLineReq MSHR miss cycles
---
> system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8586027828 # number of WriteLineReq MSHR miss cycles
> system.iocache.WriteLineReq_mshr_miss_latency::total 8586027828 # number of WriteLineReq MSHR miss cycles
3171,3172c3175,3176
< system.iocache.demand_mshr_miss_latency::realview.ide 1179363033 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1182927033 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 1264162057 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 1267726057 # number of demand (read+write) MSHR miss cycles
3174,3175c3178,3179
< system.iocache.overall_mshr_miss_latency::realview.ide 1179363033 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1182927033 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 1264162057 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 1267726057 # number of overall MSHR miss cycles
3190,3191c3194,3195
< system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132289.740101 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 132116.625670 # average ReadReq mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142553.231507 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 142336.558899 # average ReadReq mshr miss latency
3194,3195c3198,3199
< system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68387.703677 # average WriteLineReq mshr miss latency
< system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68387.703677 # average WriteLineReq mshr miss latency
---
> system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80447.753429 # average WriteLineReq mshr miss latency
> system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80447.753429 # average WriteLineReq mshr miss latency
3197,3198c3201,3202
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 132289.740101 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 132096.821106 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 142553.231507 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 142313.208015 # average overall mshr miss latency
3200,3201c3204,3205
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 132289.740101 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 132096.821106 # average overall mshr miss latency
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 142553.231507 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 142313.208015 # average overall mshr miss latency
3203,3207c3207,3211
< system.l2c.tags.replacements 1604376 # number of replacements
< system.l2c.tags.tagsinuse 63973.571253 # Cycle average of tags in use
< system.l2c.tags.total_refs 5805157 # Total number of references to valid blocks.
< system.l2c.tags.sampled_refs 1664778 # Sample count of references to valid blocks.
< system.l2c.tags.avg_refs 3.487046 # Average number of references to valid blocks.
---
> system.l2c.tags.replacements 1523284 # number of replacements
> system.l2c.tags.tagsinuse 63784.617798 # Cycle average of tags in use
> system.l2c.tags.total_refs 5785768 # Total number of references to valid blocks.
> system.l2c.tags.sampled_refs 1584080 # Sample count of references to valid blocks.
> system.l2c.tags.avg_refs 3.652447 # Average number of references to valid blocks.
3209,3235c3213,3239
< system.l2c.tags.occ_blocks::writebacks 16659.203027 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.dtb.walker 347.238411 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.itb.walker 480.079854 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.inst 4726.149973 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.data 13722.940289 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 19518.694683 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.dtb.walker 39.930664 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.itb.walker 37.878689 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.inst 2515.843694 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.data 3528.824222 # Average occupied blocks per requestor
< system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2396.787747 # Average occupied blocks per requestor
< system.l2c.tags.occ_percent::writebacks 0.254199 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.dtb.walker 0.005298 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.itb.walker 0.007325 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.inst 0.072115 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.data 0.209395 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.297832 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000609 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.itb.walker 0.000578 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.inst 0.038389 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.data 0.053846 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.036572 # Average percentage of cache occupancy
< system.l2c.tags.occ_percent::total 0.976159 # Average percentage of cache occupancy
< system.l2c.tags.occ_task_id_blocks::1022 10879 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1023 220 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_blocks::1024 49303 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id
---
> system.l2c.tags.occ_blocks::writebacks 17262.204967 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.dtb.walker 288.051541 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.itb.walker 383.464514 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.inst 4972.263689 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.data 12806.585942 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 17387.012671 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.dtb.walker 85.287470 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.itb.walker 93.857044 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.inst 2455.379438 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.data 4782.512624 # Average occupied blocks per requestor
> system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3267.997898 # Average occupied blocks per requestor
> system.l2c.tags.occ_percent::writebacks 0.263400 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004395 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.itb.walker 0.005851 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.inst 0.075871 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.data 0.195413 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.265305 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001301 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.itb.walker 0.001432 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.inst 0.037466 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.data 0.072975 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.049866 # Average percentage of cache occupancy
> system.l2c.tags.occ_percent::total 0.973276 # Average percentage of cache occupancy
> system.l2c.tags.occ_task_id_blocks::1022 10918 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1023 244 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_blocks::1024 49634 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
3237,3508c3241,3513
< system.l2c.tags.age_task_id_blocks_1022::2 1360 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::3 633 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1022::4 8884 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1023::4 213 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::2 2421 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::3 4883 # Occupied blocks per task id
< system.l2c.tags.age_task_id_blocks_1024::4 41670 # Occupied blocks per task id
< system.l2c.tags.occ_task_id_percent::1022 0.166000 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id
< system.l2c.tags.occ_task_id_percent::1024 0.752304 # Percentage of cache occupancy per task id
< system.l2c.tags.tag_accesses 72712060 # Number of tag accesses
< system.l2c.tags.data_accesses 72712060 # Number of data accesses
< system.l2c.Writeback_hits::writebacks 2536205 # number of Writeback hits
< system.l2c.Writeback_hits::total 2536205 # number of Writeback hits
< system.l2c.UpgradeReq_hits::cpu0.data 30090 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::cpu1.data 27013 # number of UpgradeReq hits
< system.l2c.UpgradeReq_hits::total 57103 # number of UpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu0.data 6458 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::cpu1.data 6165 # number of SCUpgradeReq hits
< system.l2c.SCUpgradeReq_hits::total 12623 # number of SCUpgradeReq hits
< system.l2c.ReadExReq_hits::cpu0.data 162036 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::cpu1.data 153866 # number of ReadExReq hits
< system.l2c.ReadExReq_hits::total 315902 # number of ReadExReq hits
< system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6626 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4489 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.inst 594958 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.data 614676 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 296621 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6612 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4192 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.inst 566970 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.data 555261 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 284702 # number of ReadSharedReq hits
< system.l2c.ReadSharedReq_hits::total 2935107 # number of ReadSharedReq hits
< system.l2c.demand_hits::cpu0.dtb.walker 6626 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.itb.walker 4489 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.inst 594958 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.data 776712 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu0.l2cache.prefetcher 296621 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.dtb.walker 6612 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.itb.walker 4192 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.inst 566970 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.data 709127 # number of demand (read+write) hits
< system.l2c.demand_hits::cpu1.l2cache.prefetcher 284702 # number of demand (read+write) hits
< system.l2c.demand_hits::total 3251009 # number of demand (read+write) hits
< system.l2c.overall_hits::cpu0.dtb.walker 6626 # number of overall hits
< system.l2c.overall_hits::cpu0.itb.walker 4489 # number of overall hits
< system.l2c.overall_hits::cpu0.inst 594958 # number of overall hits
< system.l2c.overall_hits::cpu0.data 776712 # number of overall hits
< system.l2c.overall_hits::cpu0.l2cache.prefetcher 296621 # number of overall hits
< system.l2c.overall_hits::cpu1.dtb.walker 6612 # number of overall hits
< system.l2c.overall_hits::cpu1.itb.walker 4192 # number of overall hits
< system.l2c.overall_hits::cpu1.inst 566970 # number of overall hits
< system.l2c.overall_hits::cpu1.data 709127 # number of overall hits
< system.l2c.overall_hits::cpu1.l2cache.prefetcher 284702 # number of overall hits
< system.l2c.overall_hits::total 3251009 # number of overall hits
< system.l2c.UpgradeReq_misses::cpu0.data 47588 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::cpu1.data 43593 # number of UpgradeReq misses
< system.l2c.UpgradeReq_misses::total 91181 # number of UpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu0.data 9906 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::cpu1.data 10331 # number of SCUpgradeReq misses
< system.l2c.SCUpgradeReq_misses::total 20237 # number of SCUpgradeReq misses
< system.l2c.ReadExReq_misses::cpu0.data 509249 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::cpu1.data 164886 # number of ReadExReq misses
< system.l2c.ReadExReq_misses::total 674135 # number of ReadExReq misses
< system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2732 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2383 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.inst 65927 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.data 171520 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 297602 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2128 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1988 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.inst 40032 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.data 112082 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 243379 # number of ReadSharedReq misses
< system.l2c.ReadSharedReq_misses::total 939773 # number of ReadSharedReq misses
< system.l2c.demand_misses::cpu0.dtb.walker 2732 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.itb.walker 2383 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.inst 65927 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.data 680769 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu0.l2cache.prefetcher 297602 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.dtb.walker 2128 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.itb.walker 1988 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.inst 40032 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.data 276968 # number of demand (read+write) misses
< system.l2c.demand_misses::cpu1.l2cache.prefetcher 243379 # number of demand (read+write) misses
< system.l2c.demand_misses::total 1613908 # number of demand (read+write) misses
< system.l2c.overall_misses::cpu0.dtb.walker 2732 # number of overall misses
< system.l2c.overall_misses::cpu0.itb.walker 2383 # number of overall misses
< system.l2c.overall_misses::cpu0.inst 65927 # number of overall misses
< system.l2c.overall_misses::cpu0.data 680769 # number of overall misses
< system.l2c.overall_misses::cpu0.l2cache.prefetcher 297602 # number of overall misses
< system.l2c.overall_misses::cpu1.dtb.walker 2128 # number of overall misses
< system.l2c.overall_misses::cpu1.itb.walker 1988 # number of overall misses
< system.l2c.overall_misses::cpu1.inst 40032 # number of overall misses
< system.l2c.overall_misses::cpu1.data 276968 # number of overall misses
< system.l2c.overall_misses::cpu1.l2cache.prefetcher 243379 # number of overall misses
< system.l2c.overall_misses::total 1613908 # number of overall misses
< system.l2c.UpgradeReq_miss_latency::cpu0.data 285345500 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::cpu1.data 229148000 # number of UpgradeReq miss cycles
< system.l2c.UpgradeReq_miss_latency::total 514493500 # number of UpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu0.data 53588000 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::cpu1.data 57099500 # number of SCUpgradeReq miss cycles
< system.l2c.SCUpgradeReq_miss_latency::total 110687500 # number of SCUpgradeReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu0.data 66726621996 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::cpu1.data 17979484499 # number of ReadExReq miss cycles
< system.l2c.ReadExReq_miss_latency::total 84706106495 # number of ReadExReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 253095500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 219982000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5658543002 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.data 16552075998 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 41040485814 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 202746500 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 183043000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3466352000 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.data 10969692499 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 33324994201 # number of ReadSharedReq miss cycles
< system.l2c.ReadSharedReq_miss_latency::total 111871010514 # number of ReadSharedReq miss cycles
< system.l2c.demand_miss_latency::cpu0.dtb.walker 253095500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.itb.walker 219982000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.inst 5658543002 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.data 83278697994 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 41040485814 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.dtb.walker 202746500 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.itb.walker 183043000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.inst 3466352000 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.data 28949176998 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 33324994201 # number of demand (read+write) miss cycles
< system.l2c.demand_miss_latency::total 196577117009 # number of demand (read+write) miss cycles
< system.l2c.overall_miss_latency::cpu0.dtb.walker 253095500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.itb.walker 219982000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.inst 5658543002 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.data 83278697994 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 41040485814 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.dtb.walker 202746500 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.itb.walker 183043000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.inst 3466352000 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.data 28949176998 # number of overall miss cycles
< system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 33324994201 # number of overall miss cycles
< system.l2c.overall_miss_latency::total 196577117009 # number of overall miss cycles
< system.l2c.Writeback_accesses::writebacks 2536205 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 2536205 # number of Writeback accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu0.data 77678 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::cpu1.data 70606 # number of UpgradeReq accesses(hits+misses)
< system.l2c.UpgradeReq_accesses::total 148284 # number of UpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu0.data 16364 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::cpu1.data 16496 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.SCUpgradeReq_accesses::total 32860 # number of SCUpgradeReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu0.data 671285 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::cpu1.data 318752 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadExReq_accesses::total 990037 # number of ReadExReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 9358 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6872 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.inst 660885 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.data 786196 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 594223 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8740 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6180 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.inst 607002 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.data 667343 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 528081 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.ReadSharedReq_accesses::total 3874880 # number of ReadSharedReq accesses(hits+misses)
< system.l2c.demand_accesses::cpu0.dtb.walker 9358 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.itb.walker 6872 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.inst 660885 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.data 1457481 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu0.l2cache.prefetcher 594223 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.dtb.walker 8740 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.itb.walker 6180 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.inst 607002 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.data 986095 # number of demand (read+write) accesses
< system.l2c.demand_accesses::cpu1.l2cache.prefetcher 528081 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 4864917 # number of demand (read+write) accesses
< system.l2c.overall_accesses::cpu0.dtb.walker 9358 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.itb.walker 6872 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.inst 660885 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.data 1457481 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu0.l2cache.prefetcher 594223 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.dtb.walker 8740 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.itb.walker 6180 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.inst 607002 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.data 986095 # number of overall (read+write) accesses
< system.l2c.overall_accesses::cpu1.l2cache.prefetcher 528081 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 4864917 # number of overall (read+write) accesses
< system.l2c.UpgradeReq_miss_rate::cpu0.data 0.612632 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::cpu1.data 0.617412 # miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_miss_rate::total 0.614908 # miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.605353 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.626273 # miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_miss_rate::total 0.615855 # miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_miss_rate::cpu0.data 0.758618 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::cpu1.data 0.517286 # miss rate for ReadExReq accesses
< system.l2c.ReadExReq_miss_rate::total 0.680919 # miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.291943 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.346769 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.099756 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.218164 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.500825 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.243478 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.321683 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.065950 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.167953 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.460874 # miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_miss_rate::total 0.242530 # miss rate for ReadSharedReq accesses
< system.l2c.demand_miss_rate::cpu0.dtb.walker 0.291943 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.itb.walker 0.346769 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.inst 0.099756 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.data 0.467086 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.500825 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.dtb.walker 0.243478 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.itb.walker 0.321683 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.inst 0.065950 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.data 0.280874 # miss rate for demand accesses
< system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.460874 # miss rate for demand accesses
< system.l2c.demand_miss_rate::total 0.331744 # miss rate for demand accesses
< system.l2c.overall_miss_rate::cpu0.dtb.walker 0.291943 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.itb.walker 0.346769 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.inst 0.099756 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.data 0.467086 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.500825 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.dtb.walker 0.243478 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.itb.walker 0.321683 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.inst 0.065950 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.data 0.280874 # miss rate for overall accesses
< system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.460874 # miss rate for overall accesses
< system.l2c.overall_miss_rate::total 0.331744 # miss rate for overall accesses
< system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5996.165000 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5256.532012 # average UpgradeReq miss latency
< system.l2c.UpgradeReq_avg_miss_latency::total 5642.551628 # average UpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5409.650717 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5527.006098 # average SCUpgradeReq miss latency
< system.l2c.SCUpgradeReq_avg_miss_latency::total 5469.560706 # average SCUpgradeReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu0.data 131029.461022 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109041.910769 # average ReadExReq miss latency
< system.l2c.ReadExReq_avg_miss_latency::total 125651.548273 # average ReadExReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 92641.105417 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 92313.050776 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 85830.433692 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 96502.308757 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 137903.931472 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 95275.610902 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 92073.943662 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86589.528377 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 97872.026722 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 136926.333829 # average ReadSharedReq miss latency
< system.l2c.ReadSharedReq_avg_miss_latency::total 119040.460318 # average ReadSharedReq miss latency
< system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 92641.105417 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.itb.walker 92313.050776 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.inst 85830.433692 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.data 122330.332307 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 137903.931472 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 95275.610902 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.itb.walker 92073.943662 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.inst 86589.528377 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.data 104521.738966 # average overall miss latency
< system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 136926.333829 # average overall miss latency
< system.l2c.demand_avg_miss_latency::total 121801.934812 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 92641.105417 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.itb.walker 92313.050776 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.inst 85830.433692 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.data 122330.332307 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 137903.931472 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 95275.610902 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.itb.walker 92073.943662 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.inst 86589.528377 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.data 104521.738966 # average overall miss latency
< system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 136926.333829 # average overall miss latency
< system.l2c.overall_avg_miss_latency::total 121801.934812 # average overall miss latency
< system.l2c.blocked_cycles::no_mshrs 7662 # number of cycles access was blocked
---
> system.l2c.tags.age_task_id_blocks_1022::2 1058 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::3 384 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1022::4 9467 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1023::4 241 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::2 2538 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::3 5035 # Occupied blocks per task id
> system.l2c.tags.age_task_id_blocks_1024::4 41740 # Occupied blocks per task id
> system.l2c.tags.occ_task_id_percent::1022 0.166595 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id
> system.l2c.tags.occ_task_id_percent::1024 0.757355 # Percentage of cache occupancy per task id
> system.l2c.tags.tag_accesses 71725289 # Number of tag accesses
> system.l2c.tags.data_accesses 71725289 # Number of data accesses
> system.l2c.Writeback_hits::writebacks 2493194 # number of Writeback hits
> system.l2c.Writeback_hits::total 2493194 # number of Writeback hits
> system.l2c.UpgradeReq_hits::cpu0.data 29135 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::cpu1.data 32441 # number of UpgradeReq hits
> system.l2c.UpgradeReq_hits::total 61576 # number of UpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu0.data 6380 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::cpu1.data 5628 # number of SCUpgradeReq hits
> system.l2c.SCUpgradeReq_hits::total 12008 # number of SCUpgradeReq hits
> system.l2c.ReadExReq_hits::cpu0.data 165668 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::cpu1.data 160581 # number of ReadExReq hits
> system.l2c.ReadExReq_hits::total 326249 # number of ReadExReq hits
> system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6589 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4357 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.inst 618480 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.data 631164 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 297252 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5967 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4162 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.inst 524459 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.data 533369 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 294077 # number of ReadSharedReq hits
> system.l2c.ReadSharedReq_hits::total 2919876 # number of ReadSharedReq hits
> system.l2c.demand_hits::cpu0.dtb.walker 6589 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.itb.walker 4357 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.inst 618480 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.data 796832 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu0.l2cache.prefetcher 297252 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.dtb.walker 5967 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.itb.walker 4162 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.inst 524459 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.data 693950 # number of demand (read+write) hits
> system.l2c.demand_hits::cpu1.l2cache.prefetcher 294077 # number of demand (read+write) hits
> system.l2c.demand_hits::total 3246125 # number of demand (read+write) hits
> system.l2c.overall_hits::cpu0.dtb.walker 6589 # number of overall hits
> system.l2c.overall_hits::cpu0.itb.walker 4357 # number of overall hits
> system.l2c.overall_hits::cpu0.inst 618480 # number of overall hits
> system.l2c.overall_hits::cpu0.data 796832 # number of overall hits
> system.l2c.overall_hits::cpu0.l2cache.prefetcher 297252 # number of overall hits
> system.l2c.overall_hits::cpu1.dtb.walker 5967 # number of overall hits
> system.l2c.overall_hits::cpu1.itb.walker 4162 # number of overall hits
> system.l2c.overall_hits::cpu1.inst 524459 # number of overall hits
> system.l2c.overall_hits::cpu1.data 693950 # number of overall hits
> system.l2c.overall_hits::cpu1.l2cache.prefetcher 294077 # number of overall hits
> system.l2c.overall_hits::total 3246125 # number of overall hits
> system.l2c.UpgradeReq_misses::cpu0.data 49689 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::cpu1.data 45204 # number of UpgradeReq misses
> system.l2c.UpgradeReq_misses::total 94893 # number of UpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu0.data 10659 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::cpu1.data 8662 # number of SCUpgradeReq misses
> system.l2c.SCUpgradeReq_misses::total 19321 # number of SCUpgradeReq misses
> system.l2c.ReadExReq_misses::cpu0.data 547046 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::cpu1.data 101994 # number of ReadExReq misses
> system.l2c.ReadExReq_misses::total 649040 # number of ReadExReq misses
> system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3253 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3182 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.inst 67580 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.data 173763 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 345323 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1427 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1037 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.inst 36484 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.data 93466 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 171017 # number of ReadSharedReq misses
> system.l2c.ReadSharedReq_misses::total 896532 # number of ReadSharedReq misses
> system.l2c.demand_misses::cpu0.dtb.walker 3253 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.itb.walker 3182 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.inst 67580 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.data 720809 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu0.l2cache.prefetcher 345323 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.dtb.walker 1427 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.itb.walker 1037 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.inst 36484 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.data 195460 # number of demand (read+write) misses
> system.l2c.demand_misses::cpu1.l2cache.prefetcher 171017 # number of demand (read+write) misses
> system.l2c.demand_misses::total 1545572 # number of demand (read+write) misses
> system.l2c.overall_misses::cpu0.dtb.walker 3253 # number of overall misses
> system.l2c.overall_misses::cpu0.itb.walker 3182 # number of overall misses
> system.l2c.overall_misses::cpu0.inst 67580 # number of overall misses
> system.l2c.overall_misses::cpu0.data 720809 # number of overall misses
> system.l2c.overall_misses::cpu0.l2cache.prefetcher 345323 # number of overall misses
> system.l2c.overall_misses::cpu1.dtb.walker 1427 # number of overall misses
> system.l2c.overall_misses::cpu1.itb.walker 1037 # number of overall misses
> system.l2c.overall_misses::cpu1.inst 36484 # number of overall misses
> system.l2c.overall_misses::cpu1.data 195460 # number of overall misses
> system.l2c.overall_misses::cpu1.l2cache.prefetcher 171017 # number of overall misses
> system.l2c.overall_misses::total 1545572 # number of overall misses
> system.l2c.UpgradeReq_miss_latency::cpu0.data 823665000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::cpu1.data 712158000 # number of UpgradeReq miss cycles
> system.l2c.UpgradeReq_miss_latency::total 1535823000 # number of UpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu0.data 169857000 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::cpu1.data 128692500 # number of SCUpgradeReq miss cycles
> system.l2c.SCUpgradeReq_miss_latency::total 298549500 # number of SCUpgradeReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu0.data 97772317996 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::cpu1.data 15251359498 # number of ReadExReq miss cycles
> system.l2c.ReadExReq_miss_latency::total 113023677494 # number of ReadExReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 459886500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 447245500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.inst 9268037502 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.data 25632017498 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 63422033653 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 210125000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 151697000 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5011265500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.data 13524553500 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 31614845146 # number of ReadSharedReq miss cycles
> system.l2c.ReadSharedReq_miss_latency::total 149741706799 # number of ReadSharedReq miss cycles
> system.l2c.demand_miss_latency::cpu0.dtb.walker 459886500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.itb.walker 447245500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.inst 9268037502 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.data 123404335494 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 63422033653 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.dtb.walker 210125000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.itb.walker 151697000 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.inst 5011265500 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.data 28775912998 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 31614845146 # number of demand (read+write) miss cycles
> system.l2c.demand_miss_latency::total 262765384293 # number of demand (read+write) miss cycles
> system.l2c.overall_miss_latency::cpu0.dtb.walker 459886500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.itb.walker 447245500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.inst 9268037502 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.data 123404335494 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 63422033653 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.dtb.walker 210125000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.itb.walker 151697000 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.inst 5011265500 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.data 28775912998 # number of overall miss cycles
> system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 31614845146 # number of overall miss cycles
> system.l2c.overall_miss_latency::total 262765384293 # number of overall miss cycles
> system.l2c.Writeback_accesses::writebacks 2493194 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 2493194 # number of Writeback accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu0.data 78824 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::cpu1.data 77645 # number of UpgradeReq accesses(hits+misses)
> system.l2c.UpgradeReq_accesses::total 156469 # number of UpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu0.data 17039 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::cpu1.data 14290 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.SCUpgradeReq_accesses::total 31329 # number of SCUpgradeReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu0.data 712714 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::cpu1.data 262575 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadExReq_accesses::total 975289 # number of ReadExReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 9842 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7539 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.inst 686060 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.data 804927 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 642575 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 7394 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5199 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.inst 560943 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.data 626835 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 465094 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.ReadSharedReq_accesses::total 3816408 # number of ReadSharedReq accesses(hits+misses)
> system.l2c.demand_accesses::cpu0.dtb.walker 9842 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.itb.walker 7539 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.inst 686060 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.data 1517641 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu0.l2cache.prefetcher 642575 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.dtb.walker 7394 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.itb.walker 5199 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.inst 560943 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.data 889410 # number of demand (read+write) accesses
> system.l2c.demand_accesses::cpu1.l2cache.prefetcher 465094 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 4791697 # number of demand (read+write) accesses
> system.l2c.overall_accesses::cpu0.dtb.walker 9842 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.itb.walker 7539 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.inst 686060 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.data 1517641 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu0.l2cache.prefetcher 642575 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.dtb.walker 7394 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.itb.walker 5199 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.inst 560943 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.data 889410 # number of overall (read+write) accesses
> system.l2c.overall_accesses::cpu1.l2cache.prefetcher 465094 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 4791697 # number of overall (read+write) accesses
> system.l2c.UpgradeReq_miss_rate::cpu0.data 0.630379 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::cpu1.data 0.582188 # miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_miss_rate::total 0.606465 # miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.625565 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.606158 # miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_miss_rate::total 0.616713 # miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_miss_rate::cpu0.data 0.767553 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::cpu1.data 0.388438 # miss rate for ReadExReq accesses
> system.l2c.ReadExReq_miss_rate::total 0.665485 # miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.330522 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.422072 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.098505 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.215874 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.537405 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.192994 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.199461 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.065040 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.149108 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.367704 # miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_miss_rate::total 0.234915 # miss rate for ReadSharedReq accesses
> system.l2c.demand_miss_rate::cpu0.dtb.walker 0.330522 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.itb.walker 0.422072 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.inst 0.098505 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.data 0.474954 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.537405 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.dtb.walker 0.192994 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.itb.walker 0.199461 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.inst 0.065040 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.data 0.219764 # miss rate for demand accesses
> system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.367704 # miss rate for demand accesses
> system.l2c.demand_miss_rate::total 0.322552 # miss rate for demand accesses
> system.l2c.overall_miss_rate::cpu0.dtb.walker 0.330522 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.itb.walker 0.422072 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.inst 0.098505 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.data 0.474954 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.537405 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.dtb.walker 0.192994 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.itb.walker 0.199461 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.inst 0.065040 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.data 0.219764 # miss rate for overall accesses
> system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.367704 # miss rate for overall accesses
> system.l2c.overall_miss_rate::total 0.322552 # miss rate for overall accesses
> system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16576.405241 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15754.313778 # average UpgradeReq miss latency
> system.l2c.UpgradeReq_avg_miss_latency::total 16184.787076 # average UpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15935.547425 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 14857.134611 # average SCUpgradeReq miss latency
> system.l2c.SCUpgradeReq_avg_miss_latency::total 15452.072874 # average SCUpgradeReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu0.data 178727.781569 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::cpu1.data 149531.928329 # average ReadExReq miss latency
> system.l2c.ReadExReq_avg_miss_latency::total 174139.771808 # average ReadExReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 141373.040271 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 140554.839723 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 137141.720953 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 147511.366045 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 183660.033224 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 147249.474422 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 146284.474446 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137355.155685 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 144700.249289 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 184863.757088 # average ReadSharedReq miss latency
> system.l2c.ReadSharedReq_avg_miss_latency::total 167023.270557 # average ReadSharedReq miss latency
> system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 141373.040271 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.itb.walker 140554.839723 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.inst 137141.720953 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.data 171202.545326 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 183660.033224 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 147249.474422 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.itb.walker 146284.474446 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.inst 137355.155685 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.data 147221.492878 # average overall miss latency
> system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 184863.757088 # average overall miss latency
> system.l2c.demand_avg_miss_latency::total 170011.739533 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 141373.040271 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.itb.walker 140554.839723 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.inst 137141.720953 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.data 171202.545326 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 183660.033224 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 147249.474422 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.itb.walker 146284.474446 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.inst 137355.155685 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.data 147221.492878 # average overall miss latency
> system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 184863.757088 # average overall miss latency
> system.l2c.overall_avg_miss_latency::total 170011.739533 # average overall miss latency
> system.l2c.blocked_cycles::no_mshrs 10627 # number of cycles access was blocked
3510c3515
< system.l2c.blocked::no_mshrs 92 # number of cycles access was blocked
---
> system.l2c.blocked::no_mshrs 95 # number of cycles access was blocked
3512c3517
< system.l2c.avg_blocked_cycles::no_mshrs 83.282609 # average number of cycles each access was blocked
---
> system.l2c.avg_blocked_cycles::no_mshrs 111.863158 # average number of cycles each access was blocked
3516,3584c3521,3581
< system.l2c.writebacks::writebacks 1246552 # number of writebacks
< system.l2c.writebacks::total 1246552 # number of writebacks
< system.l2c.ReadExReq_mshr_hits::cpu0.data 3 # number of ReadExReq MSHR hits
< system.l2c.ReadExReq_mshr_hits::total 3 # number of ReadExReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 217 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu0.data 87 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 35 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 178 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.data 73 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 8 # number of ReadSharedReq MSHR hits
< system.l2c.ReadSharedReq_mshr_hits::total 598 # number of ReadSharedReq MSHR hits
< system.l2c.demand_mshr_hits::cpu0.inst 217 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu0.data 90 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 35 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.inst 178 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.data 73 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 8 # number of demand (read+write) MSHR hits
< system.l2c.demand_mshr_hits::total 601 # number of demand (read+write) MSHR hits
< system.l2c.overall_mshr_hits::cpu0.inst 217 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu0.data 90 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 35 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.inst 178 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.data 73 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 8 # number of overall MSHR hits
< system.l2c.overall_mshr_hits::total 601 # number of overall MSHR hits
< system.l2c.CleanEvict_mshr_misses::writebacks 52518 # number of CleanEvict MSHR misses
< system.l2c.CleanEvict_mshr_misses::total 52518 # number of CleanEvict MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu0.data 47588 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::cpu1.data 43593 # number of UpgradeReq MSHR misses
< system.l2c.UpgradeReq_mshr_misses::total 91181 # number of UpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9906 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 10331 # number of SCUpgradeReq MSHR misses
< system.l2c.SCUpgradeReq_mshr_misses::total 20237 # number of SCUpgradeReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu0.data 509246 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::cpu1.data 164886 # number of ReadExReq MSHR misses
< system.l2c.ReadExReq_mshr_misses::total 674132 # number of ReadExReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2732 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2383 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 65710 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.data 171433 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 297567 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2128 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1988 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 39854 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.data 112009 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 243371 # number of ReadSharedReq MSHR misses
< system.l2c.ReadSharedReq_mshr_misses::total 939175 # number of ReadSharedReq MSHR misses
< system.l2c.demand_mshr_misses::cpu0.dtb.walker 2732 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.itb.walker 2383 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.inst 65710 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.data 680679 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 297567 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.dtb.walker 2128 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.itb.walker 1988 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.inst 39854 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.data 276895 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 243371 # number of demand (read+write) MSHR misses
< system.l2c.demand_mshr_misses::total 1613307 # number of demand (read+write) MSHR misses
< system.l2c.overall_mshr_misses::cpu0.dtb.walker 2732 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.itb.walker 2383 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.inst 65710 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.data 680679 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 297567 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.dtb.walker 2128 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.itb.walker 1988 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.inst 39854 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.data 276895 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 243371 # number of overall MSHR misses
< system.l2c.overall_mshr_misses::total 1613307 # number of overall MSHR misses
---
> system.l2c.writebacks::writebacks 1190221 # number of writebacks
> system.l2c.writebacks::total 1190221 # number of writebacks
> system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 97 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu0.data 21 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 189 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::cpu1.data 20 # number of ReadSharedReq MSHR hits
> system.l2c.ReadSharedReq_mshr_hits::total 327 # number of ReadSharedReq MSHR hits
> system.l2c.demand_mshr_hits::cpu0.inst 97 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu0.data 21 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.inst 189 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::cpu1.data 20 # number of demand (read+write) MSHR hits
> system.l2c.demand_mshr_hits::total 327 # number of demand (read+write) MSHR hits
> system.l2c.overall_mshr_hits::cpu0.inst 97 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu0.data 21 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.inst 189 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::cpu1.data 20 # number of overall MSHR hits
> system.l2c.overall_mshr_hits::total 327 # number of overall MSHR hits
> system.l2c.CleanEvict_mshr_misses::writebacks 49518 # number of CleanEvict MSHR misses
> system.l2c.CleanEvict_mshr_misses::total 49518 # number of CleanEvict MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu0.data 49689 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::cpu1.data 45204 # number of UpgradeReq MSHR misses
> system.l2c.UpgradeReq_mshr_misses::total 94893 # number of UpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 10659 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 8662 # number of SCUpgradeReq MSHR misses
> system.l2c.SCUpgradeReq_mshr_misses::total 19321 # number of SCUpgradeReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu0.data 547046 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::cpu1.data 101994 # number of ReadExReq MSHR misses
> system.l2c.ReadExReq_mshr_misses::total 649040 # number of ReadExReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 3253 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3182 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 67483 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.data 173742 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 345323 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1427 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1037 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 36295 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.data 93446 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 171017 # number of ReadSharedReq MSHR misses
> system.l2c.ReadSharedReq_mshr_misses::total 896205 # number of ReadSharedReq MSHR misses
> system.l2c.demand_mshr_misses::cpu0.dtb.walker 3253 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.itb.walker 3182 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.inst 67483 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.data 720788 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 345323 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.dtb.walker 1427 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.itb.walker 1037 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.inst 36295 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.data 195440 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 171017 # number of demand (read+write) MSHR misses
> system.l2c.demand_mshr_misses::total 1545245 # number of demand (read+write) MSHR misses
> system.l2c.overall_mshr_misses::cpu0.dtb.walker 3253 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.itb.walker 3182 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.inst 67483 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.data 720788 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 345323 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.dtb.walker 1427 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.itb.walker 1037 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.inst 36295 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.data 195440 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 171017 # number of overall MSHR misses
> system.l2c.overall_mshr_misses::total 1545245 # number of overall MSHR misses
3586c3583
< system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32342 # number of ReadReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31951 # number of ReadReq MSHR uncacheable
3588,3592c3585,3589
< system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6434 # number of ReadReq MSHR uncacheable
< system.l2c.ReadReq_mshr_uncacheable::total 60137 # number of ReadReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu0.data 31823 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::cpu1.data 6853 # number of WriteReq MSHR uncacheable
< system.l2c.WriteReq_mshr_uncacheable::total 38676 # number of WriteReq MSHR uncacheable
---
> system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6824 # number of ReadReq MSHR uncacheable
> system.l2c.ReadReq_mshr_uncacheable::total 60136 # number of ReadReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu0.data 31485 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::cpu1.data 7171 # number of WriteReq MSHR uncacheable
> system.l2c.WriteReq_mshr_uncacheable::total 38656 # number of WriteReq MSHR uncacheable
3594c3591
< system.l2c.overall_mshr_uncacheable_misses::cpu0.data 64165 # number of overall MSHR uncacheable misses
---
> system.l2c.overall_mshr_uncacheable_misses::cpu0.data 63436 # number of overall MSHR uncacheable misses
3596,3652c3593,3649
< system.l2c.overall_mshr_uncacheable_misses::cpu1.data 13287 # number of overall MSHR uncacheable misses
< system.l2c.overall_mshr_uncacheable_misses::total 98813 # number of overall MSHR uncacheable misses
< system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 990436504 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 906238506 # number of UpgradeReq MSHR miss cycles
< system.l2c.UpgradeReq_mshr_miss_latency::total 1896675010 # number of UpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 205762002 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 214626501 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.SCUpgradeReq_mshr_miss_latency::total 420388503 # number of SCUpgradeReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 61634019996 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 16330624499 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadExReq_mshr_miss_latency::total 77964644495 # number of ReadExReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 225775500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 196152000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 4984045002 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 14830916998 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38062777880 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 181466500 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 163163000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 3054573000 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 9843412999 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 30890783215 # number of ReadSharedReq MSHR miss cycles
< system.l2c.ReadSharedReq_mshr_miss_latency::total 102433066094 # number of ReadSharedReq MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 225775500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 196152000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.inst 4984045002 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.data 76464936994 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 38062777880 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 181466500 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 163163000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.inst 3054573000 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.data 26174037498 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 30890783215 # number of demand (read+write) MSHR miss cycles
< system.l2c.demand_mshr_miss_latency::total 180397710589 # number of demand (read+write) MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 225775500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 196152000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.inst 4984045002 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.data 76464936994 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38062777880 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 181466500 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 163163000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.inst 3054573000 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.data 26174037498 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 30890783215 # number of overall MSHR miss cycles
< system.l2c.overall_mshr_miss_latency::total 180397710589 # number of overall MSHR miss cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1320748000 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4976486500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4081500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 543120500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.ReadReq_mshr_uncacheable_latency::total 6844436500 # number of ReadReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4733537033 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 691840500 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 5425377533 # number of WriteReq MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1320748000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9710023533 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4081500 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1234961000 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 12269814033 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_misses::cpu1.data 13995 # number of overall MSHR uncacheable misses
> system.l2c.overall_mshr_uncacheable_misses::total 98792 # number of overall MSHR uncacheable misses
> system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 3656557006 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3330209007 # number of UpgradeReq MSHR miss cycles
> system.l2c.UpgradeReq_mshr_miss_latency::total 6986766013 # number of UpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 815429503 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 662042995 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.SCUpgradeReq_mshr_miss_latency::total 1477472498 # number of SCUpgradeReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 92301857996 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 14231419498 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadExReq_mshr_miss_latency::total 106533277494 # number of ReadExReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 427356500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 415425500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 8580768502 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 23891460998 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 59968803653 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 195855000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 141327000 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4625471500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 12587638500 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 29904675146 # number of ReadSharedReq MSHR miss cycles
> system.l2c.ReadSharedReq_mshr_miss_latency::total 140738782299 # number of ReadSharedReq MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 427356500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 415425500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.inst 8580768502 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.data 116193318994 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 59968803653 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 195855000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 141327000 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.inst 4625471500 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.data 26819057998 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 29904675146 # number of demand (read+write) MSHR miss cycles
> system.l2c.demand_mshr_miss_latency::total 247272059793 # number of demand (read+write) MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 427356500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 415425500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.inst 8580768502 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.data 116193318994 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 59968803653 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 195855000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 141327000 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.inst 4625471500 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.data 26819057998 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 29904675146 # number of overall MSHR miss cycles
> system.l2c.overall_mshr_miss_latency::total 247272059793 # number of overall MSHR miss cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2396727000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4940514000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7197500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 587373500 # number of ReadReq MSHR uncacheable cycles
> system.l2c.ReadReq_mshr_uncacheable_latency::total 7931812000 # number of ReadReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4820729533 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 738465000 # number of WriteReq MSHR uncacheable cycles
> system.l2c.WriteReq_mshr_uncacheable_latency::total 5559194533 # number of WriteReq MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2396727000 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9761243533 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7197500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1325838500 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 13491006533 # number of overall MSHR uncacheable cycles
3655,3751c3652,3748
< system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.612632 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.617412 # mshr miss rate for UpgradeReq accesses
< system.l2c.UpgradeReq_mshr_miss_rate::total 0.614908 # mshr miss rate for UpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.605353 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.626273 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.615855 # mshr miss rate for SCUpgradeReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.758614 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.517286 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadExReq_mshr_miss_rate::total 0.680916 # mshr miss rate for ReadExReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.291943 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.346769 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.099427 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.218054 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.500767 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.243478 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.321683 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.065657 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.167843 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.460859 # mshr miss rate for ReadSharedReq accesses
< system.l2c.ReadSharedReq_mshr_miss_rate::total 0.242375 # mshr miss rate for ReadSharedReq accesses
< system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.291943 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.346769 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.inst 0.099427 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.data 0.467024 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.500767 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.243478 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.321683 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.inst 0.065657 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.data 0.280800 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.460859 # mshr miss rate for demand accesses
< system.l2c.demand_mshr_miss_rate::total 0.331621 # mshr miss rate for demand accesses
< system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.291943 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.346769 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.inst 0.099427 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.data 0.467024 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.500767 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.243478 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.321683 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.inst 0.065657 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.data 0.280800 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.460859 # mshr miss rate for overall accesses
< system.l2c.overall_mshr_miss_rate::total 0.331621 # mshr miss rate for overall accesses
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20812.736488 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20788.624458 # average UpgradeReq mshr miss latency
< system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20801.208695 # average UpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20771.451847 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20774.997677 # average SCUpgradeReq mshr miss latency
< system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20773.261995 # average SCUpgradeReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 121029.954081 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99041.910769 # average ReadExReq mshr miss latency
< system.l2c.ReadExReq_avg_mshr_miss_latency::total 115651.896802 # average ReadExReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 82641.105417 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 82313.050776 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75849.109755 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 86511.447609 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127913.303155 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 85275.610902 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82073.943662 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76644.075877 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 87880.554232 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126928.776292 # average ReadSharedReq mshr miss latency
< system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 109067.070667 # average ReadSharedReq mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 82641.105417 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82313.050776 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75849.109755 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.data 112336.265691 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127913.303155 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 85275.610902 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82073.943662 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76644.075877 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94526.941613 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126928.776292 # average overall mshr miss latency
< system.l2c.demand_avg_mshr_miss_latency::total 111818.587900 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 82641.105417 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82313.050776 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75849.109755 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.data 112336.265691 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 127913.303155 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 85275.610902 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82073.943662 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76644.075877 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94526.941613 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 126928.776292 # average overall mshr miss latency
< system.l2c.overall_avg_mshr_miss_latency::total 111818.587900 # average overall mshr miss latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 153870.709913 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60917.910448 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 84414.128070 # average ReadReq mshr uncacheable latency
< system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 113814.066215 # average ReadReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148745.782390 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100954.399533 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 140277.627805 # average WriteReq mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151328.972695 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60917.910448 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 92945.059080 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 124172.062714 # average overall mshr uncacheable latency
---
> system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.630379 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.582188 # mshr miss rate for UpgradeReq accesses
> system.l2c.UpgradeReq_mshr_miss_rate::total 0.606465 # mshr miss rate for UpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.625565 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.606158 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.616713 # mshr miss rate for SCUpgradeReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.767553 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.388438 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadExReq_mshr_miss_rate::total 0.665485 # mshr miss rate for ReadExReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.330522 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.422072 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.098363 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.215848 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.537405 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.192994 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.199461 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.064704 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.149076 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.367704 # mshr miss rate for ReadSharedReq accesses
> system.l2c.ReadSharedReq_mshr_miss_rate::total 0.234829 # mshr miss rate for ReadSharedReq accesses
> system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.330522 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.422072 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.inst 0.098363 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.data 0.474940 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.537405 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.192994 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.199461 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.inst 0.064704 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.data 0.219741 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.367704 # mshr miss rate for demand accesses
> system.l2c.demand_mshr_miss_rate::total 0.322484 # mshr miss rate for demand accesses
> system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.330522 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.422072 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.inst 0.098363 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.data 0.474940 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.537405 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.192994 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.199461 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.inst 0.064704 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.data 0.219741 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.367704 # mshr miss rate for overall accesses
> system.l2c.overall_mshr_miss_rate::total 0.322484 # mshr miss rate for overall accesses
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73588.862847 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73670.670892 # average UpgradeReq mshr miss latency
> system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73627.833592 # average UpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76501.501360 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76430.731355 # average SCUpgradeReq mshr miss latency
> system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76469.773718 # average SCUpgradeReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 168727.781569 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139531.928329 # average ReadExReq mshr miss latency
> system.l2c.ReadExReq_avg_mshr_miss_latency::total 164139.771808 # average ReadExReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 131373.040271 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 130554.839723 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127154.520427 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 137511.142948 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173660.033224 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 137249.474422 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 136284.474446 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127441.011159 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 134704.947242 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174863.757088 # average ReadSharedReq mshr miss latency
> system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 157038.604224 # average ReadSharedReq mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 131373.040271 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 130554.839723 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127154.520427 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.data 161203.181787 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173660.033224 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 137249.474422 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 136284.474446 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127441.011159 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.data 137223.997124 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174863.757088 # average overall mshr miss latency
> system.l2c.demand_avg_mshr_miss_latency::total 160021.265102 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131373.040271 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130554.839723 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127154.520427 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.data 161203.181787 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173660.033224 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 137249.474422 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 136284.474446 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127441.011159 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.data 137223.997124 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174863.757088 # average overall mshr miss latency
> system.l2c.overall_avg_mshr_miss_latency::total 160021.265102 # average overall mshr miss latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112554.099746 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154627.836374 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107425.373134 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 86074.662954 # average ReadReq mshr uncacheable latency
> system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131897.898098 # average ReadReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153111.943243 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 102979.361316 # average WriteReq mshr uncacheable latency
> system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 143811.944666 # average WriteReq mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112554.099746 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 153875.457674 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107425.373134 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 94736.584494 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 136559.706586 # average overall mshr uncacheable latency
3753,3765c3750,3762
< system.membus.trans_dist::ReadReq 60137 # Transaction distribution
< system.membus.trans_dist::ReadResp 1008264 # Transaction distribution
< system.membus.trans_dist::WriteReq 38676 # Transaction distribution
< system.membus.trans_dist::WriteResp 38676 # Transaction distribution
< system.membus.trans_dist::Writeback 1353245 # Transaction distribution
< system.membus.trans_dist::CleanEvict 256072 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 446472 # Transaction distribution
< system.membus.trans_dist::SCUpgradeReq 317458 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 117838 # Transaction distribution
< system.membus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
< system.membus.trans_dist::ReadExReq 689582 # Transaction distribution
< system.membus.trans_dist::ReadExResp 667715 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 948127 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 60136 # Transaction distribution
> system.membus.trans_dist::ReadResp 965246 # Transaction distribution
> system.membus.trans_dist::WriteReq 38656 # Transaction distribution
> system.membus.trans_dist::WriteResp 38656 # Transaction distribution
> system.membus.trans_dist::Writeback 1296915 # Transaction distribution
> system.membus.trans_dist::CleanEvict 243951 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 452760 # Transaction distribution
> system.membus.trans_dist::SCUpgradeReq 304384 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 121976 # Transaction distribution
> system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
> system.membus.trans_dist::ReadExReq 662340 # Transaction distribution
> system.membus.trans_dist::ReadExResp 641281 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 905110 # Transaction distribution
3768c3765
< system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122682 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122826 # Packet count per connected master and slave (bytes)
3770,3776c3767,3773
< system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27002 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5660502 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.l2c.mem_side::total 5810264 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342643 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 342643 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 6152907 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155812 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26816 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5450054 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.l2c.mem_side::total 5599774 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342030 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 342030 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 5941804 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155933 # Cumulative packet size per connected master and slave (bytes)
3778,3785c3775,3782
< system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54004 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 182936448 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.l2c.mem_side::total 183146836 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7268096 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 7268096 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 190414932 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 670794 # Total snoops (count)
< system.membus.snoop_fanout::samples 4218827 # Request fanout histogram
---
> system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 53632 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174888448 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.l2c.mem_side::total 175098585 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7250496 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 7250496 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 182349081 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 659296 # Total snoops (count)
> system.membus.snoop_fanout::samples 4073524 # Request fanout histogram
3790c3787
< system.membus.snoop_fanout::1 4218827 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 4073524 100.00% 100.00% # Request fanout histogram
3795,3796c3792,3793
< system.membus.snoop_fanout::total 4218827 # Request fanout histogram
< system.membus.reqLayer0.occupancy 97993999 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 4073524 # Request fanout histogram
> system.membus.reqLayer0.occupancy 98143499 # Layer occupancy (ticks)
3800c3797
< system.membus.reqLayer2.occupancy 22746984 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 22747469 # Layer occupancy (ticks)
3802c3799
< system.membus.reqLayer5.occupancy 9381331556 # Layer occupancy (ticks)
---
> system.membus.reqLayer5.occupancy 9016528809 # Layer occupancy (ticks)
3804c3801
< system.membus.respLayer2.occupancy 8783305125 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 8432717951 # Layer occupancy (ticks)
3806c3803
< system.membus.respLayer3.occupancy 229295864 # Layer occupancy (ticks)
---
> system.membus.respLayer3.occupancy 230475062 # Layer occupancy (ticks)
3860,3873c3857,3876
< system.toL2Bus.trans_dist::ReadReq 60139 # Transaction distribution
< system.toL2Bus.trans_dist::ReadResp 4816420 # Transaction distribution
< system.toL2Bus.trans_dist::WriteReq 38676 # Transaction distribution
< system.toL2Bus.trans_dist::WriteResp 38676 # Transaction distribution
< system.toL2Bus.trans_dist::Writeback 3889503 # Transaction distribution
< system.toL2Bus.trans_dist::CleanEvict 1527175 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeReq 497158 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeReq 330081 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeResp 827239 # Transaction distribution
< system.toL2Bus.trans_dist::SCUpgradeFailReq 247 # Transaction distribution
< system.toL2Bus.trans_dist::UpgradeFailResp 247 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExReq 1142368 # Transaction distribution
< system.toL2Bus.trans_dist::ReadExResp 1142368 # Transaction distribution
< system.toL2Bus.trans_dist::ReadSharedReq 4763508 # Transaction distribution
---
> system.toL2Bus.snoop_filter.tot_requests 11519638 # Total number of requests made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_requests 5862055 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_requests 2048796 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.snoop_filter.tot_snoops 167370 # Total number of snoops made to the snoop filter.
> system.toL2Bus.snoop_filter.hit_single_snoops 156134 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.toL2Bus.snoop_filter.hit_multi_snoops 11236 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.toL2Bus.trans_dist::ReadReq 60138 # Transaction distribution
> system.toL2Bus.trans_dist::ReadResp 4755206 # Transaction distribution
> system.toL2Bus.trans_dist::WriteReq 38656 # Transaction distribution
> system.toL2Bus.trans_dist::WriteResp 38656 # Transaction distribution
> system.toL2Bus.trans_dist::Writeback 3790142 # Transaction distribution
> system.toL2Bus.trans_dist::CleanEvict 1500041 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeReq 506577 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeReq 316392 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeResp 822969 # Transaction distribution
> system.toL2Bus.trans_dist::SCUpgradeFailReq 115 # Transaction distribution
> system.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExReq 1127077 # Transaction distribution
> system.toL2Bus.trans_dist::ReadExResp 1127077 # Transaction distribution
> system.toL2Bus.trans_dist::ReadSharedReq 4702306 # Transaction distribution
3875,3884c3878,3887
< system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8767118 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6899331 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_count::total 15666449 # Packet count per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 271825986 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 202528722 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.pkt_size::total 474354708 # Cumulative packet size per connected master and slave (bytes)
< system.toL2Bus.snoops 3515812 # Total snoops (count)
< system.toL2Bus.snoop_fanout::samples 13605383 # Request fanout histogram
< system.toL2Bus.snoop_fanout::mean 1.134927 # Request fanout histogram
< system.toL2Bus.snoop_fanout::stdev 0.341646 # Request fanout histogram
---
> system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9146865 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6326733 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_count::total 15473598 # Packet count per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 285949105 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 180962856 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.pkt_size::total 466911961 # Cumulative packet size per connected master and slave (bytes)
> system.toL2Bus.snoops 3420267 # Total snoops (count)
> system.toL2Bus.snoop_fanout::samples 13372960 # Request fanout histogram
> system.toL2Bus.snoop_fanout::mean 0.331842 # Request fanout histogram
> system.toL2Bus.snoop_fanout::stdev 0.472656 # Request fanout histogram
3886,3888c3889,3891
< system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.toL2Bus.snoop_fanout::1 11769647 86.51% 86.51% # Request fanout histogram
< system.toL2Bus.snoop_fanout::2 1835736 13.49% 100.00% # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::0 8946480 66.90% 66.90% # Request fanout histogram
> system.toL2Bus.snoop_fanout::1 4415244 33.02% 99.92% # Request fanout histogram
> system.toL2Bus.snoop_fanout::2 11236 0.08% 100.00% # Request fanout histogram
3890c3893
< system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3892,3893c3895,3896
< system.toL2Bus.snoop_fanout::total 13605383 # Request fanout histogram
< system.toL2Bus.reqLayer0.occupancy 8891301093 # Layer occupancy (ticks)
---
> system.toL2Bus.snoop_fanout::total 13372960 # Request fanout histogram
> system.toL2Bus.reqLayer0.occupancy 8776402150 # Layer occupancy (ticks)
3895c3898
< system.toL2Bus.snoopLayer0.occupancy 2589000 # Layer occupancy (ticks)
---
> system.toL2Bus.snoopLayer0.occupancy 2601544 # Layer occupancy (ticks)
3897c3900
< system.toL2Bus.respLayer0.occupancy 5132723331 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer0.occupancy 5338662327 # Layer occupancy (ticks)
3899c3902
< system.toL2Bus.respLayer1.occupancy 4211299918 # Layer occupancy (ticks)
---
> system.toL2Bus.respLayer1.occupancy 3896618177 # Layer occupancy (ticks)
3902c3905
< system.cpu0.kern.inst.quiesce 14670 # number of quiesce instructions executed
---
> system.cpu0.kern.inst.quiesce 14407 # number of quiesce instructions executed
3904c3907
< system.cpu1.kern.inst.quiesce 7288 # number of quiesce instructions executed
---
> system.cpu1.kern.inst.quiesce 7094 # number of quiesce instructions executed