Cross Reference: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt

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stats.txt (11530:6e143fd2cabf)	stats.txt (11547:dd6dfd38b6c2)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.384315 # Number of seconds simulated 4sim_ticks 47384315163000 # Number of ticks simulated 5final_tick 47384315163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.384315 # Number of seconds simulated 4sim_ticks 47384315163000 # Number of ticks simulated 5final_tick 47384315163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 162093 # Simulator instruction rate (inst/s) 8host_op_rate 190619 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 8503081814 # Simulator tick rate (ticks/s) 10host_mem_usage 814268 # Number of bytes of host memory used 11host_seconds 5572.60 # Real time elapsed on the host	7host_inst_rate 151085 # Simulator instruction rate (inst/s) 8host_op_rate 177673 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 7925620115 # Simulator tick rate (ticks/s) 10host_mem_usage 773240 # Number of bytes of host memory used 11host_seconds 5978.63 # Real time elapsed on the host
12sim_insts 903281747 # Number of instructions simulated 13sim_ops 1062243320 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 88320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 58304 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 4233376 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 12825352 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 13896960 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 201536 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 189312 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 2647264 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 11439440 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 16431296 # Number of bytes read from this memory 27system.physmem.bytes_read::realview.ide 444928 # Number of bytes read from this memory 28system.physmem.bytes_read::total 62456088 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 4233376 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 2647264 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 6880640 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 79489088 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 35system.physmem.bytes_written::total 79509672 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 1380 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 911 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 82099 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 200409 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 217140 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 3149 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.itb.walker 2958 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.inst 41407 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 178754 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 256739 # Number of read requests responded to by this memory 46system.physmem.num_reads::realview.ide 6952 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 991898 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 1242017 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 51system.physmem.num_writes::total 1244591 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 1864 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.itb.walker 1230 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.inst 89341 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 270667 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 293282 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 4253 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.itb.walker 3995 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.inst 55868 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 241418 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 346767 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::realview.ide 9390 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::total 1318075 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 89341 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 55868 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 145209 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 1677540 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::total 1677974 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 1677540 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 1864 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.itb.walker 1230 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.inst 89341 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 271101 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 293282 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 4253 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.itb.walker 3995 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.inst 55868 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 241418 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 346767 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::realview.ide 9390 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::total 2996050 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 991898 # Number of read requests accepted 85system.physmem.writeReqs 1244591 # Number of write requests accepted 86system.physmem.readBursts 991898 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 1244591 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 63457600 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 23872 # Total number of bytes read from write queue 90system.physmem.bytesWritten 79508544 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 62456088 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 79509672 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 373 # Number of DRAM read bursts serviced by the write queue 94system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 96system.physmem.perBankRdBursts::0 57534 # Per bank write bursts 97system.physmem.perBankRdBursts::1 67322 # Per bank write bursts 98system.physmem.perBankRdBursts::2 57239 # Per bank write bursts 99system.physmem.perBankRdBursts::3 59640 # Per bank write bursts 100system.physmem.perBankRdBursts::4 58543 # Per bank write bursts 101system.physmem.perBankRdBursts::5 68655 # Per bank write bursts 102system.physmem.perBankRdBursts::6 57471 # Per bank write bursts 103system.physmem.perBankRdBursts::7 60839 # Per bank write bursts 104system.physmem.perBankRdBursts::8 60208 # Per bank write bursts 105system.physmem.perBankRdBursts::9 81942 # Per bank write bursts 106system.physmem.perBankRdBursts::10 59318 # Per bank write bursts 107system.physmem.perBankRdBursts::11 61436 # Per bank write bursts 108system.physmem.perBankRdBursts::12 60309 # Per bank write bursts 109system.physmem.perBankRdBursts::13 62906 # Per bank write bursts 110system.physmem.perBankRdBursts::14 58748 # Per bank write bursts 111system.physmem.perBankRdBursts::15 59415 # Per bank write bursts 112system.physmem.perBankWrBursts::0 74024 # Per bank write bursts 113system.physmem.perBankWrBursts::1 81724 # Per bank write bursts 114system.physmem.perBankWrBursts::2 74878 # Per bank write bursts 115system.physmem.perBankWrBursts::3 76858 # Per bank write bursts 116system.physmem.perBankWrBursts::4 76593 # Per bank write bursts 117system.physmem.perBankWrBursts::5 82864 # Per bank write bursts 118system.physmem.perBankWrBursts::6 74278 # Per bank write bursts 119system.physmem.perBankWrBursts::7 78173 # Per bank write bursts 120system.physmem.perBankWrBursts::8 76626 # Per bank write bursts 121system.physmem.perBankWrBursts::9 80136 # Per bank write bursts 122system.physmem.perBankWrBursts::10 77163 # Per bank write bursts 123system.physmem.perBankWrBursts::11 80655 # Per bank write bursts 124system.physmem.perBankWrBursts::12 76245 # Per bank write bursts 125system.physmem.perBankWrBursts::13 79687 # Per bank write bursts 126system.physmem.perBankWrBursts::14 75064 # Per bank write bursts 127system.physmem.perBankWrBursts::15 77353 # Per bank write bursts 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 129system.physmem.numWrRetry 51477 # Number of times write queue was full causing retry 130system.physmem.totGap 47384313590500 # Total gap between requests 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 0 # Read request sizes (log2) 134system.physmem.readPktSize::3 25 # Read request sizes (log2) 135system.physmem.readPktSize::4 21333 # Read request sizes (log2) 136system.physmem.readPktSize::5 0 # Read request sizes (log2) 137system.physmem.readPktSize::6 970540 # Read request sizes (log2) 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 2 # Write request sizes (log2) 141system.physmem.writePktSize::3 2572 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) 144system.physmem.writePktSize::6 1242017 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 445378 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 243433 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 76996 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 56880 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 37150 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 31949 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 29173 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 27068 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 25124 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 6848 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 3836 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 2454 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 1543 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 1198 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::14 708 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 591 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::16 507 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 398 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 167 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 104 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 177system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::15 23188 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 27066 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 36083 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 41131 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 44808 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 48159 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 53054 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 57269 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 61997 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 63720 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 68707 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 72599 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 69938 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 72538 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 82492 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 73770 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 67397 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 63055 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 4615 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 3320 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 2487 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 2032 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 1667 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 1537 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 1438 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 1351 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 1216 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 1258 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 1384 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 1422 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 1370 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 1543 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 1563 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 1451 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 1716 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 1865 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 2021 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 2168 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 2359 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 2664 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 2841 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 3106 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 3376 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 3630 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 3943 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 4563 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 6136 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 24445 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 120872 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 982131 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 145.566960 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 98.657532 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 193.069606 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 654413 66.63% 66.63% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 194527 19.81% 86.44% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 50477 5.14% 91.58% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 21176 2.16% 93.73% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 16419 1.67% 95.41% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 9395 0.96% 96.36% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 6596 0.67% 97.03% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 5289 0.54% 97.57% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 23839 2.43% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 982131 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 56922 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 17.418608 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 74.895923 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-511 56917 99.99% 99.99% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::512-1023 2 0.00% 99.99% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes 262system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes 263system.physmem.rdPerTurnAround::total 56922 # Reads before turning the bus around for writes 264system.physmem.wrPerTurnAround::samples 56922 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::mean 21.824971 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::gmean 17.750218 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::stdev 638.100533 # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::0-4095 56920 100.00% 100.00% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::45056-49151 1 0.00% 100.00% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::143360-147455 1 0.00% 100.00% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::total 56922 # Writes before turning the bus around for reads 272system.physmem.totQLat 43578574020 # Total ticks spent queuing 273system.physmem.totMemAccLat 62169667770 # Total ticks spent from burst creation until serviced by the DRAM 274system.physmem.totBusLat 4957625000 # Total ticks spent in databus transfers 275system.physmem.avgQLat 43951.06 # Average queueing delay per DRAM burst 276system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 277system.physmem.avgMemAccLat 62701.06 # Average memory access latency per DRAM burst 278system.physmem.avgRdBW 1.34 # Average DRAM read bandwidth in MiByte/s 279system.physmem.avgWrBW 1.68 # Average achieved write bandwidth in MiByte/s 280system.physmem.avgRdBWSys 1.32 # Average system read bandwidth in MiByte/s 281system.physmem.avgWrBWSys 1.68 # Average system write bandwidth in MiByte/s 282system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 283system.physmem.busUtil 0.02 # Data bus utilization in percentage 284system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 285system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 286system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing 287system.physmem.avgWrQLen 23.75 # Average write queue length when enqueuing 288system.physmem.readRowHits 750886 # Number of row buffer hits during reads 289system.physmem.writeRowHits 500828 # Number of row buffer hits during writes 290system.physmem.readRowHitRate 75.73 # Row buffer hit rate for reads 291system.physmem.writeRowHitRate 40.31 # Row buffer hit rate for writes 292system.physmem.avgGap 21186920.03 # Average gap between requests 293system.physmem.pageHitRate 56.03 # Row buffer hit rate, read and write combined 294system.physmem_0.actEnergy 3717395640 # Energy for activate commands per rank (pJ) 295system.physmem_0.preEnergy 2028340875 # Energy for precharge commands per rank (pJ) 296system.physmem_0.readEnergy 3800456400 # Energy for read commands per rank (pJ) 297system.physmem_0.writeEnergy 4013660160 # Energy for write commands per rank (pJ) 298system.physmem_0.refreshEnergy 3094913078400 # Energy for refresh commands per rank (pJ) 299system.physmem_0.actBackEnergy 1158326321940 # Energy for active background per rank (pJ) 300system.physmem_0.preBackEnergy 27414513105000 # Energy for precharge background per rank (pJ) 301system.physmem_0.totalEnergy 31681312358415 # Total energy per rank (pJ) 302system.physmem_0.averagePower 668.603367 # Core power per rank (mW) 303system.physmem_0.memoryStateTime::IDLE 45606511009457 # Time in different power states 304system.physmem_0.memoryStateTime::REF 1582266400000 # Time in different power states 305system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 306system.physmem_0.memoryStateTime::ACT 195537314293 # Time in different power states 307system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 308system.physmem_1.actEnergy 3707514720 # Energy for activate commands per rank (pJ) 309system.physmem_1.preEnergy 2022949500 # Energy for precharge commands per rank (pJ) 310system.physmem_1.readEnergy 3933399600 # Energy for read commands per rank (pJ) 311system.physmem_1.writeEnergy 4036579920 # Energy for write commands per rank (pJ) 312system.physmem_1.refreshEnergy 3094913078400 # Energy for refresh commands per rank (pJ) 313system.physmem_1.actBackEnergy 1156667621085 # Energy for active background per rank (pJ) 314system.physmem_1.preBackEnergy 27415968105750 # Energy for precharge background per rank (pJ) 315system.physmem_1.totalEnergy 31681249248975 # Total energy per rank (pJ) 316system.physmem_1.averagePower 668.602035 # Core power per rank (mW) 317system.physmem_1.memoryStateTime::IDLE 45608919765384 # Time in different power states 318system.physmem_1.memoryStateTime::REF 1582266400000 # Time in different power states 319system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 320system.physmem_1.memoryStateTime::ACT 193128558366 # Time in different power states 321system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 322system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 323system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory 324system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 325system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory 326system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 327system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory 328system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory 329system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory 330system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory 331system.realview.nvmem.num_reads::cpu0.inst 23 # Number of read requests responded to by this memory 332system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 333system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 334system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 335system.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory 336system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) 337system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 338system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s) 339system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 340system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s) 341system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) 342system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s) 343system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s) 344system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) 345system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 346system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) 347system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 348system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) 349system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 350system.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 351system.bridge.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 352system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 353system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 354system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 355system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 356system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 357system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 358system.cpu0.branchPred.lookups 138091637 # Number of BP lookups 359system.cpu0.branchPred.condPredicted 91311717 # Number of conditional branches predicted 360system.cpu0.branchPred.condIncorrect 6789940 # Number of conditional branches incorrect 361system.cpu0.branchPred.BTBLookups 97223509 # Number of BTB lookups 362system.cpu0.branchPred.BTBHits 59866310 # Number of BTB hits 363system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 364system.cpu0.branchPred.BTBHitPct 61.575961 # BTB Hit Percentage 365system.cpu0.branchPred.usedRAS 18644167 # Number of times the RAS was used to get a target. 366system.cpu0.branchPred.RASInCorrect 188685 # Number of incorrect RAS predictions. 367system.cpu0.branchPred.indirectLookups 4389066 # Number of indirect predictor lookups. 368system.cpu0.branchPred.indirectHits 2747803 # Number of indirect target hits. 369system.cpu0.branchPred.indirectMisses 1641263 # Number of indirect misses. 370system.cpu0.branchPredindirectMispredicted 409141 # Number of mispredicted indirect branches. 371system.cpu_clk_domain.clock 500 # Clock period in ticks 372system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 373system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 374system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 375system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 377system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 378system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 379system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 380system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 381system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 382system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 383system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 384system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 385system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 386system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 387system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 388system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 389system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 390system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 391system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 392system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 393system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 394system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 395system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 396system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 397system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 398system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 399system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 400system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 401system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 402system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 403system.cpu0.dtb.walker.walks 530338 # Table walker walks requested 404system.cpu0.dtb.walker.walksLong 530338 # Table walker walks initiated with long descriptors 405system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10426 # Level at which table walker walks with long descriptors terminate 406system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79784 # Level at which table walker walks with long descriptors terminate 407system.cpu0.dtb.walker.walksSquashedBefore 241995 # Table walks squashed before starting 408system.cpu0.dtb.walker.walkWaitTime::samples 288343 # Table walker wait (enqueue to first request) latency 409system.cpu0.dtb.walker.walkWaitTime::mean 2099.123266 # Table walker wait (enqueue to first request) latency 410system.cpu0.dtb.walker.walkWaitTime::stdev 12230.418976 # Table walker wait (enqueue to first request) latency 411system.cpu0.dtb.walker.walkWaitTime::0-65535 286535 99.37% 99.37% # Table walker wait (enqueue to first request) latency 412system.cpu0.dtb.walker.walkWaitTime::65536-131071 1269 0.44% 99.81% # Table walker wait (enqueue to first request) latency 413system.cpu0.dtb.walker.walkWaitTime::131072-196607 337 0.12% 99.93% # Table walker wait (enqueue to first request) latency 414system.cpu0.dtb.walker.walkWaitTime::196608-262143 138 0.05% 99.98% # Table walker wait (enqueue to first request) latency 415system.cpu0.dtb.walker.walkWaitTime::262144-327679 37 0.01% 99.99% # Table walker wait (enqueue to first request) latency 416system.cpu0.dtb.walker.walkWaitTime::327680-393215 22 0.01% 100.00% # Table walker wait (enqueue to first request) latency 417system.cpu0.dtb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 418system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 419system.cpu0.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkWaitTime::total 288343 # Table walker wait (enqueue to first request) latency 421system.cpu0.dtb.walker.walkCompletionTime::samples 261783 # Table walker service (enqueue to completion) latency 422system.cpu0.dtb.walker.walkCompletionTime::mean 19021.382214 # Table walker service (enqueue to completion) latency 423system.cpu0.dtb.walker.walkCompletionTime::gmean 16878.246550 # Table walker service (enqueue to completion) latency 424system.cpu0.dtb.walker.walkCompletionTime::stdev 10891.763559 # Table walker service (enqueue to completion) latency 425system.cpu0.dtb.walker.walkCompletionTime::0-32767 246122 94.02% 94.02% # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walkCompletionTime::32768-65535 14409 5.50% 99.52% # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::65536-98303 656 0.25% 99.77% # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walkCompletionTime::98304-131071 427 0.16% 99.94% # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::131072-163839 44 0.02% 99.95% # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::163840-196607 15 0.01% 99.96% # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::196608-229375 47 0.02% 99.98% # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::229376-262143 25 0.01% 99.99% # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::262144-294911 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::294912-327679 22 0.01% 99.99% # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::327680-360447 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::360448-393215 5 0.00% 100.00% # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::393216-425983 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::total 261783 # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walksPending::samples 513336492752 # Table walker pending requests distribution 441system.cpu0.dtb.walker.walksPending::mean 0.609866 # Table walker pending requests distribution 442system.cpu0.dtb.walker.walksPending::stdev 0.537961 # Table walker pending requests distribution 443system.cpu0.dtb.walker.walksPending::0-1 512309669252 99.80% 99.80% # Table walker pending requests distribution 444system.cpu0.dtb.walker.walksPending::2-3 522001000 0.10% 99.90% # Table walker pending requests distribution 445system.cpu0.dtb.walker.walksPending::4-5 221126000 0.04% 99.94% # Table walker pending requests distribution 446system.cpu0.dtb.walker.walksPending::6-7 109873500 0.02% 99.97% # Table walker pending requests distribution 447system.cpu0.dtb.walker.walksPending::8-9 86703000 0.02% 99.98% # Table walker pending requests distribution 448system.cpu0.dtb.walker.walksPending::10-11 51185000 0.01% 99.99% # Table walker pending requests distribution 449system.cpu0.dtb.walker.walksPending::12-13 14405500 0.00% 100.00% # Table walker pending requests distribution 450system.cpu0.dtb.walker.walksPending::14-15 21121500 0.00% 100.00% # Table walker pending requests distribution 451system.cpu0.dtb.walker.walksPending::16-17 397500 0.00% 100.00% # Table walker pending requests distribution 452system.cpu0.dtb.walker.walksPending::18-19 10500 0.00% 100.00% # Table walker pending requests distribution 453system.cpu0.dtb.walker.walksPending::total 513336492752 # Table walker pending requests distribution 454system.cpu0.dtb.walker.walkPageSizes::4K 79785 88.44% 88.44% # Table walker page sizes translated 455system.cpu0.dtb.walker.walkPageSizes::2M 10426 11.56% 100.00% # Table walker page sizes translated 456system.cpu0.dtb.walker.walkPageSizes::total 90211 # Table walker page sizes translated 457system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 530338 # Table walker requests started/completed, data/inst 458system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 459system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 530338 # Table walker requests started/completed, data/inst 460system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 90211 # Table walker requests started/completed, data/inst 461system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 462system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 90211 # Table walker requests started/completed, data/inst 463system.cpu0.dtb.walker.walkRequestOrigin::total 620549 # Table walker requests started/completed, data/inst 464system.cpu0.dtb.inst_hits 0 # ITB inst hits 465system.cpu0.dtb.inst_misses 0 # ITB inst misses 466system.cpu0.dtb.read_hits 99690232 # DTB read hits 467system.cpu0.dtb.read_misses 367422 # DTB read misses 468system.cpu0.dtb.write_hits 83046551 # DTB write hits 469system.cpu0.dtb.write_misses 162916 # DTB write misses 470system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 471system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 472system.cpu0.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID 473system.cpu0.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID	12sim_insts 903281747 # Number of instructions simulated 13sim_ops 1062243320 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 88320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 58304 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 4233376 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 12825352 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 13896960 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 201536 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 189312 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 2647264 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 11439440 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 16431296 # Number of bytes read from this memory 27system.physmem.bytes_read::realview.ide 444928 # Number of bytes read from this memory 28system.physmem.bytes_read::total 62456088 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 4233376 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 2647264 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 6880640 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 79489088 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 35system.physmem.bytes_written::total 79509672 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 1380 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 911 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 82099 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 200409 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 217140 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 3149 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.itb.walker 2958 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.inst 41407 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 178754 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 256739 # Number of read requests responded to by this memory 46system.physmem.num_reads::realview.ide 6952 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 991898 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 1242017 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 51system.physmem.num_writes::total 1244591 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 1864 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.itb.walker 1230 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.inst 89341 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 270667 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 293282 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 4253 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.itb.walker 3995 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.inst 55868 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 241418 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 346767 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::realview.ide 9390 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::total 1318075 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 89341 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 55868 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 145209 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 1677540 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::total 1677974 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 1677540 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 1864 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.itb.walker 1230 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.inst 89341 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 271101 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 293282 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 4253 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.itb.walker 3995 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.inst 55868 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 241418 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 346767 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::realview.ide 9390 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::total 2996050 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 991898 # Number of read requests accepted 85system.physmem.writeReqs 1244591 # Number of write requests accepted 86system.physmem.readBursts 991898 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 1244591 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 63457600 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 23872 # Total number of bytes read from write queue 90system.physmem.bytesWritten 79508544 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 62456088 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 79509672 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 373 # Number of DRAM read bursts serviced by the write queue 94system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 96system.physmem.perBankRdBursts::0 57534 # Per bank write bursts 97system.physmem.perBankRdBursts::1 67322 # Per bank write bursts 98system.physmem.perBankRdBursts::2 57239 # Per bank write bursts 99system.physmem.perBankRdBursts::3 59640 # Per bank write bursts 100system.physmem.perBankRdBursts::4 58543 # Per bank write bursts 101system.physmem.perBankRdBursts::5 68655 # Per bank write bursts 102system.physmem.perBankRdBursts::6 57471 # Per bank write bursts 103system.physmem.perBankRdBursts::7 60839 # Per bank write bursts 104system.physmem.perBankRdBursts::8 60208 # Per bank write bursts 105system.physmem.perBankRdBursts::9 81942 # Per bank write bursts 106system.physmem.perBankRdBursts::10 59318 # Per bank write bursts 107system.physmem.perBankRdBursts::11 61436 # Per bank write bursts 108system.physmem.perBankRdBursts::12 60309 # Per bank write bursts 109system.physmem.perBankRdBursts::13 62906 # Per bank write bursts 110system.physmem.perBankRdBursts::14 58748 # Per bank write bursts 111system.physmem.perBankRdBursts::15 59415 # Per bank write bursts 112system.physmem.perBankWrBursts::0 74024 # Per bank write bursts 113system.physmem.perBankWrBursts::1 81724 # Per bank write bursts 114system.physmem.perBankWrBursts::2 74878 # Per bank write bursts 115system.physmem.perBankWrBursts::3 76858 # Per bank write bursts 116system.physmem.perBankWrBursts::4 76593 # Per bank write bursts 117system.physmem.perBankWrBursts::5 82864 # Per bank write bursts 118system.physmem.perBankWrBursts::6 74278 # Per bank write bursts 119system.physmem.perBankWrBursts::7 78173 # Per bank write bursts 120system.physmem.perBankWrBursts::8 76626 # Per bank write bursts 121system.physmem.perBankWrBursts::9 80136 # Per bank write bursts 122system.physmem.perBankWrBursts::10 77163 # Per bank write bursts 123system.physmem.perBankWrBursts::11 80655 # Per bank write bursts 124system.physmem.perBankWrBursts::12 76245 # Per bank write bursts 125system.physmem.perBankWrBursts::13 79687 # Per bank write bursts 126system.physmem.perBankWrBursts::14 75064 # Per bank write bursts 127system.physmem.perBankWrBursts::15 77353 # Per bank write bursts 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 129system.physmem.numWrRetry 51477 # Number of times write queue was full causing retry 130system.physmem.totGap 47384313590500 # Total gap between requests 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 0 # Read request sizes (log2) 134system.physmem.readPktSize::3 25 # Read request sizes (log2) 135system.physmem.readPktSize::4 21333 # Read request sizes (log2) 136system.physmem.readPktSize::5 0 # Read request sizes (log2) 137system.physmem.readPktSize::6 970540 # Read request sizes (log2) 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 2 # Write request sizes (log2) 141system.physmem.writePktSize::3 2572 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) 144system.physmem.writePktSize::6 1242017 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 445378 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 243433 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 76996 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 56880 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 37150 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 31949 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 29173 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 27068 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 25124 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 6848 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 3836 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 2454 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 1543 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 1198 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::14 708 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 591 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::16 507 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 398 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 167 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 104 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 177system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::15 23188 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 27066 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 36083 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 41131 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 44808 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 48159 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 53054 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 57269 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 61997 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 63720 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 68707 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 72599 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 69938 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 72538 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 82492 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 73770 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 67397 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 63055 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 4615 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 3320 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 2487 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 2032 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 1667 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 1537 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 1438 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 1351 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 1216 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 1258 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 1384 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 1422 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 1370 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 1543 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 1563 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 1451 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 1716 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 1865 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 2021 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 2168 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 2359 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 2664 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 2841 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 3106 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 3376 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 3630 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 3943 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 4563 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 6136 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 24445 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 120872 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 982131 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 145.566960 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 98.657532 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 193.069606 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 654413 66.63% 66.63% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 194527 19.81% 86.44% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 50477 5.14% 91.58% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 21176 2.16% 93.73% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 16419 1.67% 95.41% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 9395 0.96% 96.36% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 6596 0.67% 97.03% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 5289 0.54% 97.57% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 23839 2.43% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 982131 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 56922 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 17.418608 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 74.895923 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-511 56917 99.99% 99.99% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::512-1023 2 0.00% 99.99% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes 262system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes 263system.physmem.rdPerTurnAround::total 56922 # Reads before turning the bus around for writes 264system.physmem.wrPerTurnAround::samples 56922 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::mean 21.824971 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::gmean 17.750218 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::stdev 638.100533 # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::0-4095 56920 100.00% 100.00% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::45056-49151 1 0.00% 100.00% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::143360-147455 1 0.00% 100.00% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::total 56922 # Writes before turning the bus around for reads 272system.physmem.totQLat 43578574020 # Total ticks spent queuing 273system.physmem.totMemAccLat 62169667770 # Total ticks spent from burst creation until serviced by the DRAM 274system.physmem.totBusLat 4957625000 # Total ticks spent in databus transfers 275system.physmem.avgQLat 43951.06 # Average queueing delay per DRAM burst 276system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 277system.physmem.avgMemAccLat 62701.06 # Average memory access latency per DRAM burst 278system.physmem.avgRdBW 1.34 # Average DRAM read bandwidth in MiByte/s 279system.physmem.avgWrBW 1.68 # Average achieved write bandwidth in MiByte/s 280system.physmem.avgRdBWSys 1.32 # Average system read bandwidth in MiByte/s 281system.physmem.avgWrBWSys 1.68 # Average system write bandwidth in MiByte/s 282system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 283system.physmem.busUtil 0.02 # Data bus utilization in percentage 284system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 285system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 286system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing 287system.physmem.avgWrQLen 23.75 # Average write queue length when enqueuing 288system.physmem.readRowHits 750886 # Number of row buffer hits during reads 289system.physmem.writeRowHits 500828 # Number of row buffer hits during writes 290system.physmem.readRowHitRate 75.73 # Row buffer hit rate for reads 291system.physmem.writeRowHitRate 40.31 # Row buffer hit rate for writes 292system.physmem.avgGap 21186920.03 # Average gap between requests 293system.physmem.pageHitRate 56.03 # Row buffer hit rate, read and write combined 294system.physmem_0.actEnergy 3717395640 # Energy for activate commands per rank (pJ) 295system.physmem_0.preEnergy 2028340875 # Energy for precharge commands per rank (pJ) 296system.physmem_0.readEnergy 3800456400 # Energy for read commands per rank (pJ) 297system.physmem_0.writeEnergy 4013660160 # Energy for write commands per rank (pJ) 298system.physmem_0.refreshEnergy 3094913078400 # Energy for refresh commands per rank (pJ) 299system.physmem_0.actBackEnergy 1158326321940 # Energy for active background per rank (pJ) 300system.physmem_0.preBackEnergy 27414513105000 # Energy for precharge background per rank (pJ) 301system.physmem_0.totalEnergy 31681312358415 # Total energy per rank (pJ) 302system.physmem_0.averagePower 668.603367 # Core power per rank (mW) 303system.physmem_0.memoryStateTime::IDLE 45606511009457 # Time in different power states 304system.physmem_0.memoryStateTime::REF 1582266400000 # Time in different power states 305system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 306system.physmem_0.memoryStateTime::ACT 195537314293 # Time in different power states 307system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 308system.physmem_1.actEnergy 3707514720 # Energy for activate commands per rank (pJ) 309system.physmem_1.preEnergy 2022949500 # Energy for precharge commands per rank (pJ) 310system.physmem_1.readEnergy 3933399600 # Energy for read commands per rank (pJ) 311system.physmem_1.writeEnergy 4036579920 # Energy for write commands per rank (pJ) 312system.physmem_1.refreshEnergy 3094913078400 # Energy for refresh commands per rank (pJ) 313system.physmem_1.actBackEnergy 1156667621085 # Energy for active background per rank (pJ) 314system.physmem_1.preBackEnergy 27415968105750 # Energy for precharge background per rank (pJ) 315system.physmem_1.totalEnergy 31681249248975 # Total energy per rank (pJ) 316system.physmem_1.averagePower 668.602035 # Core power per rank (mW) 317system.physmem_1.memoryStateTime::IDLE 45608919765384 # Time in different power states 318system.physmem_1.memoryStateTime::REF 1582266400000 # Time in different power states 319system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 320system.physmem_1.memoryStateTime::ACT 193128558366 # Time in different power states 321system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 322system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 323system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory 324system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 325system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory 326system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 327system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory 328system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory 329system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory 330system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory 331system.realview.nvmem.num_reads::cpu0.inst 23 # Number of read requests responded to by this memory 332system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 333system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 334system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 335system.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory 336system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) 337system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 338system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s) 339system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 340system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s) 341system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) 342system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s) 343system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s) 344system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) 345system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 346system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) 347system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 348system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) 349system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 350system.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 351system.bridge.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 352system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 353system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 354system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 355system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 356system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 357system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 358system.cpu0.branchPred.lookups 138091637 # Number of BP lookups 359system.cpu0.branchPred.condPredicted 91311717 # Number of conditional branches predicted 360system.cpu0.branchPred.condIncorrect 6789940 # Number of conditional branches incorrect 361system.cpu0.branchPred.BTBLookups 97223509 # Number of BTB lookups 362system.cpu0.branchPred.BTBHits 59866310 # Number of BTB hits 363system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 364system.cpu0.branchPred.BTBHitPct 61.575961 # BTB Hit Percentage 365system.cpu0.branchPred.usedRAS 18644167 # Number of times the RAS was used to get a target. 366system.cpu0.branchPred.RASInCorrect 188685 # Number of incorrect RAS predictions. 367system.cpu0.branchPred.indirectLookups 4389066 # Number of indirect predictor lookups. 368system.cpu0.branchPred.indirectHits 2747803 # Number of indirect target hits. 369system.cpu0.branchPred.indirectMisses 1641263 # Number of indirect misses. 370system.cpu0.branchPredindirectMispredicted 409141 # Number of mispredicted indirect branches. 371system.cpu_clk_domain.clock 500 # Clock period in ticks 372system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 373system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 374system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 375system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 377system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 378system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 379system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 380system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 381system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 382system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 383system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 384system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 385system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 386system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 387system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 388system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 389system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 390system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 391system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 392system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 393system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 394system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 395system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 396system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 397system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 398system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 399system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 400system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 401system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 402system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 403system.cpu0.dtb.walker.walks 530338 # Table walker walks requested 404system.cpu0.dtb.walker.walksLong 530338 # Table walker walks initiated with long descriptors 405system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10426 # Level at which table walker walks with long descriptors terminate 406system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79784 # Level at which table walker walks with long descriptors terminate 407system.cpu0.dtb.walker.walksSquashedBefore 241995 # Table walks squashed before starting 408system.cpu0.dtb.walker.walkWaitTime::samples 288343 # Table walker wait (enqueue to first request) latency 409system.cpu0.dtb.walker.walkWaitTime::mean 2099.123266 # Table walker wait (enqueue to first request) latency 410system.cpu0.dtb.walker.walkWaitTime::stdev 12230.418976 # Table walker wait (enqueue to first request) latency 411system.cpu0.dtb.walker.walkWaitTime::0-65535 286535 99.37% 99.37% # Table walker wait (enqueue to first request) latency 412system.cpu0.dtb.walker.walkWaitTime::65536-131071 1269 0.44% 99.81% # Table walker wait (enqueue to first request) latency 413system.cpu0.dtb.walker.walkWaitTime::131072-196607 337 0.12% 99.93% # Table walker wait (enqueue to first request) latency 414system.cpu0.dtb.walker.walkWaitTime::196608-262143 138 0.05% 99.98% # Table walker wait (enqueue to first request) latency 415system.cpu0.dtb.walker.walkWaitTime::262144-327679 37 0.01% 99.99% # Table walker wait (enqueue to first request) latency 416system.cpu0.dtb.walker.walkWaitTime::327680-393215 22 0.01% 100.00% # Table walker wait (enqueue to first request) latency 417system.cpu0.dtb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 418system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 419system.cpu0.dtb.walker.walkWaitTime::786432-851967 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkWaitTime::total 288343 # Table walker wait (enqueue to first request) latency 421system.cpu0.dtb.walker.walkCompletionTime::samples 261783 # Table walker service (enqueue to completion) latency 422system.cpu0.dtb.walker.walkCompletionTime::mean 19021.382214 # Table walker service (enqueue to completion) latency 423system.cpu0.dtb.walker.walkCompletionTime::gmean 16878.246550 # Table walker service (enqueue to completion) latency 424system.cpu0.dtb.walker.walkCompletionTime::stdev 10891.763559 # Table walker service (enqueue to completion) latency 425system.cpu0.dtb.walker.walkCompletionTime::0-32767 246122 94.02% 94.02% # Table walker service (enqueue to completion) latency 426system.cpu0.dtb.walker.walkCompletionTime::32768-65535 14409 5.50% 99.52% # Table walker service (enqueue to completion) latency 427system.cpu0.dtb.walker.walkCompletionTime::65536-98303 656 0.25% 99.77% # Table walker service (enqueue to completion) latency 428system.cpu0.dtb.walker.walkCompletionTime::98304-131071 427 0.16% 99.94% # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::131072-163839 44 0.02% 99.95% # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::163840-196607 15 0.01% 99.96% # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::196608-229375 47 0.02% 99.98% # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::229376-262143 25 0.01% 99.99% # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::262144-294911 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::294912-327679 22 0.01% 99.99% # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::327680-360447 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::360448-393215 5 0.00% 100.00% # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::393216-425983 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::total 261783 # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walksPending::samples 513336492752 # Table walker pending requests distribution 441system.cpu0.dtb.walker.walksPending::mean 0.609866 # Table walker pending requests distribution 442system.cpu0.dtb.walker.walksPending::stdev 0.537961 # Table walker pending requests distribution 443system.cpu0.dtb.walker.walksPending::0-1 512309669252 99.80% 99.80% # Table walker pending requests distribution 444system.cpu0.dtb.walker.walksPending::2-3 522001000 0.10% 99.90% # Table walker pending requests distribution 445system.cpu0.dtb.walker.walksPending::4-5 221126000 0.04% 99.94% # Table walker pending requests distribution 446system.cpu0.dtb.walker.walksPending::6-7 109873500 0.02% 99.97% # Table walker pending requests distribution 447system.cpu0.dtb.walker.walksPending::8-9 86703000 0.02% 99.98% # Table walker pending requests distribution 448system.cpu0.dtb.walker.walksPending::10-11 51185000 0.01% 99.99% # Table walker pending requests distribution 449system.cpu0.dtb.walker.walksPending::12-13 14405500 0.00% 100.00% # Table walker pending requests distribution 450system.cpu0.dtb.walker.walksPending::14-15 21121500 0.00% 100.00% # Table walker pending requests distribution 451system.cpu0.dtb.walker.walksPending::16-17 397500 0.00% 100.00% # Table walker pending requests distribution 452system.cpu0.dtb.walker.walksPending::18-19 10500 0.00% 100.00% # Table walker pending requests distribution 453system.cpu0.dtb.walker.walksPending::total 513336492752 # Table walker pending requests distribution 454system.cpu0.dtb.walker.walkPageSizes::4K 79785 88.44% 88.44% # Table walker page sizes translated 455system.cpu0.dtb.walker.walkPageSizes::2M 10426 11.56% 100.00% # Table walker page sizes translated 456system.cpu0.dtb.walker.walkPageSizes::total 90211 # Table walker page sizes translated 457system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 530338 # Table walker requests started/completed, data/inst 458system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 459system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 530338 # Table walker requests started/completed, data/inst 460system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 90211 # Table walker requests started/completed, data/inst 461system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 462system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 90211 # Table walker requests started/completed, data/inst 463system.cpu0.dtb.walker.walkRequestOrigin::total 620549 # Table walker requests started/completed, data/inst 464system.cpu0.dtb.inst_hits 0 # ITB inst hits 465system.cpu0.dtb.inst_misses 0 # ITB inst misses 466system.cpu0.dtb.read_hits 99690232 # DTB read hits 467system.cpu0.dtb.read_misses 367422 # DTB read misses 468system.cpu0.dtb.write_hits 83046551 # DTB write hits 469system.cpu0.dtb.write_misses 162916 # DTB write misses 470system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 471system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 472system.cpu0.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID 473system.cpu0.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID
474system.cpu0.dtb.flush_entries 35541 # Number of entries that have been flushed from TLB	474system.cpu0.dtb.flush_entries 35477 # Number of entries that have been flushed from TLB
475system.cpu0.dtb.align_faults 482 # Number of TLB faults due to alignment restrictions 476system.cpu0.dtb.prefetch_faults 6442 # Number of TLB faults due to prefetch 477system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 478system.cpu0.dtb.perms_faults 39704 # Number of TLB faults due to permissions restrictions 479system.cpu0.dtb.read_accesses 100057654 # DTB read accesses 480system.cpu0.dtb.write_accesses 83209467 # DTB write accesses 481system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 482system.cpu0.dtb.hits 182736783 # DTB hits 483system.cpu0.dtb.misses 530338 # DTB misses 484system.cpu0.dtb.accesses 183267121 # DTB accesses 485system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 486system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 489system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 490system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 491system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 492system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 493system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 494system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 495system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 496system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 497system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 498system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 499system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 500system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 501system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 502system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 503system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 504system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 505system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 506system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 507system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 508system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 509system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 510system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 511system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 512system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 513system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 514system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 515system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 516system.cpu0.itb.walker.walks 81834 # Table walker walks requested 517system.cpu0.itb.walker.walksLong 81834 # Table walker walks initiated with long descriptors 518system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1030 # Level at which table walker walks with long descriptors terminate 519system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58824 # Level at which table walker walks with long descriptors terminate 520system.cpu0.itb.walker.walksSquashedBefore 9805 # Table walks squashed before starting 521system.cpu0.itb.walker.walkWaitTime::samples 72029 # Table walker wait (enqueue to first request) latency 522system.cpu0.itb.walker.walkWaitTime::mean 864.033931 # Table walker wait (enqueue to first request) latency 523system.cpu0.itb.walker.walkWaitTime::stdev 6165.525550 # Table walker wait (enqueue to first request) latency 524system.cpu0.itb.walker.walkWaitTime::0-32767 71606 99.41% 99.41% # Table walker wait (enqueue to first request) latency 525system.cpu0.itb.walker.walkWaitTime::32768-65535 296 0.41% 99.82% # Table walker wait (enqueue to first request) latency 526system.cpu0.itb.walker.walkWaitTime::65536-98303 49 0.07% 99.89% # Table walker wait (enqueue to first request) latency 527system.cpu0.itb.walker.walkWaitTime::98304-131071 70 0.10% 99.99% # Table walker wait (enqueue to first request) latency 528system.cpu0.itb.walker.walkWaitTime::131072-163839 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 529system.cpu0.itb.walker.walkWaitTime::163840-196607 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency 530system.cpu0.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 531system.cpu0.itb.walker.walkWaitTime::229376-262143 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 532system.cpu0.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 533system.cpu0.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 534system.cpu0.itb.walker.walkWaitTime::total 72029 # Table walker wait (enqueue to first request) latency 535system.cpu0.itb.walker.walkCompletionTime::samples 69659 # Table walker service (enqueue to completion) latency 536system.cpu0.itb.walker.walkCompletionTime::mean 23684.893553 # Table walker service (enqueue to completion) latency 537system.cpu0.itb.walker.walkCompletionTime::gmean 21955.996989 # Table walker service (enqueue to completion) latency 538system.cpu0.itb.walker.walkCompletionTime::stdev 12765.700584 # Table walker service (enqueue to completion) latency 539system.cpu0.itb.walker.walkCompletionTime::0-32767 63811 91.60% 91.60% # Table walker service (enqueue to completion) latency 540system.cpu0.itb.walker.walkCompletionTime::32768-65535 5242 7.53% 99.13% # Table walker service (enqueue to completion) latency 541system.cpu0.itb.walker.walkCompletionTime::65536-98303 100 0.14% 99.27% # Table walker service (enqueue to completion) latency 542system.cpu0.itb.walker.walkCompletionTime::98304-131071 402 0.58% 99.85% # Table walker service (enqueue to completion) latency 543system.cpu0.itb.walker.walkCompletionTime::131072-163839 39 0.06% 99.91% # Table walker service (enqueue to completion) latency 544system.cpu0.itb.walker.walkCompletionTime::163840-196607 17 0.02% 99.93% # Table walker service (enqueue to completion) latency 545system.cpu0.itb.walker.walkCompletionTime::196608-229375 16 0.02% 99.95% # Table walker service (enqueue to completion) latency 546system.cpu0.itb.walker.walkCompletionTime::229376-262143 8 0.01% 99.97% # Table walker service (enqueue to completion) latency 547system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency 548system.cpu0.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.98% # Table walker service (enqueue to completion) latency 549system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 550system.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency 551system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 552system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 553system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 554system.cpu0.itb.walker.walkCompletionTime::total 69659 # Table walker service (enqueue to completion) latency 555system.cpu0.itb.walker.walksPending::samples 375894589280 # Table walker pending requests distribution 556system.cpu0.itb.walker.walksPending::mean 0.860066 # Table walker pending requests distribution 557system.cpu0.itb.walker.walksPending::stdev 0.347066 # Table walker pending requests distribution 558system.cpu0.itb.walker.walksPending::0 52618427692 14.00% 14.00% # Table walker pending requests distribution 559system.cpu0.itb.walker.walksPending::1 323259257588 86.00% 100.00% # Table walker pending requests distribution 560system.cpu0.itb.walker.walksPending::2 15893500 0.00% 100.00% # Table walker pending requests distribution 561system.cpu0.itb.walker.walksPending::3 943500 0.00% 100.00% # Table walker pending requests distribution 562system.cpu0.itb.walker.walksPending::4 54500 0.00% 100.00% # Table walker pending requests distribution 563system.cpu0.itb.walker.walksPending::5 12500 0.00% 100.00% # Table walker pending requests distribution 564system.cpu0.itb.walker.walksPending::total 375894589280 # Table walker pending requests distribution 565system.cpu0.itb.walker.walkPageSizes::4K 58824 98.28% 98.28% # Table walker page sizes translated 566system.cpu0.itb.walker.walkPageSizes::2M 1030 1.72% 100.00% # Table walker page sizes translated 567system.cpu0.itb.walker.walkPageSizes::total 59854 # Table walker page sizes translated 568system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 569system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 81834 # Table walker requests started/completed, data/inst 570system.cpu0.itb.walker.walkRequestOrigin_Requested::total 81834 # Table walker requests started/completed, data/inst 571system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 572system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59854 # Table walker requests started/completed, data/inst 573system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59854 # Table walker requests started/completed, data/inst 574system.cpu0.itb.walker.walkRequestOrigin::total 141688 # Table walker requests started/completed, data/inst 575system.cpu0.itb.inst_hits 216521473 # ITB inst hits 576system.cpu0.itb.inst_misses 81834 # ITB inst misses 577system.cpu0.itb.read_hits 0 # DTB read hits 578system.cpu0.itb.read_misses 0 # DTB read misses 579system.cpu0.itb.write_hits 0 # DTB write hits 580system.cpu0.itb.write_misses 0 # DTB write misses 581system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 582system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 583system.cpu0.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID 584system.cpu0.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID	475system.cpu0.dtb.align_faults 482 # Number of TLB faults due to alignment restrictions 476system.cpu0.dtb.prefetch_faults 6442 # Number of TLB faults due to prefetch 477system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 478system.cpu0.dtb.perms_faults 39704 # Number of TLB faults due to permissions restrictions 479system.cpu0.dtb.read_accesses 100057654 # DTB read accesses 480system.cpu0.dtb.write_accesses 83209467 # DTB write accesses 481system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 482system.cpu0.dtb.hits 182736783 # DTB hits 483system.cpu0.dtb.misses 530338 # DTB misses 484system.cpu0.dtb.accesses 183267121 # DTB accesses 485system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 486system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 489system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 490system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 491system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 492system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 493system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 494system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 495system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 496system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 497system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 498system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 499system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 500system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 501system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 502system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 503system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 504system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 505system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 506system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 507system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 508system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 509system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 510system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 511system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 512system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 513system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 514system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 515system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 516system.cpu0.itb.walker.walks 81834 # Table walker walks requested 517system.cpu0.itb.walker.walksLong 81834 # Table walker walks initiated with long descriptors 518system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1030 # Level at which table walker walks with long descriptors terminate 519system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58824 # Level at which table walker walks with long descriptors terminate 520system.cpu0.itb.walker.walksSquashedBefore 9805 # Table walks squashed before starting 521system.cpu0.itb.walker.walkWaitTime::samples 72029 # Table walker wait (enqueue to first request) latency 522system.cpu0.itb.walker.walkWaitTime::mean 864.033931 # Table walker wait (enqueue to first request) latency 523system.cpu0.itb.walker.walkWaitTime::stdev 6165.525550 # Table walker wait (enqueue to first request) latency 524system.cpu0.itb.walker.walkWaitTime::0-32767 71606 99.41% 99.41% # Table walker wait (enqueue to first request) latency 525system.cpu0.itb.walker.walkWaitTime::32768-65535 296 0.41% 99.82% # Table walker wait (enqueue to first request) latency 526system.cpu0.itb.walker.walkWaitTime::65536-98303 49 0.07% 99.89% # Table walker wait (enqueue to first request) latency 527system.cpu0.itb.walker.walkWaitTime::98304-131071 70 0.10% 99.99% # Table walker wait (enqueue to first request) latency 528system.cpu0.itb.walker.walkWaitTime::131072-163839 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 529system.cpu0.itb.walker.walkWaitTime::163840-196607 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency 530system.cpu0.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 531system.cpu0.itb.walker.walkWaitTime::229376-262143 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 532system.cpu0.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 533system.cpu0.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 534system.cpu0.itb.walker.walkWaitTime::total 72029 # Table walker wait (enqueue to first request) latency 535system.cpu0.itb.walker.walkCompletionTime::samples 69659 # Table walker service (enqueue to completion) latency 536system.cpu0.itb.walker.walkCompletionTime::mean 23684.893553 # Table walker service (enqueue to completion) latency 537system.cpu0.itb.walker.walkCompletionTime::gmean 21955.996989 # Table walker service (enqueue to completion) latency 538system.cpu0.itb.walker.walkCompletionTime::stdev 12765.700584 # Table walker service (enqueue to completion) latency 539system.cpu0.itb.walker.walkCompletionTime::0-32767 63811 91.60% 91.60% # Table walker service (enqueue to completion) latency 540system.cpu0.itb.walker.walkCompletionTime::32768-65535 5242 7.53% 99.13% # Table walker service (enqueue to completion) latency 541system.cpu0.itb.walker.walkCompletionTime::65536-98303 100 0.14% 99.27% # Table walker service (enqueue to completion) latency 542system.cpu0.itb.walker.walkCompletionTime::98304-131071 402 0.58% 99.85% # Table walker service (enqueue to completion) latency 543system.cpu0.itb.walker.walkCompletionTime::131072-163839 39 0.06% 99.91% # Table walker service (enqueue to completion) latency 544system.cpu0.itb.walker.walkCompletionTime::163840-196607 17 0.02% 99.93% # Table walker service (enqueue to completion) latency 545system.cpu0.itb.walker.walkCompletionTime::196608-229375 16 0.02% 99.95% # Table walker service (enqueue to completion) latency 546system.cpu0.itb.walker.walkCompletionTime::229376-262143 8 0.01% 99.97% # Table walker service (enqueue to completion) latency 547system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency 548system.cpu0.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.98% # Table walker service (enqueue to completion) latency 549system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 550system.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency 551system.cpu0.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 552system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 553system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 554system.cpu0.itb.walker.walkCompletionTime::total 69659 # Table walker service (enqueue to completion) latency 555system.cpu0.itb.walker.walksPending::samples 375894589280 # Table walker pending requests distribution 556system.cpu0.itb.walker.walksPending::mean 0.860066 # Table walker pending requests distribution 557system.cpu0.itb.walker.walksPending::stdev 0.347066 # Table walker pending requests distribution 558system.cpu0.itb.walker.walksPending::0 52618427692 14.00% 14.00% # Table walker pending requests distribution 559system.cpu0.itb.walker.walksPending::1 323259257588 86.00% 100.00% # Table walker pending requests distribution 560system.cpu0.itb.walker.walksPending::2 15893500 0.00% 100.00% # Table walker pending requests distribution 561system.cpu0.itb.walker.walksPending::3 943500 0.00% 100.00% # Table walker pending requests distribution 562system.cpu0.itb.walker.walksPending::4 54500 0.00% 100.00% # Table walker pending requests distribution 563system.cpu0.itb.walker.walksPending::5 12500 0.00% 100.00% # Table walker pending requests distribution 564system.cpu0.itb.walker.walksPending::total 375894589280 # Table walker pending requests distribution 565system.cpu0.itb.walker.walkPageSizes::4K 58824 98.28% 98.28% # Table walker page sizes translated 566system.cpu0.itb.walker.walkPageSizes::2M 1030 1.72% 100.00% # Table walker page sizes translated 567system.cpu0.itb.walker.walkPageSizes::total 59854 # Table walker page sizes translated 568system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 569system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 81834 # Table walker requests started/completed, data/inst 570system.cpu0.itb.walker.walkRequestOrigin_Requested::total 81834 # Table walker requests started/completed, data/inst 571system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 572system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59854 # Table walker requests started/completed, data/inst 573system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59854 # Table walker requests started/completed, data/inst 574system.cpu0.itb.walker.walkRequestOrigin::total 141688 # Table walker requests started/completed, data/inst 575system.cpu0.itb.inst_hits 216521473 # ITB inst hits 576system.cpu0.itb.inst_misses 81834 # ITB inst misses 577system.cpu0.itb.read_hits 0 # DTB read hits 578system.cpu0.itb.read_misses 0 # DTB read misses 579system.cpu0.itb.write_hits 0 # DTB write hits 580system.cpu0.itb.write_misses 0 # DTB write misses 581system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 582system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 583system.cpu0.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID 584system.cpu0.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID
585system.cpu0.itb.flush_entries 25342 # Number of entries that have been flushed from TLB	585system.cpu0.itb.flush_entries 25278 # Number of entries that have been flushed from TLB
586system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 587system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 588system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 589system.cpu0.itb.perms_faults 198402 # Number of TLB faults due to permissions restrictions 590system.cpu0.itb.read_accesses 0 # DTB read accesses 591system.cpu0.itb.write_accesses 0 # DTB write accesses 592system.cpu0.itb.inst_accesses 216603307 # ITB inst accesses 593system.cpu0.itb.hits 216521473 # DTB hits 594system.cpu0.itb.misses 81834 # DTB misses 595system.cpu0.itb.accesses 216603307 # DTB accesses 596system.cpu0.numPwrStateTransitions 26480 # Number of power state transitions 597system.cpu0.pwrStateClkGateDist::samples 13240 # Distribution of time spent in the clock gated state 598system.cpu0.pwrStateClkGateDist::mean 3550703383.143278 # Distribution of time spent in the clock gated state 599system.cpu0.pwrStateClkGateDist::stdev 88629328460.442917 # Distribution of time spent in the clock gated state 600system.cpu0.pwrStateClkGateDist::underflows 3078 23.25% 23.25% # Distribution of time spent in the clock gated state 601system.cpu0.pwrStateClkGateDist::1000-5e+10 10135 76.55% 99.80% # Distribution of time spent in the clock gated state 602system.cpu0.pwrStateClkGateDist::5e+10-1e+11 4 0.03% 99.83% # Distribution of time spent in the clock gated state 603system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state 604system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state 605system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state 606system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 607system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 608system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 609system.cpu0.pwrStateClkGateDist::8e+11-8.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 610system.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state 611system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 612system.cpu0.pwrStateClkGateDist::max_value 7390881192332 # Distribution of time spent in the clock gated state 613system.cpu0.pwrStateClkGateDist::total 13240 # Distribution of time spent in the clock gated state 614system.cpu0.pwrStateResidencyTicks::ON 373002370183 # Cumulative time (in ticks) in various power states 615system.cpu0.pwrStateResidencyTicks::CLK_GATED 47011312792817 # Cumulative time (in ticks) in various power states 616system.cpu0.numCycles 746014900 # number of cpu cycles simulated 617system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 618system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 619system.cpu0.fetch.icacheStallCycles 90433879 # Number of cycles fetch is stalled on an Icache miss 620system.cpu0.fetch.Insts 610172736 # Number of instructions fetch has processed 621system.cpu0.fetch.Branches 138091637 # Number of branches that fetch encountered 622system.cpu0.fetch.predictedBranches 81258280 # Number of branches that fetch has predicted taken 623system.cpu0.fetch.Cycles 615398287 # Number of cycles fetch has run and was not squashing or blocked 624system.cpu0.fetch.SquashCycles 14620490 # Number of cycles fetch has spent squashing 625system.cpu0.fetch.TlbCycles 1715297 # Number of cycles fetch has spent waiting for tlb 626system.cpu0.fetch.MiscStallCycles 295776 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 627system.cpu0.fetch.PendingTrapStallCycles 5589619 # Number of stall cycles due to pending traps 628system.cpu0.fetch.PendingQuiesceStallCycles 711520 # Number of stall cycles due to pending quiesce instructions 629system.cpu0.fetch.IcacheWaitRetryStallCycles 813110 # Number of stall cycles due to full MSHR 630system.cpu0.fetch.CacheLines 216323861 # Number of cache lines fetched 631system.cpu0.fetch.IcacheSquashes 1696724 # Number of outstanding Icache misses that were squashed 632system.cpu0.fetch.ItlbSquashes 26704 # Number of outstanding ITLB misses that were squashed 633system.cpu0.fetch.rateDist::samples 722267733 # Number of instructions fetched each cycle (Total) 634system.cpu0.fetch.rateDist::mean 0.989116 # Number of instructions fetched each cycle (Total) 635system.cpu0.fetch.rateDist::stdev 1.222569 # Number of instructions fetched each cycle (Total) 636system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 637system.cpu0.fetch.rateDist::0 380266002 52.65% 52.65% # Number of instructions fetched each cycle (Total) 638system.cpu0.fetch.rateDist::1 133082578 18.43% 71.07% # Number of instructions fetched each cycle (Total) 639system.cpu0.fetch.rateDist::2 45433566 6.29% 77.36% # Number of instructions fetched each cycle (Total) 640system.cpu0.fetch.rateDist::3 163485587 22.64% 100.00% # Number of instructions fetched each cycle (Total) 641system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 642system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 643system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 644system.cpu0.fetch.rateDist::total 722267733 # Number of instructions fetched each cycle (Total) 645system.cpu0.fetch.branchRate 0.185106 # Number of branch fetches per cycle 646system.cpu0.fetch.rate 0.817910 # Number of inst fetches per cycle 647system.cpu0.decode.IdleCycles 106050198 # Number of cycles decode is idle 648system.cpu0.decode.BlockedCycles 344087060 # Number of cycles decode is blocked 649system.cpu0.decode.RunCycles 231125881 # Number of cycles decode is running 650system.cpu0.decode.UnblockCycles 35774912 # Number of cycles decode is unblocking 651system.cpu0.decode.SquashCycles 5229682 # Number of cycles decode is squashing 652system.cpu0.decode.BranchResolved 19752919 # Number of times decode resolved a branch 653system.cpu0.decode.BranchMispred 2120005 # Number of times decode detected a branch misprediction 654system.cpu0.decode.DecodedInsts 632519077 # Number of instructions handled by decode 655system.cpu0.decode.SquashedInsts 23747295 # Number of squashed instructions handled by decode 656system.cpu0.rename.SquashCycles 5229682 # Number of cycles rename is squashing 657system.cpu0.rename.IdleCycles 140879480 # Number of cycles rename is idle 658system.cpu0.rename.BlockCycles 46445701 # Number of cycles rename is blocking 659system.cpu0.rename.serializeStallCycles 235545365 # count of cycles rename stalled for serializing inst 660system.cpu0.rename.RunCycles 231642525 # Number of cycles rename is running 661system.cpu0.rename.UnblockCycles 62524980 # Number of cycles rename is unblocking 662system.cpu0.rename.RenamedInsts 614970268 # Number of instructions processed by rename 663system.cpu0.rename.SquashedInsts 6274841 # Number of squashed instructions processed by rename 664system.cpu0.rename.ROBFullEvents 9683853 # Number of times rename has blocked due to ROB full 665system.cpu0.rename.IQFullEvents 239254 # Number of times rename has blocked due to IQ full 666system.cpu0.rename.LQFullEvents 254272 # Number of times rename has blocked due to LQ full 667system.cpu0.rename.SQFullEvents 29219197 # Number of times rename has blocked due to SQ full 668system.cpu0.rename.FullRegisterEvents 11058 # Number of times there has been no free registers 669system.cpu0.rename.RenamedOperands 585821211 # Number of destination operands rename has renamed 670system.cpu0.rename.RenameLookups 944611426 # Number of register rename lookups that rename has made 671system.cpu0.rename.int_rename_lookups 725501320 # Number of integer rename lookups 672system.cpu0.rename.fp_rename_lookups 860588 # Number of floating rename lookups 673system.cpu0.rename.CommittedMaps 527918401 # Number of HB maps that are committed 674system.cpu0.rename.UndoneMaps 57902804 # Number of HB maps that are undone due to squashing 675system.cpu0.rename.serializingInsts 14873386 # count of serializing insts renamed 676system.cpu0.rename.tempSerializingInsts 12932012 # count of temporary serializing insts renamed 677system.cpu0.rename.skidInsts 72326353 # count of insts added to the skid buffer 678system.cpu0.memDep0.insertedLoads 100125445 # Number of loads inserted to the mem dependence unit. 679system.cpu0.memDep0.insertedStores 86327833 # Number of stores inserted to the mem dependence unit. 680system.cpu0.memDep0.conflictingLoads 8833111 # Number of conflicting loads. 681system.cpu0.memDep0.conflictingStores 7713299 # Number of conflicting stores. 682system.cpu0.iq.iqInstsAdded 593239093 # Number of instructions added to the IQ (excludes non-spec) 683system.cpu0.iq.iqNonSpecInstsAdded 14925406 # Number of non-speculative instructions added to the IQ 684system.cpu0.iq.iqInstsIssued 596650262 # Number of instructions issued 685system.cpu0.iq.iqSquashedInstsIssued 2740149 # Number of squashed instructions issued 686system.cpu0.iq.iqSquashedInstsExamined 54305512 # Number of squashed instructions iterated over during squash; mainly for profiling 687system.cpu0.iq.iqSquashedOperandsExamined 35087941 # Number of squashed operands that are examined and possibly removed from graph 688system.cpu0.iq.iqSquashedNonSpecRemoved 259840 # Number of squashed non-spec instructions that were removed 689system.cpu0.iq.issued_per_cycle::samples 722267733 # Number of insts issued each cycle 690system.cpu0.iq.issued_per_cycle::mean 0.826079 # Number of insts issued each cycle 691system.cpu0.iq.issued_per_cycle::stdev 1.071801 # Number of insts issued each cycle 692system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 693system.cpu0.iq.issued_per_cycle::0 398653423 55.19% 55.19% # Number of insts issued each cycle 694system.cpu0.iq.issued_per_cycle::1 132668388 18.37% 73.56% # Number of insts issued each cycle 695system.cpu0.iq.issued_per_cycle::2 116695962 16.16% 89.72% # Number of insts issued each cycle 696system.cpu0.iq.issued_per_cycle::3 66414173 9.20% 98.92% # Number of insts issued each cycle 697system.cpu0.iq.issued_per_cycle::4 7831504 1.08% 100.00% # Number of insts issued each cycle 698system.cpu0.iq.issued_per_cycle::5 4283 0.00% 100.00% # Number of insts issued each cycle 699system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 700system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 701system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 702system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 703system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 704system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 705system.cpu0.iq.issued_per_cycle::total 722267733 # Number of insts issued each cycle 706system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 707system.cpu0.iq.fu_full::IntAlu 62572261 45.86% 45.86% # attempts to use FU when none available 708system.cpu0.iq.fu_full::IntMult 47637 0.03% 45.89% # attempts to use FU when none available 709system.cpu0.iq.fu_full::IntDiv 27538 0.02% 45.91% # attempts to use FU when none available 710system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.91% # attempts to use FU when none available 711system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.91% # attempts to use FU when none available 712system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.91% # attempts to use FU when none available 713system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.91% # attempts to use FU when none available 714system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.91% # attempts to use FU when none available 715system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.91% # attempts to use FU when none available 716system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.91% # attempts to use FU when none available 717system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.91% # attempts to use FU when none available 718system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.91% # attempts to use FU when none available 719system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.91% # attempts to use FU when none available 720system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.91% # attempts to use FU when none available 721system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.91% # attempts to use FU when none available 722system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.91% # attempts to use FU when none available 723system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.91% # attempts to use FU when none available 724system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.91% # attempts to use FU when none available 725system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.91% # attempts to use FU when none available 726system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.91% # attempts to use FU when none available 727system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.91% # attempts to use FU when none available 728system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.91% # attempts to use FU when none available 729system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.91% # attempts to use FU when none available 730system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.91% # attempts to use FU when none available 731system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.91% # attempts to use FU when none available 732system.cpu0.iq.fu_full::SimdFloatMisc 12 0.00% 45.91% # attempts to use FU when none available 733system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.91% # attempts to use FU when none available 734system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.91% # attempts to use FU when none available 735system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.91% # attempts to use FU when none available 736system.cpu0.iq.fu_full::MemRead 35025206 25.67% 71.58% # attempts to use FU when none available 737system.cpu0.iq.fu_full::MemWrite 38780691 28.42% 100.00% # attempts to use FU when none available 738system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 739system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 740system.cpu0.iq.FU_type_0::No_OpClass 37 0.00% 0.00% # Type of FU issued 741system.cpu0.iq.FU_type_0::IntAlu 408003074 68.38% 68.38% # Type of FU issued 742system.cpu0.iq.FU_type_0::IntMult 1391206 0.23% 68.62% # Type of FU issued 743system.cpu0.iq.FU_type_0::IntDiv 75246 0.01% 68.63% # Type of FU issued 744system.cpu0.iq.FU_type_0::FloatAdd 5 0.00% 68.63% # Type of FU issued 745system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.63% # Type of FU issued 746system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.63% # Type of FU issued 747system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.63% # Type of FU issued 748system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.63% # Type of FU issued 749system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.63% # Type of FU issued 750system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.63% # Type of FU issued 751system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.63% # Type of FU issued 752system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.63% # Type of FU issued 753system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.63% # Type of FU issued 754system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.63% # Type of FU issued 755system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.63% # Type of FU issued 756system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.63% # Type of FU issued 757system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.63% # Type of FU issued 758system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.63% # Type of FU issued 759system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.63% # Type of FU issued 760system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.63% # Type of FU issued 761system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.63% # Type of FU issued 762system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.63% # Type of FU issued 763system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.63% # Type of FU issued 764system.cpu0.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.63% # Type of FU issued 765system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.63% # Type of FU issued 766system.cpu0.iq.FU_type_0::SimdFloatMisc 75513 0.01% 68.64% # Type of FU issued 767system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.64% # Type of FU issued 768system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.64% # Type of FU issued 769system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.64% # Type of FU issued 770system.cpu0.iq.FU_type_0::MemRead 102801955 17.23% 85.87% # Type of FU issued 771system.cpu0.iq.FU_type_0::MemWrite 84303178 14.13% 100.00% # Type of FU issued 772system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 773system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 774system.cpu0.iq.FU_type_0::total 596650262 # Type of FU issued 775system.cpu0.iq.rate 0.799783 # Inst issue rate 776system.cpu0.iq.fu_busy_cnt 136453345 # FU busy when requested 777system.cpu0.iq.fu_busy_rate 0.228699 # FU busy rate (busy events/executed inst) 778system.cpu0.iq.int_inst_queue_reads 2053360508 # Number of integer instruction queue reads 779system.cpu0.iq.int_inst_queue_writes 662051351 # Number of integer instruction queue writes 780system.cpu0.iq.int_inst_queue_wakeup_accesses 579495604 # Number of integer instruction queue wakeup accesses 781system.cpu0.iq.fp_inst_queue_reads 1401241 # Number of floating instruction queue reads 782system.cpu0.iq.fp_inst_queue_writes 556367 # Number of floating instruction queue writes 783system.cpu0.iq.fp_inst_queue_wakeup_accesses 521179 # Number of floating instruction queue wakeup accesses 784system.cpu0.iq.int_alu_accesses 732235238 # Number of integer alu accesses 785system.cpu0.iq.fp_alu_accesses 868332 # Number of floating point alu accesses 786system.cpu0.iew.lsq.thread0.forwLoads 2674563 # Number of loads that had data forwarded from stores 787system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 788system.cpu0.iew.lsq.thread0.squashedLoads 12322480 # Number of loads squashed 789system.cpu0.iew.lsq.thread0.ignoredResponses 16225 # Number of memory responses ignored because the instruction is squashed 790system.cpu0.iew.lsq.thread0.memOrderViolation 138716 # Number of memory ordering violations 791system.cpu0.iew.lsq.thread0.squashedStores 5498195 # Number of stores squashed 792system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 793system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 794system.cpu0.iew.lsq.thread0.rescheduledLoads 2627025 # Number of loads that were rescheduled 795system.cpu0.iew.lsq.thread0.cacheBlocked 4349073 # Number of times an access to memory failed due to the cache being blocked 796system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 797system.cpu0.iew.iewSquashCycles 5229682 # Number of cycles IEW is squashing 798system.cpu0.iew.iewBlockCycles 6015766 # Number of cycles IEW is blocking 799system.cpu0.iew.iewUnblockCycles 1577054 # Number of cycles IEW is unblocking 800system.cpu0.iew.iewDispatchedInsts 608291813 # Number of instructions dispatched to IQ 801system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 802system.cpu0.iew.iewDispLoadInsts 100125445 # Number of dispatched load instructions 803system.cpu0.iew.iewDispStoreInsts 86327833 # Number of dispatched store instructions 804system.cpu0.iew.iewDispNonSpecInsts 12661031 # Number of dispatched non-speculative instructions 805system.cpu0.iew.iewIQFullEvents 57348 # Number of times the IQ has become full, causing a stall 806system.cpu0.iew.iewLSQFullEvents 1462300 # Number of times the LSQ has become full, causing a stall 807system.cpu0.iew.memOrderViolationEvents 138716 # Number of memory order violations 808system.cpu0.iew.predictedTakenIncorrect 1920652 # Number of branches that were predicted taken incorrectly 809system.cpu0.iew.predictedNotTakenIncorrect 3139987 # Number of branches that were predicted not taken incorrectly 810system.cpu0.iew.branchMispredicts 5060639 # Number of branch mispredicts detected at execute 811system.cpu0.iew.iewExecutedInsts 588583301 # Number of executed instructions 812system.cpu0.iew.iewExecLoadInsts 99681195 # Number of load instructions executed 813system.cpu0.iew.iewExecSquashedInsts 7546532 # Number of squashed instructions skipped in execute 814system.cpu0.iew.exec_swp 0 # number of swp insts executed 815system.cpu0.iew.exec_nop 127314 # number of nop insts executed 816system.cpu0.iew.exec_refs 182727665 # number of memory reference insts executed 817system.cpu0.iew.exec_branches 110905985 # Number of branches executed 818system.cpu0.iew.exec_stores 83046470 # Number of stores executed 819system.cpu0.iew.exec_rate 0.788970 # Inst execution rate 820system.cpu0.iew.wb_sent 580785082 # cumulative count of insts sent to commit 821system.cpu0.iew.wb_count 580016783 # cumulative count of insts written-back 822system.cpu0.iew.wb_producers 281571835 # num instructions producing a value 823system.cpu0.iew.wb_consumers 462036259 # num instructions consuming a value 824system.cpu0.iew.wb_rate 0.777487 # insts written-back per cycle 825system.cpu0.iew.wb_fanout 0.609415 # average fanout of values written-back 826system.cpu0.commit.commitSquashedInsts 47239068 # The number of squashed insts skipped by commit 827system.cpu0.commit.commitNonSpecStalls 14665566 # The number of times commit has been forced to stall to communicate backwards 828system.cpu0.commit.branchMispredicts 4709377 # The number of times a branch was mispredicted 829system.cpu0.commit.committed_per_cycle::samples 713265593 # Number of insts commited each cycle 830system.cpu0.commit.committed_per_cycle::mean 0.776512 # Number of insts commited each cycle 831system.cpu0.commit.committed_per_cycle::stdev 1.575400 # Number of insts commited each cycle 832system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 833system.cpu0.commit.committed_per_cycle::0 472345396 66.22% 66.22% # Number of insts commited each cycle 834system.cpu0.commit.committed_per_cycle::1 122854697 17.22% 83.45% # Number of insts commited each cycle 835system.cpu0.commit.committed_per_cycle::2 54352038 7.62% 91.07% # Number of insts commited each cycle 836system.cpu0.commit.committed_per_cycle::3 18530727 2.60% 93.67% # Number of insts commited each cycle 837system.cpu0.commit.committed_per_cycle::4 13156863 1.84% 95.51% # Number of insts commited each cycle 838system.cpu0.commit.committed_per_cycle::5 8843989 1.24% 96.75% # Number of insts commited each cycle 839system.cpu0.commit.committed_per_cycle::6 5973723 0.84% 97.59% # Number of insts commited each cycle 840system.cpu0.commit.committed_per_cycle::7 3646989 0.51% 98.10% # Number of insts commited each cycle 841system.cpu0.commit.committed_per_cycle::8 13561171 1.90% 100.00% # Number of insts commited each cycle 842system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 843system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 844system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 845system.cpu0.commit.committed_per_cycle::total 713265593 # Number of insts commited each cycle 846system.cpu0.commit.committedInsts 471410910 # Number of instructions committed 847system.cpu0.commit.committedOps 553858980 # Number of ops (including micro ops) committed 848system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 849system.cpu0.commit.refs 168632602 # Number of memory references committed 850system.cpu0.commit.loads 87802964 # Number of loads committed 851system.cpu0.commit.membars 3653468 # Number of memory barriers committed 852system.cpu0.commit.branches 105429162 # Number of branches committed 853system.cpu0.commit.fp_insts 512997 # Number of committed floating point instructions. 854system.cpu0.commit.int_insts 508174699 # Number of committed integer instructions. 855system.cpu0.commit.function_calls 13889214 # Number of function calls committed. 856system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 857system.cpu0.commit.op_class_0::IntAlu 383941234 69.32% 69.32% # Class of committed instruction 858system.cpu0.commit.op_class_0::IntMult 1156077 0.21% 69.53% # Class of committed instruction 859system.cpu0.commit.op_class_0::IntDiv 59954 0.01% 69.54% # Class of committed instruction 860system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.54% # Class of committed instruction 861system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.54% # Class of committed instruction 862system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.54% # Class of committed instruction 863system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.54% # Class of committed instruction 864system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.54% # Class of committed instruction 865system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.54% # Class of committed instruction 866system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.54% # Class of committed instruction 867system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.54% # Class of committed instruction 868system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.54% # Class of committed instruction 869system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.54% # Class of committed instruction 870system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.54% # Class of committed instruction 871system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.54% # Class of committed instruction 872system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.54% # Class of committed instruction 873system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.54% # Class of committed instruction 874system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.54% # Class of committed instruction 875system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.54% # Class of committed instruction 876system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.54% # Class of committed instruction 877system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.54% # Class of committed instruction 878system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.54% # Class of committed instruction 879system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.54% # Class of committed instruction 880system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.54% # Class of committed instruction 881system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.54% # Class of committed instruction 882system.cpu0.commit.op_class_0::SimdFloatMisc 69071 0.01% 69.55% # Class of committed instruction 883system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.55% # Class of committed instruction 884system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.55% # Class of committed instruction 885system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.55% # Class of committed instruction 886system.cpu0.commit.op_class_0::MemRead 87802964 15.85% 85.41% # Class of committed instruction 887system.cpu0.commit.op_class_0::MemWrite 80829638 14.59% 100.00% # Class of committed instruction 888system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 889system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 890system.cpu0.commit.op_class_0::total 553858980 # Class of committed instruction 891system.cpu0.commit.bw_lim_events 13561171 # number cycles where commit BW limit reached 892system.cpu0.rob.rob_reads 1296549352 # The number of ROB reads 893system.cpu0.rob.rob_writes 1211163120 # The number of ROB writes 894system.cpu0.timesIdled 982435 # Number of times that the entire CPU went into an idle state and unscheduled itself 895system.cpu0.idleCycles 23747167 # Total number of cycles that the CPU has spent unscheduled due to idling 896system.cpu0.quiesceCycles 94022615466 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 897system.cpu0.committedInsts 471410910 # Number of Instructions Simulated 898system.cpu0.committedOps 553858980 # Number of Ops (including micro ops) Simulated 899system.cpu0.cpi 1.582515 # CPI: Cycles Per Instruction 900system.cpu0.cpi_total 1.582515 # CPI: Total CPI of All Threads 901system.cpu0.ipc 0.631905 # IPC: Instructions Per Cycle 902system.cpu0.ipc_total 0.631905 # IPC: Total IPC of All Threads 903system.cpu0.int_regfile_reads 694459704 # number of integer regfile reads 904system.cpu0.int_regfile_writes 413089219 # number of integer regfile writes 905system.cpu0.fp_regfile_reads 846069 # number of floating regfile reads 906system.cpu0.fp_regfile_writes 429660 # number of floating regfile writes 907system.cpu0.cc_regfile_reads 127998327 # number of cc regfile reads 908system.cpu0.cc_regfile_writes 128742208 # number of cc regfile writes 909system.cpu0.misc_regfile_reads 1288788249 # number of misc regfile reads 910system.cpu0.misc_regfile_writes 14832406 # number of misc regfile writes 911system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 912system.cpu0.dcache.tags.replacements 5793916 # number of replacements 913system.cpu0.dcache.tags.tagsinuse 505.305765 # Cycle average of tags in use 914system.cpu0.dcache.tags.total_refs 157106373 # Total number of references to valid blocks. 915system.cpu0.dcache.tags.sampled_refs 5794427 # Sample count of references to valid blocks. 916system.cpu0.dcache.tags.avg_refs 27.113358 # Average number of references to valid blocks. 917system.cpu0.dcache.tags.warmup_cycle 1908955000 # Cycle when the warmup percentage was hit. 918system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.305765 # Average occupied blocks per requestor 919system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986925 # Average percentage of cache occupancy 920system.cpu0.dcache.tags.occ_percent::total 0.986925 # Average percentage of cache occupancy 921system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 922system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 923system.cpu0.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id 924system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id 925system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 926system.cpu0.dcache.tags.tag_accesses 349540400 # Number of tag accesses 927system.cpu0.dcache.tags.data_accesses 349540400 # Number of data accesses 928system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 929system.cpu0.dcache.ReadReq_hits::cpu0.data 81616032 # number of ReadReq hits 930system.cpu0.dcache.ReadReq_hits::total 81616032 # number of ReadReq hits 931system.cpu0.dcache.WriteReq_hits::cpu0.data 70522769 # number of WriteReq hits 932system.cpu0.dcache.WriteReq_hits::total 70522769 # number of WriteReq hits 933system.cpu0.dcache.SoftPFReq_hits::cpu0.data 213045 # number of SoftPFReq hits 934system.cpu0.dcache.SoftPFReq_hits::total 213045 # number of SoftPFReq hits 935system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259663 # number of WriteLineReq hits 936system.cpu0.dcache.WriteLineReq_hits::total 259663 # number of WriteLineReq hits 937system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1810689 # number of LoadLockedReq hits 938system.cpu0.dcache.LoadLockedReq_hits::total 1810689 # number of LoadLockedReq hits 939system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1836259 # number of StoreCondReq hits 940system.cpu0.dcache.StoreCondReq_hits::total 1836259 # number of StoreCondReq hits 941system.cpu0.dcache.demand_hits::cpu0.data 152398464 # number of demand (read+write) hits 942system.cpu0.dcache.demand_hits::total 152398464 # number of demand (read+write) hits 943system.cpu0.dcache.overall_hits::cpu0.data 152611509 # number of overall hits 944system.cpu0.dcache.overall_hits::total 152611509 # number of overall hits 945system.cpu0.dcache.ReadReq_misses::cpu0.data 6448823 # number of ReadReq misses 946system.cpu0.dcache.ReadReq_misses::total 6448823 # number of ReadReq misses 947system.cpu0.dcache.WriteReq_misses::cpu0.data 7191873 # number of WriteReq misses 948system.cpu0.dcache.WriteReq_misses::total 7191873 # number of WriteReq misses 949system.cpu0.dcache.SoftPFReq_misses::cpu0.data 676181 # number of SoftPFReq misses 950system.cpu0.dcache.SoftPFReq_misses::total 676181 # number of SoftPFReq misses 951system.cpu0.dcache.WriteLineReq_misses::cpu0.data 810826 # number of WriteLineReq misses 952system.cpu0.dcache.WriteLineReq_misses::total 810826 # number of WriteLineReq misses 953system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 247493 # number of LoadLockedReq misses 954system.cpu0.dcache.LoadLockedReq_misses::total 247493 # number of LoadLockedReq misses 955system.cpu0.dcache.StoreCondReq_misses::cpu0.data 187335 # number of StoreCondReq misses 956system.cpu0.dcache.StoreCondReq_misses::total 187335 # number of StoreCondReq misses 957system.cpu0.dcache.demand_misses::cpu0.data 14451522 # number of demand (read+write) misses 958system.cpu0.dcache.demand_misses::total 14451522 # number of demand (read+write) misses 959system.cpu0.dcache.overall_misses::cpu0.data 15127703 # number of overall misses 960system.cpu0.dcache.overall_misses::total 15127703 # number of overall misses 961system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 92981912000 # number of ReadReq miss cycles 962system.cpu0.dcache.ReadReq_miss_latency::total 92981912000 # number of ReadReq miss cycles 963system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 133998931168 # number of WriteReq miss cycles 964system.cpu0.dcache.WriteReq_miss_latency::total 133998931168 # number of WriteReq miss cycles 965system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 29936196189 # number of WriteLineReq miss cycles 966system.cpu0.dcache.WriteLineReq_miss_latency::total 29936196189 # number of WriteLineReq miss cycles 967system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3415607500 # number of LoadLockedReq miss cycles 968system.cpu0.dcache.LoadLockedReq_miss_latency::total 3415607500 # number of LoadLockedReq miss cycles 969system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4687136000 # number of StoreCondReq miss cycles 970system.cpu0.dcache.StoreCondReq_miss_latency::total 4687136000 # number of StoreCondReq miss cycles 971system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3788500 # number of StoreCondFailReq miss cycles 972system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3788500 # number of StoreCondFailReq miss cycles 973system.cpu0.dcache.demand_miss_latency::cpu0.data 256917039357 # number of demand (read+write) miss cycles 974system.cpu0.dcache.demand_miss_latency::total 256917039357 # number of demand (read+write) miss cycles 975system.cpu0.dcache.overall_miss_latency::cpu0.data 256917039357 # number of overall miss cycles 976system.cpu0.dcache.overall_miss_latency::total 256917039357 # number of overall miss cycles 977system.cpu0.dcache.ReadReq_accesses::cpu0.data 88064855 # number of ReadReq accesses(hits+misses) 978system.cpu0.dcache.ReadReq_accesses::total 88064855 # number of ReadReq accesses(hits+misses) 979system.cpu0.dcache.WriteReq_accesses::cpu0.data 77714642 # number of WriteReq accesses(hits+misses) 980system.cpu0.dcache.WriteReq_accesses::total 77714642 # number of WriteReq accesses(hits+misses) 981system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 889226 # number of SoftPFReq accesses(hits+misses) 982system.cpu0.dcache.SoftPFReq_accesses::total 889226 # number of SoftPFReq accesses(hits+misses) 983system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1070489 # number of WriteLineReq accesses(hits+misses) 984system.cpu0.dcache.WriteLineReq_accesses::total 1070489 # number of WriteLineReq accesses(hits+misses) 985system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2058182 # number of LoadLockedReq accesses(hits+misses) 986system.cpu0.dcache.LoadLockedReq_accesses::total 2058182 # number of LoadLockedReq accesses(hits+misses) 987system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2023594 # number of StoreCondReq accesses(hits+misses) 988system.cpu0.dcache.StoreCondReq_accesses::total 2023594 # number of StoreCondReq accesses(hits+misses) 989system.cpu0.dcache.demand_accesses::cpu0.data 166849986 # number of demand (read+write) accesses 990system.cpu0.dcache.demand_accesses::total 166849986 # number of demand (read+write) accesses 991system.cpu0.dcache.overall_accesses::cpu0.data 167739212 # number of overall (read+write) accesses 992system.cpu0.dcache.overall_accesses::total 167739212 # number of overall (read+write) accesses 993system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.073228 # miss rate for ReadReq accesses 994system.cpu0.dcache.ReadReq_miss_rate::total 0.073228 # miss rate for ReadReq accesses 995system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.092542 # miss rate for WriteReq accesses 996system.cpu0.dcache.WriteReq_miss_rate::total 0.092542 # miss rate for WriteReq accesses 997system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760415 # miss rate for SoftPFReq accesses 998system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760415 # miss rate for SoftPFReq accesses 999system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.757435 # miss rate for WriteLineReq accesses 1000system.cpu0.dcache.WriteLineReq_miss_rate::total 0.757435 # miss rate for WriteLineReq accesses 1001system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.120248 # miss rate for LoadLockedReq accesses 1002system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.120248 # miss rate for LoadLockedReq accesses 1003system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.092575 # miss rate for StoreCondReq accesses 1004system.cpu0.dcache.StoreCondReq_miss_rate::total 0.092575 # miss rate for StoreCondReq accesses 1005system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086614 # miss rate for demand accesses 1006system.cpu0.dcache.demand_miss_rate::total 0.086614 # miss rate for demand accesses 1007system.cpu0.dcache.overall_miss_rate::cpu0.data 0.090186 # miss rate for overall accesses 1008system.cpu0.dcache.overall_miss_rate::total 0.090186 # miss rate for overall accesses 1009system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14418.431394 # average ReadReq miss latency 1010system.cpu0.dcache.ReadReq_avg_miss_latency::total 14418.431394 # average ReadReq miss latency 1011system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18631.993525 # average WriteReq miss latency 1012system.cpu0.dcache.WriteReq_avg_miss_latency::total 18631.993525 # average WriteReq miss latency 1013system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 36920.616987 # average WriteLineReq miss latency 1014system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 36920.616987 # average WriteLineReq miss latency 1015system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13800.824670 # average LoadLockedReq miss latency 1016system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13800.824670 # average LoadLockedReq miss latency 1017system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25020.076334 # average StoreCondReq miss latency 1018system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25020.076334 # average StoreCondReq miss latency 1019system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1020system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1021system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17777.853389 # average overall miss latency 1022system.cpu0.dcache.demand_avg_miss_latency::total 17777.853389 # average overall miss latency 1023system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16983.215453 # average overall miss latency 1024system.cpu0.dcache.overall_avg_miss_latency::total 16983.215453 # average overall miss latency 1025system.cpu0.dcache.blocked_cycles::no_mshrs 9060649 # number of cycles access was blocked 1026system.cpu0.dcache.blocked_cycles::no_targets 19650869 # number of cycles access was blocked 1027system.cpu0.dcache.blocked::no_mshrs 747322 # number of cycles access was blocked 1028system.cpu0.dcache.blocked::no_targets 698056 # number of cycles access was blocked 1029system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.124157 # average number of cycles each access was blocked 1030system.cpu0.dcache.avg_blocked_cycles::no_targets 28.150849 # average number of cycles each access was blocked 1031system.cpu0.dcache.writebacks::writebacks 5793928 # number of writebacks 1032system.cpu0.dcache.writebacks::total 5793928 # number of writebacks 1033system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3323367 # number of ReadReq MSHR hits 1034system.cpu0.dcache.ReadReq_mshr_hits::total 3323367 # number of ReadReq MSHR hits 1035system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5758852 # number of WriteReq MSHR hits 1036system.cpu0.dcache.WriteReq_mshr_hits::total 5758852 # number of WriteReq MSHR hits 1037system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4670 # number of WriteLineReq MSHR hits 1038system.cpu0.dcache.WriteLineReq_mshr_hits::total 4670 # number of WriteLineReq MSHR hits 1039system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 128237 # number of LoadLockedReq MSHR hits 1040system.cpu0.dcache.LoadLockedReq_mshr_hits::total 128237 # number of LoadLockedReq MSHR hits 1041system.cpu0.dcache.demand_mshr_hits::cpu0.data 9086889 # number of demand (read+write) MSHR hits 1042system.cpu0.dcache.demand_mshr_hits::total 9086889 # number of demand (read+write) MSHR hits 1043system.cpu0.dcache.overall_mshr_hits::cpu0.data 9086889 # number of overall MSHR hits 1044system.cpu0.dcache.overall_mshr_hits::total 9086889 # number of overall MSHR hits 1045system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3125456 # number of ReadReq MSHR misses 1046system.cpu0.dcache.ReadReq_mshr_misses::total 3125456 # number of ReadReq MSHR misses 1047system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1433021 # number of WriteReq MSHR misses 1048system.cpu0.dcache.WriteReq_mshr_misses::total 1433021 # number of WriteReq MSHR misses 1049system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 669278 # number of SoftPFReq MSHR misses 1050system.cpu0.dcache.SoftPFReq_mshr_misses::total 669278 # number of SoftPFReq MSHR misses 1051system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 806156 # number of WriteLineReq MSHR misses 1052system.cpu0.dcache.WriteLineReq_mshr_misses::total 806156 # number of WriteLineReq MSHR misses 1053system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 119256 # number of LoadLockedReq MSHR misses 1054system.cpu0.dcache.LoadLockedReq_mshr_misses::total 119256 # number of LoadLockedReq MSHR misses 1055system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 187331 # number of StoreCondReq MSHR misses 1056system.cpu0.dcache.StoreCondReq_mshr_misses::total 187331 # number of StoreCondReq MSHR misses 1057system.cpu0.dcache.demand_mshr_misses::cpu0.data 5364633 # number of demand (read+write) MSHR misses 1058system.cpu0.dcache.demand_mshr_misses::total 5364633 # number of demand (read+write) MSHR misses 1059system.cpu0.dcache.overall_mshr_misses::cpu0.data 6033911 # number of overall MSHR misses 1060system.cpu0.dcache.overall_mshr_misses::total 6033911 # number of overall MSHR misses 1061system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32527 # number of ReadReq MSHR uncacheable 1062system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32527 # number of ReadReq MSHR uncacheable 1063system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32351 # number of WriteReq MSHR uncacheable 1064system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32351 # number of WriteReq MSHR uncacheable 1065system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 64878 # number of overall MSHR uncacheable misses 1066system.cpu0.dcache.overall_mshr_uncacheable_misses::total 64878 # number of overall MSHR uncacheable misses 1067system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43142423000 # number of ReadReq MSHR miss cycles 1068system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43142423000 # number of ReadReq MSHR miss cycles 1069system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30169010620 # number of WriteReq MSHR miss cycles 1070system.cpu0.dcache.WriteReq_mshr_miss_latency::total 30169010620 # number of WriteReq MSHR miss cycles 1071system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14964455000 # number of SoftPFReq MSHR miss cycles 1072system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14964455000 # number of SoftPFReq MSHR miss cycles 1073system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28947099689 # number of WriteLineReq MSHR miss cycles 1074system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28947099689 # number of WriteLineReq MSHR miss cycles 1075system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1564593500 # number of LoadLockedReq MSHR miss cycles 1076system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1564593500 # number of LoadLockedReq MSHR miss cycles 1077system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4499876000 # number of StoreCondReq MSHR miss cycles 1078system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4499876000 # number of StoreCondReq MSHR miss cycles 1079system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3717500 # number of StoreCondFailReq MSHR miss cycles 1080system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3717500 # number of StoreCondFailReq MSHR miss cycles 1081system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 102258533309 # number of demand (read+write) MSHR miss cycles 1082system.cpu0.dcache.demand_mshr_miss_latency::total 102258533309 # number of demand (read+write) MSHR miss cycles 1083system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 117222988309 # number of overall MSHR miss cycles 1084system.cpu0.dcache.overall_mshr_miss_latency::total 117222988309 # number of overall MSHR miss cycles 1085system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6208668000 # number of ReadReq MSHR uncacheable cycles 1086system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6208668000 # number of ReadReq MSHR uncacheable cycles 1087system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6208668000 # number of overall MSHR uncacheable cycles 1088system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6208668000 # number of overall MSHR uncacheable cycles 1089system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035490 # mshr miss rate for ReadReq accesses 1090system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035490 # mshr miss rate for ReadReq accesses 1091system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018440 # mshr miss rate for WriteReq accesses 1092system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018440 # mshr miss rate for WriteReq accesses 1093system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.752652 # mshr miss rate for SoftPFReq accesses 1094system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.752652 # mshr miss rate for SoftPFReq accesses 1095system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.753073 # mshr miss rate for WriteLineReq accesses 1096system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.753073 # mshr miss rate for WriteLineReq accesses 1097system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057942 # mshr miss rate for LoadLockedReq accesses 1098system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057942 # mshr miss rate for LoadLockedReq accesses 1099system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092573 # mshr miss rate for StoreCondReq accesses 1100system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092573 # mshr miss rate for StoreCondReq accesses 1101system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032152 # mshr miss rate for demand accesses 1102system.cpu0.dcache.demand_mshr_miss_rate::total 0.032152 # mshr miss rate for demand accesses 1103system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.035972 # mshr miss rate for overall accesses 1104system.cpu0.dcache.overall_mshr_miss_rate::total 0.035972 # mshr miss rate for overall accesses 1105system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13803.561144 # average ReadReq mshr miss latency 1106system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13803.561144 # average ReadReq mshr miss latency 1107system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21052.734482 # average WriteReq mshr miss latency 1108system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21052.734482 # average WriteReq mshr miss latency 1109system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22359.101898 # average SoftPFReq mshr miss latency 1110system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22359.101898 # average SoftPFReq mshr miss latency 1111system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 35907.565892 # average WriteLineReq mshr miss latency 1112system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 35907.565892 # average WriteLineReq mshr miss latency 1113system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13119.620816 # average LoadLockedReq mshr miss latency 1114system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13119.620816 # average LoadLockedReq mshr miss latency 1115system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24020.989585 # average StoreCondReq mshr miss latency 1116system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24020.989585 # average StoreCondReq mshr miss latency 1117system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1118system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1119system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19061.608373 # average overall mshr miss latency 1120system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19061.608373 # average overall mshr miss latency 1121system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19427.364492 # average overall mshr miss latency 1122system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19427.364492 # average overall mshr miss latency 1123system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190877.363421 # average ReadReq mshr uncacheable latency 1124system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190877.363421 # average ReadReq mshr uncacheable latency 1125system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95697.586239 # average overall mshr uncacheable latency 1126system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95697.586239 # average overall mshr uncacheable latency 1127system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 1128system.cpu0.icache.tags.replacements 6136519 # number of replacements 1129system.cpu0.icache.tags.tagsinuse 511.962391 # Cycle average of tags in use 1130system.cpu0.icache.tags.total_refs 209807209 # Total number of references to valid blocks. 1131system.cpu0.icache.tags.sampled_refs 6137031 # Sample count of references to valid blocks. 1132system.cpu0.icache.tags.avg_refs 34.187086 # Average number of references to valid blocks. 1133system.cpu0.icache.tags.warmup_cycle 12886295000 # Cycle when the warmup percentage was hit. 1134system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.962391 # Average occupied blocks per requestor 1135system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999927 # Average percentage of cache occupancy 1136system.cpu0.icache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy 1137system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1138system.cpu0.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id 1139system.cpu0.icache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id 1140system.cpu0.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id 1141system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1142system.cpu0.icache.tags.tag_accesses 438728804 # Number of tag accesses 1143system.cpu0.icache.tags.data_accesses 438728804 # Number of data accesses 1144system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 1145system.cpu0.icache.ReadReq_hits::cpu0.inst 209807209 # number of ReadReq hits 1146system.cpu0.icache.ReadReq_hits::total 209807209 # number of ReadReq hits 1147system.cpu0.icache.demand_hits::cpu0.inst 209807209 # number of demand (read+write) hits 1148system.cpu0.icache.demand_hits::total 209807209 # number of demand (read+write) hits 1149system.cpu0.icache.overall_hits::cpu0.inst 209807209 # number of overall hits 1150system.cpu0.icache.overall_hits::total 209807209 # number of overall hits 1151system.cpu0.icache.ReadReq_misses::cpu0.inst 6488653 # number of ReadReq misses 1152system.cpu0.icache.ReadReq_misses::total 6488653 # number of ReadReq misses 1153system.cpu0.icache.demand_misses::cpu0.inst 6488653 # number of demand (read+write) misses 1154system.cpu0.icache.demand_misses::total 6488653 # number of demand (read+write) misses 1155system.cpu0.icache.overall_misses::cpu0.inst 6488653 # number of overall misses 1156system.cpu0.icache.overall_misses::total 6488653 # number of overall misses 1157system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 69596700450 # number of ReadReq miss cycles 1158system.cpu0.icache.ReadReq_miss_latency::total 69596700450 # number of ReadReq miss cycles 1159system.cpu0.icache.demand_miss_latency::cpu0.inst 69596700450 # number of demand (read+write) miss cycles 1160system.cpu0.icache.demand_miss_latency::total 69596700450 # number of demand (read+write) miss cycles 1161system.cpu0.icache.overall_miss_latency::cpu0.inst 69596700450 # number of overall miss cycles 1162system.cpu0.icache.overall_miss_latency::total 69596700450 # number of overall miss cycles 1163system.cpu0.icache.ReadReq_accesses::cpu0.inst 216295862 # number of ReadReq accesses(hits+misses) 1164system.cpu0.icache.ReadReq_accesses::total 216295862 # number of ReadReq accesses(hits+misses) 1165system.cpu0.icache.demand_accesses::cpu0.inst 216295862 # number of demand (read+write) accesses 1166system.cpu0.icache.demand_accesses::total 216295862 # number of demand (read+write) accesses 1167system.cpu0.icache.overall_accesses::cpu0.inst 216295862 # number of overall (read+write) accesses 1168system.cpu0.icache.overall_accesses::total 216295862 # number of overall (read+write) accesses 1169system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029999 # miss rate for ReadReq accesses 1170system.cpu0.icache.ReadReq_miss_rate::total 0.029999 # miss rate for ReadReq accesses 1171system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029999 # miss rate for demand accesses 1172system.cpu0.icache.demand_miss_rate::total 0.029999 # miss rate for demand accesses 1173system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029999 # miss rate for overall accesses 1174system.cpu0.icache.overall_miss_rate::total 0.029999 # miss rate for overall accesses 1175system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10725.908821 # average ReadReq miss latency 1176system.cpu0.icache.ReadReq_avg_miss_latency::total 10725.908821 # average ReadReq miss latency 1177system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10725.908821 # average overall miss latency 1178system.cpu0.icache.demand_avg_miss_latency::total 10725.908821 # average overall miss latency 1179system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10725.908821 # average overall miss latency 1180system.cpu0.icache.overall_avg_miss_latency::total 10725.908821 # average overall miss latency 1181system.cpu0.icache.blocked_cycles::no_mshrs 10132412 # number of cycles access was blocked 1182system.cpu0.icache.blocked_cycles::no_targets 436 # number of cycles access was blocked 1183system.cpu0.icache.blocked::no_mshrs 737599 # number of cycles access was blocked 1184system.cpu0.icache.blocked::no_targets 9 # number of cycles access was blocked 1185system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.737020 # average number of cycles each access was blocked 1186system.cpu0.icache.avg_blocked_cycles::no_targets 48.444444 # average number of cycles each access was blocked 1187system.cpu0.icache.writebacks::writebacks 6136519 # number of writebacks 1188system.cpu0.icache.writebacks::total 6136519 # number of writebacks 1189system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 351573 # number of ReadReq MSHR hits 1190system.cpu0.icache.ReadReq_mshr_hits::total 351573 # number of ReadReq MSHR hits 1191system.cpu0.icache.demand_mshr_hits::cpu0.inst 351573 # number of demand (read+write) MSHR hits 1192system.cpu0.icache.demand_mshr_hits::total 351573 # number of demand (read+write) MSHR hits 1193system.cpu0.icache.overall_mshr_hits::cpu0.inst 351573 # number of overall MSHR hits 1194system.cpu0.icache.overall_mshr_hits::total 351573 # number of overall MSHR hits 1195system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6137080 # number of ReadReq MSHR misses 1196system.cpu0.icache.ReadReq_mshr_misses::total 6137080 # number of ReadReq MSHR misses 1197system.cpu0.icache.demand_mshr_misses::cpu0.inst 6137080 # number of demand (read+write) MSHR misses 1198system.cpu0.icache.demand_mshr_misses::total 6137080 # number of demand (read+write) MSHR misses 1199system.cpu0.icache.overall_mshr_misses::cpu0.inst 6137080 # number of overall MSHR misses 1200system.cpu0.icache.overall_mshr_misses::total 6137080 # number of overall MSHR misses 1201system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 1202system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable 1203system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 1204system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses 1205system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 62984871633 # number of ReadReq MSHR miss cycles 1206system.cpu0.icache.ReadReq_mshr_miss_latency::total 62984871633 # number of ReadReq MSHR miss cycles 1207system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 62984871633 # number of demand (read+write) MSHR miss cycles 1208system.cpu0.icache.demand_mshr_miss_latency::total 62984871633 # number of demand (read+write) MSHR miss cycles 1209system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 62984871633 # number of overall MSHR miss cycles 1210system.cpu0.icache.overall_mshr_miss_latency::total 62984871633 # number of overall MSHR miss cycles 1211system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of ReadReq MSHR uncacheable cycles 1212system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1885677498 # number of ReadReq MSHR uncacheable cycles 1213system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of overall MSHR uncacheable cycles 1214system.cpu0.icache.overall_mshr_uncacheable_latency::total 1885677498 # number of overall MSHR uncacheable cycles 1215system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028374 # mshr miss rate for ReadReq accesses 1216system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028374 # mshr miss rate for ReadReq accesses 1217system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028374 # mshr miss rate for demand accesses 1218system.cpu0.icache.demand_mshr_miss_rate::total 0.028374 # mshr miss rate for demand accesses 1219system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028374 # mshr miss rate for overall accesses 1220system.cpu0.icache.overall_mshr_miss_rate::total 0.028374 # mshr miss rate for overall accesses 1221system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average ReadReq mshr miss latency 1222system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10263.003193 # average ReadReq mshr miss latency 1223system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency 1224system.cpu0.icache.demand_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency 1225system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency 1226system.cpu0.icache.overall_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency 1227system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average ReadReq mshr uncacheable latency 1228system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753 # average ReadReq mshr uncacheable latency 1229system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average overall mshr uncacheable latency 1230system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753 # average overall mshr uncacheable latency 1231system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 1232system.cpu0.l2cache.prefetcher.num_hwpf_issued 7743703 # number of hwpf issued 1233system.cpu0.l2cache.prefetcher.pfIdentified 7754051 # number of prefetch candidates identified 1234system.cpu0.l2cache.prefetcher.pfBufferHit 9277 # number of redundant prefetches already in prefetch queue 1235system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1236system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1237system.cpu0.l2cache.prefetcher.pfSpanPage 1008365 # number of prefetches not generated due to page crossing 1238system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 1239system.cpu0.l2cache.tags.replacements 2565485 # number of replacements 1240system.cpu0.l2cache.tags.tagsinuse 15956.741738 # Cycle average of tags in use 1241system.cpu0.l2cache.tags.total_refs 17408441 # Total number of references to valid blocks. 1242system.cpu0.l2cache.tags.sampled_refs 2581334 # Sample count of references to valid blocks. 1243system.cpu0.l2cache.tags.avg_refs 6.743971 # Average number of references to valid blocks. 1244system.cpu0.l2cache.tags.warmup_cycle 2212473000 # Cycle when the warmup percentage was hit. 1245system.cpu0.l2cache.tags.occ_blocks::writebacks 14849.648482 # Average occupied blocks per requestor 1246system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 36.124813 # Average occupied blocks per requestor 1247system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 23.448036 # Average occupied blocks per requestor 1248system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000032 # Average occupied blocks per requestor 1249system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1047.520376 # Average occupied blocks per requestor 1250system.cpu0.l2cache.tags.occ_percent::writebacks 0.906351 # Average percentage of cache occupancy 1251system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002205 # Average percentage of cache occupancy 1252system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001431 # Average percentage of cache occupancy 1253system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy 1254system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063936 # Average percentage of cache occupancy 1255system.cpu0.l2cache.tags.occ_percent::total 0.973922 # Average percentage of cache occupancy 1256system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1203 # Occupied blocks per task id 1257system.cpu0.l2cache.tags.occ_task_id_blocks::1023 77 # Occupied blocks per task id 1258system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14569 # Occupied blocks per task id 1259system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id 1260system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 211 # Occupied blocks per task id 1261system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 564 # Occupied blocks per task id 1262system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 414 # Occupied blocks per task id 1263system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 59 # Occupied blocks per task id 1264system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 1265system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 1266system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id 1267system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1288 # Occupied blocks per task id 1268system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4722 # Occupied blocks per task id 1269system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4695 # Occupied blocks per task id 1270system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3741 # Occupied blocks per task id 1271system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.073425 # Percentage of cache occupancy per task id 1272system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id 1273system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.889221 # Percentage of cache occupancy per task id 1274system.cpu0.l2cache.tags.tag_accesses 408243228 # Number of tag accesses 1275system.cpu0.l2cache.tags.data_accesses 408243228 # Number of data accesses 1276system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 1277system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 539952 # number of ReadReq hits 1278system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 183800 # number of ReadReq hits 1279system.cpu0.l2cache.ReadReq_hits::total 723752 # number of ReadReq hits 1280system.cpu0.l2cache.WritebackDirty_hits::writebacks 3863126 # number of WritebackDirty hits 1281system.cpu0.l2cache.WritebackDirty_hits::total 3863126 # number of WritebackDirty hits 1282system.cpu0.l2cache.WritebackClean_hits::writebacks 8065215 # number of WritebackClean hits 1283system.cpu0.l2cache.WritebackClean_hits::total 8065215 # number of WritebackClean hits 1284system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 386 # number of UpgradeReq hits 1285system.cpu0.l2cache.UpgradeReq_hits::total 386 # number of UpgradeReq hits 1286system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 6 # number of SCUpgradeReq hits 1287system.cpu0.l2cache.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits 1288system.cpu0.l2cache.ReadExReq_hits::cpu0.data 895474 # number of ReadExReq hits 1289system.cpu0.l2cache.ReadExReq_hits::total 895474 # number of ReadExReq hits 1290system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5563145 # number of ReadCleanReq hits 1291system.cpu0.l2cache.ReadCleanReq_hits::total 5563145 # number of ReadCleanReq hits 1292system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2937118 # number of ReadSharedReq hits 1293system.cpu0.l2cache.ReadSharedReq_hits::total 2937118 # number of ReadSharedReq hits 1294system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 202987 # number of InvalidateReq hits 1295system.cpu0.l2cache.InvalidateReq_hits::total 202987 # number of InvalidateReq hits 1296system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 539952 # number of demand (read+write) hits 1297system.cpu0.l2cache.demand_hits::cpu0.itb.walker 183800 # number of demand (read+write) hits 1298system.cpu0.l2cache.demand_hits::cpu0.inst 5563145 # number of demand (read+write) hits 1299system.cpu0.l2cache.demand_hits::cpu0.data 3832592 # number of demand (read+write) hits 1300system.cpu0.l2cache.demand_hits::total 10119489 # number of demand (read+write) hits 1301system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 539952 # number of overall hits 1302system.cpu0.l2cache.overall_hits::cpu0.itb.walker 183800 # number of overall hits 1303system.cpu0.l2cache.overall_hits::cpu0.inst 5563145 # number of overall hits 1304system.cpu0.l2cache.overall_hits::cpu0.data 3832592 # number of overall hits 1305system.cpu0.l2cache.overall_hits::total 10119489 # number of overall hits 1306system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10772 # number of ReadReq misses 1307system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7627 # number of ReadReq misses 1308system.cpu0.l2cache.ReadReq_misses::total 18399 # number of ReadReq misses 1309system.cpu0.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses 1310system.cpu0.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses 1311system.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 1312system.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses 1313system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 260447 # number of UpgradeReq misses 1314system.cpu0.l2cache.UpgradeReq_misses::total 260447 # number of UpgradeReq misses 1315system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 187318 # number of SCUpgradeReq misses 1316system.cpu0.l2cache.SCUpgradeReq_misses::total 187318 # number of SCUpgradeReq misses 1317system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # number of SCUpgradeFailReq misses 1318system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses 1319system.cpu0.l2cache.ReadExReq_misses::cpu0.data 288236 # number of ReadExReq misses 1320system.cpu0.l2cache.ReadExReq_misses::total 288236 # number of ReadExReq misses 1321system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 573862 # number of ReadCleanReq misses 1322system.cpu0.l2cache.ReadCleanReq_misses::total 573862 # number of ReadCleanReq misses 1323system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 973549 # number of ReadSharedReq misses 1324system.cpu0.l2cache.ReadSharedReq_misses::total 973549 # number of ReadSharedReq misses 1325system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 600983 # number of InvalidateReq misses 1326system.cpu0.l2cache.InvalidateReq_misses::total 600983 # number of InvalidateReq misses 1327system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10772 # number of demand (read+write) misses 1328system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7627 # number of demand (read+write) misses 1329system.cpu0.l2cache.demand_misses::cpu0.inst 573862 # number of demand (read+write) misses 1330system.cpu0.l2cache.demand_misses::cpu0.data 1261785 # number of demand (read+write) misses 1331system.cpu0.l2cache.demand_misses::total 1854046 # number of demand (read+write) misses 1332system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10772 # number of overall misses 1333system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7627 # number of overall misses 1334system.cpu0.l2cache.overall_misses::cpu0.inst 573862 # number of overall misses 1335system.cpu0.l2cache.overall_misses::cpu0.data 1261785 # number of overall misses 1336system.cpu0.l2cache.overall_misses::total 1854046 # number of overall misses 1337system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 369514500 # number of ReadReq miss cycles 1338system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 247873000 # number of ReadReq miss cycles 1339system.cpu0.l2cache.ReadReq_miss_latency::total 617387500 # number of ReadReq miss cycles 1340system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2108131500 # number of UpgradeReq miss cycles 1341system.cpu0.l2cache.UpgradeReq_miss_latency::total 2108131500 # number of UpgradeReq miss cycles 1342system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1419046500 # number of SCUpgradeReq miss cycles 1343system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1419046500 # number of SCUpgradeReq miss cycles 1344system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3609499 # number of SCUpgradeFailReq miss cycles 1345system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3609499 # number of SCUpgradeFailReq miss cycles 1346system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 14578954500 # number of ReadExReq miss cycles 1347system.cpu0.l2cache.ReadExReq_miss_latency::total 14578954500 # number of ReadExReq miss cycles 1348system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 20073597500 # number of ReadCleanReq miss cycles 1349system.cpu0.l2cache.ReadCleanReq_miss_latency::total 20073597500 # number of ReadCleanReq miss cycles 1350system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 34202997471 # number of ReadSharedReq miss cycles 1351system.cpu0.l2cache.ReadSharedReq_miss_latency::total 34202997471 # number of ReadSharedReq miss cycles 1352system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 348158000 # number of InvalidateReq miss cycles 1353system.cpu0.l2cache.InvalidateReq_miss_latency::total 348158000 # number of InvalidateReq miss cycles 1354system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 369514500 # number of demand (read+write) miss cycles 1355system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 247873000 # number of demand (read+write) miss cycles 1356system.cpu0.l2cache.demand_miss_latency::cpu0.inst 20073597500 # number of demand (read+write) miss cycles 1357system.cpu0.l2cache.demand_miss_latency::cpu0.data 48781951971 # number of demand (read+write) miss cycles 1358system.cpu0.l2cache.demand_miss_latency::total 69472936971 # number of demand (read+write) miss cycles 1359system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 369514500 # number of overall miss cycles 1360system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 247873000 # number of overall miss cycles 1361system.cpu0.l2cache.overall_miss_latency::cpu0.inst 20073597500 # number of overall miss cycles 1362system.cpu0.l2cache.overall_miss_latency::cpu0.data 48781951971 # number of overall miss cycles 1363system.cpu0.l2cache.overall_miss_latency::total 69472936971 # number of overall miss cycles 1364system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 550724 # number of ReadReq accesses(hits+misses) 1365system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 191427 # number of ReadReq accesses(hits+misses) 1366system.cpu0.l2cache.ReadReq_accesses::total 742151 # number of ReadReq accesses(hits+misses) 1367system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3863128 # number of WritebackDirty accesses(hits+misses) 1368system.cpu0.l2cache.WritebackDirty_accesses::total 3863128 # number of WritebackDirty accesses(hits+misses) 1369system.cpu0.l2cache.WritebackClean_accesses::writebacks 8065216 # number of WritebackClean accesses(hits+misses) 1370system.cpu0.l2cache.WritebackClean_accesses::total 8065216 # number of WritebackClean accesses(hits+misses) 1371system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 260833 # number of UpgradeReq accesses(hits+misses) 1372system.cpu0.l2cache.UpgradeReq_accesses::total 260833 # number of UpgradeReq accesses(hits+misses) 1373system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 187324 # number of SCUpgradeReq accesses(hits+misses) 1374system.cpu0.l2cache.SCUpgradeReq_accesses::total 187324 # number of SCUpgradeReq accesses(hits+misses) 1375system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 7 # number of SCUpgradeFailReq accesses(hits+misses) 1376system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) 1377system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1183710 # number of ReadExReq accesses(hits+misses) 1378system.cpu0.l2cache.ReadExReq_accesses::total 1183710 # number of ReadExReq accesses(hits+misses) 1379system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6137007 # number of ReadCleanReq accesses(hits+misses) 1380system.cpu0.l2cache.ReadCleanReq_accesses::total 6137007 # number of ReadCleanReq accesses(hits+misses) 1381system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3910667 # number of ReadSharedReq accesses(hits+misses) 1382system.cpu0.l2cache.ReadSharedReq_accesses::total 3910667 # number of ReadSharedReq accesses(hits+misses) 1383system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 803970 # number of InvalidateReq accesses(hits+misses) 1384system.cpu0.l2cache.InvalidateReq_accesses::total 803970 # number of InvalidateReq accesses(hits+misses) 1385system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 550724 # number of demand (read+write) accesses 1386system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 191427 # number of demand (read+write) accesses 1387system.cpu0.l2cache.demand_accesses::cpu0.inst 6137007 # number of demand (read+write) accesses 1388system.cpu0.l2cache.demand_accesses::cpu0.data 5094377 # number of demand (read+write) accesses 1389system.cpu0.l2cache.demand_accesses::total 11973535 # number of demand (read+write) accesses 1390system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 550724 # number of overall (read+write) accesses 1391system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 191427 # number of overall (read+write) accesses 1392system.cpu0.l2cache.overall_accesses::cpu0.inst 6137007 # number of overall (read+write) accesses 1393system.cpu0.l2cache.overall_accesses::cpu0.data 5094377 # number of overall (read+write) accesses 1394system.cpu0.l2cache.overall_accesses::total 11973535 # number of overall (read+write) accesses 1395system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.019560 # miss rate for ReadReq accesses 1396system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.039843 # miss rate for ReadReq accesses 1397system.cpu0.l2cache.ReadReq_miss_rate::total 0.024791 # miss rate for ReadReq accesses 1398system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses 1399system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses 1400system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 1401system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 1402system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998520 # miss rate for UpgradeReq accesses 1403system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998520 # miss rate for UpgradeReq accesses 1404system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999968 # miss rate for SCUpgradeReq accesses 1405system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999968 # miss rate for SCUpgradeReq accesses 1406system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1407system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1408system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.243502 # miss rate for ReadExReq accesses 1409system.cpu0.l2cache.ReadExReq_miss_rate::total 0.243502 # miss rate for ReadExReq accesses 1410system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.093508 # miss rate for ReadCleanReq accesses 1411system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.093508 # miss rate for ReadCleanReq accesses 1412system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.248947 # miss rate for ReadSharedReq accesses 1413system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.248947 # miss rate for ReadSharedReq accesses 1414system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.747519 # miss rate for InvalidateReq accesses 1415system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.747519 # miss rate for InvalidateReq accesses 1416system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.019560 # miss rate for demand accesses 1417system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.039843 # miss rate for demand accesses 1418system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.093508 # miss rate for demand accesses 1419system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.247682 # miss rate for demand accesses 1420system.cpu0.l2cache.demand_miss_rate::total 0.154845 # miss rate for demand accesses 1421system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.019560 # miss rate for overall accesses 1422system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.039843 # miss rate for overall accesses 1423system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.093508 # miss rate for overall accesses 1424system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.247682 # miss rate for overall accesses 1425system.cpu0.l2cache.overall_miss_rate::total 0.154845 # miss rate for overall accesses 1426system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34303.239881 # average ReadReq miss latency 1427system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 32499.409991 # average ReadReq miss latency 1428system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33555.492146 # average ReadReq miss latency 1429system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 8094.282138 # average UpgradeReq miss latency 1430system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 8094.282138 # average UpgradeReq miss latency 1431system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 7575.601384 # average SCUpgradeReq miss latency 1432system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 7575.601384 # average SCUpgradeReq miss latency 1433system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 515642.714286 # average SCUpgradeFailReq miss latency 1434system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 515642.714286 # average SCUpgradeFailReq miss latency 1435system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50579.922355 # average ReadExReq miss latency 1436system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50579.922355 # average ReadExReq miss latency 1437system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 34979.834002 # average ReadCleanReq miss latency 1438system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 34979.834002 # average ReadCleanReq miss latency 1439system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35132.281448 # average ReadSharedReq miss latency 1440system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35132.281448 # average ReadSharedReq miss latency 1441system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 579.314224 # average InvalidateReq miss latency 1442system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 579.314224 # average InvalidateReq miss latency 1443system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34303.239881 # average overall miss latency 1444system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 32499.409991 # average overall miss latency 1445system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34979.834002 # average overall miss latency 1446system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38661.065055 # average overall miss latency 1447system.cpu0.l2cache.demand_avg_miss_latency::total 37470.988838 # average overall miss latency 1448system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34303.239881 # average overall miss latency 1449system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 32499.409991 # average overall miss latency 1450system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34979.834002 # average overall miss latency 1451system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38661.065055 # average overall miss latency 1452system.cpu0.l2cache.overall_avg_miss_latency::total 37470.988838 # average overall miss latency 1453system.cpu0.l2cache.blocked_cycles::no_mshrs 395 # number of cycles access was blocked 1454system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1455system.cpu0.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked 1456system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1457system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 56.428571 # average number of cycles each access was blocked 1458system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1459system.cpu0.l2cache.unused_prefetches 43030 # number of HardPF blocks evicted w/o reference 1460system.cpu0.l2cache.writebacks::writebacks 1602911 # number of writebacks 1461system.cpu0.l2cache.writebacks::total 1602911 # number of writebacks 1462system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 2 # number of ReadReq MSHR hits 1463system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 13 # number of ReadReq MSHR hits 1464system.cpu0.l2cache.ReadReq_mshr_hits::total 15 # number of ReadReq MSHR hits 1465system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 13671 # number of ReadExReq MSHR hits 1466system.cpu0.l2cache.ReadExReq_mshr_hits::total 13671 # number of ReadExReq MSHR hits 1467system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 3 # number of ReadCleanReq MSHR hits 1468system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 1469system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 5375 # number of ReadSharedReq MSHR hits 1470system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 5375 # number of ReadSharedReq MSHR hits 1471system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 2 # number of demand (read+write) MSHR hits 1472system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 13 # number of demand (read+write) MSHR hits 1473system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits 1474system.cpu0.l2cache.demand_mshr_hits::cpu0.data 19046 # number of demand (read+write) MSHR hits 1475system.cpu0.l2cache.demand_mshr_hits::total 19064 # number of demand (read+write) MSHR hits 1476system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 2 # number of overall MSHR hits 1477system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 13 # number of overall MSHR hits 1478system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits 1479system.cpu0.l2cache.overall_mshr_hits::cpu0.data 19046 # number of overall MSHR hits 1480system.cpu0.l2cache.overall_mshr_hits::total 19064 # number of overall MSHR hits 1481system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10770 # number of ReadReq MSHR misses 1482system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7614 # number of ReadReq MSHR misses 1483system.cpu0.l2cache.ReadReq_mshr_misses::total 18384 # number of ReadReq MSHR misses 1484system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 2 # number of WritebackDirty MSHR misses 1485system.cpu0.l2cache.WritebackDirty_mshr_misses::total 2 # number of WritebackDirty MSHR misses 1486system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 1487system.cpu0.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses 1488system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 773321 # number of HardPFReq MSHR misses 1489system.cpu0.l2cache.HardPFReq_mshr_misses::total 773321 # number of HardPFReq MSHR misses 1490system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 260447 # number of UpgradeReq MSHR misses 1491system.cpu0.l2cache.UpgradeReq_mshr_misses::total 260447 # number of UpgradeReq MSHR misses 1492system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 187318 # number of SCUpgradeReq MSHR misses 1493system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 187318 # number of SCUpgradeReq MSHR misses 1494system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 7 # number of SCUpgradeFailReq MSHR misses 1495system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses 1496system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 274565 # number of ReadExReq MSHR misses 1497system.cpu0.l2cache.ReadExReq_mshr_misses::total 274565 # number of ReadExReq MSHR misses 1498system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 573859 # number of ReadCleanReq MSHR misses 1499system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 573859 # number of ReadCleanReq MSHR misses 1500system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 968174 # number of ReadSharedReq MSHR misses 1501system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 968174 # number of ReadSharedReq MSHR misses 1502system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 600983 # number of InvalidateReq MSHR misses 1503system.cpu0.l2cache.InvalidateReq_mshr_misses::total 600983 # number of InvalidateReq MSHR misses 1504system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10770 # number of demand (read+write) MSHR misses 1505system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7614 # number of demand (read+write) MSHR misses 1506system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 573859 # number of demand (read+write) MSHR misses 1507system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1242739 # number of demand (read+write) MSHR misses 1508system.cpu0.l2cache.demand_mshr_misses::total 1834982 # number of demand (read+write) MSHR misses 1509system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10770 # number of overall MSHR misses 1510system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7614 # number of overall MSHR misses 1511system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 573859 # number of overall MSHR misses 1512system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1242739 # number of overall MSHR misses 1513system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 773321 # number of overall MSHR misses 1514system.cpu0.l2cache.overall_mshr_misses::total 2608303 # number of overall MSHR misses 1515system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 1516system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32527 # number of ReadReq MSHR uncacheable 1517system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 53820 # number of ReadReq MSHR uncacheable 1518system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32351 # number of WriteReq MSHR uncacheable 1519system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32351 # number of WriteReq MSHR uncacheable 1520system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 1521system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 64878 # number of overall MSHR uncacheable misses 1522system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 86171 # number of overall MSHR uncacheable misses 1523system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 304850000 # number of ReadReq MSHR miss cycles 1524system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 201976000 # number of ReadReq MSHR miss cycles 1525system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 506826000 # number of ReadReq MSHR miss cycles 1526system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 36226481632 # number of HardPFReq MSHR miss cycles 1527system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 36226481632 # number of HardPFReq MSHR miss cycles 1528system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 5428667497 # number of UpgradeReq MSHR miss cycles 1529system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 5428667497 # number of UpgradeReq MSHR miss cycles 1530system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3091853999 # number of SCUpgradeReq MSHR miss cycles 1531system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3091853999 # number of SCUpgradeReq MSHR miss cycles 1532system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 3183499 # number of SCUpgradeFailReq MSHR miss cycles 1533system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3183499 # number of SCUpgradeFailReq MSHR miss cycles 1534system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11062749000 # number of ReadExReq MSHR miss cycles 1535system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11062749000 # number of ReadExReq MSHR miss cycles 1536system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 16630399500 # number of ReadCleanReq MSHR miss cycles 1537system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 16630399500 # number of ReadCleanReq MSHR miss cycles 1538system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 28032243476 # number of ReadSharedReq MSHR miss cycles 1539system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 28032243476 # number of ReadSharedReq MSHR miss cycles 1540system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 21947187999 # number of InvalidateReq MSHR miss cycles 1541system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 21947187999 # number of InvalidateReq MSHR miss cycles 1542system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 304850000 # number of demand (read+write) MSHR miss cycles 1543system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 201976000 # number of demand (read+write) MSHR miss cycles 1544system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 16630399500 # number of demand (read+write) MSHR miss cycles 1545system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 39094992476 # number of demand (read+write) MSHR miss cycles 1546system.cpu0.l2cache.demand_mshr_miss_latency::total 56232217976 # number of demand (read+write) MSHR miss cycles 1547system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 304850000 # number of overall MSHR miss cycles 1548system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 201976000 # number of overall MSHR miss cycles 1549system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 16630399500 # number of overall MSHR miss cycles 1550system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 39094992476 # number of overall MSHR miss cycles 1551system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 36226481632 # number of overall MSHR miss cycles 1552system.cpu0.l2cache.overall_mshr_miss_latency::total 92458699608 # number of overall MSHR miss cycles 1553system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1725979000 # number of ReadReq MSHR uncacheable cycles 1554system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5947854500 # number of ReadReq MSHR uncacheable cycles 1555system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7673833500 # number of ReadReq MSHR uncacheable cycles 1556system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1725979000 # number of overall MSHR uncacheable cycles 1557system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5947854500 # number of overall MSHR uncacheable cycles 1558system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7673833500 # number of overall MSHR uncacheable cycles 1559system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.019556 # mshr miss rate for ReadReq accesses 1560system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.039775 # mshr miss rate for ReadReq accesses 1561system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.024771 # mshr miss rate for ReadReq accesses 1562system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 1563system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses 1564system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 1565system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 1566system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1567system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1568system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998520 # mshr miss rate for UpgradeReq accesses 1569system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998520 # mshr miss rate for UpgradeReq accesses 1570system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999968 # mshr miss rate for SCUpgradeReq accesses 1571system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999968 # mshr miss rate for SCUpgradeReq accesses 1572system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1573system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1574system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.231953 # mshr miss rate for ReadExReq accesses 1575system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231953 # mshr miss rate for ReadExReq accesses 1576system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.093508 # mshr miss rate for ReadCleanReq accesses 1577system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.093508 # mshr miss rate for ReadCleanReq accesses 1578system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.247573 # mshr miss rate for ReadSharedReq accesses 1579system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.247573 # mshr miss rate for ReadSharedReq accesses 1580system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.747519 # mshr miss rate for InvalidateReq accesses 1581system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.747519 # mshr miss rate for InvalidateReq accesses 1582system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.019556 # mshr miss rate for demand accesses 1583system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.039775 # mshr miss rate for demand accesses 1584system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.093508 # mshr miss rate for demand accesses 1585system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.243943 # mshr miss rate for demand accesses 1586system.cpu0.l2cache.demand_mshr_miss_rate::total 0.153253 # mshr miss rate for demand accesses 1587system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.019556 # mshr miss rate for overall accesses 1588system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.039775 # mshr miss rate for overall accesses 1589system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.093508 # mshr miss rate for overall accesses 1590system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.243943 # mshr miss rate for overall accesses 1591system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1592system.cpu0.l2cache.overall_mshr_miss_rate::total 0.217839 # mshr miss rate for overall accesses 1593system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28305.478180 # average ReadReq mshr miss latency 1594system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26526.924087 # average ReadReq mshr miss latency 1595system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27568.864230 # average ReadReq mshr miss latency 1596system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46845.335420 # average HardPFReq mshr miss latency 1597system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46845.335420 # average HardPFReq mshr miss latency 1598system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20843.655320 # average UpgradeReq mshr miss latency 1599system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20843.655320 # average UpgradeReq mshr miss latency 1600system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16505.909731 # average SCUpgradeReq mshr miss latency 1601system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16505.909731 # average SCUpgradeReq mshr miss latency 1602system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 454785.571429 # average SCUpgradeFailReq mshr miss latency 1603system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 454785.571429 # average SCUpgradeFailReq mshr miss latency 1604system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40291.912662 # average ReadExReq mshr miss latency 1605system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40291.912662 # average ReadExReq mshr miss latency 1606system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28979.940194 # average ReadCleanReq mshr miss latency 1607system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28979.940194 # average ReadCleanReq mshr miss latency 1608system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28953.724719 # average ReadSharedReq mshr miss latency 1609system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28953.724719 # average ReadSharedReq mshr miss latency 1610system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36518.816670 # average InvalidateReq mshr miss latency 1611system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36518.816670 # average InvalidateReq mshr miss latency 1612system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28305.478180 # average overall mshr miss latency 1613system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26526.924087 # average overall mshr miss latency 1614system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28979.940194 # average overall mshr miss latency 1615system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31458.731460 # average overall mshr miss latency 1616system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30644.561078 # average overall mshr miss latency 1617system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28305.478180 # average overall mshr miss latency 1618system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26526.924087 # average overall mshr miss latency 1619system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28979.940194 # average overall mshr miss latency 1620system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31458.731460 # average overall mshr miss latency 1621system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46845.335420 # average overall mshr miss latency 1622system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35447.837007 # average overall mshr miss latency 1623system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average ReadReq mshr uncacheable latency 1624system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182858.994066 # average ReadReq mshr uncacheable latency 1625system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142583.305463 # average ReadReq mshr uncacheable latency 1626system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average overall mshr uncacheable latency 1627system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91677.525509 # average overall mshr uncacheable latency 1628system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89053.550498 # average overall mshr uncacheable latency 1629system.cpu0.toL2Bus.snoop_filter.tot_requests 24754475 # Total number of requests made to the snoop filter. 1630system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12719207 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1631system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2136 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1632system.cpu0.toL2Bus.snoop_filter.tot_snoops 1997962 # Total number of snoops made to the snoop filter. 1633system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1997498 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1634system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 464 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1635system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 1636system.cpu0.toL2Bus.trans_dist::ReadReq 885324 # Transaction distribution 1637system.cpu0.toL2Bus.trans_dist::ReadResp 11040535 # Transaction distribution 1638system.cpu0.toL2Bus.trans_dist::WriteReq 32352 # Transaction distribution 1639system.cpu0.toL2Bus.trans_dist::WriteResp 32351 # Transaction distribution 1640system.cpu0.toL2Bus.trans_dist::WritebackDirty 5471965 # Transaction distribution 1641system.cpu0.toL2Bus.trans_dist::WritebackClean 8067317 # Transaction distribution 1642system.cpu0.toL2Bus.trans_dist::CleanEvict 2568559 # Transaction distribution 1643system.cpu0.toL2Bus.trans_dist::HardPFReq 991385 # Transaction distribution 1644system.cpu0.toL2Bus.trans_dist::HardPFResp 10 # Transaction distribution 1645system.cpu0.toL2Bus.trans_dist::UpgradeReq 475065 # Transaction distribution 1646system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 341372 # Transaction distribution 1647system.cpu0.toL2Bus.trans_dist::UpgradeResp 522361 # Transaction distribution 1648system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 76 # Transaction distribution 1649system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 140 # Transaction distribution 1650system.cpu0.toL2Bus.trans_dist::ReadExReq 1216718 # Transaction distribution 1651system.cpu0.toL2Bus.trans_dist::ReadExResp 1192935 # Transaction distribution 1652system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6137080 # Transaction distribution 1653system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4901216 # Transaction distribution 1654system.cpu0.toL2Bus.trans_dist::InvalidateReq 866556 # Transaction distribution 1655system.cpu0.toL2Bus.trans_dist::InvalidateResp 803970 # Transaction distribution 1656system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18453192 # Packet count per connected master and slave (bytes) 1657system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18807742 # Packet count per connected master and slave (bytes) 1658system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 402695 # Packet count per connected master and slave (bytes) 1659system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1170958 # Packet count per connected master and slave (bytes) 1660system.cpu0.toL2Bus.pkt_count::total 38834587 # Packet count per connected master and slave (bytes) 1661system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 785846352 # Cumulative packet size per connected master and slave (bytes) 1662system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 704525389 # Cumulative packet size per connected master and slave (bytes) 1663system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1531416 # Cumulative packet size per connected master and slave (bytes) 1664system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4405792 # Cumulative packet size per connected master and slave (bytes) 1665system.cpu0.toL2Bus.pkt_size::total 1496308949 # Cumulative packet size per connected master and slave (bytes) 1666system.cpu0.toL2Bus.snoops 6903738 # Total snoops (count) 1667system.cpu0.toL2Bus.snoop_fanout::samples 20024554 # Request fanout histogram 1668system.cpu0.toL2Bus.snoop_fanout::mean 0.116908 # Request fanout histogram 1669system.cpu0.toL2Bus.snoop_fanout::stdev 0.321383 # Request fanout histogram 1670system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1671system.cpu0.toL2Bus.snoop_fanout::0 17683990 88.31% 88.31% # Request fanout histogram 1672system.cpu0.toL2Bus.snoop_fanout::1 2340100 11.69% 100.00% # Request fanout histogram 1673system.cpu0.toL2Bus.snoop_fanout::2 464 0.00% 100.00% # Request fanout histogram 1674system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1675system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1676system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1677system.cpu0.toL2Bus.snoop_fanout::total 20024554 # Request fanout histogram 1678system.cpu0.toL2Bus.reqLayer0.occupancy 24612511939 # Layer occupancy (ticks) 1679system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1680system.cpu0.toL2Bus.snoopLayer0.occupancy 212521499 # Layer occupancy (ticks) 1681system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1682system.cpu0.toL2Bus.respLayer0.occupancy 9233457820 # Layer occupancy (ticks) 1683system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1684system.cpu0.toL2Bus.respLayer1.occupancy 8324768239 # Layer occupancy (ticks) 1685system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1686system.cpu0.toL2Bus.respLayer2.occupancy 211573883 # Layer occupancy (ticks) 1687system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1688system.cpu0.toL2Bus.respLayer3.occupancy 620908635 # Layer occupancy (ticks) 1689system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1690system.cpu1.branchPred.lookups 127244460 # Number of BP lookups 1691system.cpu1.branchPred.condPredicted 83927531 # Number of conditional branches predicted 1692system.cpu1.branchPred.condIncorrect 6411720 # Number of conditional branches incorrect 1693system.cpu1.branchPred.BTBLookups 89791062 # Number of BTB lookups 1694system.cpu1.branchPred.BTBHits 55539581 # Number of BTB hits 1695system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1696system.cpu1.branchPred.BTBHitPct 61.854242 # BTB Hit Percentage 1697system.cpu1.branchPred.usedRAS 17406269 # Number of times the RAS was used to get a target. 1698system.cpu1.branchPred.RASInCorrect 177185 # Number of incorrect RAS predictions. 1699system.cpu1.branchPred.indirectLookups 4036084 # Number of indirect predictor lookups. 1700system.cpu1.branchPred.indirectHits 2495247 # Number of indirect target hits. 1701system.cpu1.branchPred.indirectMisses 1540837 # Number of indirect misses. 1702system.cpu1.branchPredindirectMispredicted 386993 # Number of mispredicted indirect branches. 1703system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 1704system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1705system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1706system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1707system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1708system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1709system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1710system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1711system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1712system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1713system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1714system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1715system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1716system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1717system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1718system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1719system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1720system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1721system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1722system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1723system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1724system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1725system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1726system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1727system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1728system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1729system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1730system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1731system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1732system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1733system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 1734system.cpu1.dtb.walker.walks 579824 # Table walker walks requested 1735system.cpu1.dtb.walker.walksLong 579824 # Table walker walks initiated with long descriptors 1736system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12232 # Level at which table walker walks with long descriptors terminate 1737system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93540 # Level at which table walker walks with long descriptors terminate 1738system.cpu1.dtb.walker.walksSquashedBefore 278610 # Table walks squashed before starting 1739system.cpu1.dtb.walker.walkWaitTime::samples 301214 # Table walker wait (enqueue to first request) latency 1740system.cpu1.dtb.walker.walkWaitTime::mean 2385.289196 # Table walker wait (enqueue to first request) latency 1741system.cpu1.dtb.walker.walkWaitTime::stdev 13264.000730 # Table walker wait (enqueue to first request) latency 1742system.cpu1.dtb.walker.walkWaitTime::0-65535 298702 99.17% 99.17% # Table walker wait (enqueue to first request) latency 1743system.cpu1.dtb.walker.walkWaitTime::65536-131071 1877 0.62% 99.79% # Table walker wait (enqueue to first request) latency 1744system.cpu1.dtb.walker.walkWaitTime::131072-196607 425 0.14% 99.93% # Table walker wait (enqueue to first request) latency 1745system.cpu1.dtb.walker.walkWaitTime::196608-262143 126 0.04% 99.97% # Table walker wait (enqueue to first request) latency 1746system.cpu1.dtb.walker.walkWaitTime::262144-327679 47 0.02% 99.99% # Table walker wait (enqueue to first request) latency 1747system.cpu1.dtb.walker.walkWaitTime::327680-393215 33 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1748system.cpu1.dtb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1749system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1750system.cpu1.dtb.walker.walkWaitTime::total 301214 # Table walker wait (enqueue to first request) latency 1751system.cpu1.dtb.walker.walkCompletionTime::samples 311038 # Table walker service (enqueue to completion) latency 1752system.cpu1.dtb.walker.walkCompletionTime::mean 20491.173104 # Table walker service (enqueue to completion) latency 1753system.cpu1.dtb.walker.walkCompletionTime::gmean 17661.433181 # Table walker service (enqueue to completion) latency 1754system.cpu1.dtb.walker.walkCompletionTime::stdev 17134.136599 # Table walker service (enqueue to completion) latency 1755system.cpu1.dtb.walker.walkCompletionTime::0-65535 306887 98.67% 98.67% # Table walker service (enqueue to completion) latency 1756system.cpu1.dtb.walker.walkCompletionTime::65536-131071 3006 0.97% 99.63% # Table walker service (enqueue to completion) latency 1757system.cpu1.dtb.walker.walkCompletionTime::131072-196607 404 0.13% 99.76% # Table walker service (enqueue to completion) latency 1758system.cpu1.dtb.walker.walkCompletionTime::196608-262143 531 0.17% 99.93% # Table walker service (enqueue to completion) latency 1759system.cpu1.dtb.walker.walkCompletionTime::262144-327679 109 0.04% 99.97% # Table walker service (enqueue to completion) latency 1760system.cpu1.dtb.walker.walkCompletionTime::327680-393215 60 0.02% 99.99% # Table walker service (enqueue to completion) latency 1761system.cpu1.dtb.walker.walkCompletionTime::393216-458751 29 0.01% 100.00% # Table walker service (enqueue to completion) latency 1762system.cpu1.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency 1763system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 1764system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1765system.cpu1.dtb.walker.walkCompletionTime::total 311038 # Table walker service (enqueue to completion) latency 1766system.cpu1.dtb.walker.walksPending::samples 427436234332 # Table walker pending requests distribution 1767system.cpu1.dtb.walker.walksPending::mean 0.596252 # Table walker pending requests distribution 1768system.cpu1.dtb.walker.walksPending::stdev 0.559035 # Table walker pending requests distribution 1769system.cpu1.dtb.walker.walksPending::0-1 426093627832 99.69% 99.69% # Table walker pending requests distribution 1770system.cpu1.dtb.walker.walksPending::2-3 733360500 0.17% 99.86% # Table walker pending requests distribution 1771system.cpu1.dtb.walker.walksPending::4-5 289523500 0.07% 99.93% # Table walker pending requests distribution 1772system.cpu1.dtb.walker.walksPending::6-7 124054000 0.03% 99.95% # Table walker pending requests distribution 1773system.cpu1.dtb.walker.walksPending::8-9 101131500 0.02% 99.98% # Table walker pending requests distribution 1774system.cpu1.dtb.walker.walksPending::10-11 55199000 0.01% 99.99% # Table walker pending requests distribution 1775system.cpu1.dtb.walker.walksPending::12-13 17877500 0.00% 99.99% # Table walker pending requests distribution 1776system.cpu1.dtb.walker.walksPending::14-15 20812500 0.00% 100.00% # Table walker pending requests distribution 1777system.cpu1.dtb.walker.walksPending::16-17 638500 0.00% 100.00% # Table walker pending requests distribution 1778system.cpu1.dtb.walker.walksPending::18-19 9500 0.00% 100.00% # Table walker pending requests distribution 1779system.cpu1.dtb.walker.walksPending::total 427436234332 # Table walker pending requests distribution 1780system.cpu1.dtb.walker.walkPageSizes::4K 93540 88.44% 88.44% # Table walker page sizes translated 1781system.cpu1.dtb.walker.walkPageSizes::2M 12232 11.56% 100.00% # Table walker page sizes translated 1782system.cpu1.dtb.walker.walkPageSizes::total 105772 # Table walker page sizes translated 1783system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 579824 # Table walker requests started/completed, data/inst 1784system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1785system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 579824 # Table walker requests started/completed, data/inst 1786system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105772 # Table walker requests started/completed, data/inst 1787system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1788system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105772 # Table walker requests started/completed, data/inst 1789system.cpu1.dtb.walker.walkRequestOrigin::total 685596 # Table walker requests started/completed, data/inst 1790system.cpu1.dtb.inst_hits 0 # ITB inst hits 1791system.cpu1.dtb.inst_misses 0 # ITB inst misses 1792system.cpu1.dtb.read_hits 94100008 # DTB read hits 1793system.cpu1.dtb.read_misses 416726 # DTB read misses 1794system.cpu1.dtb.write_hits 75732153 # DTB write hits 1795system.cpu1.dtb.write_misses 163098 # DTB write misses 1796system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1797system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1798system.cpu1.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID 1799system.cpu1.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID	586system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 587system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 588system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 589system.cpu0.itb.perms_faults 198402 # Number of TLB faults due to permissions restrictions 590system.cpu0.itb.read_accesses 0 # DTB read accesses 591system.cpu0.itb.write_accesses 0 # DTB write accesses 592system.cpu0.itb.inst_accesses 216603307 # ITB inst accesses 593system.cpu0.itb.hits 216521473 # DTB hits 594system.cpu0.itb.misses 81834 # DTB misses 595system.cpu0.itb.accesses 216603307 # DTB accesses 596system.cpu0.numPwrStateTransitions 26480 # Number of power state transitions 597system.cpu0.pwrStateClkGateDist::samples 13240 # Distribution of time spent in the clock gated state 598system.cpu0.pwrStateClkGateDist::mean 3550703383.143278 # Distribution of time spent in the clock gated state 599system.cpu0.pwrStateClkGateDist::stdev 88629328460.442917 # Distribution of time spent in the clock gated state 600system.cpu0.pwrStateClkGateDist::underflows 3078 23.25% 23.25% # Distribution of time spent in the clock gated state 601system.cpu0.pwrStateClkGateDist::1000-5e+10 10135 76.55% 99.80% # Distribution of time spent in the clock gated state 602system.cpu0.pwrStateClkGateDist::5e+10-1e+11 4 0.03% 99.83% # Distribution of time spent in the clock gated state 603system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.83% # Distribution of time spent in the clock gated state 604system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 2 0.02% 99.85% # Distribution of time spent in the clock gated state 605system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 2 0.02% 99.86% # Distribution of time spent in the clock gated state 606system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 607system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 608system.cpu0.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 609system.cpu0.pwrStateClkGateDist::8e+11-8.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 610system.cpu0.pwrStateClkGateDist::overflows 14 0.11% 100.00% # Distribution of time spent in the clock gated state 611system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 612system.cpu0.pwrStateClkGateDist::max_value 7390881192332 # Distribution of time spent in the clock gated state 613system.cpu0.pwrStateClkGateDist::total 13240 # Distribution of time spent in the clock gated state 614system.cpu0.pwrStateResidencyTicks::ON 373002370183 # Cumulative time (in ticks) in various power states 615system.cpu0.pwrStateResidencyTicks::CLK_GATED 47011312792817 # Cumulative time (in ticks) in various power states 616system.cpu0.numCycles 746014900 # number of cpu cycles simulated 617system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 618system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 619system.cpu0.fetch.icacheStallCycles 90433879 # Number of cycles fetch is stalled on an Icache miss 620system.cpu0.fetch.Insts 610172736 # Number of instructions fetch has processed 621system.cpu0.fetch.Branches 138091637 # Number of branches that fetch encountered 622system.cpu0.fetch.predictedBranches 81258280 # Number of branches that fetch has predicted taken 623system.cpu0.fetch.Cycles 615398287 # Number of cycles fetch has run and was not squashing or blocked 624system.cpu0.fetch.SquashCycles 14620490 # Number of cycles fetch has spent squashing 625system.cpu0.fetch.TlbCycles 1715297 # Number of cycles fetch has spent waiting for tlb 626system.cpu0.fetch.MiscStallCycles 295776 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 627system.cpu0.fetch.PendingTrapStallCycles 5589619 # Number of stall cycles due to pending traps 628system.cpu0.fetch.PendingQuiesceStallCycles 711520 # Number of stall cycles due to pending quiesce instructions 629system.cpu0.fetch.IcacheWaitRetryStallCycles 813110 # Number of stall cycles due to full MSHR 630system.cpu0.fetch.CacheLines 216323861 # Number of cache lines fetched 631system.cpu0.fetch.IcacheSquashes 1696724 # Number of outstanding Icache misses that were squashed 632system.cpu0.fetch.ItlbSquashes 26704 # Number of outstanding ITLB misses that were squashed 633system.cpu0.fetch.rateDist::samples 722267733 # Number of instructions fetched each cycle (Total) 634system.cpu0.fetch.rateDist::mean 0.989116 # Number of instructions fetched each cycle (Total) 635system.cpu0.fetch.rateDist::stdev 1.222569 # Number of instructions fetched each cycle (Total) 636system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 637system.cpu0.fetch.rateDist::0 380266002 52.65% 52.65% # Number of instructions fetched each cycle (Total) 638system.cpu0.fetch.rateDist::1 133082578 18.43% 71.07% # Number of instructions fetched each cycle (Total) 639system.cpu0.fetch.rateDist::2 45433566 6.29% 77.36% # Number of instructions fetched each cycle (Total) 640system.cpu0.fetch.rateDist::3 163485587 22.64% 100.00% # Number of instructions fetched each cycle (Total) 641system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 642system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 643system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 644system.cpu0.fetch.rateDist::total 722267733 # Number of instructions fetched each cycle (Total) 645system.cpu0.fetch.branchRate 0.185106 # Number of branch fetches per cycle 646system.cpu0.fetch.rate 0.817910 # Number of inst fetches per cycle 647system.cpu0.decode.IdleCycles 106050198 # Number of cycles decode is idle 648system.cpu0.decode.BlockedCycles 344087060 # Number of cycles decode is blocked 649system.cpu0.decode.RunCycles 231125881 # Number of cycles decode is running 650system.cpu0.decode.UnblockCycles 35774912 # Number of cycles decode is unblocking 651system.cpu0.decode.SquashCycles 5229682 # Number of cycles decode is squashing 652system.cpu0.decode.BranchResolved 19752919 # Number of times decode resolved a branch 653system.cpu0.decode.BranchMispred 2120005 # Number of times decode detected a branch misprediction 654system.cpu0.decode.DecodedInsts 632519077 # Number of instructions handled by decode 655system.cpu0.decode.SquashedInsts 23747295 # Number of squashed instructions handled by decode 656system.cpu0.rename.SquashCycles 5229682 # Number of cycles rename is squashing 657system.cpu0.rename.IdleCycles 140879480 # Number of cycles rename is idle 658system.cpu0.rename.BlockCycles 46445701 # Number of cycles rename is blocking 659system.cpu0.rename.serializeStallCycles 235545365 # count of cycles rename stalled for serializing inst 660system.cpu0.rename.RunCycles 231642525 # Number of cycles rename is running 661system.cpu0.rename.UnblockCycles 62524980 # Number of cycles rename is unblocking 662system.cpu0.rename.RenamedInsts 614970268 # Number of instructions processed by rename 663system.cpu0.rename.SquashedInsts 6274841 # Number of squashed instructions processed by rename 664system.cpu0.rename.ROBFullEvents 9683853 # Number of times rename has blocked due to ROB full 665system.cpu0.rename.IQFullEvents 239254 # Number of times rename has blocked due to IQ full 666system.cpu0.rename.LQFullEvents 254272 # Number of times rename has blocked due to LQ full 667system.cpu0.rename.SQFullEvents 29219197 # Number of times rename has blocked due to SQ full 668system.cpu0.rename.FullRegisterEvents 11058 # Number of times there has been no free registers 669system.cpu0.rename.RenamedOperands 585821211 # Number of destination operands rename has renamed 670system.cpu0.rename.RenameLookups 944611426 # Number of register rename lookups that rename has made 671system.cpu0.rename.int_rename_lookups 725501320 # Number of integer rename lookups 672system.cpu0.rename.fp_rename_lookups 860588 # Number of floating rename lookups 673system.cpu0.rename.CommittedMaps 527918401 # Number of HB maps that are committed 674system.cpu0.rename.UndoneMaps 57902804 # Number of HB maps that are undone due to squashing 675system.cpu0.rename.serializingInsts 14873386 # count of serializing insts renamed 676system.cpu0.rename.tempSerializingInsts 12932012 # count of temporary serializing insts renamed 677system.cpu0.rename.skidInsts 72326353 # count of insts added to the skid buffer 678system.cpu0.memDep0.insertedLoads 100125445 # Number of loads inserted to the mem dependence unit. 679system.cpu0.memDep0.insertedStores 86327833 # Number of stores inserted to the mem dependence unit. 680system.cpu0.memDep0.conflictingLoads 8833111 # Number of conflicting loads. 681system.cpu0.memDep0.conflictingStores 7713299 # Number of conflicting stores. 682system.cpu0.iq.iqInstsAdded 593239093 # Number of instructions added to the IQ (excludes non-spec) 683system.cpu0.iq.iqNonSpecInstsAdded 14925406 # Number of non-speculative instructions added to the IQ 684system.cpu0.iq.iqInstsIssued 596650262 # Number of instructions issued 685system.cpu0.iq.iqSquashedInstsIssued 2740149 # Number of squashed instructions issued 686system.cpu0.iq.iqSquashedInstsExamined 54305512 # Number of squashed instructions iterated over during squash; mainly for profiling 687system.cpu0.iq.iqSquashedOperandsExamined 35087941 # Number of squashed operands that are examined and possibly removed from graph 688system.cpu0.iq.iqSquashedNonSpecRemoved 259840 # Number of squashed non-spec instructions that were removed 689system.cpu0.iq.issued_per_cycle::samples 722267733 # Number of insts issued each cycle 690system.cpu0.iq.issued_per_cycle::mean 0.826079 # Number of insts issued each cycle 691system.cpu0.iq.issued_per_cycle::stdev 1.071801 # Number of insts issued each cycle 692system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 693system.cpu0.iq.issued_per_cycle::0 398653423 55.19% 55.19% # Number of insts issued each cycle 694system.cpu0.iq.issued_per_cycle::1 132668388 18.37% 73.56% # Number of insts issued each cycle 695system.cpu0.iq.issued_per_cycle::2 116695962 16.16% 89.72% # Number of insts issued each cycle 696system.cpu0.iq.issued_per_cycle::3 66414173 9.20% 98.92% # Number of insts issued each cycle 697system.cpu0.iq.issued_per_cycle::4 7831504 1.08% 100.00% # Number of insts issued each cycle 698system.cpu0.iq.issued_per_cycle::5 4283 0.00% 100.00% # Number of insts issued each cycle 699system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 700system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 701system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 702system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 703system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 704system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 705system.cpu0.iq.issued_per_cycle::total 722267733 # Number of insts issued each cycle 706system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 707system.cpu0.iq.fu_full::IntAlu 62572261 45.86% 45.86% # attempts to use FU when none available 708system.cpu0.iq.fu_full::IntMult 47637 0.03% 45.89% # attempts to use FU when none available 709system.cpu0.iq.fu_full::IntDiv 27538 0.02% 45.91% # attempts to use FU when none available 710system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.91% # attempts to use FU when none available 711system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.91% # attempts to use FU when none available 712system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.91% # attempts to use FU when none available 713system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.91% # attempts to use FU when none available 714system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.91% # attempts to use FU when none available 715system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.91% # attempts to use FU when none available 716system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.91% # attempts to use FU when none available 717system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.91% # attempts to use FU when none available 718system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.91% # attempts to use FU when none available 719system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.91% # attempts to use FU when none available 720system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.91% # attempts to use FU when none available 721system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.91% # attempts to use FU when none available 722system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.91% # attempts to use FU when none available 723system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.91% # attempts to use FU when none available 724system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.91% # attempts to use FU when none available 725system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.91% # attempts to use FU when none available 726system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.91% # attempts to use FU when none available 727system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.91% # attempts to use FU when none available 728system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.91% # attempts to use FU when none available 729system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.91% # attempts to use FU when none available 730system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.91% # attempts to use FU when none available 731system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.91% # attempts to use FU when none available 732system.cpu0.iq.fu_full::SimdFloatMisc 12 0.00% 45.91% # attempts to use FU when none available 733system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.91% # attempts to use FU when none available 734system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.91% # attempts to use FU when none available 735system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.91% # attempts to use FU when none available 736system.cpu0.iq.fu_full::MemRead 35025206 25.67% 71.58% # attempts to use FU when none available 737system.cpu0.iq.fu_full::MemWrite 38780691 28.42% 100.00% # attempts to use FU when none available 738system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 739system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 740system.cpu0.iq.FU_type_0::No_OpClass 37 0.00% 0.00% # Type of FU issued 741system.cpu0.iq.FU_type_0::IntAlu 408003074 68.38% 68.38% # Type of FU issued 742system.cpu0.iq.FU_type_0::IntMult 1391206 0.23% 68.62% # Type of FU issued 743system.cpu0.iq.FU_type_0::IntDiv 75246 0.01% 68.63% # Type of FU issued 744system.cpu0.iq.FU_type_0::FloatAdd 5 0.00% 68.63% # Type of FU issued 745system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.63% # Type of FU issued 746system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.63% # Type of FU issued 747system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.63% # Type of FU issued 748system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.63% # Type of FU issued 749system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.63% # Type of FU issued 750system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.63% # Type of FU issued 751system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.63% # Type of FU issued 752system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.63% # Type of FU issued 753system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.63% # Type of FU issued 754system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.63% # Type of FU issued 755system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.63% # Type of FU issued 756system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.63% # Type of FU issued 757system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.63% # Type of FU issued 758system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.63% # Type of FU issued 759system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.63% # Type of FU issued 760system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.63% # Type of FU issued 761system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.63% # Type of FU issued 762system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.63% # Type of FU issued 763system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.63% # Type of FU issued 764system.cpu0.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.63% # Type of FU issued 765system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.63% # Type of FU issued 766system.cpu0.iq.FU_type_0::SimdFloatMisc 75513 0.01% 68.64% # Type of FU issued 767system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.64% # Type of FU issued 768system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.64% # Type of FU issued 769system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.64% # Type of FU issued 770system.cpu0.iq.FU_type_0::MemRead 102801955 17.23% 85.87% # Type of FU issued 771system.cpu0.iq.FU_type_0::MemWrite 84303178 14.13% 100.00% # Type of FU issued 772system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 773system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 774system.cpu0.iq.FU_type_0::total 596650262 # Type of FU issued 775system.cpu0.iq.rate 0.799783 # Inst issue rate 776system.cpu0.iq.fu_busy_cnt 136453345 # FU busy when requested 777system.cpu0.iq.fu_busy_rate 0.228699 # FU busy rate (busy events/executed inst) 778system.cpu0.iq.int_inst_queue_reads 2053360508 # Number of integer instruction queue reads 779system.cpu0.iq.int_inst_queue_writes 662051351 # Number of integer instruction queue writes 780system.cpu0.iq.int_inst_queue_wakeup_accesses 579495604 # Number of integer instruction queue wakeup accesses 781system.cpu0.iq.fp_inst_queue_reads 1401241 # Number of floating instruction queue reads 782system.cpu0.iq.fp_inst_queue_writes 556367 # Number of floating instruction queue writes 783system.cpu0.iq.fp_inst_queue_wakeup_accesses 521179 # Number of floating instruction queue wakeup accesses 784system.cpu0.iq.int_alu_accesses 732235238 # Number of integer alu accesses 785system.cpu0.iq.fp_alu_accesses 868332 # Number of floating point alu accesses 786system.cpu0.iew.lsq.thread0.forwLoads 2674563 # Number of loads that had data forwarded from stores 787system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 788system.cpu0.iew.lsq.thread0.squashedLoads 12322480 # Number of loads squashed 789system.cpu0.iew.lsq.thread0.ignoredResponses 16225 # Number of memory responses ignored because the instruction is squashed 790system.cpu0.iew.lsq.thread0.memOrderViolation 138716 # Number of memory ordering violations 791system.cpu0.iew.lsq.thread0.squashedStores 5498195 # Number of stores squashed 792system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 793system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 794system.cpu0.iew.lsq.thread0.rescheduledLoads 2627025 # Number of loads that were rescheduled 795system.cpu0.iew.lsq.thread0.cacheBlocked 4349073 # Number of times an access to memory failed due to the cache being blocked 796system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 797system.cpu0.iew.iewSquashCycles 5229682 # Number of cycles IEW is squashing 798system.cpu0.iew.iewBlockCycles 6015766 # Number of cycles IEW is blocking 799system.cpu0.iew.iewUnblockCycles 1577054 # Number of cycles IEW is unblocking 800system.cpu0.iew.iewDispatchedInsts 608291813 # Number of instructions dispatched to IQ 801system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 802system.cpu0.iew.iewDispLoadInsts 100125445 # Number of dispatched load instructions 803system.cpu0.iew.iewDispStoreInsts 86327833 # Number of dispatched store instructions 804system.cpu0.iew.iewDispNonSpecInsts 12661031 # Number of dispatched non-speculative instructions 805system.cpu0.iew.iewIQFullEvents 57348 # Number of times the IQ has become full, causing a stall 806system.cpu0.iew.iewLSQFullEvents 1462300 # Number of times the LSQ has become full, causing a stall 807system.cpu0.iew.memOrderViolationEvents 138716 # Number of memory order violations 808system.cpu0.iew.predictedTakenIncorrect 1920652 # Number of branches that were predicted taken incorrectly 809system.cpu0.iew.predictedNotTakenIncorrect 3139987 # Number of branches that were predicted not taken incorrectly 810system.cpu0.iew.branchMispredicts 5060639 # Number of branch mispredicts detected at execute 811system.cpu0.iew.iewExecutedInsts 588583301 # Number of executed instructions 812system.cpu0.iew.iewExecLoadInsts 99681195 # Number of load instructions executed 813system.cpu0.iew.iewExecSquashedInsts 7546532 # Number of squashed instructions skipped in execute 814system.cpu0.iew.exec_swp 0 # number of swp insts executed 815system.cpu0.iew.exec_nop 127314 # number of nop insts executed 816system.cpu0.iew.exec_refs 182727665 # number of memory reference insts executed 817system.cpu0.iew.exec_branches 110905985 # Number of branches executed 818system.cpu0.iew.exec_stores 83046470 # Number of stores executed 819system.cpu0.iew.exec_rate 0.788970 # Inst execution rate 820system.cpu0.iew.wb_sent 580785082 # cumulative count of insts sent to commit 821system.cpu0.iew.wb_count 580016783 # cumulative count of insts written-back 822system.cpu0.iew.wb_producers 281571835 # num instructions producing a value 823system.cpu0.iew.wb_consumers 462036259 # num instructions consuming a value 824system.cpu0.iew.wb_rate 0.777487 # insts written-back per cycle 825system.cpu0.iew.wb_fanout 0.609415 # average fanout of values written-back 826system.cpu0.commit.commitSquashedInsts 47239068 # The number of squashed insts skipped by commit 827system.cpu0.commit.commitNonSpecStalls 14665566 # The number of times commit has been forced to stall to communicate backwards 828system.cpu0.commit.branchMispredicts 4709377 # The number of times a branch was mispredicted 829system.cpu0.commit.committed_per_cycle::samples 713265593 # Number of insts commited each cycle 830system.cpu0.commit.committed_per_cycle::mean 0.776512 # Number of insts commited each cycle 831system.cpu0.commit.committed_per_cycle::stdev 1.575400 # Number of insts commited each cycle 832system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 833system.cpu0.commit.committed_per_cycle::0 472345396 66.22% 66.22% # Number of insts commited each cycle 834system.cpu0.commit.committed_per_cycle::1 122854697 17.22% 83.45% # Number of insts commited each cycle 835system.cpu0.commit.committed_per_cycle::2 54352038 7.62% 91.07% # Number of insts commited each cycle 836system.cpu0.commit.committed_per_cycle::3 18530727 2.60% 93.67% # Number of insts commited each cycle 837system.cpu0.commit.committed_per_cycle::4 13156863 1.84% 95.51% # Number of insts commited each cycle 838system.cpu0.commit.committed_per_cycle::5 8843989 1.24% 96.75% # Number of insts commited each cycle 839system.cpu0.commit.committed_per_cycle::6 5973723 0.84% 97.59% # Number of insts commited each cycle 840system.cpu0.commit.committed_per_cycle::7 3646989 0.51% 98.10% # Number of insts commited each cycle 841system.cpu0.commit.committed_per_cycle::8 13561171 1.90% 100.00% # Number of insts commited each cycle 842system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 843system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 844system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 845system.cpu0.commit.committed_per_cycle::total 713265593 # Number of insts commited each cycle 846system.cpu0.commit.committedInsts 471410910 # Number of instructions committed 847system.cpu0.commit.committedOps 553858980 # Number of ops (including micro ops) committed 848system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 849system.cpu0.commit.refs 168632602 # Number of memory references committed 850system.cpu0.commit.loads 87802964 # Number of loads committed 851system.cpu0.commit.membars 3653468 # Number of memory barriers committed 852system.cpu0.commit.branches 105429162 # Number of branches committed 853system.cpu0.commit.fp_insts 512997 # Number of committed floating point instructions. 854system.cpu0.commit.int_insts 508174699 # Number of committed integer instructions. 855system.cpu0.commit.function_calls 13889214 # Number of function calls committed. 856system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 857system.cpu0.commit.op_class_0::IntAlu 383941234 69.32% 69.32% # Class of committed instruction 858system.cpu0.commit.op_class_0::IntMult 1156077 0.21% 69.53% # Class of committed instruction 859system.cpu0.commit.op_class_0::IntDiv 59954 0.01% 69.54% # Class of committed instruction 860system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.54% # Class of committed instruction 861system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.54% # Class of committed instruction 862system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.54% # Class of committed instruction 863system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.54% # Class of committed instruction 864system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.54% # Class of committed instruction 865system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.54% # Class of committed instruction 866system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.54% # Class of committed instruction 867system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.54% # Class of committed instruction 868system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.54% # Class of committed instruction 869system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.54% # Class of committed instruction 870system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.54% # Class of committed instruction 871system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.54% # Class of committed instruction 872system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.54% # Class of committed instruction 873system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.54% # Class of committed instruction 874system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.54% # Class of committed instruction 875system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.54% # Class of committed instruction 876system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.54% # Class of committed instruction 877system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.54% # Class of committed instruction 878system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.54% # Class of committed instruction 879system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.54% # Class of committed instruction 880system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.54% # Class of committed instruction 881system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.54% # Class of committed instruction 882system.cpu0.commit.op_class_0::SimdFloatMisc 69071 0.01% 69.55% # Class of committed instruction 883system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.55% # Class of committed instruction 884system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.55% # Class of committed instruction 885system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.55% # Class of committed instruction 886system.cpu0.commit.op_class_0::MemRead 87802964 15.85% 85.41% # Class of committed instruction 887system.cpu0.commit.op_class_0::MemWrite 80829638 14.59% 100.00% # Class of committed instruction 888system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 889system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 890system.cpu0.commit.op_class_0::total 553858980 # Class of committed instruction 891system.cpu0.commit.bw_lim_events 13561171 # number cycles where commit BW limit reached 892system.cpu0.rob.rob_reads 1296549352 # The number of ROB reads 893system.cpu0.rob.rob_writes 1211163120 # The number of ROB writes 894system.cpu0.timesIdled 982435 # Number of times that the entire CPU went into an idle state and unscheduled itself 895system.cpu0.idleCycles 23747167 # Total number of cycles that the CPU has spent unscheduled due to idling 896system.cpu0.quiesceCycles 94022615466 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 897system.cpu0.committedInsts 471410910 # Number of Instructions Simulated 898system.cpu0.committedOps 553858980 # Number of Ops (including micro ops) Simulated 899system.cpu0.cpi 1.582515 # CPI: Cycles Per Instruction 900system.cpu0.cpi_total 1.582515 # CPI: Total CPI of All Threads 901system.cpu0.ipc 0.631905 # IPC: Instructions Per Cycle 902system.cpu0.ipc_total 0.631905 # IPC: Total IPC of All Threads 903system.cpu0.int_regfile_reads 694459704 # number of integer regfile reads 904system.cpu0.int_regfile_writes 413089219 # number of integer regfile writes 905system.cpu0.fp_regfile_reads 846069 # number of floating regfile reads 906system.cpu0.fp_regfile_writes 429660 # number of floating regfile writes 907system.cpu0.cc_regfile_reads 127998327 # number of cc regfile reads 908system.cpu0.cc_regfile_writes 128742208 # number of cc regfile writes 909system.cpu0.misc_regfile_reads 1288788249 # number of misc regfile reads 910system.cpu0.misc_regfile_writes 14832406 # number of misc regfile writes 911system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 912system.cpu0.dcache.tags.replacements 5793916 # number of replacements 913system.cpu0.dcache.tags.tagsinuse 505.305765 # Cycle average of tags in use 914system.cpu0.dcache.tags.total_refs 157106373 # Total number of references to valid blocks. 915system.cpu0.dcache.tags.sampled_refs 5794427 # Sample count of references to valid blocks. 916system.cpu0.dcache.tags.avg_refs 27.113358 # Average number of references to valid blocks. 917system.cpu0.dcache.tags.warmup_cycle 1908955000 # Cycle when the warmup percentage was hit. 918system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.305765 # Average occupied blocks per requestor 919system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986925 # Average percentage of cache occupancy 920system.cpu0.dcache.tags.occ_percent::total 0.986925 # Average percentage of cache occupancy 921system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 922system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 923system.cpu0.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id 924system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id 925system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 926system.cpu0.dcache.tags.tag_accesses 349540400 # Number of tag accesses 927system.cpu0.dcache.tags.data_accesses 349540400 # Number of data accesses 928system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 929system.cpu0.dcache.ReadReq_hits::cpu0.data 81616032 # number of ReadReq hits 930system.cpu0.dcache.ReadReq_hits::total 81616032 # number of ReadReq hits 931system.cpu0.dcache.WriteReq_hits::cpu0.data 70522769 # number of WriteReq hits 932system.cpu0.dcache.WriteReq_hits::total 70522769 # number of WriteReq hits 933system.cpu0.dcache.SoftPFReq_hits::cpu0.data 213045 # number of SoftPFReq hits 934system.cpu0.dcache.SoftPFReq_hits::total 213045 # number of SoftPFReq hits 935system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259663 # number of WriteLineReq hits 936system.cpu0.dcache.WriteLineReq_hits::total 259663 # number of WriteLineReq hits 937system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1810689 # number of LoadLockedReq hits 938system.cpu0.dcache.LoadLockedReq_hits::total 1810689 # number of LoadLockedReq hits 939system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1836259 # number of StoreCondReq hits 940system.cpu0.dcache.StoreCondReq_hits::total 1836259 # number of StoreCondReq hits 941system.cpu0.dcache.demand_hits::cpu0.data 152398464 # number of demand (read+write) hits 942system.cpu0.dcache.demand_hits::total 152398464 # number of demand (read+write) hits 943system.cpu0.dcache.overall_hits::cpu0.data 152611509 # number of overall hits 944system.cpu0.dcache.overall_hits::total 152611509 # number of overall hits 945system.cpu0.dcache.ReadReq_misses::cpu0.data 6448823 # number of ReadReq misses 946system.cpu0.dcache.ReadReq_misses::total 6448823 # number of ReadReq misses 947system.cpu0.dcache.WriteReq_misses::cpu0.data 7191873 # number of WriteReq misses 948system.cpu0.dcache.WriteReq_misses::total 7191873 # number of WriteReq misses 949system.cpu0.dcache.SoftPFReq_misses::cpu0.data 676181 # number of SoftPFReq misses 950system.cpu0.dcache.SoftPFReq_misses::total 676181 # number of SoftPFReq misses 951system.cpu0.dcache.WriteLineReq_misses::cpu0.data 810826 # number of WriteLineReq misses 952system.cpu0.dcache.WriteLineReq_misses::total 810826 # number of WriteLineReq misses 953system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 247493 # number of LoadLockedReq misses 954system.cpu0.dcache.LoadLockedReq_misses::total 247493 # number of LoadLockedReq misses 955system.cpu0.dcache.StoreCondReq_misses::cpu0.data 187335 # number of StoreCondReq misses 956system.cpu0.dcache.StoreCondReq_misses::total 187335 # number of StoreCondReq misses 957system.cpu0.dcache.demand_misses::cpu0.data 14451522 # number of demand (read+write) misses 958system.cpu0.dcache.demand_misses::total 14451522 # number of demand (read+write) misses 959system.cpu0.dcache.overall_misses::cpu0.data 15127703 # number of overall misses 960system.cpu0.dcache.overall_misses::total 15127703 # number of overall misses 961system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 92981912000 # number of ReadReq miss cycles 962system.cpu0.dcache.ReadReq_miss_latency::total 92981912000 # number of ReadReq miss cycles 963system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 133998931168 # number of WriteReq miss cycles 964system.cpu0.dcache.WriteReq_miss_latency::total 133998931168 # number of WriteReq miss cycles 965system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 29936196189 # number of WriteLineReq miss cycles 966system.cpu0.dcache.WriteLineReq_miss_latency::total 29936196189 # number of WriteLineReq miss cycles 967system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3415607500 # number of LoadLockedReq miss cycles 968system.cpu0.dcache.LoadLockedReq_miss_latency::total 3415607500 # number of LoadLockedReq miss cycles 969system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4687136000 # number of StoreCondReq miss cycles 970system.cpu0.dcache.StoreCondReq_miss_latency::total 4687136000 # number of StoreCondReq miss cycles 971system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3788500 # number of StoreCondFailReq miss cycles 972system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3788500 # number of StoreCondFailReq miss cycles 973system.cpu0.dcache.demand_miss_latency::cpu0.data 256917039357 # number of demand (read+write) miss cycles 974system.cpu0.dcache.demand_miss_latency::total 256917039357 # number of demand (read+write) miss cycles 975system.cpu0.dcache.overall_miss_latency::cpu0.data 256917039357 # number of overall miss cycles 976system.cpu0.dcache.overall_miss_latency::total 256917039357 # number of overall miss cycles 977system.cpu0.dcache.ReadReq_accesses::cpu0.data 88064855 # number of ReadReq accesses(hits+misses) 978system.cpu0.dcache.ReadReq_accesses::total 88064855 # number of ReadReq accesses(hits+misses) 979system.cpu0.dcache.WriteReq_accesses::cpu0.data 77714642 # number of WriteReq accesses(hits+misses) 980system.cpu0.dcache.WriteReq_accesses::total 77714642 # number of WriteReq accesses(hits+misses) 981system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 889226 # number of SoftPFReq accesses(hits+misses) 982system.cpu0.dcache.SoftPFReq_accesses::total 889226 # number of SoftPFReq accesses(hits+misses) 983system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1070489 # number of WriteLineReq accesses(hits+misses) 984system.cpu0.dcache.WriteLineReq_accesses::total 1070489 # number of WriteLineReq accesses(hits+misses) 985system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2058182 # number of LoadLockedReq accesses(hits+misses) 986system.cpu0.dcache.LoadLockedReq_accesses::total 2058182 # number of LoadLockedReq accesses(hits+misses) 987system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2023594 # number of StoreCondReq accesses(hits+misses) 988system.cpu0.dcache.StoreCondReq_accesses::total 2023594 # number of StoreCondReq accesses(hits+misses) 989system.cpu0.dcache.demand_accesses::cpu0.data 166849986 # number of demand (read+write) accesses 990system.cpu0.dcache.demand_accesses::total 166849986 # number of demand (read+write) accesses 991system.cpu0.dcache.overall_accesses::cpu0.data 167739212 # number of overall (read+write) accesses 992system.cpu0.dcache.overall_accesses::total 167739212 # number of overall (read+write) accesses 993system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.073228 # miss rate for ReadReq accesses 994system.cpu0.dcache.ReadReq_miss_rate::total 0.073228 # miss rate for ReadReq accesses 995system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.092542 # miss rate for WriteReq accesses 996system.cpu0.dcache.WriteReq_miss_rate::total 0.092542 # miss rate for WriteReq accesses 997system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760415 # miss rate for SoftPFReq accesses 998system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760415 # miss rate for SoftPFReq accesses 999system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.757435 # miss rate for WriteLineReq accesses 1000system.cpu0.dcache.WriteLineReq_miss_rate::total 0.757435 # miss rate for WriteLineReq accesses 1001system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.120248 # miss rate for LoadLockedReq accesses 1002system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.120248 # miss rate for LoadLockedReq accesses 1003system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.092575 # miss rate for StoreCondReq accesses 1004system.cpu0.dcache.StoreCondReq_miss_rate::total 0.092575 # miss rate for StoreCondReq accesses 1005system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086614 # miss rate for demand accesses 1006system.cpu0.dcache.demand_miss_rate::total 0.086614 # miss rate for demand accesses 1007system.cpu0.dcache.overall_miss_rate::cpu0.data 0.090186 # miss rate for overall accesses 1008system.cpu0.dcache.overall_miss_rate::total 0.090186 # miss rate for overall accesses 1009system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14418.431394 # average ReadReq miss latency 1010system.cpu0.dcache.ReadReq_avg_miss_latency::total 14418.431394 # average ReadReq miss latency 1011system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18631.993525 # average WriteReq miss latency 1012system.cpu0.dcache.WriteReq_avg_miss_latency::total 18631.993525 # average WriteReq miss latency 1013system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 36920.616987 # average WriteLineReq miss latency 1014system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 36920.616987 # average WriteLineReq miss latency 1015system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13800.824670 # average LoadLockedReq miss latency 1016system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13800.824670 # average LoadLockedReq miss latency 1017system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25020.076334 # average StoreCondReq miss latency 1018system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25020.076334 # average StoreCondReq miss latency 1019system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1020system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1021system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17777.853389 # average overall miss latency 1022system.cpu0.dcache.demand_avg_miss_latency::total 17777.853389 # average overall miss latency 1023system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16983.215453 # average overall miss latency 1024system.cpu0.dcache.overall_avg_miss_latency::total 16983.215453 # average overall miss latency 1025system.cpu0.dcache.blocked_cycles::no_mshrs 9060649 # number of cycles access was blocked 1026system.cpu0.dcache.blocked_cycles::no_targets 19650869 # number of cycles access was blocked 1027system.cpu0.dcache.blocked::no_mshrs 747322 # number of cycles access was blocked 1028system.cpu0.dcache.blocked::no_targets 698056 # number of cycles access was blocked 1029system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.124157 # average number of cycles each access was blocked 1030system.cpu0.dcache.avg_blocked_cycles::no_targets 28.150849 # average number of cycles each access was blocked 1031system.cpu0.dcache.writebacks::writebacks 5793928 # number of writebacks 1032system.cpu0.dcache.writebacks::total 5793928 # number of writebacks 1033system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3323367 # number of ReadReq MSHR hits 1034system.cpu0.dcache.ReadReq_mshr_hits::total 3323367 # number of ReadReq MSHR hits 1035system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5758852 # number of WriteReq MSHR hits 1036system.cpu0.dcache.WriteReq_mshr_hits::total 5758852 # number of WriteReq MSHR hits 1037system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4670 # number of WriteLineReq MSHR hits 1038system.cpu0.dcache.WriteLineReq_mshr_hits::total 4670 # number of WriteLineReq MSHR hits 1039system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 128237 # number of LoadLockedReq MSHR hits 1040system.cpu0.dcache.LoadLockedReq_mshr_hits::total 128237 # number of LoadLockedReq MSHR hits 1041system.cpu0.dcache.demand_mshr_hits::cpu0.data 9086889 # number of demand (read+write) MSHR hits 1042system.cpu0.dcache.demand_mshr_hits::total 9086889 # number of demand (read+write) MSHR hits 1043system.cpu0.dcache.overall_mshr_hits::cpu0.data 9086889 # number of overall MSHR hits 1044system.cpu0.dcache.overall_mshr_hits::total 9086889 # number of overall MSHR hits 1045system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3125456 # number of ReadReq MSHR misses 1046system.cpu0.dcache.ReadReq_mshr_misses::total 3125456 # number of ReadReq MSHR misses 1047system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1433021 # number of WriteReq MSHR misses 1048system.cpu0.dcache.WriteReq_mshr_misses::total 1433021 # number of WriteReq MSHR misses 1049system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 669278 # number of SoftPFReq MSHR misses 1050system.cpu0.dcache.SoftPFReq_mshr_misses::total 669278 # number of SoftPFReq MSHR misses 1051system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 806156 # number of WriteLineReq MSHR misses 1052system.cpu0.dcache.WriteLineReq_mshr_misses::total 806156 # number of WriteLineReq MSHR misses 1053system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 119256 # number of LoadLockedReq MSHR misses 1054system.cpu0.dcache.LoadLockedReq_mshr_misses::total 119256 # number of LoadLockedReq MSHR misses 1055system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 187331 # number of StoreCondReq MSHR misses 1056system.cpu0.dcache.StoreCondReq_mshr_misses::total 187331 # number of StoreCondReq MSHR misses 1057system.cpu0.dcache.demand_mshr_misses::cpu0.data 5364633 # number of demand (read+write) MSHR misses 1058system.cpu0.dcache.demand_mshr_misses::total 5364633 # number of demand (read+write) MSHR misses 1059system.cpu0.dcache.overall_mshr_misses::cpu0.data 6033911 # number of overall MSHR misses 1060system.cpu0.dcache.overall_mshr_misses::total 6033911 # number of overall MSHR misses 1061system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32527 # number of ReadReq MSHR uncacheable 1062system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32527 # number of ReadReq MSHR uncacheable 1063system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32351 # number of WriteReq MSHR uncacheable 1064system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32351 # number of WriteReq MSHR uncacheable 1065system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 64878 # number of overall MSHR uncacheable misses 1066system.cpu0.dcache.overall_mshr_uncacheable_misses::total 64878 # number of overall MSHR uncacheable misses 1067system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43142423000 # number of ReadReq MSHR miss cycles 1068system.cpu0.dcache.ReadReq_mshr_miss_latency::total 43142423000 # number of ReadReq MSHR miss cycles 1069system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30169010620 # number of WriteReq MSHR miss cycles 1070system.cpu0.dcache.WriteReq_mshr_miss_latency::total 30169010620 # number of WriteReq MSHR miss cycles 1071system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14964455000 # number of SoftPFReq MSHR miss cycles 1072system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14964455000 # number of SoftPFReq MSHR miss cycles 1073system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28947099689 # number of WriteLineReq MSHR miss cycles 1074system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28947099689 # number of WriteLineReq MSHR miss cycles 1075system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1564593500 # number of LoadLockedReq MSHR miss cycles 1076system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1564593500 # number of LoadLockedReq MSHR miss cycles 1077system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4499876000 # number of StoreCondReq MSHR miss cycles 1078system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4499876000 # number of StoreCondReq MSHR miss cycles 1079system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3717500 # number of StoreCondFailReq MSHR miss cycles 1080system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3717500 # number of StoreCondFailReq MSHR miss cycles 1081system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 102258533309 # number of demand (read+write) MSHR miss cycles 1082system.cpu0.dcache.demand_mshr_miss_latency::total 102258533309 # number of demand (read+write) MSHR miss cycles 1083system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 117222988309 # number of overall MSHR miss cycles 1084system.cpu0.dcache.overall_mshr_miss_latency::total 117222988309 # number of overall MSHR miss cycles 1085system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6208668000 # number of ReadReq MSHR uncacheable cycles 1086system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6208668000 # number of ReadReq MSHR uncacheable cycles 1087system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6208668000 # number of overall MSHR uncacheable cycles 1088system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6208668000 # number of overall MSHR uncacheable cycles 1089system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035490 # mshr miss rate for ReadReq accesses 1090system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035490 # mshr miss rate for ReadReq accesses 1091system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018440 # mshr miss rate for WriteReq accesses 1092system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018440 # mshr miss rate for WriteReq accesses 1093system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.752652 # mshr miss rate for SoftPFReq accesses 1094system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.752652 # mshr miss rate for SoftPFReq accesses 1095system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.753073 # mshr miss rate for WriteLineReq accesses 1096system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.753073 # mshr miss rate for WriteLineReq accesses 1097system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057942 # mshr miss rate for LoadLockedReq accesses 1098system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057942 # mshr miss rate for LoadLockedReq accesses 1099system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092573 # mshr miss rate for StoreCondReq accesses 1100system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092573 # mshr miss rate for StoreCondReq accesses 1101system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032152 # mshr miss rate for demand accesses 1102system.cpu0.dcache.demand_mshr_miss_rate::total 0.032152 # mshr miss rate for demand accesses 1103system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.035972 # mshr miss rate for overall accesses 1104system.cpu0.dcache.overall_mshr_miss_rate::total 0.035972 # mshr miss rate for overall accesses 1105system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13803.561144 # average ReadReq mshr miss latency 1106system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13803.561144 # average ReadReq mshr miss latency 1107system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21052.734482 # average WriteReq mshr miss latency 1108system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21052.734482 # average WriteReq mshr miss latency 1109system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22359.101898 # average SoftPFReq mshr miss latency 1110system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22359.101898 # average SoftPFReq mshr miss latency 1111system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 35907.565892 # average WriteLineReq mshr miss latency 1112system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 35907.565892 # average WriteLineReq mshr miss latency 1113system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13119.620816 # average LoadLockedReq mshr miss latency 1114system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13119.620816 # average LoadLockedReq mshr miss latency 1115system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24020.989585 # average StoreCondReq mshr miss latency 1116system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24020.989585 # average StoreCondReq mshr miss latency 1117system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1118system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1119system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19061.608373 # average overall mshr miss latency 1120system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19061.608373 # average overall mshr miss latency 1121system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19427.364492 # average overall mshr miss latency 1122system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19427.364492 # average overall mshr miss latency 1123system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190877.363421 # average ReadReq mshr uncacheable latency 1124system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190877.363421 # average ReadReq mshr uncacheable latency 1125system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95697.586239 # average overall mshr uncacheable latency 1126system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95697.586239 # average overall mshr uncacheable latency 1127system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 1128system.cpu0.icache.tags.replacements 6136519 # number of replacements 1129system.cpu0.icache.tags.tagsinuse 511.962391 # Cycle average of tags in use 1130system.cpu0.icache.tags.total_refs 209807209 # Total number of references to valid blocks. 1131system.cpu0.icache.tags.sampled_refs 6137031 # Sample count of references to valid blocks. 1132system.cpu0.icache.tags.avg_refs 34.187086 # Average number of references to valid blocks. 1133system.cpu0.icache.tags.warmup_cycle 12886295000 # Cycle when the warmup percentage was hit. 1134system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.962391 # Average occupied blocks per requestor 1135system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999927 # Average percentage of cache occupancy 1136system.cpu0.icache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy 1137system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1138system.cpu0.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id 1139system.cpu0.icache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id 1140system.cpu0.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id 1141system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1142system.cpu0.icache.tags.tag_accesses 438728804 # Number of tag accesses 1143system.cpu0.icache.tags.data_accesses 438728804 # Number of data accesses 1144system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 1145system.cpu0.icache.ReadReq_hits::cpu0.inst 209807209 # number of ReadReq hits 1146system.cpu0.icache.ReadReq_hits::total 209807209 # number of ReadReq hits 1147system.cpu0.icache.demand_hits::cpu0.inst 209807209 # number of demand (read+write) hits 1148system.cpu0.icache.demand_hits::total 209807209 # number of demand (read+write) hits 1149system.cpu0.icache.overall_hits::cpu0.inst 209807209 # number of overall hits 1150system.cpu0.icache.overall_hits::total 209807209 # number of overall hits 1151system.cpu0.icache.ReadReq_misses::cpu0.inst 6488653 # number of ReadReq misses 1152system.cpu0.icache.ReadReq_misses::total 6488653 # number of ReadReq misses 1153system.cpu0.icache.demand_misses::cpu0.inst 6488653 # number of demand (read+write) misses 1154system.cpu0.icache.demand_misses::total 6488653 # number of demand (read+write) misses 1155system.cpu0.icache.overall_misses::cpu0.inst 6488653 # number of overall misses 1156system.cpu0.icache.overall_misses::total 6488653 # number of overall misses 1157system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 69596700450 # number of ReadReq miss cycles 1158system.cpu0.icache.ReadReq_miss_latency::total 69596700450 # number of ReadReq miss cycles 1159system.cpu0.icache.demand_miss_latency::cpu0.inst 69596700450 # number of demand (read+write) miss cycles 1160system.cpu0.icache.demand_miss_latency::total 69596700450 # number of demand (read+write) miss cycles 1161system.cpu0.icache.overall_miss_latency::cpu0.inst 69596700450 # number of overall miss cycles 1162system.cpu0.icache.overall_miss_latency::total 69596700450 # number of overall miss cycles 1163system.cpu0.icache.ReadReq_accesses::cpu0.inst 216295862 # number of ReadReq accesses(hits+misses) 1164system.cpu0.icache.ReadReq_accesses::total 216295862 # number of ReadReq accesses(hits+misses) 1165system.cpu0.icache.demand_accesses::cpu0.inst 216295862 # number of demand (read+write) accesses 1166system.cpu0.icache.demand_accesses::total 216295862 # number of demand (read+write) accesses 1167system.cpu0.icache.overall_accesses::cpu0.inst 216295862 # number of overall (read+write) accesses 1168system.cpu0.icache.overall_accesses::total 216295862 # number of overall (read+write) accesses 1169system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029999 # miss rate for ReadReq accesses 1170system.cpu0.icache.ReadReq_miss_rate::total 0.029999 # miss rate for ReadReq accesses 1171system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029999 # miss rate for demand accesses 1172system.cpu0.icache.demand_miss_rate::total 0.029999 # miss rate for demand accesses 1173system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029999 # miss rate for overall accesses 1174system.cpu0.icache.overall_miss_rate::total 0.029999 # miss rate for overall accesses 1175system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10725.908821 # average ReadReq miss latency 1176system.cpu0.icache.ReadReq_avg_miss_latency::total 10725.908821 # average ReadReq miss latency 1177system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10725.908821 # average overall miss latency 1178system.cpu0.icache.demand_avg_miss_latency::total 10725.908821 # average overall miss latency 1179system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10725.908821 # average overall miss latency 1180system.cpu0.icache.overall_avg_miss_latency::total 10725.908821 # average overall miss latency 1181system.cpu0.icache.blocked_cycles::no_mshrs 10132412 # number of cycles access was blocked 1182system.cpu0.icache.blocked_cycles::no_targets 436 # number of cycles access was blocked 1183system.cpu0.icache.blocked::no_mshrs 737599 # number of cycles access was blocked 1184system.cpu0.icache.blocked::no_targets 9 # number of cycles access was blocked 1185system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.737020 # average number of cycles each access was blocked 1186system.cpu0.icache.avg_blocked_cycles::no_targets 48.444444 # average number of cycles each access was blocked 1187system.cpu0.icache.writebacks::writebacks 6136519 # number of writebacks 1188system.cpu0.icache.writebacks::total 6136519 # number of writebacks 1189system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 351573 # number of ReadReq MSHR hits 1190system.cpu0.icache.ReadReq_mshr_hits::total 351573 # number of ReadReq MSHR hits 1191system.cpu0.icache.demand_mshr_hits::cpu0.inst 351573 # number of demand (read+write) MSHR hits 1192system.cpu0.icache.demand_mshr_hits::total 351573 # number of demand (read+write) MSHR hits 1193system.cpu0.icache.overall_mshr_hits::cpu0.inst 351573 # number of overall MSHR hits 1194system.cpu0.icache.overall_mshr_hits::total 351573 # number of overall MSHR hits 1195system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6137080 # number of ReadReq MSHR misses 1196system.cpu0.icache.ReadReq_mshr_misses::total 6137080 # number of ReadReq MSHR misses 1197system.cpu0.icache.demand_mshr_misses::cpu0.inst 6137080 # number of demand (read+write) MSHR misses 1198system.cpu0.icache.demand_mshr_misses::total 6137080 # number of demand (read+write) MSHR misses 1199system.cpu0.icache.overall_mshr_misses::cpu0.inst 6137080 # number of overall MSHR misses 1200system.cpu0.icache.overall_mshr_misses::total 6137080 # number of overall MSHR misses 1201system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 1202system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable 1203system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 1204system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses 1205system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 62984871633 # number of ReadReq MSHR miss cycles 1206system.cpu0.icache.ReadReq_mshr_miss_latency::total 62984871633 # number of ReadReq MSHR miss cycles 1207system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 62984871633 # number of demand (read+write) MSHR miss cycles 1208system.cpu0.icache.demand_mshr_miss_latency::total 62984871633 # number of demand (read+write) MSHR miss cycles 1209system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 62984871633 # number of overall MSHR miss cycles 1210system.cpu0.icache.overall_mshr_miss_latency::total 62984871633 # number of overall MSHR miss cycles 1211system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of ReadReq MSHR uncacheable cycles 1212system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1885677498 # number of ReadReq MSHR uncacheable cycles 1213system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of overall MSHR uncacheable cycles 1214system.cpu0.icache.overall_mshr_uncacheable_latency::total 1885677498 # number of overall MSHR uncacheable cycles 1215system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028374 # mshr miss rate for ReadReq accesses 1216system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028374 # mshr miss rate for ReadReq accesses 1217system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028374 # mshr miss rate for demand accesses 1218system.cpu0.icache.demand_mshr_miss_rate::total 0.028374 # mshr miss rate for demand accesses 1219system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028374 # mshr miss rate for overall accesses 1220system.cpu0.icache.overall_mshr_miss_rate::total 0.028374 # mshr miss rate for overall accesses 1221system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average ReadReq mshr miss latency 1222system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10263.003193 # average ReadReq mshr miss latency 1223system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency 1224system.cpu0.icache.demand_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency 1225system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency 1226system.cpu0.icache.overall_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency 1227system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average ReadReq mshr uncacheable latency 1228system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753 # average ReadReq mshr uncacheable latency 1229system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average overall mshr uncacheable latency 1230system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753 # average overall mshr uncacheable latency 1231system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 1232system.cpu0.l2cache.prefetcher.num_hwpf_issued 7743703 # number of hwpf issued 1233system.cpu0.l2cache.prefetcher.pfIdentified 7754051 # number of prefetch candidates identified 1234system.cpu0.l2cache.prefetcher.pfBufferHit 9277 # number of redundant prefetches already in prefetch queue 1235system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1236system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1237system.cpu0.l2cache.prefetcher.pfSpanPage 1008365 # number of prefetches not generated due to page crossing 1238system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 1239system.cpu0.l2cache.tags.replacements 2565485 # number of replacements 1240system.cpu0.l2cache.tags.tagsinuse 15956.741738 # Cycle average of tags in use 1241system.cpu0.l2cache.tags.total_refs 17408441 # Total number of references to valid blocks. 1242system.cpu0.l2cache.tags.sampled_refs 2581334 # Sample count of references to valid blocks. 1243system.cpu0.l2cache.tags.avg_refs 6.743971 # Average number of references to valid blocks. 1244system.cpu0.l2cache.tags.warmup_cycle 2212473000 # Cycle when the warmup percentage was hit. 1245system.cpu0.l2cache.tags.occ_blocks::writebacks 14849.648482 # Average occupied blocks per requestor 1246system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 36.124813 # Average occupied blocks per requestor 1247system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 23.448036 # Average occupied blocks per requestor 1248system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000032 # Average occupied blocks per requestor 1249system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1047.520376 # Average occupied blocks per requestor 1250system.cpu0.l2cache.tags.occ_percent::writebacks 0.906351 # Average percentage of cache occupancy 1251system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002205 # Average percentage of cache occupancy 1252system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001431 # Average percentage of cache occupancy 1253system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy 1254system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063936 # Average percentage of cache occupancy 1255system.cpu0.l2cache.tags.occ_percent::total 0.973922 # Average percentage of cache occupancy 1256system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1203 # Occupied blocks per task id 1257system.cpu0.l2cache.tags.occ_task_id_blocks::1023 77 # Occupied blocks per task id 1258system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14569 # Occupied blocks per task id 1259system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id 1260system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 211 # Occupied blocks per task id 1261system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 564 # Occupied blocks per task id 1262system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 414 # Occupied blocks per task id 1263system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 59 # Occupied blocks per task id 1264system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 1265system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id 1266system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id 1267system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1288 # Occupied blocks per task id 1268system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4722 # Occupied blocks per task id 1269system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4695 # Occupied blocks per task id 1270system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3741 # Occupied blocks per task id 1271system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.073425 # Percentage of cache occupancy per task id 1272system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id 1273system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.889221 # Percentage of cache occupancy per task id 1274system.cpu0.l2cache.tags.tag_accesses 408243228 # Number of tag accesses 1275system.cpu0.l2cache.tags.data_accesses 408243228 # Number of data accesses 1276system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 1277system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 539952 # number of ReadReq hits 1278system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 183800 # number of ReadReq hits 1279system.cpu0.l2cache.ReadReq_hits::total 723752 # number of ReadReq hits 1280system.cpu0.l2cache.WritebackDirty_hits::writebacks 3863126 # number of WritebackDirty hits 1281system.cpu0.l2cache.WritebackDirty_hits::total 3863126 # number of WritebackDirty hits 1282system.cpu0.l2cache.WritebackClean_hits::writebacks 8065215 # number of WritebackClean hits 1283system.cpu0.l2cache.WritebackClean_hits::total 8065215 # number of WritebackClean hits 1284system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 386 # number of UpgradeReq hits 1285system.cpu0.l2cache.UpgradeReq_hits::total 386 # number of UpgradeReq hits 1286system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 6 # number of SCUpgradeReq hits 1287system.cpu0.l2cache.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits 1288system.cpu0.l2cache.ReadExReq_hits::cpu0.data 895474 # number of ReadExReq hits 1289system.cpu0.l2cache.ReadExReq_hits::total 895474 # number of ReadExReq hits 1290system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5563145 # number of ReadCleanReq hits 1291system.cpu0.l2cache.ReadCleanReq_hits::total 5563145 # number of ReadCleanReq hits 1292system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2937118 # number of ReadSharedReq hits 1293system.cpu0.l2cache.ReadSharedReq_hits::total 2937118 # number of ReadSharedReq hits 1294system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 202987 # number of InvalidateReq hits 1295system.cpu0.l2cache.InvalidateReq_hits::total 202987 # number of InvalidateReq hits 1296system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 539952 # number of demand (read+write) hits 1297system.cpu0.l2cache.demand_hits::cpu0.itb.walker 183800 # number of demand (read+write) hits 1298system.cpu0.l2cache.demand_hits::cpu0.inst 5563145 # number of demand (read+write) hits 1299system.cpu0.l2cache.demand_hits::cpu0.data 3832592 # number of demand (read+write) hits 1300system.cpu0.l2cache.demand_hits::total 10119489 # number of demand (read+write) hits 1301system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 539952 # number of overall hits 1302system.cpu0.l2cache.overall_hits::cpu0.itb.walker 183800 # number of overall hits 1303system.cpu0.l2cache.overall_hits::cpu0.inst 5563145 # number of overall hits 1304system.cpu0.l2cache.overall_hits::cpu0.data 3832592 # number of overall hits 1305system.cpu0.l2cache.overall_hits::total 10119489 # number of overall hits 1306system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10772 # number of ReadReq misses 1307system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7627 # number of ReadReq misses 1308system.cpu0.l2cache.ReadReq_misses::total 18399 # number of ReadReq misses 1309system.cpu0.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses 1310system.cpu0.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses 1311system.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 1312system.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses 1313system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 260447 # number of UpgradeReq misses 1314system.cpu0.l2cache.UpgradeReq_misses::total 260447 # number of UpgradeReq misses 1315system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 187318 # number of SCUpgradeReq misses 1316system.cpu0.l2cache.SCUpgradeReq_misses::total 187318 # number of SCUpgradeReq misses 1317system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # number of SCUpgradeFailReq misses 1318system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses 1319system.cpu0.l2cache.ReadExReq_misses::cpu0.data 288236 # number of ReadExReq misses 1320system.cpu0.l2cache.ReadExReq_misses::total 288236 # number of ReadExReq misses 1321system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 573862 # number of ReadCleanReq misses 1322system.cpu0.l2cache.ReadCleanReq_misses::total 573862 # number of ReadCleanReq misses 1323system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 973549 # number of ReadSharedReq misses 1324system.cpu0.l2cache.ReadSharedReq_misses::total 973549 # number of ReadSharedReq misses 1325system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 600983 # number of InvalidateReq misses 1326system.cpu0.l2cache.InvalidateReq_misses::total 600983 # number of InvalidateReq misses 1327system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10772 # number of demand (read+write) misses 1328system.cpu0.l2cache.demand_misses::cpu0.itb.walker 7627 # number of demand (read+write) misses 1329system.cpu0.l2cache.demand_misses::cpu0.inst 573862 # number of demand (read+write) misses 1330system.cpu0.l2cache.demand_misses::cpu0.data 1261785 # number of demand (read+write) misses 1331system.cpu0.l2cache.demand_misses::total 1854046 # number of demand (read+write) misses 1332system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10772 # number of overall misses 1333system.cpu0.l2cache.overall_misses::cpu0.itb.walker 7627 # number of overall misses 1334system.cpu0.l2cache.overall_misses::cpu0.inst 573862 # number of overall misses 1335system.cpu0.l2cache.overall_misses::cpu0.data 1261785 # number of overall misses 1336system.cpu0.l2cache.overall_misses::total 1854046 # number of overall misses 1337system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 369514500 # number of ReadReq miss cycles 1338system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 247873000 # number of ReadReq miss cycles 1339system.cpu0.l2cache.ReadReq_miss_latency::total 617387500 # number of ReadReq miss cycles 1340system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2108131500 # number of UpgradeReq miss cycles 1341system.cpu0.l2cache.UpgradeReq_miss_latency::total 2108131500 # number of UpgradeReq miss cycles 1342system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1419046500 # number of SCUpgradeReq miss cycles 1343system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1419046500 # number of SCUpgradeReq miss cycles 1344system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3609499 # number of SCUpgradeFailReq miss cycles 1345system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3609499 # number of SCUpgradeFailReq miss cycles 1346system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 14578954500 # number of ReadExReq miss cycles 1347system.cpu0.l2cache.ReadExReq_miss_latency::total 14578954500 # number of ReadExReq miss cycles 1348system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 20073597500 # number of ReadCleanReq miss cycles 1349system.cpu0.l2cache.ReadCleanReq_miss_latency::total 20073597500 # number of ReadCleanReq miss cycles 1350system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 34202997471 # number of ReadSharedReq miss cycles 1351system.cpu0.l2cache.ReadSharedReq_miss_latency::total 34202997471 # number of ReadSharedReq miss cycles 1352system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 348158000 # number of InvalidateReq miss cycles 1353system.cpu0.l2cache.InvalidateReq_miss_latency::total 348158000 # number of InvalidateReq miss cycles 1354system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 369514500 # number of demand (read+write) miss cycles 1355system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 247873000 # number of demand (read+write) miss cycles 1356system.cpu0.l2cache.demand_miss_latency::cpu0.inst 20073597500 # number of demand (read+write) miss cycles 1357system.cpu0.l2cache.demand_miss_latency::cpu0.data 48781951971 # number of demand (read+write) miss cycles 1358system.cpu0.l2cache.demand_miss_latency::total 69472936971 # number of demand (read+write) miss cycles 1359system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 369514500 # number of overall miss cycles 1360system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 247873000 # number of overall miss cycles 1361system.cpu0.l2cache.overall_miss_latency::cpu0.inst 20073597500 # number of overall miss cycles 1362system.cpu0.l2cache.overall_miss_latency::cpu0.data 48781951971 # number of overall miss cycles 1363system.cpu0.l2cache.overall_miss_latency::total 69472936971 # number of overall miss cycles 1364system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 550724 # number of ReadReq accesses(hits+misses) 1365system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 191427 # number of ReadReq accesses(hits+misses) 1366system.cpu0.l2cache.ReadReq_accesses::total 742151 # number of ReadReq accesses(hits+misses) 1367system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3863128 # number of WritebackDirty accesses(hits+misses) 1368system.cpu0.l2cache.WritebackDirty_accesses::total 3863128 # number of WritebackDirty accesses(hits+misses) 1369system.cpu0.l2cache.WritebackClean_accesses::writebacks 8065216 # number of WritebackClean accesses(hits+misses) 1370system.cpu0.l2cache.WritebackClean_accesses::total 8065216 # number of WritebackClean accesses(hits+misses) 1371system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 260833 # number of UpgradeReq accesses(hits+misses) 1372system.cpu0.l2cache.UpgradeReq_accesses::total 260833 # number of UpgradeReq accesses(hits+misses) 1373system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 187324 # number of SCUpgradeReq accesses(hits+misses) 1374system.cpu0.l2cache.SCUpgradeReq_accesses::total 187324 # number of SCUpgradeReq accesses(hits+misses) 1375system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 7 # number of SCUpgradeFailReq accesses(hits+misses) 1376system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) 1377system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1183710 # number of ReadExReq accesses(hits+misses) 1378system.cpu0.l2cache.ReadExReq_accesses::total 1183710 # number of ReadExReq accesses(hits+misses) 1379system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6137007 # number of ReadCleanReq accesses(hits+misses) 1380system.cpu0.l2cache.ReadCleanReq_accesses::total 6137007 # number of ReadCleanReq accesses(hits+misses) 1381system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3910667 # number of ReadSharedReq accesses(hits+misses) 1382system.cpu0.l2cache.ReadSharedReq_accesses::total 3910667 # number of ReadSharedReq accesses(hits+misses) 1383system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 803970 # number of InvalidateReq accesses(hits+misses) 1384system.cpu0.l2cache.InvalidateReq_accesses::total 803970 # number of InvalidateReq accesses(hits+misses) 1385system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 550724 # number of demand (read+write) accesses 1386system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 191427 # number of demand (read+write) accesses 1387system.cpu0.l2cache.demand_accesses::cpu0.inst 6137007 # number of demand (read+write) accesses 1388system.cpu0.l2cache.demand_accesses::cpu0.data 5094377 # number of demand (read+write) accesses 1389system.cpu0.l2cache.demand_accesses::total 11973535 # number of demand (read+write) accesses 1390system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 550724 # number of overall (read+write) accesses 1391system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 191427 # number of overall (read+write) accesses 1392system.cpu0.l2cache.overall_accesses::cpu0.inst 6137007 # number of overall (read+write) accesses 1393system.cpu0.l2cache.overall_accesses::cpu0.data 5094377 # number of overall (read+write) accesses 1394system.cpu0.l2cache.overall_accesses::total 11973535 # number of overall (read+write) accesses 1395system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.019560 # miss rate for ReadReq accesses 1396system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.039843 # miss rate for ReadReq accesses 1397system.cpu0.l2cache.ReadReq_miss_rate::total 0.024791 # miss rate for ReadReq accesses 1398system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses 1399system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses 1400system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 1401system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 1402system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998520 # miss rate for UpgradeReq accesses 1403system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998520 # miss rate for UpgradeReq accesses 1404system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999968 # miss rate for SCUpgradeReq accesses 1405system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999968 # miss rate for SCUpgradeReq accesses 1406system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1407system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1408system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.243502 # miss rate for ReadExReq accesses 1409system.cpu0.l2cache.ReadExReq_miss_rate::total 0.243502 # miss rate for ReadExReq accesses 1410system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.093508 # miss rate for ReadCleanReq accesses 1411system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.093508 # miss rate for ReadCleanReq accesses 1412system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.248947 # miss rate for ReadSharedReq accesses 1413system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.248947 # miss rate for ReadSharedReq accesses 1414system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.747519 # miss rate for InvalidateReq accesses 1415system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.747519 # miss rate for InvalidateReq accesses 1416system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.019560 # miss rate for demand accesses 1417system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.039843 # miss rate for demand accesses 1418system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.093508 # miss rate for demand accesses 1419system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.247682 # miss rate for demand accesses 1420system.cpu0.l2cache.demand_miss_rate::total 0.154845 # miss rate for demand accesses 1421system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.019560 # miss rate for overall accesses 1422system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.039843 # miss rate for overall accesses 1423system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.093508 # miss rate for overall accesses 1424system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.247682 # miss rate for overall accesses 1425system.cpu0.l2cache.overall_miss_rate::total 0.154845 # miss rate for overall accesses 1426system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 34303.239881 # average ReadReq miss latency 1427system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 32499.409991 # average ReadReq miss latency 1428system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33555.492146 # average ReadReq miss latency 1429system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 8094.282138 # average UpgradeReq miss latency 1430system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 8094.282138 # average UpgradeReq miss latency 1431system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 7575.601384 # average SCUpgradeReq miss latency 1432system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 7575.601384 # average SCUpgradeReq miss latency 1433system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 515642.714286 # average SCUpgradeFailReq miss latency 1434system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 515642.714286 # average SCUpgradeFailReq miss latency 1435system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50579.922355 # average ReadExReq miss latency 1436system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50579.922355 # average ReadExReq miss latency 1437system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 34979.834002 # average ReadCleanReq miss latency 1438system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 34979.834002 # average ReadCleanReq miss latency 1439system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 35132.281448 # average ReadSharedReq miss latency 1440system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 35132.281448 # average ReadSharedReq miss latency 1441system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 579.314224 # average InvalidateReq miss latency 1442system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 579.314224 # average InvalidateReq miss latency 1443system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 34303.239881 # average overall miss latency 1444system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 32499.409991 # average overall miss latency 1445system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34979.834002 # average overall miss latency 1446system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38661.065055 # average overall miss latency 1447system.cpu0.l2cache.demand_avg_miss_latency::total 37470.988838 # average overall miss latency 1448system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 34303.239881 # average overall miss latency 1449system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 32499.409991 # average overall miss latency 1450system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34979.834002 # average overall miss latency 1451system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38661.065055 # average overall miss latency 1452system.cpu0.l2cache.overall_avg_miss_latency::total 37470.988838 # average overall miss latency 1453system.cpu0.l2cache.blocked_cycles::no_mshrs 395 # number of cycles access was blocked 1454system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1455system.cpu0.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked 1456system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1457system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 56.428571 # average number of cycles each access was blocked 1458system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1459system.cpu0.l2cache.unused_prefetches 43030 # number of HardPF blocks evicted w/o reference 1460system.cpu0.l2cache.writebacks::writebacks 1602911 # number of writebacks 1461system.cpu0.l2cache.writebacks::total 1602911 # number of writebacks 1462system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 2 # number of ReadReq MSHR hits 1463system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 13 # number of ReadReq MSHR hits 1464system.cpu0.l2cache.ReadReq_mshr_hits::total 15 # number of ReadReq MSHR hits 1465system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 13671 # number of ReadExReq MSHR hits 1466system.cpu0.l2cache.ReadExReq_mshr_hits::total 13671 # number of ReadExReq MSHR hits 1467system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 3 # number of ReadCleanReq MSHR hits 1468system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 1469system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 5375 # number of ReadSharedReq MSHR hits 1470system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 5375 # number of ReadSharedReq MSHR hits 1471system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 2 # number of demand (read+write) MSHR hits 1472system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 13 # number of demand (read+write) MSHR hits 1473system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits 1474system.cpu0.l2cache.demand_mshr_hits::cpu0.data 19046 # number of demand (read+write) MSHR hits 1475system.cpu0.l2cache.demand_mshr_hits::total 19064 # number of demand (read+write) MSHR hits 1476system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 2 # number of overall MSHR hits 1477system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 13 # number of overall MSHR hits 1478system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits 1479system.cpu0.l2cache.overall_mshr_hits::cpu0.data 19046 # number of overall MSHR hits 1480system.cpu0.l2cache.overall_mshr_hits::total 19064 # number of overall MSHR hits 1481system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10770 # number of ReadReq MSHR misses 1482system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7614 # number of ReadReq MSHR misses 1483system.cpu0.l2cache.ReadReq_mshr_misses::total 18384 # number of ReadReq MSHR misses 1484system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 2 # number of WritebackDirty MSHR misses 1485system.cpu0.l2cache.WritebackDirty_mshr_misses::total 2 # number of WritebackDirty MSHR misses 1486system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 1487system.cpu0.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses 1488system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 773321 # number of HardPFReq MSHR misses 1489system.cpu0.l2cache.HardPFReq_mshr_misses::total 773321 # number of HardPFReq MSHR misses 1490system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 260447 # number of UpgradeReq MSHR misses 1491system.cpu0.l2cache.UpgradeReq_mshr_misses::total 260447 # number of UpgradeReq MSHR misses 1492system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 187318 # number of SCUpgradeReq MSHR misses 1493system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 187318 # number of SCUpgradeReq MSHR misses 1494system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 7 # number of SCUpgradeFailReq MSHR misses 1495system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses 1496system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 274565 # number of ReadExReq MSHR misses 1497system.cpu0.l2cache.ReadExReq_mshr_misses::total 274565 # number of ReadExReq MSHR misses 1498system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 573859 # number of ReadCleanReq MSHR misses 1499system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 573859 # number of ReadCleanReq MSHR misses 1500system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 968174 # number of ReadSharedReq MSHR misses 1501system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 968174 # number of ReadSharedReq MSHR misses 1502system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 600983 # number of InvalidateReq MSHR misses 1503system.cpu0.l2cache.InvalidateReq_mshr_misses::total 600983 # number of InvalidateReq MSHR misses 1504system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10770 # number of demand (read+write) MSHR misses 1505system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7614 # number of demand (read+write) MSHR misses 1506system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 573859 # number of demand (read+write) MSHR misses 1507system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1242739 # number of demand (read+write) MSHR misses 1508system.cpu0.l2cache.demand_mshr_misses::total 1834982 # number of demand (read+write) MSHR misses 1509system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10770 # number of overall MSHR misses 1510system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7614 # number of overall MSHR misses 1511system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 573859 # number of overall MSHR misses 1512system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1242739 # number of overall MSHR misses 1513system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 773321 # number of overall MSHR misses 1514system.cpu0.l2cache.overall_mshr_misses::total 2608303 # number of overall MSHR misses 1515system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 1516system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32527 # number of ReadReq MSHR uncacheable 1517system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 53820 # number of ReadReq MSHR uncacheable 1518system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32351 # number of WriteReq MSHR uncacheable 1519system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32351 # number of WriteReq MSHR uncacheable 1520system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 1521system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 64878 # number of overall MSHR uncacheable misses 1522system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 86171 # number of overall MSHR uncacheable misses 1523system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 304850000 # number of ReadReq MSHR miss cycles 1524system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 201976000 # number of ReadReq MSHR miss cycles 1525system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 506826000 # number of ReadReq MSHR miss cycles 1526system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 36226481632 # number of HardPFReq MSHR miss cycles 1527system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 36226481632 # number of HardPFReq MSHR miss cycles 1528system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 5428667497 # number of UpgradeReq MSHR miss cycles 1529system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 5428667497 # number of UpgradeReq MSHR miss cycles 1530system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3091853999 # number of SCUpgradeReq MSHR miss cycles 1531system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3091853999 # number of SCUpgradeReq MSHR miss cycles 1532system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 3183499 # number of SCUpgradeFailReq MSHR miss cycles 1533system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3183499 # number of SCUpgradeFailReq MSHR miss cycles 1534system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11062749000 # number of ReadExReq MSHR miss cycles 1535system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11062749000 # number of ReadExReq MSHR miss cycles 1536system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 16630399500 # number of ReadCleanReq MSHR miss cycles 1537system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 16630399500 # number of ReadCleanReq MSHR miss cycles 1538system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 28032243476 # number of ReadSharedReq MSHR miss cycles 1539system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 28032243476 # number of ReadSharedReq MSHR miss cycles 1540system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 21947187999 # number of InvalidateReq MSHR miss cycles 1541system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 21947187999 # number of InvalidateReq MSHR miss cycles 1542system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 304850000 # number of demand (read+write) MSHR miss cycles 1543system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 201976000 # number of demand (read+write) MSHR miss cycles 1544system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 16630399500 # number of demand (read+write) MSHR miss cycles 1545system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 39094992476 # number of demand (read+write) MSHR miss cycles 1546system.cpu0.l2cache.demand_mshr_miss_latency::total 56232217976 # number of demand (read+write) MSHR miss cycles 1547system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 304850000 # number of overall MSHR miss cycles 1548system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 201976000 # number of overall MSHR miss cycles 1549system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 16630399500 # number of overall MSHR miss cycles 1550system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 39094992476 # number of overall MSHR miss cycles 1551system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 36226481632 # number of overall MSHR miss cycles 1552system.cpu0.l2cache.overall_mshr_miss_latency::total 92458699608 # number of overall MSHR miss cycles 1553system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1725979000 # number of ReadReq MSHR uncacheable cycles 1554system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5947854500 # number of ReadReq MSHR uncacheable cycles 1555system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7673833500 # number of ReadReq MSHR uncacheable cycles 1556system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1725979000 # number of overall MSHR uncacheable cycles 1557system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5947854500 # number of overall MSHR uncacheable cycles 1558system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7673833500 # number of overall MSHR uncacheable cycles 1559system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.019556 # mshr miss rate for ReadReq accesses 1560system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.039775 # mshr miss rate for ReadReq accesses 1561system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.024771 # mshr miss rate for ReadReq accesses 1562system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 1563system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses 1564system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 1565system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 1566system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1567system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1568system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998520 # mshr miss rate for UpgradeReq accesses 1569system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998520 # mshr miss rate for UpgradeReq accesses 1570system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999968 # mshr miss rate for SCUpgradeReq accesses 1571system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999968 # mshr miss rate for SCUpgradeReq accesses 1572system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1573system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1574system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.231953 # mshr miss rate for ReadExReq accesses 1575system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231953 # mshr miss rate for ReadExReq accesses 1576system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.093508 # mshr miss rate for ReadCleanReq accesses 1577system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.093508 # mshr miss rate for ReadCleanReq accesses 1578system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.247573 # mshr miss rate for ReadSharedReq accesses 1579system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.247573 # mshr miss rate for ReadSharedReq accesses 1580system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.747519 # mshr miss rate for InvalidateReq accesses 1581system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.747519 # mshr miss rate for InvalidateReq accesses 1582system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.019556 # mshr miss rate for demand accesses 1583system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.039775 # mshr miss rate for demand accesses 1584system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.093508 # mshr miss rate for demand accesses 1585system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.243943 # mshr miss rate for demand accesses 1586system.cpu0.l2cache.demand_mshr_miss_rate::total 0.153253 # mshr miss rate for demand accesses 1587system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.019556 # mshr miss rate for overall accesses 1588system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.039775 # mshr miss rate for overall accesses 1589system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.093508 # mshr miss rate for overall accesses 1590system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.243943 # mshr miss rate for overall accesses 1591system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1592system.cpu0.l2cache.overall_mshr_miss_rate::total 0.217839 # mshr miss rate for overall accesses 1593system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28305.478180 # average ReadReq mshr miss latency 1594system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26526.924087 # average ReadReq mshr miss latency 1595system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27568.864230 # average ReadReq mshr miss latency 1596system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46845.335420 # average HardPFReq mshr miss latency 1597system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46845.335420 # average HardPFReq mshr miss latency 1598system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20843.655320 # average UpgradeReq mshr miss latency 1599system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20843.655320 # average UpgradeReq mshr miss latency 1600system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16505.909731 # average SCUpgradeReq mshr miss latency 1601system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16505.909731 # average SCUpgradeReq mshr miss latency 1602system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 454785.571429 # average SCUpgradeFailReq mshr miss latency 1603system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 454785.571429 # average SCUpgradeFailReq mshr miss latency 1604system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40291.912662 # average ReadExReq mshr miss latency 1605system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40291.912662 # average ReadExReq mshr miss latency 1606system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 28979.940194 # average ReadCleanReq mshr miss latency 1607system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28979.940194 # average ReadCleanReq mshr miss latency 1608system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28953.724719 # average ReadSharedReq mshr miss latency 1609system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28953.724719 # average ReadSharedReq mshr miss latency 1610system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36518.816670 # average InvalidateReq mshr miss latency 1611system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36518.816670 # average InvalidateReq mshr miss latency 1612system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28305.478180 # average overall mshr miss latency 1613system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26526.924087 # average overall mshr miss latency 1614system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 28979.940194 # average overall mshr miss latency 1615system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31458.731460 # average overall mshr miss latency 1616system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30644.561078 # average overall mshr miss latency 1617system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28305.478180 # average overall mshr miss latency 1618system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26526.924087 # average overall mshr miss latency 1619system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 28979.940194 # average overall mshr miss latency 1620system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31458.731460 # average overall mshr miss latency 1621system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46845.335420 # average overall mshr miss latency 1622system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35447.837007 # average overall mshr miss latency 1623system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average ReadReq mshr uncacheable latency 1624system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182858.994066 # average ReadReq mshr uncacheable latency 1625system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142583.305463 # average ReadReq mshr uncacheable latency 1626system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average overall mshr uncacheable latency 1627system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91677.525509 # average overall mshr uncacheable latency 1628system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89053.550498 # average overall mshr uncacheable latency 1629system.cpu0.toL2Bus.snoop_filter.tot_requests 24754475 # Total number of requests made to the snoop filter. 1630system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12719207 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1631system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2136 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1632system.cpu0.toL2Bus.snoop_filter.tot_snoops 1997962 # Total number of snoops made to the snoop filter. 1633system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1997498 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1634system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 464 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1635system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 1636system.cpu0.toL2Bus.trans_dist::ReadReq 885324 # Transaction distribution 1637system.cpu0.toL2Bus.trans_dist::ReadResp 11040535 # Transaction distribution 1638system.cpu0.toL2Bus.trans_dist::WriteReq 32352 # Transaction distribution 1639system.cpu0.toL2Bus.trans_dist::WriteResp 32351 # Transaction distribution 1640system.cpu0.toL2Bus.trans_dist::WritebackDirty 5471965 # Transaction distribution 1641system.cpu0.toL2Bus.trans_dist::WritebackClean 8067317 # Transaction distribution 1642system.cpu0.toL2Bus.trans_dist::CleanEvict 2568559 # Transaction distribution 1643system.cpu0.toL2Bus.trans_dist::HardPFReq 991385 # Transaction distribution 1644system.cpu0.toL2Bus.trans_dist::HardPFResp 10 # Transaction distribution 1645system.cpu0.toL2Bus.trans_dist::UpgradeReq 475065 # Transaction distribution 1646system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 341372 # Transaction distribution 1647system.cpu0.toL2Bus.trans_dist::UpgradeResp 522361 # Transaction distribution 1648system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 76 # Transaction distribution 1649system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 140 # Transaction distribution 1650system.cpu0.toL2Bus.trans_dist::ReadExReq 1216718 # Transaction distribution 1651system.cpu0.toL2Bus.trans_dist::ReadExResp 1192935 # Transaction distribution 1652system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6137080 # Transaction distribution 1653system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4901216 # Transaction distribution 1654system.cpu0.toL2Bus.trans_dist::InvalidateReq 866556 # Transaction distribution 1655system.cpu0.toL2Bus.trans_dist::InvalidateResp 803970 # Transaction distribution 1656system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18453192 # Packet count per connected master and slave (bytes) 1657system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18807742 # Packet count per connected master and slave (bytes) 1658system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 402695 # Packet count per connected master and slave (bytes) 1659system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1170958 # Packet count per connected master and slave (bytes) 1660system.cpu0.toL2Bus.pkt_count::total 38834587 # Packet count per connected master and slave (bytes) 1661system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 785846352 # Cumulative packet size per connected master and slave (bytes) 1662system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 704525389 # Cumulative packet size per connected master and slave (bytes) 1663system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1531416 # Cumulative packet size per connected master and slave (bytes) 1664system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4405792 # Cumulative packet size per connected master and slave (bytes) 1665system.cpu0.toL2Bus.pkt_size::total 1496308949 # Cumulative packet size per connected master and slave (bytes) 1666system.cpu0.toL2Bus.snoops 6903738 # Total snoops (count) 1667system.cpu0.toL2Bus.snoop_fanout::samples 20024554 # Request fanout histogram 1668system.cpu0.toL2Bus.snoop_fanout::mean 0.116908 # Request fanout histogram 1669system.cpu0.toL2Bus.snoop_fanout::stdev 0.321383 # Request fanout histogram 1670system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1671system.cpu0.toL2Bus.snoop_fanout::0 17683990 88.31% 88.31% # Request fanout histogram 1672system.cpu0.toL2Bus.snoop_fanout::1 2340100 11.69% 100.00% # Request fanout histogram 1673system.cpu0.toL2Bus.snoop_fanout::2 464 0.00% 100.00% # Request fanout histogram 1674system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1675system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1676system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1677system.cpu0.toL2Bus.snoop_fanout::total 20024554 # Request fanout histogram 1678system.cpu0.toL2Bus.reqLayer0.occupancy 24612511939 # Layer occupancy (ticks) 1679system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1680system.cpu0.toL2Bus.snoopLayer0.occupancy 212521499 # Layer occupancy (ticks) 1681system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1682system.cpu0.toL2Bus.respLayer0.occupancy 9233457820 # Layer occupancy (ticks) 1683system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1684system.cpu0.toL2Bus.respLayer1.occupancy 8324768239 # Layer occupancy (ticks) 1685system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1686system.cpu0.toL2Bus.respLayer2.occupancy 211573883 # Layer occupancy (ticks) 1687system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1688system.cpu0.toL2Bus.respLayer3.occupancy 620908635 # Layer occupancy (ticks) 1689system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1690system.cpu1.branchPred.lookups 127244460 # Number of BP lookups 1691system.cpu1.branchPred.condPredicted 83927531 # Number of conditional branches predicted 1692system.cpu1.branchPred.condIncorrect 6411720 # Number of conditional branches incorrect 1693system.cpu1.branchPred.BTBLookups 89791062 # Number of BTB lookups 1694system.cpu1.branchPred.BTBHits 55539581 # Number of BTB hits 1695system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1696system.cpu1.branchPred.BTBHitPct 61.854242 # BTB Hit Percentage 1697system.cpu1.branchPred.usedRAS 17406269 # Number of times the RAS was used to get a target. 1698system.cpu1.branchPred.RASInCorrect 177185 # Number of incorrect RAS predictions. 1699system.cpu1.branchPred.indirectLookups 4036084 # Number of indirect predictor lookups. 1700system.cpu1.branchPred.indirectHits 2495247 # Number of indirect target hits. 1701system.cpu1.branchPred.indirectMisses 1540837 # Number of indirect misses. 1702system.cpu1.branchPredindirectMispredicted 386993 # Number of mispredicted indirect branches. 1703system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 1704system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1705system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1706system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1707system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1708system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1709system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1710system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1711system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1712system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1713system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1714system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1715system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1716system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1717system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1718system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1719system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1720system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1721system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1722system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1723system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1724system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1725system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1726system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1727system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1728system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1729system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1730system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1731system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1732system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1733system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 1734system.cpu1.dtb.walker.walks 579824 # Table walker walks requested 1735system.cpu1.dtb.walker.walksLong 579824 # Table walker walks initiated with long descriptors 1736system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12232 # Level at which table walker walks with long descriptors terminate 1737system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93540 # Level at which table walker walks with long descriptors terminate 1738system.cpu1.dtb.walker.walksSquashedBefore 278610 # Table walks squashed before starting 1739system.cpu1.dtb.walker.walkWaitTime::samples 301214 # Table walker wait (enqueue to first request) latency 1740system.cpu1.dtb.walker.walkWaitTime::mean 2385.289196 # Table walker wait (enqueue to first request) latency 1741system.cpu1.dtb.walker.walkWaitTime::stdev 13264.000730 # Table walker wait (enqueue to first request) latency 1742system.cpu1.dtb.walker.walkWaitTime::0-65535 298702 99.17% 99.17% # Table walker wait (enqueue to first request) latency 1743system.cpu1.dtb.walker.walkWaitTime::65536-131071 1877 0.62% 99.79% # Table walker wait (enqueue to first request) latency 1744system.cpu1.dtb.walker.walkWaitTime::131072-196607 425 0.14% 99.93% # Table walker wait (enqueue to first request) latency 1745system.cpu1.dtb.walker.walkWaitTime::196608-262143 126 0.04% 99.97% # Table walker wait (enqueue to first request) latency 1746system.cpu1.dtb.walker.walkWaitTime::262144-327679 47 0.02% 99.99% # Table walker wait (enqueue to first request) latency 1747system.cpu1.dtb.walker.walkWaitTime::327680-393215 33 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1748system.cpu1.dtb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1749system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1750system.cpu1.dtb.walker.walkWaitTime::total 301214 # Table walker wait (enqueue to first request) latency 1751system.cpu1.dtb.walker.walkCompletionTime::samples 311038 # Table walker service (enqueue to completion) latency 1752system.cpu1.dtb.walker.walkCompletionTime::mean 20491.173104 # Table walker service (enqueue to completion) latency 1753system.cpu1.dtb.walker.walkCompletionTime::gmean 17661.433181 # Table walker service (enqueue to completion) latency 1754system.cpu1.dtb.walker.walkCompletionTime::stdev 17134.136599 # Table walker service (enqueue to completion) latency 1755system.cpu1.dtb.walker.walkCompletionTime::0-65535 306887 98.67% 98.67% # Table walker service (enqueue to completion) latency 1756system.cpu1.dtb.walker.walkCompletionTime::65536-131071 3006 0.97% 99.63% # Table walker service (enqueue to completion) latency 1757system.cpu1.dtb.walker.walkCompletionTime::131072-196607 404 0.13% 99.76% # Table walker service (enqueue to completion) latency 1758system.cpu1.dtb.walker.walkCompletionTime::196608-262143 531 0.17% 99.93% # Table walker service (enqueue to completion) latency 1759system.cpu1.dtb.walker.walkCompletionTime::262144-327679 109 0.04% 99.97% # Table walker service (enqueue to completion) latency 1760system.cpu1.dtb.walker.walkCompletionTime::327680-393215 60 0.02% 99.99% # Table walker service (enqueue to completion) latency 1761system.cpu1.dtb.walker.walkCompletionTime::393216-458751 29 0.01% 100.00% # Table walker service (enqueue to completion) latency 1762system.cpu1.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency 1763system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 1764system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1765system.cpu1.dtb.walker.walkCompletionTime::total 311038 # Table walker service (enqueue to completion) latency 1766system.cpu1.dtb.walker.walksPending::samples 427436234332 # Table walker pending requests distribution 1767system.cpu1.dtb.walker.walksPending::mean 0.596252 # Table walker pending requests distribution 1768system.cpu1.dtb.walker.walksPending::stdev 0.559035 # Table walker pending requests distribution 1769system.cpu1.dtb.walker.walksPending::0-1 426093627832 99.69% 99.69% # Table walker pending requests distribution 1770system.cpu1.dtb.walker.walksPending::2-3 733360500 0.17% 99.86% # Table walker pending requests distribution 1771system.cpu1.dtb.walker.walksPending::4-5 289523500 0.07% 99.93% # Table walker pending requests distribution 1772system.cpu1.dtb.walker.walksPending::6-7 124054000 0.03% 99.95% # Table walker pending requests distribution 1773system.cpu1.dtb.walker.walksPending::8-9 101131500 0.02% 99.98% # Table walker pending requests distribution 1774system.cpu1.dtb.walker.walksPending::10-11 55199000 0.01% 99.99% # Table walker pending requests distribution 1775system.cpu1.dtb.walker.walksPending::12-13 17877500 0.00% 99.99% # Table walker pending requests distribution 1776system.cpu1.dtb.walker.walksPending::14-15 20812500 0.00% 100.00% # Table walker pending requests distribution 1777system.cpu1.dtb.walker.walksPending::16-17 638500 0.00% 100.00% # Table walker pending requests distribution 1778system.cpu1.dtb.walker.walksPending::18-19 9500 0.00% 100.00% # Table walker pending requests distribution 1779system.cpu1.dtb.walker.walksPending::total 427436234332 # Table walker pending requests distribution 1780system.cpu1.dtb.walker.walkPageSizes::4K 93540 88.44% 88.44% # Table walker page sizes translated 1781system.cpu1.dtb.walker.walkPageSizes::2M 12232 11.56% 100.00% # Table walker page sizes translated 1782system.cpu1.dtb.walker.walkPageSizes::total 105772 # Table walker page sizes translated 1783system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 579824 # Table walker requests started/completed, data/inst 1784system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1785system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 579824 # Table walker requests started/completed, data/inst 1786system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105772 # Table walker requests started/completed, data/inst 1787system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1788system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105772 # Table walker requests started/completed, data/inst 1789system.cpu1.dtb.walker.walkRequestOrigin::total 685596 # Table walker requests started/completed, data/inst 1790system.cpu1.dtb.inst_hits 0 # ITB inst hits 1791system.cpu1.dtb.inst_misses 0 # ITB inst misses 1792system.cpu1.dtb.read_hits 94100008 # DTB read hits 1793system.cpu1.dtb.read_misses 416726 # DTB read misses 1794system.cpu1.dtb.write_hits 75732153 # DTB write hits 1795system.cpu1.dtb.write_misses 163098 # DTB write misses 1796system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1797system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1798system.cpu1.dtb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID 1799system.cpu1.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID
1800system.cpu1.dtb.flush_entries 40949 # Number of entries that have been flushed from TLB	1800system.cpu1.dtb.flush_entries 40885 # Number of entries that have been flushed from TLB
1801system.cpu1.dtb.align_faults 397 # Number of TLB faults due to alignment restrictions 1802system.cpu1.dtb.prefetch_faults 6052 # Number of TLB faults due to prefetch 1803system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1804system.cpu1.dtb.perms_faults 38110 # Number of TLB faults due to permissions restrictions 1805system.cpu1.dtb.read_accesses 94516734 # DTB read accesses 1806system.cpu1.dtb.write_accesses 75895251 # DTB write accesses 1807system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1808system.cpu1.dtb.hits 169832161 # DTB hits 1809system.cpu1.dtb.misses 579824 # DTB misses 1810system.cpu1.dtb.accesses 170411985 # DTB accesses 1811system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 1812system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1813system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1814system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1815system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1816system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1817system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1818system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1819system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1820system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1821system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1822system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1823system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1824system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1825system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1826system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1827system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1828system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1829system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1830system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1831system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1832system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1833system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1834system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1835system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1836system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1837system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1838system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1839system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1840system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1841system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 1842system.cpu1.itb.walker.walks 86146 # Table walker walks requested 1843system.cpu1.itb.walker.walksLong 86146 # Table walker walks initiated with long descriptors 1844system.cpu1.itb.walker.walksLongTerminationLevel::Level2 983 # Level at which table walker walks with long descriptors terminate 1845system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61109 # Level at which table walker walks with long descriptors terminate 1846system.cpu1.itb.walker.walksSquashedBefore 10267 # Table walks squashed before starting 1847system.cpu1.itb.walker.walkWaitTime::samples 75879 # Table walker wait (enqueue to first request) latency 1848system.cpu1.itb.walker.walkWaitTime::mean 1365.727013 # Table walker wait (enqueue to first request) latency 1849system.cpu1.itb.walker.walkWaitTime::stdev 9905.301438 # Table walker wait (enqueue to first request) latency 1850system.cpu1.itb.walker.walkWaitTime::0-32767 74992 98.83% 98.83% # Table walker wait (enqueue to first request) latency 1851system.cpu1.itb.walker.walkWaitTime::32768-65535 442 0.58% 99.41% # Table walker wait (enqueue to first request) latency 1852system.cpu1.itb.walker.walkWaitTime::65536-98303 265 0.35% 99.76% # Table walker wait (enqueue to first request) latency 1853system.cpu1.itb.walker.walkWaitTime::98304-131071 132 0.17% 99.94% # Table walker wait (enqueue to first request) latency 1854system.cpu1.itb.walker.walkWaitTime::131072-163839 11 0.01% 99.95% # Table walker wait (enqueue to first request) latency 1855system.cpu1.itb.walker.walkWaitTime::163840-196607 13 0.02% 99.97% # Table walker wait (enqueue to first request) latency 1856system.cpu1.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency 1857system.cpu1.itb.walker.walkWaitTime::229376-262143 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1858system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency 1859system.cpu1.itb.walker.walkWaitTime::294912-327679 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1860system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 1861system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1862system.cpu1.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1863system.cpu1.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1864system.cpu1.itb.walker.walkWaitTime::total 75879 # Table walker wait (enqueue to first request) latency 1865system.cpu1.itb.walker.walkCompletionTime::samples 72359 # Table walker service (enqueue to completion) latency 1866system.cpu1.itb.walker.walkCompletionTime::mean 25927.458920 # Table walker service (enqueue to completion) latency 1867system.cpu1.itb.walker.walkCompletionTime::gmean 22905.536509 # Table walker service (enqueue to completion) latency 1868system.cpu1.itb.walker.walkCompletionTime::stdev 21012.178040 # Table walker service (enqueue to completion) latency 1869system.cpu1.itb.walker.walkCompletionTime::0-65535 70191 97.00% 97.00% # Table walker service (enqueue to completion) latency 1870system.cpu1.itb.walker.walkCompletionTime::65536-131071 1833 2.53% 99.54% # Table walker service (enqueue to completion) latency 1871system.cpu1.itb.walker.walkCompletionTime::131072-196607 132 0.18% 99.72% # Table walker service (enqueue to completion) latency 1872system.cpu1.itb.walker.walkCompletionTime::196608-262143 128 0.18% 99.90% # Table walker service (enqueue to completion) latency 1873system.cpu1.itb.walker.walkCompletionTime::262144-327679 41 0.06% 99.95% # Table walker service (enqueue to completion) latency 1874system.cpu1.itb.walker.walkCompletionTime::327680-393215 21 0.03% 99.98% # Table walker service (enqueue to completion) latency 1875system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 1876system.cpu1.itb.walker.walkCompletionTime::458752-524287 7 0.01% 100.00% # Table walker service (enqueue to completion) latency 1877system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1878system.cpu1.itb.walker.walkCompletionTime::total 72359 # Table walker service (enqueue to completion) latency 1879system.cpu1.itb.walker.walksPending::samples 388687033168 # Table walker pending requests distribution 1880system.cpu1.itb.walker.walksPending::mean 0.860499 # Table walker pending requests distribution 1881system.cpu1.itb.walker.walksPending::stdev 0.346749 # Table walker pending requests distribution 1882system.cpu1.itb.walker.walksPending::0 54258161808 13.96% 13.96% # Table walker pending requests distribution 1883system.cpu1.itb.walker.walksPending::1 334394621860 86.03% 99.99% # Table walker pending requests distribution 1884system.cpu1.itb.walker.walksPending::2 32560000 0.01% 100.00% # Table walker pending requests distribution 1885system.cpu1.itb.walker.walksPending::3 1626500 0.00% 100.00% # Table walker pending requests distribution 1886system.cpu1.itb.walker.walksPending::4 63000 0.00% 100.00% # Table walker pending requests distribution 1887system.cpu1.itb.walker.walksPending::total 388687033168 # Table walker pending requests distribution 1888system.cpu1.itb.walker.walkPageSizes::4K 61109 98.42% 98.42% # Table walker page sizes translated 1889system.cpu1.itb.walker.walkPageSizes::2M 983 1.58% 100.00% # Table walker page sizes translated 1890system.cpu1.itb.walker.walkPageSizes::total 62092 # Table walker page sizes translated 1891system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1892system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 86146 # Table walker requests started/completed, data/inst 1893system.cpu1.itb.walker.walkRequestOrigin_Requested::total 86146 # Table walker requests started/completed, data/inst 1894system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1895system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62092 # Table walker requests started/completed, data/inst 1896system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62092 # Table walker requests started/completed, data/inst 1897system.cpu1.itb.walker.walkRequestOrigin::total 148238 # Table walker requests started/completed, data/inst 1898system.cpu1.itb.inst_hits 200179962 # ITB inst hits 1899system.cpu1.itb.inst_misses 86146 # ITB inst misses 1900system.cpu1.itb.read_hits 0 # DTB read hits 1901system.cpu1.itb.read_misses 0 # DTB read misses 1902system.cpu1.itb.write_hits 0 # DTB write hits 1903system.cpu1.itb.write_misses 0 # DTB write misses 1904system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1905system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1906system.cpu1.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID 1907system.cpu1.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID	1801system.cpu1.dtb.align_faults 397 # Number of TLB faults due to alignment restrictions 1802system.cpu1.dtb.prefetch_faults 6052 # Number of TLB faults due to prefetch 1803system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1804system.cpu1.dtb.perms_faults 38110 # Number of TLB faults due to permissions restrictions 1805system.cpu1.dtb.read_accesses 94516734 # DTB read accesses 1806system.cpu1.dtb.write_accesses 75895251 # DTB write accesses 1807system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1808system.cpu1.dtb.hits 169832161 # DTB hits 1809system.cpu1.dtb.misses 579824 # DTB misses 1810system.cpu1.dtb.accesses 170411985 # DTB accesses 1811system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 1812system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1813system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1814system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1815system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1816system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1817system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1818system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1819system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1820system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1821system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1822system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1823system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1824system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1825system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1826system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1827system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1828system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1829system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1830system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1831system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1832system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1833system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1834system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1835system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1836system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1837system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1838system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1839system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1840system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1841system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 1842system.cpu1.itb.walker.walks 86146 # Table walker walks requested 1843system.cpu1.itb.walker.walksLong 86146 # Table walker walks initiated with long descriptors 1844system.cpu1.itb.walker.walksLongTerminationLevel::Level2 983 # Level at which table walker walks with long descriptors terminate 1845system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61109 # Level at which table walker walks with long descriptors terminate 1846system.cpu1.itb.walker.walksSquashedBefore 10267 # Table walks squashed before starting 1847system.cpu1.itb.walker.walkWaitTime::samples 75879 # Table walker wait (enqueue to first request) latency 1848system.cpu1.itb.walker.walkWaitTime::mean 1365.727013 # Table walker wait (enqueue to first request) latency 1849system.cpu1.itb.walker.walkWaitTime::stdev 9905.301438 # Table walker wait (enqueue to first request) latency 1850system.cpu1.itb.walker.walkWaitTime::0-32767 74992 98.83% 98.83% # Table walker wait (enqueue to first request) latency 1851system.cpu1.itb.walker.walkWaitTime::32768-65535 442 0.58% 99.41% # Table walker wait (enqueue to first request) latency 1852system.cpu1.itb.walker.walkWaitTime::65536-98303 265 0.35% 99.76% # Table walker wait (enqueue to first request) latency 1853system.cpu1.itb.walker.walkWaitTime::98304-131071 132 0.17% 99.94% # Table walker wait (enqueue to first request) latency 1854system.cpu1.itb.walker.walkWaitTime::131072-163839 11 0.01% 99.95% # Table walker wait (enqueue to first request) latency 1855system.cpu1.itb.walker.walkWaitTime::163840-196607 13 0.02% 99.97% # Table walker wait (enqueue to first request) latency 1856system.cpu1.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency 1857system.cpu1.itb.walker.walkWaitTime::229376-262143 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1858system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency 1859system.cpu1.itb.walker.walkWaitTime::294912-327679 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1860system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 1861system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1862system.cpu1.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1863system.cpu1.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1864system.cpu1.itb.walker.walkWaitTime::total 75879 # Table walker wait (enqueue to first request) latency 1865system.cpu1.itb.walker.walkCompletionTime::samples 72359 # Table walker service (enqueue to completion) latency 1866system.cpu1.itb.walker.walkCompletionTime::mean 25927.458920 # Table walker service (enqueue to completion) latency 1867system.cpu1.itb.walker.walkCompletionTime::gmean 22905.536509 # Table walker service (enqueue to completion) latency 1868system.cpu1.itb.walker.walkCompletionTime::stdev 21012.178040 # Table walker service (enqueue to completion) latency 1869system.cpu1.itb.walker.walkCompletionTime::0-65535 70191 97.00% 97.00% # Table walker service (enqueue to completion) latency 1870system.cpu1.itb.walker.walkCompletionTime::65536-131071 1833 2.53% 99.54% # Table walker service (enqueue to completion) latency 1871system.cpu1.itb.walker.walkCompletionTime::131072-196607 132 0.18% 99.72% # Table walker service (enqueue to completion) latency 1872system.cpu1.itb.walker.walkCompletionTime::196608-262143 128 0.18% 99.90% # Table walker service (enqueue to completion) latency 1873system.cpu1.itb.walker.walkCompletionTime::262144-327679 41 0.06% 99.95% # Table walker service (enqueue to completion) latency 1874system.cpu1.itb.walker.walkCompletionTime::327680-393215 21 0.03% 99.98% # Table walker service (enqueue to completion) latency 1875system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 1876system.cpu1.itb.walker.walkCompletionTime::458752-524287 7 0.01% 100.00% # Table walker service (enqueue to completion) latency 1877system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1878system.cpu1.itb.walker.walkCompletionTime::total 72359 # Table walker service (enqueue to completion) latency 1879system.cpu1.itb.walker.walksPending::samples 388687033168 # Table walker pending requests distribution 1880system.cpu1.itb.walker.walksPending::mean 0.860499 # Table walker pending requests distribution 1881system.cpu1.itb.walker.walksPending::stdev 0.346749 # Table walker pending requests distribution 1882system.cpu1.itb.walker.walksPending::0 54258161808 13.96% 13.96% # Table walker pending requests distribution 1883system.cpu1.itb.walker.walksPending::1 334394621860 86.03% 99.99% # Table walker pending requests distribution 1884system.cpu1.itb.walker.walksPending::2 32560000 0.01% 100.00% # Table walker pending requests distribution 1885system.cpu1.itb.walker.walksPending::3 1626500 0.00% 100.00% # Table walker pending requests distribution 1886system.cpu1.itb.walker.walksPending::4 63000 0.00% 100.00% # Table walker pending requests distribution 1887system.cpu1.itb.walker.walksPending::total 388687033168 # Table walker pending requests distribution 1888system.cpu1.itb.walker.walkPageSizes::4K 61109 98.42% 98.42% # Table walker page sizes translated 1889system.cpu1.itb.walker.walkPageSizes::2M 983 1.58% 100.00% # Table walker page sizes translated 1890system.cpu1.itb.walker.walkPageSizes::total 62092 # Table walker page sizes translated 1891system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1892system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 86146 # Table walker requests started/completed, data/inst 1893system.cpu1.itb.walker.walkRequestOrigin_Requested::total 86146 # Table walker requests started/completed, data/inst 1894system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1895system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62092 # Table walker requests started/completed, data/inst 1896system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62092 # Table walker requests started/completed, data/inst 1897system.cpu1.itb.walker.walkRequestOrigin::total 148238 # Table walker requests started/completed, data/inst 1898system.cpu1.itb.inst_hits 200179962 # ITB inst hits 1899system.cpu1.itb.inst_misses 86146 # ITB inst misses 1900system.cpu1.itb.read_hits 0 # DTB read hits 1901system.cpu1.itb.read_misses 0 # DTB read misses 1902system.cpu1.itb.write_hits 0 # DTB write hits 1903system.cpu1.itb.write_misses 0 # DTB write misses 1904system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1905system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1906system.cpu1.itb.flush_tlb_mva_asid 42813 # Number of times TLB was flushed by MVA & ASID 1907system.cpu1.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID
1908system.cpu1.itb.flush_entries 29991 # Number of entries that have been flushed from TLB	1908system.cpu1.itb.flush_entries 29927 # Number of entries that have been flushed from TLB
1909system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1910system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1911system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1912system.cpu1.itb.perms_faults 205105 # Number of TLB faults due to permissions restrictions 1913system.cpu1.itb.read_accesses 0 # DTB read accesses 1914system.cpu1.itb.write_accesses 0 # DTB write accesses 1915system.cpu1.itb.inst_accesses 200266108 # ITB inst accesses 1916system.cpu1.itb.hits 200179962 # DTB hits 1917system.cpu1.itb.misses 86146 # DTB misses 1918system.cpu1.itb.accesses 200266108 # DTB accesses 1919system.cpu1.numPwrStateTransitions 11252 # Number of power state transitions 1920system.cpu1.pwrStateClkGateDist::samples 5626 # Distribution of time spent in the clock gated state 1921system.cpu1.pwrStateClkGateDist::mean 8361647359.894774 # Distribution of time spent in the clock gated state 1922system.cpu1.pwrStateClkGateDist::stdev 196584250353.907135 # Distribution of time spent in the clock gated state 1923system.cpu1.pwrStateClkGateDist::underflows 4008 71.24% 71.24% # Distribution of time spent in the clock gated state 1924system.cpu1.pwrStateClkGateDist::1000-5e+10 1597 28.39% 99.63% # Distribution of time spent in the clock gated state 1925system.cpu1.pwrStateClkGateDist::5e+10-1e+11 6 0.11% 99.73% # Distribution of time spent in the clock gated state 1926system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state 1927system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.77% # Distribution of time spent in the clock gated state 1928system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.79% # Distribution of time spent in the clock gated state 1929system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state 1930system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state 1931system.cpu1.pwrStateClkGateDist::overflows 10 0.18% 100.00% # Distribution of time spent in the clock gated state 1932system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 1933system.cpu1.pwrStateClkGateDist::max_value 11813562713000 # Distribution of time spent in the clock gated state 1934system.cpu1.pwrStateClkGateDist::total 5626 # Distribution of time spent in the clock gated state 1935system.cpu1.pwrStateResidencyTicks::ON 341687116232 # Cumulative time (in ticks) in various power states 1936system.cpu1.pwrStateResidencyTicks::CLK_GATED 47042628046768 # Cumulative time (in ticks) in various power states 1937system.cpu1.numCycles 683375860 # number of cpu cycles simulated 1938system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1939system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1940system.cpu1.fetch.icacheStallCycles 83886783 # Number of cycles fetch is stalled on an Icache miss 1941system.cpu1.fetch.Insts 563469851 # Number of instructions fetch has processed 1942system.cpu1.fetch.Branches 127244460 # Number of branches that fetch encountered 1943system.cpu1.fetch.predictedBranches 75441097 # Number of branches that fetch has predicted taken 1944system.cpu1.fetch.Cycles 564344995 # Number of cycles fetch has run and was not squashing or blocked 1945system.cpu1.fetch.SquashCycles 13807906 # Number of cycles fetch has spent squashing 1946system.cpu1.fetch.TlbCycles 2007349 # Number of cycles fetch has spent waiting for tlb 1947system.cpu1.fetch.MiscStallCycles 258832 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1948system.cpu1.fetch.PendingTrapStallCycles 5872913 # Number of stall cycles due to pending traps 1949system.cpu1.fetch.PendingQuiesceStallCycles 777107 # Number of stall cycles due to pending quiesce instructions 1950system.cpu1.fetch.IcacheWaitRetryStallCycles 768148 # Number of stall cycles due to full MSHR 1951system.cpu1.fetch.CacheLines 199953853 # Number of cache lines fetched 1952system.cpu1.fetch.IcacheSquashes 1622392 # Number of outstanding Icache misses that were squashed 1953system.cpu1.fetch.ItlbSquashes 27919 # Number of outstanding ITLB misses that were squashed 1954system.cpu1.fetch.rateDist::samples 664820080 # Number of instructions fetched each cycle (Total) 1955system.cpu1.fetch.rateDist::mean 0.994147 # Number of instructions fetched each cycle (Total) 1956system.cpu1.fetch.rateDist::stdev 1.223667 # Number of instructions fetched each cycle (Total) 1957system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1958system.cpu1.fetch.rateDist::0 348468390 52.42% 52.42% # Number of instructions fetched each cycle (Total) 1959system.cpu1.fetch.rateDist::1 123001690 18.50% 70.92% # Number of instructions fetched each cycle (Total) 1960system.cpu1.fetch.rateDist::2 42123132 6.34% 77.25% # Number of instructions fetched each cycle (Total) 1961system.cpu1.fetch.rateDist::3 151226868 22.75% 100.00% # Number of instructions fetched each cycle (Total) 1962system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1963system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1964system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 1965system.cpu1.fetch.rateDist::total 664820080 # Number of instructions fetched each cycle (Total) 1966system.cpu1.fetch.branchRate 0.186200 # Number of branch fetches per cycle 1967system.cpu1.fetch.rate 0.824539 # Number of inst fetches per cycle 1968system.cpu1.decode.IdleCycles 100313259 # Number of cycles decode is idle 1969system.cpu1.decode.BlockedCycles 315334519 # Number of cycles decode is blocked 1970system.cpu1.decode.RunCycles 208757120 # Number of cycles decode is running 1971system.cpu1.decode.UnblockCycles 35486026 # Number of cycles decode is unblocking 1972system.cpu1.decode.SquashCycles 4929156 # Number of cycles decode is squashing 1973system.cpu1.decode.BranchResolved 17976704 # Number of times decode resolved a branch 1974system.cpu1.decode.BranchMispred 2012194 # Number of times decode detected a branch misprediction 1975system.cpu1.decode.DecodedInsts 582722672 # Number of instructions handled by decode 1976system.cpu1.decode.SquashedInsts 22029645 # Number of squashed instructions handled by decode 1977system.cpu1.rename.SquashCycles 4929156 # Number of cycles rename is squashing 1978system.cpu1.rename.IdleCycles 133756265 # Number of cycles rename is idle 1979system.cpu1.rename.BlockCycles 43242401 # Number of cycles rename is blocking 1980system.cpu1.rename.serializeStallCycles 214462360 # count of cycles rename stalled for serializing inst 1981system.cpu1.rename.RunCycles 210347945 # Number of cycles rename is running 1982system.cpu1.rename.UnblockCycles 58081953 # Number of cycles rename is unblocking 1983system.cpu1.rename.RenamedInsts 566482483 # Number of instructions processed by rename 1984system.cpu1.rename.SquashedInsts 5736321 # Number of squashed instructions processed by rename 1985system.cpu1.rename.ROBFullEvents 9739688 # Number of times rename has blocked due to ROB full 1986system.cpu1.rename.IQFullEvents 342221 # Number of times rename has blocked due to IQ full 1987system.cpu1.rename.LQFullEvents 843279 # Number of times rename has blocked due to LQ full 1988system.cpu1.rename.SQFullEvents 24527700 # Number of times rename has blocked due to SQ full 1989system.cpu1.rename.FullRegisterEvents 11906 # Number of times there has been no free registers 1990system.cpu1.rename.RenamedOperands 538415916 # Number of destination operands rename has renamed 1991system.cpu1.rename.RenameLookups 871757488 # Number of register rename lookups that rename has made 1992system.cpu1.rename.int_rename_lookups 668460678 # Number of integer rename lookups 1993system.cpu1.rename.fp_rename_lookups 644937 # Number of floating rename lookups 1994system.cpu1.rename.CommittedMaps 483561743 # Number of HB maps that are committed 1995system.cpu1.rename.UndoneMaps 54854172 # Number of HB maps that are undone due to squashing 1996system.cpu1.rename.serializingInsts 15093428 # count of serializing insts renamed 1997system.cpu1.rename.tempSerializingInsts 13190698 # count of temporary serializing insts renamed 1998system.cpu1.rename.skidInsts 71341154 # count of insts added to the skid buffer 1999system.cpu1.memDep0.insertedLoads 94469141 # Number of loads inserted to the mem dependence unit. 2000system.cpu1.memDep0.insertedStores 78816060 # Number of stores inserted to the mem dependence unit. 2001system.cpu1.memDep0.conflictingLoads 9208116 # Number of conflicting loads. 2002system.cpu1.memDep0.conflictingStores 7878049 # Number of conflicting stores. 2003system.cpu1.iq.iqInstsAdded 544809829 # Number of instructions added to the IQ (excludes non-spec) 2004system.cpu1.iq.iqNonSpecInstsAdded 15364466 # Number of non-speculative instructions added to the IQ 2005system.cpu1.iq.iqInstsIssued 549398452 # Number of instructions issued 2006system.cpu1.iq.iqSquashedInstsIssued 2550658 # Number of squashed instructions issued 2007system.cpu1.iq.iqSquashedInstsExamined 51789954 # Number of squashed instructions iterated over during squash; mainly for profiling 2008system.cpu1.iq.iqSquashedOperandsExamined 33366441 # Number of squashed operands that are examined and possibly removed from graph 2009system.cpu1.iq.iqSquashedNonSpecRemoved 282362 # Number of squashed non-spec instructions that were removed 2010system.cpu1.iq.issued_per_cycle::samples 664820080 # Number of insts issued each cycle 2011system.cpu1.iq.issued_per_cycle::mean 0.826387 # Number of insts issued each cycle 2012system.cpu1.iq.issued_per_cycle::stdev 1.065764 # Number of insts issued each cycle 2013system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 2014system.cpu1.iq.issued_per_cycle::0 363096071 54.62% 54.62% # Number of insts issued each cycle 2015system.cpu1.iq.issued_per_cycle::1 129026402 19.41% 74.02% # Number of insts issued each cycle 2016system.cpu1.iq.issued_per_cycle::2 104942160 15.79% 89.81% # Number of insts issued each cycle 2017system.cpu1.iq.issued_per_cycle::3 60539163 9.11% 98.91% # Number of insts issued each cycle 2018system.cpu1.iq.issued_per_cycle::4 7211179 1.08% 100.00% # Number of insts issued each cycle 2019system.cpu1.iq.issued_per_cycle::5 5105 0.00% 100.00% # Number of insts issued each cycle 2020system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 2021system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 2022system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 2023system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2024system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2025system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 2026system.cpu1.iq.issued_per_cycle::total 664820080 # Number of insts issued each cycle 2027system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 2028system.cpu1.iq.fu_full::IntAlu 54936992 44.00% 44.00% # attempts to use FU when none available 2029system.cpu1.iq.fu_full::IntMult 69872 0.06% 44.05% # attempts to use FU when none available 2030system.cpu1.iq.fu_full::IntDiv 6570 0.01% 44.06% # attempts to use FU when none available 2031system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.06% # attempts to use FU when none available 2032system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.06% # attempts to use FU when none available 2033system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.06% # attempts to use FU when none available 2034system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.06% # attempts to use FU when none available 2035system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.06% # attempts to use FU when none available 2036system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.06% # attempts to use FU when none available 2037system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.06% # attempts to use FU when none available 2038system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.06% # attempts to use FU when none available 2039system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.06% # attempts to use FU when none available 2040system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.06% # attempts to use FU when none available 2041system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.06% # attempts to use FU when none available 2042system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.06% # attempts to use FU when none available 2043system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.06% # attempts to use FU when none available 2044system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.06% # attempts to use FU when none available 2045system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.06% # attempts to use FU when none available 2046system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.06% # attempts to use FU when none available 2047system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.06% # attempts to use FU when none available 2048system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.06% # attempts to use FU when none available 2049system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.06% # attempts to use FU when none available 2050system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.06% # attempts to use FU when none available 2051system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.06% # attempts to use FU when none available 2052system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.06% # attempts to use FU when none available 2053system.cpu1.iq.fu_full::SimdFloatMisc 17 0.00% 44.06% # attempts to use FU when none available 2054system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.06% # attempts to use FU when none available 2055system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.06% # attempts to use FU when none available 2056system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.06% # attempts to use FU when none available 2057system.cpu1.iq.fu_full::MemRead 34367116 27.52% 71.58% # attempts to use FU when none available 2058system.cpu1.iq.fu_full::MemWrite 35481157 28.42% 100.00% # attempts to use FU when none available 2059system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2060system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2061system.cpu1.iq.FU_type_0::No_OpClass 56 0.00% 0.00% # Type of FU issued 2062system.cpu1.iq.FU_type_0::IntAlu 373883416 68.05% 68.05% # Type of FU issued 2063system.cpu1.iq.FU_type_0::IntMult 1335155 0.24% 68.30% # Type of FU issued 2064system.cpu1.iq.FU_type_0::IntDiv 74884 0.01% 68.31% # Type of FU issued 2065system.cpu1.iq.FU_type_0::FloatAdd 11 0.00% 68.31% # Type of FU issued 2066system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued 2067system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued 2068system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued 2069system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.31% # Type of FU issued 2070system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.31% # Type of FU issued 2071system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.31% # Type of FU issued 2072system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.31% # Type of FU issued 2073system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.31% # Type of FU issued 2074system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.31% # Type of FU issued 2075system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.31% # Type of FU issued 2076system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.31% # Type of FU issued 2077system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.31% # Type of FU issued 2078system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.31% # Type of FU issued 2079system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.31% # Type of FU issued 2080system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.31% # Type of FU issued 2081system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.31% # Type of FU issued 2082system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.31% # Type of FU issued 2083system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.31% # Type of FU issued 2084system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.31% # Type of FU issued 2085system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.31% # Type of FU issued 2086system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.31% # Type of FU issued 2087system.cpu1.iq.FU_type_0::SimdFloatMisc 48854 0.01% 68.32% # Type of FU issued 2088system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued 2089system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued 2090system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued 2091system.cpu1.iq.FU_type_0::MemRead 97153433 17.68% 86.00% # Type of FU issued 2092system.cpu1.iq.FU_type_0::MemWrite 76902643 14.00% 100.00% # Type of FU issued 2093system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2094system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2095system.cpu1.iq.FU_type_0::total 549398452 # Type of FU issued 2096system.cpu1.iq.rate 0.803948 # Inst issue rate 2097system.cpu1.iq.fu_busy_cnt 124861724 # FU busy when requested 2098system.cpu1.iq.fu_busy_rate 0.227270 # FU busy rate (busy events/executed inst) 2099system.cpu1.iq.int_inst_queue_reads 1889962970 # Number of integer instruction queue reads 2100system.cpu1.iq.int_inst_queue_writes 611689245 # Number of integer instruction queue writes 2101system.cpu1.iq.int_inst_queue_wakeup_accesses 533047508 # Number of integer instruction queue wakeup accesses 2102system.cpu1.iq.fp_inst_queue_reads 1066396 # Number of floating instruction queue reads 2103system.cpu1.iq.fp_inst_queue_writes 424008 # Number of floating instruction queue writes 2104system.cpu1.iq.fp_inst_queue_wakeup_accesses 393622 # Number of floating instruction queue wakeup accesses 2105system.cpu1.iq.int_alu_accesses 673596915 # Number of integer alu accesses 2106system.cpu1.iq.fp_alu_accesses 663205 # Number of floating point alu accesses 2107system.cpu1.iew.lsq.thread0.forwLoads 2524444 # Number of loads that had data forwarded from stores 2108system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2109system.cpu1.iew.lsq.thread0.squashedLoads 12144847 # Number of loads squashed 2110system.cpu1.iew.lsq.thread0.ignoredResponses 16403 # Number of memory responses ignored because the instruction is squashed 2111system.cpu1.iew.lsq.thread0.memOrderViolation 149896 # Number of memory ordering violations 2112system.cpu1.iew.lsq.thread0.squashedStores 5262071 # Number of stores squashed 2113system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2114system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2115system.cpu1.iew.lsq.thread0.rescheduledLoads 2572719 # Number of loads that were rescheduled 2116system.cpu1.iew.lsq.thread0.cacheBlocked 4009144 # Number of times an access to memory failed due to the cache being blocked 2117system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2118system.cpu1.iew.iewSquashCycles 4929156 # Number of cycles IEW is squashing 2119system.cpu1.iew.iewBlockCycles 7182655 # Number of cycles IEW is blocking 2120system.cpu1.iew.iewUnblockCycles 1646879 # Number of cycles IEW is unblocking 2121system.cpu1.iew.iewDispatchedInsts 560304926 # Number of instructions dispatched to IQ 2122system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 2123system.cpu1.iew.iewDispLoadInsts 94469141 # Number of dispatched load instructions 2124system.cpu1.iew.iewDispStoreInsts 78816060 # Number of dispatched store instructions 2125system.cpu1.iew.iewDispNonSpecInsts 12974148 # Number of dispatched non-speculative instructions 2126system.cpu1.iew.iewIQFullEvents 56258 # Number of times the IQ has become full, causing a stall 2127system.cpu1.iew.iewLSQFullEvents 1524659 # Number of times the LSQ has become full, causing a stall 2128system.cpu1.iew.memOrderViolationEvents 149896 # Number of memory order violations 2129system.cpu1.iew.predictedTakenIncorrect 1843431 # Number of branches that were predicted taken incorrectly 2130system.cpu1.iew.predictedNotTakenIncorrect 2924818 # Number of branches that were predicted not taken incorrectly 2131system.cpu1.iew.branchMispredicts 4768249 # Number of branch mispredicts detected at execute 2132system.cpu1.iew.iewExecutedInsts 541845400 # Number of executed instructions 2133system.cpu1.iew.iewExecLoadInsts 94094962 # Number of load instructions executed 2134system.cpu1.iew.iewExecSquashedInsts 6980663 # Number of squashed instructions skipped in execute 2135system.cpu1.iew.exec_swp 0 # number of swp insts executed 2136system.cpu1.iew.exec_nop 130631 # number of nop insts executed 2137system.cpu1.iew.exec_refs 169824676 # number of memory reference insts executed 2138system.cpu1.iew.exec_branches 101510793 # Number of branches executed 2139system.cpu1.iew.exec_stores 75729714 # Number of stores executed 2140system.cpu1.iew.exec_rate 0.792895 # Inst execution rate 2141system.cpu1.iew.wb_sent 534152020 # cumulative count of insts sent to commit 2142system.cpu1.iew.wb_count 533441130 # cumulative count of insts written-back 2143system.cpu1.iew.wb_producers 258912640 # num instructions producing a value 2144system.cpu1.iew.wb_consumers 423656459 # num instructions consuming a value 2145system.cpu1.iew.wb_rate 0.780597 # insts written-back per cycle 2146system.cpu1.iew.wb_fanout 0.611138 # average fanout of values written-back 2147system.cpu1.commit.commitSquashedInsts 45293147 # The number of squashed insts skipped by commit 2148system.cpu1.commit.commitNonSpecStalls 15082103 # The number of times commit has been forced to stall to communicate backwards 2149system.cpu1.commit.branchMispredicts 4436923 # The number of times a branch was mispredicted 2150system.cpu1.commit.committed_per_cycle::samples 656213363 # Number of insts commited each cycle 2151system.cpu1.commit.committed_per_cycle::mean 0.774724 # Number of insts commited each cycle 2152system.cpu1.commit.committed_per_cycle::stdev 1.573400 # Number of insts commited each cycle 2153system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2154system.cpu1.commit.committed_per_cycle::0 432598016 65.92% 65.92% # Number of insts commited each cycle 2155system.cpu1.commit.committed_per_cycle::1 117091486 17.84% 83.77% # Number of insts commited each cycle 2156system.cpu1.commit.committed_per_cycle::2 49126445 7.49% 91.25% # Number of insts commited each cycle 2157system.cpu1.commit.committed_per_cycle::3 16229930 2.47% 93.73% # Number of insts commited each cycle 2158system.cpu1.commit.committed_per_cycle::4 11628277 1.77% 95.50% # Number of insts commited each cycle 2159system.cpu1.commit.committed_per_cycle::5 8033144 1.22% 96.72% # Number of insts commited each cycle 2160system.cpu1.commit.committed_per_cycle::6 5546832 0.85% 97.57% # Number of insts commited each cycle 2161system.cpu1.commit.committed_per_cycle::7 3283510 0.50% 98.07% # Number of insts commited each cycle 2162system.cpu1.commit.committed_per_cycle::8 12675723 1.93% 100.00% # Number of insts commited each cycle 2163system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2164system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2165system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2166system.cpu1.commit.committed_per_cycle::total 656213363 # Number of insts commited each cycle 2167system.cpu1.commit.committedInsts 431870837 # Number of instructions committed 2168system.cpu1.commit.committedOps 508384340 # Number of ops (including micro ops) committed 2169system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 2170system.cpu1.commit.refs 155878283 # Number of memory references committed 2171system.cpu1.commit.loads 82324294 # Number of loads committed 2172system.cpu1.commit.membars 3722309 # Number of memory barriers committed 2173system.cpu1.commit.branches 96290107 # Number of branches committed 2174system.cpu1.commit.fp_insts 384716 # Number of committed floating point instructions. 2175system.cpu1.commit.int_insts 467163355 # Number of committed integer instructions. 2176system.cpu1.commit.function_calls 12903273 # Number of function calls committed. 2177system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 2178system.cpu1.commit.op_class_0::IntAlu 351312000 69.10% 69.10% # Class of committed instruction 2179system.cpu1.commit.op_class_0::IntMult 1092238 0.21% 69.32% # Class of committed instruction 2180system.cpu1.commit.op_class_0::IntDiv 59391 0.01% 69.33% # Class of committed instruction 2181system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction 2182system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction 2183system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction 2184system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction 2185system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction 2186system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction 2187system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction 2188system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction 2189system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction 2190system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction 2191system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction 2192system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction 2193system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction 2194system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction 2195system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction 2196system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction 2197system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction 2198system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction 2199system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction 2200system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction 2201system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction 2202system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction 2203system.cpu1.commit.op_class_0::SimdFloatMisc 42428 0.01% 69.34% # Class of committed instruction 2204system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.34% # Class of committed instruction 2205system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.34% # Class of committed instruction 2206system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.34% # Class of committed instruction 2207system.cpu1.commit.op_class_0::MemRead 82324294 16.19% 85.53% # Class of committed instruction 2208system.cpu1.commit.op_class_0::MemWrite 73553989 14.47% 100.00% # Class of committed instruction 2209system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2210system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2211system.cpu1.commit.op_class_0::total 508384340 # Class of committed instruction 2212system.cpu1.commit.bw_lim_events 12675723 # number cycles where commit BW limit reached 2213system.cpu1.rob.rob_reads 1193390155 # The number of ROB reads 2214system.cpu1.rob.rob_writes 1115923607 # The number of ROB writes 2215system.cpu1.timesIdled 934929 # Number of times that the entire CPU went into an idle state and unscheduled itself 2216system.cpu1.idleCycles 18555780 # Total number of cycles that the CPU has spent unscheduled due to idling 2217system.cpu1.quiesceCycles 94085254498 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2218system.cpu1.committedInsts 431870837 # Number of Instructions Simulated 2219system.cpu1.committedOps 508384340 # Number of Ops (including micro ops) Simulated 2220system.cpu1.cpi 1.582362 # CPI: Cycles Per Instruction 2221system.cpu1.cpi_total 1.582362 # CPI: Total CPI of All Threads 2222system.cpu1.ipc 0.631967 # IPC: Instructions Per Cycle 2223system.cpu1.ipc_total 0.631967 # IPC: Total IPC of All Threads 2224system.cpu1.int_regfile_reads 639570382 # number of integer regfile reads 2225system.cpu1.int_regfile_writes 380109427 # number of integer regfile writes 2226system.cpu1.fp_regfile_reads 631427 # number of floating regfile reads 2227system.cpu1.fp_regfile_writes 338972 # number of floating regfile writes 2228system.cpu1.cc_regfile_reads 115255782 # number of cc regfile reads 2229system.cpu1.cc_regfile_writes 115917819 # number of cc regfile writes 2230system.cpu1.misc_regfile_reads 1185795918 # number of misc regfile reads 2231system.cpu1.misc_regfile_writes 15045931 # number of misc regfile writes 2232system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 2233system.cpu1.dcache.tags.replacements 5420466 # number of replacements 2234system.cpu1.dcache.tags.tagsinuse 437.277482 # Cycle average of tags in use 2235system.cpu1.dcache.tags.total_refs 144971712 # Total number of references to valid blocks. 2236system.cpu1.dcache.tags.sampled_refs 5420977 # Sample count of references to valid blocks. 2237system.cpu1.dcache.tags.avg_refs 26.742728 # Average number of references to valid blocks. 2238system.cpu1.dcache.tags.warmup_cycle 8477404255000 # Cycle when the warmup percentage was hit. 2239system.cpu1.dcache.tags.occ_blocks::cpu1.data 437.277482 # Average occupied blocks per requestor 2240system.cpu1.dcache.tags.occ_percent::cpu1.data 0.854058 # Average percentage of cache occupancy 2241system.cpu1.dcache.tags.occ_percent::total 0.854058 # Average percentage of cache occupancy 2242system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 2243system.cpu1.dcache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id 2244system.cpu1.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id 2245system.cpu1.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 2246system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 2247system.cpu1.dcache.tags.tag_accesses 323922794 # Number of tag accesses 2248system.cpu1.dcache.tags.data_accesses 323922794 # Number of data accesses 2249system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 2250system.cpu1.dcache.ReadReq_hits::cpu1.data 76466425 # number of ReadReq hits 2251system.cpu1.dcache.ReadReq_hits::total 76466425 # number of ReadReq hits 2252system.cpu1.dcache.WriteReq_hits::cpu1.data 64110613 # number of WriteReq hits 2253system.cpu1.dcache.WriteReq_hits::total 64110613 # number of WriteReq hits 2254system.cpu1.dcache.SoftPFReq_hits::cpu1.data 170428 # number of SoftPFReq hits 2255system.cpu1.dcache.SoftPFReq_hits::total 170428 # number of SoftPFReq hits 2256system.cpu1.dcache.WriteLineReq_hits::cpu1.data 51164 # number of WriteLineReq hits 2257system.cpu1.dcache.WriteLineReq_hits::total 51164 # number of WriteLineReq hits 2258system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1700918 # number of LoadLockedReq hits 2259system.cpu1.dcache.LoadLockedReq_hits::total 1700918 # number of LoadLockedReq hits 2260system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1741756 # number of StoreCondReq hits 2261system.cpu1.dcache.StoreCondReq_hits::total 1741756 # number of StoreCondReq hits 2262system.cpu1.dcache.demand_hits::cpu1.data 140628202 # number of demand (read+write) hits 2263system.cpu1.dcache.demand_hits::total 140628202 # number of demand (read+write) hits 2264system.cpu1.dcache.overall_hits::cpu1.data 140798630 # number of overall hits 2265system.cpu1.dcache.overall_hits::total 140798630 # number of overall hits 2266system.cpu1.dcache.ReadReq_misses::cpu1.data 6372316 # number of ReadReq misses 2267system.cpu1.dcache.ReadReq_misses::total 6372316 # number of ReadReq misses 2268system.cpu1.dcache.WriteReq_misses::cpu1.data 7014697 # number of WriteReq misses 2269system.cpu1.dcache.WriteReq_misses::total 7014697 # number of WriteReq misses 2270system.cpu1.dcache.SoftPFReq_misses::cpu1.data 658076 # number of SoftPFReq misses 2271system.cpu1.dcache.SoftPFReq_misses::total 658076 # number of SoftPFReq misses 2272system.cpu1.dcache.WriteLineReq_misses::cpu1.data 445973 # number of WriteLineReq misses 2273system.cpu1.dcache.WriteLineReq_misses::total 445973 # number of WriteLineReq misses 2274system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 278553 # number of LoadLockedReq misses 2275system.cpu1.dcache.LoadLockedReq_misses::total 278553 # number of LoadLockedReq misses 2276system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193453 # number of StoreCondReq misses 2277system.cpu1.dcache.StoreCondReq_misses::total 193453 # number of StoreCondReq misses 2278system.cpu1.dcache.demand_misses::cpu1.data 13832986 # number of demand (read+write) misses 2279system.cpu1.dcache.demand_misses::total 13832986 # number of demand (read+write) misses 2280system.cpu1.dcache.overall_misses::cpu1.data 14491062 # number of overall misses 2281system.cpu1.dcache.overall_misses::total 14491062 # number of overall misses 2282system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 93736923500 # number of ReadReq miss cycles 2283system.cpu1.dcache.ReadReq_miss_latency::total 93736923500 # number of ReadReq miss cycles 2284system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 131113304741 # number of WriteReq miss cycles 2285system.cpu1.dcache.WriteReq_miss_latency::total 131113304741 # number of WriteReq miss cycles 2286system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11858807099 # number of WriteLineReq miss cycles 2287system.cpu1.dcache.WriteLineReq_miss_latency::total 11858807099 # number of WriteLineReq miss cycles 2288system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4107251000 # number of LoadLockedReq miss cycles 2289system.cpu1.dcache.LoadLockedReq_miss_latency::total 4107251000 # number of LoadLockedReq miss cycles 2290system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4806521000 # number of StoreCondReq miss cycles 2291system.cpu1.dcache.StoreCondReq_miss_latency::total 4806521000 # number of StoreCondReq miss cycles 2292system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3714500 # number of StoreCondFailReq miss cycles 2293system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3714500 # number of StoreCondFailReq miss cycles 2294system.cpu1.dcache.demand_miss_latency::cpu1.data 236709035340 # number of demand (read+write) miss cycles 2295system.cpu1.dcache.demand_miss_latency::total 236709035340 # number of demand (read+write) miss cycles 2296system.cpu1.dcache.overall_miss_latency::cpu1.data 236709035340 # number of overall miss cycles 2297system.cpu1.dcache.overall_miss_latency::total 236709035340 # number of overall miss cycles 2298system.cpu1.dcache.ReadReq_accesses::cpu1.data 82838741 # number of ReadReq accesses(hits+misses) 2299system.cpu1.dcache.ReadReq_accesses::total 82838741 # number of ReadReq accesses(hits+misses) 2300system.cpu1.dcache.WriteReq_accesses::cpu1.data 71125310 # number of WriteReq accesses(hits+misses) 2301system.cpu1.dcache.WriteReq_accesses::total 71125310 # number of WriteReq accesses(hits+misses) 2302system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 828504 # number of SoftPFReq accesses(hits+misses) 2303system.cpu1.dcache.SoftPFReq_accesses::total 828504 # number of SoftPFReq accesses(hits+misses) 2304system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 497137 # number of WriteLineReq accesses(hits+misses) 2305system.cpu1.dcache.WriteLineReq_accesses::total 497137 # number of WriteLineReq accesses(hits+misses) 2306system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1979471 # number of LoadLockedReq accesses(hits+misses) 2307system.cpu1.dcache.LoadLockedReq_accesses::total 1979471 # number of LoadLockedReq accesses(hits+misses) 2308system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1935209 # number of StoreCondReq accesses(hits+misses) 2309system.cpu1.dcache.StoreCondReq_accesses::total 1935209 # number of StoreCondReq accesses(hits+misses) 2310system.cpu1.dcache.demand_accesses::cpu1.data 154461188 # number of demand (read+write) accesses 2311system.cpu1.dcache.demand_accesses::total 154461188 # number of demand (read+write) accesses 2312system.cpu1.dcache.overall_accesses::cpu1.data 155289692 # number of overall (read+write) accesses 2313system.cpu1.dcache.overall_accesses::total 155289692 # number of overall (read+write) accesses 2314system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.076924 # miss rate for ReadReq accesses 2315system.cpu1.dcache.ReadReq_miss_rate::total 0.076924 # miss rate for ReadReq accesses 2316system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.098624 # miss rate for WriteReq accesses 2317system.cpu1.dcache.WriteReq_miss_rate::total 0.098624 # miss rate for WriteReq accesses 2318system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.794294 # miss rate for SoftPFReq accesses 2319system.cpu1.dcache.SoftPFReq_miss_rate::total 0.794294 # miss rate for SoftPFReq accesses 2320system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.897083 # miss rate for WriteLineReq accesses 2321system.cpu1.dcache.WriteLineReq_miss_rate::total 0.897083 # miss rate for WriteLineReq accesses 2322system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.140721 # miss rate for LoadLockedReq accesses 2323system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.140721 # miss rate for LoadLockedReq accesses 2324system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099965 # miss rate for StoreCondReq accesses 2325system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099965 # miss rate for StoreCondReq accesses 2326system.cpu1.dcache.demand_miss_rate::cpu1.data 0.089556 # miss rate for demand accesses 2327system.cpu1.dcache.demand_miss_rate::total 0.089556 # miss rate for demand accesses 2328system.cpu1.dcache.overall_miss_rate::cpu1.data 0.093316 # miss rate for overall accesses 2329system.cpu1.dcache.overall_miss_rate::total 0.093316 # miss rate for overall accesses 2330system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14710.024346 # average ReadReq miss latency 2331system.cpu1.dcache.ReadReq_avg_miss_latency::total 14710.024346 # average ReadReq miss latency 2332system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18691.228536 # average WriteReq miss latency 2333system.cpu1.dcache.WriteReq_avg_miss_latency::total 18691.228536 # average WriteReq miss latency 2334system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 26590.863346 # average WriteLineReq miss latency 2335system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 26590.863346 # average WriteLineReq miss latency 2336system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14744.953384 # average LoadLockedReq miss latency 2337system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14744.953384 # average LoadLockedReq miss latency 2338system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24845.936739 # average StoreCondReq miss latency 2339system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24845.936739 # average StoreCondReq miss latency 2340system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2341system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2342system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17111.926184 # average overall miss latency 2343system.cpu1.dcache.demand_avg_miss_latency::total 17111.926184 # average overall miss latency 2344system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16334.830072 # average overall miss latency 2345system.cpu1.dcache.overall_avg_miss_latency::total 16334.830072 # average overall miss latency 2346system.cpu1.dcache.blocked_cycles::no_mshrs 3137293 # number of cycles access was blocked 2347system.cpu1.dcache.blocked_cycles::no_targets 21285332 # number of cycles access was blocked 2348system.cpu1.dcache.blocked::no_mshrs 376632 # number of cycles access was blocked 2349system.cpu1.dcache.blocked::no_targets 706469 # number of cycles access was blocked 2350system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.329863 # average number of cycles each access was blocked 2351system.cpu1.dcache.avg_blocked_cycles::no_targets 30.129180 # average number of cycles each access was blocked 2352system.cpu1.dcache.writebacks::writebacks 5420571 # number of writebacks 2353system.cpu1.dcache.writebacks::total 5420571 # number of writebacks 2354system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3225514 # number of ReadReq MSHR hits 2355system.cpu1.dcache.ReadReq_mshr_hits::total 3225514 # number of ReadReq MSHR hits 2356system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5658563 # number of WriteReq MSHR hits 2357system.cpu1.dcache.WriteReq_mshr_hits::total 5658563 # number of WriteReq MSHR hits 2358system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3397 # number of WriteLineReq MSHR hits 2359system.cpu1.dcache.WriteLineReq_mshr_hits::total 3397 # number of WriteLineReq MSHR hits 2360system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 142581 # number of LoadLockedReq MSHR hits 2361system.cpu1.dcache.LoadLockedReq_mshr_hits::total 142581 # number of LoadLockedReq MSHR hits 2362system.cpu1.dcache.demand_mshr_hits::cpu1.data 8887474 # number of demand (read+write) MSHR hits 2363system.cpu1.dcache.demand_mshr_hits::total 8887474 # number of demand (read+write) MSHR hits 2364system.cpu1.dcache.overall_mshr_hits::cpu1.data 8887474 # number of overall MSHR hits 2365system.cpu1.dcache.overall_mshr_hits::total 8887474 # number of overall MSHR hits 2366system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3146802 # number of ReadReq MSHR misses 2367system.cpu1.dcache.ReadReq_mshr_misses::total 3146802 # number of ReadReq MSHR misses 2368system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1356134 # number of WriteReq MSHR misses 2369system.cpu1.dcache.WriteReq_mshr_misses::total 1356134 # number of WriteReq MSHR misses 2370system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 657988 # number of SoftPFReq MSHR misses 2371system.cpu1.dcache.SoftPFReq_mshr_misses::total 657988 # number of SoftPFReq MSHR misses 2372system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 442576 # number of WriteLineReq MSHR misses 2373system.cpu1.dcache.WriteLineReq_mshr_misses::total 442576 # number of WriteLineReq MSHR misses 2374system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 135972 # number of LoadLockedReq MSHR misses 2375system.cpu1.dcache.LoadLockedReq_mshr_misses::total 135972 # number of LoadLockedReq MSHR misses 2376system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193443 # number of StoreCondReq MSHR misses 2377system.cpu1.dcache.StoreCondReq_mshr_misses::total 193443 # number of StoreCondReq MSHR misses 2378system.cpu1.dcache.demand_mshr_misses::cpu1.data 4945512 # number of demand (read+write) MSHR misses 2379system.cpu1.dcache.demand_mshr_misses::total 4945512 # number of demand (read+write) MSHR misses 2380system.cpu1.dcache.overall_mshr_misses::cpu1.data 5603500 # number of overall MSHR misses 2381system.cpu1.dcache.overall_mshr_misses::total 5603500 # number of overall MSHR misses 2382system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6118 # number of ReadReq MSHR uncacheable 2383system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6118 # number of ReadReq MSHR uncacheable 2384system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 6183 # number of WriteReq MSHR uncacheable 2385system.cpu1.dcache.WriteReq_mshr_uncacheable::total 6183 # number of WriteReq MSHR uncacheable 2386system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 12301 # number of overall MSHR uncacheable misses 2387system.cpu1.dcache.overall_mshr_uncacheable_misses::total 12301 # number of overall MSHR uncacheable misses 2388system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43613350000 # number of ReadReq MSHR miss cycles 2389system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43613350000 # number of ReadReq MSHR miss cycles 2390system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26794309953 # number of WriteReq MSHR miss cycles 2391system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26794309953 # number of WriteReq MSHR miss cycles 2392system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14059014500 # number of SoftPFReq MSHR miss cycles 2393system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14059014500 # number of SoftPFReq MSHR miss cycles 2394system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 11316204599 # number of WriteLineReq MSHR miss cycles 2395system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 11316204599 # number of WriteLineReq MSHR miss cycles 2396system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1866790500 # number of LoadLockedReq MSHR miss cycles 2397system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1866790500 # number of LoadLockedReq MSHR miss cycles 2398system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4613147000 # number of StoreCondReq MSHR miss cycles 2399system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4613147000 # number of StoreCondReq MSHR miss cycles 2400system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3645500 # number of StoreCondFailReq MSHR miss cycles 2401system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3645500 # number of StoreCondFailReq MSHR miss cycles 2402system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 81723864552 # number of demand (read+write) MSHR miss cycles 2403system.cpu1.dcache.demand_mshr_miss_latency::total 81723864552 # number of demand (read+write) MSHR miss cycles 2404system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 95782879052 # number of overall MSHR miss cycles 2405system.cpu1.dcache.overall_mshr_miss_latency::total 95782879052 # number of overall MSHR miss cycles 2406system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 749898500 # number of ReadReq MSHR uncacheable cycles 2407system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 749898500 # number of ReadReq MSHR uncacheable cycles 2408system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 749898500 # number of overall MSHR uncacheable cycles 2409system.cpu1.dcache.overall_mshr_uncacheable_latency::total 749898500 # number of overall MSHR uncacheable cycles 2410system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037987 # mshr miss rate for ReadReq accesses 2411system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037987 # mshr miss rate for ReadReq accesses 2412system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019067 # mshr miss rate for WriteReq accesses 2413system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019067 # mshr miss rate for WriteReq accesses 2414system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.794188 # mshr miss rate for SoftPFReq accesses 2415system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.794188 # mshr miss rate for SoftPFReq accesses 2416system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.890250 # mshr miss rate for WriteLineReq accesses 2417system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.890250 # mshr miss rate for WriteLineReq accesses 2418system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068691 # mshr miss rate for LoadLockedReq accesses 2419system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068691 # mshr miss rate for LoadLockedReq accesses 2420system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099960 # mshr miss rate for StoreCondReq accesses 2421system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099960 # mshr miss rate for StoreCondReq accesses 2422system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032018 # mshr miss rate for demand accesses 2423system.cpu1.dcache.demand_mshr_miss_rate::total 0.032018 # mshr miss rate for demand accesses 2424system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036084 # mshr miss rate for overall accesses 2425system.cpu1.dcache.overall_mshr_miss_rate::total 0.036084 # mshr miss rate for overall accesses 2426system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13859.578709 # average ReadReq mshr miss latency 2427system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13859.578709 # average ReadReq mshr miss latency 2428system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19757.863126 # average WriteReq mshr miss latency 2429system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19757.863126 # average WriteReq mshr miss latency 2430system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21366.673100 # average SoftPFReq mshr miss latency 2431system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21366.673100 # average SoftPFReq mshr miss latency 2432system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 25568.952223 # average WriteLineReq mshr miss latency 2433system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 25568.952223 # average WriteLineReq mshr miss latency 2434system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13729.227341 # average LoadLockedReq mshr miss latency 2435system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13729.227341 # average LoadLockedReq mshr miss latency 2436system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23847.577839 # average StoreCondReq mshr miss latency 2437system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23847.577839 # average StoreCondReq mshr miss latency 2438system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2439system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2440system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16524.854161 # average overall mshr miss latency 2441system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16524.854161 # average overall mshr miss latency 2442system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17093.402169 # average overall mshr miss latency 2443system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17093.402169 # average overall mshr miss latency 2444system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122572.491010 # average ReadReq mshr uncacheable latency 2445system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 122572.491010 # average ReadReq mshr uncacheable latency 2446system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 60962.401431 # average overall mshr uncacheable latency 2447system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 60962.401431 # average overall mshr uncacheable latency 2448system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 2449system.cpu1.icache.tags.replacements 5742782 # number of replacements 2450system.cpu1.icache.tags.tagsinuse 501.536552 # Cycle average of tags in use 2451system.cpu1.icache.tags.total_refs 193871102 # Total number of references to valid blocks. 2452system.cpu1.icache.tags.sampled_refs 5743294 # Sample count of references to valid blocks. 2453system.cpu1.icache.tags.avg_refs 33.756082 # Average number of references to valid blocks. 2454system.cpu1.icache.tags.warmup_cycle 8517126060000 # Cycle when the warmup percentage was hit. 2455system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.536552 # Average occupied blocks per requestor 2456system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979564 # Average percentage of cache occupancy 2457system.cpu1.icache.tags.occ_percent::total 0.979564 # Average percentage of cache occupancy 2458system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2459system.cpu1.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id 2460system.cpu1.icache.tags.age_task_id_blocks_1024::1 396 # Occupied blocks per task id 2461system.cpu1.icache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id 2462system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2463system.cpu1.icache.tags.tag_accesses 405638078 # Number of tag accesses 2464system.cpu1.icache.tags.data_accesses 405638078 # Number of data accesses 2465system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 2466system.cpu1.icache.ReadReq_hits::cpu1.inst 193871102 # number of ReadReq hits 2467system.cpu1.icache.ReadReq_hits::total 193871102 # number of ReadReq hits 2468system.cpu1.icache.demand_hits::cpu1.inst 193871102 # number of demand (read+write) hits 2469system.cpu1.icache.demand_hits::total 193871102 # number of demand (read+write) hits 2470system.cpu1.icache.overall_hits::cpu1.inst 193871102 # number of overall hits 2471system.cpu1.icache.overall_hits::total 193871102 # number of overall hits 2472system.cpu1.icache.ReadReq_misses::cpu1.inst 6076268 # number of ReadReq misses 2473system.cpu1.icache.ReadReq_misses::total 6076268 # number of ReadReq misses 2474system.cpu1.icache.demand_misses::cpu1.inst 6076268 # number of demand (read+write) misses 2475system.cpu1.icache.demand_misses::total 6076268 # number of demand (read+write) misses 2476system.cpu1.icache.overall_misses::cpu1.inst 6076268 # number of overall misses 2477system.cpu1.icache.overall_misses::total 6076268 # number of overall misses 2478system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 64119298557 # number of ReadReq miss cycles 2479system.cpu1.icache.ReadReq_miss_latency::total 64119298557 # number of ReadReq miss cycles 2480system.cpu1.icache.demand_miss_latency::cpu1.inst 64119298557 # number of demand (read+write) miss cycles 2481system.cpu1.icache.demand_miss_latency::total 64119298557 # number of demand (read+write) miss cycles 2482system.cpu1.icache.overall_miss_latency::cpu1.inst 64119298557 # number of overall miss cycles 2483system.cpu1.icache.overall_miss_latency::total 64119298557 # number of overall miss cycles 2484system.cpu1.icache.ReadReq_accesses::cpu1.inst 199947370 # number of ReadReq accesses(hits+misses) 2485system.cpu1.icache.ReadReq_accesses::total 199947370 # number of ReadReq accesses(hits+misses) 2486system.cpu1.icache.demand_accesses::cpu1.inst 199947370 # number of demand (read+write) accesses 2487system.cpu1.icache.demand_accesses::total 199947370 # number of demand (read+write) accesses 2488system.cpu1.icache.overall_accesses::cpu1.inst 199947370 # number of overall (read+write) accesses 2489system.cpu1.icache.overall_accesses::total 199947370 # number of overall (read+write) accesses 2490system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030389 # miss rate for ReadReq accesses 2491system.cpu1.icache.ReadReq_miss_rate::total 0.030389 # miss rate for ReadReq accesses 2492system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030389 # miss rate for demand accesses 2493system.cpu1.icache.demand_miss_rate::total 0.030389 # miss rate for demand accesses 2494system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030389 # miss rate for overall accesses 2495system.cpu1.icache.overall_miss_rate::total 0.030389 # miss rate for overall accesses 2496system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10552.414501 # average ReadReq miss latency 2497system.cpu1.icache.ReadReq_avg_miss_latency::total 10552.414501 # average ReadReq miss latency 2498system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10552.414501 # average overall miss latency 2499system.cpu1.icache.demand_avg_miss_latency::total 10552.414501 # average overall miss latency 2500system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10552.414501 # average overall miss latency 2501system.cpu1.icache.overall_avg_miss_latency::total 10552.414501 # average overall miss latency 2502system.cpu1.icache.blocked_cycles::no_mshrs 9320412 # number of cycles access was blocked 2503system.cpu1.icache.blocked_cycles::no_targets 212 # number of cycles access was blocked 2504system.cpu1.icache.blocked::no_mshrs 713481 # number of cycles access was blocked 2505system.cpu1.icache.blocked::no_targets 3 # number of cycles access was blocked 2506system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.063294 # average number of cycles each access was blocked 2507system.cpu1.icache.avg_blocked_cycles::no_targets 70.666667 # average number of cycles each access was blocked 2508system.cpu1.icache.writebacks::writebacks 5742782 # number of writebacks 2509system.cpu1.icache.writebacks::total 5742782 # number of writebacks 2510system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 332930 # number of ReadReq MSHR hits 2511system.cpu1.icache.ReadReq_mshr_hits::total 332930 # number of ReadReq MSHR hits 2512system.cpu1.icache.demand_mshr_hits::cpu1.inst 332930 # number of demand (read+write) MSHR hits 2513system.cpu1.icache.demand_mshr_hits::total 332930 # number of demand (read+write) MSHR hits 2514system.cpu1.icache.overall_mshr_hits::cpu1.inst 332930 # number of overall MSHR hits 2515system.cpu1.icache.overall_mshr_hits::total 332930 # number of overall MSHR hits 2516system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5743338 # number of ReadReq MSHR misses 2517system.cpu1.icache.ReadReq_mshr_misses::total 5743338 # number of ReadReq MSHR misses 2518system.cpu1.icache.demand_mshr_misses::cpu1.inst 5743338 # number of demand (read+write) MSHR misses 2519system.cpu1.icache.demand_mshr_misses::total 5743338 # number of demand (read+write) MSHR misses 2520system.cpu1.icache.overall_mshr_misses::cpu1.inst 5743338 # number of overall MSHR misses 2521system.cpu1.icache.overall_mshr_misses::total 5743338 # number of overall MSHR misses 2522system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 2523system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable 2524system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 2525system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses 2526system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 58166889552 # number of ReadReq MSHR miss cycles 2527system.cpu1.icache.ReadReq_mshr_miss_latency::total 58166889552 # number of ReadReq MSHR miss cycles 2528system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 58166889552 # number of demand (read+write) MSHR miss cycles 2529system.cpu1.icache.demand_mshr_miss_latency::total 58166889552 # number of demand (read+write) MSHR miss cycles 2530system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58166889552 # number of overall MSHR miss cycles 2531system.cpu1.icache.overall_mshr_miss_latency::total 58166889552 # number of overall MSHR miss cycles 2532system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6789498 # number of ReadReq MSHR uncacheable cycles 2533system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6789498 # number of ReadReq MSHR uncacheable cycles 2534system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6789498 # number of overall MSHR uncacheable cycles 2535system.cpu1.icache.overall_mshr_uncacheable_latency::total 6789498 # number of overall MSHR uncacheable cycles 2536system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028724 # mshr miss rate for ReadReq accesses 2537system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028724 # mshr miss rate for ReadReq accesses 2538system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028724 # mshr miss rate for demand accesses 2539system.cpu1.icache.demand_mshr_miss_rate::total 0.028724 # mshr miss rate for demand accesses 2540system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028724 # mshr miss rate for overall accesses 2541system.cpu1.icache.overall_mshr_miss_rate::total 0.028724 # mshr miss rate for overall accesses 2542system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average ReadReq mshr miss latency 2543system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10127.714850 # average ReadReq mshr miss latency 2544system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency 2545system.cpu1.icache.demand_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency 2546system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency 2547system.cpu1.icache.overall_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency 2548system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average ReadReq mshr uncacheable latency 2549system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101335.791045 # average ReadReq mshr uncacheable latency 2550system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average overall mshr uncacheable latency 2551system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101335.791045 # average overall mshr uncacheable latency 2552system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 2553system.cpu1.l2cache.prefetcher.num_hwpf_issued 7416585 # number of hwpf issued 2554system.cpu1.l2cache.prefetcher.pfIdentified 7422175 # number of prefetch candidates identified 2555system.cpu1.l2cache.prefetcher.pfBufferHit 5069 # number of redundant prefetches already in prefetch queue 2556system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2557system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2558system.cpu1.l2cache.prefetcher.pfSpanPage 930081 # number of prefetches not generated due to page crossing 2559system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 2560system.cpu1.l2cache.tags.replacements 2216875 # number of replacements 2561system.cpu1.l2cache.tags.tagsinuse 13443.573819 # Cycle average of tags in use 2562system.cpu1.l2cache.tags.total_refs 16807540 # Total number of references to valid blocks. 2563system.cpu1.l2cache.tags.sampled_refs 2232789 # Sample count of references to valid blocks. 2564system.cpu1.l2cache.tags.avg_refs 7.527599 # Average number of references to valid blocks. 2565system.cpu1.l2cache.tags.warmup_cycle 9871196159000 # Cycle when the warmup percentage was hit. 2566system.cpu1.l2cache.tags.occ_blocks::writebacks 12560.451650 # Average occupied blocks per requestor 2567system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 62.875087 # Average occupied blocks per requestor 2568system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 63.205555 # Average occupied blocks per requestor 2569system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 757.041527 # Average occupied blocks per requestor 2570system.cpu1.l2cache.tags.occ_percent::writebacks 0.766629 # Average percentage of cache occupancy 2571system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003838 # Average percentage of cache occupancy 2572system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003858 # Average percentage of cache occupancy 2573system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.046206 # Average percentage of cache occupancy 2574system.cpu1.l2cache.tags.occ_percent::total 0.820531 # Average percentage of cache occupancy 2575system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1320 # Occupied blocks per task id 2576system.cpu1.l2cache.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id 2577system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14527 # Occupied blocks per task id 2578system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 25 # Occupied blocks per task id 2579system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 72 # Occupied blocks per task id 2580system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 117 # Occupied blocks per task id 2581system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 681 # Occupied blocks per task id 2582system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 425 # Occupied blocks per task id 2583system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 2584system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id 2585system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id 2586system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 2587system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id 2588system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1030 # Occupied blocks per task id 2589system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5623 # Occupied blocks per task id 2590system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4561 # Occupied blocks per task id 2591system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3143 # Occupied blocks per task id 2592system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080566 # Percentage of cache occupancy per task id 2593system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004089 # Percentage of cache occupancy per task id 2594system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.886658 # Percentage of cache occupancy per task id 2595system.cpu1.l2cache.tags.tag_accesses 383680582 # Number of tag accesses 2596system.cpu1.l2cache.tags.data_accesses 383680582 # Number of data accesses 2597system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 2598system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 591753 # number of ReadReq hits 2599system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 193382 # number of ReadReq hits 2600system.cpu1.l2cache.ReadReq_hits::total 785135 # number of ReadReq hits 2601system.cpu1.l2cache.WritebackDirty_hits::writebacks 3353025 # number of WritebackDirty hits 2602system.cpu1.l2cache.WritebackDirty_hits::total 3353025 # number of WritebackDirty hits 2603system.cpu1.l2cache.WritebackClean_hits::writebacks 7809020 # number of WritebackClean hits 2604system.cpu1.l2cache.WritebackClean_hits::total 7809020 # number of WritebackClean hits 2605system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 779 # number of UpgradeReq hits 2606system.cpu1.l2cache.UpgradeReq_hits::total 779 # number of UpgradeReq hits 2607system.cpu1.l2cache.ReadExReq_hits::cpu1.data 872441 # number of ReadExReq hits 2608system.cpu1.l2cache.ReadExReq_hits::total 872441 # number of ReadExReq hits 2609system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5195235 # number of ReadCleanReq hits 2610system.cpu1.l2cache.ReadCleanReq_hits::total 5195235 # number of ReadCleanReq hits 2611system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2967964 # number of ReadSharedReq hits 2612system.cpu1.l2cache.ReadSharedReq_hits::total 2967964 # number of ReadSharedReq hits 2613system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 177430 # number of InvalidateReq hits 2614system.cpu1.l2cache.InvalidateReq_hits::total 177430 # number of InvalidateReq hits 2615system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 591753 # number of demand (read+write) hits 2616system.cpu1.l2cache.demand_hits::cpu1.itb.walker 193382 # number of demand (read+write) hits 2617system.cpu1.l2cache.demand_hits::cpu1.inst 5195235 # number of demand (read+write) hits 2618system.cpu1.l2cache.demand_hits::cpu1.data 3840405 # number of demand (read+write) hits 2619system.cpu1.l2cache.demand_hits::total 9820775 # number of demand (read+write) hits 2620system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 591753 # number of overall hits 2621system.cpu1.l2cache.overall_hits::cpu1.itb.walker 193382 # number of overall hits 2622system.cpu1.l2cache.overall_hits::cpu1.inst 5195235 # number of overall hits 2623system.cpu1.l2cache.overall_hits::cpu1.data 3840405 # number of overall hits 2624system.cpu1.l2cache.overall_hits::total 9820775 # number of overall hits 2625system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 13125 # number of ReadReq misses 2626system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9784 # number of ReadReq misses 2627system.cpu1.l2cache.ReadReq_misses::total 22909 # number of ReadReq misses 2628system.cpu1.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses 2629system.cpu1.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses 2630system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 2631system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses 2632system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 227942 # number of UpgradeReq misses 2633system.cpu1.l2cache.UpgradeReq_misses::total 227942 # number of UpgradeReq misses 2634system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 193439 # number of SCUpgradeReq misses 2635system.cpu1.l2cache.SCUpgradeReq_misses::total 193439 # number of SCUpgradeReq misses 2636system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses 2637system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 2638system.cpu1.l2cache.ReadExReq_misses::cpu1.data 262152 # number of ReadExReq misses 2639system.cpu1.l2cache.ReadExReq_misses::total 262152 # number of ReadExReq misses 2640system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 548077 # number of ReadCleanReq misses 2641system.cpu1.l2cache.ReadCleanReq_misses::total 548077 # number of ReadCleanReq misses 2642system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 970504 # number of ReadSharedReq misses 2643system.cpu1.l2cache.ReadSharedReq_misses::total 970504 # number of ReadSharedReq misses 2644system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 263582 # number of InvalidateReq misses 2645system.cpu1.l2cache.InvalidateReq_misses::total 263582 # number of InvalidateReq misses 2646system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 13125 # number of demand (read+write) misses 2647system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9784 # number of demand (read+write) misses 2648system.cpu1.l2cache.demand_misses::cpu1.inst 548077 # number of demand (read+write) misses 2649system.cpu1.l2cache.demand_misses::cpu1.data 1232656 # number of demand (read+write) misses 2650system.cpu1.l2cache.demand_misses::total 1803642 # number of demand (read+write) misses 2651system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 13125 # number of overall misses 2652system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9784 # number of overall misses 2653system.cpu1.l2cache.overall_misses::cpu1.inst 548077 # number of overall misses 2654system.cpu1.l2cache.overall_misses::cpu1.data 1232656 # number of overall misses 2655system.cpu1.l2cache.overall_misses::total 1803642 # number of overall misses 2656system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 561719500 # number of ReadReq miss cycles 2657system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 455404000 # number of ReadReq miss cycles 2658system.cpu1.l2cache.ReadReq_miss_latency::total 1017123500 # number of ReadReq miss cycles 2659system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 1976830000 # number of UpgradeReq miss cycles 2660system.cpu1.l2cache.UpgradeReq_miss_latency::total 1976830000 # number of UpgradeReq miss cycles 2661system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1436047000 # number of SCUpgradeReq miss cycles 2662system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1436047000 # number of SCUpgradeReq miss cycles 2663system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3542000 # number of SCUpgradeFailReq miss cycles 2664system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3542000 # number of SCUpgradeFailReq miss cycles 2665system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12377259499 # number of ReadExReq miss cycles 2666system.cpu1.l2cache.ReadExReq_miss_latency::total 12377259499 # number of ReadExReq miss cycles 2667system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 18066070500 # number of ReadCleanReq miss cycles 2668system.cpu1.l2cache.ReadCleanReq_miss_latency::total 18066070500 # number of ReadCleanReq miss cycles 2669system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 33827571986 # number of ReadSharedReq miss cycles 2670system.cpu1.l2cache.ReadSharedReq_miss_latency::total 33827571986 # number of ReadSharedReq miss cycles 2671system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 317775500 # number of InvalidateReq miss cycles 2672system.cpu1.l2cache.InvalidateReq_miss_latency::total 317775500 # number of InvalidateReq miss cycles 2673system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 561719500 # number of demand (read+write) miss cycles 2674system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 455404000 # number of demand (read+write) miss cycles 2675system.cpu1.l2cache.demand_miss_latency::cpu1.inst 18066070500 # number of demand (read+write) miss cycles 2676system.cpu1.l2cache.demand_miss_latency::cpu1.data 46204831485 # number of demand (read+write) miss cycles 2677system.cpu1.l2cache.demand_miss_latency::total 65288025485 # number of demand (read+write) miss cycles 2678system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 561719500 # number of overall miss cycles 2679system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 455404000 # number of overall miss cycles 2680system.cpu1.l2cache.overall_miss_latency::cpu1.inst 18066070500 # number of overall miss cycles 2681system.cpu1.l2cache.overall_miss_latency::cpu1.data 46204831485 # number of overall miss cycles 2682system.cpu1.l2cache.overall_miss_latency::total 65288025485 # number of overall miss cycles 2683system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 604878 # number of ReadReq accesses(hits+misses) 2684system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 203166 # number of ReadReq accesses(hits+misses) 2685system.cpu1.l2cache.ReadReq_accesses::total 808044 # number of ReadReq accesses(hits+misses) 2686system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3353027 # number of WritebackDirty accesses(hits+misses) 2687system.cpu1.l2cache.WritebackDirty_accesses::total 3353027 # number of WritebackDirty accesses(hits+misses) 2688system.cpu1.l2cache.WritebackClean_accesses::writebacks 7809021 # number of WritebackClean accesses(hits+misses) 2689system.cpu1.l2cache.WritebackClean_accesses::total 7809021 # number of WritebackClean accesses(hits+misses) 2690system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 228721 # number of UpgradeReq accesses(hits+misses) 2691system.cpu1.l2cache.UpgradeReq_accesses::total 228721 # number of UpgradeReq accesses(hits+misses) 2692system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 193439 # number of SCUpgradeReq accesses(hits+misses) 2693system.cpu1.l2cache.SCUpgradeReq_accesses::total 193439 # number of SCUpgradeReq accesses(hits+misses) 2694system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 2695system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 2696system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1134593 # number of ReadExReq accesses(hits+misses) 2697system.cpu1.l2cache.ReadExReq_accesses::total 1134593 # number of ReadExReq accesses(hits+misses) 2698system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5743312 # number of ReadCleanReq accesses(hits+misses) 2699system.cpu1.l2cache.ReadCleanReq_accesses::total 5743312 # number of ReadCleanReq accesses(hits+misses) 2700system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3938468 # number of ReadSharedReq accesses(hits+misses) 2701system.cpu1.l2cache.ReadSharedReq_accesses::total 3938468 # number of ReadSharedReq accesses(hits+misses) 2702system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 441012 # number of InvalidateReq accesses(hits+misses) 2703system.cpu1.l2cache.InvalidateReq_accesses::total 441012 # number of InvalidateReq accesses(hits+misses) 2704system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 604878 # number of demand (read+write) accesses 2705system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 203166 # number of demand (read+write) accesses 2706system.cpu1.l2cache.demand_accesses::cpu1.inst 5743312 # number of demand (read+write) accesses 2707system.cpu1.l2cache.demand_accesses::cpu1.data 5073061 # number of demand (read+write) accesses 2708system.cpu1.l2cache.demand_accesses::total 11624417 # number of demand (read+write) accesses 2709system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 604878 # number of overall (read+write) accesses 2710system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 203166 # number of overall (read+write) accesses 2711system.cpu1.l2cache.overall_accesses::cpu1.inst 5743312 # number of overall (read+write) accesses 2712system.cpu1.l2cache.overall_accesses::cpu1.data 5073061 # number of overall (read+write) accesses 2713system.cpu1.l2cache.overall_accesses::total 11624417 # number of overall (read+write) accesses 2714system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021699 # miss rate for ReadReq accesses 2715system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048158 # miss rate for ReadReq accesses 2716system.cpu1.l2cache.ReadReq_miss_rate::total 0.028351 # miss rate for ReadReq accesses 2717system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses 2718system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses 2719system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 2720system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 2721system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.996594 # miss rate for UpgradeReq accesses 2722system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.996594 # miss rate for UpgradeReq accesses 2723system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2724system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2725system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2726system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2727system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.231054 # miss rate for ReadExReq accesses 2728system.cpu1.l2cache.ReadExReq_miss_rate::total 0.231054 # miss rate for ReadExReq accesses 2729system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.095429 # miss rate for ReadCleanReq accesses 2730system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.095429 # miss rate for ReadCleanReq accesses 2731system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.246417 # miss rate for ReadSharedReq accesses 2732system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.246417 # miss rate for ReadSharedReq accesses 2733system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.597675 # miss rate for InvalidateReq accesses 2734system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.597675 # miss rate for InvalidateReq accesses 2735system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021699 # miss rate for demand accesses 2736system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048158 # miss rate for demand accesses 2737system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.095429 # miss rate for demand accesses 2738system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.242981 # miss rate for demand accesses 2739system.cpu1.l2cache.demand_miss_rate::total 0.155160 # miss rate for demand accesses 2740system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021699 # miss rate for overall accesses 2741system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048158 # miss rate for overall accesses 2742system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.095429 # miss rate for overall accesses 2743system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.242981 # miss rate for overall accesses 2744system.cpu1.l2cache.overall_miss_rate::total 0.155160 # miss rate for overall accesses 2745system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 42797.676190 # average ReadReq miss latency 2746system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 46545.789043 # average ReadReq miss latency 2747system.cpu1.l2cache.ReadReq_avg_miss_latency::total 44398.424200 # average ReadReq miss latency 2748system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 8672.513183 # average UpgradeReq miss latency 2749system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 8672.513183 # average UpgradeReq miss latency 2750system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 7423.771835 # average SCUpgradeReq miss latency 2751system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 7423.771835 # average SCUpgradeReq miss latency 2752system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 885500 # average SCUpgradeFailReq miss latency 2753system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 885500 # average SCUpgradeFailReq miss latency 2754system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 47214.057108 # average ReadExReq miss latency 2755system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 47214.057108 # average ReadExReq miss latency 2756system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 32962.650321 # average ReadCleanReq miss latency 2757system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 32962.650321 # average ReadCleanReq miss latency 2758system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 34855.674975 # average ReadSharedReq miss latency 2759system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 34855.674975 # average ReadSharedReq miss latency 2760system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1205.603949 # average InvalidateReq miss latency 2761system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1205.603949 # average InvalidateReq miss latency 2762system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 42797.676190 # average overall miss latency 2763system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 46545.789043 # average overall miss latency 2764system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32962.650321 # average overall miss latency 2765system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37483.962667 # average overall miss latency 2766system.cpu1.l2cache.demand_avg_miss_latency::total 36197.884882 # average overall miss latency 2767system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 42797.676190 # average overall miss latency 2768system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 46545.789043 # average overall miss latency 2769system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32962.650321 # average overall miss latency 2770system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37483.962667 # average overall miss latency 2771system.cpu1.l2cache.overall_avg_miss_latency::total 36197.884882 # average overall miss latency 2772system.cpu1.l2cache.blocked_cycles::no_mshrs 860 # number of cycles access was blocked 2773system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2774system.cpu1.l2cache.blocked::no_mshrs 17 # number of cycles access was blocked 2775system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2776system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 50.588235 # average number of cycles each access was blocked 2777system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2778system.cpu1.l2cache.unused_prefetches 44363 # number of HardPF blocks evicted w/o reference 2779system.cpu1.l2cache.writebacks::writebacks 1196648 # number of writebacks 2780system.cpu1.l2cache.writebacks::total 1196648 # number of writebacks 2781system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits 2782system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 8 # number of ReadReq MSHR hits 2783system.cpu1.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits 2784system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 12956 # number of ReadExReq MSHR hits 2785system.cpu1.l2cache.ReadExReq_mshr_hits::total 12956 # number of ReadExReq MSHR hits 2786system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4132 # number of ReadSharedReq MSHR hits 2787system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4132 # number of ReadSharedReq MSHR hits 2788system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 5 # number of InvalidateReq MSHR hits 2789system.cpu1.l2cache.InvalidateReq_mshr_hits::total 5 # number of InvalidateReq MSHR hits 2790system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 2791system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 8 # number of demand (read+write) MSHR hits 2792system.cpu1.l2cache.demand_mshr_hits::cpu1.data 17088 # number of demand (read+write) MSHR hits 2793system.cpu1.l2cache.demand_mshr_hits::total 17097 # number of demand (read+write) MSHR hits 2794system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 2795system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 8 # number of overall MSHR hits 2796system.cpu1.l2cache.overall_mshr_hits::cpu1.data 17088 # number of overall MSHR hits 2797system.cpu1.l2cache.overall_mshr_hits::total 17097 # number of overall MSHR hits 2798system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 13124 # number of ReadReq MSHR misses 2799system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9776 # number of ReadReq MSHR misses 2800system.cpu1.l2cache.ReadReq_mshr_misses::total 22900 # number of ReadReq MSHR misses 2801system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 2 # number of WritebackDirty MSHR misses 2802system.cpu1.l2cache.WritebackDirty_mshr_misses::total 2 # number of WritebackDirty MSHR misses 2803system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 2804system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses 2805system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 773530 # number of HardPFReq MSHR misses 2806system.cpu1.l2cache.HardPFReq_mshr_misses::total 773530 # number of HardPFReq MSHR misses 2807system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 227942 # number of UpgradeReq MSHR misses 2808system.cpu1.l2cache.UpgradeReq_mshr_misses::total 227942 # number of UpgradeReq MSHR misses 2809system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 193439 # number of SCUpgradeReq MSHR misses 2810system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 193439 # number of SCUpgradeReq MSHR misses 2811system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses 2812system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 2813system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 249196 # number of ReadExReq MSHR misses 2814system.cpu1.l2cache.ReadExReq_mshr_misses::total 249196 # number of ReadExReq MSHR misses 2815system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 548077 # number of ReadCleanReq MSHR misses 2816system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 548077 # number of ReadCleanReq MSHR misses 2817system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 966372 # number of ReadSharedReq MSHR misses 2818system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 966372 # number of ReadSharedReq MSHR misses 2819system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 263577 # number of InvalidateReq MSHR misses 2820system.cpu1.l2cache.InvalidateReq_mshr_misses::total 263577 # number of InvalidateReq MSHR misses 2821system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 13124 # number of demand (read+write) MSHR misses 2822system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9776 # number of demand (read+write) MSHR misses 2823system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 548077 # number of demand (read+write) MSHR misses 2824system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1215568 # number of demand (read+write) MSHR misses 2825system.cpu1.l2cache.demand_mshr_misses::total 1786545 # number of demand (read+write) MSHR misses 2826system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 13124 # number of overall MSHR misses 2827system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9776 # number of overall MSHR misses 2828system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 548077 # number of overall MSHR misses 2829system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1215568 # number of overall MSHR misses 2830system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 773530 # number of overall MSHR misses 2831system.cpu1.l2cache.overall_mshr_misses::total 2560075 # number of overall MSHR misses 2832system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 2833system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6118 # number of ReadReq MSHR uncacheable 2834system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 6185 # number of ReadReq MSHR uncacheable 2835system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 6183 # number of WriteReq MSHR uncacheable 2836system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 6183 # number of WriteReq MSHR uncacheable 2837system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 2838system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 12301 # number of overall MSHR uncacheable misses 2839system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 12368 # number of overall MSHR uncacheable misses 2840system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 482957500 # number of ReadReq MSHR miss cycles 2841system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 396613500 # number of ReadReq MSHR miss cycles 2842system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 879571000 # number of ReadReq MSHR miss cycles 2843system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 40678992877 # number of HardPFReq MSHR miss cycles 2844system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 40678992877 # number of HardPFReq MSHR miss cycles 2845system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4718335995 # number of UpgradeReq MSHR miss cycles 2846system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4718335995 # number of UpgradeReq MSHR miss cycles 2847system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3159514995 # number of SCUpgradeReq MSHR miss cycles 2848system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3159514995 # number of SCUpgradeReq MSHR miss cycles 2849system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3128000 # number of SCUpgradeFailReq MSHR miss cycles 2850system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3128000 # number of SCUpgradeFailReq MSHR miss cycles 2851system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8998543499 # number of ReadExReq MSHR miss cycles 2852system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8998543499 # number of ReadExReq MSHR miss cycles 2853system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14777608500 # number of ReadCleanReq MSHR miss cycles 2854system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14777608500 # number of ReadCleanReq MSHR miss cycles 2855system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 27796571986 # number of ReadSharedReq MSHR miss cycles 2856system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 27796571986 # number of ReadSharedReq MSHR miss cycles 2857system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 7398469497 # number of InvalidateReq MSHR miss cycles 2858system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 7398469497 # number of InvalidateReq MSHR miss cycles 2859system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 482957500 # number of demand (read+write) MSHR miss cycles 2860system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 396613500 # number of demand (read+write) MSHR miss cycles 2861system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14777608500 # number of demand (read+write) MSHR miss cycles 2862system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 36795115485 # number of demand (read+write) MSHR miss cycles 2863system.cpu1.l2cache.demand_mshr_miss_latency::total 52452294985 # number of demand (read+write) MSHR miss cycles 2864system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 482957500 # number of overall MSHR miss cycles 2865system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 396613500 # number of overall MSHR miss cycles 2866system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14777608500 # number of overall MSHR miss cycles 2867system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 36795115485 # number of overall MSHR miss cycles 2868system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 40678992877 # number of overall MSHR miss cycles 2869system.cpu1.l2cache.overall_mshr_miss_latency::total 93131287862 # number of overall MSHR miss cycles 2870system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6286000 # number of ReadReq MSHR uncacheable cycles 2871system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 700808000 # number of ReadReq MSHR uncacheable cycles 2872system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 707094000 # number of ReadReq MSHR uncacheable cycles 2873system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6286000 # number of overall MSHR uncacheable cycles 2874system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 700808000 # number of overall MSHR uncacheable cycles 2875system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 707094000 # number of overall MSHR uncacheable cycles 2876system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021697 # mshr miss rate for ReadReq accesses 2877system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048118 # mshr miss rate for ReadReq accesses 2878system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028340 # mshr miss rate for ReadReq accesses 2879system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 2880system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses 2881system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 2882system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 2883system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2884system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2885system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996594 # mshr miss rate for UpgradeReq accesses 2886system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996594 # mshr miss rate for UpgradeReq accesses 2887system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2888system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2889system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2890system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2891system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.219635 # mshr miss rate for ReadExReq accesses 2892system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.219635 # mshr miss rate for ReadExReq accesses 2893system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.095429 # mshr miss rate for ReadCleanReq accesses 2894system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.095429 # mshr miss rate for ReadCleanReq accesses 2895system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.245367 # mshr miss rate for ReadSharedReq accesses 2896system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.245367 # mshr miss rate for ReadSharedReq accesses 2897system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.597664 # mshr miss rate for InvalidateReq accesses 2898system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.597664 # mshr miss rate for InvalidateReq accesses 2899system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021697 # mshr miss rate for demand accesses 2900system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048118 # mshr miss rate for demand accesses 2901system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.095429 # mshr miss rate for demand accesses 2902system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.239612 # mshr miss rate for demand accesses 2903system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153689 # mshr miss rate for demand accesses 2904system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021697 # mshr miss rate for overall accesses 2905system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048118 # mshr miss rate for overall accesses 2906system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.095429 # mshr miss rate for overall accesses 2907system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.239612 # mshr miss rate for overall accesses 2908system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2909system.cpu1.l2cache.overall_mshr_miss_rate::total 0.220233 # mshr miss rate for overall accesses 2910system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 36799.565681 # average ReadReq mshr miss latency 2911system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40570.120704 # average ReadReq mshr miss latency 2912system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38409.213974 # average ReadReq mshr miss latency 2913system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52588.772093 # average HardPFReq mshr miss latency 2914system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 52588.772093 # average HardPFReq mshr miss latency 2915system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20699.721837 # average UpgradeReq mshr miss latency 2916system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20699.721837 # average UpgradeReq mshr miss latency 2917system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16333.391896 # average SCUpgradeReq mshr miss latency 2918system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16333.391896 # average SCUpgradeReq mshr miss latency 2919system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 782000 # average SCUpgradeFailReq mshr miss latency 2920system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 782000 # average SCUpgradeFailReq mshr miss latency 2921system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36110.304736 # average ReadExReq mshr miss latency 2922system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36110.304736 # average ReadExReq mshr miss latency 2923system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26962.650321 # average ReadCleanReq mshr miss latency 2924system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26962.650321 # average ReadCleanReq mshr miss latency 2925system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28763.842481 # average ReadSharedReq mshr miss latency 2926system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28763.842481 # average ReadSharedReq mshr miss latency 2927system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 28069.480634 # average InvalidateReq mshr miss latency 2928system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 28069.480634 # average InvalidateReq mshr miss latency 2929system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 36799.565681 # average overall mshr miss latency 2930system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 40570.120704 # average overall mshr miss latency 2931system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26962.650321 # average overall mshr miss latency 2932system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 30269.894802 # average overall mshr miss latency 2933system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29359.627093 # average overall mshr miss latency 2934system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 36799.565681 # average overall mshr miss latency 2935system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 40570.120704 # average overall mshr miss latency 2936system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26962.650321 # average overall mshr miss latency 2937system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 30269.894802 # average overall mshr miss latency 2938system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52588.772093 # average overall mshr miss latency 2939system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36378.343549 # average overall mshr miss latency 2940system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93820.895522 # average ReadReq mshr uncacheable latency 2941system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 114548.545276 # average ReadReq mshr uncacheable latency 2942system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114324.009701 # average ReadReq mshr uncacheable latency 2943system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93820.895522 # average overall mshr uncacheable latency 2944system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 56971.628323 # average overall mshr uncacheable latency 2945system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 57171.248383 # average overall mshr uncacheable latency 2946system.cpu1.toL2Bus.snoop_filter.tot_requests 23197310 # Total number of requests made to the snoop filter. 2947system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11940096 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2948system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2949system.cpu1.toL2Bus.snoop_filter.tot_snoops 1942556 # Total number of snoops made to the snoop filter. 2950system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1942287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2951system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 269 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2952system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 2953system.cpu1.toL2Bus.trans_dist::ReadReq 900600 # Transaction distribution 2954system.cpu1.toL2Bus.trans_dist::ReadResp 10671947 # Transaction distribution 2955system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 2956system.cpu1.toL2Bus.trans_dist::WriteReq 6183 # Transaction distribution 2957system.cpu1.toL2Bus.trans_dist::WriteResp 6183 # Transaction distribution 2958system.cpu1.toL2Bus.trans_dist::WritebackDirty 4554023 # Transaction distribution 2959system.cpu1.toL2Bus.trans_dist::WritebackClean 7810324 # Transaction distribution 2960system.cpu1.toL2Bus.trans_dist::CleanEvict 2589255 # Transaction distribution 2961system.cpu1.toL2Bus.trans_dist::HardPFReq 981692 # Transaction distribution 2962system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution 2963system.cpu1.toL2Bus.trans_dist::UpgradeReq 441382 # Transaction distribution 2964system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 342905 # Transaction distribution 2965system.cpu1.toL2Bus.trans_dist::UpgradeResp 485827 # Transaction distribution 2966system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution 2967system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 140 # Transaction distribution 2968system.cpu1.toL2Bus.trans_dist::ReadExReq 1162425 # Transaction distribution 2969system.cpu1.toL2Bus.trans_dist::ReadExResp 1140502 # Transaction distribution 2970system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5743338 # Transaction distribution 2971system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4866994 # Transaction distribution 2972system.cpu1.toL2Bus.trans_dist::InvalidateReq 495411 # Transaction distribution 2973system.cpu1.toL2Bus.trans_dist::InvalidateResp 441012 # Transaction distribution 2974system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17229566 # Packet count per connected master and slave (bytes) 2975system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17476902 # Packet count per connected master and slave (bytes) 2976system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 425595 # Packet count per connected master and slave (bytes) 2977system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1276864 # Packet count per connected master and slave (bytes) 2978system.cpu1.toL2Bus.pkt_count::total 36408927 # Packet count per connected master and slave (bytes) 2979system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 735111088 # Cumulative packet size per connected master and slave (bytes) 2980system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 677743701 # Cumulative packet size per connected master and slave (bytes) 2981system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1625328 # Cumulative packet size per connected master and slave (bytes) 2982system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4839024 # Cumulative packet size per connected master and slave (bytes) 2983system.cpu1.toL2Bus.pkt_size::total 1419319141 # Cumulative packet size per connected master and slave (bytes) 2984system.cpu1.toL2Bus.snoops 6390553 # Total snoops (count) 2985system.cpu1.toL2Bus.snoop_fanout::samples 18731260 # Request fanout histogram 2986system.cpu1.toL2Bus.snoop_fanout::mean 0.122712 # Request fanout histogram 2987system.cpu1.toL2Bus.snoop_fanout::stdev 0.328150 # Request fanout histogram 2988system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2989system.cpu1.toL2Bus.snoop_fanout::0 16432977 87.73% 87.73% # Request fanout histogram 2990system.cpu1.toL2Bus.snoop_fanout::1 2298014 12.27% 100.00% # Request fanout histogram 2991system.cpu1.toL2Bus.snoop_fanout::2 269 0.00% 100.00% # Request fanout histogram 2992system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2993system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2994system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2995system.cpu1.toL2Bus.snoop_fanout::total 18731260 # Request fanout histogram 2996system.cpu1.toL2Bus.reqLayer0.occupancy 23041315974 # Layer occupancy (ticks) 2997system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2998system.cpu1.toL2Bus.snoopLayer0.occupancy 175324271 # Layer occupancy (ticks) 2999system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3000system.cpu1.toL2Bus.respLayer0.occupancy 8621166733 # Layer occupancy (ticks) 3001system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3002system.cpu1.toL2Bus.respLayer1.occupancy 8059431425 # Layer occupancy (ticks) 3003system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3004system.cpu1.toL2Bus.respLayer2.occupancy 222762323 # Layer occupancy (ticks) 3005system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 3006system.cpu1.toL2Bus.respLayer3.occupancy 672656647 # Layer occupancy (ticks) 3007system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 3008system.iobus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3009system.iobus.trans_dist::ReadReq 40341 # Transaction distribution 3010system.iobus.trans_dist::ReadResp 40341 # Transaction distribution 3011system.iobus.trans_dist::WriteReq 136646 # Transaction distribution 3012system.iobus.trans_dist::WriteResp 136646 # Transaction distribution 3013system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47790 # Packet count per connected master and slave (bytes) 3014system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 3015system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 3016system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 3017system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 3018system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 3019system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 3020system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 3021system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 3022system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 3023system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 3024system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 3025system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 3026system.iobus.pkt_count_system.bridge.master::total 122672 # Packet count per connected master and slave (bytes) 3027system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231222 # Packet count per connected master and slave (bytes) 3028system.iobus.pkt_count_system.realview.ide.dma::total 231222 # Packet count per connected master and slave (bytes) 3029system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 3030system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 3031system.iobus.pkt_count::total 353974 # Packet count per connected master and slave (bytes) 3032system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47810 # Cumulative packet size per connected master and slave (bytes) 3033system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 3034system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 3035system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 3036system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 3037system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 3038system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3039system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3040system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3041system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 3042system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3043system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 3044system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 3045system.iobus.pkt_size_system.bridge.master::total 155802 # Cumulative packet size per connected master and slave (bytes) 3046system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338904 # Cumulative packet size per connected master and slave (bytes) 3047system.iobus.pkt_size_system.realview.ide.dma::total 7338904 # Cumulative packet size per connected master and slave (bytes) 3048system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 3049system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 3050system.iobus.pkt_size::total 7496792 # Cumulative packet size per connected master and slave (bytes) 3051system.iobus.reqLayer0.occupancy 37061004 # Layer occupancy (ticks) 3052system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 3053system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) 3054system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 3055system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks) 3056system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 3057system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) 3058system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 3059system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) 3060system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 3061system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks) 3062system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 3063system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) 3064system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 3065system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) 3066system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 3067system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) 3068system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 3069system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) 3070system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 3071system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 3072system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 3073system.iobus.reqLayer23.occupancy 24283001 # Layer occupancy (ticks) 3074system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 3075system.iobus.reqLayer24.occupancy 36403501 # Layer occupancy (ticks) 3076system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 3077system.iobus.reqLayer25.occupancy 569028004 # Layer occupancy (ticks) 3078system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 3079system.iobus.respLayer0.occupancy 92757000 # Layer occupancy (ticks) 3080system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 3081system.iobus.respLayer3.occupancy 147918000 # Layer occupancy (ticks) 3082system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 3083system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 3084system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 3085system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3086system.iocache.tags.replacements 115592 # number of replacements 3087system.iocache.tags.tagsinuse 11.302694 # Cycle average of tags in use 3088system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 3089system.iocache.tags.sampled_refs 115608 # Sample count of references to valid blocks. 3090system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 3091system.iocache.tags.warmup_cycle 9115775800000 # Cycle when the warmup percentage was hit. 3092system.iocache.tags.occ_blocks::realview.ethernet 3.842796 # Average occupied blocks per requestor 3093system.iocache.tags.occ_blocks::realview.ide 7.459898 # Average occupied blocks per requestor 3094system.iocache.tags.occ_percent::realview.ethernet 0.240175 # Average percentage of cache occupancy 3095system.iocache.tags.occ_percent::realview.ide 0.466244 # Average percentage of cache occupancy 3096system.iocache.tags.occ_percent::total 0.706418 # Average percentage of cache occupancy 3097system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 3098system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 3099system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 3100system.iocache.tags.tag_accesses 1040856 # Number of tag accesses 3101system.iocache.tags.data_accesses 1040856 # Number of data accesses 3102system.iocache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3103system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 3104system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses 3105system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses 3106system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 3107system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 3108system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 3109system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 3110system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 3111system.iocache.demand_misses::realview.ide 115611 # number of demand (read+write) misses 3112system.iocache.demand_misses::total 115651 # number of demand (read+write) misses 3113system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 3114system.iocache.overall_misses::realview.ide 115611 # number of overall misses 3115system.iocache.overall_misses::total 115651 # number of overall misses 3116system.iocache.ReadReq_miss_latency::realview.ethernet 5246000 # number of ReadReq miss cycles 3117system.iocache.ReadReq_miss_latency::realview.ide 1667860010 # number of ReadReq miss cycles 3118system.iocache.ReadReq_miss_latency::total 1673106010 # number of ReadReq miss cycles 3119system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 3120system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 3121system.iocache.WriteLineReq_miss_latency::realview.ide 12956345994 # number of WriteLineReq miss cycles 3122system.iocache.WriteLineReq_miss_latency::total 12956345994 # number of WriteLineReq miss cycles 3123system.iocache.demand_miss_latency::realview.ethernet 5615000 # number of demand (read+write) miss cycles 3124system.iocache.demand_miss_latency::realview.ide 14624206004 # number of demand (read+write) miss cycles 3125system.iocache.demand_miss_latency::total 14629821004 # number of demand (read+write) miss cycles 3126system.iocache.overall_miss_latency::realview.ethernet 5615000 # number of overall miss cycles 3127system.iocache.overall_miss_latency::realview.ide 14624206004 # number of overall miss cycles 3128system.iocache.overall_miss_latency::total 14629821004 # number of overall miss cycles 3129system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 3130system.iocache.ReadReq_accesses::realview.ide 8883 # number of ReadReq accesses(hits+misses) 3131system.iocache.ReadReq_accesses::total 8920 # number of ReadReq accesses(hits+misses) 3132system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 3133system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 3134system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 3135system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 3136system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 3137system.iocache.demand_accesses::realview.ide 115611 # number of demand (read+write) accesses 3138system.iocache.demand_accesses::total 115651 # number of demand (read+write) accesses 3139system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 3140system.iocache.overall_accesses::realview.ide 115611 # number of overall (read+write) accesses 3141system.iocache.overall_accesses::total 115651 # number of overall (read+write) accesses 3142system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 3143system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 3144system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3145system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 3146system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 3147system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 3148system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 3149system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 3150system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 3151system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3152system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 3153system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 3154system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 3155system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141783.783784 # average ReadReq miss latency 3156system.iocache.ReadReq_avg_miss_latency::realview.ide 187758.641225 # average ReadReq miss latency 3157system.iocache.ReadReq_avg_miss_latency::total 187567.938341 # average ReadReq miss latency 3158system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 3159system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 3160system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121395.941028 # average WriteLineReq miss latency 3161system.iocache.WriteLineReq_avg_miss_latency::total 121395.941028 # average WriteLineReq miss latency 3162system.iocache.demand_avg_miss_latency::realview.ethernet 140375 # average overall miss latency 3163system.iocache.demand_avg_miss_latency::realview.ide 126494.935638 # average overall miss latency 3164system.iocache.demand_avg_miss_latency::total 126499.736310 # average overall miss latency 3165system.iocache.overall_avg_miss_latency::realview.ethernet 140375 # average overall miss latency 3166system.iocache.overall_avg_miss_latency::realview.ide 126494.935638 # average overall miss latency 3167system.iocache.overall_avg_miss_latency::total 126499.736310 # average overall miss latency 3168system.iocache.blocked_cycles::no_mshrs 33436 # number of cycles access was blocked 3169system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3170system.iocache.blocked::no_mshrs 3541 # number of cycles access was blocked 3171system.iocache.blocked::no_targets 0 # number of cycles access was blocked 3172system.iocache.avg_blocked_cycles::no_mshrs 9.442530 # average number of cycles each access was blocked 3173system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3174system.iocache.writebacks::writebacks 106694 # number of writebacks 3175system.iocache.writebacks::total 106694 # number of writebacks 3176system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 3177system.iocache.ReadReq_mshr_misses::realview.ide 8883 # number of ReadReq MSHR misses 3178system.iocache.ReadReq_mshr_misses::total 8920 # number of ReadReq MSHR misses 3179system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 3180system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 3181system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 3182system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 3183system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 3184system.iocache.demand_mshr_misses::realview.ide 115611 # number of demand (read+write) MSHR misses 3185system.iocache.demand_mshr_misses::total 115651 # number of demand (read+write) MSHR misses 3186system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 3187system.iocache.overall_mshr_misses::realview.ide 115611 # number of overall MSHR misses 3188system.iocache.overall_mshr_misses::total 115651 # number of overall MSHR misses 3189system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3396000 # number of ReadReq MSHR miss cycles 3190system.iocache.ReadReq_mshr_miss_latency::realview.ide 1223710010 # number of ReadReq MSHR miss cycles 3191system.iocache.ReadReq_mshr_miss_latency::total 1227106010 # number of ReadReq MSHR miss cycles 3192system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 3193system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 3194system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7611309187 # number of WriteLineReq MSHR miss cycles 3195system.iocache.WriteLineReq_mshr_miss_latency::total 7611309187 # number of WriteLineReq MSHR miss cycles 3196system.iocache.demand_mshr_miss_latency::realview.ethernet 3615000 # number of demand (read+write) MSHR miss cycles 3197system.iocache.demand_mshr_miss_latency::realview.ide 8835019197 # number of demand (read+write) MSHR miss cycles 3198system.iocache.demand_mshr_miss_latency::total 8838634197 # number of demand (read+write) MSHR miss cycles 3199system.iocache.overall_mshr_miss_latency::realview.ethernet 3615000 # number of overall MSHR miss cycles 3200system.iocache.overall_mshr_miss_latency::realview.ide 8835019197 # number of overall MSHR miss cycles 3201system.iocache.overall_mshr_miss_latency::total 8838634197 # number of overall MSHR miss cycles 3202system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 3203system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3204system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3205system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 3206system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 3207system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 3208system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 3209system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 3210system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3211system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3212system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 3213system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3214system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 3215system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91783.783784 # average ReadReq mshr miss latency 3216system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137758.641225 # average ReadReq mshr miss latency 3217system.iocache.ReadReq_avg_mshr_miss_latency::total 137567.938341 # average ReadReq mshr miss latency 3218system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 3219system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 3220system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71315.017493 # average WriteLineReq mshr miss latency 3221system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71315.017493 # average WriteLineReq mshr miss latency 3222system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency 3223system.iocache.demand_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency 3224system.iocache.demand_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency 3225system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency 3226system.iocache.overall_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency 3227system.iocache.overall_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency 3228system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3229system.l2c.tags.replacements 1423185 # number of replacements 3230system.l2c.tags.tagsinuse 63448.336905 # Cycle average of tags in use 3231system.l2c.tags.total_refs 6060449 # Total number of references to valid blocks. 3232system.l2c.tags.sampled_refs 1482600 # Sample count of references to valid blocks. 3233system.l2c.tags.avg_refs 4.087717 # Average number of references to valid blocks. 3234system.l2c.tags.warmup_cycle 3022937500 # Cycle when the warmup percentage was hit. 3235system.l2c.tags.occ_blocks::writebacks 20826.975184 # Average occupied blocks per requestor 3236system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.832374 # Average occupied blocks per requestor 3237system.l2c.tags.occ_blocks::cpu0.itb.walker 12.742051 # Average occupied blocks per requestor 3238system.l2c.tags.occ_blocks::cpu0.inst 3854.622142 # Average occupied blocks per requestor 3239system.l2c.tags.occ_blocks::cpu0.data 3569.542843 # Average occupied blocks per requestor 3240system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 2315.690288 # Average occupied blocks per requestor 3241system.l2c.tags.occ_blocks::cpu1.dtb.walker 335.622211 # Average occupied blocks per requestor 3242system.l2c.tags.occ_blocks::cpu1.itb.walker 552.279614 # Average occupied blocks per requestor 3243system.l2c.tags.occ_blocks::cpu1.inst 2996.807733 # Average occupied blocks per requestor 3244system.l2c.tags.occ_blocks::cpu1.data 11095.009846 # Average occupied blocks per requestor 3245system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17872.212619 # Average occupied blocks per requestor 3246system.l2c.tags.occ_percent::writebacks 0.317794 # Average percentage of cache occupancy 3247system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000257 # Average percentage of cache occupancy 3248system.l2c.tags.occ_percent::cpu0.itb.walker 0.000194 # Average percentage of cache occupancy 3249system.l2c.tags.occ_percent::cpu0.inst 0.058817 # Average percentage of cache occupancy 3250system.l2c.tags.occ_percent::cpu0.data 0.054467 # Average percentage of cache occupancy 3251system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.035335 # Average percentage of cache occupancy 3252system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005121 # Average percentage of cache occupancy 3253system.l2c.tags.occ_percent::cpu1.itb.walker 0.008427 # Average percentage of cache occupancy 3254system.l2c.tags.occ_percent::cpu1.inst 0.045728 # Average percentage of cache occupancy 3255system.l2c.tags.occ_percent::cpu1.data 0.169296 # Average percentage of cache occupancy 3256system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.272708 # Average percentage of cache occupancy 3257system.l2c.tags.occ_percent::total 0.968145 # Average percentage of cache occupancy 3258system.l2c.tags.occ_task_id_blocks::1022 10702 # Occupied blocks per task id 3259system.l2c.tags.occ_task_id_blocks::1023 222 # Occupied blocks per task id 3260system.l2c.tags.occ_task_id_blocks::1024 48491 # Occupied blocks per task id 3261system.l2c.tags.age_task_id_blocks_1022::0 11 # Occupied blocks per task id 3262system.l2c.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id 3263system.l2c.tags.age_task_id_blocks_1022::2 1377 # Occupied blocks per task id 3264system.l2c.tags.age_task_id_blocks_1022::3 482 # Occupied blocks per task id 3265system.l2c.tags.age_task_id_blocks_1022::4 8826 # Occupied blocks per task id 3266system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 3267system.l2c.tags.age_task_id_blocks_1023::4 218 # Occupied blocks per task id 3268system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 3269system.l2c.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id 3270system.l2c.tags.age_task_id_blocks_1024::2 2760 # Occupied blocks per task id 3271system.l2c.tags.age_task_id_blocks_1024::3 5614 # Occupied blocks per task id 3272system.l2c.tags.age_task_id_blocks_1024::4 39761 # Occupied blocks per task id 3273system.l2c.tags.occ_task_id_percent::1022 0.163300 # Percentage of cache occupancy per task id 3274system.l2c.tags.occ_task_id_percent::1023 0.003387 # Percentage of cache occupancy per task id 3275system.l2c.tags.occ_task_id_percent::1024 0.739914 # Percentage of cache occupancy per task id 3276system.l2c.tags.tag_accesses 76659871 # Number of tag accesses 3277system.l2c.tags.data_accesses 76659871 # Number of data accesses 3278system.l2c.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3279system.l2c.WritebackDirty_hits::writebacks 2799563 # number of WritebackDirty hits 3280system.l2c.WritebackDirty_hits::total 2799563 # number of WritebackDirty hits 3281system.l2c.UpgradeReq_hits::cpu0.data 175772 # number of UpgradeReq hits 3282system.l2c.UpgradeReq_hits::cpu1.data 127713 # number of UpgradeReq hits 3283system.l2c.UpgradeReq_hits::total 303485 # number of UpgradeReq hits 3284system.l2c.SCUpgradeReq_hits::cpu0.data 39800 # number of SCUpgradeReq hits 3285system.l2c.SCUpgradeReq_hits::cpu1.data 41169 # number of SCUpgradeReq hits 3286system.l2c.SCUpgradeReq_hits::total 80969 # number of SCUpgradeReq hits 3287system.l2c.ReadExReq_hits::cpu0.data 55176 # number of ReadExReq hits 3288system.l2c.ReadExReq_hits::cpu1.data 52470 # number of ReadExReq hits 3289system.l2c.ReadExReq_hits::total 107646 # number of ReadExReq hits 3290system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6441 # number of ReadSharedReq hits 3291system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4632 # number of ReadSharedReq hits 3292system.l2c.ReadSharedReq_hits::cpu0.inst 512914 # number of ReadSharedReq hits 3293system.l2c.ReadSharedReq_hits::cpu0.data 602529 # number of ReadSharedReq hits 3294system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 321191 # number of ReadSharedReq hits 3295system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6205 # number of ReadSharedReq hits 3296system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4222 # number of ReadSharedReq hits 3297system.l2c.ReadSharedReq_hits::cpu1.inst 506602 # number of ReadSharedReq hits 3298system.l2c.ReadSharedReq_hits::cpu1.data 564191 # number of ReadSharedReq hits 3299system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 285940 # number of ReadSharedReq hits 3300system.l2c.ReadSharedReq_hits::total 2814867 # number of ReadSharedReq hits 3301system.l2c.InvalidateReq_hits::cpu0.data 134470 # number of InvalidateReq hits 3302system.l2c.InvalidateReq_hits::cpu1.data 123510 # number of InvalidateReq hits 3303system.l2c.InvalidateReq_hits::total 257980 # number of InvalidateReq hits 3304system.l2c.demand_hits::cpu0.dtb.walker 6441 # number of demand (read+write) hits 3305system.l2c.demand_hits::cpu0.itb.walker 4632 # number of demand (read+write) hits 3306system.l2c.demand_hits::cpu0.inst 512914 # number of demand (read+write) hits 3307system.l2c.demand_hits::cpu0.data 657705 # number of demand (read+write) hits 3308system.l2c.demand_hits::cpu0.l2cache.prefetcher 321191 # number of demand (read+write) hits 3309system.l2c.demand_hits::cpu1.dtb.walker 6205 # number of demand (read+write) hits 3310system.l2c.demand_hits::cpu1.itb.walker 4222 # number of demand (read+write) hits 3311system.l2c.demand_hits::cpu1.inst 506602 # number of demand (read+write) hits 3312system.l2c.demand_hits::cpu1.data 616661 # number of demand (read+write) hits 3313system.l2c.demand_hits::cpu1.l2cache.prefetcher 285940 # number of demand (read+write) hits 3314system.l2c.demand_hits::total 2922513 # number of demand (read+write) hits 3315system.l2c.overall_hits::cpu0.dtb.walker 6441 # number of overall hits 3316system.l2c.overall_hits::cpu0.itb.walker 4632 # number of overall hits 3317system.l2c.overall_hits::cpu0.inst 512914 # number of overall hits 3318system.l2c.overall_hits::cpu0.data 657705 # number of overall hits 3319system.l2c.overall_hits::cpu0.l2cache.prefetcher 321191 # number of overall hits 3320system.l2c.overall_hits::cpu1.dtb.walker 6205 # number of overall hits 3321system.l2c.overall_hits::cpu1.itb.walker 4222 # number of overall hits 3322system.l2c.overall_hits::cpu1.inst 506602 # number of overall hits 3323system.l2c.overall_hits::cpu1.data 616661 # number of overall hits 3324system.l2c.overall_hits::cpu1.l2cache.prefetcher 285940 # number of overall hits 3325system.l2c.overall_hits::total 2922513 # number of overall hits 3326system.l2c.UpgradeReq_misses::cpu0.data 65800 # number of UpgradeReq misses 3327system.l2c.UpgradeReq_misses::cpu1.data 60076 # number of UpgradeReq misses 3328system.l2c.UpgradeReq_misses::total 125876 # number of UpgradeReq misses 3329system.l2c.SCUpgradeReq_misses::cpu0.data 12292 # number of SCUpgradeReq misses 3330system.l2c.SCUpgradeReq_misses::cpu1.data 11651 # number of SCUpgradeReq misses 3331system.l2c.SCUpgradeReq_misses::total 23943 # number of SCUpgradeReq misses 3332system.l2c.ReadExReq_misses::cpu0.data 76423 # number of ReadExReq misses 3333system.l2c.ReadExReq_misses::cpu1.data 57499 # number of ReadExReq misses 3334system.l2c.ReadExReq_misses::total 133922 # number of ReadExReq misses 3335system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1380 # number of ReadSharedReq misses 3336system.l2c.ReadSharedReq_misses::cpu0.itb.walker 911 # number of ReadSharedReq misses 3337system.l2c.ReadSharedReq_misses::cpu0.inst 60940 # number of ReadSharedReq misses 3338system.l2c.ReadSharedReq_misses::cpu0.data 127468 # number of ReadSharedReq misses 3339system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 217255 # number of ReadSharedReq misses 3340system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3149 # number of ReadSharedReq misses 3341system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2958 # number of ReadSharedReq misses 3342system.l2c.ReadSharedReq_misses::cpu1.inst 41472 # number of ReadSharedReq misses 3343system.l2c.ReadSharedReq_misses::cpu1.data 123752 # number of ReadSharedReq misses 3344system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 256869 # number of ReadSharedReq misses 3345system.l2c.ReadSharedReq_misses::total 836154 # number of ReadSharedReq misses 3346system.l2c.InvalidateReq_misses::cpu0.data 453643 # number of InvalidateReq misses 3347system.l2c.InvalidateReq_misses::cpu1.data 128024 # number of InvalidateReq misses 3348system.l2c.InvalidateReq_misses::total 581667 # number of InvalidateReq misses 3349system.l2c.demand_misses::cpu0.dtb.walker 1380 # number of demand (read+write) misses 3350system.l2c.demand_misses::cpu0.itb.walker 911 # number of demand (read+write) misses 3351system.l2c.demand_misses::cpu0.inst 60940 # number of demand (read+write) misses 3352system.l2c.demand_misses::cpu0.data 203891 # number of demand (read+write) misses 3353system.l2c.demand_misses::cpu0.l2cache.prefetcher 217255 # number of demand (read+write) misses 3354system.l2c.demand_misses::cpu1.dtb.walker 3149 # number of demand (read+write) misses 3355system.l2c.demand_misses::cpu1.itb.walker 2958 # number of demand (read+write) misses 3356system.l2c.demand_misses::cpu1.inst 41472 # number of demand (read+write) misses 3357system.l2c.demand_misses::cpu1.data 181251 # number of demand (read+write) misses 3358system.l2c.demand_misses::cpu1.l2cache.prefetcher 256869 # number of demand (read+write) misses 3359system.l2c.demand_misses::total 970076 # number of demand (read+write) misses 3360system.l2c.overall_misses::cpu0.dtb.walker 1380 # number of overall misses 3361system.l2c.overall_misses::cpu0.itb.walker 911 # number of overall misses 3362system.l2c.overall_misses::cpu0.inst 60940 # number of overall misses 3363system.l2c.overall_misses::cpu0.data 203891 # number of overall misses 3364system.l2c.overall_misses::cpu0.l2cache.prefetcher 217255 # number of overall misses 3365system.l2c.overall_misses::cpu1.dtb.walker 3149 # number of overall misses 3366system.l2c.overall_misses::cpu1.itb.walker 2958 # number of overall misses 3367system.l2c.overall_misses::cpu1.inst 41472 # number of overall misses 3368system.l2c.overall_misses::cpu1.data 181251 # number of overall misses 3369system.l2c.overall_misses::cpu1.l2cache.prefetcher 256869 # number of overall misses 3370system.l2c.overall_misses::total 970076 # number of overall misses 3371system.l2c.UpgradeReq_miss_latency::cpu0.data 448544000 # number of UpgradeReq miss cycles 3372system.l2c.UpgradeReq_miss_latency::cpu1.data 390663000 # number of UpgradeReq miss cycles 3373system.l2c.UpgradeReq_miss_latency::total 839207000 # number of UpgradeReq miss cycles 3374system.l2c.SCUpgradeReq_miss_latency::cpu0.data 74504000 # number of SCUpgradeReq miss cycles 3375system.l2c.SCUpgradeReq_miss_latency::cpu1.data 75234500 # number of SCUpgradeReq miss cycles 3376system.l2c.SCUpgradeReq_miss_latency::total 149738500 # number of SCUpgradeReq miss cycles 3377system.l2c.ReadExReq_miss_latency::cpu0.data 6937615986 # number of ReadExReq miss cycles 3378system.l2c.ReadExReq_miss_latency::cpu1.data 5199044498 # number of ReadExReq miss cycles 3379system.l2c.ReadExReq_miss_latency::total 12136660484 # number of ReadExReq miss cycles 3380system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 131946500 # number of ReadSharedReq miss cycles 3381system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 85177500 # number of ReadSharedReq miss cycles 3382system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5320925500 # number of ReadSharedReq miss cycles 3383system.l2c.ReadSharedReq_miss_latency::cpu0.data 12028584244 # number of ReadSharedReq miss cycles 3384system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 30519314752 # number of ReadSharedReq miss cycles 3385system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 290010000 # number of ReadSharedReq miss cycles 3386system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 265646000 # number of ReadSharedReq miss cycles 3387system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3652893500 # number of ReadSharedReq miss cycles 3388system.l2c.ReadSharedReq_miss_latency::cpu1.data 11931003997 # number of ReadSharedReq miss cycles 3389system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 35372822568 # number of ReadSharedReq miss cycles 3390system.l2c.ReadSharedReq_miss_latency::total 99598324561 # number of ReadSharedReq miss cycles 3391system.l2c.InvalidateReq_miss_latency::cpu0.data 58512500 # number of InvalidateReq miss cycles 3392system.l2c.InvalidateReq_miss_latency::cpu1.data 49578000 # number of InvalidateReq miss cycles 3393system.l2c.InvalidateReq_miss_latency::total 108090500 # number of InvalidateReq miss cycles 3394system.l2c.demand_miss_latency::cpu0.dtb.walker 131946500 # number of demand (read+write) miss cycles 3395system.l2c.demand_miss_latency::cpu0.itb.walker 85177500 # number of demand (read+write) miss cycles 3396system.l2c.demand_miss_latency::cpu0.inst 5320925500 # number of demand (read+write) miss cycles 3397system.l2c.demand_miss_latency::cpu0.data 18966200230 # number of demand (read+write) miss cycles 3398system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 30519314752 # number of demand (read+write) miss cycles 3399system.l2c.demand_miss_latency::cpu1.dtb.walker 290010000 # number of demand (read+write) miss cycles 3400system.l2c.demand_miss_latency::cpu1.itb.walker 265646000 # number of demand (read+write) miss cycles 3401system.l2c.demand_miss_latency::cpu1.inst 3652893500 # number of demand (read+write) miss cycles 3402system.l2c.demand_miss_latency::cpu1.data 17130048495 # number of demand (read+write) miss cycles 3403system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 35372822568 # number of demand (read+write) miss cycles 3404system.l2c.demand_miss_latency::total 111734985045 # number of demand (read+write) miss cycles 3405system.l2c.overall_miss_latency::cpu0.dtb.walker 131946500 # number of overall miss cycles 3406system.l2c.overall_miss_latency::cpu0.itb.walker 85177500 # number of overall miss cycles 3407system.l2c.overall_miss_latency::cpu0.inst 5320925500 # number of overall miss cycles 3408system.l2c.overall_miss_latency::cpu0.data 18966200230 # number of overall miss cycles 3409system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 30519314752 # number of overall miss cycles 3410system.l2c.overall_miss_latency::cpu1.dtb.walker 290010000 # number of overall miss cycles 3411system.l2c.overall_miss_latency::cpu1.itb.walker 265646000 # number of overall miss cycles 3412system.l2c.overall_miss_latency::cpu1.inst 3652893500 # number of overall miss cycles 3413system.l2c.overall_miss_latency::cpu1.data 17130048495 # number of overall miss cycles 3414system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 35372822568 # number of overall miss cycles 3415system.l2c.overall_miss_latency::total 111734985045 # number of overall miss cycles 3416system.l2c.WritebackDirty_accesses::writebacks 2799563 # number of WritebackDirty accesses(hits+misses) 3417system.l2c.WritebackDirty_accesses::total 2799563 # number of WritebackDirty accesses(hits+misses) 3418system.l2c.UpgradeReq_accesses::cpu0.data 241572 # number of UpgradeReq accesses(hits+misses) 3419system.l2c.UpgradeReq_accesses::cpu1.data 187789 # number of UpgradeReq accesses(hits+misses) 3420system.l2c.UpgradeReq_accesses::total 429361 # number of UpgradeReq accesses(hits+misses) 3421system.l2c.SCUpgradeReq_accesses::cpu0.data 52092 # number of SCUpgradeReq accesses(hits+misses) 3422system.l2c.SCUpgradeReq_accesses::cpu1.data 52820 # number of SCUpgradeReq accesses(hits+misses) 3423system.l2c.SCUpgradeReq_accesses::total 104912 # number of SCUpgradeReq accesses(hits+misses) 3424system.l2c.ReadExReq_accesses::cpu0.data 131599 # number of ReadExReq accesses(hits+misses) 3425system.l2c.ReadExReq_accesses::cpu1.data 109969 # number of ReadExReq accesses(hits+misses) 3426system.l2c.ReadExReq_accesses::total 241568 # number of ReadExReq accesses(hits+misses) 3427system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7821 # number of ReadSharedReq accesses(hits+misses) 3428system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5543 # number of ReadSharedReq accesses(hits+misses) 3429system.l2c.ReadSharedReq_accesses::cpu0.inst 573854 # number of ReadSharedReq accesses(hits+misses) 3430system.l2c.ReadSharedReq_accesses::cpu0.data 729997 # number of ReadSharedReq accesses(hits+misses) 3431system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 538446 # number of ReadSharedReq accesses(hits+misses) 3432system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9354 # number of ReadSharedReq accesses(hits+misses) 3433system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7180 # number of ReadSharedReq accesses(hits+misses) 3434system.l2c.ReadSharedReq_accesses::cpu1.inst 548074 # number of ReadSharedReq accesses(hits+misses) 3435system.l2c.ReadSharedReq_accesses::cpu1.data 687943 # number of ReadSharedReq accesses(hits+misses) 3436system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 542809 # number of ReadSharedReq accesses(hits+misses) 3437system.l2c.ReadSharedReq_accesses::total 3651021 # number of ReadSharedReq accesses(hits+misses) 3438system.l2c.InvalidateReq_accesses::cpu0.data 588113 # number of InvalidateReq accesses(hits+misses) 3439system.l2c.InvalidateReq_accesses::cpu1.data 251534 # number of InvalidateReq accesses(hits+misses) 3440system.l2c.InvalidateReq_accesses::total 839647 # number of InvalidateReq accesses(hits+misses) 3441system.l2c.demand_accesses::cpu0.dtb.walker 7821 # number of demand (read+write) accesses 3442system.l2c.demand_accesses::cpu0.itb.walker 5543 # number of demand (read+write) accesses 3443system.l2c.demand_accesses::cpu0.inst 573854 # number of demand (read+write) accesses 3444system.l2c.demand_accesses::cpu0.data 861596 # number of demand (read+write) accesses 3445system.l2c.demand_accesses::cpu0.l2cache.prefetcher 538446 # number of demand (read+write) accesses 3446system.l2c.demand_accesses::cpu1.dtb.walker 9354 # number of demand (read+write) accesses 3447system.l2c.demand_accesses::cpu1.itb.walker 7180 # number of demand (read+write) accesses 3448system.l2c.demand_accesses::cpu1.inst 548074 # number of demand (read+write) accesses 3449system.l2c.demand_accesses::cpu1.data 797912 # number of demand (read+write) accesses 3450system.l2c.demand_accesses::cpu1.l2cache.prefetcher 542809 # number of demand (read+write) accesses 3451system.l2c.demand_accesses::total 3892589 # number of demand (read+write) accesses 3452system.l2c.overall_accesses::cpu0.dtb.walker 7821 # number of overall (read+write) accesses 3453system.l2c.overall_accesses::cpu0.itb.walker 5543 # number of overall (read+write) accesses 3454system.l2c.overall_accesses::cpu0.inst 573854 # number of overall (read+write) accesses 3455system.l2c.overall_accesses::cpu0.data 861596 # number of overall (read+write) accesses 3456system.l2c.overall_accesses::cpu0.l2cache.prefetcher 538446 # number of overall (read+write) accesses 3457system.l2c.overall_accesses::cpu1.dtb.walker 9354 # number of overall (read+write) accesses 3458system.l2c.overall_accesses::cpu1.itb.walker 7180 # number of overall (read+write) accesses 3459system.l2c.overall_accesses::cpu1.inst 548074 # number of overall (read+write) accesses 3460system.l2c.overall_accesses::cpu1.data 797912 # number of overall (read+write) accesses 3461system.l2c.overall_accesses::cpu1.l2cache.prefetcher 542809 # number of overall (read+write) accesses 3462system.l2c.overall_accesses::total 3892589 # number of overall (read+write) accesses 3463system.l2c.UpgradeReq_miss_rate::cpu0.data 0.272383 # miss rate for UpgradeReq accesses 3464system.l2c.UpgradeReq_miss_rate::cpu1.data 0.319912 # miss rate for UpgradeReq accesses 3465system.l2c.UpgradeReq_miss_rate::total 0.293171 # miss rate for UpgradeReq accesses 3466system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.235967 # miss rate for SCUpgradeReq accesses 3467system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.220579 # miss rate for SCUpgradeReq accesses 3468system.l2c.SCUpgradeReq_miss_rate::total 0.228220 # miss rate for SCUpgradeReq accesses 3469system.l2c.ReadExReq_miss_rate::cpu0.data 0.580726 # miss rate for ReadExReq accesses 3470system.l2c.ReadExReq_miss_rate::cpu1.data 0.522866 # miss rate for ReadExReq accesses 3471system.l2c.ReadExReq_miss_rate::total 0.554386 # miss rate for ReadExReq accesses 3472system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.176448 # miss rate for ReadSharedReq accesses 3473system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.164351 # miss rate for ReadSharedReq accesses 3474system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.106194 # miss rate for ReadSharedReq accesses 3475system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.174614 # miss rate for ReadSharedReq accesses 3476system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.403485 # miss rate for ReadSharedReq accesses 3477system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.336647 # miss rate for ReadSharedReq accesses 3478system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.411978 # miss rate for ReadSharedReq accesses 3479system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.075669 # miss rate for ReadSharedReq accesses 3480system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.179887 # miss rate for ReadSharedReq accesses 3481system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.473222 # miss rate for ReadSharedReq accesses 3482system.l2c.ReadSharedReq_miss_rate::total 0.229019 # miss rate for ReadSharedReq accesses 3483system.l2c.InvalidateReq_miss_rate::cpu0.data 0.771353 # miss rate for InvalidateReq accesses 3484system.l2c.InvalidateReq_miss_rate::cpu1.data 0.508973 # miss rate for InvalidateReq accesses 3485system.l2c.InvalidateReq_miss_rate::total 0.692752 # miss rate for InvalidateReq accesses 3486system.l2c.demand_miss_rate::cpu0.dtb.walker 0.176448 # miss rate for demand accesses 3487system.l2c.demand_miss_rate::cpu0.itb.walker 0.164351 # miss rate for demand accesses 3488system.l2c.demand_miss_rate::cpu0.inst 0.106194 # miss rate for demand accesses 3489system.l2c.demand_miss_rate::cpu0.data 0.236643 # miss rate for demand accesses 3490system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.403485 # miss rate for demand accesses 3491system.l2c.demand_miss_rate::cpu1.dtb.walker 0.336647 # miss rate for demand accesses 3492system.l2c.demand_miss_rate::cpu1.itb.walker 0.411978 # miss rate for demand accesses 3493system.l2c.demand_miss_rate::cpu1.inst 0.075669 # miss rate for demand accesses 3494system.l2c.demand_miss_rate::cpu1.data 0.227157 # miss rate for demand accesses 3495system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.473222 # miss rate for demand accesses 3496system.l2c.demand_miss_rate::total 0.249211 # miss rate for demand accesses 3497system.l2c.overall_miss_rate::cpu0.dtb.walker 0.176448 # miss rate for overall accesses 3498system.l2c.overall_miss_rate::cpu0.itb.walker 0.164351 # miss rate for overall accesses 3499system.l2c.overall_miss_rate::cpu0.inst 0.106194 # miss rate for overall accesses 3500system.l2c.overall_miss_rate::cpu0.data 0.236643 # miss rate for overall accesses 3501system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.403485 # miss rate for overall accesses 3502system.l2c.overall_miss_rate::cpu1.dtb.walker 0.336647 # miss rate for overall accesses 3503system.l2c.overall_miss_rate::cpu1.itb.walker 0.411978 # miss rate for overall accesses 3504system.l2c.overall_miss_rate::cpu1.inst 0.075669 # miss rate for overall accesses 3505system.l2c.overall_miss_rate::cpu1.data 0.227157 # miss rate for overall accesses 3506system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.473222 # miss rate for overall accesses 3507system.l2c.overall_miss_rate::total 0.249211 # miss rate for overall accesses 3508system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6816.778116 # average UpgradeReq miss latency 3509system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6502.813103 # average UpgradeReq miss latency 3510system.l2c.UpgradeReq_avg_miss_latency::total 6666.934126 # average UpgradeReq miss latency 3511system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6061.178002 # average SCUpgradeReq miss latency 3512system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6457.342717 # average SCUpgradeReq miss latency 3513system.l2c.SCUpgradeReq_avg_miss_latency::total 6253.957315 # average SCUpgradeReq miss latency 3514system.l2c.ReadExReq_avg_miss_latency::cpu0.data 90779.163158 # average ReadExReq miss latency 3515system.l2c.ReadExReq_avg_miss_latency::cpu1.data 90419.737700 # average ReadExReq miss latency 3516system.l2c.ReadExReq_avg_miss_latency::total 90624.844940 # average ReadExReq miss latency 3517system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 95613.405797 # average ReadSharedReq miss latency 3518system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 93498.902305 # average ReadSharedReq miss latency 3519system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 87314.169675 # average ReadSharedReq miss latency 3520system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 94365.521103 # average ReadSharedReq miss latency 3521system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 140476.926892 # average ReadSharedReq miss latency 3522system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92095.903461 # average ReadSharedReq miss latency 3523system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 89805.949966 # average ReadSharedReq miss latency 3524system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 88080.958237 # average ReadSharedReq miss latency 3525system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 96410.595360 # average ReadSharedReq miss latency 3526system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 137707.635285 # average ReadSharedReq miss latency 3527system.l2c.ReadSharedReq_avg_miss_latency::total 119114.809665 # average ReadSharedReq miss latency 3528system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 128.983584 # average InvalidateReq miss latency 3529system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 387.255515 # average InvalidateReq miss latency 3530system.l2c.InvalidateReq_avg_miss_latency::total 185.828833 # average InvalidateReq miss latency 3531system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 95613.405797 # average overall miss latency 3532system.l2c.demand_avg_miss_latency::cpu0.itb.walker 93498.902305 # average overall miss latency 3533system.l2c.demand_avg_miss_latency::cpu0.inst 87314.169675 # average overall miss latency 3534system.l2c.demand_avg_miss_latency::cpu0.data 93021.272297 # average overall miss latency 3535system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 140476.926892 # average overall miss latency 3536system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92095.903461 # average overall miss latency 3537system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89805.949966 # average overall miss latency 3538system.l2c.demand_avg_miss_latency::cpu1.inst 88080.958237 # average overall miss latency 3539system.l2c.demand_avg_miss_latency::cpu1.data 94510.090951 # average overall miss latency 3540system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 137707.635285 # average overall miss latency 3541system.l2c.demand_avg_miss_latency::total 115181.681688 # average overall miss latency 3542system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 95613.405797 # average overall miss latency 3543system.l2c.overall_avg_miss_latency::cpu0.itb.walker 93498.902305 # average overall miss latency 3544system.l2c.overall_avg_miss_latency::cpu0.inst 87314.169675 # average overall miss latency 3545system.l2c.overall_avg_miss_latency::cpu0.data 93021.272297 # average overall miss latency 3546system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 140476.926892 # average overall miss latency 3547system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92095.903461 # average overall miss latency 3548system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89805.949966 # average overall miss latency 3549system.l2c.overall_avg_miss_latency::cpu1.inst 88080.958237 # average overall miss latency 3550system.l2c.overall_avg_miss_latency::cpu1.data 94510.090951 # average overall miss latency 3551system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 137707.635285 # average overall miss latency 3552system.l2c.overall_avg_miss_latency::total 115181.681688 # average overall miss latency 3553system.l2c.blocked_cycles::no_mshrs 9550 # number of cycles access was blocked 3554system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3555system.l2c.blocked::no_mshrs 102 # number of cycles access was blocked 3556system.l2c.blocked::no_targets 0 # number of cycles access was blocked 3557system.l2c.avg_blocked_cycles::no_mshrs 93.627451 # average number of cycles each access was blocked 3558system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3559system.l2c.writebacks::writebacks 1135323 # number of writebacks 3560system.l2c.writebacks::total 1135323 # number of writebacks 3561system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 111 # number of ReadSharedReq MSHR hits 3562system.l2c.ReadSharedReq_mshr_hits::cpu0.data 20 # number of ReadSharedReq MSHR hits 3563system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 109 # number of ReadSharedReq MSHR hits 3564system.l2c.ReadSharedReq_mshr_hits::cpu1.data 8 # number of ReadSharedReq MSHR hits 3565system.l2c.ReadSharedReq_mshr_hits::total 248 # number of ReadSharedReq MSHR hits 3566system.l2c.demand_mshr_hits::cpu0.inst 111 # number of demand (read+write) MSHR hits 3567system.l2c.demand_mshr_hits::cpu0.data 20 # number of demand (read+write) MSHR hits 3568system.l2c.demand_mshr_hits::cpu1.inst 109 # number of demand (read+write) MSHR hits 3569system.l2c.demand_mshr_hits::cpu1.data 8 # number of demand (read+write) MSHR hits 3570system.l2c.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits 3571system.l2c.overall_mshr_hits::cpu0.inst 111 # number of overall MSHR hits 3572system.l2c.overall_mshr_hits::cpu0.data 20 # number of overall MSHR hits 3573system.l2c.overall_mshr_hits::cpu1.inst 109 # number of overall MSHR hits 3574system.l2c.overall_mshr_hits::cpu1.data 8 # number of overall MSHR hits 3575system.l2c.overall_mshr_hits::total 248 # number of overall MSHR hits 3576system.l2c.CleanEvict_mshr_misses::writebacks 49298 # number of CleanEvict MSHR misses 3577system.l2c.CleanEvict_mshr_misses::total 49298 # number of CleanEvict MSHR misses 3578system.l2c.UpgradeReq_mshr_misses::cpu0.data 65800 # number of UpgradeReq MSHR misses 3579system.l2c.UpgradeReq_mshr_misses::cpu1.data 60076 # number of UpgradeReq MSHR misses 3580system.l2c.UpgradeReq_mshr_misses::total 125876 # number of UpgradeReq MSHR misses 3581system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12292 # number of SCUpgradeReq MSHR misses 3582system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11651 # number of SCUpgradeReq MSHR misses 3583system.l2c.SCUpgradeReq_mshr_misses::total 23943 # number of SCUpgradeReq MSHR misses 3584system.l2c.ReadExReq_mshr_misses::cpu0.data 76423 # number of ReadExReq MSHR misses 3585system.l2c.ReadExReq_mshr_misses::cpu1.data 57499 # number of ReadExReq MSHR misses 3586system.l2c.ReadExReq_mshr_misses::total 133922 # number of ReadExReq MSHR misses 3587system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1380 # number of ReadSharedReq MSHR misses 3588system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 911 # number of ReadSharedReq MSHR misses 3589system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 60829 # number of ReadSharedReq MSHR misses 3590system.l2c.ReadSharedReq_mshr_misses::cpu0.data 127448 # number of ReadSharedReq MSHR misses 3591system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 217255 # number of ReadSharedReq MSHR misses 3592system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 3149 # number of ReadSharedReq MSHR misses 3593system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2958 # number of ReadSharedReq MSHR misses 3594system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 41363 # number of ReadSharedReq MSHR misses 3595system.l2c.ReadSharedReq_mshr_misses::cpu1.data 123744 # number of ReadSharedReq MSHR misses 3596system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 256869 # number of ReadSharedReq MSHR misses 3597system.l2c.ReadSharedReq_mshr_misses::total 835906 # number of ReadSharedReq MSHR misses 3598system.l2c.InvalidateReq_mshr_misses::cpu0.data 453643 # number of InvalidateReq MSHR misses 3599system.l2c.InvalidateReq_mshr_misses::cpu1.data 128024 # number of InvalidateReq MSHR misses 3600system.l2c.InvalidateReq_mshr_misses::total 581667 # number of InvalidateReq MSHR misses 3601system.l2c.demand_mshr_misses::cpu0.dtb.walker 1380 # number of demand (read+write) MSHR misses 3602system.l2c.demand_mshr_misses::cpu0.itb.walker 911 # number of demand (read+write) MSHR misses 3603system.l2c.demand_mshr_misses::cpu0.inst 60829 # number of demand (read+write) MSHR misses 3604system.l2c.demand_mshr_misses::cpu0.data 203871 # number of demand (read+write) MSHR misses 3605system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 217255 # number of demand (read+write) MSHR misses 3606system.l2c.demand_mshr_misses::cpu1.dtb.walker 3149 # number of demand (read+write) MSHR misses 3607system.l2c.demand_mshr_misses::cpu1.itb.walker 2958 # number of demand (read+write) MSHR misses 3608system.l2c.demand_mshr_misses::cpu1.inst 41363 # number of demand (read+write) MSHR misses 3609system.l2c.demand_mshr_misses::cpu1.data 181243 # number of demand (read+write) MSHR misses 3610system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 256869 # number of demand (read+write) MSHR misses 3611system.l2c.demand_mshr_misses::total 969828 # number of demand (read+write) MSHR misses 3612system.l2c.overall_mshr_misses::cpu0.dtb.walker 1380 # number of overall MSHR misses 3613system.l2c.overall_mshr_misses::cpu0.itb.walker 911 # number of overall MSHR misses 3614system.l2c.overall_mshr_misses::cpu0.inst 60829 # number of overall MSHR misses 3615system.l2c.overall_mshr_misses::cpu0.data 203871 # number of overall MSHR misses 3616system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 217255 # number of overall MSHR misses 3617system.l2c.overall_mshr_misses::cpu1.dtb.walker 3149 # number of overall MSHR misses 3618system.l2c.overall_mshr_misses::cpu1.itb.walker 2958 # number of overall MSHR misses 3619system.l2c.overall_mshr_misses::cpu1.inst 41363 # number of overall MSHR misses 3620system.l2c.overall_mshr_misses::cpu1.data 181243 # number of overall MSHR misses 3621system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 256869 # number of overall MSHR misses 3622system.l2c.overall_mshr_misses::total 969828 # number of overall MSHR misses 3623system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 3624system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32527 # number of ReadReq MSHR uncacheable 3625system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 3626system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6116 # number of ReadReq MSHR uncacheable 3627system.l2c.ReadReq_mshr_uncacheable::total 60003 # number of ReadReq MSHR uncacheable 3628system.l2c.WriteReq_mshr_uncacheable::cpu0.data 32351 # number of WriteReq MSHR uncacheable 3629system.l2c.WriteReq_mshr_uncacheable::cpu1.data 6183 # number of WriteReq MSHR uncacheable 3630system.l2c.WriteReq_mshr_uncacheable::total 38534 # number of WriteReq MSHR uncacheable 3631system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 3632system.l2c.overall_mshr_uncacheable_misses::cpu0.data 64878 # number of overall MSHR uncacheable misses 3633system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 3634system.l2c.overall_mshr_uncacheable_misses::cpu1.data 12299 # number of overall MSHR uncacheable misses 3635system.l2c.overall_mshr_uncacheable_misses::total 98537 # number of overall MSHR uncacheable misses 3636system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1434481502 # number of UpgradeReq MSHR miss cycles 3637system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 1290497995 # number of UpgradeReq MSHR miss cycles 3638system.l2c.UpgradeReq_mshr_miss_latency::total 2724979497 # number of UpgradeReq MSHR miss cycles 3639system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 303964499 # number of SCUpgradeReq MSHR miss cycles 3640system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 285788496 # number of SCUpgradeReq MSHR miss cycles 3641system.l2c.SCUpgradeReq_mshr_miss_latency::total 589752995 # number of SCUpgradeReq MSHR miss cycles 3642system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6173210845 # number of ReadExReq MSHR miss cycles 3643system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4623959192 # 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number of overall MSHR miss cycles 3671system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 76067500 # number of overall MSHR miss cycles 3672system.l2c.overall_mshr_miss_latency::cpu0.inst 4704505587 # number of overall MSHR miss cycles 3673system.l2c.overall_mshr_miss_latency::cpu0.data 16925663829 # number of overall MSHR miss cycles 3674system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 28346572172 # number of overall MSHR miss cycles 3675system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 258517505 # number of overall MSHR miss cycles 3676system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 236065501 # number of overall MSHR miss cycles 3677system.l2c.overall_mshr_miss_latency::cpu1.inst 3231267055 # number of overall MSHR miss cycles 3678system.l2c.overall_mshr_miss_latency::cpu1.data 15316786940 # number of overall MSHR miss cycles 3679system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 32803939514 # number of overall MSHR miss cycles 3680system.l2c.overall_mshr_miss_latency::total 102017531105 # number of overall MSHR miss cycles 3681system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1342704500 # number of ReadReq MSHR uncacheable cycles 3682system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5362205005 # number of ReadReq MSHR uncacheable cycles 3683system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5079500 # number of ReadReq MSHR uncacheable cycles 3684system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 590567503 # number of ReadReq MSHR uncacheable cycles 3685system.l2c.ReadReq_mshr_uncacheable_latency::total 7300556508 # number of ReadReq MSHR uncacheable cycles 3686system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1342704500 # number of overall MSHR uncacheable cycles 3687system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5362205005 # number of overall MSHR uncacheable cycles 3688system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5079500 # number of overall MSHR uncacheable cycles 3689system.l2c.overall_mshr_uncacheable_latency::cpu1.data 590567503 # number of overall MSHR uncacheable cycles 3690system.l2c.overall_mshr_uncacheable_latency::total 7300556508 # number of overall MSHR uncacheable cycles 3691system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3692system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3693system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.272383 # mshr miss rate for UpgradeReq accesses 3694system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.319912 # mshr miss rate for UpgradeReq accesses 3695system.l2c.UpgradeReq_mshr_miss_rate::total 0.293171 # mshr miss rate for UpgradeReq accesses 3696system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.235967 # mshr miss rate for SCUpgradeReq accesses 3697system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.220579 # mshr miss rate for SCUpgradeReq accesses 3698system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.228220 # mshr miss rate for SCUpgradeReq accesses 3699system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.580726 # mshr miss rate for ReadExReq accesses 3700system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.522866 # mshr miss rate for ReadExReq accesses 3701system.l2c.ReadExReq_mshr_miss_rate::total 0.554386 # mshr miss rate for ReadExReq accesses 3702system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.176448 # mshr miss rate for ReadSharedReq accesses 3703system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.164351 # mshr miss rate for ReadSharedReq accesses 3704system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.106001 # mshr miss rate for ReadSharedReq accesses 3705system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.174587 # mshr miss rate for ReadSharedReq accesses 3706system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403485 # mshr miss rate for ReadSharedReq accesses 3707system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.336647 # mshr miss rate for ReadSharedReq accesses 3708system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.411978 # mshr miss rate for ReadSharedReq accesses 3709system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.075470 # mshr miss rate for ReadSharedReq accesses 3710system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.179875 # mshr miss rate for ReadSharedReq accesses 3711system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.473222 # mshr miss rate for ReadSharedReq accesses 3712system.l2c.ReadSharedReq_mshr_miss_rate::total 0.228951 # mshr miss rate for ReadSharedReq accesses 3713system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.771353 # mshr miss rate for InvalidateReq accesses 3714system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.508973 # mshr miss rate for InvalidateReq accesses 3715system.l2c.InvalidateReq_mshr_miss_rate::total 0.692752 # mshr miss rate for InvalidateReq accesses 3716system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.176448 # mshr miss rate for demand accesses 3717system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.164351 # mshr miss rate for demand accesses 3718system.l2c.demand_mshr_miss_rate::cpu0.inst 0.106001 # mshr miss rate for demand accesses 3719system.l2c.demand_mshr_miss_rate::cpu0.data 0.236620 # mshr miss rate for demand accesses 3720system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403485 # mshr miss rate for demand accesses 3721system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.336647 # mshr miss rate for demand accesses 3722system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.411978 # mshr miss rate for demand accesses 3723system.l2c.demand_mshr_miss_rate::cpu1.inst 0.075470 # mshr miss rate for demand accesses 3724system.l2c.demand_mshr_miss_rate::cpu1.data 0.227147 # mshr miss rate for demand accesses 3725system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.473222 # mshr miss rate for demand accesses 3726system.l2c.demand_mshr_miss_rate::total 0.249147 # mshr miss rate for demand accesses 3727system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.176448 # mshr miss rate for overall accesses 3728system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.164351 # mshr miss rate for overall accesses 3729system.l2c.overall_mshr_miss_rate::cpu0.inst 0.106001 # mshr miss rate for overall accesses 3730system.l2c.overall_mshr_miss_rate::cpu0.data 0.236620 # mshr miss rate for overall accesses 3731system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403485 # mshr miss rate for overall accesses 3732system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.336647 # mshr miss rate for overall accesses 3733system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.411978 # mshr miss rate for overall accesses 3734system.l2c.overall_mshr_miss_rate::cpu1.inst 0.075470 # mshr miss rate for overall accesses 3735system.l2c.overall_mshr_miss_rate::cpu1.data 0.227147 # mshr miss rate for overall accesses 3736system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.473222 # mshr miss rate for overall accesses 3737system.l2c.overall_mshr_miss_rate::total 0.249147 # mshr miss rate for overall accesses 3738system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21800.630729 # average UpgradeReq mshr miss latency 3739system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21481.090535 # average UpgradeReq mshr miss latency 3740system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21648.125910 # average UpgradeReq mshr miss latency 3741system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24728.644566 # average SCUpgradeReq mshr miss latency 3742system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24529.095872 # average SCUpgradeReq mshr miss latency 3743system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24631.541369 # average SCUpgradeReq mshr miss latency 3744system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80776.871426 # average ReadExReq mshr miss latency 3745system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 80418.080175 # average ReadExReq mshr miss latency 3746system.l2c.ReadExReq_avg_mshr_miss_latency::total 80622.825503 # average ReadExReq mshr miss latency 3747system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 85612.682609 # average ReadSharedReq mshr miss latency 3748system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 83498.902305 # average ReadSharedReq mshr miss latency 3749system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 77339.847556 # average ReadSharedReq mshr miss latency 3750system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 84367.373235 # average ReadSharedReq mshr miss latency 3751system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130476.040469 # average ReadSharedReq mshr miss latency 3752system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82095.111146 # average ReadSharedReq mshr miss latency 3753system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79805.781271 # average ReadSharedReq mshr miss latency 3754system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 78119.746029 # average ReadSharedReq mshr miss latency 3755system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 86410.878491 # average ReadSharedReq mshr miss latency 3756system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 127706.883719 # average ReadSharedReq mshr miss latency 3757system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 109127.534756 # average ReadSharedReq mshr miss latency 3758system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 25238.478491 # average InvalidateReq mshr miss latency 3759system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20854.531182 # average InvalidateReq mshr miss latency 3760system.l2c.InvalidateReq_avg_mshr_miss_latency::total 24273.578522 # average InvalidateReq mshr miss latency 3761system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 85612.682609 # average overall mshr miss latency 3762system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 83498.902305 # average overall mshr miss latency 3763system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 77339.847556 # average overall mshr miss latency 3764system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83021.439189 # average overall mshr miss latency 3765system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130476.040469 # average overall mshr miss latency 3766system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82095.111146 # average overall mshr miss latency 3767system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79805.781271 # average overall mshr miss latency 3768system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 78119.746029 # average overall mshr miss latency 3769system.l2c.demand_avg_mshr_miss_latency::cpu1.data 84509.674525 # average overall mshr miss latency 3770system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 127706.883719 # average overall mshr miss latency 3771system.l2c.demand_avg_mshr_miss_latency::total 105191.364969 # average overall mshr miss latency 3772system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 85612.682609 # average overall mshr miss latency 3773system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 83498.902305 # average overall mshr miss latency 3774system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 77339.847556 # average overall mshr miss latency 3775system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83021.439189 # average overall mshr miss latency 3776system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130476.040469 # average overall mshr miss latency 3777system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82095.111146 # average overall mshr miss latency 3778system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79805.781271 # average overall mshr miss latency 3779system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 78119.746029 # average overall mshr miss latency 3780system.l2c.overall_avg_mshr_miss_latency::cpu1.data 84509.674525 # average overall mshr miss latency 3781system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 127706.883719 # average overall mshr miss latency 3782system.l2c.overall_avg_mshr_miss_latency::total 105191.364969 # average overall mshr miss latency 3783system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average ReadReq mshr uncacheable latency 3784system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164853.967627 # average ReadReq mshr uncacheable latency 3785system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75813.432836 # average ReadReq mshr uncacheable latency 3786system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 96561.069817 # average ReadReq mshr uncacheable latency 3787system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 121669.858307 # average ReadReq mshr uncacheable latency 3788system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average overall mshr uncacheable latency 3789system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82650.590416 # average overall mshr uncacheable latency 3790system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 75813.432836 # average overall mshr uncacheable latency 3791system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 48017.521994 # average overall mshr uncacheable latency 3792system.l2c.overall_avg_mshr_uncacheable_latency::total 74089.494383 # average overall mshr uncacheable latency 3793system.membus.snoop_filter.tot_requests 3952559 # Total number of requests made to the snoop filter. 3794system.membus.snoop_filter.hit_single_requests 2414080 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3795system.membus.snoop_filter.hit_multi_requests 2931 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3796system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3797system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3798system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3799system.membus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3800system.membus.trans_dist::ReadReq 60003 # Transaction distribution 3801system.membus.trans_dist::ReadResp 904829 # Transaction distribution 3802system.membus.trans_dist::WriteReq 38534 # Transaction distribution 3803system.membus.trans_dist::WriteResp 38534 # Transaction distribution 3804system.membus.trans_dist::WritebackDirty 1242017 # Transaction distribution 3805system.membus.trans_dist::CleanEvict 238236 # Transaction distribution 3806system.membus.trans_dist::UpgradeReq 446737 # Transaction distribution 3807system.membus.trans_dist::SCUpgradeReq 299659 # Transaction distribution 3808system.membus.trans_dist::UpgradeResp 23 # Transaction distribution 3809system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 3810system.membus.trans_dist::ReadExReq 144708 # Transaction distribution 3811system.membus.trans_dist::ReadExResp 128413 # Transaction distribution 3812system.membus.trans_dist::ReadSharedReq 844826 # Transaction distribution 3813system.membus.trans_dist::InvalidateReq 684897 # Transaction distribution 3814system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122672 # Packet count per connected master and slave (bytes) 3815system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) 3816system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26462 # Packet count per connected master and slave (bytes) 3817system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4681290 # Packet count per connected master and slave (bytes) 3818system.membus.pkt_count_system.l2c.mem_side::total 4830500 # Packet count per connected master and slave (bytes) 3819system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238195 # Packet count per connected master and slave (bytes) 3820system.membus.pkt_count_system.iocache.mem_side::total 238195 # Packet count per connected master and slave (bytes) 3821system.membus.pkt_count::total 5068695 # Packet count per connected master and slave (bytes) 3822system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155802 # Cumulative packet size per connected master and slave (bytes) 3823system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) 3824system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52924 # Cumulative packet size per connected master and slave (bytes) 3825system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 134692416 # Cumulative packet size per connected master and slave (bytes) 3826system.membus.pkt_size_system.l2c.mem_side::total 134901698 # Cumulative packet size per connected master and slave (bytes) 3827system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7273344 # Cumulative packet size per connected master and slave (bytes) 3828system.membus.pkt_size_system.iocache.mem_side::total 7273344 # Cumulative packet size per connected master and slave (bytes) 3829system.membus.pkt_size::total 142175042 # Cumulative packet size per connected master and slave (bytes) 3830system.membus.snoops 606585 # Total snoops (count) 3831system.membus.snoop_fanout::samples 2519367 # Request fanout histogram 3832system.membus.snoop_fanout::mean 0.015113 # Request fanout histogram 3833system.membus.snoop_fanout::stdev 0.122002 # Request fanout histogram 3834system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3835system.membus.snoop_fanout::0 2481292 98.49% 98.49% # Request fanout histogram 3836system.membus.snoop_fanout::1 38075 1.51% 100.00% # Request fanout histogram 3837system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3838system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3839system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3840system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3841system.membus.snoop_fanout::total 2519367 # Request fanout histogram 3842system.membus.reqLayer0.occupancy 98170994 # Layer occupancy (ticks) 3843system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3844system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks) 3845system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3846system.membus.reqLayer2.occupancy 22248500 # Layer occupancy (ticks) 3847system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3848system.membus.reqLayer5.occupancy 8723892621 # Layer occupancy (ticks) 3849system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3850system.membus.respLayer2.occupancy 5223815230 # Layer occupancy (ticks) 3851system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3852system.membus.respLayer3.occupancy 45514707 # Layer occupancy (ticks) 3853system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3854system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3855system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3856system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3857system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3858system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3859system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3860system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3861system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3862system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3863system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3864system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3865system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3866system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3867system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3868system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3869system.realview.ethernet.txBytes 966 # Bytes Transmitted 3870system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3871system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3872system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3873system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3874system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3875system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3876system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3877system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3878system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3879system.realview.ethernet.totPackets 3 # Total Packets 3880system.realview.ethernet.totBytes 966 # Total Bytes 3881system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3882system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3883system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3884system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3885system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3886system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3887system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3888system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3889system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3890system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3891system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3892system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3893system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3894system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3895system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3896system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3897system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3898system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3899system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3900system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3901system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3902system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3903system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3904system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3905system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3906system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3907system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3908system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3909system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3910system.realview.ethernet.droppedPackets 0 # number of packets dropped 3911system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3912system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3913system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3914system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3915system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3916system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3917system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3918system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3919system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3920system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3921system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3922system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3923system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3924system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3925system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3926system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3927system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3928system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3929system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3930system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3931system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3932system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3933system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3934system.toL2Bus.snoop_filter.tot_requests 11842018 # Total number of requests made to the snoop filter. 3935system.toL2Bus.snoop_filter.hit_single_requests 6441759 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3936system.toL2Bus.snoop_filter.hit_multi_requests 1913591 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3937system.toL2Bus.snoop_filter.tot_snoops 133722 # Total number of snoops made to the snoop filter. 3938system.toL2Bus.snoop_filter.hit_single_snoops 121814 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3939system.toL2Bus.snoop_filter.hit_multi_snoops 11908 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3940system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3941system.toL2Bus.trans_dist::ReadReq 60005 # Transaction distribution 3942system.toL2Bus.trans_dist::ReadResp 4492996 # Transaction distribution 3943system.toL2Bus.trans_dist::WriteReq 38534 # Transaction distribution 3944system.toL2Bus.trans_dist::WriteResp 38534 # Transaction distribution 3945system.toL2Bus.trans_dist::WritebackDirty 3934886 # Transaction distribution 3946system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution 3947system.toL2Bus.trans_dist::CleanEvict 2625367 # Transaction distribution 3948system.toL2Bus.trans_dist::UpgradeReq 741215 # Transaction distribution 3949system.toL2Bus.trans_dist::SCUpgradeReq 380628 # Transaction distribution 3950system.toL2Bus.trans_dist::UpgradeResp 1121842 # Transaction distribution 3951system.toL2Bus.trans_dist::SCUpgradeFailReq 140 # Transaction distribution 3952system.toL2Bus.trans_dist::UpgradeFailResp 140 # Transaction distribution 3953system.toL2Bus.trans_dist::ReadExReq 295903 # Transaction distribution 3954system.toL2Bus.trans_dist::ReadExResp 295903 # Transaction distribution 3955system.toL2Bus.trans_dist::ReadSharedReq 4433512 # Transaction distribution 3956system.toL2Bus.trans_dist::InvalidateReq 874748 # Transaction distribution 3957system.toL2Bus.trans_dist::InvalidateResp 839647 # Transaction distribution 3958system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9358904 # Packet count per connected master and slave (bytes) 3959system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7932274 # Packet count per connected master and slave (bytes) 3960system.toL2Bus.pkt_count::total 17291178 # Packet count per connected master and slave (bytes) 3961system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 230390413 # Cumulative packet size per connected master and slave (bytes) 3962system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 198586357 # Cumulative packet size per connected master and slave (bytes) 3963system.toL2Bus.pkt_size::total 428976770 # Cumulative packet size per connected master and slave (bytes) 3964system.toL2Bus.snoops 2884507 # Total snoops (count) 3965system.toL2Bus.snoop_fanout::samples 8248846 # Request fanout histogram 3966system.toL2Bus.snoop_fanout::mean 0.358423 # Request fanout histogram 3967system.toL2Bus.snoop_fanout::stdev 0.482538 # Request fanout histogram 3968system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3969system.toL2Bus.snoop_fanout::0 5304178 64.30% 64.30% # Request fanout histogram 3970system.toL2Bus.snoop_fanout::1 2932760 35.55% 99.86% # Request fanout histogram 3971system.toL2Bus.snoop_fanout::2 11908 0.14% 100.00% # Request fanout histogram 3972system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3973system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3974system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3975system.toL2Bus.snoop_fanout::total 8248846 # Request fanout histogram 3976system.toL2Bus.reqLayer0.occupancy 9216694138 # Layer occupancy (ticks) 3977system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3978system.toL2Bus.snoopLayer0.occupancy 2593163 # Layer occupancy (ticks) 3979system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3980system.toL2Bus.respLayer0.occupancy 4234968582 # Layer occupancy (ticks) 3981system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3982system.toL2Bus.respLayer1.occupancy 3934186551 # Layer occupancy (ticks) 3983system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3984system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3985system.cpu0.kern.inst.quiesce 13240 # number of quiesce instructions executed 3986system.cpu1.kern.inst.arm 0 # number of arm instructions executed 3987system.cpu1.kern.inst.quiesce 5626 # number of quiesce instructions executed 3988 3989---------- End Simulation Statistics ----------	1909system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1910system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1911system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1912system.cpu1.itb.perms_faults 205105 # Number of TLB faults due to permissions restrictions 1913system.cpu1.itb.read_accesses 0 # DTB read accesses 1914system.cpu1.itb.write_accesses 0 # DTB write accesses 1915system.cpu1.itb.inst_accesses 200266108 # ITB inst accesses 1916system.cpu1.itb.hits 200179962 # DTB hits 1917system.cpu1.itb.misses 86146 # DTB misses 1918system.cpu1.itb.accesses 200266108 # DTB accesses 1919system.cpu1.numPwrStateTransitions 11252 # Number of power state transitions 1920system.cpu1.pwrStateClkGateDist::samples 5626 # Distribution of time spent in the clock gated state 1921system.cpu1.pwrStateClkGateDist::mean 8361647359.894774 # Distribution of time spent in the clock gated state 1922system.cpu1.pwrStateClkGateDist::stdev 196584250353.907135 # Distribution of time spent in the clock gated state 1923system.cpu1.pwrStateClkGateDist::underflows 4008 71.24% 71.24% # Distribution of time spent in the clock gated state 1924system.cpu1.pwrStateClkGateDist::1000-5e+10 1597 28.39% 99.63% # Distribution of time spent in the clock gated state 1925system.cpu1.pwrStateClkGateDist::5e+10-1e+11 6 0.11% 99.73% # Distribution of time spent in the clock gated state 1926system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state 1927system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.77% # Distribution of time spent in the clock gated state 1928system.cpu1.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.79% # Distribution of time spent in the clock gated state 1929system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 1 0.02% 99.80% # Distribution of time spent in the clock gated state 1930system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.82% # Distribution of time spent in the clock gated state 1931system.cpu1.pwrStateClkGateDist::overflows 10 0.18% 100.00% # Distribution of time spent in the clock gated state 1932system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 1933system.cpu1.pwrStateClkGateDist::max_value 11813562713000 # Distribution of time spent in the clock gated state 1934system.cpu1.pwrStateClkGateDist::total 5626 # Distribution of time spent in the clock gated state 1935system.cpu1.pwrStateResidencyTicks::ON 341687116232 # Cumulative time (in ticks) in various power states 1936system.cpu1.pwrStateResidencyTicks::CLK_GATED 47042628046768 # Cumulative time (in ticks) in various power states 1937system.cpu1.numCycles 683375860 # number of cpu cycles simulated 1938system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1939system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1940system.cpu1.fetch.icacheStallCycles 83886783 # Number of cycles fetch is stalled on an Icache miss 1941system.cpu1.fetch.Insts 563469851 # Number of instructions fetch has processed 1942system.cpu1.fetch.Branches 127244460 # Number of branches that fetch encountered 1943system.cpu1.fetch.predictedBranches 75441097 # Number of branches that fetch has predicted taken 1944system.cpu1.fetch.Cycles 564344995 # Number of cycles fetch has run and was not squashing or blocked 1945system.cpu1.fetch.SquashCycles 13807906 # Number of cycles fetch has spent squashing 1946system.cpu1.fetch.TlbCycles 2007349 # Number of cycles fetch has spent waiting for tlb 1947system.cpu1.fetch.MiscStallCycles 258832 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1948system.cpu1.fetch.PendingTrapStallCycles 5872913 # Number of stall cycles due to pending traps 1949system.cpu1.fetch.PendingQuiesceStallCycles 777107 # Number of stall cycles due to pending quiesce instructions 1950system.cpu1.fetch.IcacheWaitRetryStallCycles 768148 # Number of stall cycles due to full MSHR 1951system.cpu1.fetch.CacheLines 199953853 # Number of cache lines fetched 1952system.cpu1.fetch.IcacheSquashes 1622392 # Number of outstanding Icache misses that were squashed 1953system.cpu1.fetch.ItlbSquashes 27919 # Number of outstanding ITLB misses that were squashed 1954system.cpu1.fetch.rateDist::samples 664820080 # Number of instructions fetched each cycle (Total) 1955system.cpu1.fetch.rateDist::mean 0.994147 # Number of instructions fetched each cycle (Total) 1956system.cpu1.fetch.rateDist::stdev 1.223667 # Number of instructions fetched each cycle (Total) 1957system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1958system.cpu1.fetch.rateDist::0 348468390 52.42% 52.42% # Number of instructions fetched each cycle (Total) 1959system.cpu1.fetch.rateDist::1 123001690 18.50% 70.92% # Number of instructions fetched each cycle (Total) 1960system.cpu1.fetch.rateDist::2 42123132 6.34% 77.25% # Number of instructions fetched each cycle (Total) 1961system.cpu1.fetch.rateDist::3 151226868 22.75% 100.00% # Number of instructions fetched each cycle (Total) 1962system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1963system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1964system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 1965system.cpu1.fetch.rateDist::total 664820080 # Number of instructions fetched each cycle (Total) 1966system.cpu1.fetch.branchRate 0.186200 # Number of branch fetches per cycle 1967system.cpu1.fetch.rate 0.824539 # Number of inst fetches per cycle 1968system.cpu1.decode.IdleCycles 100313259 # Number of cycles decode is idle 1969system.cpu1.decode.BlockedCycles 315334519 # Number of cycles decode is blocked 1970system.cpu1.decode.RunCycles 208757120 # Number of cycles decode is running 1971system.cpu1.decode.UnblockCycles 35486026 # Number of cycles decode is unblocking 1972system.cpu1.decode.SquashCycles 4929156 # Number of cycles decode is squashing 1973system.cpu1.decode.BranchResolved 17976704 # Number of times decode resolved a branch 1974system.cpu1.decode.BranchMispred 2012194 # Number of times decode detected a branch misprediction 1975system.cpu1.decode.DecodedInsts 582722672 # Number of instructions handled by decode 1976system.cpu1.decode.SquashedInsts 22029645 # Number of squashed instructions handled by decode 1977system.cpu1.rename.SquashCycles 4929156 # Number of cycles rename is squashing 1978system.cpu1.rename.IdleCycles 133756265 # Number of cycles rename is idle 1979system.cpu1.rename.BlockCycles 43242401 # Number of cycles rename is blocking 1980system.cpu1.rename.serializeStallCycles 214462360 # count of cycles rename stalled for serializing inst 1981system.cpu1.rename.RunCycles 210347945 # Number of cycles rename is running 1982system.cpu1.rename.UnblockCycles 58081953 # Number of cycles rename is unblocking 1983system.cpu1.rename.RenamedInsts 566482483 # Number of instructions processed by rename 1984system.cpu1.rename.SquashedInsts 5736321 # Number of squashed instructions processed by rename 1985system.cpu1.rename.ROBFullEvents 9739688 # Number of times rename has blocked due to ROB full 1986system.cpu1.rename.IQFullEvents 342221 # Number of times rename has blocked due to IQ full 1987system.cpu1.rename.LQFullEvents 843279 # Number of times rename has blocked due to LQ full 1988system.cpu1.rename.SQFullEvents 24527700 # Number of times rename has blocked due to SQ full 1989system.cpu1.rename.FullRegisterEvents 11906 # Number of times there has been no free registers 1990system.cpu1.rename.RenamedOperands 538415916 # Number of destination operands rename has renamed 1991system.cpu1.rename.RenameLookups 871757488 # Number of register rename lookups that rename has made 1992system.cpu1.rename.int_rename_lookups 668460678 # Number of integer rename lookups 1993system.cpu1.rename.fp_rename_lookups 644937 # Number of floating rename lookups 1994system.cpu1.rename.CommittedMaps 483561743 # Number of HB maps that are committed 1995system.cpu1.rename.UndoneMaps 54854172 # Number of HB maps that are undone due to squashing 1996system.cpu1.rename.serializingInsts 15093428 # count of serializing insts renamed 1997system.cpu1.rename.tempSerializingInsts 13190698 # count of temporary serializing insts renamed 1998system.cpu1.rename.skidInsts 71341154 # count of insts added to the skid buffer 1999system.cpu1.memDep0.insertedLoads 94469141 # Number of loads inserted to the mem dependence unit. 2000system.cpu1.memDep0.insertedStores 78816060 # Number of stores inserted to the mem dependence unit. 2001system.cpu1.memDep0.conflictingLoads 9208116 # Number of conflicting loads. 2002system.cpu1.memDep0.conflictingStores 7878049 # Number of conflicting stores. 2003system.cpu1.iq.iqInstsAdded 544809829 # Number of instructions added to the IQ (excludes non-spec) 2004system.cpu1.iq.iqNonSpecInstsAdded 15364466 # Number of non-speculative instructions added to the IQ 2005system.cpu1.iq.iqInstsIssued 549398452 # Number of instructions issued 2006system.cpu1.iq.iqSquashedInstsIssued 2550658 # Number of squashed instructions issued 2007system.cpu1.iq.iqSquashedInstsExamined 51789954 # Number of squashed instructions iterated over during squash; mainly for profiling 2008system.cpu1.iq.iqSquashedOperandsExamined 33366441 # Number of squashed operands that are examined and possibly removed from graph 2009system.cpu1.iq.iqSquashedNonSpecRemoved 282362 # Number of squashed non-spec instructions that were removed 2010system.cpu1.iq.issued_per_cycle::samples 664820080 # Number of insts issued each cycle 2011system.cpu1.iq.issued_per_cycle::mean 0.826387 # Number of insts issued each cycle 2012system.cpu1.iq.issued_per_cycle::stdev 1.065764 # Number of insts issued each cycle 2013system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 2014system.cpu1.iq.issued_per_cycle::0 363096071 54.62% 54.62% # Number of insts issued each cycle 2015system.cpu1.iq.issued_per_cycle::1 129026402 19.41% 74.02% # Number of insts issued each cycle 2016system.cpu1.iq.issued_per_cycle::2 104942160 15.79% 89.81% # Number of insts issued each cycle 2017system.cpu1.iq.issued_per_cycle::3 60539163 9.11% 98.91% # Number of insts issued each cycle 2018system.cpu1.iq.issued_per_cycle::4 7211179 1.08% 100.00% # Number of insts issued each cycle 2019system.cpu1.iq.issued_per_cycle::5 5105 0.00% 100.00% # Number of insts issued each cycle 2020system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 2021system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 2022system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 2023system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2024system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2025system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 2026system.cpu1.iq.issued_per_cycle::total 664820080 # Number of insts issued each cycle 2027system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 2028system.cpu1.iq.fu_full::IntAlu 54936992 44.00% 44.00% # attempts to use FU when none available 2029system.cpu1.iq.fu_full::IntMult 69872 0.06% 44.05% # attempts to use FU when none available 2030system.cpu1.iq.fu_full::IntDiv 6570 0.01% 44.06% # attempts to use FU when none available 2031system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.06% # attempts to use FU when none available 2032system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.06% # attempts to use FU when none available 2033system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.06% # attempts to use FU when none available 2034system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.06% # attempts to use FU when none available 2035system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.06% # attempts to use FU when none available 2036system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.06% # attempts to use FU when none available 2037system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.06% # attempts to use FU when none available 2038system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.06% # attempts to use FU when none available 2039system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.06% # attempts to use FU when none available 2040system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.06% # attempts to use FU when none available 2041system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.06% # attempts to use FU when none available 2042system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.06% # attempts to use FU when none available 2043system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.06% # attempts to use FU when none available 2044system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.06% # attempts to use FU when none available 2045system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.06% # attempts to use FU when none available 2046system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.06% # attempts to use FU when none available 2047system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.06% # attempts to use FU when none available 2048system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.06% # attempts to use FU when none available 2049system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.06% # attempts to use FU when none available 2050system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.06% # attempts to use FU when none available 2051system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.06% # attempts to use FU when none available 2052system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.06% # attempts to use FU when none available 2053system.cpu1.iq.fu_full::SimdFloatMisc 17 0.00% 44.06% # attempts to use FU when none available 2054system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.06% # attempts to use FU when none available 2055system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.06% # attempts to use FU when none available 2056system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.06% # attempts to use FU when none available 2057system.cpu1.iq.fu_full::MemRead 34367116 27.52% 71.58% # attempts to use FU when none available 2058system.cpu1.iq.fu_full::MemWrite 35481157 28.42% 100.00% # attempts to use FU when none available 2059system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2060system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2061system.cpu1.iq.FU_type_0::No_OpClass 56 0.00% 0.00% # Type of FU issued 2062system.cpu1.iq.FU_type_0::IntAlu 373883416 68.05% 68.05% # Type of FU issued 2063system.cpu1.iq.FU_type_0::IntMult 1335155 0.24% 68.30% # Type of FU issued 2064system.cpu1.iq.FU_type_0::IntDiv 74884 0.01% 68.31% # Type of FU issued 2065system.cpu1.iq.FU_type_0::FloatAdd 11 0.00% 68.31% # Type of FU issued 2066system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued 2067system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued 2068system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued 2069system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.31% # Type of FU issued 2070system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.31% # Type of FU issued 2071system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.31% # Type of FU issued 2072system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.31% # Type of FU issued 2073system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.31% # Type of FU issued 2074system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.31% # Type of FU issued 2075system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.31% # Type of FU issued 2076system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.31% # Type of FU issued 2077system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.31% # Type of FU issued 2078system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.31% # Type of FU issued 2079system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.31% # Type of FU issued 2080system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.31% # Type of FU issued 2081system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.31% # Type of FU issued 2082system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.31% # Type of FU issued 2083system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.31% # Type of FU issued 2084system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.31% # Type of FU issued 2085system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.31% # Type of FU issued 2086system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.31% # Type of FU issued 2087system.cpu1.iq.FU_type_0::SimdFloatMisc 48854 0.01% 68.32% # Type of FU issued 2088system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued 2089system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued 2090system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued 2091system.cpu1.iq.FU_type_0::MemRead 97153433 17.68% 86.00% # Type of FU issued 2092system.cpu1.iq.FU_type_0::MemWrite 76902643 14.00% 100.00% # Type of FU issued 2093system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2094system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2095system.cpu1.iq.FU_type_0::total 549398452 # Type of FU issued 2096system.cpu1.iq.rate 0.803948 # Inst issue rate 2097system.cpu1.iq.fu_busy_cnt 124861724 # FU busy when requested 2098system.cpu1.iq.fu_busy_rate 0.227270 # FU busy rate (busy events/executed inst) 2099system.cpu1.iq.int_inst_queue_reads 1889962970 # Number of integer instruction queue reads 2100system.cpu1.iq.int_inst_queue_writes 611689245 # Number of integer instruction queue writes 2101system.cpu1.iq.int_inst_queue_wakeup_accesses 533047508 # Number of integer instruction queue wakeup accesses 2102system.cpu1.iq.fp_inst_queue_reads 1066396 # Number of floating instruction queue reads 2103system.cpu1.iq.fp_inst_queue_writes 424008 # Number of floating instruction queue writes 2104system.cpu1.iq.fp_inst_queue_wakeup_accesses 393622 # Number of floating instruction queue wakeup accesses 2105system.cpu1.iq.int_alu_accesses 673596915 # Number of integer alu accesses 2106system.cpu1.iq.fp_alu_accesses 663205 # Number of floating point alu accesses 2107system.cpu1.iew.lsq.thread0.forwLoads 2524444 # Number of loads that had data forwarded from stores 2108system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2109system.cpu1.iew.lsq.thread0.squashedLoads 12144847 # Number of loads squashed 2110system.cpu1.iew.lsq.thread0.ignoredResponses 16403 # Number of memory responses ignored because the instruction is squashed 2111system.cpu1.iew.lsq.thread0.memOrderViolation 149896 # Number of memory ordering violations 2112system.cpu1.iew.lsq.thread0.squashedStores 5262071 # Number of stores squashed 2113system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2114system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2115system.cpu1.iew.lsq.thread0.rescheduledLoads 2572719 # Number of loads that were rescheduled 2116system.cpu1.iew.lsq.thread0.cacheBlocked 4009144 # Number of times an access to memory failed due to the cache being blocked 2117system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2118system.cpu1.iew.iewSquashCycles 4929156 # Number of cycles IEW is squashing 2119system.cpu1.iew.iewBlockCycles 7182655 # Number of cycles IEW is blocking 2120system.cpu1.iew.iewUnblockCycles 1646879 # Number of cycles IEW is unblocking 2121system.cpu1.iew.iewDispatchedInsts 560304926 # Number of instructions dispatched to IQ 2122system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 2123system.cpu1.iew.iewDispLoadInsts 94469141 # Number of dispatched load instructions 2124system.cpu1.iew.iewDispStoreInsts 78816060 # Number of dispatched store instructions 2125system.cpu1.iew.iewDispNonSpecInsts 12974148 # Number of dispatched non-speculative instructions 2126system.cpu1.iew.iewIQFullEvents 56258 # Number of times the IQ has become full, causing a stall 2127system.cpu1.iew.iewLSQFullEvents 1524659 # Number of times the LSQ has become full, causing a stall 2128system.cpu1.iew.memOrderViolationEvents 149896 # Number of memory order violations 2129system.cpu1.iew.predictedTakenIncorrect 1843431 # Number of branches that were predicted taken incorrectly 2130system.cpu1.iew.predictedNotTakenIncorrect 2924818 # Number of branches that were predicted not taken incorrectly 2131system.cpu1.iew.branchMispredicts 4768249 # Number of branch mispredicts detected at execute 2132system.cpu1.iew.iewExecutedInsts 541845400 # Number of executed instructions 2133system.cpu1.iew.iewExecLoadInsts 94094962 # Number of load instructions executed 2134system.cpu1.iew.iewExecSquashedInsts 6980663 # Number of squashed instructions skipped in execute 2135system.cpu1.iew.exec_swp 0 # number of swp insts executed 2136system.cpu1.iew.exec_nop 130631 # number of nop insts executed 2137system.cpu1.iew.exec_refs 169824676 # number of memory reference insts executed 2138system.cpu1.iew.exec_branches 101510793 # Number of branches executed 2139system.cpu1.iew.exec_stores 75729714 # Number of stores executed 2140system.cpu1.iew.exec_rate 0.792895 # Inst execution rate 2141system.cpu1.iew.wb_sent 534152020 # cumulative count of insts sent to commit 2142system.cpu1.iew.wb_count 533441130 # cumulative count of insts written-back 2143system.cpu1.iew.wb_producers 258912640 # num instructions producing a value 2144system.cpu1.iew.wb_consumers 423656459 # num instructions consuming a value 2145system.cpu1.iew.wb_rate 0.780597 # insts written-back per cycle 2146system.cpu1.iew.wb_fanout 0.611138 # average fanout of values written-back 2147system.cpu1.commit.commitSquashedInsts 45293147 # The number of squashed insts skipped by commit 2148system.cpu1.commit.commitNonSpecStalls 15082103 # The number of times commit has been forced to stall to communicate backwards 2149system.cpu1.commit.branchMispredicts 4436923 # The number of times a branch was mispredicted 2150system.cpu1.commit.committed_per_cycle::samples 656213363 # Number of insts commited each cycle 2151system.cpu1.commit.committed_per_cycle::mean 0.774724 # Number of insts commited each cycle 2152system.cpu1.commit.committed_per_cycle::stdev 1.573400 # Number of insts commited each cycle 2153system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2154system.cpu1.commit.committed_per_cycle::0 432598016 65.92% 65.92% # Number of insts commited each cycle 2155system.cpu1.commit.committed_per_cycle::1 117091486 17.84% 83.77% # Number of insts commited each cycle 2156system.cpu1.commit.committed_per_cycle::2 49126445 7.49% 91.25% # Number of insts commited each cycle 2157system.cpu1.commit.committed_per_cycle::3 16229930 2.47% 93.73% # Number of insts commited each cycle 2158system.cpu1.commit.committed_per_cycle::4 11628277 1.77% 95.50% # Number of insts commited each cycle 2159system.cpu1.commit.committed_per_cycle::5 8033144 1.22% 96.72% # Number of insts commited each cycle 2160system.cpu1.commit.committed_per_cycle::6 5546832 0.85% 97.57% # Number of insts commited each cycle 2161system.cpu1.commit.committed_per_cycle::7 3283510 0.50% 98.07% # Number of insts commited each cycle 2162system.cpu1.commit.committed_per_cycle::8 12675723 1.93% 100.00% # Number of insts commited each cycle 2163system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2164system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2165system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2166system.cpu1.commit.committed_per_cycle::total 656213363 # Number of insts commited each cycle 2167system.cpu1.commit.committedInsts 431870837 # Number of instructions committed 2168system.cpu1.commit.committedOps 508384340 # Number of ops (including micro ops) committed 2169system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 2170system.cpu1.commit.refs 155878283 # Number of memory references committed 2171system.cpu1.commit.loads 82324294 # Number of loads committed 2172system.cpu1.commit.membars 3722309 # Number of memory barriers committed 2173system.cpu1.commit.branches 96290107 # Number of branches committed 2174system.cpu1.commit.fp_insts 384716 # Number of committed floating point instructions. 2175system.cpu1.commit.int_insts 467163355 # Number of committed integer instructions. 2176system.cpu1.commit.function_calls 12903273 # Number of function calls committed. 2177system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 2178system.cpu1.commit.op_class_0::IntAlu 351312000 69.10% 69.10% # Class of committed instruction 2179system.cpu1.commit.op_class_0::IntMult 1092238 0.21% 69.32% # Class of committed instruction 2180system.cpu1.commit.op_class_0::IntDiv 59391 0.01% 69.33% # Class of committed instruction 2181system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction 2182system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction 2183system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction 2184system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction 2185system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction 2186system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction 2187system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction 2188system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction 2189system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction 2190system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction 2191system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction 2192system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction 2193system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction 2194system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction 2195system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction 2196system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction 2197system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction 2198system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction 2199system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction 2200system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction 2201system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction 2202system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction 2203system.cpu1.commit.op_class_0::SimdFloatMisc 42428 0.01% 69.34% # Class of committed instruction 2204system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.34% # Class of committed instruction 2205system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.34% # Class of committed instruction 2206system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.34% # Class of committed instruction 2207system.cpu1.commit.op_class_0::MemRead 82324294 16.19% 85.53% # Class of committed instruction 2208system.cpu1.commit.op_class_0::MemWrite 73553989 14.47% 100.00% # Class of committed instruction 2209system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2210system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2211system.cpu1.commit.op_class_0::total 508384340 # Class of committed instruction 2212system.cpu1.commit.bw_lim_events 12675723 # number cycles where commit BW limit reached 2213system.cpu1.rob.rob_reads 1193390155 # The number of ROB reads 2214system.cpu1.rob.rob_writes 1115923607 # The number of ROB writes 2215system.cpu1.timesIdled 934929 # Number of times that the entire CPU went into an idle state and unscheduled itself 2216system.cpu1.idleCycles 18555780 # Total number of cycles that the CPU has spent unscheduled due to idling 2217system.cpu1.quiesceCycles 94085254498 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2218system.cpu1.committedInsts 431870837 # Number of Instructions Simulated 2219system.cpu1.committedOps 508384340 # Number of Ops (including micro ops) Simulated 2220system.cpu1.cpi 1.582362 # CPI: Cycles Per Instruction 2221system.cpu1.cpi_total 1.582362 # CPI: Total CPI of All Threads 2222system.cpu1.ipc 0.631967 # IPC: Instructions Per Cycle 2223system.cpu1.ipc_total 0.631967 # IPC: Total IPC of All Threads 2224system.cpu1.int_regfile_reads 639570382 # number of integer regfile reads 2225system.cpu1.int_regfile_writes 380109427 # number of integer regfile writes 2226system.cpu1.fp_regfile_reads 631427 # number of floating regfile reads 2227system.cpu1.fp_regfile_writes 338972 # number of floating regfile writes 2228system.cpu1.cc_regfile_reads 115255782 # number of cc regfile reads 2229system.cpu1.cc_regfile_writes 115917819 # number of cc regfile writes 2230system.cpu1.misc_regfile_reads 1185795918 # number of misc regfile reads 2231system.cpu1.misc_regfile_writes 15045931 # number of misc regfile writes 2232system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 2233system.cpu1.dcache.tags.replacements 5420466 # number of replacements 2234system.cpu1.dcache.tags.tagsinuse 437.277482 # Cycle average of tags in use 2235system.cpu1.dcache.tags.total_refs 144971712 # Total number of references to valid blocks. 2236system.cpu1.dcache.tags.sampled_refs 5420977 # Sample count of references to valid blocks. 2237system.cpu1.dcache.tags.avg_refs 26.742728 # Average number of references to valid blocks. 2238system.cpu1.dcache.tags.warmup_cycle 8477404255000 # Cycle when the warmup percentage was hit. 2239system.cpu1.dcache.tags.occ_blocks::cpu1.data 437.277482 # Average occupied blocks per requestor 2240system.cpu1.dcache.tags.occ_percent::cpu1.data 0.854058 # Average percentage of cache occupancy 2241system.cpu1.dcache.tags.occ_percent::total 0.854058 # Average percentage of cache occupancy 2242system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 2243system.cpu1.dcache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id 2244system.cpu1.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id 2245system.cpu1.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 2246system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 2247system.cpu1.dcache.tags.tag_accesses 323922794 # Number of tag accesses 2248system.cpu1.dcache.tags.data_accesses 323922794 # Number of data accesses 2249system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 2250system.cpu1.dcache.ReadReq_hits::cpu1.data 76466425 # number of ReadReq hits 2251system.cpu1.dcache.ReadReq_hits::total 76466425 # number of ReadReq hits 2252system.cpu1.dcache.WriteReq_hits::cpu1.data 64110613 # number of WriteReq hits 2253system.cpu1.dcache.WriteReq_hits::total 64110613 # number of WriteReq hits 2254system.cpu1.dcache.SoftPFReq_hits::cpu1.data 170428 # number of SoftPFReq hits 2255system.cpu1.dcache.SoftPFReq_hits::total 170428 # number of SoftPFReq hits 2256system.cpu1.dcache.WriteLineReq_hits::cpu1.data 51164 # number of WriteLineReq hits 2257system.cpu1.dcache.WriteLineReq_hits::total 51164 # number of WriteLineReq hits 2258system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1700918 # number of LoadLockedReq hits 2259system.cpu1.dcache.LoadLockedReq_hits::total 1700918 # number of LoadLockedReq hits 2260system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1741756 # number of StoreCondReq hits 2261system.cpu1.dcache.StoreCondReq_hits::total 1741756 # number of StoreCondReq hits 2262system.cpu1.dcache.demand_hits::cpu1.data 140628202 # number of demand (read+write) hits 2263system.cpu1.dcache.demand_hits::total 140628202 # number of demand (read+write) hits 2264system.cpu1.dcache.overall_hits::cpu1.data 140798630 # number of overall hits 2265system.cpu1.dcache.overall_hits::total 140798630 # number of overall hits 2266system.cpu1.dcache.ReadReq_misses::cpu1.data 6372316 # number of ReadReq misses 2267system.cpu1.dcache.ReadReq_misses::total 6372316 # number of ReadReq misses 2268system.cpu1.dcache.WriteReq_misses::cpu1.data 7014697 # number of WriteReq misses 2269system.cpu1.dcache.WriteReq_misses::total 7014697 # number of WriteReq misses 2270system.cpu1.dcache.SoftPFReq_misses::cpu1.data 658076 # number of SoftPFReq misses 2271system.cpu1.dcache.SoftPFReq_misses::total 658076 # number of SoftPFReq misses 2272system.cpu1.dcache.WriteLineReq_misses::cpu1.data 445973 # number of WriteLineReq misses 2273system.cpu1.dcache.WriteLineReq_misses::total 445973 # number of WriteLineReq misses 2274system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 278553 # number of LoadLockedReq misses 2275system.cpu1.dcache.LoadLockedReq_misses::total 278553 # number of LoadLockedReq misses 2276system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193453 # number of StoreCondReq misses 2277system.cpu1.dcache.StoreCondReq_misses::total 193453 # number of StoreCondReq misses 2278system.cpu1.dcache.demand_misses::cpu1.data 13832986 # number of demand (read+write) misses 2279system.cpu1.dcache.demand_misses::total 13832986 # number of demand (read+write) misses 2280system.cpu1.dcache.overall_misses::cpu1.data 14491062 # number of overall misses 2281system.cpu1.dcache.overall_misses::total 14491062 # number of overall misses 2282system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 93736923500 # number of ReadReq miss cycles 2283system.cpu1.dcache.ReadReq_miss_latency::total 93736923500 # number of ReadReq miss cycles 2284system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 131113304741 # number of WriteReq miss cycles 2285system.cpu1.dcache.WriteReq_miss_latency::total 131113304741 # number of WriteReq miss cycles 2286system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11858807099 # number of WriteLineReq miss cycles 2287system.cpu1.dcache.WriteLineReq_miss_latency::total 11858807099 # number of WriteLineReq miss cycles 2288system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4107251000 # number of LoadLockedReq miss cycles 2289system.cpu1.dcache.LoadLockedReq_miss_latency::total 4107251000 # number of LoadLockedReq miss cycles 2290system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4806521000 # number of StoreCondReq miss cycles 2291system.cpu1.dcache.StoreCondReq_miss_latency::total 4806521000 # number of StoreCondReq miss cycles 2292system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3714500 # number of StoreCondFailReq miss cycles 2293system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3714500 # number of StoreCondFailReq miss cycles 2294system.cpu1.dcache.demand_miss_latency::cpu1.data 236709035340 # number of demand (read+write) miss cycles 2295system.cpu1.dcache.demand_miss_latency::total 236709035340 # number of demand (read+write) miss cycles 2296system.cpu1.dcache.overall_miss_latency::cpu1.data 236709035340 # number of overall miss cycles 2297system.cpu1.dcache.overall_miss_latency::total 236709035340 # number of overall miss cycles 2298system.cpu1.dcache.ReadReq_accesses::cpu1.data 82838741 # number of ReadReq accesses(hits+misses) 2299system.cpu1.dcache.ReadReq_accesses::total 82838741 # number of ReadReq accesses(hits+misses) 2300system.cpu1.dcache.WriteReq_accesses::cpu1.data 71125310 # number of WriteReq accesses(hits+misses) 2301system.cpu1.dcache.WriteReq_accesses::total 71125310 # number of WriteReq accesses(hits+misses) 2302system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 828504 # number of SoftPFReq accesses(hits+misses) 2303system.cpu1.dcache.SoftPFReq_accesses::total 828504 # number of SoftPFReq accesses(hits+misses) 2304system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 497137 # number of WriteLineReq accesses(hits+misses) 2305system.cpu1.dcache.WriteLineReq_accesses::total 497137 # number of WriteLineReq accesses(hits+misses) 2306system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1979471 # number of LoadLockedReq accesses(hits+misses) 2307system.cpu1.dcache.LoadLockedReq_accesses::total 1979471 # number of LoadLockedReq accesses(hits+misses) 2308system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1935209 # number of StoreCondReq accesses(hits+misses) 2309system.cpu1.dcache.StoreCondReq_accesses::total 1935209 # number of StoreCondReq accesses(hits+misses) 2310system.cpu1.dcache.demand_accesses::cpu1.data 154461188 # number of demand (read+write) accesses 2311system.cpu1.dcache.demand_accesses::total 154461188 # number of demand (read+write) accesses 2312system.cpu1.dcache.overall_accesses::cpu1.data 155289692 # number of overall (read+write) accesses 2313system.cpu1.dcache.overall_accesses::total 155289692 # number of overall (read+write) accesses 2314system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.076924 # miss rate for ReadReq accesses 2315system.cpu1.dcache.ReadReq_miss_rate::total 0.076924 # miss rate for ReadReq accesses 2316system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.098624 # miss rate for WriteReq accesses 2317system.cpu1.dcache.WriteReq_miss_rate::total 0.098624 # miss rate for WriteReq accesses 2318system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.794294 # miss rate for SoftPFReq accesses 2319system.cpu1.dcache.SoftPFReq_miss_rate::total 0.794294 # miss rate for SoftPFReq accesses 2320system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.897083 # miss rate for WriteLineReq accesses 2321system.cpu1.dcache.WriteLineReq_miss_rate::total 0.897083 # miss rate for WriteLineReq accesses 2322system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.140721 # miss rate for LoadLockedReq accesses 2323system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.140721 # miss rate for LoadLockedReq accesses 2324system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099965 # miss rate for StoreCondReq accesses 2325system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099965 # miss rate for StoreCondReq accesses 2326system.cpu1.dcache.demand_miss_rate::cpu1.data 0.089556 # miss rate for demand accesses 2327system.cpu1.dcache.demand_miss_rate::total 0.089556 # miss rate for demand accesses 2328system.cpu1.dcache.overall_miss_rate::cpu1.data 0.093316 # miss rate for overall accesses 2329system.cpu1.dcache.overall_miss_rate::total 0.093316 # miss rate for overall accesses 2330system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14710.024346 # average ReadReq miss latency 2331system.cpu1.dcache.ReadReq_avg_miss_latency::total 14710.024346 # average ReadReq miss latency 2332system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18691.228536 # average WriteReq miss latency 2333system.cpu1.dcache.WriteReq_avg_miss_latency::total 18691.228536 # average WriteReq miss latency 2334system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 26590.863346 # average WriteLineReq miss latency 2335system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 26590.863346 # average WriteLineReq miss latency 2336system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14744.953384 # average LoadLockedReq miss latency 2337system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14744.953384 # average LoadLockedReq miss latency 2338system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24845.936739 # average StoreCondReq miss latency 2339system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24845.936739 # average StoreCondReq miss latency 2340system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2341system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2342system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17111.926184 # average overall miss latency 2343system.cpu1.dcache.demand_avg_miss_latency::total 17111.926184 # average overall miss latency 2344system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16334.830072 # average overall miss latency 2345system.cpu1.dcache.overall_avg_miss_latency::total 16334.830072 # average overall miss latency 2346system.cpu1.dcache.blocked_cycles::no_mshrs 3137293 # number of cycles access was blocked 2347system.cpu1.dcache.blocked_cycles::no_targets 21285332 # number of cycles access was blocked 2348system.cpu1.dcache.blocked::no_mshrs 376632 # number of cycles access was blocked 2349system.cpu1.dcache.blocked::no_targets 706469 # number of cycles access was blocked 2350system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.329863 # average number of cycles each access was blocked 2351system.cpu1.dcache.avg_blocked_cycles::no_targets 30.129180 # average number of cycles each access was blocked 2352system.cpu1.dcache.writebacks::writebacks 5420571 # number of writebacks 2353system.cpu1.dcache.writebacks::total 5420571 # number of writebacks 2354system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3225514 # number of ReadReq MSHR hits 2355system.cpu1.dcache.ReadReq_mshr_hits::total 3225514 # number of ReadReq MSHR hits 2356system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5658563 # number of WriteReq MSHR hits 2357system.cpu1.dcache.WriteReq_mshr_hits::total 5658563 # number of WriteReq MSHR hits 2358system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3397 # number of WriteLineReq MSHR hits 2359system.cpu1.dcache.WriteLineReq_mshr_hits::total 3397 # number of WriteLineReq MSHR hits 2360system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 142581 # number of LoadLockedReq MSHR hits 2361system.cpu1.dcache.LoadLockedReq_mshr_hits::total 142581 # number of LoadLockedReq MSHR hits 2362system.cpu1.dcache.demand_mshr_hits::cpu1.data 8887474 # number of demand (read+write) MSHR hits 2363system.cpu1.dcache.demand_mshr_hits::total 8887474 # number of demand (read+write) MSHR hits 2364system.cpu1.dcache.overall_mshr_hits::cpu1.data 8887474 # number of overall MSHR hits 2365system.cpu1.dcache.overall_mshr_hits::total 8887474 # number of overall MSHR hits 2366system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3146802 # number of ReadReq MSHR misses 2367system.cpu1.dcache.ReadReq_mshr_misses::total 3146802 # number of ReadReq MSHR misses 2368system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1356134 # number of WriteReq MSHR misses 2369system.cpu1.dcache.WriteReq_mshr_misses::total 1356134 # number of WriteReq MSHR misses 2370system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 657988 # number of SoftPFReq MSHR misses 2371system.cpu1.dcache.SoftPFReq_mshr_misses::total 657988 # number of SoftPFReq MSHR misses 2372system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 442576 # number of WriteLineReq MSHR misses 2373system.cpu1.dcache.WriteLineReq_mshr_misses::total 442576 # number of WriteLineReq MSHR misses 2374system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 135972 # number of LoadLockedReq MSHR misses 2375system.cpu1.dcache.LoadLockedReq_mshr_misses::total 135972 # number of LoadLockedReq MSHR misses 2376system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193443 # number of StoreCondReq MSHR misses 2377system.cpu1.dcache.StoreCondReq_mshr_misses::total 193443 # number of StoreCondReq MSHR misses 2378system.cpu1.dcache.demand_mshr_misses::cpu1.data 4945512 # number of demand (read+write) MSHR misses 2379system.cpu1.dcache.demand_mshr_misses::total 4945512 # number of demand (read+write) MSHR misses 2380system.cpu1.dcache.overall_mshr_misses::cpu1.data 5603500 # number of overall MSHR misses 2381system.cpu1.dcache.overall_mshr_misses::total 5603500 # number of overall MSHR misses 2382system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6118 # number of ReadReq MSHR uncacheable 2383system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6118 # number of ReadReq MSHR uncacheable 2384system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 6183 # number of WriteReq MSHR uncacheable 2385system.cpu1.dcache.WriteReq_mshr_uncacheable::total 6183 # number of WriteReq MSHR uncacheable 2386system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 12301 # number of overall MSHR uncacheable misses 2387system.cpu1.dcache.overall_mshr_uncacheable_misses::total 12301 # number of overall MSHR uncacheable misses 2388system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43613350000 # number of ReadReq MSHR miss cycles 2389system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43613350000 # number of ReadReq MSHR miss cycles 2390system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26794309953 # number of WriteReq MSHR miss cycles 2391system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26794309953 # number of WriteReq MSHR miss cycles 2392system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14059014500 # number of SoftPFReq MSHR miss cycles 2393system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14059014500 # number of SoftPFReq MSHR miss cycles 2394system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 11316204599 # number of WriteLineReq MSHR miss cycles 2395system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 11316204599 # number of WriteLineReq MSHR miss cycles 2396system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1866790500 # number of LoadLockedReq MSHR miss cycles 2397system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1866790500 # number of LoadLockedReq MSHR miss cycles 2398system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4613147000 # number of StoreCondReq MSHR miss cycles 2399system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4613147000 # number of StoreCondReq MSHR miss cycles 2400system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3645500 # number of StoreCondFailReq MSHR miss cycles 2401system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3645500 # number of StoreCondFailReq MSHR miss cycles 2402system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 81723864552 # number of demand (read+write) MSHR miss cycles 2403system.cpu1.dcache.demand_mshr_miss_latency::total 81723864552 # number of demand (read+write) MSHR miss cycles 2404system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 95782879052 # number of overall MSHR miss cycles 2405system.cpu1.dcache.overall_mshr_miss_latency::total 95782879052 # number of overall MSHR miss cycles 2406system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 749898500 # number of ReadReq MSHR uncacheable cycles 2407system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 749898500 # number of ReadReq MSHR uncacheable cycles 2408system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 749898500 # number of overall MSHR uncacheable cycles 2409system.cpu1.dcache.overall_mshr_uncacheable_latency::total 749898500 # number of overall MSHR uncacheable cycles 2410system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037987 # mshr miss rate for ReadReq accesses 2411system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037987 # mshr miss rate for ReadReq accesses 2412system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019067 # mshr miss rate for WriteReq accesses 2413system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019067 # mshr miss rate for WriteReq accesses 2414system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.794188 # mshr miss rate for SoftPFReq accesses 2415system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.794188 # mshr miss rate for SoftPFReq accesses 2416system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.890250 # mshr miss rate for WriteLineReq accesses 2417system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.890250 # mshr miss rate for WriteLineReq accesses 2418system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068691 # mshr miss rate for LoadLockedReq accesses 2419system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068691 # mshr miss rate for LoadLockedReq accesses 2420system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099960 # mshr miss rate for StoreCondReq accesses 2421system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099960 # mshr miss rate for StoreCondReq accesses 2422system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032018 # mshr miss rate for demand accesses 2423system.cpu1.dcache.demand_mshr_miss_rate::total 0.032018 # mshr miss rate for demand accesses 2424system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.036084 # mshr miss rate for overall accesses 2425system.cpu1.dcache.overall_mshr_miss_rate::total 0.036084 # mshr miss rate for overall accesses 2426system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13859.578709 # average ReadReq mshr miss latency 2427system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13859.578709 # average ReadReq mshr miss latency 2428system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19757.863126 # average WriteReq mshr miss latency 2429system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19757.863126 # average WriteReq mshr miss latency 2430system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21366.673100 # average SoftPFReq mshr miss latency 2431system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21366.673100 # average SoftPFReq mshr miss latency 2432system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 25568.952223 # average WriteLineReq mshr miss latency 2433system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 25568.952223 # average WriteLineReq mshr miss latency 2434system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13729.227341 # average LoadLockedReq mshr miss latency 2435system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13729.227341 # average LoadLockedReq mshr miss latency 2436system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23847.577839 # average StoreCondReq mshr miss latency 2437system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23847.577839 # average StoreCondReq mshr miss latency 2438system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2439system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2440system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16524.854161 # average overall mshr miss latency 2441system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16524.854161 # average overall mshr miss latency 2442system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17093.402169 # average overall mshr miss latency 2443system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17093.402169 # average overall mshr miss latency 2444system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122572.491010 # average ReadReq mshr uncacheable latency 2445system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 122572.491010 # average ReadReq mshr uncacheable latency 2446system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 60962.401431 # average overall mshr uncacheable latency 2447system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 60962.401431 # average overall mshr uncacheable latency 2448system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 2449system.cpu1.icache.tags.replacements 5742782 # number of replacements 2450system.cpu1.icache.tags.tagsinuse 501.536552 # Cycle average of tags in use 2451system.cpu1.icache.tags.total_refs 193871102 # Total number of references to valid blocks. 2452system.cpu1.icache.tags.sampled_refs 5743294 # Sample count of references to valid blocks. 2453system.cpu1.icache.tags.avg_refs 33.756082 # Average number of references to valid blocks. 2454system.cpu1.icache.tags.warmup_cycle 8517126060000 # Cycle when the warmup percentage was hit. 2455system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.536552 # Average occupied blocks per requestor 2456system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979564 # Average percentage of cache occupancy 2457system.cpu1.icache.tags.occ_percent::total 0.979564 # Average percentage of cache occupancy 2458system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2459system.cpu1.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id 2460system.cpu1.icache.tags.age_task_id_blocks_1024::1 396 # Occupied blocks per task id 2461system.cpu1.icache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id 2462system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2463system.cpu1.icache.tags.tag_accesses 405638078 # Number of tag accesses 2464system.cpu1.icache.tags.data_accesses 405638078 # Number of data accesses 2465system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 2466system.cpu1.icache.ReadReq_hits::cpu1.inst 193871102 # number of ReadReq hits 2467system.cpu1.icache.ReadReq_hits::total 193871102 # number of ReadReq hits 2468system.cpu1.icache.demand_hits::cpu1.inst 193871102 # number of demand (read+write) hits 2469system.cpu1.icache.demand_hits::total 193871102 # number of demand (read+write) hits 2470system.cpu1.icache.overall_hits::cpu1.inst 193871102 # number of overall hits 2471system.cpu1.icache.overall_hits::total 193871102 # number of overall hits 2472system.cpu1.icache.ReadReq_misses::cpu1.inst 6076268 # number of ReadReq misses 2473system.cpu1.icache.ReadReq_misses::total 6076268 # number of ReadReq misses 2474system.cpu1.icache.demand_misses::cpu1.inst 6076268 # number of demand (read+write) misses 2475system.cpu1.icache.demand_misses::total 6076268 # number of demand (read+write) misses 2476system.cpu1.icache.overall_misses::cpu1.inst 6076268 # number of overall misses 2477system.cpu1.icache.overall_misses::total 6076268 # number of overall misses 2478system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 64119298557 # number of ReadReq miss cycles 2479system.cpu1.icache.ReadReq_miss_latency::total 64119298557 # number of ReadReq miss cycles 2480system.cpu1.icache.demand_miss_latency::cpu1.inst 64119298557 # number of demand (read+write) miss cycles 2481system.cpu1.icache.demand_miss_latency::total 64119298557 # number of demand (read+write) miss cycles 2482system.cpu1.icache.overall_miss_latency::cpu1.inst 64119298557 # number of overall miss cycles 2483system.cpu1.icache.overall_miss_latency::total 64119298557 # number of overall miss cycles 2484system.cpu1.icache.ReadReq_accesses::cpu1.inst 199947370 # number of ReadReq accesses(hits+misses) 2485system.cpu1.icache.ReadReq_accesses::total 199947370 # number of ReadReq accesses(hits+misses) 2486system.cpu1.icache.demand_accesses::cpu1.inst 199947370 # number of demand (read+write) accesses 2487system.cpu1.icache.demand_accesses::total 199947370 # number of demand (read+write) accesses 2488system.cpu1.icache.overall_accesses::cpu1.inst 199947370 # number of overall (read+write) accesses 2489system.cpu1.icache.overall_accesses::total 199947370 # number of overall (read+write) accesses 2490system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030389 # miss rate for ReadReq accesses 2491system.cpu1.icache.ReadReq_miss_rate::total 0.030389 # miss rate for ReadReq accesses 2492system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030389 # miss rate for demand accesses 2493system.cpu1.icache.demand_miss_rate::total 0.030389 # miss rate for demand accesses 2494system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030389 # miss rate for overall accesses 2495system.cpu1.icache.overall_miss_rate::total 0.030389 # miss rate for overall accesses 2496system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10552.414501 # average ReadReq miss latency 2497system.cpu1.icache.ReadReq_avg_miss_latency::total 10552.414501 # average ReadReq miss latency 2498system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10552.414501 # average overall miss latency 2499system.cpu1.icache.demand_avg_miss_latency::total 10552.414501 # average overall miss latency 2500system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10552.414501 # average overall miss latency 2501system.cpu1.icache.overall_avg_miss_latency::total 10552.414501 # average overall miss latency 2502system.cpu1.icache.blocked_cycles::no_mshrs 9320412 # number of cycles access was blocked 2503system.cpu1.icache.blocked_cycles::no_targets 212 # number of cycles access was blocked 2504system.cpu1.icache.blocked::no_mshrs 713481 # number of cycles access was blocked 2505system.cpu1.icache.blocked::no_targets 3 # number of cycles access was blocked 2506system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.063294 # average number of cycles each access was blocked 2507system.cpu1.icache.avg_blocked_cycles::no_targets 70.666667 # average number of cycles each access was blocked 2508system.cpu1.icache.writebacks::writebacks 5742782 # number of writebacks 2509system.cpu1.icache.writebacks::total 5742782 # number of writebacks 2510system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 332930 # number of ReadReq MSHR hits 2511system.cpu1.icache.ReadReq_mshr_hits::total 332930 # number of ReadReq MSHR hits 2512system.cpu1.icache.demand_mshr_hits::cpu1.inst 332930 # number of demand (read+write) MSHR hits 2513system.cpu1.icache.demand_mshr_hits::total 332930 # number of demand (read+write) MSHR hits 2514system.cpu1.icache.overall_mshr_hits::cpu1.inst 332930 # number of overall MSHR hits 2515system.cpu1.icache.overall_mshr_hits::total 332930 # number of overall MSHR hits 2516system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5743338 # number of ReadReq MSHR misses 2517system.cpu1.icache.ReadReq_mshr_misses::total 5743338 # number of ReadReq MSHR misses 2518system.cpu1.icache.demand_mshr_misses::cpu1.inst 5743338 # number of demand (read+write) MSHR misses 2519system.cpu1.icache.demand_mshr_misses::total 5743338 # number of demand (read+write) MSHR misses 2520system.cpu1.icache.overall_mshr_misses::cpu1.inst 5743338 # number of overall MSHR misses 2521system.cpu1.icache.overall_mshr_misses::total 5743338 # number of overall MSHR misses 2522system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 2523system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable 2524system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 2525system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses 2526system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 58166889552 # number of ReadReq MSHR miss cycles 2527system.cpu1.icache.ReadReq_mshr_miss_latency::total 58166889552 # number of ReadReq MSHR miss cycles 2528system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 58166889552 # number of demand (read+write) MSHR miss cycles 2529system.cpu1.icache.demand_mshr_miss_latency::total 58166889552 # number of demand (read+write) MSHR miss cycles 2530system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58166889552 # number of overall MSHR miss cycles 2531system.cpu1.icache.overall_mshr_miss_latency::total 58166889552 # number of overall MSHR miss cycles 2532system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6789498 # number of ReadReq MSHR uncacheable cycles 2533system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6789498 # number of ReadReq MSHR uncacheable cycles 2534system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6789498 # number of overall MSHR uncacheable cycles 2535system.cpu1.icache.overall_mshr_uncacheable_latency::total 6789498 # number of overall MSHR uncacheable cycles 2536system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028724 # mshr miss rate for ReadReq accesses 2537system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028724 # mshr miss rate for ReadReq accesses 2538system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028724 # mshr miss rate for demand accesses 2539system.cpu1.icache.demand_mshr_miss_rate::total 0.028724 # mshr miss rate for demand accesses 2540system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028724 # mshr miss rate for overall accesses 2541system.cpu1.icache.overall_mshr_miss_rate::total 0.028724 # mshr miss rate for overall accesses 2542system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average ReadReq mshr miss latency 2543system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10127.714850 # average ReadReq mshr miss latency 2544system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency 2545system.cpu1.icache.demand_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency 2546system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency 2547system.cpu1.icache.overall_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency 2548system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average ReadReq mshr uncacheable latency 2549system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101335.791045 # average ReadReq mshr uncacheable latency 2550system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average overall mshr uncacheable latency 2551system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101335.791045 # average overall mshr uncacheable latency 2552system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 2553system.cpu1.l2cache.prefetcher.num_hwpf_issued 7416585 # number of hwpf issued 2554system.cpu1.l2cache.prefetcher.pfIdentified 7422175 # number of prefetch candidates identified 2555system.cpu1.l2cache.prefetcher.pfBufferHit 5069 # number of redundant prefetches already in prefetch queue 2556system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2557system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2558system.cpu1.l2cache.prefetcher.pfSpanPage 930081 # number of prefetches not generated due to page crossing 2559system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 2560system.cpu1.l2cache.tags.replacements 2216875 # number of replacements 2561system.cpu1.l2cache.tags.tagsinuse 13443.573819 # Cycle average of tags in use 2562system.cpu1.l2cache.tags.total_refs 16807540 # Total number of references to valid blocks. 2563system.cpu1.l2cache.tags.sampled_refs 2232789 # Sample count of references to valid blocks. 2564system.cpu1.l2cache.tags.avg_refs 7.527599 # Average number of references to valid blocks. 2565system.cpu1.l2cache.tags.warmup_cycle 9871196159000 # Cycle when the warmup percentage was hit. 2566system.cpu1.l2cache.tags.occ_blocks::writebacks 12560.451650 # Average occupied blocks per requestor 2567system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 62.875087 # Average occupied blocks per requestor 2568system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 63.205555 # Average occupied blocks per requestor 2569system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 757.041527 # Average occupied blocks per requestor 2570system.cpu1.l2cache.tags.occ_percent::writebacks 0.766629 # Average percentage of cache occupancy 2571system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003838 # Average percentage of cache occupancy 2572system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003858 # Average percentage of cache occupancy 2573system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.046206 # Average percentage of cache occupancy 2574system.cpu1.l2cache.tags.occ_percent::total 0.820531 # Average percentage of cache occupancy 2575system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1320 # Occupied blocks per task id 2576system.cpu1.l2cache.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id 2577system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14527 # Occupied blocks per task id 2578system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 25 # Occupied blocks per task id 2579system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 72 # Occupied blocks per task id 2580system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 117 # Occupied blocks per task id 2581system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 681 # Occupied blocks per task id 2582system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 425 # Occupied blocks per task id 2583system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 2584system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id 2585system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id 2586system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 2587system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id 2588system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1030 # Occupied blocks per task id 2589system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5623 # Occupied blocks per task id 2590system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4561 # Occupied blocks per task id 2591system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3143 # Occupied blocks per task id 2592system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080566 # Percentage of cache occupancy per task id 2593system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004089 # Percentage of cache occupancy per task id 2594system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.886658 # Percentage of cache occupancy per task id 2595system.cpu1.l2cache.tags.tag_accesses 383680582 # Number of tag accesses 2596system.cpu1.l2cache.tags.data_accesses 383680582 # Number of data accesses 2597system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 2598system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 591753 # number of ReadReq hits 2599system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 193382 # number of ReadReq hits 2600system.cpu1.l2cache.ReadReq_hits::total 785135 # number of ReadReq hits 2601system.cpu1.l2cache.WritebackDirty_hits::writebacks 3353025 # number of WritebackDirty hits 2602system.cpu1.l2cache.WritebackDirty_hits::total 3353025 # number of WritebackDirty hits 2603system.cpu1.l2cache.WritebackClean_hits::writebacks 7809020 # number of WritebackClean hits 2604system.cpu1.l2cache.WritebackClean_hits::total 7809020 # number of WritebackClean hits 2605system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 779 # number of UpgradeReq hits 2606system.cpu1.l2cache.UpgradeReq_hits::total 779 # number of UpgradeReq hits 2607system.cpu1.l2cache.ReadExReq_hits::cpu1.data 872441 # number of ReadExReq hits 2608system.cpu1.l2cache.ReadExReq_hits::total 872441 # number of ReadExReq hits 2609system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5195235 # number of ReadCleanReq hits 2610system.cpu1.l2cache.ReadCleanReq_hits::total 5195235 # number of ReadCleanReq hits 2611system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2967964 # number of ReadSharedReq hits 2612system.cpu1.l2cache.ReadSharedReq_hits::total 2967964 # number of ReadSharedReq hits 2613system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 177430 # number of InvalidateReq hits 2614system.cpu1.l2cache.InvalidateReq_hits::total 177430 # number of InvalidateReq hits 2615system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 591753 # number of demand (read+write) hits 2616system.cpu1.l2cache.demand_hits::cpu1.itb.walker 193382 # number of demand (read+write) hits 2617system.cpu1.l2cache.demand_hits::cpu1.inst 5195235 # number of demand (read+write) hits 2618system.cpu1.l2cache.demand_hits::cpu1.data 3840405 # number of demand (read+write) hits 2619system.cpu1.l2cache.demand_hits::total 9820775 # number of demand (read+write) hits 2620system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 591753 # number of overall hits 2621system.cpu1.l2cache.overall_hits::cpu1.itb.walker 193382 # number of overall hits 2622system.cpu1.l2cache.overall_hits::cpu1.inst 5195235 # number of overall hits 2623system.cpu1.l2cache.overall_hits::cpu1.data 3840405 # number of overall hits 2624system.cpu1.l2cache.overall_hits::total 9820775 # number of overall hits 2625system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 13125 # number of ReadReq misses 2626system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9784 # number of ReadReq misses 2627system.cpu1.l2cache.ReadReq_misses::total 22909 # number of ReadReq misses 2628system.cpu1.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses 2629system.cpu1.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses 2630system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 2631system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses 2632system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 227942 # number of UpgradeReq misses 2633system.cpu1.l2cache.UpgradeReq_misses::total 227942 # number of UpgradeReq misses 2634system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 193439 # number of SCUpgradeReq misses 2635system.cpu1.l2cache.SCUpgradeReq_misses::total 193439 # number of SCUpgradeReq misses 2636system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses 2637system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 2638system.cpu1.l2cache.ReadExReq_misses::cpu1.data 262152 # number of ReadExReq misses 2639system.cpu1.l2cache.ReadExReq_misses::total 262152 # number of ReadExReq misses 2640system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 548077 # number of ReadCleanReq misses 2641system.cpu1.l2cache.ReadCleanReq_misses::total 548077 # number of ReadCleanReq misses 2642system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 970504 # number of ReadSharedReq misses 2643system.cpu1.l2cache.ReadSharedReq_misses::total 970504 # number of ReadSharedReq misses 2644system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 263582 # number of InvalidateReq misses 2645system.cpu1.l2cache.InvalidateReq_misses::total 263582 # number of InvalidateReq misses 2646system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 13125 # number of demand (read+write) misses 2647system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9784 # number of demand (read+write) misses 2648system.cpu1.l2cache.demand_misses::cpu1.inst 548077 # number of demand (read+write) misses 2649system.cpu1.l2cache.demand_misses::cpu1.data 1232656 # number of demand (read+write) misses 2650system.cpu1.l2cache.demand_misses::total 1803642 # number of demand (read+write) misses 2651system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 13125 # number of overall misses 2652system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9784 # number of overall misses 2653system.cpu1.l2cache.overall_misses::cpu1.inst 548077 # number of overall misses 2654system.cpu1.l2cache.overall_misses::cpu1.data 1232656 # number of overall misses 2655system.cpu1.l2cache.overall_misses::total 1803642 # number of overall misses 2656system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 561719500 # number of ReadReq miss cycles 2657system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 455404000 # number of ReadReq miss cycles 2658system.cpu1.l2cache.ReadReq_miss_latency::total 1017123500 # number of ReadReq miss cycles 2659system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 1976830000 # number of UpgradeReq miss cycles 2660system.cpu1.l2cache.UpgradeReq_miss_latency::total 1976830000 # number of UpgradeReq miss cycles 2661system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1436047000 # number of SCUpgradeReq miss cycles 2662system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1436047000 # number of SCUpgradeReq miss cycles 2663system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3542000 # number of SCUpgradeFailReq miss cycles 2664system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3542000 # number of SCUpgradeFailReq miss cycles 2665system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12377259499 # number of ReadExReq miss cycles 2666system.cpu1.l2cache.ReadExReq_miss_latency::total 12377259499 # number of ReadExReq miss cycles 2667system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 18066070500 # number of ReadCleanReq miss cycles 2668system.cpu1.l2cache.ReadCleanReq_miss_latency::total 18066070500 # number of ReadCleanReq miss cycles 2669system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 33827571986 # number of ReadSharedReq miss cycles 2670system.cpu1.l2cache.ReadSharedReq_miss_latency::total 33827571986 # number of ReadSharedReq miss cycles 2671system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 317775500 # number of InvalidateReq miss cycles 2672system.cpu1.l2cache.InvalidateReq_miss_latency::total 317775500 # number of InvalidateReq miss cycles 2673system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 561719500 # number of demand (read+write) miss cycles 2674system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 455404000 # number of demand (read+write) miss cycles 2675system.cpu1.l2cache.demand_miss_latency::cpu1.inst 18066070500 # number of demand (read+write) miss cycles 2676system.cpu1.l2cache.demand_miss_latency::cpu1.data 46204831485 # number of demand (read+write) miss cycles 2677system.cpu1.l2cache.demand_miss_latency::total 65288025485 # number of demand (read+write) miss cycles 2678system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 561719500 # number of overall miss cycles 2679system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 455404000 # number of overall miss cycles 2680system.cpu1.l2cache.overall_miss_latency::cpu1.inst 18066070500 # number of overall miss cycles 2681system.cpu1.l2cache.overall_miss_latency::cpu1.data 46204831485 # number of overall miss cycles 2682system.cpu1.l2cache.overall_miss_latency::total 65288025485 # number of overall miss cycles 2683system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 604878 # number of ReadReq accesses(hits+misses) 2684system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 203166 # number of ReadReq accesses(hits+misses) 2685system.cpu1.l2cache.ReadReq_accesses::total 808044 # number of ReadReq accesses(hits+misses) 2686system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3353027 # number of WritebackDirty accesses(hits+misses) 2687system.cpu1.l2cache.WritebackDirty_accesses::total 3353027 # number of WritebackDirty accesses(hits+misses) 2688system.cpu1.l2cache.WritebackClean_accesses::writebacks 7809021 # number of WritebackClean accesses(hits+misses) 2689system.cpu1.l2cache.WritebackClean_accesses::total 7809021 # number of WritebackClean accesses(hits+misses) 2690system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 228721 # number of UpgradeReq accesses(hits+misses) 2691system.cpu1.l2cache.UpgradeReq_accesses::total 228721 # number of UpgradeReq accesses(hits+misses) 2692system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 193439 # number of SCUpgradeReq accesses(hits+misses) 2693system.cpu1.l2cache.SCUpgradeReq_accesses::total 193439 # number of SCUpgradeReq accesses(hits+misses) 2694system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 2695system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 2696system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1134593 # number of ReadExReq accesses(hits+misses) 2697system.cpu1.l2cache.ReadExReq_accesses::total 1134593 # number of ReadExReq accesses(hits+misses) 2698system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5743312 # number of ReadCleanReq accesses(hits+misses) 2699system.cpu1.l2cache.ReadCleanReq_accesses::total 5743312 # number of ReadCleanReq accesses(hits+misses) 2700system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3938468 # number of ReadSharedReq accesses(hits+misses) 2701system.cpu1.l2cache.ReadSharedReq_accesses::total 3938468 # number of ReadSharedReq accesses(hits+misses) 2702system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 441012 # number of InvalidateReq accesses(hits+misses) 2703system.cpu1.l2cache.InvalidateReq_accesses::total 441012 # number of InvalidateReq accesses(hits+misses) 2704system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 604878 # number of demand (read+write) accesses 2705system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 203166 # number of demand (read+write) accesses 2706system.cpu1.l2cache.demand_accesses::cpu1.inst 5743312 # number of demand (read+write) accesses 2707system.cpu1.l2cache.demand_accesses::cpu1.data 5073061 # number of demand (read+write) accesses 2708system.cpu1.l2cache.demand_accesses::total 11624417 # number of demand (read+write) accesses 2709system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 604878 # number of overall (read+write) accesses 2710system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 203166 # number of overall (read+write) accesses 2711system.cpu1.l2cache.overall_accesses::cpu1.inst 5743312 # number of overall (read+write) accesses 2712system.cpu1.l2cache.overall_accesses::cpu1.data 5073061 # number of overall (read+write) accesses 2713system.cpu1.l2cache.overall_accesses::total 11624417 # number of overall (read+write) accesses 2714system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021699 # miss rate for ReadReq accesses 2715system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048158 # miss rate for ReadReq accesses 2716system.cpu1.l2cache.ReadReq_miss_rate::total 0.028351 # miss rate for ReadReq accesses 2717system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses 2718system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses 2719system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 2720system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 2721system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.996594 # miss rate for UpgradeReq accesses 2722system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.996594 # miss rate for UpgradeReq accesses 2723system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2724system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2725system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2726system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2727system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.231054 # miss rate for ReadExReq accesses 2728system.cpu1.l2cache.ReadExReq_miss_rate::total 0.231054 # miss rate for ReadExReq accesses 2729system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.095429 # miss rate for ReadCleanReq accesses 2730system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.095429 # miss rate for ReadCleanReq accesses 2731system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.246417 # miss rate for ReadSharedReq accesses 2732system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.246417 # miss rate for ReadSharedReq accesses 2733system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.597675 # miss rate for InvalidateReq accesses 2734system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.597675 # miss rate for InvalidateReq accesses 2735system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021699 # miss rate for demand accesses 2736system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048158 # miss rate for demand accesses 2737system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.095429 # miss rate for demand accesses 2738system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.242981 # miss rate for demand accesses 2739system.cpu1.l2cache.demand_miss_rate::total 0.155160 # miss rate for demand accesses 2740system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021699 # miss rate for overall accesses 2741system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048158 # miss rate for overall accesses 2742system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.095429 # miss rate for overall accesses 2743system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.242981 # miss rate for overall accesses 2744system.cpu1.l2cache.overall_miss_rate::total 0.155160 # miss rate for overall accesses 2745system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 42797.676190 # average ReadReq miss latency 2746system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 46545.789043 # average ReadReq miss latency 2747system.cpu1.l2cache.ReadReq_avg_miss_latency::total 44398.424200 # average ReadReq miss latency 2748system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 8672.513183 # average UpgradeReq miss latency 2749system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 8672.513183 # average UpgradeReq miss latency 2750system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 7423.771835 # average SCUpgradeReq miss latency 2751system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 7423.771835 # average SCUpgradeReq miss latency 2752system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 885500 # average SCUpgradeFailReq miss latency 2753system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 885500 # average SCUpgradeFailReq miss latency 2754system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 47214.057108 # average ReadExReq miss latency 2755system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 47214.057108 # average ReadExReq miss latency 2756system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 32962.650321 # average ReadCleanReq miss latency 2757system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 32962.650321 # average ReadCleanReq miss latency 2758system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 34855.674975 # average ReadSharedReq miss latency 2759system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 34855.674975 # average ReadSharedReq miss latency 2760system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1205.603949 # average InvalidateReq miss latency 2761system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1205.603949 # average InvalidateReq miss latency 2762system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 42797.676190 # average overall miss latency 2763system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 46545.789043 # average overall miss latency 2764system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32962.650321 # average overall miss latency 2765system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37483.962667 # average overall miss latency 2766system.cpu1.l2cache.demand_avg_miss_latency::total 36197.884882 # average overall miss latency 2767system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 42797.676190 # average overall miss latency 2768system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 46545.789043 # average overall miss latency 2769system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32962.650321 # average overall miss latency 2770system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37483.962667 # average overall miss latency 2771system.cpu1.l2cache.overall_avg_miss_latency::total 36197.884882 # average overall miss latency 2772system.cpu1.l2cache.blocked_cycles::no_mshrs 860 # number of cycles access was blocked 2773system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2774system.cpu1.l2cache.blocked::no_mshrs 17 # number of cycles access was blocked 2775system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2776system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 50.588235 # average number of cycles each access was blocked 2777system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2778system.cpu1.l2cache.unused_prefetches 44363 # number of HardPF blocks evicted w/o reference 2779system.cpu1.l2cache.writebacks::writebacks 1196648 # number of writebacks 2780system.cpu1.l2cache.writebacks::total 1196648 # number of writebacks 2781system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits 2782system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 8 # number of ReadReq MSHR hits 2783system.cpu1.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits 2784system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 12956 # number of ReadExReq MSHR hits 2785system.cpu1.l2cache.ReadExReq_mshr_hits::total 12956 # number of ReadExReq MSHR hits 2786system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4132 # number of ReadSharedReq MSHR hits 2787system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4132 # number of ReadSharedReq MSHR hits 2788system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 5 # number of InvalidateReq MSHR hits 2789system.cpu1.l2cache.InvalidateReq_mshr_hits::total 5 # number of InvalidateReq MSHR hits 2790system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 2791system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 8 # number of demand (read+write) MSHR hits 2792system.cpu1.l2cache.demand_mshr_hits::cpu1.data 17088 # number of demand (read+write) MSHR hits 2793system.cpu1.l2cache.demand_mshr_hits::total 17097 # number of demand (read+write) MSHR hits 2794system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 2795system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 8 # number of overall MSHR hits 2796system.cpu1.l2cache.overall_mshr_hits::cpu1.data 17088 # number of overall MSHR hits 2797system.cpu1.l2cache.overall_mshr_hits::total 17097 # number of overall MSHR hits 2798system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 13124 # number of ReadReq MSHR misses 2799system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9776 # number of ReadReq MSHR misses 2800system.cpu1.l2cache.ReadReq_mshr_misses::total 22900 # number of ReadReq MSHR misses 2801system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 2 # number of WritebackDirty MSHR misses 2802system.cpu1.l2cache.WritebackDirty_mshr_misses::total 2 # number of WritebackDirty MSHR misses 2803system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 2804system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses 2805system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 773530 # number of HardPFReq MSHR misses 2806system.cpu1.l2cache.HardPFReq_mshr_misses::total 773530 # number of HardPFReq MSHR misses 2807system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 227942 # number of UpgradeReq MSHR misses 2808system.cpu1.l2cache.UpgradeReq_mshr_misses::total 227942 # number of UpgradeReq MSHR misses 2809system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 193439 # number of SCUpgradeReq MSHR misses 2810system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 193439 # number of SCUpgradeReq MSHR misses 2811system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses 2812system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 2813system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 249196 # number of ReadExReq MSHR misses 2814system.cpu1.l2cache.ReadExReq_mshr_misses::total 249196 # number of ReadExReq MSHR misses 2815system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 548077 # number of ReadCleanReq MSHR misses 2816system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 548077 # number of ReadCleanReq MSHR misses 2817system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 966372 # number of ReadSharedReq MSHR misses 2818system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 966372 # number of ReadSharedReq MSHR misses 2819system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 263577 # number of InvalidateReq MSHR misses 2820system.cpu1.l2cache.InvalidateReq_mshr_misses::total 263577 # number of InvalidateReq MSHR misses 2821system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 13124 # number of demand (read+write) MSHR misses 2822system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9776 # number of demand (read+write) MSHR misses 2823system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 548077 # number of demand (read+write) MSHR misses 2824system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1215568 # number of demand (read+write) MSHR misses 2825system.cpu1.l2cache.demand_mshr_misses::total 1786545 # number of demand (read+write) MSHR misses 2826system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 13124 # number of overall MSHR misses 2827system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9776 # number of overall MSHR misses 2828system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 548077 # number of overall MSHR misses 2829system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1215568 # number of overall MSHR misses 2830system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 773530 # number of overall MSHR misses 2831system.cpu1.l2cache.overall_mshr_misses::total 2560075 # number of overall MSHR misses 2832system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 2833system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6118 # number of ReadReq MSHR uncacheable 2834system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 6185 # number of ReadReq MSHR uncacheable 2835system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 6183 # number of WriteReq MSHR uncacheable 2836system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 6183 # number of WriteReq MSHR uncacheable 2837system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 2838system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 12301 # number of overall MSHR uncacheable misses 2839system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 12368 # number of overall MSHR uncacheable misses 2840system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 482957500 # number of ReadReq MSHR miss cycles 2841system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 396613500 # number of ReadReq MSHR miss cycles 2842system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 879571000 # number of ReadReq MSHR miss cycles 2843system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 40678992877 # number of HardPFReq MSHR miss cycles 2844system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 40678992877 # number of HardPFReq MSHR miss cycles 2845system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4718335995 # number of UpgradeReq MSHR miss cycles 2846system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4718335995 # number of UpgradeReq MSHR miss cycles 2847system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3159514995 # number of SCUpgradeReq MSHR miss cycles 2848system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3159514995 # number of SCUpgradeReq MSHR miss cycles 2849system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3128000 # number of SCUpgradeFailReq MSHR miss cycles 2850system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3128000 # number of SCUpgradeFailReq MSHR miss cycles 2851system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8998543499 # number of ReadExReq MSHR miss cycles 2852system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8998543499 # number of ReadExReq MSHR miss cycles 2853system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14777608500 # number of ReadCleanReq MSHR miss cycles 2854system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14777608500 # number of ReadCleanReq MSHR miss cycles 2855system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 27796571986 # number of ReadSharedReq MSHR miss cycles 2856system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 27796571986 # number of ReadSharedReq MSHR miss cycles 2857system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 7398469497 # number of InvalidateReq MSHR miss cycles 2858system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 7398469497 # number of InvalidateReq MSHR miss cycles 2859system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 482957500 # number of demand (read+write) MSHR miss cycles 2860system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 396613500 # number of demand (read+write) MSHR miss cycles 2861system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14777608500 # number of demand (read+write) MSHR miss cycles 2862system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 36795115485 # number of demand (read+write) MSHR miss cycles 2863system.cpu1.l2cache.demand_mshr_miss_latency::total 52452294985 # number of demand (read+write) MSHR miss cycles 2864system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 482957500 # number of overall MSHR miss cycles 2865system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 396613500 # number of overall MSHR miss cycles 2866system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14777608500 # number of overall MSHR miss cycles 2867system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 36795115485 # number of overall MSHR miss cycles 2868system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 40678992877 # number of overall MSHR miss cycles 2869system.cpu1.l2cache.overall_mshr_miss_latency::total 93131287862 # number of overall MSHR miss cycles 2870system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6286000 # number of ReadReq MSHR uncacheable cycles 2871system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 700808000 # number of ReadReq MSHR uncacheable cycles 2872system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 707094000 # number of ReadReq MSHR uncacheable cycles 2873system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6286000 # number of overall MSHR uncacheable cycles 2874system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 700808000 # number of overall MSHR uncacheable cycles 2875system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 707094000 # number of overall MSHR uncacheable cycles 2876system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021697 # mshr miss rate for ReadReq accesses 2877system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048118 # mshr miss rate for ReadReq accesses 2878system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028340 # mshr miss rate for ReadReq accesses 2879system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 2880system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses 2881system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 2882system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 2883system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2884system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2885system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996594 # mshr miss rate for UpgradeReq accesses 2886system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996594 # mshr miss rate for UpgradeReq accesses 2887system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2888system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2889system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2890system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2891system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.219635 # mshr miss rate for ReadExReq accesses 2892system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.219635 # mshr miss rate for ReadExReq accesses 2893system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.095429 # mshr miss rate for ReadCleanReq accesses 2894system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.095429 # mshr miss rate for ReadCleanReq accesses 2895system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.245367 # mshr miss rate for ReadSharedReq accesses 2896system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.245367 # mshr miss rate for ReadSharedReq accesses 2897system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.597664 # mshr miss rate for InvalidateReq accesses 2898system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.597664 # mshr miss rate for InvalidateReq accesses 2899system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021697 # mshr miss rate for demand accesses 2900system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048118 # mshr miss rate for demand accesses 2901system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.095429 # mshr miss rate for demand accesses 2902system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.239612 # mshr miss rate for demand accesses 2903system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153689 # mshr miss rate for demand accesses 2904system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021697 # mshr miss rate for overall accesses 2905system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048118 # mshr miss rate for overall accesses 2906system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.095429 # mshr miss rate for overall accesses 2907system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.239612 # mshr miss rate for overall accesses 2908system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2909system.cpu1.l2cache.overall_mshr_miss_rate::total 0.220233 # mshr miss rate for overall accesses 2910system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 36799.565681 # average ReadReq mshr miss latency 2911system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40570.120704 # average ReadReq mshr miss latency 2912system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38409.213974 # average ReadReq mshr miss latency 2913system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52588.772093 # average HardPFReq mshr miss latency 2914system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 52588.772093 # average HardPFReq mshr miss latency 2915system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20699.721837 # average UpgradeReq mshr miss latency 2916system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20699.721837 # average UpgradeReq mshr miss latency 2917system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16333.391896 # average SCUpgradeReq mshr miss latency 2918system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16333.391896 # average SCUpgradeReq mshr miss latency 2919system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 782000 # average SCUpgradeFailReq mshr miss latency 2920system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 782000 # average SCUpgradeFailReq mshr miss latency 2921system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36110.304736 # average ReadExReq mshr miss latency 2922system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36110.304736 # average ReadExReq mshr miss latency 2923system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26962.650321 # average ReadCleanReq mshr miss latency 2924system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26962.650321 # average ReadCleanReq mshr miss latency 2925system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28763.842481 # average ReadSharedReq mshr miss latency 2926system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28763.842481 # average ReadSharedReq mshr miss latency 2927system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 28069.480634 # average InvalidateReq mshr miss latency 2928system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 28069.480634 # average InvalidateReq mshr miss latency 2929system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 36799.565681 # average overall mshr miss latency 2930system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 40570.120704 # average overall mshr miss latency 2931system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26962.650321 # average overall mshr miss latency 2932system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 30269.894802 # average overall mshr miss latency 2933system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29359.627093 # average overall mshr miss latency 2934system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 36799.565681 # average overall mshr miss latency 2935system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 40570.120704 # average overall mshr miss latency 2936system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26962.650321 # average overall mshr miss latency 2937system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 30269.894802 # average overall mshr miss latency 2938system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 52588.772093 # average overall mshr miss latency 2939system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36378.343549 # average overall mshr miss latency 2940system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 93820.895522 # average ReadReq mshr uncacheable latency 2941system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 114548.545276 # average ReadReq mshr uncacheable latency 2942system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114324.009701 # average ReadReq mshr uncacheable latency 2943system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 93820.895522 # average overall mshr uncacheable latency 2944system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 56971.628323 # average overall mshr uncacheable latency 2945system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 57171.248383 # average overall mshr uncacheable latency 2946system.cpu1.toL2Bus.snoop_filter.tot_requests 23197310 # Total number of requests made to the snoop filter. 2947system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11940096 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2948system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2949system.cpu1.toL2Bus.snoop_filter.tot_snoops 1942556 # Total number of snoops made to the snoop filter. 2950system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1942287 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2951system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 269 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2952system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 2953system.cpu1.toL2Bus.trans_dist::ReadReq 900600 # Transaction distribution 2954system.cpu1.toL2Bus.trans_dist::ReadResp 10671947 # Transaction distribution 2955system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 2956system.cpu1.toL2Bus.trans_dist::WriteReq 6183 # Transaction distribution 2957system.cpu1.toL2Bus.trans_dist::WriteResp 6183 # Transaction distribution 2958system.cpu1.toL2Bus.trans_dist::WritebackDirty 4554023 # Transaction distribution 2959system.cpu1.toL2Bus.trans_dist::WritebackClean 7810324 # Transaction distribution 2960system.cpu1.toL2Bus.trans_dist::CleanEvict 2589255 # Transaction distribution 2961system.cpu1.toL2Bus.trans_dist::HardPFReq 981692 # Transaction distribution 2962system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution 2963system.cpu1.toL2Bus.trans_dist::UpgradeReq 441382 # Transaction distribution 2964system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 342905 # Transaction distribution 2965system.cpu1.toL2Bus.trans_dist::UpgradeResp 485827 # Transaction distribution 2966system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution 2967system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 140 # Transaction distribution 2968system.cpu1.toL2Bus.trans_dist::ReadExReq 1162425 # Transaction distribution 2969system.cpu1.toL2Bus.trans_dist::ReadExResp 1140502 # Transaction distribution 2970system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5743338 # Transaction distribution 2971system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4866994 # Transaction distribution 2972system.cpu1.toL2Bus.trans_dist::InvalidateReq 495411 # Transaction distribution 2973system.cpu1.toL2Bus.trans_dist::InvalidateResp 441012 # Transaction distribution 2974system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17229566 # Packet count per connected master and slave (bytes) 2975system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17476902 # Packet count per connected master and slave (bytes) 2976system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 425595 # Packet count per connected master and slave (bytes) 2977system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1276864 # Packet count per connected master and slave (bytes) 2978system.cpu1.toL2Bus.pkt_count::total 36408927 # Packet count per connected master and slave (bytes) 2979system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 735111088 # Cumulative packet size per connected master and slave (bytes) 2980system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 677743701 # Cumulative packet size per connected master and slave (bytes) 2981system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1625328 # Cumulative packet size per connected master and slave (bytes) 2982system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4839024 # Cumulative packet size per connected master and slave (bytes) 2983system.cpu1.toL2Bus.pkt_size::total 1419319141 # Cumulative packet size per connected master and slave (bytes) 2984system.cpu1.toL2Bus.snoops 6390553 # Total snoops (count) 2985system.cpu1.toL2Bus.snoop_fanout::samples 18731260 # Request fanout histogram 2986system.cpu1.toL2Bus.snoop_fanout::mean 0.122712 # Request fanout histogram 2987system.cpu1.toL2Bus.snoop_fanout::stdev 0.328150 # Request fanout histogram 2988system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2989system.cpu1.toL2Bus.snoop_fanout::0 16432977 87.73% 87.73% # Request fanout histogram 2990system.cpu1.toL2Bus.snoop_fanout::1 2298014 12.27% 100.00% # Request fanout histogram 2991system.cpu1.toL2Bus.snoop_fanout::2 269 0.00% 100.00% # Request fanout histogram 2992system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2993system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2994system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2995system.cpu1.toL2Bus.snoop_fanout::total 18731260 # Request fanout histogram 2996system.cpu1.toL2Bus.reqLayer0.occupancy 23041315974 # Layer occupancy (ticks) 2997system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2998system.cpu1.toL2Bus.snoopLayer0.occupancy 175324271 # Layer occupancy (ticks) 2999system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3000system.cpu1.toL2Bus.respLayer0.occupancy 8621166733 # Layer occupancy (ticks) 3001system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3002system.cpu1.toL2Bus.respLayer1.occupancy 8059431425 # Layer occupancy (ticks) 3003system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3004system.cpu1.toL2Bus.respLayer2.occupancy 222762323 # Layer occupancy (ticks) 3005system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 3006system.cpu1.toL2Bus.respLayer3.occupancy 672656647 # Layer occupancy (ticks) 3007system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 3008system.iobus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3009system.iobus.trans_dist::ReadReq 40341 # Transaction distribution 3010system.iobus.trans_dist::ReadResp 40341 # Transaction distribution 3011system.iobus.trans_dist::WriteReq 136646 # Transaction distribution 3012system.iobus.trans_dist::WriteResp 136646 # Transaction distribution 3013system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47790 # Packet count per connected master and slave (bytes) 3014system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 3015system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 3016system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 3017system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 3018system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 3019system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 3020system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 3021system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 3022system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 3023system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 3024system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 3025system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 3026system.iobus.pkt_count_system.bridge.master::total 122672 # Packet count per connected master and slave (bytes) 3027system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231222 # Packet count per connected master and slave (bytes) 3028system.iobus.pkt_count_system.realview.ide.dma::total 231222 # Packet count per connected master and slave (bytes) 3029system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 3030system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 3031system.iobus.pkt_count::total 353974 # Packet count per connected master and slave (bytes) 3032system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47810 # Cumulative packet size per connected master and slave (bytes) 3033system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 3034system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 3035system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 3036system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 3037system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 3038system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3039system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3040system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3041system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 3042system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3043system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 3044system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 3045system.iobus.pkt_size_system.bridge.master::total 155802 # Cumulative packet size per connected master and slave (bytes) 3046system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338904 # Cumulative packet size per connected master and slave (bytes) 3047system.iobus.pkt_size_system.realview.ide.dma::total 7338904 # Cumulative packet size per connected master and slave (bytes) 3048system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 3049system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 3050system.iobus.pkt_size::total 7496792 # Cumulative packet size per connected master and slave (bytes) 3051system.iobus.reqLayer0.occupancy 37061004 # Layer occupancy (ticks) 3052system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 3053system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) 3054system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 3055system.iobus.reqLayer2.occupancy 323500 # Layer occupancy (ticks) 3056system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 3057system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) 3058system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 3059system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) 3060system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 3061system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks) 3062system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 3063system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) 3064system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 3065system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) 3066system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 3067system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) 3068system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 3069system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) 3070system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 3071system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 3072system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 3073system.iobus.reqLayer23.occupancy 24283001 # Layer occupancy (ticks) 3074system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 3075system.iobus.reqLayer24.occupancy 36403501 # Layer occupancy (ticks) 3076system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 3077system.iobus.reqLayer25.occupancy 569028004 # Layer occupancy (ticks) 3078system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 3079system.iobus.respLayer0.occupancy 92757000 # Layer occupancy (ticks) 3080system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 3081system.iobus.respLayer3.occupancy 147918000 # Layer occupancy (ticks) 3082system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 3083system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 3084system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 3085system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3086system.iocache.tags.replacements 115592 # number of replacements 3087system.iocache.tags.tagsinuse 11.302694 # Cycle average of tags in use 3088system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 3089system.iocache.tags.sampled_refs 115608 # Sample count of references to valid blocks. 3090system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 3091system.iocache.tags.warmup_cycle 9115775800000 # Cycle when the warmup percentage was hit. 3092system.iocache.tags.occ_blocks::realview.ethernet 3.842796 # Average occupied blocks per requestor 3093system.iocache.tags.occ_blocks::realview.ide 7.459898 # Average occupied blocks per requestor 3094system.iocache.tags.occ_percent::realview.ethernet 0.240175 # Average percentage of cache occupancy 3095system.iocache.tags.occ_percent::realview.ide 0.466244 # Average percentage of cache occupancy 3096system.iocache.tags.occ_percent::total 0.706418 # Average percentage of cache occupancy 3097system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 3098system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 3099system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 3100system.iocache.tags.tag_accesses 1040856 # Number of tag accesses 3101system.iocache.tags.data_accesses 1040856 # Number of data accesses 3102system.iocache.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3103system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 3104system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses 3105system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses 3106system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 3107system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 3108system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 3109system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 3110system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 3111system.iocache.demand_misses::realview.ide 115611 # number of demand (read+write) misses 3112system.iocache.demand_misses::total 115651 # number of demand (read+write) misses 3113system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 3114system.iocache.overall_misses::realview.ide 115611 # number of overall misses 3115system.iocache.overall_misses::total 115651 # number of overall misses 3116system.iocache.ReadReq_miss_latency::realview.ethernet 5246000 # number of ReadReq miss cycles 3117system.iocache.ReadReq_miss_latency::realview.ide 1667860010 # number of ReadReq miss cycles 3118system.iocache.ReadReq_miss_latency::total 1673106010 # number of ReadReq miss cycles 3119system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 3120system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 3121system.iocache.WriteLineReq_miss_latency::realview.ide 12956345994 # number of WriteLineReq miss cycles 3122system.iocache.WriteLineReq_miss_latency::total 12956345994 # number of WriteLineReq miss cycles 3123system.iocache.demand_miss_latency::realview.ethernet 5615000 # number of demand (read+write) miss cycles 3124system.iocache.demand_miss_latency::realview.ide 14624206004 # number of demand (read+write) miss cycles 3125system.iocache.demand_miss_latency::total 14629821004 # number of demand (read+write) miss cycles 3126system.iocache.overall_miss_latency::realview.ethernet 5615000 # number of overall miss cycles 3127system.iocache.overall_miss_latency::realview.ide 14624206004 # number of overall miss cycles 3128system.iocache.overall_miss_latency::total 14629821004 # number of overall miss cycles 3129system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 3130system.iocache.ReadReq_accesses::realview.ide 8883 # number of ReadReq accesses(hits+misses) 3131system.iocache.ReadReq_accesses::total 8920 # number of ReadReq accesses(hits+misses) 3132system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 3133system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 3134system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 3135system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 3136system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 3137system.iocache.demand_accesses::realview.ide 115611 # number of demand (read+write) accesses 3138system.iocache.demand_accesses::total 115651 # number of demand (read+write) accesses 3139system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 3140system.iocache.overall_accesses::realview.ide 115611 # number of overall (read+write) accesses 3141system.iocache.overall_accesses::total 115651 # number of overall (read+write) accesses 3142system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 3143system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 3144system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3145system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 3146system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 3147system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 3148system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 3149system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 3150system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 3151system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3152system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 3153system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 3154system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 3155system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141783.783784 # average ReadReq miss latency 3156system.iocache.ReadReq_avg_miss_latency::realview.ide 187758.641225 # average ReadReq miss latency 3157system.iocache.ReadReq_avg_miss_latency::total 187567.938341 # average ReadReq miss latency 3158system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 3159system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 3160system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121395.941028 # average WriteLineReq miss latency 3161system.iocache.WriteLineReq_avg_miss_latency::total 121395.941028 # average WriteLineReq miss latency 3162system.iocache.demand_avg_miss_latency::realview.ethernet 140375 # average overall miss latency 3163system.iocache.demand_avg_miss_latency::realview.ide 126494.935638 # average overall miss latency 3164system.iocache.demand_avg_miss_latency::total 126499.736310 # average overall miss latency 3165system.iocache.overall_avg_miss_latency::realview.ethernet 140375 # average overall miss latency 3166system.iocache.overall_avg_miss_latency::realview.ide 126494.935638 # average overall miss latency 3167system.iocache.overall_avg_miss_latency::total 126499.736310 # average overall miss latency 3168system.iocache.blocked_cycles::no_mshrs 33436 # number of cycles access was blocked 3169system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3170system.iocache.blocked::no_mshrs 3541 # number of cycles access was blocked 3171system.iocache.blocked::no_targets 0 # number of cycles access was blocked 3172system.iocache.avg_blocked_cycles::no_mshrs 9.442530 # average number of cycles each access was blocked 3173system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3174system.iocache.writebacks::writebacks 106694 # number of writebacks 3175system.iocache.writebacks::total 106694 # number of writebacks 3176system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 3177system.iocache.ReadReq_mshr_misses::realview.ide 8883 # number of ReadReq MSHR misses 3178system.iocache.ReadReq_mshr_misses::total 8920 # number of ReadReq MSHR misses 3179system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 3180system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 3181system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 3182system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 3183system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 3184system.iocache.demand_mshr_misses::realview.ide 115611 # number of demand (read+write) MSHR misses 3185system.iocache.demand_mshr_misses::total 115651 # number of demand (read+write) MSHR misses 3186system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 3187system.iocache.overall_mshr_misses::realview.ide 115611 # number of overall MSHR misses 3188system.iocache.overall_mshr_misses::total 115651 # number of overall MSHR misses 3189system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3396000 # number of ReadReq MSHR miss cycles 3190system.iocache.ReadReq_mshr_miss_latency::realview.ide 1223710010 # number of ReadReq MSHR miss cycles 3191system.iocache.ReadReq_mshr_miss_latency::total 1227106010 # number of ReadReq MSHR miss cycles 3192system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 3193system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 3194system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7611309187 # number of WriteLineReq MSHR miss cycles 3195system.iocache.WriteLineReq_mshr_miss_latency::total 7611309187 # number of WriteLineReq MSHR miss cycles 3196system.iocache.demand_mshr_miss_latency::realview.ethernet 3615000 # number of demand (read+write) MSHR miss cycles 3197system.iocache.demand_mshr_miss_latency::realview.ide 8835019197 # number of demand (read+write) MSHR miss cycles 3198system.iocache.demand_mshr_miss_latency::total 8838634197 # number of demand (read+write) MSHR miss cycles 3199system.iocache.overall_mshr_miss_latency::realview.ethernet 3615000 # number of overall MSHR miss cycles 3200system.iocache.overall_mshr_miss_latency::realview.ide 8835019197 # number of overall MSHR miss cycles 3201system.iocache.overall_mshr_miss_latency::total 8838634197 # number of overall MSHR miss cycles 3202system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 3203system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3204system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3205system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 3206system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 3207system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 3208system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 3209system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 3210system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3211system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3212system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 3213system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3214system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 3215system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91783.783784 # average ReadReq mshr miss latency 3216system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137758.641225 # average ReadReq mshr miss latency 3217system.iocache.ReadReq_avg_mshr_miss_latency::total 137567.938341 # average ReadReq mshr miss latency 3218system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 3219system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 3220system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71315.017493 # average WriteLineReq mshr miss latency 3221system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71315.017493 # average WriteLineReq mshr miss latency 3222system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency 3223system.iocache.demand_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency 3224system.iocache.demand_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency 3225system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency 3226system.iocache.overall_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency 3227system.iocache.overall_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency 3228system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3229system.l2c.tags.replacements 1423185 # number of replacements 3230system.l2c.tags.tagsinuse 63448.336905 # Cycle average of tags in use 3231system.l2c.tags.total_refs 6060449 # Total number of references to valid blocks. 3232system.l2c.tags.sampled_refs 1482600 # Sample count of references to valid blocks. 3233system.l2c.tags.avg_refs 4.087717 # Average number of references to valid blocks. 3234system.l2c.tags.warmup_cycle 3022937500 # Cycle when the warmup percentage was hit. 3235system.l2c.tags.occ_blocks::writebacks 20826.975184 # Average occupied blocks per requestor 3236system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.832374 # Average occupied blocks per requestor 3237system.l2c.tags.occ_blocks::cpu0.itb.walker 12.742051 # Average occupied blocks per requestor 3238system.l2c.tags.occ_blocks::cpu0.inst 3854.622142 # Average occupied blocks per requestor 3239system.l2c.tags.occ_blocks::cpu0.data 3569.542843 # Average occupied blocks per requestor 3240system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 2315.690288 # Average occupied blocks per requestor 3241system.l2c.tags.occ_blocks::cpu1.dtb.walker 335.622211 # Average occupied blocks per requestor 3242system.l2c.tags.occ_blocks::cpu1.itb.walker 552.279614 # Average occupied blocks per requestor 3243system.l2c.tags.occ_blocks::cpu1.inst 2996.807733 # Average occupied blocks per requestor 3244system.l2c.tags.occ_blocks::cpu1.data 11095.009846 # Average occupied blocks per requestor 3245system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17872.212619 # Average occupied blocks per requestor 3246system.l2c.tags.occ_percent::writebacks 0.317794 # Average percentage of cache occupancy 3247system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000257 # Average percentage of cache occupancy 3248system.l2c.tags.occ_percent::cpu0.itb.walker 0.000194 # Average percentage of cache occupancy 3249system.l2c.tags.occ_percent::cpu0.inst 0.058817 # Average percentage of cache occupancy 3250system.l2c.tags.occ_percent::cpu0.data 0.054467 # Average percentage of cache occupancy 3251system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.035335 # Average percentage of cache occupancy 3252system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005121 # Average percentage of cache occupancy 3253system.l2c.tags.occ_percent::cpu1.itb.walker 0.008427 # Average percentage of cache occupancy 3254system.l2c.tags.occ_percent::cpu1.inst 0.045728 # Average percentage of cache occupancy 3255system.l2c.tags.occ_percent::cpu1.data 0.169296 # Average percentage of cache occupancy 3256system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.272708 # Average percentage of cache occupancy 3257system.l2c.tags.occ_percent::total 0.968145 # Average percentage of cache occupancy 3258system.l2c.tags.occ_task_id_blocks::1022 10702 # Occupied blocks per task id 3259system.l2c.tags.occ_task_id_blocks::1023 222 # Occupied blocks per task id 3260system.l2c.tags.occ_task_id_blocks::1024 48491 # Occupied blocks per task id 3261system.l2c.tags.age_task_id_blocks_1022::0 11 # Occupied blocks per task id 3262system.l2c.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id 3263system.l2c.tags.age_task_id_blocks_1022::2 1377 # Occupied blocks per task id 3264system.l2c.tags.age_task_id_blocks_1022::3 482 # Occupied blocks per task id 3265system.l2c.tags.age_task_id_blocks_1022::4 8826 # Occupied blocks per task id 3266system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 3267system.l2c.tags.age_task_id_blocks_1023::4 218 # Occupied blocks per task id 3268system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 3269system.l2c.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id 3270system.l2c.tags.age_task_id_blocks_1024::2 2760 # Occupied blocks per task id 3271system.l2c.tags.age_task_id_blocks_1024::3 5614 # Occupied blocks per task id 3272system.l2c.tags.age_task_id_blocks_1024::4 39761 # Occupied blocks per task id 3273system.l2c.tags.occ_task_id_percent::1022 0.163300 # Percentage of cache occupancy per task id 3274system.l2c.tags.occ_task_id_percent::1023 0.003387 # Percentage of cache occupancy per task id 3275system.l2c.tags.occ_task_id_percent::1024 0.739914 # Percentage of cache occupancy per task id 3276system.l2c.tags.tag_accesses 76659871 # Number of tag accesses 3277system.l2c.tags.data_accesses 76659871 # Number of data accesses 3278system.l2c.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3279system.l2c.WritebackDirty_hits::writebacks 2799563 # number of WritebackDirty hits 3280system.l2c.WritebackDirty_hits::total 2799563 # number of WritebackDirty hits 3281system.l2c.UpgradeReq_hits::cpu0.data 175772 # number of UpgradeReq hits 3282system.l2c.UpgradeReq_hits::cpu1.data 127713 # number of UpgradeReq hits 3283system.l2c.UpgradeReq_hits::total 303485 # number of UpgradeReq hits 3284system.l2c.SCUpgradeReq_hits::cpu0.data 39800 # number of SCUpgradeReq hits 3285system.l2c.SCUpgradeReq_hits::cpu1.data 41169 # number of SCUpgradeReq hits 3286system.l2c.SCUpgradeReq_hits::total 80969 # number of SCUpgradeReq hits 3287system.l2c.ReadExReq_hits::cpu0.data 55176 # number of ReadExReq hits 3288system.l2c.ReadExReq_hits::cpu1.data 52470 # number of ReadExReq hits 3289system.l2c.ReadExReq_hits::total 107646 # number of ReadExReq hits 3290system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6441 # number of ReadSharedReq hits 3291system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4632 # number of ReadSharedReq hits 3292system.l2c.ReadSharedReq_hits::cpu0.inst 512914 # number of ReadSharedReq hits 3293system.l2c.ReadSharedReq_hits::cpu0.data 602529 # number of ReadSharedReq hits 3294system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 321191 # number of ReadSharedReq hits 3295system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6205 # number of ReadSharedReq hits 3296system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4222 # number of ReadSharedReq hits 3297system.l2c.ReadSharedReq_hits::cpu1.inst 506602 # number of ReadSharedReq hits 3298system.l2c.ReadSharedReq_hits::cpu1.data 564191 # number of ReadSharedReq hits 3299system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 285940 # number of ReadSharedReq hits 3300system.l2c.ReadSharedReq_hits::total 2814867 # number of ReadSharedReq hits 3301system.l2c.InvalidateReq_hits::cpu0.data 134470 # number of InvalidateReq hits 3302system.l2c.InvalidateReq_hits::cpu1.data 123510 # number of InvalidateReq hits 3303system.l2c.InvalidateReq_hits::total 257980 # number of InvalidateReq hits 3304system.l2c.demand_hits::cpu0.dtb.walker 6441 # number of demand (read+write) hits 3305system.l2c.demand_hits::cpu0.itb.walker 4632 # number of demand (read+write) hits 3306system.l2c.demand_hits::cpu0.inst 512914 # number of demand (read+write) hits 3307system.l2c.demand_hits::cpu0.data 657705 # number of demand (read+write) hits 3308system.l2c.demand_hits::cpu0.l2cache.prefetcher 321191 # number of demand (read+write) hits 3309system.l2c.demand_hits::cpu1.dtb.walker 6205 # number of demand (read+write) hits 3310system.l2c.demand_hits::cpu1.itb.walker 4222 # number of demand (read+write) hits 3311system.l2c.demand_hits::cpu1.inst 506602 # number of demand (read+write) hits 3312system.l2c.demand_hits::cpu1.data 616661 # number of demand (read+write) hits 3313system.l2c.demand_hits::cpu1.l2cache.prefetcher 285940 # number of demand (read+write) hits 3314system.l2c.demand_hits::total 2922513 # number of demand (read+write) hits 3315system.l2c.overall_hits::cpu0.dtb.walker 6441 # number of overall hits 3316system.l2c.overall_hits::cpu0.itb.walker 4632 # number of overall hits 3317system.l2c.overall_hits::cpu0.inst 512914 # number of overall hits 3318system.l2c.overall_hits::cpu0.data 657705 # number of overall hits 3319system.l2c.overall_hits::cpu0.l2cache.prefetcher 321191 # number of overall hits 3320system.l2c.overall_hits::cpu1.dtb.walker 6205 # number of overall hits 3321system.l2c.overall_hits::cpu1.itb.walker 4222 # number of overall hits 3322system.l2c.overall_hits::cpu1.inst 506602 # number of overall hits 3323system.l2c.overall_hits::cpu1.data 616661 # number of overall hits 3324system.l2c.overall_hits::cpu1.l2cache.prefetcher 285940 # number of overall hits 3325system.l2c.overall_hits::total 2922513 # number of overall hits 3326system.l2c.UpgradeReq_misses::cpu0.data 65800 # number of UpgradeReq misses 3327system.l2c.UpgradeReq_misses::cpu1.data 60076 # number of UpgradeReq misses 3328system.l2c.UpgradeReq_misses::total 125876 # number of UpgradeReq misses 3329system.l2c.SCUpgradeReq_misses::cpu0.data 12292 # number of SCUpgradeReq misses 3330system.l2c.SCUpgradeReq_misses::cpu1.data 11651 # number of SCUpgradeReq misses 3331system.l2c.SCUpgradeReq_misses::total 23943 # number of SCUpgradeReq misses 3332system.l2c.ReadExReq_misses::cpu0.data 76423 # number of ReadExReq misses 3333system.l2c.ReadExReq_misses::cpu1.data 57499 # number of ReadExReq misses 3334system.l2c.ReadExReq_misses::total 133922 # number of ReadExReq misses 3335system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1380 # number of ReadSharedReq misses 3336system.l2c.ReadSharedReq_misses::cpu0.itb.walker 911 # number of ReadSharedReq misses 3337system.l2c.ReadSharedReq_misses::cpu0.inst 60940 # number of ReadSharedReq misses 3338system.l2c.ReadSharedReq_misses::cpu0.data 127468 # number of ReadSharedReq misses 3339system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 217255 # number of ReadSharedReq misses 3340system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3149 # number of ReadSharedReq misses 3341system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2958 # number of ReadSharedReq misses 3342system.l2c.ReadSharedReq_misses::cpu1.inst 41472 # number of ReadSharedReq misses 3343system.l2c.ReadSharedReq_misses::cpu1.data 123752 # number of ReadSharedReq misses 3344system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 256869 # number of ReadSharedReq misses 3345system.l2c.ReadSharedReq_misses::total 836154 # number of ReadSharedReq misses 3346system.l2c.InvalidateReq_misses::cpu0.data 453643 # number of InvalidateReq misses 3347system.l2c.InvalidateReq_misses::cpu1.data 128024 # number of InvalidateReq misses 3348system.l2c.InvalidateReq_misses::total 581667 # number of InvalidateReq misses 3349system.l2c.demand_misses::cpu0.dtb.walker 1380 # number of demand (read+write) misses 3350system.l2c.demand_misses::cpu0.itb.walker 911 # number of demand (read+write) misses 3351system.l2c.demand_misses::cpu0.inst 60940 # number of demand (read+write) misses 3352system.l2c.demand_misses::cpu0.data 203891 # number of demand (read+write) misses 3353system.l2c.demand_misses::cpu0.l2cache.prefetcher 217255 # number of demand (read+write) misses 3354system.l2c.demand_misses::cpu1.dtb.walker 3149 # number of demand (read+write) misses 3355system.l2c.demand_misses::cpu1.itb.walker 2958 # number of demand (read+write) misses 3356system.l2c.demand_misses::cpu1.inst 41472 # number of demand (read+write) misses 3357system.l2c.demand_misses::cpu1.data 181251 # number of demand (read+write) misses 3358system.l2c.demand_misses::cpu1.l2cache.prefetcher 256869 # number of demand (read+write) misses 3359system.l2c.demand_misses::total 970076 # number of demand (read+write) misses 3360system.l2c.overall_misses::cpu0.dtb.walker 1380 # number of overall misses 3361system.l2c.overall_misses::cpu0.itb.walker 911 # number of overall misses 3362system.l2c.overall_misses::cpu0.inst 60940 # number of overall misses 3363system.l2c.overall_misses::cpu0.data 203891 # number of overall misses 3364system.l2c.overall_misses::cpu0.l2cache.prefetcher 217255 # number of overall misses 3365system.l2c.overall_misses::cpu1.dtb.walker 3149 # number of overall misses 3366system.l2c.overall_misses::cpu1.itb.walker 2958 # number of overall misses 3367system.l2c.overall_misses::cpu1.inst 41472 # number of overall misses 3368system.l2c.overall_misses::cpu1.data 181251 # number of overall misses 3369system.l2c.overall_misses::cpu1.l2cache.prefetcher 256869 # number of overall misses 3370system.l2c.overall_misses::total 970076 # number of overall misses 3371system.l2c.UpgradeReq_miss_latency::cpu0.data 448544000 # number of UpgradeReq miss cycles 3372system.l2c.UpgradeReq_miss_latency::cpu1.data 390663000 # number of UpgradeReq miss cycles 3373system.l2c.UpgradeReq_miss_latency::total 839207000 # number of UpgradeReq miss cycles 3374system.l2c.SCUpgradeReq_miss_latency::cpu0.data 74504000 # number of SCUpgradeReq miss cycles 3375system.l2c.SCUpgradeReq_miss_latency::cpu1.data 75234500 # number of SCUpgradeReq miss cycles 3376system.l2c.SCUpgradeReq_miss_latency::total 149738500 # number of SCUpgradeReq miss cycles 3377system.l2c.ReadExReq_miss_latency::cpu0.data 6937615986 # number of ReadExReq miss cycles 3378system.l2c.ReadExReq_miss_latency::cpu1.data 5199044498 # number of ReadExReq miss cycles 3379system.l2c.ReadExReq_miss_latency::total 12136660484 # number of ReadExReq miss cycles 3380system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 131946500 # number of ReadSharedReq miss cycles 3381system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 85177500 # number of ReadSharedReq miss cycles 3382system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5320925500 # number of ReadSharedReq miss cycles 3383system.l2c.ReadSharedReq_miss_latency::cpu0.data 12028584244 # number of ReadSharedReq miss cycles 3384system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 30519314752 # number of ReadSharedReq miss cycles 3385system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 290010000 # number of ReadSharedReq miss cycles 3386system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 265646000 # number of ReadSharedReq miss cycles 3387system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3652893500 # number of ReadSharedReq miss cycles 3388system.l2c.ReadSharedReq_miss_latency::cpu1.data 11931003997 # number of ReadSharedReq miss cycles 3389system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 35372822568 # number of ReadSharedReq miss cycles 3390system.l2c.ReadSharedReq_miss_latency::total 99598324561 # number of ReadSharedReq miss cycles 3391system.l2c.InvalidateReq_miss_latency::cpu0.data 58512500 # number of InvalidateReq miss cycles 3392system.l2c.InvalidateReq_miss_latency::cpu1.data 49578000 # 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number of demand (read+write) miss cycles 3403system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 35372822568 # number of demand (read+write) miss cycles 3404system.l2c.demand_miss_latency::total 111734985045 # number of demand (read+write) miss cycles 3405system.l2c.overall_miss_latency::cpu0.dtb.walker 131946500 # number of overall miss cycles 3406system.l2c.overall_miss_latency::cpu0.itb.walker 85177500 # number of overall miss cycles 3407system.l2c.overall_miss_latency::cpu0.inst 5320925500 # number of overall miss cycles 3408system.l2c.overall_miss_latency::cpu0.data 18966200230 # number of overall miss cycles 3409system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 30519314752 # number of overall miss cycles 3410system.l2c.overall_miss_latency::cpu1.dtb.walker 290010000 # number of overall miss cycles 3411system.l2c.overall_miss_latency::cpu1.itb.walker 265646000 # number of overall miss cycles 3412system.l2c.overall_miss_latency::cpu1.inst 3652893500 # number of overall miss cycles 3413system.l2c.overall_miss_latency::cpu1.data 17130048495 # number of overall miss cycles 3414system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 35372822568 # number of overall miss cycles 3415system.l2c.overall_miss_latency::total 111734985045 # number of overall miss cycles 3416system.l2c.WritebackDirty_accesses::writebacks 2799563 # number of WritebackDirty accesses(hits+misses) 3417system.l2c.WritebackDirty_accesses::total 2799563 # number of WritebackDirty accesses(hits+misses) 3418system.l2c.UpgradeReq_accesses::cpu0.data 241572 # number of UpgradeReq accesses(hits+misses) 3419system.l2c.UpgradeReq_accesses::cpu1.data 187789 # number of UpgradeReq accesses(hits+misses) 3420system.l2c.UpgradeReq_accesses::total 429361 # number of UpgradeReq accesses(hits+misses) 3421system.l2c.SCUpgradeReq_accesses::cpu0.data 52092 # number of SCUpgradeReq accesses(hits+misses) 3422system.l2c.SCUpgradeReq_accesses::cpu1.data 52820 # number of SCUpgradeReq accesses(hits+misses) 3423system.l2c.SCUpgradeReq_accesses::total 104912 # number of SCUpgradeReq accesses(hits+misses) 3424system.l2c.ReadExReq_accesses::cpu0.data 131599 # number of ReadExReq accesses(hits+misses) 3425system.l2c.ReadExReq_accesses::cpu1.data 109969 # number of ReadExReq accesses(hits+misses) 3426system.l2c.ReadExReq_accesses::total 241568 # number of ReadExReq accesses(hits+misses) 3427system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7821 # number of ReadSharedReq accesses(hits+misses) 3428system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5543 # number of ReadSharedReq accesses(hits+misses) 3429system.l2c.ReadSharedReq_accesses::cpu0.inst 573854 # number of ReadSharedReq accesses(hits+misses) 3430system.l2c.ReadSharedReq_accesses::cpu0.data 729997 # number of ReadSharedReq accesses(hits+misses) 3431system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 538446 # number of ReadSharedReq accesses(hits+misses) 3432system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9354 # number of ReadSharedReq accesses(hits+misses) 3433system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7180 # number of ReadSharedReq accesses(hits+misses) 3434system.l2c.ReadSharedReq_accesses::cpu1.inst 548074 # number of ReadSharedReq accesses(hits+misses) 3435system.l2c.ReadSharedReq_accesses::cpu1.data 687943 # number of ReadSharedReq accesses(hits+misses) 3436system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 542809 # number of ReadSharedReq accesses(hits+misses) 3437system.l2c.ReadSharedReq_accesses::total 3651021 # number of ReadSharedReq accesses(hits+misses) 3438system.l2c.InvalidateReq_accesses::cpu0.data 588113 # number of InvalidateReq accesses(hits+misses) 3439system.l2c.InvalidateReq_accesses::cpu1.data 251534 # number of InvalidateReq accesses(hits+misses) 3440system.l2c.InvalidateReq_accesses::total 839647 # number of InvalidateReq accesses(hits+misses) 3441system.l2c.demand_accesses::cpu0.dtb.walker 7821 # number of demand (read+write) accesses 3442system.l2c.demand_accesses::cpu0.itb.walker 5543 # number of demand (read+write) accesses 3443system.l2c.demand_accesses::cpu0.inst 573854 # number of demand (read+write) accesses 3444system.l2c.demand_accesses::cpu0.data 861596 # number of demand (read+write) accesses 3445system.l2c.demand_accesses::cpu0.l2cache.prefetcher 538446 # number of demand (read+write) accesses 3446system.l2c.demand_accesses::cpu1.dtb.walker 9354 # number of demand (read+write) accesses 3447system.l2c.demand_accesses::cpu1.itb.walker 7180 # number of demand (read+write) accesses 3448system.l2c.demand_accesses::cpu1.inst 548074 # number of demand (read+write) accesses 3449system.l2c.demand_accesses::cpu1.data 797912 # number of demand (read+write) accesses 3450system.l2c.demand_accesses::cpu1.l2cache.prefetcher 542809 # number of demand (read+write) accesses 3451system.l2c.demand_accesses::total 3892589 # number of demand (read+write) accesses 3452system.l2c.overall_accesses::cpu0.dtb.walker 7821 # number of overall (read+write) accesses 3453system.l2c.overall_accesses::cpu0.itb.walker 5543 # number of overall (read+write) accesses 3454system.l2c.overall_accesses::cpu0.inst 573854 # number of overall (read+write) accesses 3455system.l2c.overall_accesses::cpu0.data 861596 # number of overall (read+write) accesses 3456system.l2c.overall_accesses::cpu0.l2cache.prefetcher 538446 # number of overall (read+write) accesses 3457system.l2c.overall_accesses::cpu1.dtb.walker 9354 # number of overall (read+write) accesses 3458system.l2c.overall_accesses::cpu1.itb.walker 7180 # number of overall (read+write) accesses 3459system.l2c.overall_accesses::cpu1.inst 548074 # number of overall (read+write) accesses 3460system.l2c.overall_accesses::cpu1.data 797912 # number of overall (read+write) accesses 3461system.l2c.overall_accesses::cpu1.l2cache.prefetcher 542809 # number of overall (read+write) accesses 3462system.l2c.overall_accesses::total 3892589 # number of overall (read+write) accesses 3463system.l2c.UpgradeReq_miss_rate::cpu0.data 0.272383 # miss rate for UpgradeReq accesses 3464system.l2c.UpgradeReq_miss_rate::cpu1.data 0.319912 # miss rate for UpgradeReq accesses 3465system.l2c.UpgradeReq_miss_rate::total 0.293171 # miss rate for UpgradeReq accesses 3466system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.235967 # miss rate for SCUpgradeReq accesses 3467system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.220579 # miss rate for SCUpgradeReq accesses 3468system.l2c.SCUpgradeReq_miss_rate::total 0.228220 # miss rate for SCUpgradeReq accesses 3469system.l2c.ReadExReq_miss_rate::cpu0.data 0.580726 # miss rate for ReadExReq accesses 3470system.l2c.ReadExReq_miss_rate::cpu1.data 0.522866 # miss rate for ReadExReq accesses 3471system.l2c.ReadExReq_miss_rate::total 0.554386 # miss rate for ReadExReq accesses 3472system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.176448 # miss rate for ReadSharedReq accesses 3473system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.164351 # miss rate for ReadSharedReq accesses 3474system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.106194 # miss rate for ReadSharedReq accesses 3475system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.174614 # miss rate for ReadSharedReq accesses 3476system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.403485 # miss rate for ReadSharedReq accesses 3477system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.336647 # miss rate for ReadSharedReq accesses 3478system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.411978 # miss rate for ReadSharedReq accesses 3479system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.075669 # miss rate for ReadSharedReq accesses 3480system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.179887 # miss rate for ReadSharedReq accesses 3481system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.473222 # miss rate for ReadSharedReq accesses 3482system.l2c.ReadSharedReq_miss_rate::total 0.229019 # miss rate for ReadSharedReq accesses 3483system.l2c.InvalidateReq_miss_rate::cpu0.data 0.771353 # miss rate for InvalidateReq accesses 3484system.l2c.InvalidateReq_miss_rate::cpu1.data 0.508973 # miss rate for InvalidateReq accesses 3485system.l2c.InvalidateReq_miss_rate::total 0.692752 # miss rate for InvalidateReq accesses 3486system.l2c.demand_miss_rate::cpu0.dtb.walker 0.176448 # miss rate for demand accesses 3487system.l2c.demand_miss_rate::cpu0.itb.walker 0.164351 # miss rate for demand accesses 3488system.l2c.demand_miss_rate::cpu0.inst 0.106194 # miss rate for demand accesses 3489system.l2c.demand_miss_rate::cpu0.data 0.236643 # miss rate for demand accesses 3490system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.403485 # miss rate for demand accesses 3491system.l2c.demand_miss_rate::cpu1.dtb.walker 0.336647 # miss rate for demand accesses 3492system.l2c.demand_miss_rate::cpu1.itb.walker 0.411978 # miss rate for demand accesses 3493system.l2c.demand_miss_rate::cpu1.inst 0.075669 # miss rate for demand accesses 3494system.l2c.demand_miss_rate::cpu1.data 0.227157 # miss rate for demand accesses 3495system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.473222 # miss rate for demand accesses 3496system.l2c.demand_miss_rate::total 0.249211 # miss rate for demand accesses 3497system.l2c.overall_miss_rate::cpu0.dtb.walker 0.176448 # miss rate for overall accesses 3498system.l2c.overall_miss_rate::cpu0.itb.walker 0.164351 # miss rate for overall accesses 3499system.l2c.overall_miss_rate::cpu0.inst 0.106194 # miss rate for overall accesses 3500system.l2c.overall_miss_rate::cpu0.data 0.236643 # miss rate for overall accesses 3501system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.403485 # miss rate for overall accesses 3502system.l2c.overall_miss_rate::cpu1.dtb.walker 0.336647 # miss rate for overall accesses 3503system.l2c.overall_miss_rate::cpu1.itb.walker 0.411978 # miss rate for overall accesses 3504system.l2c.overall_miss_rate::cpu1.inst 0.075669 # miss rate for overall accesses 3505system.l2c.overall_miss_rate::cpu1.data 0.227157 # miss rate for overall accesses 3506system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.473222 # miss rate for overall accesses 3507system.l2c.overall_miss_rate::total 0.249211 # miss rate for overall accesses 3508system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6816.778116 # average UpgradeReq miss latency 3509system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6502.813103 # average UpgradeReq miss latency 3510system.l2c.UpgradeReq_avg_miss_latency::total 6666.934126 # average UpgradeReq miss latency 3511system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6061.178002 # average SCUpgradeReq miss latency 3512system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6457.342717 # average SCUpgradeReq miss latency 3513system.l2c.SCUpgradeReq_avg_miss_latency::total 6253.957315 # average SCUpgradeReq miss latency 3514system.l2c.ReadExReq_avg_miss_latency::cpu0.data 90779.163158 # average ReadExReq miss latency 3515system.l2c.ReadExReq_avg_miss_latency::cpu1.data 90419.737700 # average ReadExReq miss latency 3516system.l2c.ReadExReq_avg_miss_latency::total 90624.844940 # average ReadExReq miss latency 3517system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 95613.405797 # average ReadSharedReq miss latency 3518system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 93498.902305 # average ReadSharedReq miss latency 3519system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 87314.169675 # average ReadSharedReq miss latency 3520system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 94365.521103 # average ReadSharedReq miss latency 3521system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 140476.926892 # average ReadSharedReq miss latency 3522system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92095.903461 # average ReadSharedReq miss latency 3523system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 89805.949966 # average ReadSharedReq miss latency 3524system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 88080.958237 # average ReadSharedReq miss latency 3525system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 96410.595360 # average ReadSharedReq miss latency 3526system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 137707.635285 # average ReadSharedReq miss latency 3527system.l2c.ReadSharedReq_avg_miss_latency::total 119114.809665 # average ReadSharedReq miss latency 3528system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 128.983584 # average InvalidateReq miss latency 3529system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 387.255515 # average InvalidateReq miss latency 3530system.l2c.InvalidateReq_avg_miss_latency::total 185.828833 # average InvalidateReq miss latency 3531system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 95613.405797 # average overall miss latency 3532system.l2c.demand_avg_miss_latency::cpu0.itb.walker 93498.902305 # average overall miss latency 3533system.l2c.demand_avg_miss_latency::cpu0.inst 87314.169675 # average overall miss latency 3534system.l2c.demand_avg_miss_latency::cpu0.data 93021.272297 # average overall miss latency 3535system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 140476.926892 # average overall miss latency 3536system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92095.903461 # average overall miss latency 3537system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89805.949966 # average overall miss latency 3538system.l2c.demand_avg_miss_latency::cpu1.inst 88080.958237 # average overall miss latency 3539system.l2c.demand_avg_miss_latency::cpu1.data 94510.090951 # average overall miss latency 3540system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 137707.635285 # average overall miss latency 3541system.l2c.demand_avg_miss_latency::total 115181.681688 # average overall miss latency 3542system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 95613.405797 # average overall miss latency 3543system.l2c.overall_avg_miss_latency::cpu0.itb.walker 93498.902305 # average overall miss latency 3544system.l2c.overall_avg_miss_latency::cpu0.inst 87314.169675 # average overall miss latency 3545system.l2c.overall_avg_miss_latency::cpu0.data 93021.272297 # average overall miss latency 3546system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 140476.926892 # average overall miss latency 3547system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92095.903461 # average overall miss latency 3548system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89805.949966 # average overall miss latency 3549system.l2c.overall_avg_miss_latency::cpu1.inst 88080.958237 # average overall miss latency 3550system.l2c.overall_avg_miss_latency::cpu1.data 94510.090951 # average overall miss latency 3551system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 137707.635285 # average overall miss latency 3552system.l2c.overall_avg_miss_latency::total 115181.681688 # average overall miss latency 3553system.l2c.blocked_cycles::no_mshrs 9550 # number of cycles access was blocked 3554system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3555system.l2c.blocked::no_mshrs 102 # number of cycles access was blocked 3556system.l2c.blocked::no_targets 0 # number of cycles access was blocked 3557system.l2c.avg_blocked_cycles::no_mshrs 93.627451 # average number of cycles each access was blocked 3558system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3559system.l2c.writebacks::writebacks 1135323 # number of writebacks 3560system.l2c.writebacks::total 1135323 # number of writebacks 3561system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 111 # number of ReadSharedReq MSHR hits 3562system.l2c.ReadSharedReq_mshr_hits::cpu0.data 20 # number of ReadSharedReq MSHR hits 3563system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 109 # number of ReadSharedReq MSHR hits 3564system.l2c.ReadSharedReq_mshr_hits::cpu1.data 8 # number of ReadSharedReq MSHR hits 3565system.l2c.ReadSharedReq_mshr_hits::total 248 # number of ReadSharedReq MSHR hits 3566system.l2c.demand_mshr_hits::cpu0.inst 111 # number of demand (read+write) MSHR hits 3567system.l2c.demand_mshr_hits::cpu0.data 20 # number of demand (read+write) MSHR hits 3568system.l2c.demand_mshr_hits::cpu1.inst 109 # number of demand (read+write) MSHR hits 3569system.l2c.demand_mshr_hits::cpu1.data 8 # number of demand (read+write) MSHR hits 3570system.l2c.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits 3571system.l2c.overall_mshr_hits::cpu0.inst 111 # number of overall MSHR hits 3572system.l2c.overall_mshr_hits::cpu0.data 20 # number of overall MSHR hits 3573system.l2c.overall_mshr_hits::cpu1.inst 109 # number of overall MSHR hits 3574system.l2c.overall_mshr_hits::cpu1.data 8 # number of overall MSHR hits 3575system.l2c.overall_mshr_hits::total 248 # number of overall MSHR hits 3576system.l2c.CleanEvict_mshr_misses::writebacks 49298 # number of CleanEvict MSHR misses 3577system.l2c.CleanEvict_mshr_misses::total 49298 # number of CleanEvict MSHR misses 3578system.l2c.UpgradeReq_mshr_misses::cpu0.data 65800 # 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number of ReadSharedReq MSHR misses 3590system.l2c.ReadSharedReq_mshr_misses::cpu0.data 127448 # number of ReadSharedReq MSHR misses 3591system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 217255 # number of ReadSharedReq MSHR misses 3592system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 3149 # number of ReadSharedReq MSHR misses 3593system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2958 # number of ReadSharedReq MSHR misses 3594system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 41363 # number of ReadSharedReq MSHR misses 3595system.l2c.ReadSharedReq_mshr_misses::cpu1.data 123744 # number of ReadSharedReq MSHR misses 3596system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 256869 # number of ReadSharedReq MSHR misses 3597system.l2c.ReadSharedReq_mshr_misses::total 835906 # number of ReadSharedReq MSHR misses 3598system.l2c.InvalidateReq_mshr_misses::cpu0.data 453643 # number of InvalidateReq MSHR misses 3599system.l2c.InvalidateReq_mshr_misses::cpu1.data 128024 # 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number of overall MSHR miss cycles 3671system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 76067500 # number of overall MSHR miss cycles 3672system.l2c.overall_mshr_miss_latency::cpu0.inst 4704505587 # number of overall MSHR miss cycles 3673system.l2c.overall_mshr_miss_latency::cpu0.data 16925663829 # number of overall MSHR miss cycles 3674system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 28346572172 # number of overall MSHR miss cycles 3675system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 258517505 # number of overall MSHR miss cycles 3676system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 236065501 # number of overall MSHR miss cycles 3677system.l2c.overall_mshr_miss_latency::cpu1.inst 3231267055 # number of overall MSHR miss cycles 3678system.l2c.overall_mshr_miss_latency::cpu1.data 15316786940 # number of overall MSHR miss cycles 3679system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 32803939514 # number of overall MSHR miss cycles 3680system.l2c.overall_mshr_miss_latency::total 102017531105 # number of overall MSHR miss cycles 3681system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1342704500 # number of ReadReq MSHR uncacheable cycles 3682system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5362205005 # number of ReadReq MSHR uncacheable cycles 3683system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5079500 # number of ReadReq MSHR uncacheable cycles 3684system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 590567503 # number of ReadReq MSHR uncacheable cycles 3685system.l2c.ReadReq_mshr_uncacheable_latency::total 7300556508 # number of ReadReq MSHR uncacheable cycles 3686system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1342704500 # number of overall MSHR uncacheable cycles 3687system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5362205005 # number of overall MSHR uncacheable cycles 3688system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5079500 # number of overall MSHR uncacheable cycles 3689system.l2c.overall_mshr_uncacheable_latency::cpu1.data 590567503 # number of overall MSHR uncacheable cycles 3690system.l2c.overall_mshr_uncacheable_latency::total 7300556508 # number of overall MSHR uncacheable cycles 3691system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3692system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3693system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.272383 # mshr miss rate for UpgradeReq accesses 3694system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.319912 # mshr miss rate for UpgradeReq accesses 3695system.l2c.UpgradeReq_mshr_miss_rate::total 0.293171 # mshr miss rate for UpgradeReq accesses 3696system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.235967 # mshr miss rate for SCUpgradeReq accesses 3697system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.220579 # mshr miss rate for SCUpgradeReq accesses 3698system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.228220 # mshr miss rate for SCUpgradeReq accesses 3699system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.580726 # mshr miss rate for ReadExReq accesses 3700system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.522866 # mshr miss rate for ReadExReq accesses 3701system.l2c.ReadExReq_mshr_miss_rate::total 0.554386 # mshr miss rate for ReadExReq accesses 3702system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.176448 # mshr miss rate for ReadSharedReq accesses 3703system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.164351 # mshr miss rate for ReadSharedReq accesses 3704system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.106001 # mshr miss rate for ReadSharedReq accesses 3705system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.174587 # mshr miss rate for ReadSharedReq accesses 3706system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403485 # mshr miss rate for ReadSharedReq accesses 3707system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.336647 # mshr miss rate for ReadSharedReq accesses 3708system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.411978 # mshr miss rate for ReadSharedReq accesses 3709system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.075470 # mshr miss rate for ReadSharedReq accesses 3710system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.179875 # mshr miss rate for ReadSharedReq accesses 3711system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.473222 # mshr miss rate for ReadSharedReq accesses 3712system.l2c.ReadSharedReq_mshr_miss_rate::total 0.228951 # mshr miss rate for ReadSharedReq accesses 3713system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.771353 # mshr miss rate for InvalidateReq accesses 3714system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.508973 # mshr miss rate for InvalidateReq accesses 3715system.l2c.InvalidateReq_mshr_miss_rate::total 0.692752 # mshr miss rate for InvalidateReq accesses 3716system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.176448 # mshr miss rate for demand accesses 3717system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.164351 # mshr miss rate for demand accesses 3718system.l2c.demand_mshr_miss_rate::cpu0.inst 0.106001 # mshr miss rate for demand accesses 3719system.l2c.demand_mshr_miss_rate::cpu0.data 0.236620 # mshr miss rate for demand accesses 3720system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403485 # mshr miss rate for demand accesses 3721system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.336647 # mshr miss rate for demand accesses 3722system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.411978 # mshr miss rate for demand accesses 3723system.l2c.demand_mshr_miss_rate::cpu1.inst 0.075470 # mshr miss rate for demand accesses 3724system.l2c.demand_mshr_miss_rate::cpu1.data 0.227147 # mshr miss rate for demand accesses 3725system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.473222 # mshr miss rate for demand accesses 3726system.l2c.demand_mshr_miss_rate::total 0.249147 # mshr miss rate for demand accesses 3727system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.176448 # mshr miss rate for overall accesses 3728system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.164351 # mshr miss rate for overall accesses 3729system.l2c.overall_mshr_miss_rate::cpu0.inst 0.106001 # mshr miss rate for overall accesses 3730system.l2c.overall_mshr_miss_rate::cpu0.data 0.236620 # mshr miss rate for overall accesses 3731system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.403485 # mshr miss rate for overall accesses 3732system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.336647 # mshr miss rate for overall accesses 3733system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.411978 # mshr miss rate for overall accesses 3734system.l2c.overall_mshr_miss_rate::cpu1.inst 0.075470 # mshr miss rate for overall accesses 3735system.l2c.overall_mshr_miss_rate::cpu1.data 0.227147 # mshr miss rate for overall accesses 3736system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.473222 # mshr miss rate for overall accesses 3737system.l2c.overall_mshr_miss_rate::total 0.249147 # mshr miss rate for overall accesses 3738system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21800.630729 # average UpgradeReq mshr miss latency 3739system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21481.090535 # average UpgradeReq mshr miss latency 3740system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21648.125910 # average UpgradeReq mshr miss latency 3741system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24728.644566 # average SCUpgradeReq mshr miss latency 3742system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24529.095872 # average SCUpgradeReq mshr miss latency 3743system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24631.541369 # average SCUpgradeReq mshr miss latency 3744system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80776.871426 # average ReadExReq mshr miss latency 3745system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 80418.080175 # average ReadExReq mshr miss latency 3746system.l2c.ReadExReq_avg_mshr_miss_latency::total 80622.825503 # average ReadExReq mshr miss latency 3747system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 85612.682609 # average ReadSharedReq mshr miss latency 3748system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 83498.902305 # average ReadSharedReq mshr miss latency 3749system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 77339.847556 # average ReadSharedReq mshr miss latency 3750system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 84367.373235 # average ReadSharedReq mshr miss latency 3751system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130476.040469 # average ReadSharedReq mshr miss latency 3752system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82095.111146 # average ReadSharedReq mshr miss latency 3753system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 79805.781271 # average ReadSharedReq mshr miss latency 3754system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 78119.746029 # average ReadSharedReq mshr miss latency 3755system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 86410.878491 # average ReadSharedReq mshr miss latency 3756system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 127706.883719 # average ReadSharedReq mshr miss latency 3757system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 109127.534756 # average ReadSharedReq mshr miss latency 3758system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 25238.478491 # average InvalidateReq mshr miss latency 3759system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20854.531182 # average InvalidateReq mshr miss latency 3760system.l2c.InvalidateReq_avg_mshr_miss_latency::total 24273.578522 # average InvalidateReq mshr miss latency 3761system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 85612.682609 # average overall mshr miss latency 3762system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 83498.902305 # average overall mshr miss latency 3763system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 77339.847556 # average overall mshr miss latency 3764system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83021.439189 # average overall mshr miss latency 3765system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130476.040469 # average overall mshr miss latency 3766system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82095.111146 # average overall mshr miss latency 3767system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79805.781271 # average overall mshr miss latency 3768system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 78119.746029 # average overall mshr miss latency 3769system.l2c.demand_avg_mshr_miss_latency::cpu1.data 84509.674525 # average overall mshr miss latency 3770system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 127706.883719 # average overall mshr miss latency 3771system.l2c.demand_avg_mshr_miss_latency::total 105191.364969 # average overall mshr miss latency 3772system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 85612.682609 # average overall mshr miss latency 3773system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 83498.902305 # average overall mshr miss latency 3774system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 77339.847556 # average overall mshr miss latency 3775system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83021.439189 # average overall mshr miss latency 3776system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130476.040469 # average overall mshr miss latency 3777system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82095.111146 # average overall mshr miss latency 3778system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79805.781271 # average overall mshr miss latency 3779system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 78119.746029 # average overall mshr miss latency 3780system.l2c.overall_avg_mshr_miss_latency::cpu1.data 84509.674525 # average overall mshr miss latency 3781system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 127706.883719 # average overall mshr miss latency 3782system.l2c.overall_avg_mshr_miss_latency::total 105191.364969 # average overall mshr miss latency 3783system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average ReadReq mshr uncacheable latency 3784system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 164853.967627 # average ReadReq mshr uncacheable latency 3785system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75813.432836 # average ReadReq mshr uncacheable latency 3786system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 96561.069817 # average ReadReq mshr uncacheable latency 3787system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 121669.858307 # average ReadReq mshr uncacheable latency 3788system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average overall mshr uncacheable latency 3789system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 82650.590416 # average overall mshr uncacheable latency 3790system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 75813.432836 # average overall mshr uncacheable latency 3791system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 48017.521994 # average overall mshr uncacheable latency 3792system.l2c.overall_avg_mshr_uncacheable_latency::total 74089.494383 # average overall mshr uncacheable latency 3793system.membus.snoop_filter.tot_requests 3952559 # Total number of requests made to the snoop filter. 3794system.membus.snoop_filter.hit_single_requests 2414080 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3795system.membus.snoop_filter.hit_multi_requests 2931 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3796system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3797system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3798system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3799system.membus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3800system.membus.trans_dist::ReadReq 60003 # Transaction distribution 3801system.membus.trans_dist::ReadResp 904829 # Transaction distribution 3802system.membus.trans_dist::WriteReq 38534 # Transaction distribution 3803system.membus.trans_dist::WriteResp 38534 # Transaction distribution 3804system.membus.trans_dist::WritebackDirty 1242017 # Transaction distribution 3805system.membus.trans_dist::CleanEvict 238236 # Transaction distribution 3806system.membus.trans_dist::UpgradeReq 446737 # Transaction distribution 3807system.membus.trans_dist::SCUpgradeReq 299659 # Transaction distribution 3808system.membus.trans_dist::UpgradeResp 23 # Transaction distribution 3809system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 3810system.membus.trans_dist::ReadExReq 144708 # Transaction distribution 3811system.membus.trans_dist::ReadExResp 128413 # Transaction distribution 3812system.membus.trans_dist::ReadSharedReq 844826 # Transaction distribution 3813system.membus.trans_dist::InvalidateReq 684897 # Transaction distribution 3814system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122672 # Packet count per connected master and slave (bytes) 3815system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) 3816system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26462 # Packet count per connected master and slave (bytes) 3817system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4681290 # Packet count per connected master and slave (bytes) 3818system.membus.pkt_count_system.l2c.mem_side::total 4830500 # Packet count per connected master and slave (bytes) 3819system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238195 # Packet count per connected master and slave (bytes) 3820system.membus.pkt_count_system.iocache.mem_side::total 238195 # Packet count per connected master and slave (bytes) 3821system.membus.pkt_count::total 5068695 # Packet count per connected master and slave (bytes) 3822system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155802 # Cumulative packet size per connected master and slave (bytes) 3823system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) 3824system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52924 # Cumulative packet size per connected master and slave (bytes) 3825system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 134692416 # Cumulative packet size per connected master and slave (bytes) 3826system.membus.pkt_size_system.l2c.mem_side::total 134901698 # Cumulative packet size per connected master and slave (bytes) 3827system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7273344 # Cumulative packet size per connected master and slave (bytes) 3828system.membus.pkt_size_system.iocache.mem_side::total 7273344 # Cumulative packet size per connected master and slave (bytes) 3829system.membus.pkt_size::total 142175042 # Cumulative packet size per connected master and slave (bytes) 3830system.membus.snoops 606585 # Total snoops (count) 3831system.membus.snoop_fanout::samples 2519367 # Request fanout histogram 3832system.membus.snoop_fanout::mean 0.015113 # Request fanout histogram 3833system.membus.snoop_fanout::stdev 0.122002 # Request fanout histogram 3834system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3835system.membus.snoop_fanout::0 2481292 98.49% 98.49% # Request fanout histogram 3836system.membus.snoop_fanout::1 38075 1.51% 100.00% # Request fanout histogram 3837system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3838system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3839system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3840system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3841system.membus.snoop_fanout::total 2519367 # Request fanout histogram 3842system.membus.reqLayer0.occupancy 98170994 # Layer occupancy (ticks) 3843system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3844system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks) 3845system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3846system.membus.reqLayer2.occupancy 22248500 # Layer occupancy (ticks) 3847system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3848system.membus.reqLayer5.occupancy 8723892621 # Layer occupancy (ticks) 3849system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3850system.membus.respLayer2.occupancy 5223815230 # Layer occupancy (ticks) 3851system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3852system.membus.respLayer3.occupancy 45514707 # Layer occupancy (ticks) 3853system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3854system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3855system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3856system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3857system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3858system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3859system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3860system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3861system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3862system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3863system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3864system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3865system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3866system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3867system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3868system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3869system.realview.ethernet.txBytes 966 # Bytes Transmitted 3870system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3871system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3872system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3873system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3874system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3875system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3876system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3877system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3878system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3879system.realview.ethernet.totPackets 3 # Total Packets 3880system.realview.ethernet.totBytes 966 # Total Bytes 3881system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3882system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3883system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3884system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3885system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3886system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3887system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3888system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3889system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3890system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3891system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3892system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3893system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3894system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3895system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3896system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3897system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3898system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3899system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3900system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3901system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3902system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3903system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3904system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3905system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3906system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3907system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3908system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3909system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3910system.realview.ethernet.droppedPackets 0 # number of packets dropped 3911system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3912system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3913system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3914system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3915system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3916system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3917system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3918system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3919system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3920system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3921system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3922system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3923system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3924system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3925system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3926system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3927system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3928system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3929system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3930system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3931system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3932system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3933system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3934system.toL2Bus.snoop_filter.tot_requests 11842018 # Total number of requests made to the snoop filter. 3935system.toL2Bus.snoop_filter.hit_single_requests 6441759 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3936system.toL2Bus.snoop_filter.hit_multi_requests 1913591 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3937system.toL2Bus.snoop_filter.tot_snoops 133722 # Total number of snoops made to the snoop filter. 3938system.toL2Bus.snoop_filter.hit_single_snoops 121814 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3939system.toL2Bus.snoop_filter.hit_multi_snoops 11908 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3940system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384315163000 # Cumulative time (in ticks) in various power states 3941system.toL2Bus.trans_dist::ReadReq 60005 # Transaction distribution 3942system.toL2Bus.trans_dist::ReadResp 4492996 # Transaction distribution 3943system.toL2Bus.trans_dist::WriteReq 38534 # Transaction distribution 3944system.toL2Bus.trans_dist::WriteResp 38534 # Transaction distribution 3945system.toL2Bus.trans_dist::WritebackDirty 3934886 # Transaction distribution 3946system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution 3947system.toL2Bus.trans_dist::CleanEvict 2625367 # Transaction distribution 3948system.toL2Bus.trans_dist::UpgradeReq 741215 # Transaction distribution 3949system.toL2Bus.trans_dist::SCUpgradeReq 380628 # Transaction distribution 3950system.toL2Bus.trans_dist::UpgradeResp 1121842 # Transaction distribution 3951system.toL2Bus.trans_dist::SCUpgradeFailReq 140 # Transaction distribution 3952system.toL2Bus.trans_dist::UpgradeFailResp 140 # Transaction distribution 3953system.toL2Bus.trans_dist::ReadExReq 295903 # Transaction distribution 3954system.toL2Bus.trans_dist::ReadExResp 295903 # Transaction distribution 3955system.toL2Bus.trans_dist::ReadSharedReq 4433512 # Transaction distribution 3956system.toL2Bus.trans_dist::InvalidateReq 874748 # Transaction distribution 3957system.toL2Bus.trans_dist::InvalidateResp 839647 # Transaction distribution 3958system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9358904 # Packet count per connected master and slave (bytes) 3959system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7932274 # Packet count per connected master and slave (bytes) 3960system.toL2Bus.pkt_count::total 17291178 # Packet count per connected master and slave (bytes) 3961system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 230390413 # Cumulative packet size per connected master and slave (bytes) 3962system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 198586357 # Cumulative packet size per connected master and slave (bytes) 3963system.toL2Bus.pkt_size::total 428976770 # Cumulative packet size per connected master and slave (bytes) 3964system.toL2Bus.snoops 2884507 # Total snoops (count) 3965system.toL2Bus.snoop_fanout::samples 8248846 # Request fanout histogram 3966system.toL2Bus.snoop_fanout::mean 0.358423 # Request fanout histogram 3967system.toL2Bus.snoop_fanout::stdev 0.482538 # Request fanout histogram 3968system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3969system.toL2Bus.snoop_fanout::0 5304178 64.30% 64.30% # Request fanout histogram 3970system.toL2Bus.snoop_fanout::1 2932760 35.55% 99.86% # Request fanout histogram 3971system.toL2Bus.snoop_fanout::2 11908 0.14% 100.00% # Request fanout histogram 3972system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3973system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3974system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3975system.toL2Bus.snoop_fanout::total 8248846 # Request fanout histogram 3976system.toL2Bus.reqLayer0.occupancy 9216694138 # Layer occupancy (ticks) 3977system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3978system.toL2Bus.snoopLayer0.occupancy 2593163 # Layer occupancy (ticks) 3979system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3980system.toL2Bus.respLayer0.occupancy 4234968582 # Layer occupancy (ticks) 3981system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3982system.toL2Bus.respLayer1.occupancy 3934186551 # Layer occupancy (ticks) 3983system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3984system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3985system.cpu0.kern.inst.quiesce 13240 # number of quiesce instructions executed 3986system.cpu1.kern.inst.arm 0 # number of arm instructions executed 3987system.cpu1.kern.inst.quiesce 5626 # number of quiesce instructions executed 3988 3989---------- End Simulation Statistics ----------