1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.384315 # Number of seconds simulated
4sim_ticks 47384315163000 # Number of ticks simulated
5final_tick 47384315163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 172390 # Simulator instruction rate (inst/s)
8host_op_rate 202727 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 9043218476 # Simulator tick rate (ticks/s)
10host_mem_usage 765852 # Number of bytes of host memory used
11host_seconds 5239.76 # Real time elapsed on the host
12sim_insts 903281747 # Number of instructions simulated
13sim_ops 1062243320 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 88320 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 58304 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 4233376 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 12825352 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 13896960 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 201536 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 189312 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 2647264 # Number of bytes read from this memory
--- 289 unchanged lines hidden (view full) ---
313system.physmem_1.preBackEnergy 27415968105750 # Energy for precharge background per rank (pJ)
314system.physmem_1.totalEnergy 31681249248975 # Total energy per rank (pJ)
315system.physmem_1.averagePower 668.602035 # Core power per rank (mW)
316system.physmem_1.memoryStateTime::IDLE 45608919765384 # Time in different power states
317system.physmem_1.memoryStateTime::REF 1582266400000 # Time in different power states
318system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
319system.physmem_1.memoryStateTime::ACT 193128558366 # Time in different power states
320system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
321system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory
322system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
323system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
324system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
325system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory
326system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory
327system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory
328system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory
--- 10 unchanged lines hidden (view full) ---
339system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
340system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s)
341system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s)
342system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
343system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
344system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s)
345system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
346system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
347system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
348system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
349system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
350system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
351system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
352system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
353system.cpu0.branchPred.lookups 138091637 # Number of BP lookups
354system.cpu0.branchPred.condPredicted 91311717 # Number of conditional branches predicted
--- 4 unchanged lines hidden (view full) ---
359system.cpu0.branchPred.BTBHitPct 61.575961 # BTB Hit Percentage
360system.cpu0.branchPred.usedRAS 18644167 # Number of times the RAS was used to get a target.
361system.cpu0.branchPred.RASInCorrect 188685 # Number of incorrect RAS predictions.
362system.cpu0.branchPred.indirectLookups 4389066 # Number of indirect predictor lookups.
363system.cpu0.branchPred.indirectHits 2747803 # Number of indirect target hits.
364system.cpu0.branchPred.indirectMisses 1641263 # Number of indirect misses.
365system.cpu0.branchPredindirectMispredicted 409141 # Number of mispredicted indirect branches.
366system.cpu_clk_domain.clock 500 # Clock period in ticks
367system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
368system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
369system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
370system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
371system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
372system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
373system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
374system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
388system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
389system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
390system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
391system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
392system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
393system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
394system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
395system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
396system.cpu0.dtb.walker.walks 530338 # Table walker walks requested
397system.cpu0.dtb.walker.walksLong 530338 # Table walker walks initiated with long descriptors
398system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10426 # Level at which table walker walks with long descriptors terminate
399system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79784 # Level at which table walker walks with long descriptors terminate
400system.cpu0.dtb.walker.walksSquashedBefore 241995 # Table walks squashed before starting
401system.cpu0.dtb.walker.walkWaitTime::samples 288343 # Table walker wait (enqueue to first request) latency
402system.cpu0.dtb.walker.walkWaitTime::mean 2099.123266 # Table walker wait (enqueue to first request) latency
403system.cpu0.dtb.walker.walkWaitTime::stdev 12230.418976 # Table walker wait (enqueue to first request) latency
--- 66 unchanged lines hidden (view full) ---
470system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
471system.cpu0.dtb.perms_faults 39704 # Number of TLB faults due to permissions restrictions
472system.cpu0.dtb.read_accesses 100057654 # DTB read accesses
473system.cpu0.dtb.write_accesses 83209467 # DTB write accesses
474system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
475system.cpu0.dtb.hits 182736783 # DTB hits
476system.cpu0.dtb.misses 530338 # DTB misses
477system.cpu0.dtb.accesses 183267121 # DTB accesses
478system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
479system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
480system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
481system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
499system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
500system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
501system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
502system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
503system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
504system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
505system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
506system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
507system.cpu0.itb.walker.walks 81834 # Table walker walks requested
508system.cpu0.itb.walker.walksLong 81834 # Table walker walks initiated with long descriptors
509system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1030 # Level at which table walker walks with long descriptors terminate
510system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58824 # Level at which table walker walks with long descriptors terminate
511system.cpu0.itb.walker.walksSquashedBefore 9805 # Table walks squashed before starting
512system.cpu0.itb.walker.walkWaitTime::samples 72029 # Table walker wait (enqueue to first request) latency
513system.cpu0.itb.walker.walkWaitTime::mean 864.033931 # Table walker wait (enqueue to first request) latency
514system.cpu0.itb.walker.walkWaitTime::stdev 6165.525550 # Table walker wait (enqueue to first request) latency
--- 64 unchanged lines hidden (view full) ---
579system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
580system.cpu0.itb.perms_faults 198402 # Number of TLB faults due to permissions restrictions
581system.cpu0.itb.read_accesses 0 # DTB read accesses
582system.cpu0.itb.write_accesses 0 # DTB write accesses
583system.cpu0.itb.inst_accesses 216603307 # ITB inst accesses
584system.cpu0.itb.hits 216521473 # DTB hits
585system.cpu0.itb.misses 81834 # DTB misses
586system.cpu0.itb.accesses 216603307 # DTB accesses
587system.cpu0.numCycles 746014900 # number of cpu cycles simulated
588system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
589system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
590system.cpu0.fetch.icacheStallCycles 90433879 # Number of cycles fetch is stalled on an Icache miss
591system.cpu0.fetch.Insts 610172736 # Number of instructions fetch has processed
592system.cpu0.fetch.Branches 138091637 # Number of branches that fetch encountered
593system.cpu0.fetch.predictedBranches 81258280 # Number of branches that fetch has predicted taken
594system.cpu0.fetch.Cycles 615398287 # Number of cycles fetch has run and was not squashing or blocked
--- 279 unchanged lines hidden (view full) ---
874system.cpu0.int_regfile_reads 694459704 # number of integer regfile reads
875system.cpu0.int_regfile_writes 413089219 # number of integer regfile writes
876system.cpu0.fp_regfile_reads 846069 # number of floating regfile reads
877system.cpu0.fp_regfile_writes 429660 # number of floating regfile writes
878system.cpu0.cc_regfile_reads 127998327 # number of cc regfile reads
879system.cpu0.cc_regfile_writes 128742208 # number of cc regfile writes
880system.cpu0.misc_regfile_reads 1288788249 # number of misc regfile reads
881system.cpu0.misc_regfile_writes 14832406 # number of misc regfile writes
882system.cpu0.dcache.tags.replacements 5793916 # number of replacements
883system.cpu0.dcache.tags.tagsinuse 505.305765 # Cycle average of tags in use
884system.cpu0.dcache.tags.total_refs 157106373 # Total number of references to valid blocks.
885system.cpu0.dcache.tags.sampled_refs 5794427 # Sample count of references to valid blocks.
886system.cpu0.dcache.tags.avg_refs 27.113358 # Average number of references to valid blocks.
887system.cpu0.dcache.tags.warmup_cycle 1908955000 # Cycle when the warmup percentage was hit.
888system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.305765 # Average occupied blocks per requestor
889system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986925 # Average percentage of cache occupancy
890system.cpu0.dcache.tags.occ_percent::total 0.986925 # Average percentage of cache occupancy
891system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
892system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
893system.cpu0.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id
894system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
895system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
896system.cpu0.dcache.tags.tag_accesses 349540400 # Number of tag accesses
897system.cpu0.dcache.tags.data_accesses 349540400 # Number of data accesses
898system.cpu0.dcache.ReadReq_hits::cpu0.data 81616032 # number of ReadReq hits
899system.cpu0.dcache.ReadReq_hits::total 81616032 # number of ReadReq hits
900system.cpu0.dcache.WriteReq_hits::cpu0.data 70522769 # number of WriteReq hits
901system.cpu0.dcache.WriteReq_hits::total 70522769 # number of WriteReq hits
902system.cpu0.dcache.SoftPFReq_hits::cpu0.data 213045 # number of SoftPFReq hits
903system.cpu0.dcache.SoftPFReq_hits::total 213045 # number of SoftPFReq hits
904system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259663 # number of WriteLineReq hits
905system.cpu0.dcache.WriteLineReq_hits::total 259663 # number of WriteLineReq hits
--- 182 unchanged lines hidden (view full) ---
1088system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19061.608373 # average overall mshr miss latency
1089system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19061.608373 # average overall mshr miss latency
1090system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19427.364492 # average overall mshr miss latency
1091system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19427.364492 # average overall mshr miss latency
1092system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190877.363421 # average ReadReq mshr uncacheable latency
1093system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190877.363421 # average ReadReq mshr uncacheable latency
1094system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95697.586239 # average overall mshr uncacheable latency
1095system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95697.586239 # average overall mshr uncacheable latency
1096system.cpu0.icache.tags.replacements 6136519 # number of replacements
1097system.cpu0.icache.tags.tagsinuse 511.962391 # Cycle average of tags in use
1098system.cpu0.icache.tags.total_refs 209807209 # Total number of references to valid blocks.
1099system.cpu0.icache.tags.sampled_refs 6137031 # Sample count of references to valid blocks.
1100system.cpu0.icache.tags.avg_refs 34.187086 # Average number of references to valid blocks.
1101system.cpu0.icache.tags.warmup_cycle 12886295000 # Cycle when the warmup percentage was hit.
1102system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.962391 # Average occupied blocks per requestor
1103system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999927 # Average percentage of cache occupancy
1104system.cpu0.icache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy
1105system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1106system.cpu0.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id
1107system.cpu0.icache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id
1108system.cpu0.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id
1109system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1110system.cpu0.icache.tags.tag_accesses 438728804 # Number of tag accesses
1111system.cpu0.icache.tags.data_accesses 438728804 # Number of data accesses
1112system.cpu0.icache.ReadReq_hits::cpu0.inst 209807209 # number of ReadReq hits
1113system.cpu0.icache.ReadReq_hits::total 209807209 # number of ReadReq hits
1114system.cpu0.icache.demand_hits::cpu0.inst 209807209 # number of demand (read+write) hits
1115system.cpu0.icache.demand_hits::total 209807209 # number of demand (read+write) hits
1116system.cpu0.icache.overall_hits::cpu0.inst 209807209 # number of overall hits
1117system.cpu0.icache.overall_hits::total 209807209 # number of overall hits
1118system.cpu0.icache.ReadReq_misses::cpu0.inst 6488653 # number of ReadReq misses
1119system.cpu0.icache.ReadReq_misses::total 6488653 # number of ReadReq misses
--- 70 unchanged lines hidden (view full) ---
1190system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency
1191system.cpu0.icache.demand_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency
1192system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency
1193system.cpu0.icache.overall_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency
1194system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average ReadReq mshr uncacheable latency
1195system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753 # average ReadReq mshr uncacheable latency
1196system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average overall mshr uncacheable latency
1197system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753 # average overall mshr uncacheable latency
1198system.cpu0.l2cache.prefetcher.num_hwpf_issued 7743703 # number of hwpf issued
1199system.cpu0.l2cache.prefetcher.pfIdentified 7754051 # number of prefetch candidates identified
1200system.cpu0.l2cache.prefetcher.pfBufferHit 9277 # number of redundant prefetches already in prefetch queue
1201system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1202system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1203system.cpu0.l2cache.prefetcher.pfSpanPage 1008365 # number of prefetches not generated due to page crossing
1204system.cpu0.l2cache.tags.replacements 2565485 # number of replacements
1205system.cpu0.l2cache.tags.tagsinuse 15956.741738 # Cycle average of tags in use
1206system.cpu0.l2cache.tags.total_refs 17408441 # Total number of references to valid blocks.
1207system.cpu0.l2cache.tags.sampled_refs 2581334 # Sample count of references to valid blocks.
1208system.cpu0.l2cache.tags.avg_refs 6.743971 # Average number of references to valid blocks.
1209system.cpu0.l2cache.tags.warmup_cycle 2212473000 # Cycle when the warmup percentage was hit.
1210system.cpu0.l2cache.tags.occ_blocks::writebacks 14849.648482 # Average occupied blocks per requestor
1211system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 36.124813 # Average occupied blocks per requestor
--- 21 unchanged lines hidden (view full) ---
1233system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4722 # Occupied blocks per task id
1234system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4695 # Occupied blocks per task id
1235system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3741 # Occupied blocks per task id
1236system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.073425 # Percentage of cache occupancy per task id
1237system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id
1238system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.889221 # Percentage of cache occupancy per task id
1239system.cpu0.l2cache.tags.tag_accesses 408243228 # Number of tag accesses
1240system.cpu0.l2cache.tags.data_accesses 408243228 # Number of data accesses
1241system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 539952 # number of ReadReq hits
1242system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 183800 # number of ReadReq hits
1243system.cpu0.l2cache.ReadReq_hits::total 723752 # number of ReadReq hits
1244system.cpu0.l2cache.WritebackDirty_hits::writebacks 3863126 # number of WritebackDirty hits
1245system.cpu0.l2cache.WritebackDirty_hits::total 3863126 # number of WritebackDirty hits
1246system.cpu0.l2cache.WritebackClean_hits::writebacks 8065215 # number of WritebackClean hits
1247system.cpu0.l2cache.WritebackClean_hits::total 8065215 # number of WritebackClean hits
1248system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 386 # number of UpgradeReq hits
--- 342 unchanged lines hidden (view full) ---
1591system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91677.525509 # average overall mshr uncacheable latency
1592system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89053.550498 # average overall mshr uncacheable latency
1593system.cpu0.toL2Bus.snoop_filter.tot_requests 24754475 # Total number of requests made to the snoop filter.
1594system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12719207 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1595system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2136 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1596system.cpu0.toL2Bus.snoop_filter.tot_snoops 1997962 # Total number of snoops made to the snoop filter.
1597system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1997498 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1598system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 464 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1599system.cpu0.toL2Bus.trans_dist::ReadReq 885324 # Transaction distribution
1600system.cpu0.toL2Bus.trans_dist::ReadResp 11040535 # Transaction distribution
1601system.cpu0.toL2Bus.trans_dist::WriteReq 32352 # Transaction distribution
1602system.cpu0.toL2Bus.trans_dist::WriteResp 32351 # Transaction distribution
1603system.cpu0.toL2Bus.trans_dist::WritebackDirty 5471965 # Transaction distribution
1604system.cpu0.toL2Bus.trans_dist::WritebackClean 8067317 # Transaction distribution
1605system.cpu0.toL2Bus.trans_dist::CleanEvict 2568559 # Transaction distribution
1606system.cpu0.toL2Bus.trans_dist::HardPFReq 991385 # Transaction distribution
--- 51 unchanged lines hidden (view full) ---
1658system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1659system.cpu1.branchPred.BTBHitPct 61.854242 # BTB Hit Percentage
1660system.cpu1.branchPred.usedRAS 17406269 # Number of times the RAS was used to get a target.
1661system.cpu1.branchPred.RASInCorrect 177185 # Number of incorrect RAS predictions.
1662system.cpu1.branchPred.indirectLookups 4036084 # Number of indirect predictor lookups.
1663system.cpu1.branchPred.indirectHits 2495247 # Number of indirect target hits.
1664system.cpu1.branchPred.indirectMisses 1540837 # Number of indirect misses.
1665system.cpu1.branchPredindirectMispredicted 386993 # Number of mispredicted indirect branches.
1666system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1667system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1668system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1669system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1670system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1671system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1672system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1673system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
1687system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1688system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1689system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1690system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1691system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1692system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1693system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1694system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1695system.cpu1.dtb.walker.walks 579824 # Table walker walks requested
1696system.cpu1.dtb.walker.walksLong 579824 # Table walker walks initiated with long descriptors
1697system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12232 # Level at which table walker walks with long descriptors terminate
1698system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93540 # Level at which table walker walks with long descriptors terminate
1699system.cpu1.dtb.walker.walksSquashedBefore 278610 # Table walks squashed before starting
1700system.cpu1.dtb.walker.walkWaitTime::samples 301214 # Table walker wait (enqueue to first request) latency
1701system.cpu1.dtb.walker.walkWaitTime::mean 2385.289196 # Table walker wait (enqueue to first request) latency
1702system.cpu1.dtb.walker.walkWaitTime::stdev 13264.000730 # Table walker wait (enqueue to first request) latency
--- 61 unchanged lines hidden (view full) ---
1764system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1765system.cpu1.dtb.perms_faults 38110 # Number of TLB faults due to permissions restrictions
1766system.cpu1.dtb.read_accesses 94516734 # DTB read accesses
1767system.cpu1.dtb.write_accesses 75895251 # DTB write accesses
1768system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1769system.cpu1.dtb.hits 169832161 # DTB hits
1770system.cpu1.dtb.misses 579824 # DTB misses
1771system.cpu1.dtb.accesses 170411985 # DTB accesses
1772system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1773system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1774system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1775system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1776system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1777system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1778system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1779system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
1793system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1794system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1795system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1796system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1797system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1798system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1799system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1800system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1801system.cpu1.itb.walker.walks 86146 # Table walker walks requested
1802system.cpu1.itb.walker.walksLong 86146 # Table walker walks initiated with long descriptors
1803system.cpu1.itb.walker.walksLongTerminationLevel::Level2 983 # Level at which table walker walks with long descriptors terminate
1804system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61109 # Level at which table walker walks with long descriptors terminate
1805system.cpu1.itb.walker.walksSquashedBefore 10267 # Table walks squashed before starting
1806system.cpu1.itb.walker.walkWaitTime::samples 75879 # Table walker wait (enqueue to first request) latency
1807system.cpu1.itb.walker.walkWaitTime::mean 1365.727013 # Table walker wait (enqueue to first request) latency
1808system.cpu1.itb.walker.walkWaitTime::stdev 9905.301438 # Table walker wait (enqueue to first request) latency
--- 61 unchanged lines hidden (view full) ---
1870system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1871system.cpu1.itb.perms_faults 205105 # Number of TLB faults due to permissions restrictions
1872system.cpu1.itb.read_accesses 0 # DTB read accesses
1873system.cpu1.itb.write_accesses 0 # DTB write accesses
1874system.cpu1.itb.inst_accesses 200266108 # ITB inst accesses
1875system.cpu1.itb.hits 200179962 # DTB hits
1876system.cpu1.itb.misses 86146 # DTB misses
1877system.cpu1.itb.accesses 200266108 # DTB accesses
1878system.cpu1.numCycles 683375860 # number of cpu cycles simulated
1879system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1880system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1881system.cpu1.fetch.icacheStallCycles 83886783 # Number of cycles fetch is stalled on an Icache miss
1882system.cpu1.fetch.Insts 563469851 # Number of instructions fetch has processed
1883system.cpu1.fetch.Branches 127244460 # Number of branches that fetch encountered
1884system.cpu1.fetch.predictedBranches 75441097 # Number of branches that fetch has predicted taken
1885system.cpu1.fetch.Cycles 564344995 # Number of cycles fetch has run and was not squashing or blocked
--- 279 unchanged lines hidden (view full) ---
2165system.cpu1.int_regfile_reads 639570382 # number of integer regfile reads
2166system.cpu1.int_regfile_writes 380109427 # number of integer regfile writes
2167system.cpu1.fp_regfile_reads 631427 # number of floating regfile reads
2168system.cpu1.fp_regfile_writes 338972 # number of floating regfile writes
2169system.cpu1.cc_regfile_reads 115255782 # number of cc regfile reads
2170system.cpu1.cc_regfile_writes 115917819 # number of cc regfile writes
2171system.cpu1.misc_regfile_reads 1185795918 # number of misc regfile reads
2172system.cpu1.misc_regfile_writes 15045931 # number of misc regfile writes
2173system.cpu1.dcache.tags.replacements 5420466 # number of replacements
2174system.cpu1.dcache.tags.tagsinuse 437.277482 # Cycle average of tags in use
2175system.cpu1.dcache.tags.total_refs 144971712 # Total number of references to valid blocks.
2176system.cpu1.dcache.tags.sampled_refs 5420977 # Sample count of references to valid blocks.
2177system.cpu1.dcache.tags.avg_refs 26.742728 # Average number of references to valid blocks.
2178system.cpu1.dcache.tags.warmup_cycle 8477404255000 # Cycle when the warmup percentage was hit.
2179system.cpu1.dcache.tags.occ_blocks::cpu1.data 437.277482 # Average occupied blocks per requestor
2180system.cpu1.dcache.tags.occ_percent::cpu1.data 0.854058 # Average percentage of cache occupancy
2181system.cpu1.dcache.tags.occ_percent::total 0.854058 # Average percentage of cache occupancy
2182system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
2183system.cpu1.dcache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id
2184system.cpu1.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id
2185system.cpu1.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id
2186system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
2187system.cpu1.dcache.tags.tag_accesses 323922794 # Number of tag accesses
2188system.cpu1.dcache.tags.data_accesses 323922794 # Number of data accesses
2189system.cpu1.dcache.ReadReq_hits::cpu1.data 76466425 # number of ReadReq hits
2190system.cpu1.dcache.ReadReq_hits::total 76466425 # number of ReadReq hits
2191system.cpu1.dcache.WriteReq_hits::cpu1.data 64110613 # number of WriteReq hits
2192system.cpu1.dcache.WriteReq_hits::total 64110613 # number of WriteReq hits
2193system.cpu1.dcache.SoftPFReq_hits::cpu1.data 170428 # number of SoftPFReq hits
2194system.cpu1.dcache.SoftPFReq_hits::total 170428 # number of SoftPFReq hits
2195system.cpu1.dcache.WriteLineReq_hits::cpu1.data 51164 # number of WriteLineReq hits
2196system.cpu1.dcache.WriteLineReq_hits::total 51164 # number of WriteLineReq hits
--- 182 unchanged lines hidden (view full) ---
2379system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16524.854161 # average overall mshr miss latency
2380system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16524.854161 # average overall mshr miss latency
2381system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17093.402169 # average overall mshr miss latency
2382system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17093.402169 # average overall mshr miss latency
2383system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122572.491010 # average ReadReq mshr uncacheable latency
2384system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 122572.491010 # average ReadReq mshr uncacheable latency
2385system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 60962.401431 # average overall mshr uncacheable latency
2386system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 60962.401431 # average overall mshr uncacheable latency
2387system.cpu1.icache.tags.replacements 5742782 # number of replacements
2388system.cpu1.icache.tags.tagsinuse 501.536552 # Cycle average of tags in use
2389system.cpu1.icache.tags.total_refs 193871102 # Total number of references to valid blocks.
2390system.cpu1.icache.tags.sampled_refs 5743294 # Sample count of references to valid blocks.
2391system.cpu1.icache.tags.avg_refs 33.756082 # Average number of references to valid blocks.
2392system.cpu1.icache.tags.warmup_cycle 8517126060000 # Cycle when the warmup percentage was hit.
2393system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.536552 # Average occupied blocks per requestor
2394system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979564 # Average percentage of cache occupancy
2395system.cpu1.icache.tags.occ_percent::total 0.979564 # Average percentage of cache occupancy
2396system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2397system.cpu1.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id
2398system.cpu1.icache.tags.age_task_id_blocks_1024::1 396 # Occupied blocks per task id
2399system.cpu1.icache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id
2400system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2401system.cpu1.icache.tags.tag_accesses 405638078 # Number of tag accesses
2402system.cpu1.icache.tags.data_accesses 405638078 # Number of data accesses
2403system.cpu1.icache.ReadReq_hits::cpu1.inst 193871102 # number of ReadReq hits
2404system.cpu1.icache.ReadReq_hits::total 193871102 # number of ReadReq hits
2405system.cpu1.icache.demand_hits::cpu1.inst 193871102 # number of demand (read+write) hits
2406system.cpu1.icache.demand_hits::total 193871102 # number of demand (read+write) hits
2407system.cpu1.icache.overall_hits::cpu1.inst 193871102 # number of overall hits
2408system.cpu1.icache.overall_hits::total 193871102 # number of overall hits
2409system.cpu1.icache.ReadReq_misses::cpu1.inst 6076268 # number of ReadReq misses
2410system.cpu1.icache.ReadReq_misses::total 6076268 # number of ReadReq misses
--- 70 unchanged lines hidden (view full) ---
2481system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency
2482system.cpu1.icache.demand_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency
2483system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency
2484system.cpu1.icache.overall_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency
2485system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average ReadReq mshr uncacheable latency
2486system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101335.791045 # average ReadReq mshr uncacheable latency
2487system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average overall mshr uncacheable latency
2488system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101335.791045 # average overall mshr uncacheable latency
2489system.cpu1.l2cache.prefetcher.num_hwpf_issued 7416585 # number of hwpf issued
2490system.cpu1.l2cache.prefetcher.pfIdentified 7422175 # number of prefetch candidates identified
2491system.cpu1.l2cache.prefetcher.pfBufferHit 5069 # number of redundant prefetches already in prefetch queue
2492system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
2493system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2494system.cpu1.l2cache.prefetcher.pfSpanPage 930081 # number of prefetches not generated due to page crossing
2495system.cpu1.l2cache.tags.replacements 2216875 # number of replacements
2496system.cpu1.l2cache.tags.tagsinuse 13443.573819 # Cycle average of tags in use
2497system.cpu1.l2cache.tags.total_refs 16807540 # Total number of references to valid blocks.
2498system.cpu1.l2cache.tags.sampled_refs 2232789 # Sample count of references to valid blocks.
2499system.cpu1.l2cache.tags.avg_refs 7.527599 # Average number of references to valid blocks.
2500system.cpu1.l2cache.tags.warmup_cycle 9871196159000 # Cycle when the warmup percentage was hit.
2501system.cpu1.l2cache.tags.occ_blocks::writebacks 12560.451650 # Average occupied blocks per requestor
2502system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 62.875087 # Average occupied blocks per requestor
--- 21 unchanged lines hidden (view full) ---
2524system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5623 # Occupied blocks per task id
2525system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4561 # Occupied blocks per task id
2526system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3143 # Occupied blocks per task id
2527system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080566 # Percentage of cache occupancy per task id
2528system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004089 # Percentage of cache occupancy per task id
2529system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.886658 # Percentage of cache occupancy per task id
2530system.cpu1.l2cache.tags.tag_accesses 383680582 # Number of tag accesses
2531system.cpu1.l2cache.tags.data_accesses 383680582 # Number of data accesses
2532system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 591753 # number of ReadReq hits
2533system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 193382 # number of ReadReq hits
2534system.cpu1.l2cache.ReadReq_hits::total 785135 # number of ReadReq hits
2535system.cpu1.l2cache.WritebackDirty_hits::writebacks 3353025 # number of WritebackDirty hits
2536system.cpu1.l2cache.WritebackDirty_hits::total 3353025 # number of WritebackDirty hits
2537system.cpu1.l2cache.WritebackClean_hits::writebacks 7809020 # number of WritebackClean hits
2538system.cpu1.l2cache.WritebackClean_hits::total 7809020 # number of WritebackClean hits
2539system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 779 # number of UpgradeReq hits
--- 338 unchanged lines hidden (view full) ---
2878system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 56971.628323 # average overall mshr uncacheable latency
2879system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 57171.248383 # average overall mshr uncacheable latency
2880system.cpu1.toL2Bus.snoop_filter.tot_requests 23197310 # Total number of requests made to the snoop filter.
2881system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11940096 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2882system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2883system.cpu1.toL2Bus.snoop_filter.tot_snoops 1942556 # Total number of snoops made to the snoop filter.
2884system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1942287 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2885system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 269 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2886system.cpu1.toL2Bus.trans_dist::ReadReq 900600 # Transaction distribution
2887system.cpu1.toL2Bus.trans_dist::ReadResp 10671947 # Transaction distribution
2888system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
2889system.cpu1.toL2Bus.trans_dist::WriteReq 6183 # Transaction distribution
2890system.cpu1.toL2Bus.trans_dist::WriteResp 6183 # Transaction distribution
2891system.cpu1.toL2Bus.trans_dist::WritebackDirty 4554023 # Transaction distribution
2892system.cpu1.toL2Bus.trans_dist::WritebackClean 7810324 # Transaction distribution
2893system.cpu1.toL2Bus.trans_dist::CleanEvict 2589255 # Transaction distribution
--- 39 unchanged lines hidden (view full) ---
2933system.cpu1.toL2Bus.respLayer0.occupancy 8621166733 # Layer occupancy (ticks)
2934system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2935system.cpu1.toL2Bus.respLayer1.occupancy 8059431425 # Layer occupancy (ticks)
2936system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2937system.cpu1.toL2Bus.respLayer2.occupancy 222762323 # Layer occupancy (ticks)
2938system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2939system.cpu1.toL2Bus.respLayer3.occupancy 672656647 # Layer occupancy (ticks)
2940system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2941system.iobus.trans_dist::ReadReq 40341 # Transaction distribution
2942system.iobus.trans_dist::ReadResp 40341 # Transaction distribution
2943system.iobus.trans_dist::WriteReq 136646 # Transaction distribution
2944system.iobus.trans_dist::WriteResp 136646 # Transaction distribution
2945system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47790 # Packet count per connected master and slave (bytes)
2946system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2947system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2948system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
--- 60 unchanged lines hidden (view full) ---
3009system.iobus.reqLayer25.occupancy 569028004 # Layer occupancy (ticks)
3010system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
3011system.iobus.respLayer0.occupancy 92757000 # Layer occupancy (ticks)
3012system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
3013system.iobus.respLayer3.occupancy 147918000 # Layer occupancy (ticks)
3014system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
3015system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
3016system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
3017system.iocache.tags.replacements 115592 # number of replacements
3018system.iocache.tags.tagsinuse 11.302694 # Cycle average of tags in use
3019system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
3020system.iocache.tags.sampled_refs 115608 # Sample count of references to valid blocks.
3021system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
3022system.iocache.tags.warmup_cycle 9115775800000 # Cycle when the warmup percentage was hit.
3023system.iocache.tags.occ_blocks::realview.ethernet 3.842796 # Average occupied blocks per requestor
3024system.iocache.tags.occ_blocks::realview.ide 7.459898 # Average occupied blocks per requestor
3025system.iocache.tags.occ_percent::realview.ethernet 0.240175 # Average percentage of cache occupancy
3026system.iocache.tags.occ_percent::realview.ide 0.466244 # Average percentage of cache occupancy
3027system.iocache.tags.occ_percent::total 0.706418 # Average percentage of cache occupancy
3028system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
3029system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
3030system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
3031system.iocache.tags.tag_accesses 1040856 # Number of tag accesses
3032system.iocache.tags.data_accesses 1040856 # Number of data accesses
3033system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
3034system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses
3035system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses
3036system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
3037system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
3038system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
3039system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
3040system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
--- 109 unchanged lines hidden (view full) ---
3150system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71315.017493 # average WriteLineReq mshr miss latency
3151system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71315.017493 # average WriteLineReq mshr miss latency
3152system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency
3153system.iocache.demand_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency
3154system.iocache.demand_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency
3155system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency
3156system.iocache.overall_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency
3157system.iocache.overall_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency
3158system.l2c.tags.replacements 1423185 # number of replacements
3159system.l2c.tags.tagsinuse 63448.336905 # Cycle average of tags in use
3160system.l2c.tags.total_refs 6060449 # Total number of references to valid blocks.
3161system.l2c.tags.sampled_refs 1482600 # Sample count of references to valid blocks.
3162system.l2c.tags.avg_refs 4.087717 # Average number of references to valid blocks.
3163system.l2c.tags.warmup_cycle 3022937500 # Cycle when the warmup percentage was hit.
3164system.l2c.tags.occ_blocks::writebacks 20826.975184 # Average occupied blocks per requestor
3165system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.832374 # Average occupied blocks per requestor
--- 33 unchanged lines hidden (view full) ---
3199system.l2c.tags.age_task_id_blocks_1024::2 2760 # Occupied blocks per task id
3200system.l2c.tags.age_task_id_blocks_1024::3 5614 # Occupied blocks per task id
3201system.l2c.tags.age_task_id_blocks_1024::4 39761 # Occupied blocks per task id
3202system.l2c.tags.occ_task_id_percent::1022 0.163300 # Percentage of cache occupancy per task id
3203system.l2c.tags.occ_task_id_percent::1023 0.003387 # Percentage of cache occupancy per task id
3204system.l2c.tags.occ_task_id_percent::1024 0.739914 # Percentage of cache occupancy per task id
3205system.l2c.tags.tag_accesses 76659871 # Number of tag accesses
3206system.l2c.tags.data_accesses 76659871 # Number of data accesses
3207system.l2c.WritebackDirty_hits::writebacks 2799563 # number of WritebackDirty hits
3208system.l2c.WritebackDirty_hits::total 2799563 # number of WritebackDirty hits
3209system.l2c.UpgradeReq_hits::cpu0.data 175772 # number of UpgradeReq hits
3210system.l2c.UpgradeReq_hits::cpu1.data 127713 # number of UpgradeReq hits
3211system.l2c.UpgradeReq_hits::total 303485 # number of UpgradeReq hits
3212system.l2c.SCUpgradeReq_hits::cpu0.data 39800 # number of SCUpgradeReq hits
3213system.l2c.SCUpgradeReq_hits::cpu1.data 41169 # number of SCUpgradeReq hits
3214system.l2c.SCUpgradeReq_hits::total 80969 # number of SCUpgradeReq hits
--- 504 unchanged lines hidden (view full) ---
3719system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 48017.521994 # average overall mshr uncacheable latency
3720system.l2c.overall_avg_mshr_uncacheable_latency::total 74089.494383 # average overall mshr uncacheable latency
3721system.membus.snoop_filter.tot_requests 3952559 # Total number of requests made to the snoop filter.
3722system.membus.snoop_filter.hit_single_requests 2414080 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3723system.membus.snoop_filter.hit_multi_requests 2931 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3724system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
3725system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3726system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3727system.membus.trans_dist::ReadReq 60003 # Transaction distribution
3728system.membus.trans_dist::ReadResp 904829 # Transaction distribution
3729system.membus.trans_dist::WriteReq 38534 # Transaction distribution
3730system.membus.trans_dist::WriteResp 38534 # Transaction distribution
3731system.membus.trans_dist::WritebackDirty 1242017 # Transaction distribution
3732system.membus.trans_dist::CleanEvict 238236 # Transaction distribution
3733system.membus.trans_dist::UpgradeReq 446737 # Transaction distribution
3734system.membus.trans_dist::SCUpgradeReq 299659 # Transaction distribution
--- 38 unchanged lines hidden (view full) ---
3773system.membus.reqLayer2.occupancy 22248500 # Layer occupancy (ticks)
3774system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3775system.membus.reqLayer5.occupancy 8723892621 # Layer occupancy (ticks)
3776system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3777system.membus.respLayer2.occupancy 5223815230 # Layer occupancy (ticks)
3778system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3779system.membus.respLayer3.occupancy 45514707 # Layer occupancy (ticks)
3780system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3781system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3782system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3783system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3784system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3785system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3786system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3787system.realview.ethernet.txBytes 966 # Bytes Transmitted
3788system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3789system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3790system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3791system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3792system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3793system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
3794system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
--- 26 unchanged lines hidden (view full) ---
3821system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
3822system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3823system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3824system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
3825system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3826system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3827system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3828system.realview.ethernet.droppedPackets 0 # number of packets dropped
3829system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3830system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3831system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3832system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3833system.toL2Bus.snoop_filter.tot_requests 11842018 # Total number of requests made to the snoop filter.
3834system.toL2Bus.snoop_filter.hit_single_requests 6441759 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3835system.toL2Bus.snoop_filter.hit_multi_requests 1913591 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3836system.toL2Bus.snoop_filter.tot_snoops 133722 # Total number of snoops made to the snoop filter.
3837system.toL2Bus.snoop_filter.hit_single_snoops 121814 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3838system.toL2Bus.snoop_filter.hit_multi_snoops 11908 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3839system.toL2Bus.trans_dist::ReadReq 60005 # Transaction distribution
3840system.toL2Bus.trans_dist::ReadResp 4492996 # Transaction distribution
3841system.toL2Bus.trans_dist::WriteReq 38534 # Transaction distribution
3842system.toL2Bus.trans_dist::WriteResp 38534 # Transaction distribution
3843system.toL2Bus.trans_dist::WritebackDirty 3934886 # Transaction distribution
3844system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
3845system.toL2Bus.trans_dist::CleanEvict 2625367 # Transaction distribution
3846system.toL2Bus.trans_dist::UpgradeReq 741215 # Transaction distribution
--- 41 unchanged lines hidden ---
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.384315 # Number of seconds simulated
4sim_ticks 47384315163000 # Number of ticks simulated
5final_tick 47384315163000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 172390 # Simulator instruction rate (inst/s)
8host_op_rate 202727 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 9043218476 # Simulator tick rate (ticks/s)
10host_mem_usage 765852 # Number of bytes of host memory used
11host_seconds 5239.76 # Real time elapsed on the host
12sim_insts 903281747 # Number of instructions simulated
13sim_ops 1062243320 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 88320 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 58304 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 4233376 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 12825352 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 13896960 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 201536 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 189312 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 2647264 # Number of bytes read from this memory
--- 289 unchanged lines hidden (view full) ---
313system.physmem_1.preBackEnergy 27415968105750 # Energy for precharge background per rank (pJ)
314system.physmem_1.totalEnergy 31681249248975 # Total energy per rank (pJ)
315system.physmem_1.averagePower 668.602035 # Core power per rank (mW)
316system.physmem_1.memoryStateTime::IDLE 45608919765384 # Time in different power states
317system.physmem_1.memoryStateTime::REF 1582266400000 # Time in different power states
318system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
319system.physmem_1.memoryStateTime::ACT 193128558366 # Time in different power states
320system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
321system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory
322system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
323system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
324system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
325system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory
326system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory
327system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory
328system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory
--- 10 unchanged lines hidden (view full) ---
339system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
340system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s)
341system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s)
342system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
343system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
344system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s)
345system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
346system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
347system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
348system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
349system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
350system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
351system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
352system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
353system.cpu0.branchPred.lookups 138091637 # Number of BP lookups
354system.cpu0.branchPred.condPredicted 91311717 # Number of conditional branches predicted
--- 4 unchanged lines hidden (view full) ---
359system.cpu0.branchPred.BTBHitPct 61.575961 # BTB Hit Percentage
360system.cpu0.branchPred.usedRAS 18644167 # Number of times the RAS was used to get a target.
361system.cpu0.branchPred.RASInCorrect 188685 # Number of incorrect RAS predictions.
362system.cpu0.branchPred.indirectLookups 4389066 # Number of indirect predictor lookups.
363system.cpu0.branchPred.indirectHits 2747803 # Number of indirect target hits.
364system.cpu0.branchPred.indirectMisses 1641263 # Number of indirect misses.
365system.cpu0.branchPredindirectMispredicted 409141 # Number of mispredicted indirect branches.
366system.cpu_clk_domain.clock 500 # Clock period in ticks
367system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
368system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
369system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
370system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
371system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
372system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
373system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
374system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
388system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
389system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
390system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
391system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
392system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
393system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
394system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
395system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
396system.cpu0.dtb.walker.walks 530338 # Table walker walks requested
397system.cpu0.dtb.walker.walksLong 530338 # Table walker walks initiated with long descriptors
398system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10426 # Level at which table walker walks with long descriptors terminate
399system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 79784 # Level at which table walker walks with long descriptors terminate
400system.cpu0.dtb.walker.walksSquashedBefore 241995 # Table walks squashed before starting
401system.cpu0.dtb.walker.walkWaitTime::samples 288343 # Table walker wait (enqueue to first request) latency
402system.cpu0.dtb.walker.walkWaitTime::mean 2099.123266 # Table walker wait (enqueue to first request) latency
403system.cpu0.dtb.walker.walkWaitTime::stdev 12230.418976 # Table walker wait (enqueue to first request) latency
--- 66 unchanged lines hidden (view full) ---
470system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
471system.cpu0.dtb.perms_faults 39704 # Number of TLB faults due to permissions restrictions
472system.cpu0.dtb.read_accesses 100057654 # DTB read accesses
473system.cpu0.dtb.write_accesses 83209467 # DTB write accesses
474system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
475system.cpu0.dtb.hits 182736783 # DTB hits
476system.cpu0.dtb.misses 530338 # DTB misses
477system.cpu0.dtb.accesses 183267121 # DTB accesses
478system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
479system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
480system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
481system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
499system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
500system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
501system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
502system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
503system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
504system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
505system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
506system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
507system.cpu0.itb.walker.walks 81834 # Table walker walks requested
508system.cpu0.itb.walker.walksLong 81834 # Table walker walks initiated with long descriptors
509system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1030 # Level at which table walker walks with long descriptors terminate
510system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58824 # Level at which table walker walks with long descriptors terminate
511system.cpu0.itb.walker.walksSquashedBefore 9805 # Table walks squashed before starting
512system.cpu0.itb.walker.walkWaitTime::samples 72029 # Table walker wait (enqueue to first request) latency
513system.cpu0.itb.walker.walkWaitTime::mean 864.033931 # Table walker wait (enqueue to first request) latency
514system.cpu0.itb.walker.walkWaitTime::stdev 6165.525550 # Table walker wait (enqueue to first request) latency
--- 64 unchanged lines hidden (view full) ---
579system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
580system.cpu0.itb.perms_faults 198402 # Number of TLB faults due to permissions restrictions
581system.cpu0.itb.read_accesses 0 # DTB read accesses
582system.cpu0.itb.write_accesses 0 # DTB write accesses
583system.cpu0.itb.inst_accesses 216603307 # ITB inst accesses
584system.cpu0.itb.hits 216521473 # DTB hits
585system.cpu0.itb.misses 81834 # DTB misses
586system.cpu0.itb.accesses 216603307 # DTB accesses
587system.cpu0.numCycles 746014900 # number of cpu cycles simulated
588system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
589system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
590system.cpu0.fetch.icacheStallCycles 90433879 # Number of cycles fetch is stalled on an Icache miss
591system.cpu0.fetch.Insts 610172736 # Number of instructions fetch has processed
592system.cpu0.fetch.Branches 138091637 # Number of branches that fetch encountered
593system.cpu0.fetch.predictedBranches 81258280 # Number of branches that fetch has predicted taken
594system.cpu0.fetch.Cycles 615398287 # Number of cycles fetch has run and was not squashing or blocked
--- 279 unchanged lines hidden (view full) ---
874system.cpu0.int_regfile_reads 694459704 # number of integer regfile reads
875system.cpu0.int_regfile_writes 413089219 # number of integer regfile writes
876system.cpu0.fp_regfile_reads 846069 # number of floating regfile reads
877system.cpu0.fp_regfile_writes 429660 # number of floating regfile writes
878system.cpu0.cc_regfile_reads 127998327 # number of cc regfile reads
879system.cpu0.cc_regfile_writes 128742208 # number of cc regfile writes
880system.cpu0.misc_regfile_reads 1288788249 # number of misc regfile reads
881system.cpu0.misc_regfile_writes 14832406 # number of misc regfile writes
882system.cpu0.dcache.tags.replacements 5793916 # number of replacements
883system.cpu0.dcache.tags.tagsinuse 505.305765 # Cycle average of tags in use
884system.cpu0.dcache.tags.total_refs 157106373 # Total number of references to valid blocks.
885system.cpu0.dcache.tags.sampled_refs 5794427 # Sample count of references to valid blocks.
886system.cpu0.dcache.tags.avg_refs 27.113358 # Average number of references to valid blocks.
887system.cpu0.dcache.tags.warmup_cycle 1908955000 # Cycle when the warmup percentage was hit.
888system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.305765 # Average occupied blocks per requestor
889system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986925 # Average percentage of cache occupancy
890system.cpu0.dcache.tags.occ_percent::total 0.986925 # Average percentage of cache occupancy
891system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
892system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
893system.cpu0.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id
894system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
895system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
896system.cpu0.dcache.tags.tag_accesses 349540400 # Number of tag accesses
897system.cpu0.dcache.tags.data_accesses 349540400 # Number of data accesses
898system.cpu0.dcache.ReadReq_hits::cpu0.data 81616032 # number of ReadReq hits
899system.cpu0.dcache.ReadReq_hits::total 81616032 # number of ReadReq hits
900system.cpu0.dcache.WriteReq_hits::cpu0.data 70522769 # number of WriteReq hits
901system.cpu0.dcache.WriteReq_hits::total 70522769 # number of WriteReq hits
902system.cpu0.dcache.SoftPFReq_hits::cpu0.data 213045 # number of SoftPFReq hits
903system.cpu0.dcache.SoftPFReq_hits::total 213045 # number of SoftPFReq hits
904system.cpu0.dcache.WriteLineReq_hits::cpu0.data 259663 # number of WriteLineReq hits
905system.cpu0.dcache.WriteLineReq_hits::total 259663 # number of WriteLineReq hits
--- 182 unchanged lines hidden (view full) ---
1088system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19061.608373 # average overall mshr miss latency
1089system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19061.608373 # average overall mshr miss latency
1090system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19427.364492 # average overall mshr miss latency
1091system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19427.364492 # average overall mshr miss latency
1092system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 190877.363421 # average ReadReq mshr uncacheable latency
1093system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 190877.363421 # average ReadReq mshr uncacheable latency
1094system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 95697.586239 # average overall mshr uncacheable latency
1095system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 95697.586239 # average overall mshr uncacheable latency
1096system.cpu0.icache.tags.replacements 6136519 # number of replacements
1097system.cpu0.icache.tags.tagsinuse 511.962391 # Cycle average of tags in use
1098system.cpu0.icache.tags.total_refs 209807209 # Total number of references to valid blocks.
1099system.cpu0.icache.tags.sampled_refs 6137031 # Sample count of references to valid blocks.
1100system.cpu0.icache.tags.avg_refs 34.187086 # Average number of references to valid blocks.
1101system.cpu0.icache.tags.warmup_cycle 12886295000 # Cycle when the warmup percentage was hit.
1102system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.962391 # Average occupied blocks per requestor
1103system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999927 # Average percentage of cache occupancy
1104system.cpu0.icache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy
1105system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1106system.cpu0.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id
1107system.cpu0.icache.tags.age_task_id_blocks_1024::1 352 # Occupied blocks per task id
1108system.cpu0.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id
1109system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1110system.cpu0.icache.tags.tag_accesses 438728804 # Number of tag accesses
1111system.cpu0.icache.tags.data_accesses 438728804 # Number of data accesses
1112system.cpu0.icache.ReadReq_hits::cpu0.inst 209807209 # number of ReadReq hits
1113system.cpu0.icache.ReadReq_hits::total 209807209 # number of ReadReq hits
1114system.cpu0.icache.demand_hits::cpu0.inst 209807209 # number of demand (read+write) hits
1115system.cpu0.icache.demand_hits::total 209807209 # number of demand (read+write) hits
1116system.cpu0.icache.overall_hits::cpu0.inst 209807209 # number of overall hits
1117system.cpu0.icache.overall_hits::total 209807209 # number of overall hits
1118system.cpu0.icache.ReadReq_misses::cpu0.inst 6488653 # number of ReadReq misses
1119system.cpu0.icache.ReadReq_misses::total 6488653 # number of ReadReq misses
--- 70 unchanged lines hidden (view full) ---
1190system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency
1191system.cpu0.icache.demand_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency
1192system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10263.003193 # average overall mshr miss latency
1193system.cpu0.icache.overall_avg_mshr_miss_latency::total 10263.003193 # average overall mshr miss latency
1194system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average ReadReq mshr uncacheable latency
1195system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753 # average ReadReq mshr uncacheable latency
1196system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average overall mshr uncacheable latency
1197system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753 # average overall mshr uncacheable latency
1198system.cpu0.l2cache.prefetcher.num_hwpf_issued 7743703 # number of hwpf issued
1199system.cpu0.l2cache.prefetcher.pfIdentified 7754051 # number of prefetch candidates identified
1200system.cpu0.l2cache.prefetcher.pfBufferHit 9277 # number of redundant prefetches already in prefetch queue
1201system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1202system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1203system.cpu0.l2cache.prefetcher.pfSpanPage 1008365 # number of prefetches not generated due to page crossing
1204system.cpu0.l2cache.tags.replacements 2565485 # number of replacements
1205system.cpu0.l2cache.tags.tagsinuse 15956.741738 # Cycle average of tags in use
1206system.cpu0.l2cache.tags.total_refs 17408441 # Total number of references to valid blocks.
1207system.cpu0.l2cache.tags.sampled_refs 2581334 # Sample count of references to valid blocks.
1208system.cpu0.l2cache.tags.avg_refs 6.743971 # Average number of references to valid blocks.
1209system.cpu0.l2cache.tags.warmup_cycle 2212473000 # Cycle when the warmup percentage was hit.
1210system.cpu0.l2cache.tags.occ_blocks::writebacks 14849.648482 # Average occupied blocks per requestor
1211system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 36.124813 # Average occupied blocks per requestor
--- 21 unchanged lines hidden (view full) ---
1233system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4722 # Occupied blocks per task id
1234system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4695 # Occupied blocks per task id
1235system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3741 # Occupied blocks per task id
1236system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.073425 # Percentage of cache occupancy per task id
1237system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004700 # Percentage of cache occupancy per task id
1238system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.889221 # Percentage of cache occupancy per task id
1239system.cpu0.l2cache.tags.tag_accesses 408243228 # Number of tag accesses
1240system.cpu0.l2cache.tags.data_accesses 408243228 # Number of data accesses
1241system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 539952 # number of ReadReq hits
1242system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 183800 # number of ReadReq hits
1243system.cpu0.l2cache.ReadReq_hits::total 723752 # number of ReadReq hits
1244system.cpu0.l2cache.WritebackDirty_hits::writebacks 3863126 # number of WritebackDirty hits
1245system.cpu0.l2cache.WritebackDirty_hits::total 3863126 # number of WritebackDirty hits
1246system.cpu0.l2cache.WritebackClean_hits::writebacks 8065215 # number of WritebackClean hits
1247system.cpu0.l2cache.WritebackClean_hits::total 8065215 # number of WritebackClean hits
1248system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 386 # number of UpgradeReq hits
--- 342 unchanged lines hidden (view full) ---
1591system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 91677.525509 # average overall mshr uncacheable latency
1592system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89053.550498 # average overall mshr uncacheable latency
1593system.cpu0.toL2Bus.snoop_filter.tot_requests 24754475 # Total number of requests made to the snoop filter.
1594system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12719207 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1595system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2136 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1596system.cpu0.toL2Bus.snoop_filter.tot_snoops 1997962 # Total number of snoops made to the snoop filter.
1597system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 1997498 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1598system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 464 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1599system.cpu0.toL2Bus.trans_dist::ReadReq 885324 # Transaction distribution
1600system.cpu0.toL2Bus.trans_dist::ReadResp 11040535 # Transaction distribution
1601system.cpu0.toL2Bus.trans_dist::WriteReq 32352 # Transaction distribution
1602system.cpu0.toL2Bus.trans_dist::WriteResp 32351 # Transaction distribution
1603system.cpu0.toL2Bus.trans_dist::WritebackDirty 5471965 # Transaction distribution
1604system.cpu0.toL2Bus.trans_dist::WritebackClean 8067317 # Transaction distribution
1605system.cpu0.toL2Bus.trans_dist::CleanEvict 2568559 # Transaction distribution
1606system.cpu0.toL2Bus.trans_dist::HardPFReq 991385 # Transaction distribution
--- 51 unchanged lines hidden (view full) ---
1658system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1659system.cpu1.branchPred.BTBHitPct 61.854242 # BTB Hit Percentage
1660system.cpu1.branchPred.usedRAS 17406269 # Number of times the RAS was used to get a target.
1661system.cpu1.branchPred.RASInCorrect 177185 # Number of incorrect RAS predictions.
1662system.cpu1.branchPred.indirectLookups 4036084 # Number of indirect predictor lookups.
1663system.cpu1.branchPred.indirectHits 2495247 # Number of indirect target hits.
1664system.cpu1.branchPred.indirectMisses 1540837 # Number of indirect misses.
1665system.cpu1.branchPredindirectMispredicted 386993 # Number of mispredicted indirect branches.
1666system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1667system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1668system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1669system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1670system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1671system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1672system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1673system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
1687system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1688system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1689system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1690system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1691system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1692system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1693system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1694system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1695system.cpu1.dtb.walker.walks 579824 # Table walker walks requested
1696system.cpu1.dtb.walker.walksLong 579824 # Table walker walks initiated with long descriptors
1697system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12232 # Level at which table walker walks with long descriptors terminate
1698system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93540 # Level at which table walker walks with long descriptors terminate
1699system.cpu1.dtb.walker.walksSquashedBefore 278610 # Table walks squashed before starting
1700system.cpu1.dtb.walker.walkWaitTime::samples 301214 # Table walker wait (enqueue to first request) latency
1701system.cpu1.dtb.walker.walkWaitTime::mean 2385.289196 # Table walker wait (enqueue to first request) latency
1702system.cpu1.dtb.walker.walkWaitTime::stdev 13264.000730 # Table walker wait (enqueue to first request) latency
--- 61 unchanged lines hidden (view full) ---
1764system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1765system.cpu1.dtb.perms_faults 38110 # Number of TLB faults due to permissions restrictions
1766system.cpu1.dtb.read_accesses 94516734 # DTB read accesses
1767system.cpu1.dtb.write_accesses 75895251 # DTB write accesses
1768system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1769system.cpu1.dtb.hits 169832161 # DTB hits
1770system.cpu1.dtb.misses 579824 # DTB misses
1771system.cpu1.dtb.accesses 170411985 # DTB accesses
1772system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1773system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1774system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1775system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1776system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1777system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1778system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1779system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
--- 13 unchanged lines hidden (view full) ---
1793system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1794system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1795system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1796system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1797system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1798system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1799system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1800system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1801system.cpu1.itb.walker.walks 86146 # Table walker walks requested
1802system.cpu1.itb.walker.walksLong 86146 # Table walker walks initiated with long descriptors
1803system.cpu1.itb.walker.walksLongTerminationLevel::Level2 983 # Level at which table walker walks with long descriptors terminate
1804system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61109 # Level at which table walker walks with long descriptors terminate
1805system.cpu1.itb.walker.walksSquashedBefore 10267 # Table walks squashed before starting
1806system.cpu1.itb.walker.walkWaitTime::samples 75879 # Table walker wait (enqueue to first request) latency
1807system.cpu1.itb.walker.walkWaitTime::mean 1365.727013 # Table walker wait (enqueue to first request) latency
1808system.cpu1.itb.walker.walkWaitTime::stdev 9905.301438 # Table walker wait (enqueue to first request) latency
--- 61 unchanged lines hidden (view full) ---
1870system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1871system.cpu1.itb.perms_faults 205105 # Number of TLB faults due to permissions restrictions
1872system.cpu1.itb.read_accesses 0 # DTB read accesses
1873system.cpu1.itb.write_accesses 0 # DTB write accesses
1874system.cpu1.itb.inst_accesses 200266108 # ITB inst accesses
1875system.cpu1.itb.hits 200179962 # DTB hits
1876system.cpu1.itb.misses 86146 # DTB misses
1877system.cpu1.itb.accesses 200266108 # DTB accesses
1878system.cpu1.numCycles 683375860 # number of cpu cycles simulated
1879system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1880system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1881system.cpu1.fetch.icacheStallCycles 83886783 # Number of cycles fetch is stalled on an Icache miss
1882system.cpu1.fetch.Insts 563469851 # Number of instructions fetch has processed
1883system.cpu1.fetch.Branches 127244460 # Number of branches that fetch encountered
1884system.cpu1.fetch.predictedBranches 75441097 # Number of branches that fetch has predicted taken
1885system.cpu1.fetch.Cycles 564344995 # Number of cycles fetch has run and was not squashing or blocked
--- 279 unchanged lines hidden (view full) ---
2165system.cpu1.int_regfile_reads 639570382 # number of integer regfile reads
2166system.cpu1.int_regfile_writes 380109427 # number of integer regfile writes
2167system.cpu1.fp_regfile_reads 631427 # number of floating regfile reads
2168system.cpu1.fp_regfile_writes 338972 # number of floating regfile writes
2169system.cpu1.cc_regfile_reads 115255782 # number of cc regfile reads
2170system.cpu1.cc_regfile_writes 115917819 # number of cc regfile writes
2171system.cpu1.misc_regfile_reads 1185795918 # number of misc regfile reads
2172system.cpu1.misc_regfile_writes 15045931 # number of misc regfile writes
2173system.cpu1.dcache.tags.replacements 5420466 # number of replacements
2174system.cpu1.dcache.tags.tagsinuse 437.277482 # Cycle average of tags in use
2175system.cpu1.dcache.tags.total_refs 144971712 # Total number of references to valid blocks.
2176system.cpu1.dcache.tags.sampled_refs 5420977 # Sample count of references to valid blocks.
2177system.cpu1.dcache.tags.avg_refs 26.742728 # Average number of references to valid blocks.
2178system.cpu1.dcache.tags.warmup_cycle 8477404255000 # Cycle when the warmup percentage was hit.
2179system.cpu1.dcache.tags.occ_blocks::cpu1.data 437.277482 # Average occupied blocks per requestor
2180system.cpu1.dcache.tags.occ_percent::cpu1.data 0.854058 # Average percentage of cache occupancy
2181system.cpu1.dcache.tags.occ_percent::total 0.854058 # Average percentage of cache occupancy
2182system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
2183system.cpu1.dcache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id
2184system.cpu1.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id
2185system.cpu1.dcache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id
2186system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
2187system.cpu1.dcache.tags.tag_accesses 323922794 # Number of tag accesses
2188system.cpu1.dcache.tags.data_accesses 323922794 # Number of data accesses
2189system.cpu1.dcache.ReadReq_hits::cpu1.data 76466425 # number of ReadReq hits
2190system.cpu1.dcache.ReadReq_hits::total 76466425 # number of ReadReq hits
2191system.cpu1.dcache.WriteReq_hits::cpu1.data 64110613 # number of WriteReq hits
2192system.cpu1.dcache.WriteReq_hits::total 64110613 # number of WriteReq hits
2193system.cpu1.dcache.SoftPFReq_hits::cpu1.data 170428 # number of SoftPFReq hits
2194system.cpu1.dcache.SoftPFReq_hits::total 170428 # number of SoftPFReq hits
2195system.cpu1.dcache.WriteLineReq_hits::cpu1.data 51164 # number of WriteLineReq hits
2196system.cpu1.dcache.WriteLineReq_hits::total 51164 # number of WriteLineReq hits
--- 182 unchanged lines hidden (view full) ---
2379system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16524.854161 # average overall mshr miss latency
2380system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16524.854161 # average overall mshr miss latency
2381system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17093.402169 # average overall mshr miss latency
2382system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17093.402169 # average overall mshr miss latency
2383system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122572.491010 # average ReadReq mshr uncacheable latency
2384system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 122572.491010 # average ReadReq mshr uncacheable latency
2385system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 60962.401431 # average overall mshr uncacheable latency
2386system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 60962.401431 # average overall mshr uncacheable latency
2387system.cpu1.icache.tags.replacements 5742782 # number of replacements
2388system.cpu1.icache.tags.tagsinuse 501.536552 # Cycle average of tags in use
2389system.cpu1.icache.tags.total_refs 193871102 # Total number of references to valid blocks.
2390system.cpu1.icache.tags.sampled_refs 5743294 # Sample count of references to valid blocks.
2391system.cpu1.icache.tags.avg_refs 33.756082 # Average number of references to valid blocks.
2392system.cpu1.icache.tags.warmup_cycle 8517126060000 # Cycle when the warmup percentage was hit.
2393system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.536552 # Average occupied blocks per requestor
2394system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979564 # Average percentage of cache occupancy
2395system.cpu1.icache.tags.occ_percent::total 0.979564 # Average percentage of cache occupancy
2396system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2397system.cpu1.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id
2398system.cpu1.icache.tags.age_task_id_blocks_1024::1 396 # Occupied blocks per task id
2399system.cpu1.icache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id
2400system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2401system.cpu1.icache.tags.tag_accesses 405638078 # Number of tag accesses
2402system.cpu1.icache.tags.data_accesses 405638078 # Number of data accesses
2403system.cpu1.icache.ReadReq_hits::cpu1.inst 193871102 # number of ReadReq hits
2404system.cpu1.icache.ReadReq_hits::total 193871102 # number of ReadReq hits
2405system.cpu1.icache.demand_hits::cpu1.inst 193871102 # number of demand (read+write) hits
2406system.cpu1.icache.demand_hits::total 193871102 # number of demand (read+write) hits
2407system.cpu1.icache.overall_hits::cpu1.inst 193871102 # number of overall hits
2408system.cpu1.icache.overall_hits::total 193871102 # number of overall hits
2409system.cpu1.icache.ReadReq_misses::cpu1.inst 6076268 # number of ReadReq misses
2410system.cpu1.icache.ReadReq_misses::total 6076268 # number of ReadReq misses
--- 70 unchanged lines hidden (view full) ---
2481system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency
2482system.cpu1.icache.demand_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency
2483system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10127.714850 # average overall mshr miss latency
2484system.cpu1.icache.overall_avg_mshr_miss_latency::total 10127.714850 # average overall mshr miss latency
2485system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average ReadReq mshr uncacheable latency
2486system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101335.791045 # average ReadReq mshr uncacheable latency
2487system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101335.791045 # average overall mshr uncacheable latency
2488system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101335.791045 # average overall mshr uncacheable latency
2489system.cpu1.l2cache.prefetcher.num_hwpf_issued 7416585 # number of hwpf issued
2490system.cpu1.l2cache.prefetcher.pfIdentified 7422175 # number of prefetch candidates identified
2491system.cpu1.l2cache.prefetcher.pfBufferHit 5069 # number of redundant prefetches already in prefetch queue
2492system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
2493system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2494system.cpu1.l2cache.prefetcher.pfSpanPage 930081 # number of prefetches not generated due to page crossing
2495system.cpu1.l2cache.tags.replacements 2216875 # number of replacements
2496system.cpu1.l2cache.tags.tagsinuse 13443.573819 # Cycle average of tags in use
2497system.cpu1.l2cache.tags.total_refs 16807540 # Total number of references to valid blocks.
2498system.cpu1.l2cache.tags.sampled_refs 2232789 # Sample count of references to valid blocks.
2499system.cpu1.l2cache.tags.avg_refs 7.527599 # Average number of references to valid blocks.
2500system.cpu1.l2cache.tags.warmup_cycle 9871196159000 # Cycle when the warmup percentage was hit.
2501system.cpu1.l2cache.tags.occ_blocks::writebacks 12560.451650 # Average occupied blocks per requestor
2502system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 62.875087 # Average occupied blocks per requestor
--- 21 unchanged lines hidden (view full) ---
2524system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5623 # Occupied blocks per task id
2525system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4561 # Occupied blocks per task id
2526system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3143 # Occupied blocks per task id
2527system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.080566 # Percentage of cache occupancy per task id
2528system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004089 # Percentage of cache occupancy per task id
2529system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.886658 # Percentage of cache occupancy per task id
2530system.cpu1.l2cache.tags.tag_accesses 383680582 # Number of tag accesses
2531system.cpu1.l2cache.tags.data_accesses 383680582 # Number of data accesses
2532system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 591753 # number of ReadReq hits
2533system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 193382 # number of ReadReq hits
2534system.cpu1.l2cache.ReadReq_hits::total 785135 # number of ReadReq hits
2535system.cpu1.l2cache.WritebackDirty_hits::writebacks 3353025 # number of WritebackDirty hits
2536system.cpu1.l2cache.WritebackDirty_hits::total 3353025 # number of WritebackDirty hits
2537system.cpu1.l2cache.WritebackClean_hits::writebacks 7809020 # number of WritebackClean hits
2538system.cpu1.l2cache.WritebackClean_hits::total 7809020 # number of WritebackClean hits
2539system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 779 # number of UpgradeReq hits
--- 338 unchanged lines hidden (view full) ---
2878system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 56971.628323 # average overall mshr uncacheable latency
2879system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 57171.248383 # average overall mshr uncacheable latency
2880system.cpu1.toL2Bus.snoop_filter.tot_requests 23197310 # Total number of requests made to the snoop filter.
2881system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11940096 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2882system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1305 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2883system.cpu1.toL2Bus.snoop_filter.tot_snoops 1942556 # Total number of snoops made to the snoop filter.
2884system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1942287 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2885system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 269 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2886system.cpu1.toL2Bus.trans_dist::ReadReq 900600 # Transaction distribution
2887system.cpu1.toL2Bus.trans_dist::ReadResp 10671947 # Transaction distribution
2888system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
2889system.cpu1.toL2Bus.trans_dist::WriteReq 6183 # Transaction distribution
2890system.cpu1.toL2Bus.trans_dist::WriteResp 6183 # Transaction distribution
2891system.cpu1.toL2Bus.trans_dist::WritebackDirty 4554023 # Transaction distribution
2892system.cpu1.toL2Bus.trans_dist::WritebackClean 7810324 # Transaction distribution
2893system.cpu1.toL2Bus.trans_dist::CleanEvict 2589255 # Transaction distribution
--- 39 unchanged lines hidden (view full) ---
2933system.cpu1.toL2Bus.respLayer0.occupancy 8621166733 # Layer occupancy (ticks)
2934system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2935system.cpu1.toL2Bus.respLayer1.occupancy 8059431425 # Layer occupancy (ticks)
2936system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2937system.cpu1.toL2Bus.respLayer2.occupancy 222762323 # Layer occupancy (ticks)
2938system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2939system.cpu1.toL2Bus.respLayer3.occupancy 672656647 # Layer occupancy (ticks)
2940system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2941system.iobus.trans_dist::ReadReq 40341 # Transaction distribution
2942system.iobus.trans_dist::ReadResp 40341 # Transaction distribution
2943system.iobus.trans_dist::WriteReq 136646 # Transaction distribution
2944system.iobus.trans_dist::WriteResp 136646 # Transaction distribution
2945system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47790 # Packet count per connected master and slave (bytes)
2946system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2947system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2948system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
--- 60 unchanged lines hidden (view full) ---
3009system.iobus.reqLayer25.occupancy 569028004 # Layer occupancy (ticks)
3010system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
3011system.iobus.respLayer0.occupancy 92757000 # Layer occupancy (ticks)
3012system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
3013system.iobus.respLayer3.occupancy 147918000 # Layer occupancy (ticks)
3014system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
3015system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
3016system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
3017system.iocache.tags.replacements 115592 # number of replacements
3018system.iocache.tags.tagsinuse 11.302694 # Cycle average of tags in use
3019system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
3020system.iocache.tags.sampled_refs 115608 # Sample count of references to valid blocks.
3021system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
3022system.iocache.tags.warmup_cycle 9115775800000 # Cycle when the warmup percentage was hit.
3023system.iocache.tags.occ_blocks::realview.ethernet 3.842796 # Average occupied blocks per requestor
3024system.iocache.tags.occ_blocks::realview.ide 7.459898 # Average occupied blocks per requestor
3025system.iocache.tags.occ_percent::realview.ethernet 0.240175 # Average percentage of cache occupancy
3026system.iocache.tags.occ_percent::realview.ide 0.466244 # Average percentage of cache occupancy
3027system.iocache.tags.occ_percent::total 0.706418 # Average percentage of cache occupancy
3028system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
3029system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
3030system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
3031system.iocache.tags.tag_accesses 1040856 # Number of tag accesses
3032system.iocache.tags.data_accesses 1040856 # Number of data accesses
3033system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
3034system.iocache.ReadReq_misses::realview.ide 8883 # number of ReadReq misses
3035system.iocache.ReadReq_misses::total 8920 # number of ReadReq misses
3036system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
3037system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
3038system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
3039system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
3040system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
--- 109 unchanged lines hidden (view full) ---
3150system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71315.017493 # average WriteLineReq mshr miss latency
3151system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71315.017493 # average WriteLineReq mshr miss latency
3152system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency
3153system.iocache.demand_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency
3154system.iocache.demand_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency
3155system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90375 # average overall mshr miss latency
3156system.iocache.overall_avg_mshr_miss_latency::realview.ide 76420.229883 # average overall mshr miss latency
3157system.iocache.overall_avg_mshr_miss_latency::total 76425.056394 # average overall mshr miss latency
3158system.l2c.tags.replacements 1423185 # number of replacements
3159system.l2c.tags.tagsinuse 63448.336905 # Cycle average of tags in use
3160system.l2c.tags.total_refs 6060449 # Total number of references to valid blocks.
3161system.l2c.tags.sampled_refs 1482600 # Sample count of references to valid blocks.
3162system.l2c.tags.avg_refs 4.087717 # Average number of references to valid blocks.
3163system.l2c.tags.warmup_cycle 3022937500 # Cycle when the warmup percentage was hit.
3164system.l2c.tags.occ_blocks::writebacks 20826.975184 # Average occupied blocks per requestor
3165system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.832374 # Average occupied blocks per requestor
--- 33 unchanged lines hidden (view full) ---
3199system.l2c.tags.age_task_id_blocks_1024::2 2760 # Occupied blocks per task id
3200system.l2c.tags.age_task_id_blocks_1024::3 5614 # Occupied blocks per task id
3201system.l2c.tags.age_task_id_blocks_1024::4 39761 # Occupied blocks per task id
3202system.l2c.tags.occ_task_id_percent::1022 0.163300 # Percentage of cache occupancy per task id
3203system.l2c.tags.occ_task_id_percent::1023 0.003387 # Percentage of cache occupancy per task id
3204system.l2c.tags.occ_task_id_percent::1024 0.739914 # Percentage of cache occupancy per task id
3205system.l2c.tags.tag_accesses 76659871 # Number of tag accesses
3206system.l2c.tags.data_accesses 76659871 # Number of data accesses
3207system.l2c.WritebackDirty_hits::writebacks 2799563 # number of WritebackDirty hits
3208system.l2c.WritebackDirty_hits::total 2799563 # number of WritebackDirty hits
3209system.l2c.UpgradeReq_hits::cpu0.data 175772 # number of UpgradeReq hits
3210system.l2c.UpgradeReq_hits::cpu1.data 127713 # number of UpgradeReq hits
3211system.l2c.UpgradeReq_hits::total 303485 # number of UpgradeReq hits
3212system.l2c.SCUpgradeReq_hits::cpu0.data 39800 # number of SCUpgradeReq hits
3213system.l2c.SCUpgradeReq_hits::cpu1.data 41169 # number of SCUpgradeReq hits
3214system.l2c.SCUpgradeReq_hits::total 80969 # number of SCUpgradeReq hits
--- 504 unchanged lines hidden (view full) ---
3719system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 48017.521994 # average overall mshr uncacheable latency
3720system.l2c.overall_avg_mshr_uncacheable_latency::total 74089.494383 # average overall mshr uncacheable latency
3721system.membus.snoop_filter.tot_requests 3952559 # Total number of requests made to the snoop filter.
3722system.membus.snoop_filter.hit_single_requests 2414080 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3723system.membus.snoop_filter.hit_multi_requests 2931 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3724system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
3725system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3726system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3727system.membus.trans_dist::ReadReq 60003 # Transaction distribution
3728system.membus.trans_dist::ReadResp 904829 # Transaction distribution
3729system.membus.trans_dist::WriteReq 38534 # Transaction distribution
3730system.membus.trans_dist::WriteResp 38534 # Transaction distribution
3731system.membus.trans_dist::WritebackDirty 1242017 # Transaction distribution
3732system.membus.trans_dist::CleanEvict 238236 # Transaction distribution
3733system.membus.trans_dist::UpgradeReq 446737 # Transaction distribution
3734system.membus.trans_dist::SCUpgradeReq 299659 # Transaction distribution
--- 38 unchanged lines hidden (view full) ---
3773system.membus.reqLayer2.occupancy 22248500 # Layer occupancy (ticks)
3774system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3775system.membus.reqLayer5.occupancy 8723892621 # Layer occupancy (ticks)
3776system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3777system.membus.respLayer2.occupancy 5223815230 # Layer occupancy (ticks)
3778system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3779system.membus.respLayer3.occupancy 45514707 # Layer occupancy (ticks)
3780system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3781system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3782system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3783system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3784system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3785system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3786system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3787system.realview.ethernet.txBytes 966 # Bytes Transmitted
3788system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3789system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3790system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3791system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3792system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3793system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
3794system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
--- 26 unchanged lines hidden (view full) ---
3821system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
3822system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3823system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3824system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
3825system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3826system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3827system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3828system.realview.ethernet.droppedPackets 0 # number of packets dropped
3829system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3830system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3831system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3832system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3833system.toL2Bus.snoop_filter.tot_requests 11842018 # Total number of requests made to the snoop filter.
3834system.toL2Bus.snoop_filter.hit_single_requests 6441759 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3835system.toL2Bus.snoop_filter.hit_multi_requests 1913591 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3836system.toL2Bus.snoop_filter.tot_snoops 133722 # Total number of snoops made to the snoop filter.
3837system.toL2Bus.snoop_filter.hit_single_snoops 121814 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3838system.toL2Bus.snoop_filter.hit_multi_snoops 11908 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3839system.toL2Bus.trans_dist::ReadReq 60005 # Transaction distribution
3840system.toL2Bus.trans_dist::ReadResp 4492996 # Transaction distribution
3841system.toL2Bus.trans_dist::WriteReq 38534 # Transaction distribution
3842system.toL2Bus.trans_dist::WriteResp 38534 # Transaction distribution
3843system.toL2Bus.trans_dist::WritebackDirty 3934886 # Transaction distribution
3844system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
3845system.toL2Bus.trans_dist::CleanEvict 2625367 # Transaction distribution
3846system.toL2Bus.trans_dist::UpgradeReq 741215 # Transaction distribution
--- 41 unchanged lines hidden ---