1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.354243 # Number of seconds simulated
4sim_ticks 47354242877000 # Number of ticks simulated
5final_tick 47354242877000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 195342 # Simulator instruction rate (inst/s)
8host_op_rate 229691 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 10034841905 # Simulator tick rate (ticks/s)
10host_mem_usage 778832 # Number of bytes of host memory used
11host_seconds 4718.98 # Real time elapsed on the host
12sim_insts 921815819 # Number of instructions simulated
13sim_ops 1083910027 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 202368 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 196224 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 4450144 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 45350984 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 22283904 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 113792 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 85504 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 2862048 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 13865872 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 12452160 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 439808 # Number of bytes read from this memory
27system.physmem.bytes_read::total 102302808 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 4450144 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 2862048 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 7312192 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 85371072 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
34system.physmem.bytes_written::total 85391656 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 3162 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 3066 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 85486 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 708622 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 348186 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 1778 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.itb.walker 1336 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.inst 44763 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.data 216667 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.l2cache.prefetcher 194565 # Number of read requests responded to by this memory
45system.physmem.num_reads::realview.ide 6872 # Number of read requests responded to by this memory
46system.physmem.num_reads::total 1614503 # Number of read requests responded to by this memory
47system.physmem.num_writes::writebacks 1333923 # Number of write requests responded to by this memory
48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
50system.physmem.num_writes::total 1336497 # Number of write requests responded to by this memory
51system.physmem.bw_read::cpu0.dtb.walker 4273 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.itb.walker 4144 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.inst 93976 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.data 957696 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.l2cache.prefetcher 470579 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.dtb.walker 2403 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.itb.walker 1806 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.inst 60439 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.data 292812 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.l2cache.prefetcher 262958 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::realview.ide 9288 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::total 2160373 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::cpu0.inst 93976 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu1.inst 60439 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::total 154415 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_write::writebacks 1802818 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::total 1803252 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_total::writebacks 1802818 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.dtb.walker 4273 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.itb.walker 4144 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.inst 93976 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.data 958131 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.l2cache.prefetcher 470579 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.dtb.walker 2403 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.itb.walker 1806 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.inst 60439 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.data 292812 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.l2cache.prefetcher 262958 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.ide 9288 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::total 3963625 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.readReqs 1614503 # Number of read requests accepted
84system.physmem.writeReqs 1336497 # Number of write requests accepted
85system.physmem.readBursts 1614503 # Number of DRAM read bursts, including those serviced by the write queue
86system.physmem.writeBursts 1336497 # Number of DRAM write bursts, including those merged in the write queue
87system.physmem.bytesReadDRAM 103293760 # Total number of bytes read from DRAM
88system.physmem.bytesReadWrQ 34432 # Total number of bytes read from write queue
89system.physmem.bytesWritten 85390720 # Total number of bytes written to DRAM
90system.physmem.bytesReadSys 102302808 # Total read bytes from the system interface side
91system.physmem.bytesWrittenSys 85391656 # Total written bytes from the system interface side
92system.physmem.servicedByWrQ 538 # Number of DRAM read bursts serviced by the write queue
93system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
94system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
95system.physmem.perBankRdBursts::0 97103 # Per bank write bursts
96system.physmem.perBankRdBursts::1 99552 # Per bank write bursts
97system.physmem.perBankRdBursts::2 98906 # Per bank write bursts
98system.physmem.perBankRdBursts::3 103577 # Per bank write bursts
99system.physmem.perBankRdBursts::4 99773 # Per bank write bursts
100system.physmem.perBankRdBursts::5 105983 # Per bank write bursts
101system.physmem.perBankRdBursts::6 104785 # Per bank write bursts
102system.physmem.perBankRdBursts::7 101396 # Per bank write bursts
103system.physmem.perBankRdBursts::8 95400 # Per bank write bursts
104system.physmem.perBankRdBursts::9 122614 # Per bank write bursts
105system.physmem.perBankRdBursts::10 95999 # Per bank write bursts
106system.physmem.perBankRdBursts::11 101585 # Per bank write bursts
107system.physmem.perBankRdBursts::12 99838 # Per bank write bursts
108system.physmem.perBankRdBursts::13 98462 # Per bank write bursts
109system.physmem.perBankRdBursts::14 93633 # Per bank write bursts
110system.physmem.perBankRdBursts::15 95359 # Per bank write bursts
111system.physmem.perBankWrBursts::0 80772 # Per bank write bursts
112system.physmem.perBankWrBursts::1 85062 # Per bank write bursts
113system.physmem.perBankWrBursts::2 82679 # Per bank write bursts
114system.physmem.perBankWrBursts::3 85393 # Per bank write bursts
115system.physmem.perBankWrBursts::4 84018 # Per bank write bursts
116system.physmem.perBankWrBursts::5 87943 # Per bank write bursts
117system.physmem.perBankWrBursts::6 87092 # Per bank write bursts
118system.physmem.perBankWrBursts::7 86427 # Per bank write bursts
119system.physmem.perBankWrBursts::8 80096 # Per bank write bursts
120system.physmem.perBankWrBursts::9 84617 # Per bank write bursts
121system.physmem.perBankWrBursts::10 79653 # Per bank write bursts
122system.physmem.perBankWrBursts::11 85236 # Per bank write bursts
123system.physmem.perBankWrBursts::12 82895 # Per bank write bursts
124system.physmem.perBankWrBursts::13 82853 # Per bank write bursts
125system.physmem.perBankWrBursts::14 78695 # Per bank write bursts
126system.physmem.perBankWrBursts::15 80799 # Per bank write bursts
127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
128system.physmem.numWrRetry 46 # Number of times write queue was full causing retry
129system.physmem.totGap 47354241269500 # Total gap between requests
130system.physmem.readPktSize::0 0 # Read request sizes (log2)
131system.physmem.readPktSize::1 0 # Read request sizes (log2)
132system.physmem.readPktSize::2 0 # Read request sizes (log2)
133system.physmem.readPktSize::3 25 # Read request sizes (log2)
134system.physmem.readPktSize::4 21333 # Read request sizes (log2)
135system.physmem.readPktSize::5 0 # Read request sizes (log2)
136system.physmem.readPktSize::6 1593145 # Read request sizes (log2)
137system.physmem.writePktSize::0 0 # Write request sizes (log2)
138system.physmem.writePktSize::1 0 # Write request sizes (log2)
139system.physmem.writePktSize::2 2 # Write request sizes (log2)
140system.physmem.writePktSize::3 2572 # Write request sizes (log2)
141system.physmem.writePktSize::4 0 # Write request sizes (log2)
142system.physmem.writePktSize::5 0 # Write request sizes (log2)
143system.physmem.writePktSize::6 1333923 # Write request sizes (log2)
144system.physmem.rdQLenPdf::0 609512 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::1 408742 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::2 165543 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::3 158385 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::4 99064 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::5 61330 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::6 32974 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::7 30716 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::8 27120 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::9 7850 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::10 4295 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::11 2710 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::12 1710 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::13 1391 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::14 869 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::15 607 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::16 497 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::17 363 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::18 155 # What read queue length does an incoming req see
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164system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see
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166system.physmem.rdQLenPdf::22 7 # What read queue length does an incoming req see
167system.physmem.rdQLenPdf::23 4 # What read queue length does an incoming req see
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190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::15 21385 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::16 25204 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::17 37704 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::18 44061 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::19 53566 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::20 60840 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::21 68935 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::22 76299 # What write queue length does an incoming req see
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200system.physmem.wrQLenPdf::24 85573 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::25 89148 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::26 94653 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::27 94373 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::28 98828 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::29 112387 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::30 98640 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::31 87955 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::32 82141 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::33 5308 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::34 2603 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::35 1767 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::36 1210 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::37 957 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::38 756 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::39 659 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::40 496 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::41 462 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::42 446 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::43 410 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::44 443 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::45 472 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::46 377 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::47 359 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::48 312 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::49 324 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::50 337 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::51 280 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::52 310 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::53 218 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::54 246 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::55 222 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::56 215 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::57 217 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::58 151 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::59 167 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::60 184 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::61 234 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::62 86 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::63 109 # What write queue length does an incoming req see
240system.physmem.bytesPerActivate::samples 1039142 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::mean 181.576816 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::gmean 111.689088 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::stdev 241.244363 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::0-127 644376 62.01% 62.01% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::128-255 193180 18.59% 80.60% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::256-383 61698 5.94% 86.54% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::384-511 33929 3.27% 89.80% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::512-639 24382 2.35% 92.15% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::640-767 13748 1.32% 93.47% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::768-895 13846 1.33% 94.81% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::896-1023 7628 0.73% 95.54% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::1024-1151 46355 4.46% 100.00% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::total 1039142 # Bytes accessed per row activation
254system.physmem.rdPerTurnAround::samples 75311 # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::mean 21.430349 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::stdev 250.668355 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::0-4095 75308 100.00% 100.00% # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::65536-69631 1 0.00% 100.00% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::total 75311 # Reads before turning the bus around for writes
262system.physmem.wrPerTurnAround::samples 75311 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::mean 17.716270 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::gmean 17.189166 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::stdev 7.091364 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::16-19 70052 93.02% 93.02% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::20-23 3029 4.02% 97.04% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::24-27 423 0.56% 97.60% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::28-31 178 0.24% 97.84% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::32-35 138 0.18% 98.02% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::36-39 118 0.16% 98.18% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::40-43 205 0.27% 98.45% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::44-47 81 0.11% 98.56% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::48-51 292 0.39% 98.94% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::52-55 59 0.08% 99.02% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::56-59 23 0.03% 99.05% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::60-63 57 0.08% 99.13% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::64-67 240 0.32% 99.45% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::68-71 44 0.06% 99.51% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::72-75 27 0.04% 99.54% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::76-79 108 0.14% 99.69% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::80-83 169 0.22% 99.91% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::84-87 3 0.00% 99.91% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::100-103 2 0.00% 99.92% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::104-107 3 0.00% 99.92% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::112-115 3 0.00% 99.93% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::116-119 1 0.00% 99.93% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::120-123 2 0.00% 99.93% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::128-131 14 0.02% 99.95% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::132-135 2 0.00% 99.95% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::140-143 4 0.01% 99.96% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::144-147 13 0.02% 99.98% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::148-151 1 0.00% 99.98% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::156-159 5 0.01% 99.99% # Writes before turning the bus around for reads
297system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads
298system.physmem.wrPerTurnAround::172-175 3 0.00% 99.99% # Writes before turning the bus around for reads
299system.physmem.wrPerTurnAround::176-179 3 0.00% 100.00% # Writes before turning the bus around for reads
300system.physmem.wrPerTurnAround::192-195 3 0.00% 100.00% # Writes before turning the bus around for reads
301system.physmem.wrPerTurnAround::total 75311 # Writes before turning the bus around for reads
302system.physmem.totQLat 70116127057 # Total ticks spent queuing
303system.physmem.totMemAccLat 100377970807 # Total ticks spent from burst creation until serviced by the DRAM
304system.physmem.totBusLat 8069825000 # Total ticks spent in databus transfers
305system.physmem.avgQLat 43443.40 # Average queueing delay per DRAM burst
306system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
307system.physmem.avgMemAccLat 62193.40 # Average memory access latency per DRAM burst
308system.physmem.avgRdBW 2.18 # Average DRAM read bandwidth in MiByte/s
309system.physmem.avgWrBW 1.80 # Average achieved write bandwidth in MiByte/s
310system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s
311system.physmem.avgWrBWSys 1.80 # Average system write bandwidth in MiByte/s
312system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
313system.physmem.busUtil 0.03 # Data bus utilization in percentage
314system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
315system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
316system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing
317system.physmem.avgWrQLen 25.55 # Average write queue length when enqueuing
318system.physmem.readRowHits 1298803 # Number of row buffer hits during reads
319system.physmem.writeRowHits 610248 # Number of row buffer hits during writes
320system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads
321system.physmem.writeRowHitRate 45.74 # Row buffer hit rate for writes
322system.physmem.avgGap 16046845.57 # Average gap between requests
323system.physmem.pageHitRate 64.75 # Row buffer hit rate, read and write combined
324system.physmem_0.actEnergy 4027930200 # Energy for activate commands per rank (pJ)
325system.physmem_0.preEnergy 2197779375 # Energy for precharge commands per rank (pJ)
326system.physmem_0.readEnergy 6326346000 # Energy for read commands per rank (pJ)
327system.physmem_0.writeEnergy 4402421280 # Energy for write commands per rank (pJ)
328system.physmem_0.refreshEnergy 3092948511120 # Energy for refresh commands per rank (pJ)
329system.physmem_0.actBackEnergy 1180978829595 # Energy for active background per rank (pJ)
330system.physmem_0.preBackEnergy 27376595514000 # Energy for precharge background per rank (pJ)
331system.physmem_0.totalEnergy 31667477331570 # Total energy per rank (pJ)
332system.physmem_0.averagePower 668.735888 # Core power per rank (mW)
333system.physmem_0.memoryStateTime::IDLE 45543196260914 # Time in different power states
334system.physmem_0.memoryStateTime::REF 1581262020000 # Time in different power states
335system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
336system.physmem_0.memoryStateTime::ACT 229783905086 # Time in different power states
337system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
338system.physmem_1.actEnergy 3827983320 # Energy for activate commands per rank (pJ)
339system.physmem_1.preEnergy 2088681375 # Energy for precharge commands per rank (pJ)
340system.physmem_1.readEnergy 6262534200 # Energy for read commands per rank (pJ)
341system.physmem_1.writeEnergy 4243389120 # Energy for write commands per rank (pJ)
342system.physmem_1.refreshEnergy 3092948511120 # Energy for refresh commands per rank (pJ)
343system.physmem_1.actBackEnergy 1177720349355 # Energy for active background per rank (pJ)
344system.physmem_1.preBackEnergy 27379453830000 # Energy for precharge background per rank (pJ)
345system.physmem_1.totalEnergy 31666545278490 # Total energy per rank (pJ)
346system.physmem_1.averagePower 668.716205 # Core power per rank (mW)
347system.physmem_1.memoryStateTime::IDLE 45547950580913 # Time in different power states
348system.physmem_1.memoryStateTime::REF 1581262020000 # Time in different power states
349system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
350system.physmem_1.memoryStateTime::ACT 225030017087 # Time in different power states
351system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
352system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory
353system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
354system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
355system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
356system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory
357system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory
358system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory

--- 17 unchanged lines hidden (view full) ---

376system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
377system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
378system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
379system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
380system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
381system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
382system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
383system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
384system.cpu0.branchPred.lookups 149665852 # Number of BP lookups
385system.cpu0.branchPred.condPredicted 99294558 # Number of conditional branches predicted
386system.cpu0.branchPred.condIncorrect 7394871 # Number of conditional branches incorrect
387system.cpu0.branchPred.BTBLookups 104737280 # Number of BTB lookups
388system.cpu0.branchPred.BTBHits 69525721 # Number of BTB hits
389system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
390system.cpu0.branchPred.BTBHitPct 66.381064 # BTB Hit Percentage
391system.cpu0.branchPred.usedRAS 20507496 # Number of times the RAS was used to get a target.
392system.cpu0.branchPred.RASInCorrect 218312 # Number of incorrect RAS predictions.
393system.cpu_clk_domain.clock 500 # Clock period in ticks
394system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

415system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
416system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
417system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
418system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
419system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
420system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
421system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
422system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
423system.cpu0.dtb.walker.walks 634428 # Table walker walks requested
424system.cpu0.dtb.walker.walksLong 634428 # Table walker walks initiated with long descriptors
425system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 14162 # Level at which table walker walks with long descriptors terminate
426system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 100318 # Level at which table walker walks with long descriptors terminate
427system.cpu0.dtb.walker.walksSquashedBefore 297022 # Table walks squashed before starting
428system.cpu0.dtb.walker.walkWaitTime::samples 337406 # Table walker wait (enqueue to first request) latency
429system.cpu0.dtb.walker.walkWaitTime::mean 2383.727616 # Table walker wait (enqueue to first request) latency
430system.cpu0.dtb.walker.walkWaitTime::stdev 14932.270093 # Table walker wait (enqueue to first request) latency
431system.cpu0.dtb.walker.walkWaitTime::0-65535 334700 99.20% 99.20% # Table walker wait (enqueue to first request) latency
432system.cpu0.dtb.walker.walkWaitTime::65536-131071 1380 0.41% 99.61% # Table walker wait (enqueue to first request) latency
433system.cpu0.dtb.walker.walkWaitTime::131072-196607 1061 0.31% 99.92% # Table walker wait (enqueue to first request) latency
434system.cpu0.dtb.walker.walkWaitTime::196608-262143 114 0.03% 99.96% # Table walker wait (enqueue to first request) latency
435system.cpu0.dtb.walker.walkWaitTime::262144-327679 46 0.01% 99.97% # Table walker wait (enqueue to first request) latency
436system.cpu0.dtb.walker.walkWaitTime::327680-393215 68 0.02% 99.99% # Table walker wait (enqueue to first request) latency
437system.cpu0.dtb.walker.walkWaitTime::393216-458751 21 0.01% 100.00% # Table walker wait (enqueue to first request) latency
438system.cpu0.dtb.walker.walkWaitTime::458752-524287 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency
439system.cpu0.dtb.walker.walkWaitTime::524288-589823 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency
440system.cpu0.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
441system.cpu0.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
442system.cpu0.dtb.walker.walkWaitTime::total 337406 # Table walker wait (enqueue to first request) latency
443system.cpu0.dtb.walker.walkCompletionTime::samples 331422 # Table walker service (enqueue to completion) latency
444system.cpu0.dtb.walker.walkCompletionTime::mean 21257.229454 # Table walker service (enqueue to completion) latency
445system.cpu0.dtb.walker.walkCompletionTime::gmean 17843.462773 # Table walker service (enqueue to completion) latency
446system.cpu0.dtb.walker.walkCompletionTime::stdev 23121.353715 # Table walker service (enqueue to completion) latency
447system.cpu0.dtb.walker.walkCompletionTime::0-65535 326855 98.62% 98.62% # Table walker service (enqueue to completion) latency
448system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1016 0.31% 98.93% # Table walker service (enqueue to completion) latency
449system.cpu0.dtb.walker.walkCompletionTime::131072-196607 2453 0.74% 99.67% # Table walker service (enqueue to completion) latency
450system.cpu0.dtb.walker.walkCompletionTime::196608-262143 165 0.05% 99.72% # Table walker service (enqueue to completion) latency
451system.cpu0.dtb.walker.walkCompletionTime::262144-327679 627 0.19% 99.91% # Table walker service (enqueue to completion) latency
452system.cpu0.dtb.walker.walkCompletionTime::327680-393215 136 0.04% 99.95% # Table walker service (enqueue to completion) latency
453system.cpu0.dtb.walker.walkCompletionTime::393216-458751 104 0.03% 99.98% # Table walker service (enqueue to completion) latency
454system.cpu0.dtb.walker.walkCompletionTime::458752-524287 36 0.01% 99.99% # Table walker service (enqueue to completion) latency
455system.cpu0.dtb.walker.walkCompletionTime::524288-589823 24 0.01% 100.00% # Table walker service (enqueue to completion) latency
456system.cpu0.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
457system.cpu0.dtb.walker.walkCompletionTime::total 331422 # Table walker service (enqueue to completion) latency
458system.cpu0.dtb.walker.walksPending::samples 582048251060 # Table walker pending requests distribution
459system.cpu0.dtb.walker.walksPending::mean 0.606269 # Table walker pending requests distribution
460system.cpu0.dtb.walker.walksPending::stdev 0.543146 # Table walker pending requests distribution
461system.cpu0.dtb.walker.walksPending::0-1 580572178560 99.75% 99.75% # Table walker pending requests distribution
462system.cpu0.dtb.walker.walksPending::2-3 833055500 0.14% 99.89% # Table walker pending requests distribution
463system.cpu0.dtb.walker.walksPending::4-5 305294500 0.05% 99.94% # Table walker pending requests distribution
464system.cpu0.dtb.walker.walksPending::6-7 135391000 0.02% 99.97% # Table walker pending requests distribution
465system.cpu0.dtb.walker.walksPending::8-9 101845000 0.02% 99.98% # Table walker pending requests distribution
466system.cpu0.dtb.walker.walksPending::10-11 57765000 0.01% 99.99% # Table walker pending requests distribution
467system.cpu0.dtb.walker.walksPending::12-13 18306500 0.00% 100.00% # Table walker pending requests distribution
468system.cpu0.dtb.walker.walksPending::14-15 23753000 0.00% 100.00% # Table walker pending requests distribution
469system.cpu0.dtb.walker.walksPending::16-17 653000 0.00% 100.00% # Table walker pending requests distribution
470system.cpu0.dtb.walker.walksPending::18-19 9000 0.00% 100.00% # Table walker pending requests distribution
471system.cpu0.dtb.walker.walksPending::total 582048251060 # Table walker pending requests distribution
472system.cpu0.dtb.walker.walkPageSizes::4K 100318 87.63% 87.63% # Table walker page sizes translated
473system.cpu0.dtb.walker.walkPageSizes::2M 14162 12.37% 100.00% # Table walker page sizes translated
474system.cpu0.dtb.walker.walkPageSizes::total 114480 # Table walker page sizes translated
475system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 634428 # Table walker requests started/completed, data/inst
476system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
477system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 634428 # Table walker requests started/completed, data/inst
478system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 114480 # Table walker requests started/completed, data/inst
479system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
480system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 114480 # Table walker requests started/completed, data/inst
481system.cpu0.dtb.walker.walkRequestOrigin::total 748908 # Table walker requests started/completed, data/inst
482system.cpu0.dtb.inst_hits 0 # ITB inst hits
483system.cpu0.dtb.inst_misses 0 # ITB inst misses
484system.cpu0.dtb.read_hits 109416332 # DTB read hits
485system.cpu0.dtb.read_misses 460008 # DTB read misses
486system.cpu0.dtb.write_hits 89314742 # DTB write hits
487system.cpu0.dtb.write_misses 174420 # DTB write misses
488system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
489system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
490system.cpu0.dtb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID
491system.cpu0.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
492system.cpu0.dtb.flush_entries 43796 # Number of entries that have been flushed from TLB
493system.cpu0.dtb.align_faults 708 # Number of TLB faults due to alignment restrictions
494system.cpu0.dtb.prefetch_faults 7923 # Number of TLB faults due to prefetch
495system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
496system.cpu0.dtb.perms_faults 42753 # Number of TLB faults due to permissions restrictions
497system.cpu0.dtb.read_accesses 109876340 # DTB read accesses
498system.cpu0.dtb.write_accesses 89489162 # DTB write accesses
499system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
500system.cpu0.dtb.hits 198731074 # DTB hits
501system.cpu0.dtb.misses 634428 # DTB misses
502system.cpu0.dtb.accesses 199365502 # DTB accesses
503system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
504system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
505system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
506system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
507system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
508system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
509system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
510system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

524system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
525system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
526system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
527system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
528system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
529system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
530system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
531system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
532system.cpu0.itb.walker.walks 91298 # Table walker walks requested
533system.cpu0.itb.walker.walksLong 91298 # Table walker walks initiated with long descriptors
534system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1125 # Level at which table walker walks with long descriptors terminate
535system.cpu0.itb.walker.walksLongTerminationLevel::Level3 66671 # Level at which table walker walks with long descriptors terminate
536system.cpu0.itb.walker.walksSquashedBefore 10542 # Table walks squashed before starting
537system.cpu0.itb.walker.walkWaitTime::samples 80756 # Table walker wait (enqueue to first request) latency
538system.cpu0.itb.walker.walkWaitTime::mean 1599.144336 # Table walker wait (enqueue to first request) latency
539system.cpu0.itb.walker.walkWaitTime::stdev 12482.430449 # Table walker wait (enqueue to first request) latency
540system.cpu0.itb.walker.walkWaitTime::0-65535 80336 99.48% 99.48% # Table walker wait (enqueue to first request) latency
541system.cpu0.itb.walker.walkWaitTime::65536-131071 92 0.11% 99.59% # Table walker wait (enqueue to first request) latency
542system.cpu0.itb.walker.walkWaitTime::131072-196607 294 0.36% 99.96% # Table walker wait (enqueue to first request) latency
543system.cpu0.itb.walker.walkWaitTime::196608-262143 14 0.02% 99.98% # Table walker wait (enqueue to first request) latency
544system.cpu0.itb.walker.walkWaitTime::262144-327679 11 0.01% 99.99% # Table walker wait (enqueue to first request) latency
545system.cpu0.itb.walker.walkWaitTime::327680-393215 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency
546system.cpu0.itb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
547system.cpu0.itb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
548system.cpu0.itb.walker.walkWaitTime::total 80756 # Table walker wait (enqueue to first request) latency
549system.cpu0.itb.walker.walkCompletionTime::samples 78338 # Table walker service (enqueue to completion) latency
550system.cpu0.itb.walker.walkCompletionTime::mean 27568.581021 # Table walker service (enqueue to completion) latency
551system.cpu0.itb.walker.walkCompletionTime::gmean 23319.178868 # Table walker service (enqueue to completion) latency
552system.cpu0.itb.walker.walkCompletionTime::stdev 29698.501423 # Table walker service (enqueue to completion) latency
553system.cpu0.itb.walker.walkCompletionTime::0-65535 76052 97.08% 97.08% # Table walker service (enqueue to completion) latency
554system.cpu0.itb.walker.walkCompletionTime::65536-131071 130 0.17% 97.25% # Table walker service (enqueue to completion) latency
555system.cpu0.itb.walker.walkCompletionTime::131072-196607 1833 2.34% 99.59% # Table walker service (enqueue to completion) latency
556system.cpu0.itb.walker.walkCompletionTime::196608-262143 110 0.14% 99.73% # Table walker service (enqueue to completion) latency
557system.cpu0.itb.walker.walkCompletionTime::262144-327679 108 0.14% 99.87% # Table walker service (enqueue to completion) latency
558system.cpu0.itb.walker.walkCompletionTime::327680-393215 41 0.05% 99.92% # Table walker service (enqueue to completion) latency
559system.cpu0.itb.walker.walkCompletionTime::393216-458751 39 0.05% 99.97% # Table walker service (enqueue to completion) latency
560system.cpu0.itb.walker.walkCompletionTime::458752-524287 15 0.02% 99.99% # Table walker service (enqueue to completion) latency
561system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.99% # Table walker service (enqueue to completion) latency
562system.cpu0.itb.walker.walkCompletionTime::589824-655359 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
563system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
564system.cpu0.itb.walker.walkCompletionTime::917504-983039 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
565system.cpu0.itb.walker.walkCompletionTime::total 78338 # Table walker service (enqueue to completion) latency
566system.cpu0.itb.walker.walksPending::samples 423131286608 # Table walker pending requests distribution
567system.cpu0.itb.walker.walksPending::mean 0.845297 # Table walker pending requests distribution
568system.cpu0.itb.walker.walksPending::stdev 0.361834 # Table walker pending requests distribution
569system.cpu0.itb.walker.walksPending::0 65489609660 15.48% 15.48% # Table walker pending requests distribution
570system.cpu0.itb.walker.walksPending::1 357613926448 84.52% 99.99% # Table walker pending requests distribution
571system.cpu0.itb.walker.walksPending::2 25558000 0.01% 100.00% # Table walker pending requests distribution
572system.cpu0.itb.walker.walksPending::3 2033000 0.00% 100.00% # Table walker pending requests distribution
573system.cpu0.itb.walker.walksPending::4 159500 0.00% 100.00% # Table walker pending requests distribution
574system.cpu0.itb.walker.walksPending::total 423131286608 # Table walker pending requests distribution
575system.cpu0.itb.walker.walkPageSizes::4K 66671 98.34% 98.34% # Table walker page sizes translated
576system.cpu0.itb.walker.walkPageSizes::2M 1125 1.66% 100.00% # Table walker page sizes translated
577system.cpu0.itb.walker.walkPageSizes::total 67796 # Table walker page sizes translated
578system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
579system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 91298 # Table walker requests started/completed, data/inst
580system.cpu0.itb.walker.walkRequestOrigin_Requested::total 91298 # Table walker requests started/completed, data/inst
581system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
582system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 67796 # Table walker requests started/completed, data/inst
583system.cpu0.itb.walker.walkRequestOrigin_Completed::total 67796 # Table walker requests started/completed, data/inst
584system.cpu0.itb.walker.walkRequestOrigin::total 159094 # Table walker requests started/completed, data/inst
585system.cpu0.itb.inst_hits 236080263 # ITB inst hits
586system.cpu0.itb.inst_misses 91298 # ITB inst misses
587system.cpu0.itb.read_hits 0 # DTB read hits
588system.cpu0.itb.read_misses 0 # DTB read misses
589system.cpu0.itb.write_hits 0 # DTB write hits
590system.cpu0.itb.write_misses 0 # DTB write misses
591system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
592system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
593system.cpu0.itb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID
594system.cpu0.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
595system.cpu0.itb.flush_entries 31862 # Number of entries that have been flushed from TLB
596system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
597system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
598system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
599system.cpu0.itb.perms_faults 229508 # Number of TLB faults due to permissions restrictions
600system.cpu0.itb.read_accesses 0 # DTB read accesses
601system.cpu0.itb.write_accesses 0 # DTB write accesses
602system.cpu0.itb.inst_accesses 236171561 # ITB inst accesses
603system.cpu0.itb.hits 236080263 # DTB hits
604system.cpu0.itb.misses 91298 # DTB misses
605system.cpu0.itb.accesses 236171561 # DTB accesses
606system.cpu0.numCycles 875332831 # number of cpu cycles simulated
607system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
608system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
609system.cpu0.fetch.icacheStallCycles 98502478 # Number of cycles fetch is stalled on an Icache miss
610system.cpu0.fetch.Insts 662547160 # Number of instructions fetch has processed
611system.cpu0.fetch.Branches 149665852 # Number of branches that fetch encountered
612system.cpu0.fetch.predictedBranches 90033217 # Number of branches that fetch has predicted taken
613system.cpu0.fetch.Cycles 725278481 # Number of cycles fetch has run and was not squashing or blocked
614system.cpu0.fetch.SquashCycles 15926346 # Number of cycles fetch has spent squashing
615system.cpu0.fetch.TlbCycles 2210942 # Number of cycles fetch has spent waiting for tlb
616system.cpu0.fetch.MiscStallCycles 343253 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
617system.cpu0.fetch.PendingTrapStallCycles 6644206 # Number of stall cycles due to pending traps
618system.cpu0.fetch.PendingQuiesceStallCycles 843353 # Number of stall cycles due to pending quiesce instructions
619system.cpu0.fetch.IcacheWaitRetryStallCycles 921483 # Number of stall cycles due to full MSHR
620system.cpu0.fetch.CacheLines 235849038 # Number of cache lines fetched
621system.cpu0.fetch.IcacheSquashes 1874950 # Number of outstanding Icache misses that were squashed
622system.cpu0.fetch.ItlbSquashes 30072 # Number of outstanding ITLB misses that were squashed
623system.cpu0.fetch.rateDist::samples 842707369 # Number of instructions fetched each cycle (Total)
624system.cpu0.fetch.rateDist::mean 0.920891 # Number of instructions fetched each cycle (Total)
625system.cpu0.fetch.rateDist::stdev 1.205357 # Number of instructions fetched each cycle (Total)
626system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
627system.cpu0.fetch.rateDist::0 471086256 55.90% 55.90% # Number of instructions fetched each cycle (Total)
628system.cpu0.fetch.rateDist::1 144263495 17.12% 73.02% # Number of instructions fetched each cycle (Total)
629system.cpu0.fetch.rateDist::2 50294842 5.97% 78.99% # Number of instructions fetched each cycle (Total)
630system.cpu0.fetch.rateDist::3 177062776 21.01% 100.00% # Number of instructions fetched each cycle (Total)
631system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
632system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
633system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
634system.cpu0.fetch.rateDist::total 842707369 # Number of instructions fetched each cycle (Total)
635system.cpu0.fetch.branchRate 0.170982 # Number of branch fetches per cycle
636system.cpu0.fetch.rate 0.756909 # Number of inst fetches per cycle
637system.cpu0.decode.IdleCycles 117017992 # Number of cycles decode is idle
638system.cpu0.decode.BlockedCycles 431286061 # Number of cycles decode is blocked
639system.cpu0.decode.RunCycles 248304840 # Number of cycles decode is running
640system.cpu0.decode.UnblockCycles 40439583 # Number of cycles decode is unblocking
641system.cpu0.decode.SquashCycles 5658893 # Number of cycles decode is squashing
642system.cpu0.decode.BranchResolved 21552813 # Number of times decode resolved a branch
643system.cpu0.decode.BranchMispred 2348874 # Number of times decode detected a branch misprediction
644system.cpu0.decode.DecodedInsts 685973615 # Number of instructions handled by decode
645system.cpu0.decode.SquashedInsts 25548756 # Number of squashed instructions handled by decode
646system.cpu0.rename.SquashCycles 5658893 # Number of cycles rename is squashing
647system.cpu0.rename.IdleCycles 155339909 # Number of cycles rename is idle
648system.cpu0.rename.BlockCycles 68898576 # Number of cycles rename is blocking
649system.cpu0.rename.serializeStallCycles 270709645 # count of cycles rename stalled for serializing inst
650system.cpu0.rename.RunCycles 249775497 # Number of cycles rename is running
651system.cpu0.rename.UnblockCycles 92324849 # Number of cycles rename is unblocking
652system.cpu0.rename.RenamedInsts 667175567 # Number of instructions processed by rename
653system.cpu0.rename.SquashedInsts 6553348 # Number of squashed instructions processed by rename
654system.cpu0.rename.ROBFullEvents 11928405 # Number of times rename has blocked due to ROB full
655system.cpu0.rename.IQFullEvents 414386 # Number of times rename has blocked due to IQ full
656system.cpu0.rename.LQFullEvents 932685 # Number of times rename has blocked due to LQ full
657system.cpu0.rename.SQFullEvents 54388046 # Number of times rename has blocked due to SQ full
658system.cpu0.rename.FullRegisterEvents 11955 # Number of times there has been no free registers
659system.cpu0.rename.RenamedOperands 637281036 # Number of destination operands rename has renamed
660system.cpu0.rename.RenameLookups 1029527825 # Number of register rename lookups that rename has made
661system.cpu0.rename.int_rename_lookups 787757309 # Number of integer rename lookups
662system.cpu0.rename.fp_rename_lookups 900744 # Number of floating rename lookups
663system.cpu0.rename.CommittedMaps 574091859 # Number of HB maps that are committed
664system.cpu0.rename.UndoneMaps 63189171 # Number of HB maps that are undone due to squashing
665system.cpu0.rename.serializingInsts 16646916 # count of serializing insts renamed
666system.cpu0.rename.tempSerializingInsts 14438257 # count of temporary serializing insts renamed
667system.cpu0.rename.skidInsts 81666616 # count of insts added to the skid buffer
668system.cpu0.memDep0.insertedLoads 109512073 # Number of loads inserted to the mem dependence unit.
669system.cpu0.memDep0.insertedStores 93001551 # Number of stores inserted to the mem dependence unit.
670system.cpu0.memDep0.conflictingLoads 9792967 # Number of conflicting loads.
671system.cpu0.memDep0.conflictingStores 8489048 # Number of conflicting stores.
672system.cpu0.iq.iqInstsAdded 643441375 # Number of instructions added to the IQ (excludes non-spec)
673system.cpu0.iq.iqNonSpecInstsAdded 16650008 # Number of non-speculative instructions added to the IQ
674system.cpu0.iq.iqInstsIssued 647817648 # Number of instructions issued
675system.cpu0.iq.iqSquashedInstsIssued 2959555 # Number of squashed instructions issued
676system.cpu0.iq.iqSquashedInstsExamined 59258512 # Number of squashed instructions iterated over during squash; mainly for profiling
677system.cpu0.iq.iqSquashedOperandsExamined 38730764 # Number of squashed operands that are examined and possibly removed from graph
678system.cpu0.iq.iqSquashedNonSpecRemoved 299230 # Number of squashed non-spec instructions that were removed
679system.cpu0.iq.issued_per_cycle::samples 842707369 # Number of insts issued each cycle
680system.cpu0.iq.issued_per_cycle::mean 0.768734 # Number of insts issued each cycle
681system.cpu0.iq.issued_per_cycle::stdev 1.052616 # Number of insts issued each cycle
682system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
683system.cpu0.iq.issued_per_cycle::0 489695832 58.11% 58.11% # Number of insts issued each cycle
684system.cpu0.iq.issued_per_cycle::1 146908165 17.43% 75.54% # Number of insts issued each cycle
685system.cpu0.iq.issued_per_cycle::2 125837037 14.93% 90.48% # Number of insts issued each cycle
686system.cpu0.iq.issued_per_cycle::3 71836004 8.52% 99.00% # Number of insts issued each cycle
687system.cpu0.iq.issued_per_cycle::4 8424258 1.00% 100.00% # Number of insts issued each cycle
688system.cpu0.iq.issued_per_cycle::5 6073 0.00% 100.00% # Number of insts issued each cycle
689system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
690system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
691system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
692system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
693system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
694system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
695system.cpu0.iq.issued_per_cycle::total 842707369 # Number of insts issued each cycle
696system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
697system.cpu0.iq.fu_full::IntAlu 67261039 45.56% 45.56% # attempts to use FU when none available
698system.cpu0.iq.fu_full::IntMult 66196 0.04% 45.60% # attempts to use FU when none available
699system.cpu0.iq.fu_full::IntDiv 15732 0.01% 45.62% # attempts to use FU when none available
700system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.62% # attempts to use FU when none available
701system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.62% # attempts to use FU when none available
702system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.62% # attempts to use FU when none available
703system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.62% # attempts to use FU when none available
704system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.62% # attempts to use FU when none available
705system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.62% # attempts to use FU when none available
706system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.62% # attempts to use FU when none available
707system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.62% # attempts to use FU when none available
708system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.62% # attempts to use FU when none available
709system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.62% # attempts to use FU when none available
710system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.62% # attempts to use FU when none available
711system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.62% # attempts to use FU when none available
712system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.62% # attempts to use FU when none available
713system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.62% # attempts to use FU when none available
714system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.62% # attempts to use FU when none available
715system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.62% # attempts to use FU when none available
716system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.62% # attempts to use FU when none available
717system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.62% # attempts to use FU when none available
718system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.62% # attempts to use FU when none available
719system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.62% # attempts to use FU when none available
720system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.62% # attempts to use FU when none available
721system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.62% # attempts to use FU when none available
722system.cpu0.iq.fu_full::SimdFloatMisc 29 0.00% 45.62% # attempts to use FU when none available
723system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.62% # attempts to use FU when none available
724system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.62% # attempts to use FU when none available
725system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.62% # attempts to use FU when none available
726system.cpu0.iq.fu_full::MemRead 38768633 26.26% 71.88% # attempts to use FU when none available
727system.cpu0.iq.fu_full::MemWrite 41521295 28.12% 100.00% # attempts to use FU when none available
728system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
729system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
730system.cpu0.iq.FU_type_0::No_OpClass 14 0.00% 0.00% # Type of FU issued
731system.cpu0.iq.FU_type_0::IntAlu 442579425 68.32% 68.32% # Type of FU issued
732system.cpu0.iq.FU_type_0::IntMult 1577066 0.24% 68.56% # Type of FU issued
733system.cpu0.iq.FU_type_0::IntDiv 84316 0.01% 68.57% # Type of FU issued
734system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.57% # Type of FU issued
735system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.57% # Type of FU issued
736system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.57% # Type of FU issued
737system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.57% # Type of FU issued
738system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.57% # Type of FU issued
739system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.57% # Type of FU issued
740system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.57% # Type of FU issued
741system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.57% # Type of FU issued
742system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.57% # Type of FU issued
743system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.57% # Type of FU issued
744system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.57% # Type of FU issued
745system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.57% # Type of FU issued
746system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.57% # Type of FU issued
747system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.57% # Type of FU issued
748system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.57% # Type of FU issued
749system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.57% # Type of FU issued
750system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.57% # Type of FU issued
751system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.57% # Type of FU issued
752system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.57% # Type of FU issued
753system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.57% # Type of FU issued
754system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.57% # Type of FU issued
755system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.57% # Type of FU issued
756system.cpu0.iq.FU_type_0::SimdFloatMisc 83107 0.01% 68.59% # Type of FU issued
757system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.59% # Type of FU issued
758system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.59% # Type of FU issued
759system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.59% # Type of FU issued
760system.cpu0.iq.FU_type_0::MemRead 112773884 17.41% 86.00% # Type of FU issued
761system.cpu0.iq.FU_type_0::MemWrite 90719836 14.00% 100.00% # Type of FU issued
762system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
763system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
764system.cpu0.iq.FU_type_0::total 647817648 # Type of FU issued
765system.cpu0.iq.rate 0.740082 # Inst issue rate
766system.cpu0.iq.fu_busy_cnt 147632924 # FU busy when requested
767system.cpu0.iq.fu_busy_rate 0.227893 # FU busy rate (busy events/executed inst)
768system.cpu0.iq.int_inst_queue_reads 2287461115 # Number of integer instruction queue reads
769system.cpu0.iq.int_inst_queue_writes 718905040 # Number of integer instruction queue writes
770system.cpu0.iq.int_inst_queue_wakeup_accesses 629078745 # Number of integer instruction queue wakeup accesses
771system.cpu0.iq.fp_inst_queue_reads 1474027 # Number of floating instruction queue reads
772system.cpu0.iq.fp_inst_queue_writes 598009 # Number of floating instruction queue writes
773system.cpu0.iq.fp_inst_queue_wakeup_accesses 548346 # Number of floating instruction queue wakeup accesses
774system.cpu0.iq.int_alu_accesses 794539840 # Number of integer alu accesses
775system.cpu0.iq.fp_alu_accesses 910718 # Number of floating point alu accesses
776system.cpu0.iew.lsq.thread0.forwLoads 2963176 # Number of loads that had data forwarded from stores
777system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
778system.cpu0.iew.lsq.thread0.squashedLoads 13511879 # Number of loads squashed
779system.cpu0.iew.lsq.thread0.ignoredResponses 17808 # Number of memory responses ignored because the instruction is squashed
780system.cpu0.iew.lsq.thread0.memOrderViolation 154801 # Number of memory ordering violations
781system.cpu0.iew.lsq.thread0.squashedStores 6318307 # Number of stores squashed
782system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
783system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
784system.cpu0.iew.lsq.thread0.rescheduledLoads 2892844 # Number of loads that were rescheduled
785system.cpu0.iew.lsq.thread0.cacheBlocked 5122180 # Number of times an access to memory failed due to the cache being blocked
786system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
787system.cpu0.iew.iewSquashCycles 5658893 # Number of cycles IEW is squashing
788system.cpu0.iew.iewBlockCycles 8725604 # Number of cycles IEW is blocking
789system.cpu0.iew.iewUnblockCycles 7188731 # Number of cycles IEW is unblocking
790system.cpu0.iew.iewDispatchedInsts 660220960 # Number of instructions dispatched to IQ
791system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
792system.cpu0.iew.iewDispLoadInsts 109512073 # Number of dispatched load instructions
793system.cpu0.iew.iewDispStoreInsts 93001551 # Number of dispatched store instructions
794system.cpu0.iew.iewDispNonSpecInsts 14147683 # Number of dispatched non-speculative instructions
795system.cpu0.iew.iewIQFullEvents 61387 # Number of times the IQ has become full, causing a stall
796system.cpu0.iew.iewLSQFullEvents 7052032 # Number of times the LSQ has become full, causing a stall
797system.cpu0.iew.memOrderViolationEvents 154801 # Number of memory order violations
798system.cpu0.iew.predictedTakenIncorrect 2237378 # Number of branches that were predicted taken incorrectly
799system.cpu0.iew.predictedNotTakenIncorrect 3184169 # Number of branches that were predicted not taken incorrectly
800system.cpu0.iew.branchMispredicts 5421547 # Number of branch mispredicts detected at execute
801system.cpu0.iew.iewExecutedInsts 639276531 # Number of executed instructions
802system.cpu0.iew.iewExecLoadInsts 109409199 # Number of load instructions executed
803system.cpu0.iew.iewExecSquashedInsts 7914356 # Number of squashed instructions skipped in execute
804system.cpu0.iew.exec_swp 0 # number of swp insts executed
805system.cpu0.iew.exec_nop 129577 # number of nop insts executed
806system.cpu0.iew.exec_refs 198721456 # number of memory reference insts executed
807system.cpu0.iew.exec_branches 120519027 # Number of branches executed
808system.cpu0.iew.exec_stores 89312257 # Number of stores executed
809system.cpu0.iew.exec_rate 0.730324 # Inst execution rate
810system.cpu0.iew.wb_sent 630467148 # cumulative count of insts sent to commit
811system.cpu0.iew.wb_count 629627091 # cumulative count of insts written-back
812system.cpu0.iew.wb_producers 306648182 # num instructions producing a value
813system.cpu0.iew.wb_consumers 503078288 # num instructions consuming a value
814system.cpu0.iew.wb_rate 0.719300 # insts written-back per cycle
815system.cpu0.iew.wb_fanout 0.609544 # average fanout of values written-back
816system.cpu0.commit.commitSquashedInsts 51710398 # The number of squashed insts skipped by commit
817system.cpu0.commit.commitNonSpecStalls 16350778 # The number of times commit has been forced to stall to communicate backwards
818system.cpu0.commit.branchMispredicts 5090591 # The number of times a branch was mispredicted
819system.cpu0.commit.committed_per_cycle::samples 832883786 # Number of insts commited each cycle
820system.cpu0.commit.committed_per_cycle::mean 0.721389 # Number of insts commited each cycle
821system.cpu0.commit.committed_per_cycle::stdev 1.530255 # Number of insts commited each cycle
822system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
823system.cpu0.commit.committed_per_cycle::0 570514920 68.50% 68.50% # Number of insts commited each cycle
824system.cpu0.commit.committed_per_cycle::1 134700149 16.17% 84.67% # Number of insts commited each cycle
825system.cpu0.commit.committed_per_cycle::2 59058098 7.09% 91.76% # Number of insts commited each cycle
826system.cpu0.commit.committed_per_cycle::3 19776256 2.37% 94.14% # Number of insts commited each cycle
827system.cpu0.commit.committed_per_cycle::4 14036208 1.69% 95.82% # Number of insts commited each cycle
828system.cpu0.commit.committed_per_cycle::5 9662272 1.16% 96.98% # Number of insts commited each cycle
829system.cpu0.commit.committed_per_cycle::6 6431324 0.77% 97.75% # Number of insts commited each cycle
830system.cpu0.commit.committed_per_cycle::7 3992857 0.48% 98.23% # Number of insts commited each cycle
831system.cpu0.commit.committed_per_cycle::8 14711702 1.77% 100.00% # Number of insts commited each cycle
832system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
833system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
834system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
835system.cpu0.commit.committed_per_cycle::total 832883786 # Number of insts commited each cycle
836system.cpu0.commit.committedInsts 511876907 # Number of instructions committed
837system.cpu0.commit.committedOps 600832864 # Number of ops (including micro ops) committed
838system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
839system.cpu0.commit.refs 182683437 # Number of memory references committed
840system.cpu0.commit.loads 96000193 # Number of loads committed
841system.cpu0.commit.membars 3986424 # Number of memory barriers committed
842system.cpu0.commit.branches 114418082 # Number of branches committed
843system.cpu0.commit.fp_insts 535391 # Number of committed floating point instructions.
844system.cpu0.commit.int_insts 551244640 # Number of committed integer instructions.
845system.cpu0.commit.function_calls 15252520 # Number of function calls committed.
846system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
847system.cpu0.commit.op_class_0::IntAlu 416691372 69.35% 69.35% # Class of committed instruction
848system.cpu0.commit.op_class_0::IntMult 1318004 0.22% 69.57% # Class of committed instruction
849system.cpu0.commit.op_class_0::IntDiv 66523 0.01% 69.58% # Class of committed instruction
850system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.58% # Class of committed instruction
851system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.58% # Class of committed instruction
852system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.58% # Class of committed instruction
853system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.58% # Class of committed instruction
854system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.58% # Class of committed instruction
855system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.58% # Class of committed instruction
856system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.58% # Class of committed instruction
857system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.58% # Class of committed instruction
858system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.58% # Class of committed instruction
859system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.58% # Class of committed instruction
860system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.58% # Class of committed instruction
861system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.58% # Class of committed instruction
862system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.58% # Class of committed instruction
863system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.58% # Class of committed instruction
864system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.58% # Class of committed instruction
865system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.58% # Class of committed instruction
866system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.58% # Class of committed instruction
867system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.58% # Class of committed instruction
868system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.58% # Class of committed instruction
869system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.58% # Class of committed instruction
870system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.58% # Class of committed instruction
871system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.58% # Class of committed instruction
872system.cpu0.commit.op_class_0::SimdFloatMisc 73528 0.01% 69.59% # Class of committed instruction
873system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.59% # Class of committed instruction
874system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.59% # Class of committed instruction
875system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.59% # Class of committed instruction
876system.cpu0.commit.op_class_0::MemRead 96000193 15.98% 85.57% # Class of committed instruction
877system.cpu0.commit.op_class_0::MemWrite 86683244 14.43% 100.00% # Class of committed instruction
878system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
879system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
880system.cpu0.commit.op_class_0::total 600832864 # Class of committed instruction
881system.cpu0.commit.bw_lim_events 14711702 # number cycles where commit BW limit reached
882system.cpu0.rob.rob_reads 1466105636 # The number of ROB reads
883system.cpu0.rob.rob_writes 1314872451 # The number of ROB writes
884system.cpu0.timesIdled 1097159 # Number of times that the entire CPU went into an idle state and unscheduled itself
885system.cpu0.idleCycles 32625462 # Total number of cycles that the CPU has spent unscheduled due to idling
886system.cpu0.quiesceCycles 93833152963 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
887system.cpu0.committedInsts 511876907 # Number of Instructions Simulated
888system.cpu0.committedOps 600832864 # Number of Ops (including micro ops) Simulated
889system.cpu0.cpi 1.710046 # CPI: Cycles Per Instruction
890system.cpu0.cpi_total 1.710046 # CPI: Total CPI of All Threads
891system.cpu0.ipc 0.584780 # IPC: Instructions Per Cycle
892system.cpu0.ipc_total 0.584780 # IPC: Total IPC of All Threads
893system.cpu0.int_regfile_reads 754446272 # number of integer regfile reads
894system.cpu0.int_regfile_writes 448604038 # number of integer regfile writes
895system.cpu0.fp_regfile_reads 881646 # number of floating regfile reads
896system.cpu0.fp_regfile_writes 476304 # number of floating regfile writes
897system.cpu0.cc_regfile_reads 139793568 # number of cc regfile reads
898system.cpu0.cc_regfile_writes 140496633 # number of cc regfile writes
899system.cpu0.misc_regfile_reads 1470350924 # number of misc regfile reads
900system.cpu0.misc_regfile_writes 16456285 # number of misc regfile writes
901system.cpu0.dcache.tags.replacements 6559473 # number of replacements
902system.cpu0.dcache.tags.tagsinuse 490.326221 # Cycle average of tags in use
903system.cpu0.dcache.tags.total_refs 169584910 # Total number of references to valid blocks.
904system.cpu0.dcache.tags.sampled_refs 6559985 # Sample count of references to valid blocks.
905system.cpu0.dcache.tags.avg_refs 25.851417 # Average number of references to valid blocks.
906system.cpu0.dcache.tags.warmup_cycle 2962390000 # Cycle when the warmup percentage was hit.
907system.cpu0.dcache.tags.occ_blocks::cpu0.data 490.326221 # Average occupied blocks per requestor
908system.cpu0.dcache.tags.occ_percent::cpu0.data 0.957668 # Average percentage of cache occupancy
909system.cpu0.dcache.tags.occ_percent::total 0.957668 # Average percentage of cache occupancy
910system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
911system.cpu0.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
912system.cpu0.dcache.tags.age_task_id_blocks_1024::1 382 # Occupied blocks per task id
913system.cpu0.dcache.tags.age_task_id_blocks_1024::2 36 # Occupied blocks per task id
914system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
915system.cpu0.dcache.tags.tag_accesses 379087602 # Number of tag accesses
916system.cpu0.dcache.tags.data_accesses 379087602 # Number of data accesses
917system.cpu0.dcache.ReadReq_hits::cpu0.data 89088742 # number of ReadReq hits
918system.cpu0.dcache.ReadReq_hits::total 89088742 # number of ReadReq hits
919system.cpu0.dcache.WriteReq_hits::cpu0.data 75269986 # number of WriteReq hits
920system.cpu0.dcache.WriteReq_hits::total 75269986 # number of WriteReq hits
921system.cpu0.dcache.SoftPFReq_hits::cpu0.data 228422 # number of SoftPFReq hits
922system.cpu0.dcache.SoftPFReq_hits::total 228422 # number of SoftPFReq hits
923system.cpu0.dcache.WriteLineReq_hits::cpu0.data 263534 # number of WriteLineReq hits
924system.cpu0.dcache.WriteLineReq_hits::total 263534 # number of WriteLineReq hits
925system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1920078 # number of LoadLockedReq hits
926system.cpu0.dcache.LoadLockedReq_hits::total 1920078 # number of LoadLockedReq hits
927system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1972778 # number of StoreCondReq hits
928system.cpu0.dcache.StoreCondReq_hits::total 1972778 # number of StoreCondReq hits
929system.cpu0.dcache.demand_hits::cpu0.data 164358728 # number of demand (read+write) hits
930system.cpu0.dcache.demand_hits::total 164358728 # number of demand (read+write) hits
931system.cpu0.dcache.overall_hits::cpu0.data 164587150 # number of overall hits
932system.cpu0.dcache.overall_hits::total 164587150 # number of overall hits
933system.cpu0.dcache.ReadReq_misses::cpu0.data 7258058 # number of ReadReq misses
934system.cpu0.dcache.ReadReq_misses::total 7258058 # number of ReadReq misses
935system.cpu0.dcache.WriteReq_misses::cpu0.data 8107301 # number of WriteReq misses
936system.cpu0.dcache.WriteReq_misses::total 8107301 # number of WriteReq misses
937system.cpu0.dcache.SoftPFReq_misses::cpu0.data 768102 # number of SoftPFReq misses
938system.cpu0.dcache.SoftPFReq_misses::total 768102 # number of SoftPFReq misses
939system.cpu0.dcache.WriteLineReq_misses::cpu0.data 855425 # number of WriteLineReq misses
940system.cpu0.dcache.WriteLineReq_misses::total 855425 # number of WriteLineReq misses
941system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 287297 # number of LoadLockedReq misses
942system.cpu0.dcache.LoadLockedReq_misses::total 287297 # number of LoadLockedReq misses
943system.cpu0.dcache.StoreCondReq_misses::cpu0.data 193519 # number of StoreCondReq misses
944system.cpu0.dcache.StoreCondReq_misses::total 193519 # number of StoreCondReq misses
945system.cpu0.dcache.demand_misses::cpu0.data 15365359 # number of demand (read+write) misses
946system.cpu0.dcache.demand_misses::total 15365359 # number of demand (read+write) misses
947system.cpu0.dcache.overall_misses::cpu0.data 16133461 # number of overall misses
948system.cpu0.dcache.overall_misses::total 16133461 # number of overall misses
949system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 123043131500 # number of ReadReq miss cycles
950system.cpu0.dcache.ReadReq_miss_latency::total 123043131500 # number of ReadReq miss cycles
951system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 187154125822 # number of WriteReq miss cycles
952system.cpu0.dcache.WriteReq_miss_latency::total 187154125822 # number of WriteReq miss cycles
953system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 92776135134 # number of WriteLineReq miss cycles
954system.cpu0.dcache.WriteLineReq_miss_latency::total 92776135134 # number of WriteLineReq miss cycles
955system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4545100500 # number of LoadLockedReq miss cycles
956system.cpu0.dcache.LoadLockedReq_miss_latency::total 4545100500 # number of LoadLockedReq miss cycles
957system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5540857500 # number of StoreCondReq miss cycles
958system.cpu0.dcache.StoreCondReq_miss_latency::total 5540857500 # number of StoreCondReq miss cycles
959system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 7820000 # number of StoreCondFailReq miss cycles
960system.cpu0.dcache.StoreCondFailReq_miss_latency::total 7820000 # number of StoreCondFailReq miss cycles
961system.cpu0.dcache.demand_miss_latency::cpu0.data 310197257322 # number of demand (read+write) miss cycles
962system.cpu0.dcache.demand_miss_latency::total 310197257322 # number of demand (read+write) miss cycles
963system.cpu0.dcache.overall_miss_latency::cpu0.data 310197257322 # number of overall miss cycles
964system.cpu0.dcache.overall_miss_latency::total 310197257322 # number of overall miss cycles
965system.cpu0.dcache.ReadReq_accesses::cpu0.data 96346800 # number of ReadReq accesses(hits+misses)
966system.cpu0.dcache.ReadReq_accesses::total 96346800 # number of ReadReq accesses(hits+misses)
967system.cpu0.dcache.WriteReq_accesses::cpu0.data 83377287 # number of WriteReq accesses(hits+misses)
968system.cpu0.dcache.WriteReq_accesses::total 83377287 # number of WriteReq accesses(hits+misses)
969system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 996524 # number of SoftPFReq accesses(hits+misses)
970system.cpu0.dcache.SoftPFReq_accesses::total 996524 # number of SoftPFReq accesses(hits+misses)
971system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1118959 # number of WriteLineReq accesses(hits+misses)
972system.cpu0.dcache.WriteLineReq_accesses::total 1118959 # number of WriteLineReq accesses(hits+misses)
973system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2207375 # number of LoadLockedReq accesses(hits+misses)
974system.cpu0.dcache.LoadLockedReq_accesses::total 2207375 # number of LoadLockedReq accesses(hits+misses)
975system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2166297 # number of StoreCondReq accesses(hits+misses)
976system.cpu0.dcache.StoreCondReq_accesses::total 2166297 # number of StoreCondReq accesses(hits+misses)
977system.cpu0.dcache.demand_accesses::cpu0.data 179724087 # number of demand (read+write) accesses
978system.cpu0.dcache.demand_accesses::total 179724087 # number of demand (read+write) accesses
979system.cpu0.dcache.overall_accesses::cpu0.data 180720611 # number of overall (read+write) accesses
980system.cpu0.dcache.overall_accesses::total 180720611 # number of overall (read+write) accesses
981system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075333 # miss rate for ReadReq accesses
982system.cpu0.dcache.ReadReq_miss_rate::total 0.075333 # miss rate for ReadReq accesses
983system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.097236 # miss rate for WriteReq accesses
984system.cpu0.dcache.WriteReq_miss_rate::total 0.097236 # miss rate for WriteReq accesses
985system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770781 # miss rate for SoftPFReq accesses
986system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770781 # miss rate for SoftPFReq accesses
987system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.764483 # miss rate for WriteLineReq accesses
988system.cpu0.dcache.WriteLineReq_miss_rate::total 0.764483 # miss rate for WriteLineReq accesses
989system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.130153 # miss rate for LoadLockedReq accesses
990system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.130153 # miss rate for LoadLockedReq accesses
991system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089332 # miss rate for StoreCondReq accesses
992system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089332 # miss rate for StoreCondReq accesses
993system.cpu0.dcache.demand_miss_rate::cpu0.data 0.085494 # miss rate for demand accesses
994system.cpu0.dcache.demand_miss_rate::total 0.085494 # miss rate for demand accesses
995system.cpu0.dcache.overall_miss_rate::cpu0.data 0.089273 # miss rate for overall accesses
996system.cpu0.dcache.overall_miss_rate::total 0.089273 # miss rate for overall accesses
997system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16952.624449 # average ReadReq miss latency
998system.cpu0.dcache.ReadReq_avg_miss_latency::total 16952.624449 # average ReadReq miss latency
999system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23084.640107 # average WriteReq miss latency
1000system.cpu0.dcache.WriteReq_avg_miss_latency::total 23084.640107 # average WriteReq miss latency
1001system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 108456.188601 # average WriteLineReq miss latency
1002system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 108456.188601 # average WriteLineReq miss latency
1003system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15820.215665 # average LoadLockedReq miss latency
1004system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15820.215665 # average LoadLockedReq miss latency
1005system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28632.111059 # average StoreCondReq miss latency
1006system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28632.111059 # average StoreCondReq miss latency
1007system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
1008system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1009system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20188.090452 # average overall miss latency
1010system.cpu0.dcache.demand_avg_miss_latency::total 20188.090452 # average overall miss latency
1011system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19226.950579 # average overall miss latency
1012system.cpu0.dcache.overall_avg_miss_latency::total 19226.950579 # average overall miss latency
1013system.cpu0.dcache.blocked_cycles::no_mshrs 29213495 # number of cycles access was blocked
1014system.cpu0.dcache.blocked_cycles::no_targets 28830141 # number of cycles access was blocked
1015system.cpu0.dcache.blocked::no_mshrs 790800 # number of cycles access was blocked
1016system.cpu0.dcache.blocked::no_targets 799061 # number of cycles access was blocked
1017system.cpu0.dcache.avg_blocked_cycles::no_mshrs 36.941698 # average number of cycles each access was blocked
1018system.cpu0.dcache.avg_blocked_cycles::no_targets 36.080025 # average number of cycles each access was blocked
1019system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1020system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1021system.cpu0.dcache.writebacks::writebacks 6559531 # number of writebacks
1022system.cpu0.dcache.writebacks::total 6559531 # number of writebacks
1023system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3685333 # number of ReadReq MSHR hits
1024system.cpu0.dcache.ReadReq_mshr_hits::total 3685333 # number of ReadReq MSHR hits
1025system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6510101 # number of WriteReq MSHR hits
1026system.cpu0.dcache.WriteReq_mshr_hits::total 6510101 # number of WriteReq MSHR hits
1027system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4620 # number of WriteLineReq MSHR hits
1028system.cpu0.dcache.WriteLineReq_mshr_hits::total 4620 # number of WriteLineReq MSHR hits
1029system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 146516 # number of LoadLockedReq MSHR hits
1030system.cpu0.dcache.LoadLockedReq_mshr_hits::total 146516 # number of LoadLockedReq MSHR hits
1031system.cpu0.dcache.demand_mshr_hits::cpu0.data 10195434 # number of demand (read+write) MSHR hits
1032system.cpu0.dcache.demand_mshr_hits::total 10195434 # number of demand (read+write) MSHR hits
1033system.cpu0.dcache.overall_mshr_hits::cpu0.data 10195434 # number of overall MSHR hits
1034system.cpu0.dcache.overall_mshr_hits::total 10195434 # number of overall MSHR hits
1035system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3572725 # number of ReadReq MSHR misses
1036system.cpu0.dcache.ReadReq_mshr_misses::total 3572725 # number of ReadReq MSHR misses
1037system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1597200 # number of WriteReq MSHR misses
1038system.cpu0.dcache.WriteReq_mshr_misses::total 1597200 # number of WriteReq MSHR misses
1039system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 761247 # number of SoftPFReq MSHR misses
1040system.cpu0.dcache.SoftPFReq_mshr_misses::total 761247 # number of SoftPFReq MSHR misses
1041system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 850805 # number of WriteLineReq MSHR misses
1042system.cpu0.dcache.WriteLineReq_mshr_misses::total 850805 # number of WriteLineReq MSHR misses
1043system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 140781 # number of LoadLockedReq MSHR misses
1044system.cpu0.dcache.LoadLockedReq_mshr_misses::total 140781 # number of LoadLockedReq MSHR misses
1045system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 193511 # number of StoreCondReq MSHR misses
1046system.cpu0.dcache.StoreCondReq_mshr_misses::total 193511 # number of StoreCondReq MSHR misses
1047system.cpu0.dcache.demand_mshr_misses::cpu0.data 5169925 # number of demand (read+write) MSHR misses
1048system.cpu0.dcache.demand_mshr_misses::total 5169925 # number of demand (read+write) MSHR misses
1049system.cpu0.dcache.overall_mshr_misses::cpu0.data 5931172 # number of overall MSHR misses
1050system.cpu0.dcache.overall_mshr_misses::total 5931172 # number of overall MSHR misses
1051system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32878 # number of ReadReq MSHR uncacheable
1052system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32878 # number of ReadReq MSHR uncacheable
1053system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32941 # number of WriteReq MSHR uncacheable
1054system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32941 # number of WriteReq MSHR uncacheable
1055system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65819 # number of overall MSHR uncacheable misses
1056system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65819 # number of overall MSHR uncacheable misses
1057system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 56556979500 # number of ReadReq MSHR miss cycles
1058system.cpu0.dcache.ReadReq_mshr_miss_latency::total 56556979500 # number of ReadReq MSHR miss cycles
1059system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 42701336905 # number of WriteReq MSHR miss cycles
1060system.cpu0.dcache.WriteReq_mshr_miss_latency::total 42701336905 # number of WriteReq MSHR miss cycles
1061system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18998780500 # number of SoftPFReq MSHR miss cycles
1062system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18998780500 # number of SoftPFReq MSHR miss cycles
1063system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 91672230134 # number of WriteLineReq MSHR miss cycles
1064system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 91672230134 # number of WriteLineReq MSHR miss cycles
1065system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2014552000 # number of LoadLockedReq MSHR miss cycles
1066system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2014552000 # number of LoadLockedReq MSHR miss cycles
1067system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5347454500 # number of StoreCondReq MSHR miss cycles
1068system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5347454500 # number of StoreCondReq MSHR miss cycles
1069system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 7712000 # number of StoreCondFailReq MSHR miss cycles
1070system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 7712000 # number of StoreCondFailReq MSHR miss cycles
1071system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 99258316405 # number of demand (read+write) MSHR miss cycles
1072system.cpu0.dcache.demand_mshr_miss_latency::total 99258316405 # number of demand (read+write) MSHR miss cycles
1073system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 118257096905 # number of overall MSHR miss cycles
1074system.cpu0.dcache.overall_mshr_miss_latency::total 118257096905 # number of overall MSHR miss cycles
1075system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6293183000 # number of ReadReq MSHR uncacheable cycles
1076system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6293183000 # number of ReadReq MSHR uncacheable cycles
1077system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 6230446500 # number of WriteReq MSHR uncacheable cycles
1078system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6230446500 # number of WriteReq MSHR uncacheable cycles
1079system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12523629500 # number of overall MSHR uncacheable cycles
1080system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12523629500 # number of overall MSHR uncacheable cycles
1081system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037082 # mshr miss rate for ReadReq accesses
1082system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037082 # mshr miss rate for ReadReq accesses
1083system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019156 # mshr miss rate for WriteReq accesses
1084system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019156 # mshr miss rate for WriteReq accesses
1085system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.763902 # mshr miss rate for SoftPFReq accesses
1086system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.763902 # mshr miss rate for SoftPFReq accesses
1087system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.760354 # mshr miss rate for WriteLineReq accesses
1088system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.760354 # mshr miss rate for WriteLineReq accesses
1089system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063778 # mshr miss rate for LoadLockedReq accesses
1090system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063778 # mshr miss rate for LoadLockedReq accesses
1091system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089328 # mshr miss rate for StoreCondReq accesses
1092system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089328 # mshr miss rate for StoreCondReq accesses
1093system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028766 # mshr miss rate for demand accesses
1094system.cpu0.dcache.demand_mshr_miss_rate::total 0.028766 # mshr miss rate for demand accesses
1095system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032820 # mshr miss rate for overall accesses
1096system.cpu0.dcache.overall_mshr_miss_rate::total 0.032820 # mshr miss rate for overall accesses
1097system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15830.207895 # average ReadReq mshr miss latency
1098system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15830.207895 # average ReadReq mshr miss latency
1099system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26735.122029 # average WriteReq mshr miss latency
1100system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26735.122029 # average WriteReq mshr miss latency
1101system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24957.445481 # average SoftPFReq mshr miss latency
1102system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24957.445481 # average SoftPFReq mshr miss latency
1103system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 107747.639158 # average WriteLineReq mshr miss latency
1104system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 107747.639158 # average WriteLineReq mshr miss latency
1105system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14309.828741 # average LoadLockedReq mshr miss latency
1106system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14309.828741 # average LoadLockedReq mshr miss latency
1107system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27633.852856 # average StoreCondReq mshr miss latency
1108system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27633.852856 # average StoreCondReq mshr miss latency
1109system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
1110system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1111system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19199.179177 # average overall mshr miss latency
1112system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19199.179177 # average overall mshr miss latency
1113system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19938.234282 # average overall mshr miss latency
1114system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19938.234282 # average overall mshr miss latency
1115system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191410.152686 # average ReadReq mshr uncacheable latency
1116system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191410.152686 # average ReadReq mshr uncacheable latency
1117system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189139.567712 # average WriteReq mshr uncacheable latency
1118system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189139.567712 # average WriteReq mshr uncacheable latency
1119system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190273.773530 # average overall mshr uncacheable latency
1120system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190273.773530 # average overall mshr uncacheable latency
1121system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1122system.cpu0.icache.tags.replacements 6707377 # number of replacements
1123system.cpu0.icache.tags.tagsinuse 511.936942 # Cycle average of tags in use
1124system.cpu0.icache.tags.total_refs 228724396 # Total number of references to valid blocks.
1125system.cpu0.icache.tags.sampled_refs 6707889 # Sample count of references to valid blocks.
1126system.cpu0.icache.tags.avg_refs 34.097821 # Average number of references to valid blocks.
1127system.cpu0.icache.tags.warmup_cycle 21622819000 # Cycle when the warmup percentage was hit.
1128system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.936942 # Average occupied blocks per requestor
1129system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999877 # Average percentage of cache occupancy
1130system.cpu0.icache.tags.occ_percent::total 0.999877 # Average percentage of cache occupancy
1131system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1132system.cpu0.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
1133system.cpu0.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
1134system.cpu0.icache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id
1135system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1136system.cpu0.icache.tags.tag_accesses 478348155 # Number of tag accesses
1137system.cpu0.icache.tags.data_accesses 478348155 # Number of data accesses
1138system.cpu0.icache.ReadReq_hits::cpu0.inst 228724396 # number of ReadReq hits
1139system.cpu0.icache.ReadReq_hits::total 228724396 # number of ReadReq hits
1140system.cpu0.icache.demand_hits::cpu0.inst 228724396 # number of demand (read+write) hits
1141system.cpu0.icache.demand_hits::total 228724396 # number of demand (read+write) hits
1142system.cpu0.icache.overall_hits::cpu0.inst 228724396 # number of overall hits
1143system.cpu0.icache.overall_hits::total 228724396 # number of overall hits
1144system.cpu0.icache.ReadReq_misses::cpu0.inst 7095721 # number of ReadReq misses
1145system.cpu0.icache.ReadReq_misses::total 7095721 # number of ReadReq misses
1146system.cpu0.icache.demand_misses::cpu0.inst 7095721 # number of demand (read+write) misses
1147system.cpu0.icache.demand_misses::total 7095721 # number of demand (read+write) misses
1148system.cpu0.icache.overall_misses::cpu0.inst 7095721 # number of overall misses
1149system.cpu0.icache.overall_misses::total 7095721 # number of overall misses
1150system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 79714633751 # number of ReadReq miss cycles
1151system.cpu0.icache.ReadReq_miss_latency::total 79714633751 # number of ReadReq miss cycles
1152system.cpu0.icache.demand_miss_latency::cpu0.inst 79714633751 # number of demand (read+write) miss cycles
1153system.cpu0.icache.demand_miss_latency::total 79714633751 # number of demand (read+write) miss cycles
1154system.cpu0.icache.overall_miss_latency::cpu0.inst 79714633751 # number of overall miss cycles
1155system.cpu0.icache.overall_miss_latency::total 79714633751 # number of overall miss cycles
1156system.cpu0.icache.ReadReq_accesses::cpu0.inst 235820117 # number of ReadReq accesses(hits+misses)
1157system.cpu0.icache.ReadReq_accesses::total 235820117 # number of ReadReq accesses(hits+misses)
1158system.cpu0.icache.demand_accesses::cpu0.inst 235820117 # number of demand (read+write) accesses
1159system.cpu0.icache.demand_accesses::total 235820117 # number of demand (read+write) accesses
1160system.cpu0.icache.overall_accesses::cpu0.inst 235820117 # number of overall (read+write) accesses
1161system.cpu0.icache.overall_accesses::total 235820117 # number of overall (read+write) accesses
1162system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.030090 # miss rate for ReadReq accesses
1163system.cpu0.icache.ReadReq_miss_rate::total 0.030090 # miss rate for ReadReq accesses
1164system.cpu0.icache.demand_miss_rate::cpu0.inst 0.030090 # miss rate for demand accesses
1165system.cpu0.icache.demand_miss_rate::total 0.030090 # miss rate for demand accesses
1166system.cpu0.icache.overall_miss_rate::cpu0.inst 0.030090 # miss rate for overall accesses
1167system.cpu0.icache.overall_miss_rate::total 0.030090 # miss rate for overall accesses
1168system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11234.183778 # average ReadReq miss latency
1169system.cpu0.icache.ReadReq_avg_miss_latency::total 11234.183778 # average ReadReq miss latency
1170system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11234.183778 # average overall miss latency
1171system.cpu0.icache.demand_avg_miss_latency::total 11234.183778 # average overall miss latency
1172system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11234.183778 # average overall miss latency
1173system.cpu0.icache.overall_avg_miss_latency::total 11234.183778 # average overall miss latency
1174system.cpu0.icache.blocked_cycles::no_mshrs 12261513 # number of cycles access was blocked
1175system.cpu0.icache.blocked_cycles::no_targets 1787 # number of cycles access was blocked
1176system.cpu0.icache.blocked::no_mshrs 839174 # number of cycles access was blocked
1177system.cpu0.icache.blocked::no_targets 14 # number of cycles access was blocked
1178system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.611407 # average number of cycles each access was blocked
1179system.cpu0.icache.avg_blocked_cycles::no_targets 127.642857 # average number of cycles each access was blocked
1180system.cpu0.icache.fast_writes 0 # number of fast writes performed
1181system.cpu0.icache.cache_copies 0 # number of cache copies performed
1182system.cpu0.icache.writebacks::writebacks 6707377 # number of writebacks
1183system.cpu0.icache.writebacks::total 6707377 # number of writebacks
1184system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 387800 # number of ReadReq MSHR hits
1185system.cpu0.icache.ReadReq_mshr_hits::total 387800 # number of ReadReq MSHR hits
1186system.cpu0.icache.demand_mshr_hits::cpu0.inst 387800 # number of demand (read+write) MSHR hits
1187system.cpu0.icache.demand_mshr_hits::total 387800 # number of demand (read+write) MSHR hits
1188system.cpu0.icache.overall_mshr_hits::cpu0.inst 387800 # number of overall MSHR hits
1189system.cpu0.icache.overall_mshr_hits::total 387800 # number of overall MSHR hits
1190system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6707921 # number of ReadReq MSHR misses
1191system.cpu0.icache.ReadReq_mshr_misses::total 6707921 # number of ReadReq MSHR misses
1192system.cpu0.icache.demand_mshr_misses::cpu0.inst 6707921 # number of demand (read+write) MSHR misses
1193system.cpu0.icache.demand_mshr_misses::total 6707921 # number of demand (read+write) MSHR misses
1194system.cpu0.icache.overall_mshr_misses::cpu0.inst 6707921 # number of overall MSHR misses
1195system.cpu0.icache.overall_mshr_misses::total 6707921 # number of overall MSHR misses
1196system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
1197system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable
1198system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
1199system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses
1200system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 71756007072 # number of ReadReq MSHR miss cycles
1201system.cpu0.icache.ReadReq_mshr_miss_latency::total 71756007072 # number of ReadReq MSHR miss cycles
1202system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 71756007072 # number of demand (read+write) MSHR miss cycles
1203system.cpu0.icache.demand_mshr_miss_latency::total 71756007072 # number of demand (read+write) MSHR miss cycles
1204system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 71756007072 # number of overall MSHR miss cycles
1205system.cpu0.icache.overall_mshr_miss_latency::total 71756007072 # number of overall MSHR miss cycles
1206system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of ReadReq MSHR uncacheable cycles
1207system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939780998 # number of ReadReq MSHR uncacheable cycles
1208system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of overall MSHR uncacheable cycles
1209system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939780998 # number of overall MSHR uncacheable cycles
1210system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028445 # mshr miss rate for ReadReq accesses
1211system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028445 # mshr miss rate for ReadReq accesses
1212system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028445 # mshr miss rate for demand accesses
1213system.cpu0.icache.demand_mshr_miss_rate::total 0.028445 # mshr miss rate for demand accesses
1214system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028445 # mshr miss rate for overall accesses
1215system.cpu0.icache.overall_mshr_miss_rate::total 0.028445 # mshr miss rate for overall accesses
1216system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10697.205151 # average ReadReq mshr miss latency
1217system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10697.205151 # average ReadReq mshr miss latency
1218system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10697.205151 # average overall mshr miss latency
1219system.cpu0.icache.demand_avg_mshr_miss_latency::total 10697.205151 # average overall mshr miss latency
1220system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10697.205151 # average overall mshr miss latency
1221system.cpu0.icache.overall_avg_mshr_miss_latency::total 10697.205151 # average overall mshr miss latency
1222system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average ReadReq mshr uncacheable latency
1223system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.260132 # average ReadReq mshr uncacheable latency
1224system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average overall mshr uncacheable latency
1225system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.260132 # average overall mshr uncacheable latency
1226system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1227system.cpu0.l2cache.prefetcher.num_hwpf_issued 8921966 # number of hwpf issued
1228system.cpu0.l2cache.prefetcher.pfIdentified 8932201 # number of prefetch candidates identified
1229system.cpu0.l2cache.prefetcher.pfBufferHit 9178 # number of redundant prefetches already in prefetch queue
1230system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1231system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1232system.cpu0.l2cache.prefetcher.pfSpanPage 1125087 # number of prefetches not generated due to page crossing
1233system.cpu0.l2cache.tags.replacements 2909208 # number of replacements
1234system.cpu0.l2cache.tags.tagsinuse 16158.656650 # Cycle average of tags in use
1235system.cpu0.l2cache.tags.total_refs 19404404 # Total number of references to valid blocks.
1236system.cpu0.l2cache.tags.sampled_refs 2925253 # Sample count of references to valid blocks.
1237system.cpu0.l2cache.tags.avg_refs 6.633411 # Average number of references to valid blocks.
1238system.cpu0.l2cache.tags.warmup_cycle 3536776000 # Cycle when the warmup percentage was hit.
1239system.cpu0.l2cache.tags.occ_blocks::writebacks 15221.688116 # Average occupied blocks per requestor
1240system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.041534 # Average occupied blocks per requestor
1241system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 63.344722 # Average occupied blocks per requestor
1242system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000040 # Average occupied blocks per requestor
1243system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 812.582238 # Average occupied blocks per requestor
1244system.cpu0.l2cache.tags.occ_percent::writebacks 0.929058 # Average percentage of cache occupancy
1245system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003726 # Average percentage of cache occupancy
1246system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003866 # Average percentage of cache occupancy
1247system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy
1248system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.049596 # Average percentage of cache occupancy
1249system.cpu0.l2cache.tags.occ_percent::total 0.986246 # Average percentage of cache occupancy
1250system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1170 # Occupied blocks per task id
1251system.cpu0.l2cache.tags.occ_task_id_blocks::1023 75 # Occupied blocks per task id
1252system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14800 # Occupied blocks per task id
1253system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 10 # Occupied blocks per task id
1254system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 38 # Occupied blocks per task id
1255system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 178 # Occupied blocks per task id
1256system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 606 # Occupied blocks per task id
1257system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 338 # Occupied blocks per task id
1258system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
1259system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id
1260system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id
1261system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id
1262system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
1263system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1308 # Occupied blocks per task id
1264system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5860 # Occupied blocks per task id
1265system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4512 # Occupied blocks per task id
1266system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3004 # Occupied blocks per task id
1267system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.071411 # Percentage of cache occupancy per task id
1268system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004578 # Percentage of cache occupancy per task id
1269system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.903320 # Percentage of cache occupancy per task id
1270system.cpu0.l2cache.tags.tag_accesses 454144773 # Number of tag accesses
1271system.cpu0.l2cache.tags.data_accesses 454144773 # Number of data accesses
1272system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 651189 # number of ReadReq hits
1273system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 209837 # number of ReadReq hits
1274system.cpu0.l2cache.ReadReq_hits::total 861026 # number of ReadReq hits
1275system.cpu0.l2cache.WritebackDirty_hits::writebacks 4295929 # number of WritebackDirty hits
1276system.cpu0.l2cache.WritebackDirty_hits::total 4295929 # number of WritebackDirty hits
1277system.cpu0.l2cache.WritebackClean_hits::writebacks 8968573 # number of WritebackClean hits
1278system.cpu0.l2cache.WritebackClean_hits::total 8968573 # number of WritebackClean hits
1279system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 805 # number of UpgradeReq hits
1280system.cpu0.l2cache.UpgradeReq_hits::total 805 # number of UpgradeReq hits
1281system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits
1282system.cpu0.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
1283system.cpu0.l2cache.ReadExReq_hits::cpu0.data 980855 # number of ReadExReq hits
1284system.cpu0.l2cache.ReadExReq_hits::total 980855 # number of ReadExReq hits
1285system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 6087853 # number of ReadCleanReq hits
1286system.cpu0.l2cache.ReadCleanReq_hits::total 6087853 # number of ReadCleanReq hits
1287system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3397389 # number of ReadSharedReq hits
1288system.cpu0.l2cache.ReadSharedReq_hits::total 3397389 # number of ReadSharedReq hits
1289system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 211269 # number of InvalidateReq hits
1290system.cpu0.l2cache.InvalidateReq_hits::total 211269 # number of InvalidateReq hits
1291system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 651189 # number of demand (read+write) hits
1292system.cpu0.l2cache.demand_hits::cpu0.itb.walker 209837 # number of demand (read+write) hits
1293system.cpu0.l2cache.demand_hits::cpu0.inst 6087853 # number of demand (read+write) hits
1294system.cpu0.l2cache.demand_hits::cpu0.data 4378244 # number of demand (read+write) hits
1295system.cpu0.l2cache.demand_hits::total 11327123 # number of demand (read+write) hits
1296system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 651189 # number of overall hits
1297system.cpu0.l2cache.overall_hits::cpu0.itb.walker 209837 # number of overall hits
1298system.cpu0.l2cache.overall_hits::cpu0.inst 6087853 # number of overall hits
1299system.cpu0.l2cache.overall_hits::cpu0.data 4378244 # number of overall hits
1300system.cpu0.l2cache.overall_hits::total 11327123 # number of overall hits
1301system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13609 # number of ReadReq misses
1302system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10441 # number of ReadReq misses
1303system.cpu0.l2cache.ReadReq_misses::total 24050 # number of ReadReq misses
1304system.cpu0.l2cache.WritebackDirty_misses::writebacks 4 # number of WritebackDirty misses
1305system.cpu0.l2cache.WritebackDirty_misses::total 4 # number of WritebackDirty misses
1306system.cpu0.l2cache.WritebackClean_misses::writebacks 2 # number of WritebackClean misses
1307system.cpu0.l2cache.WritebackClean_misses::total 2 # number of WritebackClean misses
1308system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 266523 # number of UpgradeReq misses
1309system.cpu0.l2cache.UpgradeReq_misses::total 266523 # number of UpgradeReq misses
1310system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 193497 # number of SCUpgradeReq misses
1311system.cpu0.l2cache.SCUpgradeReq_misses::total 193497 # number of SCUpgradeReq misses
1312system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 13 # number of SCUpgradeFailReq misses
1313system.cpu0.l2cache.SCUpgradeFailReq_misses::total 13 # number of SCUpgradeFailReq misses
1314system.cpu0.l2cache.ReadExReq_misses::cpu0.data 359046 # number of ReadExReq misses
1315system.cpu0.l2cache.ReadExReq_misses::total 359046 # number of ReadExReq misses
1316system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 620051 # number of ReadCleanReq misses
1317system.cpu0.l2cache.ReadCleanReq_misses::total 620051 # number of ReadCleanReq misses
1318system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1074980 # number of ReadSharedReq misses
1319system.cpu0.l2cache.ReadSharedReq_misses::total 1074980 # number of ReadSharedReq misses
1320system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 637513 # number of InvalidateReq misses
1321system.cpu0.l2cache.InvalidateReq_misses::total 637513 # number of InvalidateReq misses
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1329system.cpu0.l2cache.overall_misses::cpu0.inst 620051 # number of overall misses
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1333system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 642927000 # number of ReadReq miss cycles
1334system.cpu0.l2cache.ReadReq_miss_latency::total 1374107000 # number of ReadReq miss cycles
1335system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3539737000 # number of UpgradeReq miss cycles
1336system.cpu0.l2cache.UpgradeReq_miss_latency::total 3539737000 # number of UpgradeReq miss cycles
1337system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2018375000 # number of SCUpgradeReq miss cycles
1338system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2018375000 # number of SCUpgradeReq miss cycles
1339system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 7547996 # number of SCUpgradeFailReq miss cycles
1340system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 7547996 # number of SCUpgradeFailReq miss cycles
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1342system.cpu0.l2cache.ReadExReq_miss_latency::total 23661492999 # number of ReadExReq miss cycles
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1344system.cpu0.l2cache.ReadCleanReq_miss_latency::total 24792926998 # number of ReadCleanReq miss cycles
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1346system.cpu0.l2cache.ReadSharedReq_miss_latency::total 48196505484 # number of ReadSharedReq miss cycles
1347system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 87950874488 # number of InvalidateReq miss cycles
1348system.cpu0.l2cache.InvalidateReq_miss_latency::total 87950874488 # number of InvalidateReq miss cycles
1349system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 731180000 # number of demand (read+write) miss cycles
1350system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 642927000 # number of demand (read+write) miss cycles
1351system.cpu0.l2cache.demand_miss_latency::cpu0.inst 24792926998 # number of demand (read+write) miss cycles
1352system.cpu0.l2cache.demand_miss_latency::cpu0.data 71857998483 # number of demand (read+write) miss cycles
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1354system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 731180000 # number of overall miss cycles
1355system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 642927000 # number of overall miss cycles
1356system.cpu0.l2cache.overall_miss_latency::cpu0.inst 24792926998 # number of overall miss cycles
1357system.cpu0.l2cache.overall_miss_latency::cpu0.data 71857998483 # number of overall miss cycles
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1360system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 220278 # number of ReadReq accesses(hits+misses)
1361system.cpu0.l2cache.ReadReq_accesses::total 885076 # number of ReadReq accesses(hits+misses)
1362system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4295933 # number of WritebackDirty accesses(hits+misses)
1363system.cpu0.l2cache.WritebackDirty_accesses::total 4295933 # number of WritebackDirty accesses(hits+misses)
1364system.cpu0.l2cache.WritebackClean_accesses::writebacks 8968575 # number of WritebackClean accesses(hits+misses)
1365system.cpu0.l2cache.WritebackClean_accesses::total 8968575 # number of WritebackClean accesses(hits+misses)
1366system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 267328 # number of UpgradeReq accesses(hits+misses)
1367system.cpu0.l2cache.UpgradeReq_accesses::total 267328 # number of UpgradeReq accesses(hits+misses)
1368system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 193498 # number of SCUpgradeReq accesses(hits+misses)
1369system.cpu0.l2cache.SCUpgradeReq_accesses::total 193498 # number of SCUpgradeReq accesses(hits+misses)
1370system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 13 # number of SCUpgradeFailReq accesses(hits+misses)
1371system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 13 # number of SCUpgradeFailReq accesses(hits+misses)
1372system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1339901 # number of ReadExReq accesses(hits+misses)
1373system.cpu0.l2cache.ReadExReq_accesses::total 1339901 # number of ReadExReq accesses(hits+misses)
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1375system.cpu0.l2cache.ReadCleanReq_accesses::total 6707904 # number of ReadCleanReq accesses(hits+misses)
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1377system.cpu0.l2cache.ReadSharedReq_accesses::total 4472369 # number of ReadSharedReq accesses(hits+misses)
1378system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 848782 # number of InvalidateReq accesses(hits+misses)
1379system.cpu0.l2cache.InvalidateReq_accesses::total 848782 # number of InvalidateReq accesses(hits+misses)
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1381system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 220278 # number of demand (read+write) accesses
1382system.cpu0.l2cache.demand_accesses::cpu0.inst 6707904 # number of demand (read+write) accesses
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1386system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 220278 # number of overall (read+write) accesses
1387system.cpu0.l2cache.overall_accesses::cpu0.inst 6707904 # number of overall (read+write) accesses
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1391system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.047399 # miss rate for ReadReq accesses
1392system.cpu0.l2cache.ReadReq_miss_rate::total 0.027173 # miss rate for ReadReq accesses
1393system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses
1394system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses
1395system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses
1396system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses
1397system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.996989 # miss rate for UpgradeReq accesses
1398system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.996989 # miss rate for UpgradeReq accesses
1399system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999995 # miss rate for SCUpgradeReq accesses
1400system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999995 # miss rate for SCUpgradeReq accesses
1401system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1402system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
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1404system.cpu0.l2cache.ReadExReq_miss_rate::total 0.267965 # miss rate for ReadExReq accesses
1405system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.092436 # miss rate for ReadCleanReq accesses
1406system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.092436 # miss rate for ReadCleanReq accesses
1407system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.240360 # miss rate for ReadSharedReq accesses
1408system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.240360 # miss rate for ReadSharedReq accesses
1409system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.751092 # miss rate for InvalidateReq accesses
1410system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.751092 # miss rate for InvalidateReq accesses
1411system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020471 # miss rate for demand accesses
1412system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.047399 # miss rate for demand accesses
1413system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.092436 # miss rate for demand accesses
1414system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.246724 # miss rate for demand accesses
1415system.cpu0.l2cache.demand_miss_rate::total 0.155023 # miss rate for demand accesses
1416system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020471 # miss rate for overall accesses
1417system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.047399 # miss rate for overall accesses
1418system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.092436 # miss rate for overall accesses
1419system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.246724 # miss rate for overall accesses
1420system.cpu0.l2cache.overall_miss_rate::total 0.155023 # miss rate for overall accesses
1421system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 53727.680212 # average ReadReq miss latency
1422system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 61577.147783 # average ReadReq miss latency
1423system.cpu0.l2cache.ReadReq_avg_miss_latency::total 57135.426195 # average ReadReq miss latency
1424system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13281.168980 # average UpgradeReq miss latency
1425system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13281.168980 # average UpgradeReq miss latency
1426system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10431.040275 # average SCUpgradeReq miss latency
1427system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10431.040275 # average SCUpgradeReq miss latency
1428system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 580615.076923 # average SCUpgradeFailReq miss latency
1429system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 580615.076923 # average SCUpgradeFailReq miss latency
1430system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 65901.007111 # average ReadExReq miss latency
1431system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 65901.007111 # average ReadExReq miss latency
1432system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39985.302819 # average ReadCleanReq miss latency
1433system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39985.302819 # average ReadCleanReq miss latency
1434system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 44834.792725 # average ReadSharedReq miss latency
1435system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 44834.792725 # average ReadSharedReq miss latency
1436system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 137959.342771 # average InvalidateReq miss latency
1437system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 137959.342771 # average InvalidateReq miss latency
1438system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 53727.680212 # average overall miss latency
1439system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 61577.147783 # average overall miss latency
1440system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39985.302819 # average overall miss latency
1441system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 50109.271717 # average overall miss latency
1442system.cpu0.l2cache.demand_avg_miss_latency::total 47169.895045 # average overall miss latency
1443system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 53727.680212 # average overall miss latency
1444system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 61577.147783 # average overall miss latency
1445system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39985.302819 # average overall miss latency
1446system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 50109.271717 # average overall miss latency
1447system.cpu0.l2cache.overall_avg_miss_latency::total 47169.895045 # average overall miss latency
1448system.cpu0.l2cache.blocked_cycles::no_mshrs 3672 # number of cycles access was blocked
1449system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1450system.cpu0.l2cache.blocked::no_mshrs 25 # number of cycles access was blocked
1451system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1452system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 146.880000 # average number of cycles each access was blocked
1453system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1454system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1455system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1456system.cpu0.l2cache.writebacks::writebacks 1813424 # number of writebacks
1457system.cpu0.l2cache.writebacks::total 1813424 # number of writebacks
1458system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 5 # number of ReadReq MSHR hits
1459system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 178 # number of ReadReq MSHR hits
1460system.cpu0.l2cache.ReadReq_mshr_hits::total 183 # number of ReadReq MSHR hits
1461system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 69322 # number of ReadExReq MSHR hits
1462system.cpu0.l2cache.ReadExReq_mshr_hits::total 69322 # number of ReadExReq MSHR hits
1463system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 4 # number of ReadCleanReq MSHR hits
1464system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits
1465system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 7219 # number of ReadSharedReq MSHR hits
1466system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 7219 # number of ReadSharedReq MSHR hits
1467system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 5 # number of InvalidateReq MSHR hits
1468system.cpu0.l2cache.InvalidateReq_mshr_hits::total 5 # number of InvalidateReq MSHR hits
1469system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 5 # number of demand (read+write) MSHR hits
1470system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 178 # number of demand (read+write) MSHR hits
1471system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits
1472system.cpu0.l2cache.demand_mshr_hits::cpu0.data 76541 # number of demand (read+write) MSHR hits
1473system.cpu0.l2cache.demand_mshr_hits::total 76728 # number of demand (read+write) MSHR hits
1474system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 5 # number of overall MSHR hits
1475system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 178 # number of overall MSHR hits
1476system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits
1477system.cpu0.l2cache.overall_mshr_hits::cpu0.data 76541 # number of overall MSHR hits
1478system.cpu0.l2cache.overall_mshr_hits::total 76728 # number of overall MSHR hits
1479system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 13604 # number of ReadReq MSHR misses
1480system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10263 # number of ReadReq MSHR misses
1481system.cpu0.l2cache.ReadReq_mshr_misses::total 23867 # number of ReadReq MSHR misses
1482system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 4 # number of WritebackDirty MSHR misses
1483system.cpu0.l2cache.WritebackDirty_mshr_misses::total 4 # number of WritebackDirty MSHR misses
1484system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 2 # number of WritebackClean MSHR misses
1485system.cpu0.l2cache.WritebackClean_mshr_misses::total 2 # number of WritebackClean MSHR misses
1486system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 927565 # number of HardPFReq MSHR misses
1487system.cpu0.l2cache.HardPFReq_mshr_misses::total 927565 # number of HardPFReq MSHR misses
1488system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 266523 # number of UpgradeReq MSHR misses
1489system.cpu0.l2cache.UpgradeReq_mshr_misses::total 266523 # number of UpgradeReq MSHR misses
1490system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 193497 # number of SCUpgradeReq MSHR misses
1491system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 193497 # number of SCUpgradeReq MSHR misses
1492system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 13 # number of SCUpgradeFailReq MSHR misses
1493system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 13 # number of SCUpgradeFailReq MSHR misses
1494system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 289724 # number of ReadExReq MSHR misses
1495system.cpu0.l2cache.ReadExReq_mshr_misses::total 289724 # number of ReadExReq MSHR misses
1496system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 620047 # number of ReadCleanReq MSHR misses
1497system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 620047 # number of ReadCleanReq MSHR misses
1498system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1067761 # number of ReadSharedReq MSHR misses
1499system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1067761 # number of ReadSharedReq MSHR misses
1500system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 637508 # number of InvalidateReq MSHR misses
1501system.cpu0.l2cache.InvalidateReq_mshr_misses::total 637508 # number of InvalidateReq MSHR misses
1502system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 13604 # number of demand (read+write) MSHR misses
1503system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10263 # number of demand (read+write) MSHR misses
1504system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 620047 # number of demand (read+write) MSHR misses
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1507system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 13604 # number of overall MSHR misses
1508system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10263 # number of overall MSHR misses
1509system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 620047 # number of overall MSHR misses
1510system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1357485 # number of overall MSHR misses
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1512system.cpu0.l2cache.overall_mshr_misses::total 2928964 # number of overall MSHR misses
1513system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
1514system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32878 # number of ReadReq MSHR uncacheable
1515system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 54171 # number of ReadReq MSHR uncacheable
1516system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32941 # number of WriteReq MSHR uncacheable
1517system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32941 # number of WriteReq MSHR uncacheable
1518system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
1519system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 65819 # number of overall MSHR uncacheable misses
1520system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 87112 # number of overall MSHR uncacheable misses
1521system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 649200000 # number of ReadReq MSHR miss cycles
1522system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 572348000 # number of ReadReq MSHR miss cycles
1523system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1221548000 # number of ReadReq MSHR miss cycles
1524system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 68343452519 # number of HardPFReq MSHR miss cycles
1525system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 68343452519 # number of HardPFReq MSHR miss cycles
1526system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7943943496 # number of UpgradeReq MSHR miss cycles
1527system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7943943496 # number of UpgradeReq MSHR miss cycles
1528system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3893295994 # number of SCUpgradeReq MSHR miss cycles
1529system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3893295994 # number of SCUpgradeReq MSHR miss cycles
1530system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 6899996 # number of SCUpgradeFailReq MSHR miss cycles
1531system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6899996 # number of SCUpgradeFailReq MSHR miss cycles
1532system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 17756340999 # number of ReadExReq MSHR miss cycles
1533system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 17756340999 # number of ReadExReq MSHR miss cycles
1534system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 21072592498 # number of ReadCleanReq MSHR miss cycles
1535system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 21072592498 # number of ReadCleanReq MSHR miss cycles
1536system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 41283242484 # number of ReadSharedReq MSHR miss cycles
1537system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 41283242484 # number of ReadSharedReq MSHR miss cycles
1538system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 84125646988 # number of InvalidateReq MSHR miss cycles
1539system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 84125646988 # number of InvalidateReq MSHR miss cycles
1540system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 649200000 # number of demand (read+write) MSHR miss cycles
1541system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 572348000 # number of demand (read+write) MSHR miss cycles
1542system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 21072592498 # number of demand (read+write) MSHR miss cycles
1543system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 59039583483 # number of demand (read+write) MSHR miss cycles
1544system.cpu0.l2cache.demand_mshr_miss_latency::total 81333723981 # number of demand (read+write) MSHR miss cycles
1545system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 649200000 # number of overall MSHR miss cycles
1546system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 572348000 # number of overall MSHR miss cycles
1547system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 21072592498 # number of overall MSHR miss cycles
1548system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 59039583483 # number of overall MSHR miss cycles
1549system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 68343452519 # number of overall MSHR miss cycles
1550system.cpu0.l2cache.overall_mshr_miss_latency::total 149677176500 # number of overall MSHR miss cycles
1551system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780082500 # number of ReadReq MSHR uncacheable cycles
1552system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6029953000 # number of ReadReq MSHR uncacheable cycles
1553system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8810035500 # number of ReadReq MSHR uncacheable cycles
1554system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5977560967 # number of WriteReq MSHR uncacheable cycles
1555system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5977560967 # number of WriteReq MSHR uncacheable cycles
1556system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 2780082500 # number of overall MSHR uncacheable cycles
1557system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 12007513967 # number of overall MSHR uncacheable cycles
1558system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14787596467 # number of overall MSHR uncacheable cycles
1559system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020463 # mshr miss rate for ReadReq accesses
1560system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.046591 # mshr miss rate for ReadReq accesses
1561system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.026966 # mshr miss rate for ReadReq accesses
1562system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses
1563system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses
1564system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
1565system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
1566system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1567system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1568system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.996989 # mshr miss rate for UpgradeReq accesses
1569system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.996989 # mshr miss rate for UpgradeReq accesses
1570system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999995 # mshr miss rate for SCUpgradeReq accesses
1571system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses
1572system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1573system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1574system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.216228 # mshr miss rate for ReadExReq accesses
1575system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.216228 # mshr miss rate for ReadExReq accesses
1576system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092435 # mshr miss rate for ReadCleanReq accesses
1577system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092435 # mshr miss rate for ReadCleanReq accesses
1578system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.238746 # mshr miss rate for ReadSharedReq accesses
1579system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.238746 # mshr miss rate for ReadSharedReq accesses
1580system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.751086 # mshr miss rate for InvalidateReq accesses
1581system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.751086 # mshr miss rate for InvalidateReq accesses
1582system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.020463 # mshr miss rate for demand accesses
1583system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046591 # mshr miss rate for demand accesses
1584system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092435 # mshr miss rate for demand accesses
1585system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.233555 # mshr miss rate for demand accesses
1586system.cpu0.l2cache.demand_mshr_miss_rate::total 0.149300 # mshr miss rate for demand accesses
1587system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.020463 # mshr miss rate for overall accesses
1588system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046591 # mshr miss rate for overall accesses
1589system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092435 # mshr miss rate for overall accesses
1590system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.233555 # mshr miss rate for overall accesses
1591system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1592system.cpu0.l2cache.overall_mshr_miss_rate::total 0.218494 # mshr miss rate for overall accesses
1593system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 47721.258453 # average ReadReq mshr miss latency
1594system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 55768.098996 # average ReadReq mshr miss latency
1595system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 51181.463946 # average ReadReq mshr miss latency
1596system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 73680.499500 # average HardPFReq mshr miss latency
1597system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 73680.499500 # average HardPFReq mshr miss latency
1598system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29805.846010 # average UpgradeReq mshr miss latency
1599system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29805.846010 # average UpgradeReq mshr miss latency
1600system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20120.704683 # average SCUpgradeReq mshr miss latency
1601system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20120.704683 # average SCUpgradeReq mshr miss latency
1602system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 530768.923077 # average SCUpgradeFailReq mshr miss latency
1603system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 530768.923077 # average SCUpgradeFailReq mshr miss latency
1604system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 61287.090469 # average ReadExReq mshr miss latency
1605system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 61287.090469 # average ReadExReq mshr miss latency
1606system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33985.476098 # average ReadCleanReq mshr miss latency
1607system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33985.476098 # average ReadCleanReq mshr miss latency
1608system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38663.373624 # average ReadSharedReq mshr miss latency
1609system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38663.373624 # average ReadSharedReq mshr miss latency
1610system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 131960.143226 # average InvalidateReq mshr miss latency
1611system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 131960.143226 # average InvalidateReq mshr miss latency
1612system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 47721.258453 # average overall mshr miss latency
1613system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 55768.098996 # average overall mshr miss latency
1614system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33985.476098 # average overall mshr miss latency
1615system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43491.886454 # average overall mshr miss latency
1616system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40638.435405 # average overall mshr miss latency
1617system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 47721.258453 # average overall mshr miss latency
1618system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 55768.098996 # average overall mshr miss latency
1619system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33985.476098 # average overall mshr miss latency
1620system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43491.886454 # average overall mshr miss latency
1621system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 73680.499500 # average overall mshr miss latency
1622system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 51102.429562 # average overall mshr miss latency
1623system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average ReadReq mshr uncacheable latency
1624system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183403.887098 # average ReadReq mshr uncacheable latency
1625system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162633.798527 # average ReadReq mshr uncacheable latency
1626system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181462.644334 # average WriteReq mshr uncacheable latency
1627system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181462.644334 # average WriteReq mshr uncacheable latency
1628system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average overall mshr uncacheable latency
1629system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 182432.336666 # average overall mshr uncacheable latency
1630system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 169753.839505 # average overall mshr uncacheable latency
1631system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1632system.cpu0.toL2Bus.snoop_filter.tot_requests 27467007 # Total number of requests made to the snoop filter.
1633system.cpu0.toL2Bus.snoop_filter.hit_single_requests 14098216 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1634system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2397 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1635system.cpu0.toL2Bus.snoop_filter.tot_snoops 2174971 # Total number of snoops made to the snoop filter.
1636system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2174417 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1637system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 554 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1638system.cpu0.toL2Bus.trans_dist::ReadReq 1027741 # Transaction distribution
1639system.cpu0.toL2Bus.trans_dist::ReadResp 12311555 # Transaction distribution
1640system.cpu0.toL2Bus.trans_dist::WriteReq 32941 # Transaction distribution
1641system.cpu0.toL2Bus.trans_dist::WriteResp 32941 # Transaction distribution
1642system.cpu0.toL2Bus.trans_dist::WritebackDirty 6114023 # Transaction distribution
1643system.cpu0.toL2Bus.trans_dist::WritebackClean 8970970 # Transaction distribution
1644system.cpu0.toL2Bus.trans_dist::CleanEvict 2853143 # Transaction distribution
1645system.cpu0.toL2Bus.trans_dist::HardPFReq 1178619 # Transaction distribution
1646system.cpu0.toL2Bus.trans_dist::HardPFResp 8 # Transaction distribution
1647system.cpu0.toL2Bus.trans_dist::UpgradeReq 489036 # Transaction distribution
1648system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 343853 # Transaction distribution
1649system.cpu0.toL2Bus.trans_dist::UpgradeResp 531725 # Transaction distribution
1650system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 106 # Transaction distribution
1651system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 201 # Transaction distribution
1652system.cpu0.toL2Bus.trans_dist::ReadExReq 1422561 # Transaction distribution
1653system.cpu0.toL2Bus.trans_dist::ReadExResp 1350501 # Transaction distribution
1654system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6707921 # Transaction distribution
1655system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5424362 # Transaction distribution
1656system.cpu0.toL2Bus.trans_dist::InvalidateReq 856015 # Transaction distribution
1657system.cpu0.toL2Bus.trans_dist::InvalidateResp 848782 # Transaction distribution
1658system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20165788 # Packet count per connected master and slave (bytes)
1659system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21120167 # Packet count per connected master and slave (bytes)
1660system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 459340 # Packet count per connected master and slave (bytes)
1661system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1399304 # Packet count per connected master and slave (bytes)
1662system.cpu0.toL2Bus.pkt_count::total 43144599 # Packet count per connected master and slave (bytes)
1663system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 858918672 # Cumulative packet size per connected master and slave (bytes)
1664system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 799305801 # Cumulative packet size per connected master and slave (bytes)
1665system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1762224 # Cumulative packet size per connected master and slave (bytes)
1666system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5318384 # Cumulative packet size per connected master and slave (bytes)
1667system.cpu0.toL2Bus.pkt_size::total 1665305081 # Cumulative packet size per connected master and slave (bytes)
1668system.cpu0.toL2Bus.snoops 7537626 # Total snoops (count)
1669system.cpu0.toL2Bus.snoop_fanout::samples 22154436 # Request fanout histogram
1670system.cpu0.toL2Bus.snoop_fanout::mean 0.115021 # Request fanout histogram
1671system.cpu0.toL2Bus.snoop_fanout::stdev 0.319126 # Request fanout histogram
1672system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1673system.cpu0.toL2Bus.snoop_fanout::0 19606761 88.50% 88.50% # Request fanout histogram
1674system.cpu0.toL2Bus.snoop_fanout::1 2547121 11.50% 100.00% # Request fanout histogram
1675system.cpu0.toL2Bus.snoop_fanout::2 554 0.00% 100.00% # Request fanout histogram
1676system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1677system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1678system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1679system.cpu0.toL2Bus.snoop_fanout::total 22154436 # Request fanout histogram
1680system.cpu0.toL2Bus.reqLayer0.occupancy 27362140922 # Layer occupancy (ticks)
1681system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1682system.cpu0.toL2Bus.snoopLayer0.occupancy 207113536 # Layer occupancy (ticks)
1683system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1684system.cpu0.toL2Bus.respLayer0.occupancy 10089828109 # Layer occupancy (ticks)
1685system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1686system.cpu0.toL2Bus.respLayer1.occupancy 9431575123 # Layer occupancy (ticks)
1687system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1688system.cpu0.toL2Bus.respLayer2.occupancy 239573965 # Layer occupancy (ticks)
1689system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1690system.cpu0.toL2Bus.respLayer3.occupancy 735155181 # Layer occupancy (ticks)
1691system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1692system.cpu1.branchPred.lookups 119891525 # Number of BP lookups
1693system.cpu1.branchPred.condPredicted 80198528 # Number of conditional branches predicted
1694system.cpu1.branchPred.condIncorrect 5904198 # Number of conditional branches incorrect
1695system.cpu1.branchPred.BTBLookups 84182887 # Number of BTB lookups
1696system.cpu1.branchPred.BTBHits 54925615 # Number of BTB hits
1697system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1698system.cpu1.branchPred.BTBHitPct 65.245583 # BTB Hit Percentage
1699system.cpu1.branchPred.usedRAS 16054982 # Number of times the RAS was used to get a target.
1700system.cpu1.branchPred.RASInCorrect 157154 # Number of incorrect RAS predictions.
1701system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1702system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1703system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1704system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1705system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1706system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1707system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1708system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

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1722system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1723system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1724system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1725system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1726system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1727system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1728system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1729system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1730system.cpu1.dtb.walker.walks 523591 # Table walker walks requested
1731system.cpu1.dtb.walker.walksLong 523591 # Table walker walks initiated with long descriptors
1732system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9887 # Level at which table walker walks with long descriptors terminate
1733system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 82113 # Level at which table walker walks with long descriptors terminate
1734system.cpu1.dtb.walker.walksSquashedBefore 242894 # Table walks squashed before starting
1735system.cpu1.dtb.walker.walkWaitTime::samples 280697 # Table walker wait (enqueue to first request) latency
1736system.cpu1.dtb.walker.walkWaitTime::mean 2503.193835 # Table walker wait (enqueue to first request) latency
1737system.cpu1.dtb.walker.walkWaitTime::stdev 14937.525211 # Table walker wait (enqueue to first request) latency
1738system.cpu1.dtb.walker.walkWaitTime::0-65535 278494 99.22% 99.22% # Table walker wait (enqueue to first request) latency
1739system.cpu1.dtb.walker.walkWaitTime::65536-131071 1255 0.45% 99.66% # Table walker wait (enqueue to first request) latency
1740system.cpu1.dtb.walker.walkWaitTime::131072-196607 659 0.23% 99.90% # Table walker wait (enqueue to first request) latency
1741system.cpu1.dtb.walker.walkWaitTime::196608-262143 166 0.06% 99.96% # Table walker wait (enqueue to first request) latency
1742system.cpu1.dtb.walker.walkWaitTime::262144-327679 38 0.01% 99.97% # Table walker wait (enqueue to first request) latency
1743system.cpu1.dtb.walker.walkWaitTime::327680-393215 57 0.02% 99.99% # Table walker wait (enqueue to first request) latency
1744system.cpu1.dtb.walker.walkWaitTime::393216-458751 13 0.00% 99.99% # Table walker wait (enqueue to first request) latency
1745system.cpu1.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1746system.cpu1.dtb.walker.walkWaitTime::524288-589823 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1747system.cpu1.dtb.walker.walkWaitTime::589824-655359 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1748system.cpu1.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1749system.cpu1.dtb.walker.walkWaitTime::total 280697 # Table walker wait (enqueue to first request) latency
1750system.cpu1.dtb.walker.walkCompletionTime::samples 263545 # Table walker service (enqueue to completion) latency
1751system.cpu1.dtb.walker.walkCompletionTime::mean 19785.484452 # Table walker service (enqueue to completion) latency
1752system.cpu1.dtb.walker.walkCompletionTime::gmean 17259.480271 # Table walker service (enqueue to completion) latency
1753system.cpu1.dtb.walker.walkCompletionTime::stdev 16001.974136 # Table walker service (enqueue to completion) latency
1754system.cpu1.dtb.walker.walkCompletionTime::0-65535 261738 99.31% 99.31% # Table walker service (enqueue to completion) latency
1755system.cpu1.dtb.walker.walkCompletionTime::65536-131071 658 0.25% 99.56% # Table walker service (enqueue to completion) latency
1756system.cpu1.dtb.walker.walkCompletionTime::131072-196607 820 0.31% 99.88% # Table walker service (enqueue to completion) latency
1757system.cpu1.dtb.walker.walkCompletionTime::196608-262143 79 0.03% 99.91% # Table walker service (enqueue to completion) latency
1758system.cpu1.dtb.walker.walkCompletionTime::262144-327679 151 0.06% 99.96% # Table walker service (enqueue to completion) latency
1759system.cpu1.dtb.walker.walkCompletionTime::327680-393215 47 0.02% 99.98% # Table walker service (enqueue to completion) latency
1760system.cpu1.dtb.walker.walkCompletionTime::393216-458751 31 0.01% 99.99% # Table walker service (enqueue to completion) latency
1761system.cpu1.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency
1762system.cpu1.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
1763system.cpu1.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
1764system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1765system.cpu1.dtb.walker.walkCompletionTime::total 263545 # Table walker service (enqueue to completion) latency
1766system.cpu1.dtb.walker.walksPending::samples 427419381904 # Table walker pending requests distribution
1767system.cpu1.dtb.walker.walksPending::mean 0.550644 # Table walker pending requests distribution
1768system.cpu1.dtb.walker.walksPending::stdev 0.560610 # Table walker pending requests distribution
1769system.cpu1.dtb.walker.walksPending::0-1 426298998404 99.74% 99.74% # Table walker pending requests distribution
1770system.cpu1.dtb.walker.walksPending::2-3 579725500 0.14% 99.87% # Table walker pending requests distribution
1771system.cpu1.dtb.walker.walksPending::4-5 235009500 0.05% 99.93% # Table walker pending requests distribution
1772system.cpu1.dtb.walker.walksPending::6-7 123480000 0.03% 99.96% # Table walker pending requests distribution
1773system.cpu1.dtb.walker.walksPending::8-9 88192000 0.02% 99.98% # Table walker pending requests distribution
1774system.cpu1.dtb.walker.walksPending::10-11 51481500 0.01% 99.99% # Table walker pending requests distribution
1775system.cpu1.dtb.walker.walksPending::12-13 16753000 0.00% 99.99% # Table walker pending requests distribution
1776system.cpu1.dtb.walker.walksPending::14-15 25205500 0.01% 100.00% # Table walker pending requests distribution
1777system.cpu1.dtb.walker.walksPending::16-17 518000 0.00% 100.00% # Table walker pending requests distribution
1778system.cpu1.dtb.walker.walksPending::18-19 18500 0.00% 100.00% # Table walker pending requests distribution
1779system.cpu1.dtb.walker.walksPending::total 427419381904 # Table walker pending requests distribution
1780system.cpu1.dtb.walker.walkPageSizes::4K 82114 89.25% 89.25% # Table walker page sizes translated
1781system.cpu1.dtb.walker.walkPageSizes::2M 9887 10.75% 100.00% # Table walker page sizes translated
1782system.cpu1.dtb.walker.walkPageSizes::total 92001 # Table walker page sizes translated
1783system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 523591 # Table walker requests started/completed, data/inst
1784system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1785system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 523591 # Table walker requests started/completed, data/inst
1786system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92001 # Table walker requests started/completed, data/inst
1787system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1788system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92001 # Table walker requests started/completed, data/inst
1789system.cpu1.dtb.walker.walkRequestOrigin::total 615592 # Table walker requests started/completed, data/inst
1790system.cpu1.dtb.inst_hits 0 # ITB inst hits
1791system.cpu1.dtb.inst_misses 0 # ITB inst misses
1792system.cpu1.dtb.read_hits 88459625 # DTB read hits
1793system.cpu1.dtb.read_misses 355289 # DTB read misses
1794system.cpu1.dtb.write_hits 73058314 # DTB write hits
1795system.cpu1.dtb.write_misses 168302 # DTB write misses
1796system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1797system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1798system.cpu1.dtb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID
1799system.cpu1.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
1800system.cpu1.dtb.flush_entries 34429 # Number of entries that have been flushed from TLB
1801system.cpu1.dtb.align_faults 243 # Number of TLB faults due to alignment restrictions
1802system.cpu1.dtb.prefetch_faults 5558 # Number of TLB faults due to prefetch
1803system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1804system.cpu1.dtb.perms_faults 38457 # Number of TLB faults due to permissions restrictions
1805system.cpu1.dtb.read_accesses 88814914 # DTB read accesses
1806system.cpu1.dtb.write_accesses 73226616 # DTB write accesses
1807system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1808system.cpu1.dtb.hits 161517939 # DTB hits
1809system.cpu1.dtb.misses 523591 # DTB misses
1810system.cpu1.dtb.accesses 162041530 # DTB accesses
1811system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1812system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1813system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1814system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1815system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1816system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1817system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1818system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1832system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1833system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1834system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1835system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1836system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1837system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1838system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1839system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1840system.cpu1.itb.walker.walks 79238 # Table walker walks requested
1841system.cpu1.itb.walker.walksLong 79238 # Table walker walks initiated with long descriptors
1842system.cpu1.itb.walker.walksLongTerminationLevel::Level2 670 # Level at which table walker walks with long descriptors terminate
1843system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55768 # Level at which table walker walks with long descriptors terminate
1844system.cpu1.itb.walker.walksSquashedBefore 9704 # Table walks squashed before starting
1845system.cpu1.itb.walker.walkWaitTime::samples 69534 # Table walker wait (enqueue to first request) latency
1846system.cpu1.itb.walker.walkWaitTime::mean 1362.196911 # Table walker wait (enqueue to first request) latency
1847system.cpu1.itb.walker.walkWaitTime::stdev 10189.827482 # Table walker wait (enqueue to first request) latency
1848system.cpu1.itb.walker.walkWaitTime::0-32767 68875 99.05% 99.05% # Table walker wait (enqueue to first request) latency
1849system.cpu1.itb.walker.walkWaitTime::32768-65535 429 0.62% 99.67% # Table walker wait (enqueue to first request) latency
1850system.cpu1.itb.walker.walkWaitTime::65536-98303 22 0.03% 99.70% # Table walker wait (enqueue to first request) latency
1851system.cpu1.itb.walker.walkWaitTime::98304-131071 45 0.06% 99.77% # Table walker wait (enqueue to first request) latency
1852system.cpu1.itb.walker.walkWaitTime::131072-163839 97 0.14% 99.91% # Table walker wait (enqueue to first request) latency
1853system.cpu1.itb.walker.walkWaitTime::163840-196607 46 0.07% 99.97% # Table walker wait (enqueue to first request) latency
1854system.cpu1.itb.walker.walkWaitTime::196608-229375 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency
1855system.cpu1.itb.walker.walkWaitTime::229376-262143 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency
1856system.cpu1.itb.walker.walkWaitTime::262144-294911 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
1857system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1858system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1859system.cpu1.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1860system.cpu1.itb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1861system.cpu1.itb.walker.walkWaitTime::total 69534 # Table walker wait (enqueue to first request) latency
1862system.cpu1.itb.walker.walkCompletionTime::samples 66142 # Table walker service (enqueue to completion) latency
1863system.cpu1.itb.walker.walkCompletionTime::mean 24972.294457 # Table walker service (enqueue to completion) latency
1864system.cpu1.itb.walker.walkCompletionTime::gmean 22450.763423 # Table walker service (enqueue to completion) latency
1865system.cpu1.itb.walker.walkCompletionTime::stdev 20128.243900 # Table walker service (enqueue to completion) latency
1866system.cpu1.itb.walker.walkCompletionTime::0-65535 65282 98.70% 98.70% # Table walker service (enqueue to completion) latency
1867system.cpu1.itb.walker.walkCompletionTime::65536-131071 106 0.16% 98.86% # Table walker service (enqueue to completion) latency
1868system.cpu1.itb.walker.walkCompletionTime::131072-196607 635 0.96% 99.82% # Table walker service (enqueue to completion) latency
1869system.cpu1.itb.walker.walkCompletionTime::196608-262143 41 0.06% 99.88% # Table walker service (enqueue to completion) latency
1870system.cpu1.itb.walker.walkCompletionTime::262144-327679 34 0.05% 99.93% # Table walker service (enqueue to completion) latency
1871system.cpu1.itb.walker.walkCompletionTime::327680-393215 18 0.03% 99.96% # Table walker service (enqueue to completion) latency
1872system.cpu1.itb.walker.walkCompletionTime::393216-458751 18 0.03% 99.99% # Table walker service (enqueue to completion) latency
1873system.cpu1.itb.walker.walkCompletionTime::458752-524287 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
1874system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1875system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1876system.cpu1.itb.walker.walkCompletionTime::total 66142 # Table walker service (enqueue to completion) latency
1877system.cpu1.itb.walker.walksPending::samples 405913969924 # Table walker pending requests distribution
1878system.cpu1.itb.walker.walksPending::mean 0.852777 # Table walker pending requests distribution
1879system.cpu1.itb.walker.walksPending::stdev 0.354498 # Table walker pending requests distribution
1880system.cpu1.itb.walker.walksPending::0 59781305300 14.73% 14.73% # Table walker pending requests distribution
1881system.cpu1.itb.walker.walksPending::1 346114009624 85.27% 100.00% # Table walker pending requests distribution
1882system.cpu1.itb.walker.walksPending::2 16127000 0.00% 100.00% # Table walker pending requests distribution
1883system.cpu1.itb.walker.walksPending::3 2369500 0.00% 100.00% # Table walker pending requests distribution
1884system.cpu1.itb.walker.walksPending::4 82500 0.00% 100.00% # Table walker pending requests distribution
1885system.cpu1.itb.walker.walksPending::5 76000 0.00% 100.00% # Table walker pending requests distribution
1886system.cpu1.itb.walker.walksPending::total 405913969924 # Table walker pending requests distribution
1887system.cpu1.itb.walker.walkPageSizes::4K 55768 98.81% 98.81% # Table walker page sizes translated
1888system.cpu1.itb.walker.walkPageSizes::2M 670 1.19% 100.00% # Table walker page sizes translated
1889system.cpu1.itb.walker.walkPageSizes::total 56438 # Table walker page sizes translated
1890system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1891system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 79238 # Table walker requests started/completed, data/inst
1892system.cpu1.itb.walker.walkRequestOrigin_Requested::total 79238 # Table walker requests started/completed, data/inst
1893system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1894system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56438 # Table walker requests started/completed, data/inst
1895system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56438 # Table walker requests started/completed, data/inst
1896system.cpu1.itb.walker.walkRequestOrigin::total 135676 # Table walker requests started/completed, data/inst
1897system.cpu1.itb.inst_hits 188743149 # ITB inst hits
1898system.cpu1.itb.inst_misses 79238 # ITB inst misses
1899system.cpu1.itb.read_hits 0 # DTB read hits
1900system.cpu1.itb.read_misses 0 # DTB read misses
1901system.cpu1.itb.write_hits 0 # DTB write hits
1902system.cpu1.itb.write_misses 0 # DTB write misses
1903system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1904system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1905system.cpu1.itb.flush_tlb_mva_asid 44586 # Number of times TLB was flushed by MVA & ASID
1906system.cpu1.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
1907system.cpu1.itb.flush_entries 24595 # Number of entries that have been flushed from TLB
1908system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1909system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1910system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1911system.cpu1.itb.perms_faults 203696 # Number of TLB faults due to permissions restrictions
1912system.cpu1.itb.read_accesses 0 # DTB read accesses
1913system.cpu1.itb.write_accesses 0 # DTB write accesses
1914system.cpu1.itb.inst_accesses 188822387 # ITB inst accesses
1915system.cpu1.itb.hits 188743149 # DTB hits
1916system.cpu1.itb.misses 79238 # DTB misses
1917system.cpu1.itb.accesses 188822387 # DTB accesses
1918system.cpu1.numCycles 668763369 # number of cpu cycles simulated
1919system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1920system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1921system.cpu1.fetch.icacheStallCycles 76762482 # Number of cycles fetch is stalled on an Icache miss
1922system.cpu1.fetch.Insts 531105996 # Number of instructions fetch has processed
1923system.cpu1.fetch.Branches 119891525 # Number of branches that fetch encountered
1924system.cpu1.fetch.predictedBranches 70980597 # Number of branches that fetch has predicted taken
1925system.cpu1.fetch.Cycles 555217707 # Number of cycles fetch has run and was not squashing or blocked
1926system.cpu1.fetch.SquashCycles 12731518 # Number of cycles fetch has spent squashing
1927system.cpu1.fetch.TlbCycles 1797928 # Number of cycles fetch has spent waiting for tlb
1928system.cpu1.fetch.MiscStallCycles 295013 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1929system.cpu1.fetch.PendingTrapStallCycles 5987179 # Number of stall cycles due to pending traps
1930system.cpu1.fetch.PendingQuiesceStallCycles 752221 # Number of stall cycles due to pending quiesce instructions
1931system.cpu1.fetch.IcacheWaitRetryStallCycles 763722 # Number of stall cycles due to full MSHR
1932system.cpu1.fetch.CacheLines 188519405 # Number of cache lines fetched
1933system.cpu1.fetch.IcacheSquashes 1489379 # Number of outstanding Icache misses that were squashed
1934system.cpu1.fetch.ItlbSquashes 27517 # Number of outstanding ITLB misses that were squashed
1935system.cpu1.fetch.rateDist::samples 647942011 # Number of instructions fetched each cycle (Total)
1936system.cpu1.fetch.rateDist::mean 0.963740 # Number of instructions fetched each cycle (Total)
1937system.cpu1.fetch.rateDist::stdev 1.217002 # Number of instructions fetched each cycle (Total)
1938system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1939system.cpu1.fetch.rateDist::0 349005233 53.86% 53.86% # Number of instructions fetched each cycle (Total)
1940system.cpu1.fetch.rateDist::1 116425876 17.97% 71.83% # Number of instructions fetched each cycle (Total)
1941system.cpu1.fetch.rateDist::2 39511198 6.10% 77.93% # Number of instructions fetched each cycle (Total)
1942system.cpu1.fetch.rateDist::3 142999704 22.07% 100.00% # Number of instructions fetched each cycle (Total)
1943system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1944system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1945system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
1946system.cpu1.fetch.rateDist::total 647942011 # Number of instructions fetched each cycle (Total)
1947system.cpu1.fetch.branchRate 0.179273 # Number of branch fetches per cycle
1948system.cpu1.fetch.rate 0.794161 # Number of inst fetches per cycle
1949system.cpu1.decode.IdleCycles 92682171 # Number of cycles decode is idle
1950system.cpu1.decode.BlockedCycles 320350015 # Number of cycles decode is blocked
1951system.cpu1.decode.RunCycles 196661442 # Number of cycles decode is running
1952system.cpu1.decode.UnblockCycles 33741382 # Number of cycles decode is unblocking
1953system.cpu1.decode.SquashCycles 4507001 # Number of cycles decode is squashing
1954system.cpu1.decode.BranchResolved 16971690 # Number of times decode resolved a branch
1955system.cpu1.decode.BranchMispred 1895430 # Number of times decode detected a branch misprediction
1956system.cpu1.decode.DecodedInsts 551371568 # Number of instructions handled by decode
1957system.cpu1.decode.SquashedInsts 20348682 # Number of squashed instructions handled by decode
1958system.cpu1.rename.SquashCycles 4507001 # Number of cycles rename is squashing
1959system.cpu1.rename.IdleCycles 124070698 # Number of cycles rename is idle
1960system.cpu1.rename.BlockCycles 47114866 # Number of cycles rename is blocking
1961system.cpu1.rename.serializeStallCycles 212074227 # count of cycles rename stalled for serializing inst
1962system.cpu1.rename.RunCycles 198637530 # Number of cycles rename is running
1963system.cpu1.rename.UnblockCycles 61537689 # Number of cycles rename is unblocking
1964system.cpu1.rename.RenamedInsts 536563152 # Number of instructions processed by rename
1965system.cpu1.rename.SquashedInsts 5145214 # Number of squashed instructions processed by rename
1966system.cpu1.rename.ROBFullEvents 9840770 # Number of times rename has blocked due to ROB full
1967system.cpu1.rename.IQFullEvents 223861 # Number of times rename has blocked due to IQ full
1968system.cpu1.rename.LQFullEvents 282097 # Number of times rename has blocked due to LQ full
1969system.cpu1.rename.SQFullEvents 29934469 # Number of times rename has blocked due to SQ full
1970system.cpu1.rename.FullRegisterEvents 10810 # Number of times there has been no free registers
1971system.cpu1.rename.RenamedOperands 509803663 # Number of destination operands rename has renamed
1972system.cpu1.rename.RenameLookups 829081125 # Number of register rename lookups that rename has made
1973system.cpu1.rename.int_rename_lookups 634679636 # Number of integer rename lookups
1974system.cpu1.rename.fp_rename_lookups 600803 # Number of floating rename lookups
1975system.cpu1.rename.CommittedMaps 459431302 # Number of HB maps that are committed
1976system.cpu1.rename.UndoneMaps 50372361 # Number of HB maps that are undone due to squashing
1977system.cpu1.rename.serializingInsts 14562905 # count of serializing insts renamed
1978system.cpu1.rename.tempSerializingInsts 12854163 # count of temporary serializing insts renamed
1979system.cpu1.rename.skidInsts 68041373 # count of insts added to the skid buffer
1980system.cpu1.memDep0.insertedLoads 88476596 # Number of loads inserted to the mem dependence unit.
1981system.cpu1.memDep0.insertedStores 76035338 # Number of stores inserted to the mem dependence unit.
1982system.cpu1.memDep0.conflictingLoads 8565835 # Number of conflicting loads.
1983system.cpu1.memDep0.conflictingStores 7285035 # Number of conflicting stores.
1984system.cpu1.iq.iqInstsAdded 516079501 # Number of instructions added to the IQ (excludes non-spec)
1985system.cpu1.iq.iqNonSpecInstsAdded 14870100 # Number of non-speculative instructions added to the IQ
1986system.cpu1.iq.iqInstsIssued 521291240 # Number of instructions issued
1987system.cpu1.iq.iqSquashedInstsIssued 2377203 # Number of squashed instructions issued
1988system.cpu1.iq.iqSquashedInstsExamined 47872437 # Number of squashed instructions iterated over during squash; mainly for profiling
1989system.cpu1.iq.iqSquashedOperandsExamined 30743352 # Number of squashed operands that are examined and possibly removed from graph
1990system.cpu1.iq.iqSquashedNonSpecRemoved 257935 # Number of squashed non-spec instructions that were removed
1991system.cpu1.iq.issued_per_cycle::samples 647942011 # Number of insts issued each cycle
1992system.cpu1.iq.issued_per_cycle::mean 0.804534 # Number of insts issued each cycle
1993system.cpu1.iq.issued_per_cycle::stdev 1.061029 # Number of insts issued each cycle
1994system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1995system.cpu1.iq.issued_per_cycle::0 361872507 55.85% 55.85% # Number of insts issued each cycle
1996system.cpu1.iq.issued_per_cycle::1 122353667 18.88% 74.73% # Number of insts issued each cycle
1997system.cpu1.iq.issued_per_cycle::2 99252241 15.32% 90.05% # Number of insts issued each cycle
1998system.cpu1.iq.issued_per_cycle::3 57424869 8.86% 98.91% # Number of insts issued each cycle
1999system.cpu1.iq.issued_per_cycle::4 7035151 1.09% 100.00% # Number of insts issued each cycle
2000system.cpu1.iq.issued_per_cycle::5 3576 0.00% 100.00% # Number of insts issued each cycle
2001system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
2002system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
2003system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
2004system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
2005system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2006system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2007system.cpu1.iq.issued_per_cycle::total 647942011 # Number of insts issued each cycle
2008system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2009system.cpu1.iq.fu_full::IntAlu 52040674 43.67% 43.67% # attempts to use FU when none available
2010system.cpu1.iq.fu_full::IntMult 50092 0.04% 43.71% # attempts to use FU when none available
2011system.cpu1.iq.fu_full::IntDiv 18388 0.02% 43.72% # attempts to use FU when none available
2012system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.72% # attempts to use FU when none available
2013system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.72% # attempts to use FU when none available
2014system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.72% # attempts to use FU when none available
2015system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.72% # attempts to use FU when none available
2016system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.72% # attempts to use FU when none available
2017system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.72% # attempts to use FU when none available
2018system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.72% # attempts to use FU when none available
2019system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.72% # attempts to use FU when none available
2020system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.72% # attempts to use FU when none available
2021system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.72% # attempts to use FU when none available
2022system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.72% # attempts to use FU when none available
2023system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.72% # attempts to use FU when none available
2024system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.72% # attempts to use FU when none available
2025system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.72% # attempts to use FU when none available
2026system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.72% # attempts to use FU when none available
2027system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.72% # attempts to use FU when none available
2028system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.72% # attempts to use FU when none available
2029system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.72% # attempts to use FU when none available
2030system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.72% # attempts to use FU when none available
2031system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.72% # attempts to use FU when none available
2032system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.72% # attempts to use FU when none available
2033system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.72% # attempts to use FU when none available
2034system.cpu1.iq.fu_full::SimdFloatMisc 16 0.00% 43.72% # attempts to use FU when none available
2035system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.72% # attempts to use FU when none available
2036system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.72% # attempts to use FU when none available
2037system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.72% # attempts to use FU when none available
2038system.cpu1.iq.fu_full::MemRead 32200400 27.02% 70.74% # attempts to use FU when none available
2039system.cpu1.iq.fu_full::MemWrite 34865580 29.26% 100.00% # attempts to use FU when none available
2040system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
2041system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2042system.cpu1.iq.FU_type_0::No_OpClass 27 0.00% 0.00% # Type of FU issued
2043system.cpu1.iq.FU_type_0::IntAlu 354670500 68.04% 68.04% # Type of FU issued
2044system.cpu1.iq.FU_type_0::IntMult 1183955 0.23% 68.26% # Type of FU issued
2045system.cpu1.iq.FU_type_0::IntDiv 65513 0.01% 68.28% # Type of FU issued
2046system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.28% # Type of FU issued
2047system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.28% # Type of FU issued
2048system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.28% # Type of FU issued
2049system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.28% # Type of FU issued
2050system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.28% # Type of FU issued
2051system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.28% # Type of FU issued
2052system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.28% # Type of FU issued
2053system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.28% # Type of FU issued
2054system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.28% # Type of FU issued
2055system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.28% # Type of FU issued
2056system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.28% # Type of FU issued
2057system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.28% # Type of FU issued
2058system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.28% # Type of FU issued
2059system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.28% # Type of FU issued
2060system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.28% # Type of FU issued
2061system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.28% # Type of FU issued
2062system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.28% # Type of FU issued
2063system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.28% # Type of FU issued
2064system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.28% # Type of FU issued
2065system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.28% # Type of FU issued
2066system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.28% # Type of FU issued
2067system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.28% # Type of FU issued
2068system.cpu1.iq.FU_type_0::SimdFloatMisc 42657 0.01% 68.28% # Type of FU issued
2069system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.28% # Type of FU issued
2070system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.28% # Type of FU issued
2071system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.28% # Type of FU issued
2072system.cpu1.iq.FU_type_0::MemRead 91135432 17.48% 85.77% # Type of FU issued
2073system.cpu1.iq.FU_type_0::MemWrite 74193108 14.23% 100.00% # Type of FU issued
2074system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
2075system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2076system.cpu1.iq.FU_type_0::total 521291240 # Type of FU issued
2077system.cpu1.iq.rate 0.779485 # Inst issue rate
2078system.cpu1.iq.fu_busy_cnt 119175150 # FU busy when requested
2079system.cpu1.iq.fu_busy_rate 0.228615 # FU busy rate (busy events/executed inst)
2080system.cpu1.iq.int_inst_queue_reads 1811086365 # Number of integer instruction queue reads
2081system.cpu1.iq.int_inst_queue_writes 578565811 # Number of integer instruction queue writes
2082system.cpu1.iq.int_inst_queue_wakeup_accesses 506287229 # Number of integer instruction queue wakeup accesses
2083system.cpu1.iq.fp_inst_queue_reads 990479 # Number of floating instruction queue reads
2084system.cpu1.iq.fp_inst_queue_writes 395514 # Number of floating instruction queue writes
2085system.cpu1.iq.fp_inst_queue_wakeup_accesses 364516 # Number of floating instruction queue wakeup accesses
2086system.cpu1.iq.int_alu_accesses 639849832 # Number of integer alu accesses
2087system.cpu1.iq.fp_alu_accesses 616531 # Number of floating point alu accesses
2088system.cpu1.iew.lsq.thread0.forwLoads 2398408 # Number of loads that had data forwarded from stores
2089system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2090system.cpu1.iew.lsq.thread0.squashedLoads 11063470 # Number of loads squashed
2091system.cpu1.iew.lsq.thread0.ignoredResponses 14436 # Number of memory responses ignored because the instruction is squashed
2092system.cpu1.iew.lsq.thread0.memOrderViolation 140383 # Number of memory ordering violations
2093system.cpu1.iew.lsq.thread0.squashedStores 5257500 # Number of stores squashed
2094system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2095system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2096system.cpu1.iew.lsq.thread0.rescheduledLoads 2402216 # Number of loads that were rescheduled
2097system.cpu1.iew.lsq.thread0.cacheBlocked 3864822 # Number of times an access to memory failed due to the cache being blocked
2098system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2099system.cpu1.iew.iewSquashCycles 4507001 # Number of cycles IEW is squashing
2100system.cpu1.iew.iewBlockCycles 5849706 # Number of cycles IEW is blocking
2101system.cpu1.iew.iewUnblockCycles 2188326 # Number of cycles IEW is unblocking
2102system.cpu1.iew.iewDispatchedInsts 531063111 # Number of instructions dispatched to IQ
2103system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2104system.cpu1.iew.iewDispLoadInsts 88476596 # Number of dispatched load instructions
2105system.cpu1.iew.iewDispStoreInsts 76035338 # Number of dispatched store instructions
2106system.cpu1.iew.iewDispNonSpecInsts 12650539 # Number of dispatched non-speculative instructions
2107system.cpu1.iew.iewIQFullEvents 60907 # Number of times the IQ has become full, causing a stall
2108system.cpu1.iew.iewLSQFullEvents 2070757 # Number of times the LSQ has become full, causing a stall
2109system.cpu1.iew.memOrderViolationEvents 140383 # Number of memory order violations
2110system.cpu1.iew.predictedTakenIncorrect 1813068 # Number of branches that were predicted taken incorrectly
2111system.cpu1.iew.predictedNotTakenIncorrect 2483133 # Number of branches that were predicted not taken incorrectly
2112system.cpu1.iew.branchMispredicts 4296201 # Number of branch mispredicts detected at execute
2113system.cpu1.iew.iewExecutedInsts 514538937 # Number of executed instructions
2114system.cpu1.iew.iewExecLoadInsts 88454625 # Number of load instructions executed
2115system.cpu1.iew.iewExecSquashedInsts 6240485 # Number of squashed instructions skipped in execute
2116system.cpu1.iew.exec_swp 0 # number of swp insts executed
2117system.cpu1.iew.exec_nop 113510 # number of nop insts executed
2118system.cpu1.iew.exec_refs 161513914 # number of memory reference insts executed
2119system.cpu1.iew.exec_branches 96416033 # Number of branches executed
2120system.cpu1.iew.exec_stores 73059289 # Number of stores executed
2121system.cpu1.iew.exec_rate 0.769389 # Inst execution rate
2122system.cpu1.iew.wb_sent 507314383 # cumulative count of insts sent to commit
2123system.cpu1.iew.wb_count 506651745 # cumulative count of insts written-back
2124system.cpu1.iew.wb_producers 244576343 # num instructions producing a value
2125system.cpu1.iew.wb_consumers 400655745 # num instructions consuming a value
2126system.cpu1.iew.wb_rate 0.757595 # insts written-back per cycle
2127system.cpu1.iew.wb_fanout 0.610440 # average fanout of values written-back
2128system.cpu1.commit.commitSquashedInsts 41944033 # The number of squashed insts skipped by commit
2129system.cpu1.commit.commitNonSpecStalls 14612165 # The number of times commit has been forced to stall to communicate backwards
2130system.cpu1.commit.branchMispredicts 4045440 # The number of times a branch was mispredicted
2131system.cpu1.commit.committed_per_cycle::samples 639995571 # Number of insts commited each cycle
2132system.cpu1.commit.committed_per_cycle::mean 0.754813 # Number of insts commited each cycle
2133system.cpu1.commit.committed_per_cycle::stdev 1.555930 # Number of insts commited each cycle
2134system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2135system.cpu1.commit.committed_per_cycle::0 426913272 66.71% 66.71% # Number of insts commited each cycle
2136system.cpu1.commit.committed_per_cycle::1 112061055 17.51% 84.22% # Number of insts commited each cycle
2137system.cpu1.commit.committed_per_cycle::2 46474767 7.26% 91.48% # Number of insts commited each cycle
2138system.cpu1.commit.committed_per_cycle::3 15512784 2.42% 93.90% # Number of insts commited each cycle
2139system.cpu1.commit.committed_per_cycle::4 11149430 1.74% 95.64% # Number of insts commited each cycle
2140system.cpu1.commit.committed_per_cycle::5 7505688 1.17% 96.82% # Number of insts commited each cycle
2141system.cpu1.commit.committed_per_cycle::6 5285555 0.83% 97.64% # Number of insts commited each cycle
2142system.cpu1.commit.committed_per_cycle::7 3055428 0.48% 98.12% # Number of insts commited each cycle
2143system.cpu1.commit.committed_per_cycle::8 12037592 1.88% 100.00% # Number of insts commited each cycle
2144system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2145system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2146system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2147system.cpu1.commit.committed_per_cycle::total 639995571 # Number of insts commited each cycle
2148system.cpu1.commit.committedInsts 409938912 # Number of instructions committed
2149system.cpu1.commit.committedOps 483077163 # Number of ops (including micro ops) committed
2150system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2151system.cpu1.commit.refs 148190964 # Number of memory references committed
2152system.cpu1.commit.loads 77413126 # Number of loads committed
2153system.cpu1.commit.membars 3553266 # Number of memory barriers committed
2154system.cpu1.commit.branches 91478423 # Number of branches committed
2155system.cpu1.commit.fp_insts 356192 # Number of committed floating point instructions.
2156system.cpu1.commit.int_insts 443462583 # Number of committed integer instructions.
2157system.cpu1.commit.function_calls 11919697 # Number of function calls committed.
2158system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2159system.cpu1.commit.op_class_0::IntAlu 333838399 69.11% 69.11% # Class of committed instruction
2160system.cpu1.commit.op_class_0::IntMult 958189 0.20% 69.30% # Class of committed instruction
2161system.cpu1.commit.op_class_0::IntDiv 52064 0.01% 69.32% # Class of committed instruction
2162system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.32% # Class of committed instruction
2163system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.32% # Class of committed instruction
2164system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.32% # Class of committed instruction
2165system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.32% # Class of committed instruction
2166system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.32% # Class of committed instruction
2167system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.32% # Class of committed instruction
2168system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.32% # Class of committed instruction
2169system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.32% # Class of committed instruction
2170system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.32% # Class of committed instruction
2171system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.32% # Class of committed instruction
2172system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.32% # Class of committed instruction
2173system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.32% # Class of committed instruction
2174system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.32% # Class of committed instruction
2175system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.32% # Class of committed instruction
2176system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.32% # Class of committed instruction
2177system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.32% # Class of committed instruction
2178system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.32% # Class of committed instruction
2179system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.32% # Class of committed instruction
2180system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.32% # Class of committed instruction
2181system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.32% # Class of committed instruction
2182system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.32% # Class of committed instruction
2183system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.32% # Class of committed instruction
2184system.cpu1.commit.op_class_0::SimdFloatMisc 37505 0.01% 69.32% # Class of committed instruction
2185system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.32% # Class of committed instruction
2186system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.32% # Class of committed instruction
2187system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.32% # Class of committed instruction
2188system.cpu1.commit.op_class_0::MemRead 77413126 16.03% 85.35% # Class of committed instruction
2189system.cpu1.commit.op_class_0::MemWrite 70777838 14.65% 100.00% # Class of committed instruction
2190system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2191system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2192system.cpu1.commit.op_class_0::total 483077163 # Class of committed instruction
2193system.cpu1.commit.bw_lim_events 12037592 # number cycles where commit BW limit reached
2194system.cpu1.rob.rob_reads 1149378464 # The number of ROB reads
2195system.cpu1.rob.rob_writes 1057951201 # The number of ROB writes
2196system.cpu1.timesIdled 862725 # Number of times that the entire CPU went into an idle state and unscheduled itself
2197system.cpu1.idleCycles 20821358 # Total number of cycles that the CPU has spent unscheduled due to idling
2198system.cpu1.quiesceCycles 94039702456 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2199system.cpu1.committedInsts 409938912 # Number of Instructions Simulated
2200system.cpu1.committedOps 483077163 # Number of Ops (including micro ops) Simulated
2201system.cpu1.cpi 1.631373 # CPI: Cycles Per Instruction
2202system.cpu1.cpi_total 1.631373 # CPI: Total CPI of All Threads
2203system.cpu1.ipc 0.612981 # IPC: Instructions Per Cycle
2204system.cpu1.ipc_total 0.612981 # IPC: Total IPC of All Threads
2205system.cpu1.int_regfile_reads 608507800 # number of integer regfile reads
2206system.cpu1.int_regfile_writes 359700181 # number of integer regfile writes
2207system.cpu1.fp_regfile_reads 588843 # number of floating regfile reads
2208system.cpu1.fp_regfile_writes 298828 # number of floating regfile writes
2209system.cpu1.cc_regfile_reads 110183943 # number of cc regfile reads
2210system.cpu1.cc_regfile_writes 110950246 # number of cc regfile writes
2211system.cpu1.misc_regfile_reads 1143200959 # number of misc regfile reads
2212system.cpu1.misc_regfile_writes 14699928 # number of misc regfile writes
2213system.cpu1.dcache.tags.replacements 4943818 # number of replacements
2214system.cpu1.dcache.tags.tagsinuse 455.490717 # Cycle average of tags in use
2215system.cpu1.dcache.tags.total_refs 138046990 # Total number of references to valid blocks.
2216system.cpu1.dcache.tags.sampled_refs 4944322 # Sample count of references to valid blocks.
2217system.cpu1.dcache.tags.avg_refs 27.920307 # Average number of references to valid blocks.
2218system.cpu1.dcache.tags.warmup_cycle 8486298300000 # Cycle when the warmup percentage was hit.
2219system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.490717 # Average occupied blocks per requestor
2220system.cpu1.dcache.tags.occ_percent::cpu1.data 0.889630 # Average percentage of cache occupancy
2221system.cpu1.dcache.tags.occ_percent::total 0.889630 # Average percentage of cache occupancy
2222system.cpu1.dcache.tags.occ_task_id_blocks::1024 504 # Occupied blocks per task id
2223system.cpu1.dcache.tags.age_task_id_blocks_1024::1 434 # Occupied blocks per task id
2224system.cpu1.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id
2225system.cpu1.dcache.tags.occ_task_id_percent::1024 0.984375 # Percentage of cache occupancy per task id
2226system.cpu1.dcache.tags.tag_accesses 307427480 # Number of tag accesses
2227system.cpu1.dcache.tags.data_accesses 307427480 # Number of data accesses
2228system.cpu1.dcache.ReadReq_hits::cpu1.data 71852716 # number of ReadReq hits
2229system.cpu1.dcache.ReadReq_hits::total 71852716 # number of ReadReq hits
2230system.cpu1.dcache.WriteReq_hits::cpu1.data 61790747 # number of WriteReq hits
2231system.cpu1.dcache.WriteReq_hits::total 61790747 # number of WriteReq hits
2232system.cpu1.dcache.SoftPFReq_hits::cpu1.data 162379 # number of SoftPFReq hits
2233system.cpu1.dcache.SoftPFReq_hits::total 162379 # number of SoftPFReq hits
2234system.cpu1.dcache.WriteLineReq_hits::cpu1.data 50057 # number of WriteLineReq hits
2235system.cpu1.dcache.WriteLineReq_hits::total 50057 # number of WriteLineReq hits
2236system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1706960 # number of LoadLockedReq hits
2237system.cpu1.dcache.LoadLockedReq_hits::total 1706960 # number of LoadLockedReq hits
2238system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1722622 # number of StoreCondReq hits
2239system.cpu1.dcache.StoreCondReq_hits::total 1722622 # number of StoreCondReq hits
2240system.cpu1.dcache.demand_hits::cpu1.data 133643463 # number of demand (read+write) hits
2241system.cpu1.dcache.demand_hits::total 133643463 # number of demand (read+write) hits
2242system.cpu1.dcache.overall_hits::cpu1.data 133805842 # number of overall hits
2243system.cpu1.dcache.overall_hits::total 133805842 # number of overall hits
2244system.cpu1.dcache.ReadReq_misses::cpu1.data 5820950 # number of ReadReq misses
2245system.cpu1.dcache.ReadReq_misses::total 5820950 # number of ReadReq misses
2246system.cpu1.dcache.WriteReq_misses::cpu1.data 6630483 # number of WriteReq misses
2247system.cpu1.dcache.WriteReq_misses::total 6630483 # number of WriteReq misses
2248system.cpu1.dcache.SoftPFReq_misses::cpu1.data 628859 # number of SoftPFReq misses
2249system.cpu1.dcache.SoftPFReq_misses::total 628859 # number of SoftPFReq misses
2250system.cpu1.dcache.WriteLineReq_misses::cpu1.data 401328 # number of WriteLineReq misses
2251system.cpu1.dcache.WriteLineReq_misses::total 401328 # number of WriteLineReq misses
2252system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 243245 # number of LoadLockedReq misses
2253system.cpu1.dcache.LoadLockedReq_misses::total 243245 # number of LoadLockedReq misses
2254system.cpu1.dcache.StoreCondReq_misses::cpu1.data 186259 # number of StoreCondReq misses
2255system.cpu1.dcache.StoreCondReq_misses::total 186259 # number of StoreCondReq misses
2256system.cpu1.dcache.demand_misses::cpu1.data 12451433 # number of demand (read+write) misses
2257system.cpu1.dcache.demand_misses::total 12451433 # number of demand (read+write) misses
2258system.cpu1.dcache.overall_misses::cpu1.data 13080292 # number of overall misses
2259system.cpu1.dcache.overall_misses::total 13080292 # number of overall misses
2260system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96708932500 # number of ReadReq miss cycles
2261system.cpu1.dcache.ReadReq_miss_latency::total 96708932500 # number of ReadReq miss cycles
2262system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 144491403356 # number of WriteReq miss cycles
2263system.cpu1.dcache.WriteReq_miss_latency::total 144491403356 # number of WriteReq miss cycles
2264system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16631824083 # number of WriteLineReq miss cycles
2265system.cpu1.dcache.WriteLineReq_miss_latency::total 16631824083 # number of WriteLineReq miss cycles
2266system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3760760000 # number of LoadLockedReq miss cycles
2267system.cpu1.dcache.LoadLockedReq_miss_latency::total 3760760000 # number of LoadLockedReq miss cycles
2268system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5141971500 # number of StoreCondReq miss cycles
2269system.cpu1.dcache.StoreCondReq_miss_latency::total 5141971500 # number of StoreCondReq miss cycles
2270system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 6754500 # number of StoreCondFailReq miss cycles
2271system.cpu1.dcache.StoreCondFailReq_miss_latency::total 6754500 # number of StoreCondFailReq miss cycles
2272system.cpu1.dcache.demand_miss_latency::cpu1.data 241200335856 # number of demand (read+write) miss cycles
2273system.cpu1.dcache.demand_miss_latency::total 241200335856 # number of demand (read+write) miss cycles
2274system.cpu1.dcache.overall_miss_latency::cpu1.data 241200335856 # number of overall miss cycles
2275system.cpu1.dcache.overall_miss_latency::total 241200335856 # number of overall miss cycles
2276system.cpu1.dcache.ReadReq_accesses::cpu1.data 77673666 # number of ReadReq accesses(hits+misses)
2277system.cpu1.dcache.ReadReq_accesses::total 77673666 # number of ReadReq accesses(hits+misses)
2278system.cpu1.dcache.WriteReq_accesses::cpu1.data 68421230 # number of WriteReq accesses(hits+misses)
2279system.cpu1.dcache.WriteReq_accesses::total 68421230 # number of WriteReq accesses(hits+misses)
2280system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 791238 # number of SoftPFReq accesses(hits+misses)
2281system.cpu1.dcache.SoftPFReq_accesses::total 791238 # number of SoftPFReq accesses(hits+misses)
2282system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 451385 # number of WriteLineReq accesses(hits+misses)
2283system.cpu1.dcache.WriteLineReq_accesses::total 451385 # number of WriteLineReq accesses(hits+misses)
2284system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1950205 # number of LoadLockedReq accesses(hits+misses)
2285system.cpu1.dcache.LoadLockedReq_accesses::total 1950205 # number of LoadLockedReq accesses(hits+misses)
2286system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1908881 # number of StoreCondReq accesses(hits+misses)
2287system.cpu1.dcache.StoreCondReq_accesses::total 1908881 # number of StoreCondReq accesses(hits+misses)
2288system.cpu1.dcache.demand_accesses::cpu1.data 146094896 # number of demand (read+write) accesses
2289system.cpu1.dcache.demand_accesses::total 146094896 # number of demand (read+write) accesses
2290system.cpu1.dcache.overall_accesses::cpu1.data 146886134 # number of overall (read+write) accesses
2291system.cpu1.dcache.overall_accesses::total 146886134 # number of overall (read+write) accesses
2292system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074941 # miss rate for ReadReq accesses
2293system.cpu1.dcache.ReadReq_miss_rate::total 0.074941 # miss rate for ReadReq accesses
2294system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.096907 # miss rate for WriteReq accesses
2295system.cpu1.dcache.WriteReq_miss_rate::total 0.096907 # miss rate for WriteReq accesses
2296system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.794779 # miss rate for SoftPFReq accesses
2297system.cpu1.dcache.SoftPFReq_miss_rate::total 0.794779 # miss rate for SoftPFReq accesses
2298system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.889104 # miss rate for WriteLineReq accesses
2299system.cpu1.dcache.WriteLineReq_miss_rate::total 0.889104 # miss rate for WriteLineReq accesses
2300system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124728 # miss rate for LoadLockedReq accesses
2301system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124728 # miss rate for LoadLockedReq accesses
2302system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097575 # miss rate for StoreCondReq accesses
2303system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097575 # miss rate for StoreCondReq accesses
2304system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085228 # miss rate for demand accesses
2305system.cpu1.dcache.demand_miss_rate::total 0.085228 # miss rate for demand accesses
2306system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089051 # miss rate for overall accesses
2307system.cpu1.dcache.overall_miss_rate::total 0.089051 # miss rate for overall accesses
2308system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16613.943171 # average ReadReq miss latency
2309system.cpu1.dcache.ReadReq_avg_miss_latency::total 16613.943171 # average ReadReq miss latency
2310system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21791.987606 # average WriteReq miss latency
2311system.cpu1.dcache.WriteReq_avg_miss_latency::total 21791.987606 # average WriteReq miss latency
2312system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 41441.972858 # average WriteLineReq miss latency
2313system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 41441.972858 # average WriteLineReq miss latency
2314system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15460.790561 # average LoadLockedReq miss latency
2315system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15460.790561 # average LoadLockedReq miss latency
2316system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27606.566663 # average StoreCondReq miss latency
2317system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27606.566663 # average StoreCondReq miss latency
2318system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
2319system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2320system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19371.291309 # average overall miss latency
2321system.cpu1.dcache.demand_avg_miss_latency::total 19371.291309 # average overall miss latency
2322system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18439.980992 # average overall miss latency
2323system.cpu1.dcache.overall_avg_miss_latency::total 18439.980992 # average overall miss latency
2324system.cpu1.dcache.blocked_cycles::no_mshrs 4381553 # number of cycles access was blocked
2325system.cpu1.dcache.blocked_cycles::no_targets 22968096 # number of cycles access was blocked
2326system.cpu1.dcache.blocked::no_mshrs 326353 # number of cycles access was blocked
2327system.cpu1.dcache.blocked::no_targets 670571 # number of cycles access was blocked
2328system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.425809 # average number of cycles each access was blocked
2329system.cpu1.dcache.avg_blocked_cycles::no_targets 34.251550 # average number of cycles each access was blocked
2330system.cpu1.dcache.fast_writes 0 # number of fast writes performed
2331system.cpu1.dcache.cache_copies 0 # number of cache copies performed
2332system.cpu1.dcache.writebacks::writebacks 4943833 # number of writebacks
2333system.cpu1.dcache.writebacks::total 4943833 # number of writebacks
2334system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 2977175 # number of ReadReq MSHR hits
2335system.cpu1.dcache.ReadReq_mshr_hits::total 2977175 # number of ReadReq MSHR hits
2336system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5355618 # number of WriteReq MSHR hits
2337system.cpu1.dcache.WriteReq_mshr_hits::total 5355618 # number of WriteReq MSHR hits
2338system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3078 # number of WriteLineReq MSHR hits
2339system.cpu1.dcache.WriteLineReq_mshr_hits::total 3078 # number of WriteLineReq MSHR hits
2340system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 125917 # number of LoadLockedReq MSHR hits
2341system.cpu1.dcache.LoadLockedReq_mshr_hits::total 125917 # number of LoadLockedReq MSHR hits
2342system.cpu1.dcache.demand_mshr_hits::cpu1.data 8332793 # number of demand (read+write) MSHR hits
2343system.cpu1.dcache.demand_mshr_hits::total 8332793 # number of demand (read+write) MSHR hits
2344system.cpu1.dcache.overall_mshr_hits::cpu1.data 8332793 # number of overall MSHR hits
2345system.cpu1.dcache.overall_mshr_hits::total 8332793 # number of overall MSHR hits
2346system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2843775 # number of ReadReq MSHR misses
2347system.cpu1.dcache.ReadReq_mshr_misses::total 2843775 # number of ReadReq MSHR misses
2348system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1274865 # number of WriteReq MSHR misses
2349system.cpu1.dcache.WriteReq_mshr_misses::total 1274865 # number of WriteReq MSHR misses
2350system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 628773 # number of SoftPFReq MSHR misses
2351system.cpu1.dcache.SoftPFReq_mshr_misses::total 628773 # number of SoftPFReq MSHR misses
2352system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 398250 # number of WriteLineReq MSHR misses
2353system.cpu1.dcache.WriteLineReq_mshr_misses::total 398250 # number of WriteLineReq MSHR misses
2354system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 117328 # number of LoadLockedReq MSHR misses
2355system.cpu1.dcache.LoadLockedReq_mshr_misses::total 117328 # number of LoadLockedReq MSHR misses
2356system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 186249 # number of StoreCondReq MSHR misses
2357system.cpu1.dcache.StoreCondReq_mshr_misses::total 186249 # number of StoreCondReq MSHR misses
2358system.cpu1.dcache.demand_mshr_misses::cpu1.data 4118640 # number of demand (read+write) MSHR misses
2359system.cpu1.dcache.demand_mshr_misses::total 4118640 # number of demand (read+write) MSHR misses
2360system.cpu1.dcache.overall_mshr_misses::cpu1.data 4747413 # number of overall MSHR misses
2361system.cpu1.dcache.overall_mshr_misses::total 4747413 # number of overall MSHR misses
2362system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5429 # number of ReadReq MSHR uncacheable
2363system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5429 # number of ReadReq MSHR uncacheable
2364system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5284 # number of WriteReq MSHR uncacheable
2365system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5284 # number of WriteReq MSHR uncacheable
2366system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10713 # number of overall MSHR uncacheable misses
2367system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10713 # number of overall MSHR uncacheable misses
2368system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43326231000 # number of ReadReq MSHR miss cycles
2369system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43326231000 # number of ReadReq MSHR miss cycles
2370system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 30961849442 # number of WriteReq MSHR miss cycles
2371system.cpu1.dcache.WriteReq_mshr_miss_latency::total 30961849442 # number of WriteReq MSHR miss cycles
2372system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15267610500 # number of SoftPFReq MSHR miss cycles
2373system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15267610500 # number of SoftPFReq MSHR miss cycles
2374system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 16078596583 # number of WriteLineReq MSHR miss cycles
2375system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 16078596583 # number of WriteLineReq MSHR miss cycles
2376system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1709363500 # number of LoadLockedReq MSHR miss cycles
2377system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1709363500 # number of LoadLockedReq MSHR miss cycles
2378system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4955815500 # number of StoreCondReq MSHR miss cycles
2379system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4955815500 # number of StoreCondReq MSHR miss cycles
2380system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 6661500 # number of StoreCondFailReq MSHR miss cycles
2381system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 6661500 # number of StoreCondFailReq MSHR miss cycles
2382system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 74288080442 # number of demand (read+write) MSHR miss cycles
2383system.cpu1.dcache.demand_mshr_miss_latency::total 74288080442 # number of demand (read+write) MSHR miss cycles
2384system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 89555690942 # number of overall MSHR miss cycles
2385system.cpu1.dcache.overall_mshr_miss_latency::total 89555690942 # number of overall MSHR miss cycles
2386system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 604887500 # number of ReadReq MSHR uncacheable cycles
2387system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 604887500 # number of ReadReq MSHR uncacheable cycles
2388system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 670175500 # number of WriteReq MSHR uncacheable cycles
2389system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 670175500 # number of WriteReq MSHR uncacheable cycles
2390system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1275063000 # number of overall MSHR uncacheable cycles
2391system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1275063000 # number of overall MSHR uncacheable cycles
2392system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036612 # mshr miss rate for ReadReq accesses
2393system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036612 # mshr miss rate for ReadReq accesses
2394system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018633 # mshr miss rate for WriteReq accesses
2395system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018633 # mshr miss rate for WriteReq accesses
2396system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.794670 # mshr miss rate for SoftPFReq accesses
2397system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.794670 # mshr miss rate for SoftPFReq accesses
2398system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.882285 # mshr miss rate for WriteLineReq accesses
2399system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.882285 # mshr miss rate for WriteLineReq accesses
2400system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060162 # mshr miss rate for LoadLockedReq accesses
2401system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060162 # mshr miss rate for LoadLockedReq accesses
2402system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097570 # mshr miss rate for StoreCondReq accesses
2403system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097570 # mshr miss rate for StoreCondReq accesses
2404system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028192 # mshr miss rate for demand accesses
2405system.cpu1.dcache.demand_mshr_miss_rate::total 0.028192 # mshr miss rate for demand accesses
2406system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032320 # mshr miss rate for overall accesses
2407system.cpu1.dcache.overall_mshr_miss_rate::total 0.032320 # mshr miss rate for overall accesses
2408system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15235.463776 # average ReadReq mshr miss latency
2409system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15235.463776 # average ReadReq mshr miss latency
2410system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24286.374982 # average WriteReq mshr miss latency
2411system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24286.374982 # average WriteReq mshr miss latency
2412system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24281.593675 # average SoftPFReq mshr miss latency
2413system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24281.593675 # average SoftPFReq mshr miss latency
2414system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40373.123874 # average WriteLineReq mshr miss latency
2415system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 40373.123874 # average WriteLineReq mshr miss latency
2416system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14569.101152 # average LoadLockedReq mshr miss latency
2417system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14569.101152 # average LoadLockedReq mshr miss latency
2418system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26608.548234 # average StoreCondReq mshr miss latency
2419system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26608.548234 # average StoreCondReq mshr miss latency
2420system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
2421system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2422system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18037.041461 # average overall mshr miss latency
2423system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18037.041461 # average overall mshr miss latency
2424system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18864.103659 # average overall mshr miss latency
2425system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18864.103659 # average overall mshr miss latency
2426system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 111417.848591 # average ReadReq mshr uncacheable latency
2427system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 111417.848591 # average ReadReq mshr uncacheable latency
2428system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 126831.093868 # average WriteReq mshr uncacheable latency
2429system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 126831.093868 # average WriteReq mshr uncacheable latency
2430system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 119020.162419 # average overall mshr uncacheable latency
2431system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 119020.162419 # average overall mshr uncacheable latency
2432system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2433system.cpu1.icache.tags.replacements 5253385 # number of replacements
2434system.cpu1.icache.tags.tagsinuse 501.776230 # Cycle average of tags in use
2435system.cpu1.icache.tags.total_refs 182951519 # Total number of references to valid blocks.
2436system.cpu1.icache.tags.sampled_refs 5253897 # Sample count of references to valid blocks.
2437system.cpu1.icache.tags.avg_refs 34.822060 # Average number of references to valid blocks.
2438system.cpu1.icache.tags.warmup_cycle 8525973531000 # Cycle when the warmup percentage was hit.
2439system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.776230 # Average occupied blocks per requestor
2440system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980032 # Average percentage of cache occupancy
2441system.cpu1.icache.tags.occ_percent::total 0.980032 # Average percentage of cache occupancy
2442system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2443system.cpu1.icache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id
2444system.cpu1.icache.tags.age_task_id_blocks_1024::2 104 # Occupied blocks per task id
2445system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2446system.cpu1.icache.tags.tag_accesses 382279380 # Number of tag accesses
2447system.cpu1.icache.tags.data_accesses 382279380 # Number of data accesses
2448system.cpu1.icache.ReadReq_hits::cpu1.inst 182951519 # number of ReadReq hits
2449system.cpu1.icache.ReadReq_hits::total 182951519 # number of ReadReq hits
2450system.cpu1.icache.demand_hits::cpu1.inst 182951519 # number of demand (read+write) hits
2451system.cpu1.icache.demand_hits::total 182951519 # number of demand (read+write) hits
2452system.cpu1.icache.overall_hits::cpu1.inst 182951519 # number of overall hits
2453system.cpu1.icache.overall_hits::total 182951519 # number of overall hits
2454system.cpu1.icache.ReadReq_misses::cpu1.inst 5561220 # number of ReadReq misses
2455system.cpu1.icache.ReadReq_misses::total 5561220 # number of ReadReq misses
2456system.cpu1.icache.demand_misses::cpu1.inst 5561220 # number of demand (read+write) misses
2457system.cpu1.icache.demand_misses::total 5561220 # number of demand (read+write) misses
2458system.cpu1.icache.overall_misses::cpu1.inst 5561220 # number of overall misses
2459system.cpu1.icache.overall_misses::total 5561220 # number of overall misses
2460system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 62243274721 # number of ReadReq miss cycles
2461system.cpu1.icache.ReadReq_miss_latency::total 62243274721 # number of ReadReq miss cycles
2462system.cpu1.icache.demand_miss_latency::cpu1.inst 62243274721 # number of demand (read+write) miss cycles
2463system.cpu1.icache.demand_miss_latency::total 62243274721 # number of demand (read+write) miss cycles
2464system.cpu1.icache.overall_miss_latency::cpu1.inst 62243274721 # number of overall miss cycles
2465system.cpu1.icache.overall_miss_latency::total 62243274721 # number of overall miss cycles
2466system.cpu1.icache.ReadReq_accesses::cpu1.inst 188512739 # number of ReadReq accesses(hits+misses)
2467system.cpu1.icache.ReadReq_accesses::total 188512739 # number of ReadReq accesses(hits+misses)
2468system.cpu1.icache.demand_accesses::cpu1.inst 188512739 # number of demand (read+write) accesses
2469system.cpu1.icache.demand_accesses::total 188512739 # number of demand (read+write) accesses
2470system.cpu1.icache.overall_accesses::cpu1.inst 188512739 # number of overall (read+write) accesses
2471system.cpu1.icache.overall_accesses::total 188512739 # number of overall (read+write) accesses
2472system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029500 # miss rate for ReadReq accesses
2473system.cpu1.icache.ReadReq_miss_rate::total 0.029500 # miss rate for ReadReq accesses
2474system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029500 # miss rate for demand accesses
2475system.cpu1.icache.demand_miss_rate::total 0.029500 # miss rate for demand accesses
2476system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029500 # miss rate for overall accesses
2477system.cpu1.icache.overall_miss_rate::total 0.029500 # miss rate for overall accesses
2478system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11192.377701 # average ReadReq miss latency
2479system.cpu1.icache.ReadReq_avg_miss_latency::total 11192.377701 # average ReadReq miss latency
2480system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11192.377701 # average overall miss latency
2481system.cpu1.icache.demand_avg_miss_latency::total 11192.377701 # average overall miss latency
2482system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11192.377701 # average overall miss latency
2483system.cpu1.icache.overall_avg_miss_latency::total 11192.377701 # average overall miss latency
2484system.cpu1.icache.blocked_cycles::no_mshrs 9679381 # number of cycles access was blocked
2485system.cpu1.icache.blocked_cycles::no_targets 762 # number of cycles access was blocked
2486system.cpu1.icache.blocked::no_mshrs 668024 # number of cycles access was blocked
2487system.cpu1.icache.blocked::no_targets 6 # number of cycles access was blocked
2488system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.489571 # average number of cycles each access was blocked
2489system.cpu1.icache.avg_blocked_cycles::no_targets 127 # average number of cycles each access was blocked
2490system.cpu1.icache.fast_writes 0 # number of fast writes performed
2491system.cpu1.icache.cache_copies 0 # number of cache copies performed
2492system.cpu1.icache.writebacks::writebacks 5253385 # number of writebacks
2493system.cpu1.icache.writebacks::total 5253385 # number of writebacks
2494system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 307318 # number of ReadReq MSHR hits
2495system.cpu1.icache.ReadReq_mshr_hits::total 307318 # number of ReadReq MSHR hits
2496system.cpu1.icache.demand_mshr_hits::cpu1.inst 307318 # number of demand (read+write) MSHR hits
2497system.cpu1.icache.demand_mshr_hits::total 307318 # number of demand (read+write) MSHR hits
2498system.cpu1.icache.overall_mshr_hits::cpu1.inst 307318 # number of overall MSHR hits
2499system.cpu1.icache.overall_mshr_hits::total 307318 # number of overall MSHR hits
2500system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5253902 # number of ReadReq MSHR misses
2501system.cpu1.icache.ReadReq_mshr_misses::total 5253902 # number of ReadReq MSHR misses
2502system.cpu1.icache.demand_mshr_misses::cpu1.inst 5253902 # number of demand (read+write) MSHR misses
2503system.cpu1.icache.demand_mshr_misses::total 5253902 # number of demand (read+write) MSHR misses
2504system.cpu1.icache.overall_mshr_misses::cpu1.inst 5253902 # number of overall MSHR misses
2505system.cpu1.icache.overall_mshr_misses::total 5253902 # number of overall MSHR misses
2506system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
2507system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable
2508system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
2509system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses
2510system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 56076616223 # number of ReadReq MSHR miss cycles
2511system.cpu1.icache.ReadReq_mshr_miss_latency::total 56076616223 # number of ReadReq MSHR miss cycles
2512system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 56076616223 # number of demand (read+write) MSHR miss cycles
2513system.cpu1.icache.demand_mshr_miss_latency::total 56076616223 # number of demand (read+write) MSHR miss cycles
2514system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 56076616223 # number of overall MSHR miss cycles
2515system.cpu1.icache.overall_mshr_miss_latency::total 56076616223 # number of overall MSHR miss cycles
2516system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9266998 # number of ReadReq MSHR uncacheable cycles
2517system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9266998 # number of ReadReq MSHR uncacheable cycles
2518system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9266998 # number of overall MSHR uncacheable cycles
2519system.cpu1.icache.overall_mshr_uncacheable_latency::total 9266998 # number of overall MSHR uncacheable cycles
2520system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027870 # mshr miss rate for ReadReq accesses
2521system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027870 # mshr miss rate for ReadReq accesses
2522system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027870 # mshr miss rate for demand accesses
2523system.cpu1.icache.demand_mshr_miss_rate::total 0.027870 # mshr miss rate for demand accesses
2524system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027870 # mshr miss rate for overall accesses
2525system.cpu1.icache.overall_mshr_miss_rate::total 0.027870 # mshr miss rate for overall accesses
2526system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10673.327409 # average ReadReq mshr miss latency
2527system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10673.327409 # average ReadReq mshr miss latency
2528system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10673.327409 # average overall mshr miss latency
2529system.cpu1.icache.demand_avg_mshr_miss_latency::total 10673.327409 # average overall mshr miss latency
2530system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10673.327409 # average overall mshr miss latency
2531system.cpu1.icache.overall_avg_mshr_miss_latency::total 10673.327409 # average overall mshr miss latency
2532system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 138313.402985 # average ReadReq mshr uncacheable latency
2533system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 138313.402985 # average ReadReq mshr uncacheable latency
2534system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 138313.402985 # average overall mshr uncacheable latency
2535system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 138313.402985 # average overall mshr uncacheable latency
2536system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2537system.cpu1.l2cache.prefetcher.num_hwpf_issued 6897065 # number of hwpf issued
2538system.cpu1.l2cache.prefetcher.pfIdentified 6901426 # number of prefetch candidates identified
2539system.cpu1.l2cache.prefetcher.pfBufferHit 4002 # number of redundant prefetches already in prefetch queue
2540system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
2541system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2542system.cpu1.l2cache.prefetcher.pfSpanPage 806814 # number of prefetches not generated due to page crossing
2543system.cpu1.l2cache.tags.replacements 2026565 # number of replacements
2544system.cpu1.l2cache.tags.tagsinuse 13359.801047 # Cycle average of tags in use
2545system.cpu1.l2cache.tags.total_refs 15204091 # Total number of references to valid blocks.
2546system.cpu1.l2cache.tags.sampled_refs 2042184 # Sample count of references to valid blocks.
2547system.cpu1.l2cache.tags.avg_refs 7.445015 # Average number of references to valid blocks.
2548system.cpu1.l2cache.tags.warmup_cycle 10003867799500 # Cycle when the warmup percentage was hit.
2549system.cpu1.l2cache.tags.occ_blocks::writebacks 12523.198532 # Average occupied blocks per requestor
2550system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 53.208861 # Average occupied blocks per requestor
2551system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 55.513996 # Average occupied blocks per requestor
2552system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 727.879658 # Average occupied blocks per requestor
2553system.cpu1.l2cache.tags.occ_percent::writebacks 0.764355 # Average percentage of cache occupancy
2554system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003248 # Average percentage of cache occupancy
2555system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003388 # Average percentage of cache occupancy
2556system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.044426 # Average percentage of cache occupancy
2557system.cpu1.l2cache.tags.occ_percent::total 0.815418 # Average percentage of cache occupancy
2558system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1266 # Occupied blocks per task id
2559system.cpu1.l2cache.tags.occ_task_id_blocks::1023 101 # Occupied blocks per task id
2560system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14252 # Occupied blocks per task id
2561system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 87 # Occupied blocks per task id
2562system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 167 # Occupied blocks per task id
2563system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 620 # Occupied blocks per task id
2564system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 392 # Occupied blocks per task id
2565system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id
2566system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 76 # Occupied blocks per task id
2567system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id
2568system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id
2569system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 933 # Occupied blocks per task id
2570system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4753 # Occupied blocks per task id
2571system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4784 # Occupied blocks per task id
2572system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3782 # Occupied blocks per task id
2573system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.077271 # Percentage of cache occupancy per task id
2574system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006165 # Percentage of cache occupancy per task id
2575system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.869873 # Percentage of cache occupancy per task id
2576system.cpu1.l2cache.tags.tag_accesses 351102850 # Number of tag accesses
2577system.cpu1.l2cache.tags.data_accesses 351102850 # Number of data accesses
2578system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 535016 # number of ReadReq hits
2579system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 179387 # number of ReadReq hits
2580system.cpu1.l2cache.ReadReq_hits::total 714403 # number of ReadReq hits
2581system.cpu1.l2cache.WritebackDirty_hits::writebacks 3106842 # number of WritebackDirty hits
2582system.cpu1.l2cache.WritebackDirty_hits::total 3106842 # number of WritebackDirty hits
2583system.cpu1.l2cache.WritebackClean_hits::writebacks 7089221 # number of WritebackClean hits
2584system.cpu1.l2cache.WritebackClean_hits::total 7089221 # number of WritebackClean hits
2585system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 559 # number of UpgradeReq hits
2586system.cpu1.l2cache.UpgradeReq_hits::total 559 # number of UpgradeReq hits
2587system.cpu1.l2cache.ReadExReq_hits::cpu1.data 768937 # number of ReadExReq hits
2588system.cpu1.l2cache.ReadExReq_hits::total 768937 # number of ReadExReq hits
2589system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4743157 # number of ReadCleanReq hits
2590system.cpu1.l2cache.ReadCleanReq_hits::total 4743157 # number of ReadCleanReq hits
2591system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2644934 # number of ReadSharedReq hits
2592system.cpu1.l2cache.ReadSharedReq_hits::total 2644934 # number of ReadSharedReq hits
2593system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 173458 # number of InvalidateReq hits
2594system.cpu1.l2cache.InvalidateReq_hits::total 173458 # number of InvalidateReq hits
2595system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 535016 # number of demand (read+write) hits
2596system.cpu1.l2cache.demand_hits::cpu1.itb.walker 179387 # number of demand (read+write) hits
2597system.cpu1.l2cache.demand_hits::cpu1.inst 4743157 # number of demand (read+write) hits
2598system.cpu1.l2cache.demand_hits::cpu1.data 3413871 # number of demand (read+write) hits
2599system.cpu1.l2cache.demand_hits::total 8871431 # number of demand (read+write) hits
2600system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 535016 # number of overall hits
2601system.cpu1.l2cache.overall_hits::cpu1.itb.walker 179387 # number of overall hits
2602system.cpu1.l2cache.overall_hits::cpu1.inst 4743157 # number of overall hits
2603system.cpu1.l2cache.overall_hits::cpu1.data 3413871 # number of overall hits
2604system.cpu1.l2cache.overall_hits::total 8871431 # number of overall hits
2605system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11427 # number of ReadReq misses
2606system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8460 # number of ReadReq misses
2607system.cpu1.l2cache.ReadReq_misses::total 19887 # number of ReadReq misses
2608system.cpu1.l2cache.WritebackDirty_misses::writebacks 5 # number of WritebackDirty misses
2609system.cpu1.l2cache.WritebackDirty_misses::total 5 # number of WritebackDirty misses
2610system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 231672 # number of UpgradeReq misses
2611system.cpu1.l2cache.UpgradeReq_misses::total 231672 # number of UpgradeReq misses
2612system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 186238 # number of SCUpgradeReq misses
2613system.cpu1.l2cache.SCUpgradeReq_misses::total 186238 # number of SCUpgradeReq misses
2614system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 11 # number of SCUpgradeFailReq misses
2615system.cpu1.l2cache.SCUpgradeFailReq_misses::total 11 # number of SCUpgradeFailReq misses
2616system.cpu1.l2cache.ReadExReq_misses::cpu1.data 282579 # number of ReadExReq misses
2617system.cpu1.l2cache.ReadExReq_misses::total 282579 # number of ReadExReq misses
2618system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 510739 # number of ReadCleanReq misses
2619system.cpu1.l2cache.ReadCleanReq_misses::total 510739 # number of ReadCleanReq misses
2620system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 941159 # number of ReadSharedReq misses
2621system.cpu1.l2cache.ReadSharedReq_misses::total 941159 # number of ReadSharedReq misses
2622system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 223115 # number of InvalidateReq misses
2623system.cpu1.l2cache.InvalidateReq_misses::total 223115 # number of InvalidateReq misses
2624system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11427 # number of demand (read+write) misses
2625system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8460 # number of demand (read+write) misses
2626system.cpu1.l2cache.demand_misses::cpu1.inst 510739 # number of demand (read+write) misses
2627system.cpu1.l2cache.demand_misses::cpu1.data 1223738 # number of demand (read+write) misses
2628system.cpu1.l2cache.demand_misses::total 1754364 # number of demand (read+write) misses
2629system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11427 # number of overall misses
2630system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8460 # number of overall misses
2631system.cpu1.l2cache.overall_misses::cpu1.inst 510739 # number of overall misses
2632system.cpu1.l2cache.overall_misses::cpu1.data 1223738 # number of overall misses
2633system.cpu1.l2cache.overall_misses::total 1754364 # number of overall misses
2634system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 504816000 # number of ReadReq miss cycles
2635system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 376201500 # number of ReadReq miss cycles
2636system.cpu1.l2cache.ReadReq_miss_latency::total 881017500 # number of ReadReq miss cycles
2637system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3395371000 # number of UpgradeReq miss cycles
2638system.cpu1.l2cache.UpgradeReq_miss_latency::total 3395371000 # number of UpgradeReq miss cycles
2639system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1764127500 # number of SCUpgradeReq miss cycles
2640system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1764127500 # number of SCUpgradeReq miss cycles
2641system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 6519498 # number of SCUpgradeFailReq miss cycles
2642system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 6519498 # number of SCUpgradeFailReq miss cycles
2643system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 14960777499 # number of ReadExReq miss cycles
2644system.cpu1.l2cache.ReadExReq_miss_latency::total 14960777499 # number of ReadExReq miss cycles
2645system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 19472916000 # number of ReadCleanReq miss cycles
2646system.cpu1.l2cache.ReadCleanReq_miss_latency::total 19472916000 # number of ReadCleanReq miss cycles
2647system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 37255203986 # number of ReadSharedReq miss cycles
2648system.cpu1.l2cache.ReadSharedReq_miss_latency::total 37255203986 # number of ReadSharedReq miss cycles
2649system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 13917612499 # number of InvalidateReq miss cycles
2650system.cpu1.l2cache.InvalidateReq_miss_latency::total 13917612499 # number of InvalidateReq miss cycles
2651system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 504816000 # number of demand (read+write) miss cycles
2652system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 376201500 # number of demand (read+write) miss cycles
2653system.cpu1.l2cache.demand_miss_latency::cpu1.inst 19472916000 # number of demand (read+write) miss cycles
2654system.cpu1.l2cache.demand_miss_latency::cpu1.data 52215981485 # number of demand (read+write) miss cycles
2655system.cpu1.l2cache.demand_miss_latency::total 72569914985 # number of demand (read+write) miss cycles
2656system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 504816000 # number of overall miss cycles
2657system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 376201500 # number of overall miss cycles
2658system.cpu1.l2cache.overall_miss_latency::cpu1.inst 19472916000 # number of overall miss cycles
2659system.cpu1.l2cache.overall_miss_latency::cpu1.data 52215981485 # number of overall miss cycles
2660system.cpu1.l2cache.overall_miss_latency::total 72569914985 # number of overall miss cycles
2661system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 546443 # number of ReadReq accesses(hits+misses)
2662system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 187847 # number of ReadReq accesses(hits+misses)
2663system.cpu1.l2cache.ReadReq_accesses::total 734290 # number of ReadReq accesses(hits+misses)
2664system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3106847 # number of WritebackDirty accesses(hits+misses)
2665system.cpu1.l2cache.WritebackDirty_accesses::total 3106847 # number of WritebackDirty accesses(hits+misses)
2666system.cpu1.l2cache.WritebackClean_accesses::writebacks 7089221 # number of WritebackClean accesses(hits+misses)
2667system.cpu1.l2cache.WritebackClean_accesses::total 7089221 # number of WritebackClean accesses(hits+misses)
2668system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 232231 # number of UpgradeReq accesses(hits+misses)
2669system.cpu1.l2cache.UpgradeReq_accesses::total 232231 # number of UpgradeReq accesses(hits+misses)
2670system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 186238 # number of SCUpgradeReq accesses(hits+misses)
2671system.cpu1.l2cache.SCUpgradeReq_accesses::total 186238 # number of SCUpgradeReq accesses(hits+misses)
2672system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 11 # number of SCUpgradeFailReq accesses(hits+misses)
2673system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 11 # number of SCUpgradeFailReq accesses(hits+misses)
2674system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1051516 # number of ReadExReq accesses(hits+misses)
2675system.cpu1.l2cache.ReadExReq_accesses::total 1051516 # number of ReadExReq accesses(hits+misses)
2676system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5253896 # number of ReadCleanReq accesses(hits+misses)
2677system.cpu1.l2cache.ReadCleanReq_accesses::total 5253896 # number of ReadCleanReq accesses(hits+misses)
2678system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3586093 # number of ReadSharedReq accesses(hits+misses)
2679system.cpu1.l2cache.ReadSharedReq_accesses::total 3586093 # number of ReadSharedReq accesses(hits+misses)
2680system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 396573 # number of InvalidateReq accesses(hits+misses)
2681system.cpu1.l2cache.InvalidateReq_accesses::total 396573 # number of InvalidateReq accesses(hits+misses)
2682system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 546443 # number of demand (read+write) accesses
2683system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 187847 # number of demand (read+write) accesses
2684system.cpu1.l2cache.demand_accesses::cpu1.inst 5253896 # number of demand (read+write) accesses
2685system.cpu1.l2cache.demand_accesses::cpu1.data 4637609 # number of demand (read+write) accesses
2686system.cpu1.l2cache.demand_accesses::total 10625795 # number of demand (read+write) accesses
2687system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 546443 # number of overall (read+write) accesses
2688system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 187847 # number of overall (read+write) accesses
2689system.cpu1.l2cache.overall_accesses::cpu1.inst 5253896 # number of overall (read+write) accesses
2690system.cpu1.l2cache.overall_accesses::cpu1.data 4637609 # number of overall (read+write) accesses
2691system.cpu1.l2cache.overall_accesses::total 10625795 # number of overall (read+write) accesses
2692system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020912 # miss rate for ReadReq accesses
2693system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.045037 # miss rate for ReadReq accesses
2694system.cpu1.l2cache.ReadReq_miss_rate::total 0.027083 # miss rate for ReadReq accesses
2695system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000002 # miss rate for WritebackDirty accesses
2696system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000002 # miss rate for WritebackDirty accesses
2697system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.997593 # miss rate for UpgradeReq accesses
2698system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.997593 # miss rate for UpgradeReq accesses
2699system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
2700system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2701system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2702system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2703system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.268735 # miss rate for ReadExReq accesses
2704system.cpu1.l2cache.ReadExReq_miss_rate::total 0.268735 # miss rate for ReadExReq accesses
2705system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097211 # miss rate for ReadCleanReq accesses
2706system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097211 # miss rate for ReadCleanReq accesses
2707system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.262447 # miss rate for ReadSharedReq accesses
2708system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.262447 # miss rate for ReadSharedReq accesses
2709system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.562608 # miss rate for InvalidateReq accesses
2710system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.562608 # miss rate for InvalidateReq accesses
2711system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020912 # miss rate for demand accesses
2712system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.045037 # miss rate for demand accesses
2713system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097211 # miss rate for demand accesses
2714system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.263873 # miss rate for demand accesses
2715system.cpu1.l2cache.demand_miss_rate::total 0.165104 # miss rate for demand accesses
2716system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020912 # miss rate for overall accesses
2717system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.045037 # miss rate for overall accesses
2718system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097211 # miss rate for overall accesses
2719system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.263873 # miss rate for overall accesses
2720system.cpu1.l2cache.overall_miss_rate::total 0.165104 # miss rate for overall accesses
2721system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 44177.474403 # average ReadReq miss latency
2722system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 44468.262411 # average ReadReq miss latency
2723system.cpu1.l2cache.ReadReq_avg_miss_latency::total 44301.176648 # average ReadReq miss latency
2724system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14655.940295 # average UpgradeReq miss latency
2725system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14655.940295 # average UpgradeReq miss latency
2726system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9472.435808 # average SCUpgradeReq miss latency
2727system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9472.435808 # average SCUpgradeReq miss latency
2728system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 592681.636364 # average SCUpgradeFailReq miss latency
2729system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 592681.636364 # average SCUpgradeFailReq miss latency
2730system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52943.698927 # average ReadExReq miss latency
2731system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52943.698927 # average ReadExReq miss latency
2732system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38126.941549 # average ReadCleanReq miss latency
2733system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38126.941549 # average ReadCleanReq miss latency
2734system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 39584.389020 # average ReadSharedReq miss latency
2735system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 39584.389020 # average ReadSharedReq miss latency
2736system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 62378.650019 # average InvalidateReq miss latency
2737system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 62378.650019 # average InvalidateReq miss latency
2738system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 44177.474403 # average overall miss latency
2739system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 44468.262411 # average overall miss latency
2740system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38126.941549 # average overall miss latency
2741system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 42669.249043 # average overall miss latency
2742system.cpu1.l2cache.demand_avg_miss_latency::total 41365.369436 # average overall miss latency
2743system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 44177.474403 # average overall miss latency
2744system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 44468.262411 # average overall miss latency
2745system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38126.941549 # average overall miss latency
2746system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 42669.249043 # average overall miss latency
2747system.cpu1.l2cache.overall_avg_miss_latency::total 41365.369436 # average overall miss latency
2748system.cpu1.l2cache.blocked_cycles::no_mshrs 688 # number of cycles access was blocked
2749system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2750system.cpu1.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
2751system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2752system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 172 # average number of cycles each access was blocked
2753system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2754system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2755system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2756system.cpu1.l2cache.writebacks::writebacks 1085694 # number of writebacks
2757system.cpu1.l2cache.writebacks::total 1085694 # number of writebacks
2758system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 5 # number of ReadReq MSHR hits
2759system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 200 # number of ReadReq MSHR hits
2760system.cpu1.l2cache.ReadReq_mshr_hits::total 205 # number of ReadReq MSHR hits
2761system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 34736 # number of ReadExReq MSHR hits
2762system.cpu1.l2cache.ReadExReq_mshr_hits::total 34736 # number of ReadExReq MSHR hits
2763system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4713 # number of ReadSharedReq MSHR hits
2764system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4713 # number of ReadSharedReq MSHR hits
2765system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 6 # number of InvalidateReq MSHR hits
2766system.cpu1.l2cache.InvalidateReq_mshr_hits::total 6 # number of InvalidateReq MSHR hits
2767system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 5 # number of demand (read+write) MSHR hits
2768system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 200 # number of demand (read+write) MSHR hits
2769system.cpu1.l2cache.demand_mshr_hits::cpu1.data 39449 # number of demand (read+write) MSHR hits
2770system.cpu1.l2cache.demand_mshr_hits::total 39654 # number of demand (read+write) MSHR hits
2771system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 5 # number of overall MSHR hits
2772system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 200 # number of overall MSHR hits
2773system.cpu1.l2cache.overall_mshr_hits::cpu1.data 39449 # number of overall MSHR hits
2774system.cpu1.l2cache.overall_mshr_hits::total 39654 # number of overall MSHR hits
2775system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11422 # number of ReadReq MSHR misses
2776system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8260 # number of ReadReq MSHR misses
2777system.cpu1.l2cache.ReadReq_mshr_misses::total 19682 # number of ReadReq MSHR misses
2778system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 5 # number of WritebackDirty MSHR misses
2779system.cpu1.l2cache.WritebackDirty_mshr_misses::total 5 # number of WritebackDirty MSHR misses
2780system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 718118 # number of HardPFReq MSHR misses
2781system.cpu1.l2cache.HardPFReq_mshr_misses::total 718118 # number of HardPFReq MSHR misses
2782system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 231672 # number of UpgradeReq MSHR misses
2783system.cpu1.l2cache.UpgradeReq_mshr_misses::total 231672 # number of UpgradeReq MSHR misses
2784system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 186238 # number of SCUpgradeReq MSHR misses
2785system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 186238 # number of SCUpgradeReq MSHR misses
2786system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 11 # number of SCUpgradeFailReq MSHR misses
2787system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 11 # number of SCUpgradeFailReq MSHR misses
2788system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 247843 # number of ReadExReq MSHR misses
2789system.cpu1.l2cache.ReadExReq_mshr_misses::total 247843 # number of ReadExReq MSHR misses
2790system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 510739 # number of ReadCleanReq MSHR misses
2791system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 510739 # number of ReadCleanReq MSHR misses
2792system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 936446 # number of ReadSharedReq MSHR misses
2793system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 936446 # number of ReadSharedReq MSHR misses
2794system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 223109 # number of InvalidateReq MSHR misses
2795system.cpu1.l2cache.InvalidateReq_mshr_misses::total 223109 # number of InvalidateReq MSHR misses
2796system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11422 # number of demand (read+write) MSHR misses
2797system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8260 # number of demand (read+write) MSHR misses
2798system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 510739 # number of demand (read+write) MSHR misses
2799system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1184289 # number of demand (read+write) MSHR misses
2800system.cpu1.l2cache.demand_mshr_misses::total 1714710 # number of demand (read+write) MSHR misses
2801system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11422 # number of overall MSHR misses
2802system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8260 # number of overall MSHR misses
2803system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 510739 # number of overall MSHR misses
2804system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1184289 # number of overall MSHR misses
2805system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 718118 # number of overall MSHR misses
2806system.cpu1.l2cache.overall_mshr_misses::total 2432828 # number of overall MSHR misses
2807system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
2808system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5429 # number of ReadReq MSHR uncacheable
2809system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5496 # number of ReadReq MSHR uncacheable
2810system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5284 # number of WriteReq MSHR uncacheable
2811system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5284 # number of WriteReq MSHR uncacheable
2812system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
2813system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10713 # number of overall MSHR uncacheable misses
2814system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10780 # number of overall MSHR uncacheable misses
2815system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 436185000 # number of ReadReq MSHR miss cycles
2816system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 314747000 # number of ReadReq MSHR miss cycles
2817system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 750932000 # number of ReadReq MSHR miss cycles
2818system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 40592481689 # number of HardPFReq MSHR miss cycles
2819system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 40592481689 # number of HardPFReq MSHR miss cycles
2820system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7117149993 # number of UpgradeReq MSHR miss cycles
2821system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7117149993 # number of UpgradeReq MSHR miss cycles
2822system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3556198494 # number of SCUpgradeReq MSHR miss cycles
2823system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3556198494 # number of SCUpgradeReq MSHR miss cycles
2824system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 5961498 # number of SCUpgradeFailReq MSHR miss cycles
2825system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 5961498 # number of SCUpgradeFailReq MSHR miss cycles
2826system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11593238999 # number of ReadExReq MSHR miss cycles
2827system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11593238999 # number of ReadExReq MSHR miss cycles
2828system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 16408482000 # number of ReadCleanReq MSHR miss cycles
2829system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 16408482000 # number of ReadCleanReq MSHR miss cycles
2830system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 31352302486 # number of ReadSharedReq MSHR miss cycles
2831system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 31352302486 # number of ReadSharedReq MSHR miss cycles
2832system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 12578456999 # number of InvalidateReq MSHR miss cycles
2833system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 12578456999 # number of InvalidateReq MSHR miss cycles
2834system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 436185000 # number of demand (read+write) MSHR miss cycles
2835system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 314747000 # number of demand (read+write) MSHR miss cycles
2836system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 16408482000 # number of demand (read+write) MSHR miss cycles
2837system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 42945541485 # number of demand (read+write) MSHR miss cycles
2838system.cpu1.l2cache.demand_mshr_miss_latency::total 60104955485 # number of demand (read+write) MSHR miss cycles
2839system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 436185000 # number of overall MSHR miss cycles
2840system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 314747000 # number of overall MSHR miss cycles
2841system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16408482000 # number of overall MSHR miss cycles
2842system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 42945541485 # number of overall MSHR miss cycles
2843system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 40592481689 # number of overall MSHR miss cycles
2844system.cpu1.l2cache.overall_mshr_miss_latency::total 100697437174 # number of overall MSHR miss cycles
2845system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8763500 # number of ReadReq MSHR uncacheable cycles
2846system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 561342500 # number of ReadReq MSHR uncacheable cycles
2847system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 570106000 # number of ReadReq MSHR uncacheable cycles
2848system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 630451500 # number of WriteReq MSHR uncacheable cycles
2849system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 630451500 # number of WriteReq MSHR uncacheable cycles
2850system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8763500 # number of overall MSHR uncacheable cycles
2851system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1191794000 # number of overall MSHR uncacheable cycles
2852system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1200557500 # number of overall MSHR uncacheable cycles
2853system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020902 # mshr miss rate for ReadReq accesses
2854system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.043972 # mshr miss rate for ReadReq accesses
2855system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.026804 # mshr miss rate for ReadReq accesses
2856system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for WritebackDirty accesses
2857system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000002 # mshr miss rate for WritebackDirty accesses
2858system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2859system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2860system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997593 # mshr miss rate for UpgradeReq accesses
2861system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997593 # mshr miss rate for UpgradeReq accesses
2862system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2863system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2864system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2865system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2866system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.235701 # mshr miss rate for ReadExReq accesses
2867system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.235701 # mshr miss rate for ReadExReq accesses
2868system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.097211 # mshr miss rate for ReadCleanReq accesses
2869system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097211 # mshr miss rate for ReadCleanReq accesses
2870system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.261133 # mshr miss rate for ReadSharedReq accesses
2871system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.261133 # mshr miss rate for ReadSharedReq accesses
2872system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.562593 # mshr miss rate for InvalidateReq accesses
2873system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.562593 # mshr miss rate for InvalidateReq accesses
2874system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020902 # mshr miss rate for demand accesses
2875system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.043972 # mshr miss rate for demand accesses
2876system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.097211 # mshr miss rate for demand accesses
2877system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.255366 # mshr miss rate for demand accesses
2878system.cpu1.l2cache.demand_mshr_miss_rate::total 0.161372 # mshr miss rate for demand accesses
2879system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020902 # mshr miss rate for overall accesses
2880system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.043972 # mshr miss rate for overall accesses
2881system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.097211 # mshr miss rate for overall accesses
2882system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.255366 # mshr miss rate for overall accesses
2883system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2884system.cpu1.l2cache.overall_mshr_miss_rate::total 0.228955 # mshr miss rate for overall accesses
2885system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 38188.145684 # average ReadReq mshr miss latency
2886system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38104.963680 # average ReadReq mshr miss latency
2887system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 38153.236460 # average ReadReq mshr miss latency
2888system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 56526.199996 # average HardPFReq mshr miss latency
2889system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 56526.199996 # average HardPFReq mshr miss latency
2890system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 30720.803520 # average UpgradeReq mshr miss latency
2891system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30720.803520 # average UpgradeReq mshr miss latency
2892system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19094.913466 # average SCUpgradeReq mshr miss latency
2893system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19094.913466 # average SCUpgradeReq mshr miss latency
2894system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 541954.363636 # average SCUpgradeFailReq mshr miss latency
2895system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 541954.363636 # average SCUpgradeFailReq mshr miss latency
2896system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46776.544018 # average ReadExReq mshr miss latency
2897system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46776.544018 # average ReadExReq mshr miss latency
2898system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32126.941549 # average ReadCleanReq mshr miss latency
2899system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32126.941549 # average ReadCleanReq mshr miss latency
2900system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 33480.096542 # average ReadSharedReq mshr miss latency
2901system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33480.096542 # average ReadSharedReq mshr miss latency
2902system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 56378.079768 # average InvalidateReq mshr miss latency
2903system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 56378.079768 # average InvalidateReq mshr miss latency
2904system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 38188.145684 # average overall mshr miss latency
2905system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38104.963680 # average overall mshr miss latency
2906system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32126.941549 # average overall mshr miss latency
2907system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36262.720911 # average overall mshr miss latency
2908system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35052.548527 # average overall mshr miss latency
2909system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 38188.145684 # average overall mshr miss latency
2910system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38104.963680 # average overall mshr miss latency
2911system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32126.941549 # average overall mshr miss latency
2912system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36262.720911 # average overall mshr miss latency
2913system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 56526.199996 # average overall mshr miss latency
2914system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 41391.104169 # average overall mshr miss latency
2915system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 130798.507463 # average ReadReq mshr uncacheable latency
2916system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 103397.034445 # average ReadReq mshr uncacheable latency
2917system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 103731.077147 # average ReadReq mshr uncacheable latency
2918system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 119313.304315 # average WriteReq mshr uncacheable latency
2919system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 119313.304315 # average WriteReq mshr uncacheable latency
2920system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 130798.507463 # average overall mshr uncacheable latency
2921system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 111247.456361 # average overall mshr uncacheable latency
2922system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 111368.970315 # average overall mshr uncacheable latency
2923system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2924system.cpu1.toL2Bus.snoop_filter.tot_requests 21246355 # Total number of requests made to the snoop filter.
2925system.cpu1.toL2Bus.snoop_filter.hit_single_requests 10958434 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2926system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1131 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2927system.cpu1.toL2Bus.snoop_filter.tot_snoops 1866438 # Total number of snoops made to the snoop filter.
2928system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1866138 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2929system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 300 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2930system.cpu1.toL2Bus.trans_dist::ReadReq 825754 # Transaction distribution
2931system.cpu1.toL2Bus.trans_dist::ReadResp 9752282 # Transaction distribution
2932system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
2933system.cpu1.toL2Bus.trans_dist::WriteReq 5284 # Transaction distribution
2934system.cpu1.toL2Bus.trans_dist::WriteResp 5284 # Transaction distribution
2935system.cpu1.toL2Bus.trans_dist::WritebackDirty 4201386 # Transaction distribution
2936system.cpu1.toL2Bus.trans_dist::WritebackClean 7090370 # Transaction distribution
2937system.cpu1.toL2Bus.trans_dist::CleanEvict 2466487 # Transaction distribution
2938system.cpu1.toL2Bus.trans_dist::HardPFReq 905169 # Transaction distribution
2939system.cpu1.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution
2940system.cpu1.toL2Bus.trans_dist::UpgradeReq 447608 # Transaction distribution
2941system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337242 # Transaction distribution
2942system.cpu1.toL2Bus.trans_dist::UpgradeResp 479463 # Transaction distribution
2943system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 119 # Transaction distribution
2944system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 201 # Transaction distribution
2945system.cpu1.toL2Bus.trans_dist::ReadExReq 1130462 # Transaction distribution
2946system.cpu1.toL2Bus.trans_dist::ReadExResp 1058321 # Transaction distribution
2947system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5253902 # Transaction distribution
2948system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4579290 # Transaction distribution
2949system.cpu1.toL2Bus.trans_dist::InvalidateReq 402900 # Transaction distribution
2950system.cpu1.toL2Bus.trans_dist::InvalidateResp 396573 # Transaction distribution
2951system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15761317 # Packet count per connected master and slave (bytes)
2952system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16025111 # Packet count per connected master and slave (bytes)
2953system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 394044 # Packet count per connected master and slave (bytes)
2954system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1160504 # Packet count per connected master and slave (bytes)
2955system.cpu1.toL2Bus.pkt_count::total 33340976 # Packet count per connected master and slave (bytes)
2956system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 672467056 # Cumulative packet size per connected master and slave (bytes)
2957system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 619232766 # Cumulative packet size per connected master and slave (bytes)
2958system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1502776 # Cumulative packet size per connected master and slave (bytes)
2959system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4371544 # Cumulative packet size per connected master and slave (bytes)
2960system.cpu1.toL2Bus.pkt_size::total 1297574142 # Cumulative packet size per connected master and slave (bytes)
2961system.cpu1.toL2Bus.snoops 6151657 # Total snoops (count)
2962system.cpu1.toL2Bus.snoop_fanout::samples 17448758 # Request fanout histogram
2963system.cpu1.toL2Bus.snoop_fanout::mean 0.126682 # Request fanout histogram
2964system.cpu1.toL2Bus.snoop_fanout::stdev 0.332668 # Request fanout histogram
2965system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2966system.cpu1.toL2Bus.snoop_fanout::0 15238612 87.33% 87.33% # Request fanout histogram
2967system.cpu1.toL2Bus.snoop_fanout::1 2209846 12.66% 100.00% # Request fanout histogram
2968system.cpu1.toL2Bus.snoop_fanout::2 300 0.00% 100.00% # Request fanout histogram
2969system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2970system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2971system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2972system.cpu1.toL2Bus.snoop_fanout::total 17448758 # Request fanout histogram
2973system.cpu1.toL2Bus.reqLayer0.occupancy 21067285470 # Layer occupancy (ticks)
2974system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2975system.cpu1.toL2Bus.snoopLayer0.occupancy 170823638 # Layer occupancy (ticks)
2976system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2977system.cpu1.toL2Bus.respLayer0.occupancy 7886135987 # Layer occupancy (ticks)
2978system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2979system.cpu1.toL2Bus.respLayer1.occupancy 7380840948 # Layer occupancy (ticks)
2980system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2981system.cpu1.toL2Bus.respLayer2.occupancy 206620146 # Layer occupancy (ticks)
2982system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2983system.cpu1.toL2Bus.respLayer3.occupancy 614769571 # Layer occupancy (ticks)
2984system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2985system.iobus.trans_dist::ReadReq 40283 # Transaction distribution
2986system.iobus.trans_dist::ReadResp 40283 # Transaction distribution
2987system.iobus.trans_dist::WriteReq 136631 # Transaction distribution
2988system.iobus.trans_dist::WriteResp 136631 # Transaction distribution
2989system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47650 # Packet count per connected master and slave (bytes)
2990system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2991system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2992system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2993system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2994system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2995system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2996system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2997system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2998system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2999system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
3000system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
3001system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
3002system.iobus.pkt_count_system.bridge.master::total 122584 # Packet count per connected master and slave (bytes)
3003system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231164 # Packet count per connected master and slave (bytes)
3004system.iobus.pkt_count_system.realview.ide.dma::total 231164 # Packet count per connected master and slave (bytes)
3005system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
3006system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
3007system.iobus.pkt_count::total 353828 # Packet count per connected master and slave (bytes)
3008system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47670 # Cumulative packet size per connected master and slave (bytes)
3009system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
3010system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
3011system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
3012system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
3013system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
3014system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
3015system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
3016system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
3017system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
3018system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
3019system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
3020system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
3021system.iobus.pkt_size_system.bridge.master::total 155691 # Cumulative packet size per connected master and slave (bytes)
3022system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338672 # Cumulative packet size per connected master and slave (bytes)
3023system.iobus.pkt_size_system.realview.ide.dma::total 7338672 # Cumulative packet size per connected master and slave (bytes)
3024system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
3025system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
3026system.iobus.pkt_size::total 7496449 # Cumulative packet size per connected master and slave (bytes)
3027system.iobus.reqLayer0.occupancy 36944000 # Layer occupancy (ticks)
3028system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
3029system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
3030system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
3031system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks)
3032system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
3033system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks)
3034system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
3035system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks)
3036system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
3037system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
3038system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
3039system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks)
3040system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
3041system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks)
3042system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
3043system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
3044system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
3045system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks)
3046system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
3047system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks)
3048system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
3049system.iobus.reqLayer23.occupancy 24787502 # Layer occupancy (ticks)
3050system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
3051system.iobus.reqLayer24.occupancy 36442000 # Layer occupancy (ticks)
3052system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
3053system.iobus.reqLayer25.occupancy 567400129 # Layer occupancy (ticks)
3054system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
3055system.iobus.respLayer0.occupancy 92684000 # Layer occupancy (ticks)
3056system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
3057system.iobus.respLayer3.occupancy 147860000 # Layer occupancy (ticks)
3058system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
3059system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
3060system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
3061system.iocache.tags.replacements 115578 # number of replacements
3062system.iocache.tags.tagsinuse 11.298905 # Cycle average of tags in use
3063system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
3064system.iocache.tags.sampled_refs 115594 # Sample count of references to valid blocks.
3065system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
3066system.iocache.tags.warmup_cycle 9125697698000 # Cycle when the warmup percentage was hit.
3067system.iocache.tags.occ_blocks::realview.ethernet 7.418105 # Average occupied blocks per requestor
3068system.iocache.tags.occ_blocks::realview.ide 3.880800 # Average occupied blocks per requestor
3069system.iocache.tags.occ_percent::realview.ethernet 0.463632 # Average percentage of cache occupancy
3070system.iocache.tags.occ_percent::realview.ide 0.242550 # Average percentage of cache occupancy
3071system.iocache.tags.occ_percent::total 0.706182 # Average percentage of cache occupancy
3072system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
3073system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
3074system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
3075system.iocache.tags.tag_accesses 1040595 # Number of tag accesses
3076system.iocache.tags.data_accesses 1040595 # Number of data accesses
3077system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
3078system.iocache.ReadReq_misses::realview.ide 8854 # number of ReadReq misses
3079system.iocache.ReadReq_misses::total 8891 # number of ReadReq misses
3080system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
3081system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
3082system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
3083system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
3084system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
3085system.iocache.demand_misses::realview.ide 8854 # number of demand (read+write) misses
3086system.iocache.demand_misses::total 8894 # number of demand (read+write) misses
3087system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
3088system.iocache.overall_misses::realview.ide 8854 # number of overall misses
3089system.iocache.overall_misses::total 8894 # number of overall misses
3090system.iocache.ReadReq_miss_latency::realview.ethernet 5230500 # number of ReadReq miss cycles
3091system.iocache.ReadReq_miss_latency::realview.ide 1713293012 # number of ReadReq miss cycles
3092system.iocache.ReadReq_miss_latency::total 1718523512 # number of ReadReq miss cycles
3093system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
3094system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
3095system.iocache.WriteLineReq_miss_latency::realview.ide 13529785617 # number of WriteLineReq miss cycles
3096system.iocache.WriteLineReq_miss_latency::total 13529785617 # number of WriteLineReq miss cycles
3097system.iocache.demand_miss_latency::realview.ethernet 5599500 # number of demand (read+write) miss cycles
3098system.iocache.demand_miss_latency::realview.ide 1713293012 # number of demand (read+write) miss cycles
3099system.iocache.demand_miss_latency::total 1718892512 # number of demand (read+write) miss cycles
3100system.iocache.overall_miss_latency::realview.ethernet 5599500 # number of overall miss cycles
3101system.iocache.overall_miss_latency::realview.ide 1713293012 # number of overall miss cycles
3102system.iocache.overall_miss_latency::total 1718892512 # number of overall miss cycles
3103system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
3104system.iocache.ReadReq_accesses::realview.ide 8854 # number of ReadReq accesses(hits+misses)
3105system.iocache.ReadReq_accesses::total 8891 # number of ReadReq accesses(hits+misses)
3106system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
3107system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
3108system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
3109system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
3110system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
3111system.iocache.demand_accesses::realview.ide 8854 # number of demand (read+write) accesses
3112system.iocache.demand_accesses::total 8894 # number of demand (read+write) accesses
3113system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
3114system.iocache.overall_accesses::realview.ide 8854 # number of overall (read+write) accesses
3115system.iocache.overall_accesses::total 8894 # number of overall (read+write) accesses
3116system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
3117system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
3118system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
3119system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
3120system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
3121system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
3122system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
3123system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
3124system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
3125system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
3126system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
3127system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
3128system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
3129system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141364.864865 # average ReadReq miss latency
3130system.iocache.ReadReq_avg_miss_latency::realview.ide 193504.970861 # average ReadReq miss latency
3131system.iocache.ReadReq_avg_miss_latency::total 193287.989203 # average ReadReq miss latency
3132system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
3133system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
3134system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126768.848072 # average WriteLineReq miss latency
3135system.iocache.WriteLineReq_avg_miss_latency::total 126768.848072 # average WriteLineReq miss latency
3136system.iocache.demand_avg_miss_latency::realview.ethernet 139987.500000 # average overall miss latency
3137system.iocache.demand_avg_miss_latency::realview.ide 193504.970861 # average overall miss latency
3138system.iocache.demand_avg_miss_latency::total 193264.280639 # average overall miss latency
3139system.iocache.overall_avg_miss_latency::realview.ethernet 139987.500000 # average overall miss latency
3140system.iocache.overall_avg_miss_latency::realview.ide 193504.970861 # average overall miss latency
3141system.iocache.overall_avg_miss_latency::total 193264.280639 # average overall miss latency
3142system.iocache.blocked_cycles::no_mshrs 34686 # number of cycles access was blocked
3143system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
3144system.iocache.blocked::no_mshrs 3488 # number of cycles access was blocked
3145system.iocache.blocked::no_targets 0 # number of cycles access was blocked
3146system.iocache.avg_blocked_cycles::no_mshrs 9.944381 # average number of cycles each access was blocked
3147system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3148system.iocache.fast_writes 0 # number of fast writes performed
3149system.iocache.cache_copies 0 # number of cache copies performed
3150system.iocache.writebacks::writebacks 106694 # number of writebacks
3151system.iocache.writebacks::total 106694 # number of writebacks
3152system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
3153system.iocache.ReadReq_mshr_misses::realview.ide 8854 # number of ReadReq MSHR misses
3154system.iocache.ReadReq_mshr_misses::total 8891 # number of ReadReq MSHR misses
3155system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
3156system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
3157system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
3158system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
3159system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
3160system.iocache.demand_mshr_misses::realview.ide 8854 # number of demand (read+write) MSHR misses
3161system.iocache.demand_mshr_misses::total 8894 # number of demand (read+write) MSHR misses
3162system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
3163system.iocache.overall_mshr_misses::realview.ide 8854 # number of overall MSHR misses
3164system.iocache.overall_mshr_misses::total 8894 # number of overall MSHR misses
3165system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3380500 # number of ReadReq MSHR miss cycles
3166system.iocache.ReadReq_mshr_miss_latency::realview.ide 1270593012 # number of ReadReq MSHR miss cycles
3167system.iocache.ReadReq_mshr_miss_latency::total 1273973512 # number of ReadReq MSHR miss cycles
3168system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
3169system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
3170system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8187257903 # number of WriteLineReq MSHR miss cycles
3171system.iocache.WriteLineReq_mshr_miss_latency::total 8187257903 # number of WriteLineReq MSHR miss cycles
3172system.iocache.demand_mshr_miss_latency::realview.ethernet 3599500 # number of demand (read+write) MSHR miss cycles
3173system.iocache.demand_mshr_miss_latency::realview.ide 1270593012 # number of demand (read+write) MSHR miss cycles
3174system.iocache.demand_mshr_miss_latency::total 1274192512 # number of demand (read+write) MSHR miss cycles
3175system.iocache.overall_mshr_miss_latency::realview.ethernet 3599500 # number of overall MSHR miss cycles
3176system.iocache.overall_mshr_miss_latency::realview.ide 1270593012 # number of overall MSHR miss cycles
3177system.iocache.overall_mshr_miss_latency::total 1274192512 # number of overall MSHR miss cycles
3178system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
3179system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
3180system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
3181system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
3182system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
3183system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
3184system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
3185system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
3186system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
3187system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
3188system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
3189system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
3190system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
3191system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91364.864865 # average ReadReq mshr miss latency
3192system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 143504.970861 # average ReadReq mshr miss latency
3193system.iocache.ReadReq_avg_mshr_miss_latency::total 143287.989203 # average ReadReq mshr miss latency
3194system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
3195system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
3196system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76711.433766 # average WriteLineReq mshr miss latency
3197system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76711.433766 # average WriteLineReq mshr miss latency
3198system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89987.500000 # average overall mshr miss latency
3199system.iocache.demand_avg_mshr_miss_latency::realview.ide 143504.970861 # average overall mshr miss latency
3200system.iocache.demand_avg_mshr_miss_latency::total 143264.280639 # average overall mshr miss latency
3201system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89987.500000 # average overall mshr miss latency
3202system.iocache.overall_avg_mshr_miss_latency::realview.ide 143504.970861 # average overall mshr miss latency
3203system.iocache.overall_avg_mshr_miss_latency::total 143264.280639 # average overall mshr miss latency
3204system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
3205system.l2c.tags.replacements 1550465 # number of replacements
3206system.l2c.tags.tagsinuse 63029.233494 # Cycle average of tags in use
3207system.l2c.tags.total_refs 6222316 # Total number of references to valid blocks.
3208system.l2c.tags.sampled_refs 1609843 # Sample count of references to valid blocks.
3209system.l2c.tags.avg_refs 3.865169 # Average number of references to valid blocks.
3210system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
3211system.l2c.tags.occ_blocks::writebacks 21079.795710 # Average occupied blocks per requestor
3212system.l2c.tags.occ_blocks::cpu0.dtb.walker 246.485529 # Average occupied blocks per requestor
3213system.l2c.tags.occ_blocks::cpu0.itb.walker 359.766358 # Average occupied blocks per requestor
3214system.l2c.tags.occ_blocks::cpu0.inst 4048.838393 # Average occupied blocks per requestor
3215system.l2c.tags.occ_blocks::cpu0.data 9854.606144 # Average occupied blocks per requestor
3216system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 15763.557433 # Average occupied blocks per requestor
3217system.l2c.tags.occ_blocks::cpu1.dtb.walker 96.147248 # Average occupied blocks per requestor
3218system.l2c.tags.occ_blocks::cpu1.itb.walker 123.490081 # Average occupied blocks per requestor
3219system.l2c.tags.occ_blocks::cpu1.inst 3067.505167 # Average occupied blocks per requestor
3220system.l2c.tags.occ_blocks::cpu1.data 4557.367994 # Average occupied blocks per requestor
3221system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3831.673436 # Average occupied blocks per requestor
3222system.l2c.tags.occ_percent::writebacks 0.321652 # Average percentage of cache occupancy
3223system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003761 # Average percentage of cache occupancy
3224system.l2c.tags.occ_percent::cpu0.itb.walker 0.005490 # Average percentage of cache occupancy
3225system.l2c.tags.occ_percent::cpu0.inst 0.061780 # Average percentage of cache occupancy
3226system.l2c.tags.occ_percent::cpu0.data 0.150369 # Average percentage of cache occupancy
3227system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.240533 # Average percentage of cache occupancy
3228system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001467 # Average percentage of cache occupancy
3229system.l2c.tags.occ_percent::cpu1.itb.walker 0.001884 # Average percentage of cache occupancy
3230system.l2c.tags.occ_percent::cpu1.inst 0.046806 # Average percentage of cache occupancy
3231system.l2c.tags.occ_percent::cpu1.data 0.069540 # Average percentage of cache occupancy
3232system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.058467 # Average percentage of cache occupancy
3233system.l2c.tags.occ_percent::total 0.961750 # Average percentage of cache occupancy
3234system.l2c.tags.occ_task_id_blocks::1022 10787 # Occupied blocks per task id
3235system.l2c.tags.occ_task_id_blocks::1023 260 # Occupied blocks per task id
3236system.l2c.tags.occ_task_id_blocks::1024 48331 # Occupied blocks per task id
3237system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
3238system.l2c.tags.age_task_id_blocks_1022::2 1394 # Occupied blocks per task id
3239system.l2c.tags.age_task_id_blocks_1022::3 453 # Occupied blocks per task id
3240system.l2c.tags.age_task_id_blocks_1022::4 8932 # Occupied blocks per task id
3241system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
3242system.l2c.tags.age_task_id_blocks_1023::4 256 # Occupied blocks per task id
3243system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
3244system.l2c.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id
3245system.l2c.tags.age_task_id_blocks_1024::2 2970 # Occupied blocks per task id
3246system.l2c.tags.age_task_id_blocks_1024::3 5917 # Occupied blocks per task id
3247system.l2c.tags.age_task_id_blocks_1024::4 39033 # Occupied blocks per task id
3248system.l2c.tags.occ_task_id_percent::1022 0.164597 # Percentage of cache occupancy per task id
3249system.l2c.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id
3250system.l2c.tags.occ_task_id_percent::1024 0.737473 # Percentage of cache occupancy per task id
3251system.l2c.tags.tag_accesses 79030194 # Number of tag accesses
3252system.l2c.tags.data_accesses 79030194 # Number of data accesses
3253system.l2c.WritebackDirty_hits::writebacks 2899125 # number of WritebackDirty hits
3254system.l2c.WritebackDirty_hits::total 2899125 # number of WritebackDirty hits
3255system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
3256system.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits
3257system.l2c.UpgradeReq_hits::cpu0.data 179542 # number of UpgradeReq hits
3258system.l2c.UpgradeReq_hits::cpu1.data 131751 # number of UpgradeReq hits
3259system.l2c.UpgradeReq_hits::total 311293 # number of UpgradeReq hits
3260system.l2c.SCUpgradeReq_hits::cpu0.data 44871 # number of SCUpgradeReq hits
3261system.l2c.SCUpgradeReq_hits::cpu1.data 37587 # number of SCUpgradeReq hits
3262system.l2c.SCUpgradeReq_hits::total 82458 # number of SCUpgradeReq hits
3263system.l2c.ReadExReq_hits::cpu0.data 177447 # number of ReadExReq hits
3264system.l2c.ReadExReq_hits::cpu1.data 158953 # number of ReadExReq hits
3265system.l2c.ReadExReq_hits::total 336400 # number of ReadExReq hits
3266system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6841 # number of ReadSharedReq hits
3267system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4759 # number of ReadSharedReq hits
3268system.l2c.ReadSharedReq_hits::cpu0.inst 555678 # number of ReadSharedReq hits
3269system.l2c.ReadSharedReq_hits::cpu0.data 657090 # number of ReadSharedReq hits
3270system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 315358 # number of ReadSharedReq hits
3271system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6220 # number of ReadSharedReq hits
3272system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4455 # number of ReadSharedReq hits
3273system.l2c.ReadSharedReq_hits::cpu1.inst 465798 # number of ReadSharedReq hits
3274system.l2c.ReadSharedReq_hits::cpu1.data 550752 # number of ReadSharedReq hits
3275system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 288275 # number of ReadSharedReq hits
3276system.l2c.ReadSharedReq_hits::total 2855226 # number of ReadSharedReq hits
3277system.l2c.demand_hits::cpu0.dtb.walker 6841 # number of demand (read+write) hits
3278system.l2c.demand_hits::cpu0.itb.walker 4759 # number of demand (read+write) hits
3279system.l2c.demand_hits::cpu0.inst 555678 # number of demand (read+write) hits
3280system.l2c.demand_hits::cpu0.data 834537 # number of demand (read+write) hits
3281system.l2c.demand_hits::cpu0.l2cache.prefetcher 315358 # number of demand (read+write) hits
3282system.l2c.demand_hits::cpu1.dtb.walker 6220 # number of demand (read+write) hits
3283system.l2c.demand_hits::cpu1.itb.walker 4455 # number of demand (read+write) hits
3284system.l2c.demand_hits::cpu1.inst 465798 # number of demand (read+write) hits
3285system.l2c.demand_hits::cpu1.data 709705 # number of demand (read+write) hits
3286system.l2c.demand_hits::cpu1.l2cache.prefetcher 288275 # number of demand (read+write) hits
3287system.l2c.demand_hits::total 3191626 # number of demand (read+write) hits
3288system.l2c.overall_hits::cpu0.dtb.walker 6841 # number of overall hits
3289system.l2c.overall_hits::cpu0.itb.walker 4759 # number of overall hits
3290system.l2c.overall_hits::cpu0.inst 555678 # number of overall hits
3291system.l2c.overall_hits::cpu0.data 834537 # number of overall hits
3292system.l2c.overall_hits::cpu0.l2cache.prefetcher 315358 # number of overall hits
3293system.l2c.overall_hits::cpu1.dtb.walker 6220 # number of overall hits
3294system.l2c.overall_hits::cpu1.itb.walker 4455 # number of overall hits
3295system.l2c.overall_hits::cpu1.inst 465798 # number of overall hits
3296system.l2c.overall_hits::cpu1.data 709705 # number of overall hits
3297system.l2c.overall_hits::cpu1.l2cache.prefetcher 288275 # number of overall hits
3298system.l2c.overall_hits::total 3191626 # number of overall hits
3299system.l2c.UpgradeReq_misses::cpu0.data 65170 # number of UpgradeReq misses
3300system.l2c.UpgradeReq_misses::cpu1.data 60899 # number of UpgradeReq misses
3301system.l2c.UpgradeReq_misses::total 126069 # number of UpgradeReq misses
3302system.l2c.SCUpgradeReq_misses::cpu0.data 13497 # number of SCUpgradeReq misses
3303system.l2c.SCUpgradeReq_misses::cpu1.data 10880 # number of SCUpgradeReq misses
3304system.l2c.SCUpgradeReq_misses::total 24377 # number of SCUpgradeReq misses
3305system.l2c.ReadExReq_misses::cpu0.data 548373 # number of ReadExReq misses
3306system.l2c.ReadExReq_misses::cpu1.data 111880 # number of ReadExReq misses
3307system.l2c.ReadExReq_misses::total 660253 # number of ReadExReq misses
3308system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3162 # number of ReadSharedReq misses
3309system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3066 # number of ReadSharedReq misses
3310system.l2c.ReadSharedReq_misses::cpu0.inst 64369 # number of ReadSharedReq misses
3311system.l2c.ReadSharedReq_misses::cpu0.data 165419 # number of ReadSharedReq misses
3312system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 348485 # number of ReadSharedReq misses
3313system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1778 # number of ReadSharedReq misses
3314system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1336 # number of ReadSharedReq misses
3315system.l2c.ReadSharedReq_misses::cpu1.inst 44941 # number of ReadSharedReq misses
3316system.l2c.ReadSharedReq_misses::cpu1.data 109371 # number of ReadSharedReq misses
3317system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 194769 # number of ReadSharedReq misses
3318system.l2c.ReadSharedReq_misses::total 936696 # number of ReadSharedReq misses
3319system.l2c.demand_misses::cpu0.dtb.walker 3162 # number of demand (read+write) misses
3320system.l2c.demand_misses::cpu0.itb.walker 3066 # number of demand (read+write) misses
3321system.l2c.demand_misses::cpu0.inst 64369 # number of demand (read+write) misses
3322system.l2c.demand_misses::cpu0.data 713792 # number of demand (read+write) misses
3323system.l2c.demand_misses::cpu0.l2cache.prefetcher 348485 # number of demand (read+write) misses
3324system.l2c.demand_misses::cpu1.dtb.walker 1778 # number of demand (read+write) misses
3325system.l2c.demand_misses::cpu1.itb.walker 1336 # number of demand (read+write) misses
3326system.l2c.demand_misses::cpu1.inst 44941 # number of demand (read+write) misses
3327system.l2c.demand_misses::cpu1.data 221251 # number of demand (read+write) misses
3328system.l2c.demand_misses::cpu1.l2cache.prefetcher 194769 # number of demand (read+write) misses
3329system.l2c.demand_misses::total 1596949 # number of demand (read+write) misses
3330system.l2c.overall_misses::cpu0.dtb.walker 3162 # number of overall misses
3331system.l2c.overall_misses::cpu0.itb.walker 3066 # number of overall misses
3332system.l2c.overall_misses::cpu0.inst 64369 # number of overall misses
3333system.l2c.overall_misses::cpu0.data 713792 # number of overall misses
3334system.l2c.overall_misses::cpu0.l2cache.prefetcher 348485 # number of overall misses
3335system.l2c.overall_misses::cpu1.dtb.walker 1778 # number of overall misses
3336system.l2c.overall_misses::cpu1.itb.walker 1336 # number of overall misses
3337system.l2c.overall_misses::cpu1.inst 44941 # number of overall misses
3338system.l2c.overall_misses::cpu1.data 221251 # number of overall misses
3339system.l2c.overall_misses::cpu1.l2cache.prefetcher 194769 # number of overall misses
3340system.l2c.overall_misses::total 1596949 # number of overall misses
3341system.l2c.UpgradeReq_miss_latency::cpu0.data 1078165500 # number of UpgradeReq miss cycles
3342system.l2c.UpgradeReq_miss_latency::cpu1.data 1115927500 # number of UpgradeReq miss cycles
3343system.l2c.UpgradeReq_miss_latency::total 2194093000 # number of UpgradeReq miss cycles
3344system.l2c.SCUpgradeReq_miss_latency::cpu0.data 212502500 # number of SCUpgradeReq miss cycles
3345system.l2c.SCUpgradeReq_miss_latency::cpu1.data 171734000 # number of SCUpgradeReq miss cycles
3346system.l2c.SCUpgradeReq_miss_latency::total 384236500 # number of SCUpgradeReq miss cycles
3347system.l2c.ReadExReq_miss_latency::cpu0.data 90582434499 # number of ReadExReq miss cycles
3348system.l2c.ReadExReq_miss_latency::cpu1.data 16447344495 # number of ReadExReq miss cycles
3349system.l2c.ReadExReq_miss_latency::total 107029778994 # number of ReadExReq miss cycles
3350system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 446300000 # number of ReadSharedReq miss cycles
3351system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 433489000 # number of ReadSharedReq miss cycles
3352system.l2c.ReadSharedReq_miss_latency::cpu0.inst 8809361002 # number of ReadSharedReq miss cycles
3353system.l2c.ReadSharedReq_miss_latency::cpu0.data 23863415500 # number of ReadSharedReq miss cycles
3354system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 62552488059 # number of ReadSharedReq miss cycles
3355system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 257684000 # number of ReadSharedReq miss cycles
3356system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 192911000 # number of ReadSharedReq miss cycles
3357system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6154592500 # number of ReadSharedReq miss cycles
3358system.l2c.ReadSharedReq_miss_latency::cpu1.data 15830077997 # number of ReadSharedReq miss cycles
3359system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 35289320152 # number of ReadSharedReq miss cycles
3360system.l2c.ReadSharedReq_miss_latency::total 153829639210 # number of ReadSharedReq miss cycles
3361system.l2c.demand_miss_latency::cpu0.dtb.walker 446300000 # number of demand (read+write) miss cycles
3362system.l2c.demand_miss_latency::cpu0.itb.walker 433489000 # number of demand (read+write) miss cycles
3363system.l2c.demand_miss_latency::cpu0.inst 8809361002 # number of demand (read+write) miss cycles
3364system.l2c.demand_miss_latency::cpu0.data 114445849999 # number of demand (read+write) miss cycles
3365system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 62552488059 # number of demand (read+write) miss cycles
3366system.l2c.demand_miss_latency::cpu1.dtb.walker 257684000 # number of demand (read+write) miss cycles
3367system.l2c.demand_miss_latency::cpu1.itb.walker 192911000 # number of demand (read+write) miss cycles
3368system.l2c.demand_miss_latency::cpu1.inst 6154592500 # number of demand (read+write) miss cycles
3369system.l2c.demand_miss_latency::cpu1.data 32277422492 # number of demand (read+write) miss cycles
3370system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 35289320152 # number of demand (read+write) miss cycles
3371system.l2c.demand_miss_latency::total 260859418204 # number of demand (read+write) miss cycles
3372system.l2c.overall_miss_latency::cpu0.dtb.walker 446300000 # number of overall miss cycles
3373system.l2c.overall_miss_latency::cpu0.itb.walker 433489000 # number of overall miss cycles
3374system.l2c.overall_miss_latency::cpu0.inst 8809361002 # number of overall miss cycles
3375system.l2c.overall_miss_latency::cpu0.data 114445849999 # number of overall miss cycles
3376system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 62552488059 # number of overall miss cycles
3377system.l2c.overall_miss_latency::cpu1.dtb.walker 257684000 # number of overall miss cycles
3378system.l2c.overall_miss_latency::cpu1.itb.walker 192911000 # number of overall miss cycles
3379system.l2c.overall_miss_latency::cpu1.inst 6154592500 # number of overall miss cycles
3380system.l2c.overall_miss_latency::cpu1.data 32277422492 # number of overall miss cycles
3381system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 35289320152 # number of overall miss cycles
3382system.l2c.overall_miss_latency::total 260859418204 # number of overall miss cycles
3383system.l2c.WritebackDirty_accesses::writebacks 2899125 # number of WritebackDirty accesses(hits+misses)
3384system.l2c.WritebackDirty_accesses::total 2899125 # number of WritebackDirty accesses(hits+misses)
3385system.l2c.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses)
3386system.l2c.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses)
3387system.l2c.UpgradeReq_accesses::cpu0.data 244712 # number of UpgradeReq accesses(hits+misses)
3388system.l2c.UpgradeReq_accesses::cpu1.data 192650 # number of UpgradeReq accesses(hits+misses)
3389system.l2c.UpgradeReq_accesses::total 437362 # number of UpgradeReq accesses(hits+misses)
3390system.l2c.SCUpgradeReq_accesses::cpu0.data 58368 # number of SCUpgradeReq accesses(hits+misses)
3391system.l2c.SCUpgradeReq_accesses::cpu1.data 48467 # number of SCUpgradeReq accesses(hits+misses)
3392system.l2c.SCUpgradeReq_accesses::total 106835 # number of SCUpgradeReq accesses(hits+misses)
3393system.l2c.ReadExReq_accesses::cpu0.data 725820 # number of ReadExReq accesses(hits+misses)
3394system.l2c.ReadExReq_accesses::cpu1.data 270833 # number of ReadExReq accesses(hits+misses)
3395system.l2c.ReadExReq_accesses::total 996653 # number of ReadExReq accesses(hits+misses)
3396system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 10003 # number of ReadSharedReq accesses(hits+misses)
3397system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7825 # number of ReadSharedReq accesses(hits+misses)
3398system.l2c.ReadSharedReq_accesses::cpu0.inst 620047 # number of ReadSharedReq accesses(hits+misses)
3399system.l2c.ReadSharedReq_accesses::cpu0.data 822509 # number of ReadSharedReq accesses(hits+misses)
3400system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 663843 # number of ReadSharedReq accesses(hits+misses)
3401system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 7998 # number of ReadSharedReq accesses(hits+misses)
3402system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5791 # number of ReadSharedReq accesses(hits+misses)
3403system.l2c.ReadSharedReq_accesses::cpu1.inst 510739 # number of ReadSharedReq accesses(hits+misses)
3404system.l2c.ReadSharedReq_accesses::cpu1.data 660123 # number of ReadSharedReq accesses(hits+misses)
3405system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 483044 # number of ReadSharedReq accesses(hits+misses)
3406system.l2c.ReadSharedReq_accesses::total 3791922 # number of ReadSharedReq accesses(hits+misses)
3407system.l2c.demand_accesses::cpu0.dtb.walker 10003 # number of demand (read+write) accesses
3408system.l2c.demand_accesses::cpu0.itb.walker 7825 # number of demand (read+write) accesses
3409system.l2c.demand_accesses::cpu0.inst 620047 # number of demand (read+write) accesses
3410system.l2c.demand_accesses::cpu0.data 1548329 # number of demand (read+write) accesses
3411system.l2c.demand_accesses::cpu0.l2cache.prefetcher 663843 # number of demand (read+write) accesses
3412system.l2c.demand_accesses::cpu1.dtb.walker 7998 # number of demand (read+write) accesses
3413system.l2c.demand_accesses::cpu1.itb.walker 5791 # number of demand (read+write) accesses
3414system.l2c.demand_accesses::cpu1.inst 510739 # number of demand (read+write) accesses
3415system.l2c.demand_accesses::cpu1.data 930956 # number of demand (read+write) accesses
3416system.l2c.demand_accesses::cpu1.l2cache.prefetcher 483044 # number of demand (read+write) accesses
3417system.l2c.demand_accesses::total 4788575 # number of demand (read+write) accesses
3418system.l2c.overall_accesses::cpu0.dtb.walker 10003 # number of overall (read+write) accesses
3419system.l2c.overall_accesses::cpu0.itb.walker 7825 # number of overall (read+write) accesses
3420system.l2c.overall_accesses::cpu0.inst 620047 # number of overall (read+write) accesses
3421system.l2c.overall_accesses::cpu0.data 1548329 # number of overall (read+write) accesses
3422system.l2c.overall_accesses::cpu0.l2cache.prefetcher 663843 # number of overall (read+write) accesses
3423system.l2c.overall_accesses::cpu1.dtb.walker 7998 # number of overall (read+write) accesses
3424system.l2c.overall_accesses::cpu1.itb.walker 5791 # number of overall (read+write) accesses
3425system.l2c.overall_accesses::cpu1.inst 510739 # number of overall (read+write) accesses
3426system.l2c.overall_accesses::cpu1.data 930956 # number of overall (read+write) accesses
3427system.l2c.overall_accesses::cpu1.l2cache.prefetcher 483044 # number of overall (read+write) accesses
3428system.l2c.overall_accesses::total 4788575 # number of overall (read+write) accesses
3429system.l2c.UpgradeReq_miss_rate::cpu0.data 0.266313 # miss rate for UpgradeReq accesses
3430system.l2c.UpgradeReq_miss_rate::cpu1.data 0.316112 # miss rate for UpgradeReq accesses
3431system.l2c.UpgradeReq_miss_rate::total 0.288249 # miss rate for UpgradeReq accesses
3432system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.231240 # miss rate for SCUpgradeReq accesses
3433system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.224483 # miss rate for SCUpgradeReq accesses
3434system.l2c.SCUpgradeReq_miss_rate::total 0.228174 # miss rate for SCUpgradeReq accesses
3435system.l2c.ReadExReq_miss_rate::cpu0.data 0.755522 # miss rate for ReadExReq accesses
3436system.l2c.ReadExReq_miss_rate::cpu1.data 0.413096 # miss rate for ReadExReq accesses
3437system.l2c.ReadExReq_miss_rate::total 0.662470 # miss rate for ReadExReq accesses
3438system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.316105 # miss rate for ReadSharedReq accesses
3439system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.391821 # miss rate for ReadSharedReq accesses
3440system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.103813 # miss rate for ReadSharedReq accesses
3441system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.201115 # miss rate for ReadSharedReq accesses
3442system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.524951 # miss rate for ReadSharedReq accesses
3443system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.222306 # miss rate for ReadSharedReq accesses
3444system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.230703 # miss rate for ReadSharedReq accesses
3445system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.087992 # miss rate for ReadSharedReq accesses
3446system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.165683 # miss rate for ReadSharedReq accesses
3447system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.403212 # miss rate for ReadSharedReq accesses
3448system.l2c.ReadSharedReq_miss_rate::total 0.247024 # miss rate for ReadSharedReq accesses
3449system.l2c.demand_miss_rate::cpu0.dtb.walker 0.316105 # miss rate for demand accesses
3450system.l2c.demand_miss_rate::cpu0.itb.walker 0.391821 # miss rate for demand accesses
3451system.l2c.demand_miss_rate::cpu0.inst 0.103813 # miss rate for demand accesses
3452system.l2c.demand_miss_rate::cpu0.data 0.461008 # miss rate for demand accesses
3453system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.524951 # miss rate for demand accesses
3454system.l2c.demand_miss_rate::cpu1.dtb.walker 0.222306 # miss rate for demand accesses
3455system.l2c.demand_miss_rate::cpu1.itb.walker 0.230703 # miss rate for demand accesses
3456system.l2c.demand_miss_rate::cpu1.inst 0.087992 # miss rate for demand accesses
3457system.l2c.demand_miss_rate::cpu1.data 0.237660 # miss rate for demand accesses
3458system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.403212 # miss rate for demand accesses
3459system.l2c.demand_miss_rate::total 0.333491 # miss rate for demand accesses
3460system.l2c.overall_miss_rate::cpu0.dtb.walker 0.316105 # miss rate for overall accesses
3461system.l2c.overall_miss_rate::cpu0.itb.walker 0.391821 # miss rate for overall accesses
3462system.l2c.overall_miss_rate::cpu0.inst 0.103813 # miss rate for overall accesses
3463system.l2c.overall_miss_rate::cpu0.data 0.461008 # miss rate for overall accesses
3464system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.524951 # miss rate for overall accesses
3465system.l2c.overall_miss_rate::cpu1.dtb.walker 0.222306 # miss rate for overall accesses
3466system.l2c.overall_miss_rate::cpu1.itb.walker 0.230703 # miss rate for overall accesses
3467system.l2c.overall_miss_rate::cpu1.inst 0.087992 # miss rate for overall accesses
3468system.l2c.overall_miss_rate::cpu1.data 0.237660 # miss rate for overall accesses
3469system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.403212 # miss rate for overall accesses
3470system.l2c.overall_miss_rate::total 0.333491 # miss rate for overall accesses
3471system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16543.892896 # average UpgradeReq miss latency
3472system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 18324.233567 # average UpgradeReq miss latency
3473system.l2c.UpgradeReq_avg_miss_latency::total 17403.905798 # average UpgradeReq miss latency
3474system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15744.424687 # average SCUpgradeReq miss latency
3475system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15784.375000 # average SCUpgradeReq miss latency
3476system.l2c.SCUpgradeReq_avg_miss_latency::total 15762.255405 # average SCUpgradeReq miss latency
3477system.l2c.ReadExReq_avg_miss_latency::cpu0.data 165183.979698 # average ReadExReq miss latency
3478system.l2c.ReadExReq_avg_miss_latency::cpu1.data 147008.799562 # average ReadExReq miss latency
3479system.l2c.ReadExReq_avg_miss_latency::total 162104.191869 # average ReadExReq miss latency
3480system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 141144.845035 # average ReadSharedReq miss latency
3481system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141385.844749 # average ReadSharedReq miss latency
3482system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 136857.198372 # average ReadSharedReq miss latency
3483system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 144260.426553 # average ReadSharedReq miss latency
3484system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 179498.365953 # average ReadSharedReq miss latency
3485system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 144929.133858 # average ReadSharedReq miss latency
3486system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 144394.461078 # average ReadSharedReq miss latency
3487system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 136948.276629 # average ReadSharedReq miss latency
3488system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 144737.434942 # average ReadSharedReq miss latency
3489system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 181185.507714 # average ReadSharedReq miss latency
3490system.l2c.ReadSharedReq_avg_miss_latency::total 164225.788527 # average ReadSharedReq miss latency
3491system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 141144.845035 # average overall miss latency
3492system.l2c.demand_avg_miss_latency::cpu0.itb.walker 141385.844749 # average overall miss latency
3493system.l2c.demand_avg_miss_latency::cpu0.inst 136857.198372 # average overall miss latency
3494system.l2c.demand_avg_miss_latency::cpu0.data 160335.013560 # average overall miss latency
3495system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 179498.365953 # average overall miss latency
3496system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 144929.133858 # average overall miss latency
3497system.l2c.demand_avg_miss_latency::cpu1.itb.walker 144394.461078 # average overall miss latency
3498system.l2c.demand_avg_miss_latency::cpu1.inst 136948.276629 # average overall miss latency
3499system.l2c.demand_avg_miss_latency::cpu1.data 145885.995959 # average overall miss latency
3500system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 181185.507714 # average overall miss latency
3501system.l2c.demand_avg_miss_latency::total 163348.621781 # average overall miss latency
3502system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 141144.845035 # average overall miss latency
3503system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141385.844749 # average overall miss latency
3504system.l2c.overall_avg_miss_latency::cpu0.inst 136857.198372 # average overall miss latency
3505system.l2c.overall_avg_miss_latency::cpu0.data 160335.013560 # average overall miss latency
3506system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 179498.365953 # average overall miss latency
3507system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 144929.133858 # average overall miss latency
3508system.l2c.overall_avg_miss_latency::cpu1.itb.walker 144394.461078 # average overall miss latency
3509system.l2c.overall_avg_miss_latency::cpu1.inst 136948.276629 # average overall miss latency
3510system.l2c.overall_avg_miss_latency::cpu1.data 145885.995959 # average overall miss latency
3511system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 181185.507714 # average overall miss latency
3512system.l2c.overall_avg_miss_latency::total 163348.621781 # average overall miss latency
3513system.l2c.blocked_cycles::no_mshrs 8828 # number of cycles access was blocked
3514system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
3515system.l2c.blocked::no_mshrs 81 # number of cycles access was blocked
3516system.l2c.blocked::no_targets 0 # number of cycles access was blocked
3517system.l2c.avg_blocked_cycles::no_mshrs 108.987654 # average number of cycles each access was blocked
3518system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3519system.l2c.fast_writes 0 # number of fast writes performed
3520system.l2c.cache_copies 0 # number of cache copies performed
3521system.l2c.writebacks::writebacks 1227229 # number of writebacks
3522system.l2c.writebacks::total 1227229 # number of writebacks
3523system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 139 # number of ReadSharedReq MSHR hits
3524system.l2c.ReadSharedReq_mshr_hits::cpu0.data 160 # number of ReadSharedReq MSHR hits
3525system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 80 # number of ReadSharedReq MSHR hits
3526system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 236 # number of ReadSharedReq MSHR hits
3527system.l2c.ReadSharedReq_mshr_hits::cpu1.data 179 # number of ReadSharedReq MSHR hits
3528system.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 178 # number of ReadSharedReq MSHR hits
3529system.l2c.ReadSharedReq_mshr_hits::total 972 # number of ReadSharedReq MSHR hits
3530system.l2c.demand_mshr_hits::cpu0.inst 139 # number of demand (read+write) MSHR hits
3531system.l2c.demand_mshr_hits::cpu0.data 160 # number of demand (read+write) MSHR hits
3532system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 80 # number of demand (read+write) MSHR hits
3533system.l2c.demand_mshr_hits::cpu1.inst 236 # number of demand (read+write) MSHR hits
3534system.l2c.demand_mshr_hits::cpu1.data 179 # number of demand (read+write) MSHR hits
3535system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 178 # number of demand (read+write) MSHR hits
3536system.l2c.demand_mshr_hits::total 972 # number of demand (read+write) MSHR hits
3537system.l2c.overall_mshr_hits::cpu0.inst 139 # number of overall MSHR hits
3538system.l2c.overall_mshr_hits::cpu0.data 160 # number of overall MSHR hits
3539system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 80 # number of overall MSHR hits
3540system.l2c.overall_mshr_hits::cpu1.inst 236 # number of overall MSHR hits
3541system.l2c.overall_mshr_hits::cpu1.data 179 # number of overall MSHR hits
3542system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 178 # number of overall MSHR hits
3543system.l2c.overall_mshr_hits::total 972 # number of overall MSHR hits
3544system.l2c.CleanEvict_mshr_misses::writebacks 61997 # number of CleanEvict MSHR misses
3545system.l2c.CleanEvict_mshr_misses::total 61997 # number of CleanEvict MSHR misses
3546system.l2c.UpgradeReq_mshr_misses::cpu0.data 65170 # number of UpgradeReq MSHR misses
3547system.l2c.UpgradeReq_mshr_misses::cpu1.data 60899 # number of UpgradeReq MSHR misses
3548system.l2c.UpgradeReq_mshr_misses::total 126069 # number of UpgradeReq MSHR misses
3549system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 13497 # number of SCUpgradeReq MSHR misses
3550system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 10880 # number of SCUpgradeReq MSHR misses
3551system.l2c.SCUpgradeReq_mshr_misses::total 24377 # number of SCUpgradeReq MSHR misses
3552system.l2c.ReadExReq_mshr_misses::cpu0.data 548373 # number of ReadExReq MSHR misses
3553system.l2c.ReadExReq_mshr_misses::cpu1.data 111880 # number of ReadExReq MSHR misses
3554system.l2c.ReadExReq_mshr_misses::total 660253 # number of ReadExReq MSHR misses
3555system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 3162 # number of ReadSharedReq MSHR misses
3556system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3066 # number of ReadSharedReq MSHR misses
3557system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 64230 # number of ReadSharedReq MSHR misses
3558system.l2c.ReadSharedReq_mshr_misses::cpu0.data 165259 # number of ReadSharedReq MSHR misses
3559system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 348405 # number of ReadSharedReq MSHR misses
3560system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1778 # number of ReadSharedReq MSHR misses
3561system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1336 # number of ReadSharedReq MSHR misses
3562system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 44705 # number of ReadSharedReq MSHR misses
3563system.l2c.ReadSharedReq_mshr_misses::cpu1.data 109192 # number of ReadSharedReq MSHR misses
3564system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 194591 # number of ReadSharedReq MSHR misses
3565system.l2c.ReadSharedReq_mshr_misses::total 935724 # number of ReadSharedReq MSHR misses
3566system.l2c.demand_mshr_misses::cpu0.dtb.walker 3162 # number of demand (read+write) MSHR misses
3567system.l2c.demand_mshr_misses::cpu0.itb.walker 3066 # number of demand (read+write) MSHR misses
3568system.l2c.demand_mshr_misses::cpu0.inst 64230 # number of demand (read+write) MSHR misses
3569system.l2c.demand_mshr_misses::cpu0.data 713632 # number of demand (read+write) MSHR misses
3570system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 348405 # number of demand (read+write) MSHR misses
3571system.l2c.demand_mshr_misses::cpu1.dtb.walker 1778 # number of demand (read+write) MSHR misses
3572system.l2c.demand_mshr_misses::cpu1.itb.walker 1336 # number of demand (read+write) MSHR misses
3573system.l2c.demand_mshr_misses::cpu1.inst 44705 # number of demand (read+write) MSHR misses
3574system.l2c.demand_mshr_misses::cpu1.data 221072 # number of demand (read+write) MSHR misses
3575system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 194591 # number of demand (read+write) MSHR misses
3576system.l2c.demand_mshr_misses::total 1595977 # number of demand (read+write) MSHR misses
3577system.l2c.overall_mshr_misses::cpu0.dtb.walker 3162 # number of overall MSHR misses
3578system.l2c.overall_mshr_misses::cpu0.itb.walker 3066 # number of overall MSHR misses
3579system.l2c.overall_mshr_misses::cpu0.inst 64230 # number of overall MSHR misses
3580system.l2c.overall_mshr_misses::cpu0.data 713632 # number of overall MSHR misses
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3582system.l2c.overall_mshr_misses::cpu1.dtb.walker 1778 # number of overall MSHR misses
3583system.l2c.overall_mshr_misses::cpu1.itb.walker 1336 # number of overall MSHR misses
3584system.l2c.overall_mshr_misses::cpu1.inst 44705 # number of overall MSHR misses
3585system.l2c.overall_mshr_misses::cpu1.data 221072 # number of overall MSHR misses
3586system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 194591 # number of overall MSHR misses
3587system.l2c.overall_mshr_misses::total 1595977 # number of overall MSHR misses
3588system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
3589system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32878 # number of ReadReq MSHR uncacheable
3590system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
3591system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5427 # number of ReadReq MSHR uncacheable
3592system.l2c.ReadReq_mshr_uncacheable::total 59665 # number of ReadReq MSHR uncacheable
3593system.l2c.WriteReq_mshr_uncacheable::cpu0.data 32941 # number of WriteReq MSHR uncacheable
3594system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5284 # number of WriteReq MSHR uncacheable
3595system.l2c.WriteReq_mshr_uncacheable::total 38225 # number of WriteReq MSHR uncacheable
3596system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
3597system.l2c.overall_mshr_uncacheable_misses::cpu0.data 65819 # number of overall MSHR uncacheable misses
3598system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
3599system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10711 # number of overall MSHR uncacheable misses
3600system.l2c.overall_mshr_uncacheable_misses::total 97890 # number of overall MSHR uncacheable misses
3601system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4609555998 # number of UpgradeReq MSHR miss cycles
3602system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4294868996 # number of UpgradeReq MSHR miss cycles
3603system.l2c.UpgradeReq_mshr_miss_latency::total 8904424994 # number of UpgradeReq MSHR miss cycles
3604system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 994851497 # number of SCUpgradeReq MSHR miss cycles
3605system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 800175997 # number of SCUpgradeReq MSHR miss cycles
3606system.l2c.SCUpgradeReq_mshr_miss_latency::total 1795027494 # number of SCUpgradeReq MSHR miss cycles
3607system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 85098254939 # number of ReadExReq MSHR miss cycles
3608system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 15328209809 # number of ReadExReq MSHR miss cycles
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3610system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 414677007 # number of ReadSharedReq MSHR miss cycles
3611system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 402825012 # number of ReadSharedReq MSHR miss cycles
3612system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 8150526337 # number of ReadSharedReq MSHR miss cycles
3613system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 22190089460 # number of ReadSharedReq MSHR miss cycles
3614system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 59056286181 # number of ReadSharedReq MSHR miss cycles
3615system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 239897519 # number of ReadSharedReq MSHR miss cycles
3616system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 179549008 # number of ReadSharedReq MSHR miss cycles
3617system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5679666806 # number of ReadSharedReq MSHR miss cycles
3618system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 14716146780 # number of ReadSharedReq MSHR miss cycles
3619system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 33314353434 # number of ReadSharedReq MSHR miss cycles
3620system.l2c.ReadSharedReq_mshr_miss_latency::total 144344017544 # number of ReadSharedReq MSHR miss cycles
3621system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 414677007 # number of demand (read+write) MSHR miss cycles
3622system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 402825012 # number of demand (read+write) MSHR miss cycles
3623system.l2c.demand_mshr_miss_latency::cpu0.inst 8150526337 # number of demand (read+write) MSHR miss cycles
3624system.l2c.demand_mshr_miss_latency::cpu0.data 107288344399 # number of demand (read+write) MSHR miss cycles
3625system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 59056286181 # number of demand (read+write) MSHR miss cycles
3626system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 239897519 # number of demand (read+write) MSHR miss cycles
3627system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 179549008 # number of demand (read+write) MSHR miss cycles
3628system.l2c.demand_mshr_miss_latency::cpu1.inst 5679666806 # number of demand (read+write) MSHR miss cycles
3629system.l2c.demand_mshr_miss_latency::cpu1.data 30044356589 # number of demand (read+write) MSHR miss cycles
3630system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 33314353434 # number of demand (read+write) MSHR miss cycles
3631system.l2c.demand_mshr_miss_latency::total 244770482292 # number of demand (read+write) MSHR miss cycles
3632system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 414677007 # number of overall MSHR miss cycles
3633system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 402825012 # number of overall MSHR miss cycles
3634system.l2c.overall_mshr_miss_latency::cpu0.inst 8150526337 # number of overall MSHR miss cycles
3635system.l2c.overall_mshr_miss_latency::cpu0.data 107288344399 # number of overall MSHR miss cycles
3636system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 59056286181 # number of overall MSHR miss cycles
3637system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 239897519 # number of overall MSHR miss cycles
3638system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 179549008 # number of overall MSHR miss cycles
3639system.l2c.overall_mshr_miss_latency::cpu1.inst 5679666806 # number of overall MSHR miss cycles
3640system.l2c.overall_mshr_miss_latency::cpu1.data 30044356589 # number of overall MSHR miss cycles
3641system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 33314353434 # number of overall MSHR miss cycles
3642system.l2c.overall_mshr_miss_latency::total 244770482292 # number of overall MSHR miss cycles
3643system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2396808000 # number of ReadReq MSHR uncacheable cycles
3644system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5437993027 # number of ReadReq MSHR uncacheable cycles
3645system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7557000 # number of ReadReq MSHR uncacheable cycles
3646system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 463514024 # number of ReadReq MSHR uncacheable cycles
3647system.l2c.ReadReq_mshr_uncacheable_latency::total 8305872051 # number of ReadReq MSHR uncacheable cycles
3648system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 5417020065 # number of WriteReq MSHR uncacheable cycles
3649system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 540285518 # number of WriteReq MSHR uncacheable cycles
3650system.l2c.WriteReq_mshr_uncacheable_latency::total 5957305583 # number of WriteReq MSHR uncacheable cycles
3651system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2396808000 # number of overall MSHR uncacheable cycles
3652system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10855013092 # number of overall MSHR uncacheable cycles
3653system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7557000 # number of overall MSHR uncacheable cycles
3654system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1003799542 # number of overall MSHR uncacheable cycles
3655system.l2c.overall_mshr_uncacheable_latency::total 14263177634 # number of overall MSHR uncacheable cycles
3656system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3657system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3658system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.266313 # mshr miss rate for UpgradeReq accesses
3659system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.316112 # mshr miss rate for UpgradeReq accesses
3660system.l2c.UpgradeReq_mshr_miss_rate::total 0.288249 # mshr miss rate for UpgradeReq accesses
3661system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.231240 # mshr miss rate for SCUpgradeReq accesses
3662system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.224483 # mshr miss rate for SCUpgradeReq accesses
3663system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.228174 # mshr miss rate for SCUpgradeReq accesses
3664system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.755522 # mshr miss rate for ReadExReq accesses
3665system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.413096 # mshr miss rate for ReadExReq accesses
3666system.l2c.ReadExReq_mshr_miss_rate::total 0.662470 # mshr miss rate for ReadExReq accesses
3667system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.316105 # mshr miss rate for ReadSharedReq accesses
3668system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.391821 # mshr miss rate for ReadSharedReq accesses
3669system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.103589 # mshr miss rate for ReadSharedReq accesses
3670system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.200921 # mshr miss rate for ReadSharedReq accesses
3671system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.524830 # mshr miss rate for ReadSharedReq accesses
3672system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.222306 # mshr miss rate for ReadSharedReq accesses
3673system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.230703 # mshr miss rate for ReadSharedReq accesses
3674system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.087530 # mshr miss rate for ReadSharedReq accesses
3675system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.165412 # mshr miss rate for ReadSharedReq accesses
3676system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402843 # mshr miss rate for ReadSharedReq accesses
3677system.l2c.ReadSharedReq_mshr_miss_rate::total 0.246768 # mshr miss rate for ReadSharedReq accesses
3678system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.316105 # mshr miss rate for demand accesses
3679system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.391821 # mshr miss rate for demand accesses
3680system.l2c.demand_mshr_miss_rate::cpu0.inst 0.103589 # mshr miss rate for demand accesses
3681system.l2c.demand_mshr_miss_rate::cpu0.data 0.460905 # mshr miss rate for demand accesses
3682system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.524830 # mshr miss rate for demand accesses
3683system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.222306 # mshr miss rate for demand accesses
3684system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.230703 # mshr miss rate for demand accesses
3685system.l2c.demand_mshr_miss_rate::cpu1.inst 0.087530 # mshr miss rate for demand accesses
3686system.l2c.demand_mshr_miss_rate::cpu1.data 0.237468 # mshr miss rate for demand accesses
3687system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402843 # mshr miss rate for demand accesses
3688system.l2c.demand_mshr_miss_rate::total 0.333289 # mshr miss rate for demand accesses
3689system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.316105 # mshr miss rate for overall accesses
3690system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.391821 # mshr miss rate for overall accesses
3691system.l2c.overall_mshr_miss_rate::cpu0.inst 0.103589 # mshr miss rate for overall accesses
3692system.l2c.overall_mshr_miss_rate::cpu0.data 0.460905 # mshr miss rate for overall accesses
3693system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.524830 # mshr miss rate for overall accesses
3694system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.222306 # mshr miss rate for overall accesses
3695system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.230703 # mshr miss rate for overall accesses
3696system.l2c.overall_mshr_miss_rate::cpu1.inst 0.087530 # mshr miss rate for overall accesses
3697system.l2c.overall_mshr_miss_rate::cpu1.data 0.237468 # mshr miss rate for overall accesses
3698system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.402843 # mshr miss rate for overall accesses
3699system.l2c.overall_mshr_miss_rate::total 0.333289 # mshr miss rate for overall accesses
3700system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70731.256683 # average UpgradeReq mshr miss latency
3701system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70524.458464 # average UpgradeReq mshr miss latency
3702system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70631.360557 # average UpgradeReq mshr miss latency
3703system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73709.083278 # average SCUpgradeReq mshr miss latency
3704system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73545.587960 # average SCUpgradeReq mshr miss latency
3705system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73636.111663 # average SCUpgradeReq mshr miss latency
3706system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 155183.159891 # average ReadExReq mshr miss latency
3707system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 137005.808089 # average ReadExReq mshr miss latency
3708system.l2c.ReadExReq_avg_mshr_miss_latency::total 152103.004073 # average ReadExReq mshr miss latency
3709system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 131143.898482 # average ReadSharedReq mshr miss latency
3710system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131384.544031 # average ReadSharedReq mshr miss latency
3711system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 126895.941725 # average ReadSharedReq mshr miss latency
3712system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 134274.620202 # average ReadSharedReq mshr miss latency
3713system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169504.703380 # average ReadSharedReq mshr miss latency
3714system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 134925.488751 # average ReadSharedReq mshr miss latency
3715system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 134392.970060 # average ReadSharedReq mshr miss latency
3716system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127047.686075 # average ReadSharedReq mshr miss latency
3717system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 134773.122390 # average ReadSharedReq mshr miss latency
3718system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171201.923182 # average ReadSharedReq mshr miss latency
3719system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 154259.180639 # average ReadSharedReq mshr miss latency
3720system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 131143.898482 # average overall mshr miss latency
3721system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131384.544031 # average overall mshr miss latency
3722system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 126895.941725 # average overall mshr miss latency
3723system.l2c.demand_avg_mshr_miss_latency::cpu0.data 150341.274493 # average overall mshr miss latency
3724system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169504.703380 # average overall mshr miss latency
3725system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 134925.488751 # average overall mshr miss latency
3726system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 134392.970060 # average overall mshr miss latency
3727system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127047.686075 # average overall mshr miss latency
3728system.l2c.demand_avg_mshr_miss_latency::cpu1.data 135903.038779 # average overall mshr miss latency
3729system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171201.923182 # average overall mshr miss latency
3730system.l2c.demand_avg_mshr_miss_latency::total 153367.174021 # average overall mshr miss latency
3731system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131143.898482 # average overall mshr miss latency
3732system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131384.544031 # average overall mshr miss latency
3733system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 126895.941725 # average overall mshr miss latency
3734system.l2c.overall_avg_mshr_miss_latency::cpu0.data 150341.274493 # average overall mshr miss latency
3735system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169504.703380 # average overall mshr miss latency
3736system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 134925.488751 # average overall mshr miss latency
3737system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 134392.970060 # average overall mshr miss latency
3738system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127047.686075 # average overall mshr miss latency
3739system.l2c.overall_avg_mshr_miss_latency::cpu1.data 135903.038779 # average overall mshr miss latency
3740system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171201.923182 # average overall mshr miss latency
3741system.l2c.overall_avg_mshr_miss_latency::total 153367.174021 # average overall mshr miss latency
3742system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average ReadReq mshr uncacheable latency
3743system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165399.143105 # average ReadReq mshr uncacheable latency
3744system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112791.044776 # average ReadReq mshr uncacheable latency
3745system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 85408.885941 # average ReadReq mshr uncacheable latency
3746system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 139208.448018 # average ReadReq mshr uncacheable latency
3747system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164446.132935 # average WriteReq mshr uncacheable latency
3748system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 102249.341030 # average WriteReq mshr uncacheable latency
3749system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155848.412897 # average WriteReq mshr uncacheable latency
3750system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average overall mshr uncacheable latency
3751system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164922.181923 # average overall mshr uncacheable latency
3752system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112791.044776 # average overall mshr uncacheable latency
3753system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 93716.697040 # average overall mshr uncacheable latency
3754system.l2c.overall_avg_mshr_uncacheable_latency::total 145706.176668 # average overall mshr uncacheable latency
3755system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
3756system.membus.trans_dist::ReadReq 59665 # Transaction distribution
3757system.membus.trans_dist::ReadResp 1004280 # Transaction distribution
3758system.membus.trans_dist::WriteReq 38225 # Transaction distribution
3759system.membus.trans_dist::WriteResp 38225 # Transaction distribution
3760system.membus.trans_dist::WritebackDirty 1333923 # Transaction distribution
3761system.membus.trans_dist::CleanEvict 260984 # Transaction distribution
3762system.membus.trans_dist::UpgradeReq 453995 # Transaction distribution
3763system.membus.trans_dist::SCUpgradeReq 297100 # Transaction distribution
3764system.membus.trans_dist::UpgradeResp 23 # Transaction distribution
3765system.membus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution
3766system.membus.trans_dist::ReadExReq 671706 # Transaction distribution
3767system.membus.trans_dist::ReadExResp 651282 # Transaction distribution
3768system.membus.trans_dist::ReadSharedReq 944615 # Transaction distribution
3769system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution
3770system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes)
3771system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes)
3772system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25256 # Packet count per connected master and slave (bytes)
3773system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5471994 # Packet count per connected master and slave (bytes)
3774system.membus.pkt_count_system.l2c.mem_side::total 5619910 # Packet count per connected master and slave (bytes)
3775system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238072 # Packet count per connected master and slave (bytes)
3776system.membus.pkt_count_system.iocache.mem_side::total 238072 # Packet count per connected master and slave (bytes)
3777system.membus.pkt_count::total 5857982 # Packet count per connected master and slave (bytes)
3778system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155691 # Cumulative packet size per connected master and slave (bytes)
3779system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes)
3780system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50512 # Cumulative packet size per connected master and slave (bytes)
3781system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 180426240 # Cumulative packet size per connected master and slave (bytes)
3782system.membus.pkt_size_system.l2c.mem_side::total 180632999 # Cumulative packet size per connected master and slave (bytes)
3783system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7268224 # Cumulative packet size per connected master and slave (bytes)
3784system.membus.pkt_size_system.iocache.mem_side::total 7268224 # Cumulative packet size per connected master and slave (bytes)
3785system.membus.pkt_size::total 187901223 # Cumulative packet size per connected master and slave (bytes)
3786system.membus.snoops 614880 # Total snoops (count)
3787system.membus.snoop_fanout::samples 4166995 # Request fanout histogram
3788system.membus.snoop_fanout::mean 1 # Request fanout histogram
3789system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3790system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3791system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3792system.membus.snoop_fanout::1 4166995 100.00% 100.00% # Request fanout histogram
3793system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3794system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3795system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3796system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3797system.membus.snoop_fanout::total 4166995 # Request fanout histogram
3798system.membus.reqLayer0.occupancy 98592998 # Layer occupancy (ticks)
3799system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3800system.membus.reqLayer1.occupancy 53000 # Layer occupancy (ticks)
3801system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3802system.membus.reqLayer2.occupancy 21315973 # Layer occupancy (ticks)
3803system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3804system.membus.reqLayer5.occupancy 9342770498 # Layer occupancy (ticks)
3805system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3806system.membus.respLayer2.occupancy 8446463151 # Layer occupancy (ticks)
3807system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3808system.membus.respLayer3.occupancy 45344986 # Layer occupancy (ticks)
3809system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3810system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3811system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3812system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3813system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3814system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3815system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3816system.realview.ethernet.txBytes 966 # Bytes Transmitted

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3854system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3855system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3856system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3857system.realview.ethernet.droppedPackets 0 # number of packets dropped
3858system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3859system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3860system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3861system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3862system.toL2Bus.snoop_filter.tot_requests 12162467 # Total number of requests made to the snoop filter.
3863system.toL2Bus.snoop_filter.hit_single_requests 6606326 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3864system.toL2Bus.snoop_filter.hit_multi_requests 1941011 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3865system.toL2Bus.snoop_filter.tot_snoops 162574 # Total number of snoops made to the snoop filter.
3866system.toL2Bus.snoop_filter.hit_single_snoops 148386 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3867system.toL2Bus.snoop_filter.hit_multi_snoops 14188 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3868system.toL2Bus.trans_dist::ReadReq 59667 # Transaction distribution
3869system.toL2Bus.trans_dist::ReadResp 4643440 # Transaction distribution
3870system.toL2Bus.trans_dist::WriteReq 38225 # Transaction distribution
3871system.toL2Bus.trans_dist::WriteResp 38225 # Transaction distribution
3872system.toL2Bus.trans_dist::WritebackDirty 4233094 # Transaction distribution
3873system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
3874system.toL2Bus.trans_dist::CleanEvict 2736996 # Transaction distribution
3875system.toL2Bus.trans_dist::UpgradeReq 756317 # Transaction distribution
3876system.toL2Bus.trans_dist::SCUpgradeReq 379558 # Transaction distribution
3877system.toL2Bus.trans_dist::UpgradeResp 1135875 # Transaction distribution
3878system.toL2Bus.trans_dist::SCUpgradeFailReq 201 # Transaction distribution
3879system.toL2Bus.trans_dist::UpgradeFailResp 201 # Transaction distribution
3880system.toL2Bus.trans_dist::ReadExReq 1140134 # Transaction distribution
3881system.toL2Bus.trans_dist::ReadExResp 1140134 # Transaction distribution
3882system.toL2Bus.trans_dist::ReadSharedReq 4591007 # Transaction distribution
3883system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution
3884system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10341744 # Packet count per connected master and slave (bytes)
3885system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7350795 # Packet count per connected master and slave (bytes)
3886system.toL2Bus.pkt_count::total 17692539 # Packet count per connected master and slave (bytes)
3887system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 299067465 # Cumulative packet size per connected master and slave (bytes)
3888system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 193620382 # Cumulative packet size per connected master and slave (bytes)
3889system.toL2Bus.pkt_size::total 492687847 # Cumulative packet size per connected master and slave (bytes)
3890system.toL2Bus.snoops 3308925 # Total snoops (count)
3891system.toL2Bus.snoop_fanout::samples 8737988 # Request fanout histogram
3892system.toL2Bus.snoop_fanout::mean 0.345814 # Request fanout histogram
3893system.toL2Bus.snoop_fanout::stdev 0.479035 # Request fanout histogram
3894system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3895system.toL2Bus.snoop_fanout::0 5730454 65.58% 65.58% # Request fanout histogram
3896system.toL2Bus.snoop_fanout::1 2993346 34.26% 99.84% # Request fanout histogram
3897system.toL2Bus.snoop_fanout::2 14188 0.16% 100.00% # Request fanout histogram
3898system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3899system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3900system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3901system.toL2Bus.snoop_fanout::total 8737988 # Request fanout histogram
3902system.toL2Bus.reqLayer0.occupancy 9497901955 # Layer occupancy (ticks)
3903system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3904system.toL2Bus.snoopLayer0.occupancy 2589298 # Layer occupancy (ticks)
3905system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3906system.toL2Bus.respLayer0.occupancy 5324917465 # Layer occupancy (ticks)
3907system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3908system.toL2Bus.respLayer1.occupancy 3923923162 # Layer occupancy (ticks)
3909system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3910system.cpu0.kern.inst.arm 0 # number of arm instructions executed
3911system.cpu0.kern.inst.quiesce 12950 # number of quiesce instructions executed
3912system.cpu1.kern.inst.arm 0 # number of arm instructions executed
3913system.cpu1.kern.inst.quiesce 5465 # number of quiesce instructions executed
3914
3915---------- End Simulation Statistics ----------