1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.314506 # Number of seconds simulated
4sim_ticks 47314506373000 # Number of ticks simulated
5final_tick 47314506373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 98624 # Simulator instruction rate (inst/s)
8host_op_rate 115961 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 5063135105 # Simulator tick rate (ticks/s)
10host_mem_usage 768296 # Number of bytes of host memory used
11host_seconds 9344.90 # Real time elapsed on the host
12sim_insts 921635123 # Number of instructions simulated
13sim_ops 1083644532 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 141824 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 130048 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 4236960 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 43669256 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 19384064 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 193856 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 178880 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 3171232 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 16700240 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 15629760 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 443968 # Number of bytes read from this memory
27system.physmem.bytes_read::total 103880088 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 4236960 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 3171232 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 7408192 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 86326016 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
34system.physmem.bytes_written::total 86346600 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 2216 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 2032 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 82155 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 682345 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 302876 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 3029 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.itb.walker 2795 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.inst 49594 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.data 260954 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.l2cache.prefetcher 244215 # Number of read requests responded to by this memory
45system.physmem.num_reads::realview.ide 6937 # Number of read requests responded to by this memory
46system.physmem.num_reads::total 1639148 # Number of read requests responded to by this memory
47system.physmem.num_writes::writebacks 1348844 # Number of write requests responded to by this memory
48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
50system.physmem.num_writes::total 1351418 # Number of write requests responded to by this memory
51system.physmem.bw_read::cpu0.dtb.walker 2997 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.itb.walker 2749 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.inst 89549 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.data 922957 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.l2cache.prefetcher 409685 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.dtb.walker 4097 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.itb.walker 3781 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.inst 67025 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.data 352962 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.l2cache.prefetcher 330338 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::realview.ide 9383 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::total 2195523 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::cpu0.inst 89549 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu1.inst 67025 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::total 156573 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_write::writebacks 1824515 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::total 1824950 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_total::writebacks 1824515 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.dtb.walker 2997 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.itb.walker 2749 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.inst 89549 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.data 923392 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.l2cache.prefetcher 409685 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.dtb.walker 4097 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.itb.walker 3781 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.inst 67025 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.data 352962 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.l2cache.prefetcher 330338 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.ide 9383 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::total 4020473 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.readReqs 1639148 # Number of read requests accepted
84system.physmem.writeReqs 1351418 # Number of write requests accepted
85system.physmem.readBursts 1639148 # Number of DRAM read bursts, including those serviced by the write queue
86system.physmem.writeBursts 1351418 # Number of DRAM write bursts, including those merged in the write queue
87system.physmem.bytesReadDRAM 104871744 # Total number of bytes read from DRAM
88system.physmem.bytesReadWrQ 33728 # Total number of bytes read from write queue
89system.physmem.bytesWritten 86344960 # Total number of bytes written to DRAM
90system.physmem.bytesReadSys 103880088 # Total read bytes from the system interface side
91system.physmem.bytesWrittenSys 86346600 # Total written bytes from the system interface side
92system.physmem.servicedByWrQ 527 # Number of DRAM read bursts serviced by the write queue
93system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
94system.physmem.neitherReadNorWriteReqs 532498 # Number of requests that are neither read nor write
95system.physmem.perBankRdBursts::0 106578 # Per bank write bursts
96system.physmem.perBankRdBursts::1 104344 # Per bank write bursts
97system.physmem.perBankRdBursts::2 100892 # Per bank write bursts
98system.physmem.perBankRdBursts::3 102125 # Per bank write bursts
99system.physmem.perBankRdBursts::4 100013 # Per bank write bursts
100system.physmem.perBankRdBursts::5 109287 # Per bank write bursts
101system.physmem.perBankRdBursts::6 101103 # Per bank write bursts
102system.physmem.perBankRdBursts::7 99682 # Per bank write bursts
103system.physmem.perBankRdBursts::8 97394 # Per bank write bursts
104system.physmem.perBankRdBursts::9 128253 # Per bank write bursts
105system.physmem.perBankRdBursts::10 98226 # Per bank write bursts
106system.physmem.perBankRdBursts::11 99141 # Per bank write bursts
107system.physmem.perBankRdBursts::12 97088 # Per bank write bursts
108system.physmem.perBankRdBursts::13 102696 # Per bank write bursts
109system.physmem.perBankRdBursts::14 95500 # Per bank write bursts
110system.physmem.perBankRdBursts::15 96299 # Per bank write bursts
111system.physmem.perBankWrBursts::0 86551 # Per bank write bursts
112system.physmem.perBankWrBursts::1 88756 # Per bank write bursts
113system.physmem.perBankWrBursts::2 83871 # Per bank write bursts
114system.physmem.perBankWrBursts::3 85066 # Per bank write bursts
115system.physmem.perBankWrBursts::4 83226 # Per bank write bursts
116system.physmem.perBankWrBursts::5 90269 # Per bank write bursts
117system.physmem.perBankWrBursts::6 84251 # Per bank write bursts
118system.physmem.perBankWrBursts::7 84163 # Per bank write bursts
119system.physmem.perBankWrBursts::8 81439 # Per bank write bursts
120system.physmem.perBankWrBursts::9 87752 # Per bank write bursts
121system.physmem.perBankWrBursts::10 80936 # Per bank write bursts
122system.physmem.perBankWrBursts::11 83767 # Per bank write bursts
123system.physmem.perBankWrBursts::12 81736 # Per bank write bursts
124system.physmem.perBankWrBursts::13 86099 # Per bank write bursts
125system.physmem.perBankWrBursts::14 79882 # Per bank write bursts
126system.physmem.perBankWrBursts::15 81376 # Per bank write bursts
127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
128system.physmem.numWrRetry 31 # Number of times write queue was full causing retry
129system.physmem.totGap 47314504873500 # Total gap between requests
130system.physmem.readPktSize::0 0 # Read request sizes (log2)
131system.physmem.readPktSize::1 0 # Read request sizes (log2)
132system.physmem.readPktSize::2 0 # Read request sizes (log2)
133system.physmem.readPktSize::3 25 # Read request sizes (log2)
134system.physmem.readPktSize::4 21333 # Read request sizes (log2)
135system.physmem.readPktSize::5 0 # Read request sizes (log2)
136system.physmem.readPktSize::6 1617790 # Read request sizes (log2)
137system.physmem.writePktSize::0 0 # Write request sizes (log2)
138system.physmem.writePktSize::1 0 # Write request sizes (log2)
139system.physmem.writePktSize::2 2 # Write request sizes (log2)
140system.physmem.writePktSize::3 2572 # Write request sizes (log2)
141system.physmem.writePktSize::4 0 # Write request sizes (log2)
142system.physmem.writePktSize::5 0 # Write request sizes (log2)
143system.physmem.writePktSize::6 1348844 # Write request sizes (log2)
144system.physmem.rdQLenPdf::0 620628 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::1 413232 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::2 168696 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::3 160410 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::4 100263 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::5 61902 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::6 33280 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::7 31024 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::8 27376 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::9 8356 # What read queue length does an incoming req see
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155system.physmem.rdQLenPdf::11 2828 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::12 1806 # What read queue length does an incoming req see
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158system.physmem.rdQLenPdf::14 943 # What read queue length does an incoming req see
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192system.physmem.wrQLenPdf::16 24510 # What write queue length does an incoming req see
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194system.physmem.wrQLenPdf::18 44426 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::19 54078 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::20 62537 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::21 72022 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::22 78343 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::23 84949 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::24 88390 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::25 91151 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::26 97634 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::27 95478 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::28 99505 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::29 110959 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::30 99115 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::31 88325 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::32 81966 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::33 3988 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::34 2451 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::35 1670 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::36 1309 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::37 925 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::38 730 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::39 590 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::40 476 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::41 482 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::42 436 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::43 354 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::44 335 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::45 328 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::46 276 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::47 327 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::48 365 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::49 308 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::50 230 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::51 211 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::52 237 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::53 191 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::54 194 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::55 154 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::56 116 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::57 103 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::59 88 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::60 66 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::61 85 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::62 53 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::63 63 # What write queue length does an incoming req see
240system.physmem.bytesPerActivate::samples 1061449 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::mean 180.146498 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::gmean 111.187522 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::stdev 239.320652 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::0-127 660214 62.20% 62.20% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::128-255 197053 18.56% 80.76% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::256-383 62946 5.93% 86.69% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::384-511 34930 3.29% 89.98% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::512-639 24785 2.34% 92.32% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::640-767 13743 1.29% 93.61% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::768-895 13849 1.30% 94.92% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::896-1023 7639 0.72% 95.64% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::1024-1151 46290 4.36% 100.00% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::total 1061449 # Bytes accessed per row activation
254system.physmem.rdPerTurnAround::samples 76381 # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::mean 21.453032 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::stdev 249.608933 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::0-4095 76378 100.00% 100.00% # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::65536-69631 1 0.00% 100.00% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::total 76381 # Reads before turning the bus around for writes
262system.physmem.wrPerTurnAround::samples 76381 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::mean 17.663293 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::gmean 17.185244 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::stdev 6.515109 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::16-19 70865 92.78% 92.78% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::20-23 3094 4.05% 96.83% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::24-27 460 0.60% 97.43% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::28-31 346 0.45% 97.88% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::32-35 86 0.11% 98.00% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::36-39 303 0.40% 98.39% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::40-43 170 0.22% 98.62% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::44-47 108 0.14% 98.76% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::48-51 111 0.15% 98.90% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::52-55 84 0.11% 99.01% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::56-59 42 0.05% 99.07% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::60-63 72 0.09% 99.16% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::64-67 382 0.50% 99.66% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::68-71 49 0.06% 99.73% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::72-75 51 0.07% 99.79% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::76-79 81 0.11% 99.90% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::80-83 17 0.02% 99.92% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::84-87 3 0.00% 99.93% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::100-103 3 0.00% 99.94% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::124-127 4 0.01% 99.95% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::128-131 25 0.03% 99.98% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads
297system.physmem.wrPerTurnAround::148-151 1 0.00% 99.99% # Writes before turning the bus around for reads
298system.physmem.wrPerTurnAround::152-155 3 0.00% 99.99% # Writes before turning the bus around for reads
299system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads
300system.physmem.wrPerTurnAround::164-167 3 0.00% 99.99% # Writes before turning the bus around for reads
301system.physmem.wrPerTurnAround::168-171 2 0.00% 100.00% # Writes before turning the bus around for reads
302system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads
303system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads
304system.physmem.wrPerTurnAround::total 76381 # Writes before turning the bus around for reads
305system.physmem.totQLat 70826288095 # Total ticks spent queuing
306system.physmem.totMemAccLat 101550431845 # Total ticks spent from burst creation until serviced by the DRAM
307system.physmem.totBusLat 8193105000 # Total ticks spent in databus transfers
308system.physmem.avgQLat 43223.11 # Average queueing delay per DRAM burst
309system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
310system.physmem.avgMemAccLat 61973.11 # Average memory access latency per DRAM burst
311system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s
312system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s
313system.physmem.avgRdBWSys 2.20 # Average system read bandwidth in MiByte/s
314system.physmem.avgWrBWSys 1.82 # Average system write bandwidth in MiByte/s
315system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
316system.physmem.busUtil 0.03 # Data bus utilization in percentage
317system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
318system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
319system.physmem.avgRdQLen 1.33 # Average read queue length when enqueuing
320system.physmem.avgWrQLen 26.65 # Average write queue length when enqueuing
321system.physmem.readRowHits 1314681 # Number of row buffer hits during reads
322system.physmem.writeRowHits 611629 # Number of row buffer hits during writes
323system.physmem.readRowHitRate 80.23 # Row buffer hit rate for reads
324system.physmem.writeRowHitRate 45.33 # Row buffer hit rate for writes
325system.physmem.avgGap 15821254.20 # Average gap between requests
326system.physmem.pageHitRate 64.47 # Row buffer hit rate, read and write combined
327system.physmem_0.actEnergy 4090980600 # Energy for activate commands per rank (pJ)
328system.physmem_0.preEnergy 2232181875 # Energy for precharge commands per rank (pJ)
329system.physmem_0.readEnergy 6427387200 # Energy for read commands per rank (pJ)
330system.physmem_0.writeEnergy 4446271440 # Energy for write commands per rank (pJ)
331system.physmem_0.refreshEnergy 3090353329440 # Energy for refresh commands per rank (pJ)
332system.physmem_0.actBackEnergy 1181376195975 # Energy for active background per rank (pJ)
333system.physmem_0.preBackEnergy 27352407006750 # Energy for precharge background per rank (pJ)
334system.physmem_0.totalEnergy 31641333353280 # Total energy per rank (pJ)
335system.physmem_0.averagePower 668.744914 # Core power per rank (mW)
336system.physmem_0.memoryStateTime::IDLE 45502947755010 # Time in different power states
337system.physmem_0.memoryStateTime::REF 1579935240000 # Time in different power states
338system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
339system.physmem_0.memoryStateTime::ACT 231620211240 # Time in different power states
340system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
341system.physmem_1.actEnergy 3933573840 # Energy for activate commands per rank (pJ)
342system.physmem_1.preEnergy 2146295250 # Energy for precharge commands per rank (pJ)
343system.physmem_1.readEnergy 6353809800 # Energy for read commands per rank (pJ)
344system.physmem_1.writeEnergy 4296155760 # Energy for write commands per rank (pJ)
345system.physmem_1.refreshEnergy 3090353329440 # Energy for refresh commands per rank (pJ)
346system.physmem_1.actBackEnergy 1178540083170 # Energy for active background per rank (pJ)
347system.physmem_1.preBackEnergy 27354894825000 # Energy for precharge background per rank (pJ)
348system.physmem_1.totalEnergy 31640518072260 # Total energy per rank (pJ)
349system.physmem_1.averagePower 668.727683 # Core power per rank (mW)
350system.physmem_1.memoryStateTime::IDLE 45507092069935 # Time in different power states
351system.physmem_1.memoryStateTime::REF 1579935240000 # Time in different power states
352system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
353system.physmem_1.memoryStateTime::ACT 227478372065 # Time in different power states
354system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
355system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory
356system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
357system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
358system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
359system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory
360system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory
361system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory

--- 17 unchanged lines hidden (view full) ---

379system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
380system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
381system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
382system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
383system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
384system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
385system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
386system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
387system.cpu0.branchPred.lookups 132773230 # Number of BP lookups
388system.cpu0.branchPred.condPredicted 87983669 # Number of conditional branches predicted
389system.cpu0.branchPred.condIncorrect 6601963 # Number of conditional branches incorrect
390system.cpu0.branchPred.BTBLookups 93351299 # Number of BTB lookups
391system.cpu0.branchPred.BTBHits 61553732 # Number of BTB hits
392system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
393system.cpu0.branchPred.BTBHitPct 65.937735 # BTB Hit Percentage
394system.cpu0.branchPred.usedRAS 18245658 # Number of times the RAS was used to get a target.
395system.cpu0.branchPred.RASInCorrect 197691 # Number of incorrect RAS predictions.
396system.cpu_clk_domain.clock 500 # Clock period in ticks
397system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
401system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
402system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
403system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

418system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
419system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
420system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
421system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
422system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
423system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
424system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
425system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
426system.cpu0.dtb.walker.walks 574649 # Table walker walks requested
427system.cpu0.dtb.walker.walksLong 574649 # Table walker walks initiated with long descriptors
428system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12370 # Level at which table walker walks with long descriptors terminate
429system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88781 # Level at which table walker walks with long descriptors terminate
430system.cpu0.dtb.walker.walksSquashedBefore 269295 # Table walks squashed before starting
431system.cpu0.dtb.walker.walkWaitTime::samples 305354 # Table walker wait (enqueue to first request) latency
432system.cpu0.dtb.walker.walkWaitTime::mean 2428.535405 # Table walker wait (enqueue to first request) latency
433system.cpu0.dtb.walker.walkWaitTime::stdev 14847.246962 # Table walker wait (enqueue to first request) latency
434system.cpu0.dtb.walker.walkWaitTime::0-65535 302828 99.17% 99.17% # Table walker wait (enqueue to first request) latency
435system.cpu0.dtb.walker.walkWaitTime::65536-131071 1395 0.46% 99.63% # Table walker wait (enqueue to first request) latency
436system.cpu0.dtb.walker.walkWaitTime::131072-196607 849 0.28% 99.91% # Table walker wait (enqueue to first request) latency
437system.cpu0.dtb.walker.walkWaitTime::196608-262143 146 0.05% 99.96% # Table walker wait (enqueue to first request) latency
438system.cpu0.dtb.walker.walkWaitTime::262144-327679 44 0.01% 99.97% # Table walker wait (enqueue to first request) latency
439system.cpu0.dtb.walker.walkWaitTime::327680-393215 73 0.02% 99.99% # Table walker wait (enqueue to first request) latency
440system.cpu0.dtb.walker.walkWaitTime::393216-458751 14 0.00% 100.00% # Table walker wait (enqueue to first request) latency
441system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
442system.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
443system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
444system.cpu0.dtb.walker.walkWaitTime::total 305354 # Table walker wait (enqueue to first request) latency
445system.cpu0.dtb.walker.walkCompletionTime::samples 295785 # Table walker service (enqueue to completion) latency
446system.cpu0.dtb.walker.walkCompletionTime::mean 20483.935967 # Table walker service (enqueue to completion) latency
447system.cpu0.dtb.walker.walkCompletionTime::gmean 17662.897721 # Table walker service (enqueue to completion) latency
448system.cpu0.dtb.walker.walkCompletionTime::stdev 19270.228379 # Table walker service (enqueue to completion) latency
449system.cpu0.dtb.walker.walkCompletionTime::0-65535 292925 99.03% 99.03% # Table walker service (enqueue to completion) latency
450system.cpu0.dtb.walker.walkCompletionTime::65536-131071 638 0.22% 99.25% # Table walker service (enqueue to completion) latency
451system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1609 0.54% 99.79% # Table walker service (enqueue to completion) latency
452system.cpu0.dtb.walker.walkCompletionTime::196608-262143 142 0.05% 99.84% # Table walker service (enqueue to completion) latency
453system.cpu0.dtb.walker.walkCompletionTime::262144-327679 290 0.10% 99.94% # Table walker service (enqueue to completion) latency
454system.cpu0.dtb.walker.walkCompletionTime::327680-393215 80 0.03% 99.97% # Table walker service (enqueue to completion) latency
455system.cpu0.dtb.walker.walkCompletionTime::393216-458751 60 0.02% 99.99% # Table walker service (enqueue to completion) latency
456system.cpu0.dtb.walker.walkCompletionTime::458752-524287 29 0.01% 100.00% # Table walker service (enqueue to completion) latency
457system.cpu0.dtb.walker.walkCompletionTime::524288-589823 11 0.00% 100.00% # Table walker service (enqueue to completion) latency
458system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
459system.cpu0.dtb.walker.walkCompletionTime::total 295785 # Table walker service (enqueue to completion) latency
460system.cpu0.dtb.walker.walksPending::samples 533721818468 # Table walker pending requests distribution
461system.cpu0.dtb.walker.walksPending::mean 0.601728 # Table walker pending requests distribution
462system.cpu0.dtb.walker.walksPending::stdev 0.544409 # Table walker pending requests distribution
463system.cpu0.dtb.walker.walksPending::0-1 532429522968 99.76% 99.76% # Table walker pending requests distribution
464system.cpu0.dtb.walker.walksPending::2-3 722596500 0.14% 99.89% # Table walker pending requests distribution
465system.cpu0.dtb.walker.walksPending::4-5 256398500 0.05% 99.94% # Table walker pending requests distribution
466system.cpu0.dtb.walker.walksPending::6-7 121663500 0.02% 99.96% # Table walker pending requests distribution
467system.cpu0.dtb.walker.walksPending::8-9 95265000 0.02% 99.98% # Table walker pending requests distribution
468system.cpu0.dtb.walker.walksPending::10-11 53651000 0.01% 99.99% # Table walker pending requests distribution
469system.cpu0.dtb.walker.walksPending::12-13 19676500 0.00% 100.00% # Table walker pending requests distribution
470system.cpu0.dtb.walker.walksPending::14-15 22307000 0.00% 100.00% # Table walker pending requests distribution
471system.cpu0.dtb.walker.walksPending::16-17 728500 0.00% 100.00% # Table walker pending requests distribution
472system.cpu0.dtb.walker.walksPending::18-19 9000 0.00% 100.00% # Table walker pending requests distribution
473system.cpu0.dtb.walker.walksPending::total 533721818468 # Table walker pending requests distribution
474system.cpu0.dtb.walker.walkPageSizes::4K 88781 87.77% 87.77% # Table walker page sizes translated
475system.cpu0.dtb.walker.walkPageSizes::2M 12370 12.23% 100.00% # Table walker page sizes translated
476system.cpu0.dtb.walker.walkPageSizes::total 101151 # Table walker page sizes translated
477system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 574649 # Table walker requests started/completed, data/inst
478system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
479system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 574649 # Table walker requests started/completed, data/inst
480system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101151 # Table walker requests started/completed, data/inst
481system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
482system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101151 # Table walker requests started/completed, data/inst
483system.cpu0.dtb.walker.walkRequestOrigin::total 675800 # Table walker requests started/completed, data/inst
484system.cpu0.dtb.inst_hits 0 # ITB inst hits
485system.cpu0.dtb.inst_misses 0 # ITB inst misses
486system.cpu0.dtb.read_hits 96498807 # DTB read hits
487system.cpu0.dtb.read_misses 413728 # DTB read misses
488system.cpu0.dtb.write_hits 78559139 # DTB write hits
489system.cpu0.dtb.write_misses 160921 # DTB write misses
490system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
491system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
492system.cpu0.dtb.flush_tlb_mva_asid 44695 # Number of times TLB was flushed by MVA & ASID
493system.cpu0.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
494system.cpu0.dtb.flush_entries 38359 # Number of entries that have been flushed from TLB
495system.cpu0.dtb.align_faults 510 # Number of TLB faults due to alignment restrictions
496system.cpu0.dtb.prefetch_faults 7352 # Number of TLB faults due to prefetch
497system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
498system.cpu0.dtb.perms_faults 37571 # Number of TLB faults due to permissions restrictions
499system.cpu0.dtb.read_accesses 96912535 # DTB read accesses
500system.cpu0.dtb.write_accesses 78720060 # DTB write accesses
501system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
502system.cpu0.dtb.hits 175057946 # DTB hits
503system.cpu0.dtb.misses 574649 # DTB misses
504system.cpu0.dtb.accesses 175632595 # DTB accesses
505system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
506system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
507system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
508system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
509system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
510system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
511system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
512system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

526system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
527system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
528system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
529system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
530system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
531system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
532system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
533system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
534system.cpu0.itb.walker.walks 78486 # Table walker walks requested
535system.cpu0.itb.walker.walksLong 78486 # Table walker walks initiated with long descriptors
536system.cpu0.itb.walker.walksLongTerminationLevel::Level2 887 # Level at which table walker walks with long descriptors terminate
537system.cpu0.itb.walker.walksLongTerminationLevel::Level3 55688 # Level at which table walker walks with long descriptors terminate
538system.cpu0.itb.walker.walksSquashedBefore 9272 # Table walks squashed before starting
539system.cpu0.itb.walker.walkWaitTime::samples 69214 # Table walker wait (enqueue to first request) latency
540system.cpu0.itb.walker.walkWaitTime::mean 1487.228017 # Table walker wait (enqueue to first request) latency
541system.cpu0.itb.walker.walkWaitTime::stdev 11268.156243 # Table walker wait (enqueue to first request) latency
542system.cpu0.itb.walker.walkWaitTime::0-32767 68484 98.95% 98.95% # Table walker wait (enqueue to first request) latency
543system.cpu0.itb.walker.walkWaitTime::32768-65535 441 0.64% 99.58% # Table walker wait (enqueue to first request) latency
544system.cpu0.itb.walker.walkWaitTime::65536-98303 31 0.04% 99.63% # Table walker wait (enqueue to first request) latency
545system.cpu0.itb.walker.walkWaitTime::98304-131071 33 0.05% 99.67% # Table walker wait (enqueue to first request) latency
546system.cpu0.itb.walker.walkWaitTime::131072-163839 145 0.21% 99.88% # Table walker wait (enqueue to first request) latency
547system.cpu0.itb.walker.walkWaitTime::163840-196607 56 0.08% 99.97% # Table walker wait (enqueue to first request) latency
548system.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency
549system.cpu0.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.98% # Table walker wait (enqueue to first request) latency
550system.cpu0.itb.walker.walkWaitTime::262144-294911 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency
551system.cpu0.itb.walker.walkWaitTime::294912-327679 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency
552system.cpu0.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
553system.cpu0.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
554system.cpu0.itb.walker.walkWaitTime::total 69214 # Table walker wait (enqueue to first request) latency
555system.cpu0.itb.walker.walkCompletionTime::samples 65847 # Table walker service (enqueue to completion) latency
556system.cpu0.itb.walker.walkCompletionTime::mean 26575.804517 # Table walker service (enqueue to completion) latency
557system.cpu0.itb.walker.walkCompletionTime::gmean 22865.862438 # Table walker service (enqueue to completion) latency
558system.cpu0.itb.walker.walkCompletionTime::stdev 26620.164914 # Table walker service (enqueue to completion) latency
559system.cpu0.itb.walker.walkCompletionTime::0-65535 64258 97.59% 97.59% # Table walker service (enqueue to completion) latency
560system.cpu0.itb.walker.walkCompletionTime::65536-131071 112 0.17% 97.76% # Table walker service (enqueue to completion) latency
561system.cpu0.itb.walker.walkCompletionTime::131072-196607 1232 1.87% 99.63% # Table walker service (enqueue to completion) latency
562system.cpu0.itb.walker.walkCompletionTime::196608-262143 99 0.15% 99.78% # Table walker service (enqueue to completion) latency
563system.cpu0.itb.walker.walkCompletionTime::262144-327679 79 0.12% 99.90% # Table walker service (enqueue to completion) latency
564system.cpu0.itb.walker.walkCompletionTime::327680-393215 35 0.05% 99.95% # Table walker service (enqueue to completion) latency
565system.cpu0.itb.walker.walkCompletionTime::393216-458751 19 0.03% 99.98% # Table walker service (enqueue to completion) latency
566system.cpu0.itb.walker.walkCompletionTime::458752-524287 11 0.02% 100.00% # Table walker service (enqueue to completion) latency
567system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
568system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
569system.cpu0.itb.walker.walkCompletionTime::total 65847 # Table walker service (enqueue to completion) latency
570system.cpu0.itb.walker.walksPending::samples 404869617088 # Table walker pending requests distribution
571system.cpu0.itb.walker.walksPending::mean 0.839049 # Table walker pending requests distribution
572system.cpu0.itb.walker.walksPending::stdev 0.367685 # Table walker pending requests distribution
573system.cpu0.itb.walker.walksPending::0 65190904252 16.10% 16.10% # Table walker pending requests distribution
574system.cpu0.itb.walker.walksPending::1 339654890336 83.89% 99.99% # Table walker pending requests distribution
575system.cpu0.itb.walker.walksPending::2 21211000 0.01% 100.00% # Table walker pending requests distribution
576system.cpu0.itb.walker.walksPending::3 2423500 0.00% 100.00% # Table walker pending requests distribution
577system.cpu0.itb.walker.walksPending::4 188000 0.00% 100.00% # Table walker pending requests distribution
578system.cpu0.itb.walker.walksPending::total 404869617088 # Table walker pending requests distribution
579system.cpu0.itb.walker.walkPageSizes::4K 55688 98.43% 98.43% # Table walker page sizes translated
580system.cpu0.itb.walker.walkPageSizes::2M 887 1.57% 100.00% # Table walker page sizes translated
581system.cpu0.itb.walker.walkPageSizes::total 56575 # Table walker page sizes translated
582system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
583system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 78486 # Table walker requests started/completed, data/inst
584system.cpu0.itb.walker.walkRequestOrigin_Requested::total 78486 # Table walker requests started/completed, data/inst
585system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
586system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56575 # Table walker requests started/completed, data/inst
587system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56575 # Table walker requests started/completed, data/inst
588system.cpu0.itb.walker.walkRequestOrigin::total 135061 # Table walker requests started/completed, data/inst
589system.cpu0.itb.inst_hits 209228100 # ITB inst hits
590system.cpu0.itb.inst_misses 78486 # ITB inst misses
591system.cpu0.itb.read_hits 0 # DTB read hits
592system.cpu0.itb.read_misses 0 # DTB read misses
593system.cpu0.itb.write_hits 0 # DTB write hits
594system.cpu0.itb.write_misses 0 # DTB write misses
595system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
596system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
597system.cpu0.itb.flush_tlb_mva_asid 44695 # Number of times TLB was flushed by MVA & ASID
598system.cpu0.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
599system.cpu0.itb.flush_entries 27529 # Number of entries that have been flushed from TLB
600system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
601system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
602system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
603system.cpu0.itb.perms_faults 202656 # Number of TLB faults due to permissions restrictions
604system.cpu0.itb.read_accesses 0 # DTB read accesses
605system.cpu0.itb.write_accesses 0 # DTB write accesses
606system.cpu0.itb.inst_accesses 209306586 # ITB inst accesses
607system.cpu0.itb.hits 209228100 # DTB hits
608system.cpu0.itb.misses 78486 # DTB misses
609system.cpu0.itb.accesses 209306586 # DTB accesses
610system.cpu0.numCycles 789288757 # number of cpu cycles simulated
611system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
612system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
613system.cpu0.fetch.icacheStallCycles 88186567 # Number of cycles fetch is stalled on an Icache miss
614system.cpu0.fetch.Insts 587222731 # Number of instructions fetch has processed
615system.cpu0.fetch.Branches 132773230 # Number of branches that fetch encountered
616system.cpu0.fetch.predictedBranches 79799390 # Number of branches that fetch has predicted taken
617system.cpu0.fetch.Cycles 653950437 # Number of cycles fetch has run and was not squashing or blocked
618system.cpu0.fetch.SquashCycles 14236776 # Number of cycles fetch has spent squashing
619system.cpu0.fetch.TlbCycles 1849931 # Number of cycles fetch has spent waiting for tlb
620system.cpu0.fetch.MiscStallCycles 326899 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
621system.cpu0.fetch.PendingTrapStallCycles 5945958 # Number of stall cycles due to pending traps
622system.cpu0.fetch.PendingQuiesceStallCycles 775108 # Number of stall cycles due to pending quiesce instructions
623system.cpu0.fetch.IcacheWaitRetryStallCycles 835772 # Number of stall cycles due to full MSHR
624system.cpu0.fetch.CacheLines 209027134 # Number of cache lines fetched
625system.cpu0.fetch.IcacheSquashes 1689441 # Number of outstanding Icache misses that were squashed
626system.cpu0.fetch.ItlbSquashes 26384 # Number of outstanding ITLB misses that were squashed
627system.cpu0.fetch.rateDist::samples 758989060 # Number of instructions fetched each cycle (Total)
628system.cpu0.fetch.rateDist::mean 0.905560 # Number of instructions fetched each cycle (Total)
629system.cpu0.fetch.rateDist::stdev 1.200949 # Number of instructions fetched each cycle (Total)
630system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
631system.cpu0.fetch.rateDist::0 429796828 56.63% 56.63% # Number of instructions fetched each cycle (Total)
632system.cpu0.fetch.rateDist::1 127839256 16.84% 73.47% # Number of instructions fetched each cycle (Total)
633system.cpu0.fetch.rateDist::2 44588296 5.87% 79.35% # Number of instructions fetched each cycle (Total)
634system.cpu0.fetch.rateDist::3 156764680 20.65% 100.00% # Number of instructions fetched each cycle (Total)
635system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
636system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
637system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
638system.cpu0.fetch.rateDist::total 758989060 # Number of instructions fetched each cycle (Total)
639system.cpu0.fetch.branchRate 0.168219 # Number of branch fetches per cycle
640system.cpu0.fetch.rate 0.743990 # Number of inst fetches per cycle
641system.cpu0.decode.IdleCycles 104466806 # Number of cycles decode is idle
642system.cpu0.decode.BlockedCycles 394260374 # Number of cycles decode is blocked
643system.cpu0.decode.RunCycles 219139619 # Number of cycles decode is running
644system.cpu0.decode.UnblockCycles 36084867 # Number of cycles decode is unblocking
645system.cpu0.decode.SquashCycles 5037394 # Number of cycles decode is squashing
646system.cpu0.decode.BranchResolved 19164568 # Number of times decode resolved a branch
647system.cpu0.decode.BranchMispred 2120604 # Number of times decode detected a branch misprediction
648system.cpu0.decode.DecodedInsts 606612799 # Number of instructions handled by decode
649system.cpu0.decode.SquashedInsts 22830363 # Number of squashed instructions handled by decode
650system.cpu0.rename.SquashCycles 5037394 # Number of cycles rename is squashing
651system.cpu0.rename.IdleCycles 138662412 # Number of cycles rename is idle
652system.cpu0.rename.BlockCycles 63104555 # Number of cycles rename is blocking
653system.cpu0.rename.serializeStallCycles 247113571 # count of cycles rename stalled for serializing inst
654system.cpu0.rename.RunCycles 220473798 # Number of cycles rename is running
655system.cpu0.rename.UnblockCycles 84597330 # Number of cycles rename is unblocking
656system.cpu0.rename.RenamedInsts 589875332 # Number of instructions processed by rename
657system.cpu0.rename.SquashedInsts 5798642 # Number of squashed instructions processed by rename
658system.cpu0.rename.ROBFullEvents 10641909 # Number of times rename has blocked due to ROB full
659system.cpu0.rename.IQFullEvents 381250 # Number of times rename has blocked due to IQ full
660system.cpu0.rename.LQFullEvents 853231 # Number of times rename has blocked due to LQ full
661system.cpu0.rename.SQFullEvents 50687884 # Number of times rename has blocked due to SQ full
662system.cpu0.rename.FullRegisterEvents 10092 # Number of times there has been no free registers
663system.cpu0.rename.RenamedOperands 564041119 # Number of destination operands rename has renamed
664system.cpu0.rename.RenameLookups 911558490 # Number of register rename lookups that rename has made
665system.cpu0.rename.int_rename_lookups 696481853 # Number of integer rename lookups
666system.cpu0.rename.fp_rename_lookups 699850 # Number of floating rename lookups
667system.cpu0.rename.CommittedMaps 508008632 # Number of HB maps that are committed
668system.cpu0.rename.UndoneMaps 56032481 # Number of HB maps that are undone due to squashing
669system.cpu0.rename.serializingInsts 14857922 # count of serializing insts renamed
670system.cpu0.rename.tempSerializingInsts 12905611 # count of temporary serializing insts renamed
671system.cpu0.rename.skidInsts 72985645 # count of insts added to the skid buffer
672system.cpu0.memDep0.insertedLoads 96647129 # Number of loads inserted to the mem dependence unit.
673system.cpu0.memDep0.insertedStores 81788442 # Number of stores inserted to the mem dependence unit.
674system.cpu0.memDep0.conflictingLoads 8697028 # Number of conflicting loads.
675system.cpu0.memDep0.conflictingStores 7422933 # Number of conflicting stores.
676system.cpu0.iq.iqInstsAdded 568689811 # Number of instructions added to the IQ (excludes non-spec)
677system.cpu0.iq.iqNonSpecInstsAdded 14912069 # Number of non-speculative instructions added to the IQ
678system.cpu0.iq.iqInstsIssued 572654206 # Number of instructions issued
679system.cpu0.iq.iqSquashedInstsIssued 2621739 # Number of squashed instructions issued
680system.cpu0.iq.iqSquashedInstsExamined 52458189 # Number of squashed instructions iterated over during squash; mainly for profiling
681system.cpu0.iq.iqSquashedOperandsExamined 34404562 # Number of squashed operands that are examined and possibly removed from graph
682system.cpu0.iq.iqSquashedNonSpecRemoved 258659 # Number of squashed non-spec instructions that were removed
683system.cpu0.iq.issued_per_cycle::samples 758989060 # Number of insts issued each cycle
684system.cpu0.iq.issued_per_cycle::mean 0.754496 # Number of insts issued each cycle
685system.cpu0.iq.issued_per_cycle::stdev 1.046900 # Number of insts issued each cycle
686system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
687system.cpu0.iq.issued_per_cycle::0 446419238 58.82% 58.82% # Number of insts issued each cycle
688system.cpu0.iq.issued_per_cycle::1 130584028 17.20% 76.02% # Number of insts issued each cycle
689system.cpu0.iq.issued_per_cycle::2 111330924 14.67% 90.69% # Number of insts issued each cycle
690system.cpu0.iq.issued_per_cycle::3 63215854 8.33% 99.02% # Number of insts issued each cycle
691system.cpu0.iq.issued_per_cycle::4 7434312 0.98% 100.00% # Number of insts issued each cycle
692system.cpu0.iq.issued_per_cycle::5 4704 0.00% 100.00% # Number of insts issued each cycle
693system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
694system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
695system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
696system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
697system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
698system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
699system.cpu0.iq.issued_per_cycle::total 758989060 # Number of insts issued each cycle
700system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
701system.cpu0.iq.fu_full::IntAlu 59334745 45.62% 45.62% # attempts to use FU when none available
702system.cpu0.iq.fu_full::IntMult 61701 0.05% 45.67% # attempts to use FU when none available
703system.cpu0.iq.fu_full::IntDiv 15638 0.01% 45.68% # attempts to use FU when none available
704system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.68% # attempts to use FU when none available
705system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.68% # attempts to use FU when none available
706system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.68% # attempts to use FU when none available
707system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.68% # attempts to use FU when none available
708system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.68% # attempts to use FU when none available
709system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.68% # attempts to use FU when none available
710system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.68% # attempts to use FU when none available
711system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.68% # attempts to use FU when none available
712system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.68% # attempts to use FU when none available
713system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.68% # attempts to use FU when none available
714system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.68% # attempts to use FU when none available
715system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.68% # attempts to use FU when none available
716system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.68% # attempts to use FU when none available
717system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.68% # attempts to use FU when none available
718system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.68% # attempts to use FU when none available
719system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.68% # attempts to use FU when none available
720system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.68% # attempts to use FU when none available
721system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.68% # attempts to use FU when none available
722system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.68% # attempts to use FU when none available
723system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.68% # attempts to use FU when none available
724system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.68% # attempts to use FU when none available
725system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.68% # attempts to use FU when none available
726system.cpu0.iq.fu_full::SimdFloatMisc 17 0.00% 45.68% # attempts to use FU when none available
727system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.68% # attempts to use FU when none available
728system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.68% # attempts to use FU when none available
729system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.68% # attempts to use FU when none available
730system.cpu0.iq.fu_full::MemRead 34211739 26.30% 71.98% # attempts to use FU when none available
731system.cpu0.iq.fu_full::MemWrite 36440950 28.02% 100.00% # attempts to use FU when none available
732system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
733system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
734system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
735system.cpu0.iq.FU_type_0::IntAlu 391815865 68.42% 68.42% # Type of FU issued
736system.cpu0.iq.FU_type_0::IntMult 1438003 0.25% 68.67% # Type of FU issued
737system.cpu0.iq.FU_type_0::IntDiv 75602 0.01% 68.69% # Type of FU issued
738system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.69% # Type of FU issued
739system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.69% # Type of FU issued
740system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.69% # Type of FU issued
741system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.69% # Type of FU issued
742system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.69% # Type of FU issued
743system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.69% # Type of FU issued
744system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.69% # Type of FU issued
745system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.69% # Type of FU issued

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752system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.69% # Type of FU issued
753system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.69% # Type of FU issued
754system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.69% # Type of FU issued
755system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.69% # Type of FU issued
756system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.69% # Type of FU issued
757system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.69% # Type of FU issued
758system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.69% # Type of FU issued
759system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.69% # Type of FU issued
760system.cpu0.iq.FU_type_0::SimdFloatMisc 42288 0.01% 68.69% # Type of FU issued
761system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued
762system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued
763system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued
764system.cpu0.iq.FU_type_0::MemRead 99488891 17.37% 86.07% # Type of FU issued
765system.cpu0.iq.FU_type_0::MemWrite 79793556 13.93% 100.00% # Type of FU issued
766system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
767system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
768system.cpu0.iq.FU_type_0::total 572654206 # Type of FU issued
769system.cpu0.iq.rate 0.725532 # Inst issue rate
770system.cpu0.iq.fu_busy_cnt 130064790 # FU busy when requested
771system.cpu0.iq.fu_busy_rate 0.227126 # FU busy rate (busy events/executed inst)
772system.cpu0.iq.int_inst_queue_reads 2035873022 # Number of integer instruction queue reads
773system.cpu0.iq.int_inst_queue_writes 635743875 # Number of integer instruction queue writes
774system.cpu0.iq.int_inst_queue_wakeup_accesses 556160378 # Number of integer instruction queue wakeup accesses
775system.cpu0.iq.fp_inst_queue_reads 1110977 # Number of floating instruction queue reads
776system.cpu0.iq.fp_inst_queue_writes 443650 # Number of floating instruction queue writes
777system.cpu0.iq.fp_inst_queue_wakeup_accesses 409772 # Number of floating instruction queue wakeup accesses
778system.cpu0.iq.int_alu_accesses 702028683 # Number of integer alu accesses
779system.cpu0.iq.fp_alu_accesses 690312 # Number of floating point alu accesses
780system.cpu0.iew.lsq.thread0.forwLoads 2617659 # Number of loads that had data forwarded from stores
781system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
782system.cpu0.iew.lsq.thread0.squashedLoads 11976787 # Number of loads squashed
783system.cpu0.iew.lsq.thread0.ignoredResponses 15696 # Number of memory responses ignored because the instruction is squashed
784system.cpu0.iew.lsq.thread0.memOrderViolation 128509 # Number of memory ordering violations
785system.cpu0.iew.lsq.thread0.squashedStores 5549515 # Number of stores squashed
786system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
787system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
788system.cpu0.iew.lsq.thread0.rescheduledLoads 2485031 # Number of loads that were rescheduled
789system.cpu0.iew.lsq.thread0.cacheBlocked 4622903 # Number of times an access to memory failed due to the cache being blocked
790system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
791system.cpu0.iew.iewSquashCycles 5037394 # Number of cycles IEW is squashing
792system.cpu0.iew.iewBlockCycles 7963594 # Number of cycles IEW is blocking
793system.cpu0.iew.iewUnblockCycles 7170717 # Number of cycles IEW is unblocking
794system.cpu0.iew.iewDispatchedInsts 583715188 # Number of instructions dispatched to IQ
795system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
796system.cpu0.iew.iewDispLoadInsts 96647129 # Number of dispatched load instructions
797system.cpu0.iew.iewDispStoreInsts 81788442 # Number of dispatched store instructions
798system.cpu0.iew.iewDispNonSpecInsts 12627210 # Number of dispatched non-speculative instructions
799system.cpu0.iew.iewIQFullEvents 54569 # Number of times the IQ has become full, causing a stall
800system.cpu0.iew.iewLSQFullEvents 7047111 # Number of times the LSQ has become full, causing a stall
801system.cpu0.iew.memOrderViolationEvents 128509 # Number of memory order violations
802system.cpu0.iew.predictedTakenIncorrect 1976888 # Number of branches that were predicted taken incorrectly
803system.cpu0.iew.predictedNotTakenIncorrect 2838838 # Number of branches that were predicted not taken incorrectly
804system.cpu0.iew.branchMispredicts 4815726 # Number of branch mispredicts detected at execute
805system.cpu0.iew.iewExecutedInsts 565090405 # Number of executed instructions
806system.cpu0.iew.iewExecLoadInsts 96493854 # Number of load instructions executed
807system.cpu0.iew.iewExecSquashedInsts 6996299 # Number of squashed instructions skipped in execute
808system.cpu0.iew.exec_swp 0 # number of swp insts executed
809system.cpu0.iew.exec_nop 113308 # number of nop insts executed
810system.cpu0.iew.exec_refs 175051410 # number of memory reference insts executed
811system.cpu0.iew.exec_branches 106737211 # Number of branches executed
812system.cpu0.iew.exec_stores 78557556 # Number of stores executed
813system.cpu0.iew.exec_rate 0.715949 # Inst execution rate
814system.cpu0.iew.wb_sent 557331942 # cumulative count of insts sent to commit
815system.cpu0.iew.wb_count 556570150 # cumulative count of insts written-back
816system.cpu0.iew.wb_producers 270940614 # num instructions producing a value
817system.cpu0.iew.wb_consumers 444738310 # num instructions consuming a value
818system.cpu0.iew.wb_rate 0.705154 # insts written-back per cycle
819system.cpu0.iew.wb_fanout 0.609214 # average fanout of values written-back
820system.cpu0.commit.commitSquashedInsts 45776609 # The number of squashed insts skipped by commit
821system.cpu0.commit.commitNonSpecStalls 14653410 # The number of times commit has been forced to stall to communicate backwards
822system.cpu0.commit.branchMispredicts 4520969 # The number of times a branch was mispredicted
823system.cpu0.commit.committed_per_cycle::samples 750266004 # Number of insts commited each cycle
824system.cpu0.commit.committed_per_cycle::mean 0.707940 # Number of insts commited each cycle
825system.cpu0.commit.committed_per_cycle::stdev 1.517135 # Number of insts commited each cycle
826system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
827system.cpu0.commit.committed_per_cycle::0 517711139 69.00% 69.00% # Number of insts commited each cycle
828system.cpu0.commit.committed_per_cycle::1 119807975 15.97% 84.97% # Number of insts commited each cycle
829system.cpu0.commit.committed_per_cycle::2 52242096 6.96% 91.94% # Number of insts commited each cycle
830system.cpu0.commit.committed_per_cycle::3 17345693 2.31% 94.25% # Number of insts commited each cycle
831system.cpu0.commit.committed_per_cycle::4 12502849 1.67% 95.91% # Number of insts commited each cycle
832system.cpu0.commit.committed_per_cycle::5 8569717 1.14% 97.06% # Number of insts commited each cycle
833system.cpu0.commit.committed_per_cycle::6 5628818 0.75% 97.81% # Number of insts commited each cycle
834system.cpu0.commit.committed_per_cycle::7 3480187 0.46% 98.27% # Number of insts commited each cycle
835system.cpu0.commit.committed_per_cycle::8 12977530 1.73% 100.00% # Number of insts commited each cycle
836system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
837system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
838system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
839system.cpu0.commit.committed_per_cycle::total 750266004 # Number of insts commited each cycle
840system.cpu0.commit.committedInsts 452897446 # Number of instructions committed
841system.cpu0.commit.committedOps 531143684 # Number of ops (including micro ops) committed
842system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
843system.cpu0.commit.refs 160909268 # Number of memory references committed
844system.cpu0.commit.loads 84670341 # Number of loads committed
845system.cpu0.commit.membars 3612111 # Number of memory barriers committed
846system.cpu0.commit.branches 101352463 # Number of branches committed
847system.cpu0.commit.fp_insts 401266 # Number of committed floating point instructions.
848system.cpu0.commit.int_insts 487082373 # Number of committed integer instructions.
849system.cpu0.commit.function_calls 13540419 # Number of function calls committed.
850system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
851system.cpu0.commit.op_class_0::IntAlu 368934944 69.46% 69.46% # Class of committed instruction
852system.cpu0.commit.op_class_0::IntMult 1203387 0.23% 69.69% # Class of committed instruction
853system.cpu0.commit.op_class_0::IntDiv 59505 0.01% 69.70% # Class of committed instruction
854system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction
855system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction
856system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction
857system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction
858system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction
859system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction
860system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction
861system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction
862system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction
863system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction
864system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction
865system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction
866system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction
867system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction
868system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction
869system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction
870system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction
871system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.70% # Class of committed instruction
872system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction
873system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.70% # Class of committed instruction
874system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.70% # Class of committed instruction
875system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction
876system.cpu0.commit.op_class_0::SimdFloatMisc 36580 0.01% 69.71% # Class of committed instruction
877system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction
878system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction
879system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction
880system.cpu0.commit.op_class_0::MemRead 84670341 15.94% 85.65% # Class of committed instruction
881system.cpu0.commit.op_class_0::MemWrite 76238927 14.35% 100.00% # Class of committed instruction
882system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
883system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
884system.cpu0.commit.op_class_0::total 531143684 # Class of committed instruction
885system.cpu0.commit.bw_lim_events 12977530 # number cycles where commit BW limit reached
886system.cpu0.rob.rob_reads 1309875410 # The number of ROB reads
887system.cpu0.rob.rob_writes 1162529912 # The number of ROB writes
888system.cpu0.timesIdled 987855 # Number of times that the entire CPU went into an idle state and unscheduled itself
889system.cpu0.idleCycles 30299697 # Total number of cycles that the CPU has spent unscheduled due to idling
890system.cpu0.quiesceCycles 93839724027 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
891system.cpu0.committedInsts 452897446 # Number of Instructions Simulated
892system.cpu0.committedOps 531143684 # Number of Ops (including micro ops) Simulated
893system.cpu0.cpi 1.742754 # CPI: Cycles Per Instruction
894system.cpu0.cpi_total 1.742754 # CPI: Total CPI of All Threads
895system.cpu0.ipc 0.573805 # IPC: Instructions Per Cycle
896system.cpu0.ipc_total 0.573805 # IPC: Total IPC of All Threads
897system.cpu0.int_regfile_reads 666947650 # number of integer regfile reads
898system.cpu0.int_regfile_writes 396615179 # number of integer regfile writes
899system.cpu0.fp_regfile_reads 682678 # number of floating regfile reads
900system.cpu0.fp_regfile_writes 298828 # number of floating regfile writes
901system.cpu0.cc_regfile_reads 124079442 # number of cc regfile reads
902system.cpu0.cc_regfile_writes 124706529 # number of cc regfile writes
903system.cpu0.misc_regfile_reads 1318525921 # number of misc regfile reads
904system.cpu0.misc_regfile_writes 14734262 # number of misc regfile writes
905system.cpu0.dcache.tags.replacements 5881965 # number of replacements
906system.cpu0.dcache.tags.tagsinuse 478.956800 # Cycle average of tags in use
907system.cpu0.dcache.tags.total_refs 149156359 # Total number of references to valid blocks.
908system.cpu0.dcache.tags.sampled_refs 5882471 # Sample count of references to valid blocks.
909system.cpu0.dcache.tags.avg_refs 25.356072 # Average number of references to valid blocks.
910system.cpu0.dcache.tags.warmup_cycle 2962390000 # Cycle when the warmup percentage was hit.
911system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.956800 # Average occupied blocks per requestor
912system.cpu0.dcache.tags.occ_percent::cpu0.data 0.935463 # Average percentage of cache occupancy
913system.cpu0.dcache.tags.occ_percent::total 0.935463 # Average percentage of cache occupancy
914system.cpu0.dcache.tags.occ_task_id_blocks::1024 506 # Occupied blocks per task id
915system.cpu0.dcache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id
916system.cpu0.dcache.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id
917system.cpu0.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id
918system.cpu0.dcache.tags.occ_task_id_percent::1024 0.988281 # Percentage of cache occupancy per task id
919system.cpu0.dcache.tags.tag_accesses 334047120 # Number of tag accesses
920system.cpu0.dcache.tags.data_accesses 334047120 # Number of data accesses
921system.cpu0.dcache.ReadReq_hits::cpu0.data 78452229 # number of ReadReq hits
922system.cpu0.dcache.ReadReq_hits::total 78452229 # number of ReadReq hits
923system.cpu0.dcache.WriteReq_hits::cpu0.data 65886147 # number of WriteReq hits
924system.cpu0.dcache.WriteReq_hits::total 65886147 # number of WriteReq hits
925system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209885 # number of SoftPFReq hits
926system.cpu0.dcache.SoftPFReq_hits::total 209885 # number of SoftPFReq hits
927system.cpu0.dcache.WriteLineReq_hits::cpu0.data 258671 # number of WriteLineReq hits
928system.cpu0.dcache.WriteLineReq_hits::total 258671 # number of WriteLineReq hits
929system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1757048 # number of LoadLockedReq hits
930system.cpu0.dcache.LoadLockedReq_hits::total 1757048 # number of LoadLockedReq hits
931system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1773588 # number of StoreCondReq hits
932system.cpu0.dcache.StoreCondReq_hits::total 1773588 # number of StoreCondReq hits
933system.cpu0.dcache.demand_hits::cpu0.data 144338376 # number of demand (read+write) hits
934system.cpu0.dcache.demand_hits::total 144338376 # number of demand (read+write) hits
935system.cpu0.dcache.overall_hits::cpu0.data 144548261 # number of overall hits
936system.cpu0.dcache.overall_hits::total 144548261 # number of overall hits
937system.cpu0.dcache.ReadReq_misses::cpu0.data 6459284 # number of ReadReq misses
938system.cpu0.dcache.ReadReq_misses::total 6459284 # number of ReadReq misses
939system.cpu0.dcache.WriteReq_misses::cpu0.data 7288144 # number of WriteReq misses
940system.cpu0.dcache.WriteReq_misses::total 7288144 # number of WriteReq misses
941system.cpu0.dcache.SoftPFReq_misses::cpu0.data 689122 # number of SoftPFReq misses
942system.cpu0.dcache.SoftPFReq_misses::total 689122 # number of SoftPFReq misses
943system.cpu0.dcache.WriteLineReq_misses::cpu0.data 817042 # number of WriteLineReq misses
944system.cpu0.dcache.WriteLineReq_misses::total 817042 # number of WriteLineReq misses
945system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 245228 # number of LoadLockedReq misses
946system.cpu0.dcache.LoadLockedReq_misses::total 245228 # number of LoadLockedReq misses
947system.cpu0.dcache.StoreCondReq_misses::cpu0.data 193470 # number of StoreCondReq misses
948system.cpu0.dcache.StoreCondReq_misses::total 193470 # number of StoreCondReq misses
949system.cpu0.dcache.demand_misses::cpu0.data 13747428 # number of demand (read+write) misses
950system.cpu0.dcache.demand_misses::total 13747428 # number of demand (read+write) misses
951system.cpu0.dcache.overall_misses::cpu0.data 14436550 # number of overall misses
952system.cpu0.dcache.overall_misses::total 14436550 # number of overall misses
953system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 110052955500 # number of ReadReq miss cycles
954system.cpu0.dcache.ReadReq_miss_latency::total 110052955500 # number of ReadReq miss cycles
955system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 170225463786 # number of WriteReq miss cycles
956system.cpu0.dcache.WriteReq_miss_latency::total 170225463786 # number of WriteReq miss cycles
957system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 91498155223 # number of WriteLineReq miss cycles
958system.cpu0.dcache.WriteLineReq_miss_latency::total 91498155223 # number of WriteLineReq miss cycles
959system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3890581500 # number of LoadLockedReq miss cycles
960system.cpu0.dcache.LoadLockedReq_miss_latency::total 3890581500 # number of LoadLockedReq miss cycles
961system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5535454500 # number of StoreCondReq miss cycles
962system.cpu0.dcache.StoreCondReq_miss_latency::total 5535454500 # number of StoreCondReq miss cycles
963system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 8571500 # number of StoreCondFailReq miss cycles
964system.cpu0.dcache.StoreCondFailReq_miss_latency::total 8571500 # number of StoreCondFailReq miss cycles
965system.cpu0.dcache.demand_miss_latency::cpu0.data 280278419286 # number of demand (read+write) miss cycles
966system.cpu0.dcache.demand_miss_latency::total 280278419286 # number of demand (read+write) miss cycles
967system.cpu0.dcache.overall_miss_latency::cpu0.data 280278419286 # number of overall miss cycles
968system.cpu0.dcache.overall_miss_latency::total 280278419286 # number of overall miss cycles
969system.cpu0.dcache.ReadReq_accesses::cpu0.data 84911513 # number of ReadReq accesses(hits+misses)
970system.cpu0.dcache.ReadReq_accesses::total 84911513 # number of ReadReq accesses(hits+misses)
971system.cpu0.dcache.WriteReq_accesses::cpu0.data 73174291 # number of WriteReq accesses(hits+misses)
972system.cpu0.dcache.WriteReq_accesses::total 73174291 # number of WriteReq accesses(hits+misses)
973system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 899007 # number of SoftPFReq accesses(hits+misses)
974system.cpu0.dcache.SoftPFReq_accesses::total 899007 # number of SoftPFReq accesses(hits+misses)
975system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1075713 # number of WriteLineReq accesses(hits+misses)
976system.cpu0.dcache.WriteLineReq_accesses::total 1075713 # number of WriteLineReq accesses(hits+misses)
977system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2002276 # number of LoadLockedReq accesses(hits+misses)
978system.cpu0.dcache.LoadLockedReq_accesses::total 2002276 # number of LoadLockedReq accesses(hits+misses)
979system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1967058 # number of StoreCondReq accesses(hits+misses)
980system.cpu0.dcache.StoreCondReq_accesses::total 1967058 # number of StoreCondReq accesses(hits+misses)
981system.cpu0.dcache.demand_accesses::cpu0.data 158085804 # number of demand (read+write) accesses
982system.cpu0.dcache.demand_accesses::total 158085804 # number of demand (read+write) accesses
983system.cpu0.dcache.overall_accesses::cpu0.data 158984811 # number of overall (read+write) accesses
984system.cpu0.dcache.overall_accesses::total 158984811 # number of overall (read+write) accesses
985system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.076071 # miss rate for ReadReq accesses
986system.cpu0.dcache.ReadReq_miss_rate::total 0.076071 # miss rate for ReadReq accesses
987system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.099600 # miss rate for WriteReq accesses
988system.cpu0.dcache.WriteReq_miss_rate::total 0.099600 # miss rate for WriteReq accesses
989system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.766537 # miss rate for SoftPFReq accesses
990system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766537 # miss rate for SoftPFReq accesses
991system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.759535 # miss rate for WriteLineReq accesses
992system.cpu0.dcache.WriteLineReq_miss_rate::total 0.759535 # miss rate for WriteLineReq accesses
993system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.122475 # miss rate for LoadLockedReq accesses
994system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.122475 # miss rate for LoadLockedReq accesses
995system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098355 # miss rate for StoreCondReq accesses
996system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098355 # miss rate for StoreCondReq accesses
997system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086962 # miss rate for demand accesses
998system.cpu0.dcache.demand_miss_rate::total 0.086962 # miss rate for demand accesses
999system.cpu0.dcache.overall_miss_rate::cpu0.data 0.090805 # miss rate for overall accesses
1000system.cpu0.dcache.overall_miss_rate::total 0.090805 # miss rate for overall accesses
1001system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17037.949640 # average ReadReq miss latency
1002system.cpu0.dcache.ReadReq_avg_miss_latency::total 17037.949640 # average ReadReq miss latency
1003system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23356.490183 # average WriteReq miss latency
1004system.cpu0.dcache.WriteReq_avg_miss_latency::total 23356.490183 # average WriteReq miss latency
1005system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 111987.089064 # average WriteLineReq miss latency
1006system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 111987.089064 # average WriteLineReq miss latency
1007system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15865.160177 # average LoadLockedReq miss latency
1008system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15865.160177 # average LoadLockedReq miss latency
1009system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28611.435882 # average StoreCondReq miss latency
1010system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28611.435882 # average StoreCondReq miss latency
1011system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
1012system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1013system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20387.698651 # average overall miss latency
1014system.cpu0.dcache.demand_avg_miss_latency::total 20387.698651 # average overall miss latency
1015system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19414.501338 # average overall miss latency
1016system.cpu0.dcache.overall_avg_miss_latency::total 19414.501338 # average overall miss latency
1017system.cpu0.dcache.blocked_cycles::no_mshrs 28857818 # number of cycles access was blocked
1018system.cpu0.dcache.blocked_cycles::no_targets 25701299 # number of cycles access was blocked
1019system.cpu0.dcache.blocked::no_mshrs 757026 # number of cycles access was blocked
1020system.cpu0.dcache.blocked::no_targets 713337 # number of cycles access was blocked
1021system.cpu0.dcache.avg_blocked_cycles::no_mshrs 38.119983 # average number of cycles each access was blocked
1022system.cpu0.dcache.avg_blocked_cycles::no_targets 36.029673 # average number of cycles each access was blocked
1023system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1024system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1025system.cpu0.dcache.writebacks::writebacks 5882015 # number of writebacks
1026system.cpu0.dcache.writebacks::total 5882015 # number of writebacks
1027system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3286907 # number of ReadReq MSHR hits
1028system.cpu0.dcache.ReadReq_mshr_hits::total 3286907 # number of ReadReq MSHR hits
1029system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5842010 # number of WriteReq MSHR hits
1030system.cpu0.dcache.WriteReq_mshr_hits::total 5842010 # number of WriteReq MSHR hits
1031system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4476 # number of WriteLineReq MSHR hits
1032system.cpu0.dcache.WriteLineReq_mshr_hits::total 4476 # number of WriteLineReq MSHR hits
1033system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 122858 # number of LoadLockedReq MSHR hits
1034system.cpu0.dcache.LoadLockedReq_mshr_hits::total 122858 # number of LoadLockedReq MSHR hits
1035system.cpu0.dcache.demand_mshr_hits::cpu0.data 9128917 # number of demand (read+write) MSHR hits
1036system.cpu0.dcache.demand_mshr_hits::total 9128917 # number of demand (read+write) MSHR hits
1037system.cpu0.dcache.overall_mshr_hits::cpu0.data 9128917 # number of overall MSHR hits
1038system.cpu0.dcache.overall_mshr_hits::total 9128917 # number of overall MSHR hits
1039system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3172377 # number of ReadReq MSHR misses
1040system.cpu0.dcache.ReadReq_mshr_misses::total 3172377 # number of ReadReq MSHR misses
1041system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1446134 # number of WriteReq MSHR misses
1042system.cpu0.dcache.WriteReq_mshr_misses::total 1446134 # number of WriteReq MSHR misses
1043system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 682277 # number of SoftPFReq MSHR misses
1044system.cpu0.dcache.SoftPFReq_mshr_misses::total 682277 # number of SoftPFReq MSHR misses
1045system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 812566 # number of WriteLineReq MSHR misses
1046system.cpu0.dcache.WriteLineReq_mshr_misses::total 812566 # number of WriteLineReq MSHR misses
1047system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 122370 # number of LoadLockedReq MSHR misses
1048system.cpu0.dcache.LoadLockedReq_mshr_misses::total 122370 # number of LoadLockedReq MSHR misses
1049system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 193461 # number of StoreCondReq MSHR misses
1050system.cpu0.dcache.StoreCondReq_mshr_misses::total 193461 # number of StoreCondReq MSHR misses
1051system.cpu0.dcache.demand_mshr_misses::cpu0.data 4618511 # number of demand (read+write) MSHR misses
1052system.cpu0.dcache.demand_mshr_misses::total 4618511 # number of demand (read+write) MSHR misses
1053system.cpu0.dcache.overall_mshr_misses::cpu0.data 5300788 # number of overall MSHR misses
1054system.cpu0.dcache.overall_mshr_misses::total 5300788 # number of overall MSHR misses
1055system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32879 # number of ReadReq MSHR uncacheable
1056system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32879 # number of ReadReq MSHR uncacheable
1057system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32981 # number of WriteReq MSHR uncacheable
1058system.cpu0.dcache.WriteReq_mshr_uncacheable::total 32981 # number of WriteReq MSHR uncacheable
1059system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65860 # number of overall MSHR uncacheable misses
1060system.cpu0.dcache.overall_mshr_uncacheable_misses::total 65860 # number of overall MSHR uncacheable misses
1061system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 49995905500 # number of ReadReq MSHR miss cycles
1062system.cpu0.dcache.ReadReq_mshr_miss_latency::total 49995905500 # number of ReadReq MSHR miss cycles
1063system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 39710234771 # number of WriteReq MSHR miss cycles
1064system.cpu0.dcache.WriteReq_mshr_miss_latency::total 39710234771 # number of WriteReq MSHR miss cycles
1065system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17655223500 # number of SoftPFReq MSHR miss cycles
1066system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17655223500 # number of SoftPFReq MSHR miss cycles
1067system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 90433652723 # number of WriteLineReq MSHR miss cycles
1068system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 90433652723 # number of WriteLineReq MSHR miss cycles
1069system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1780369000 # number of LoadLockedReq MSHR miss cycles
1070system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1780369000 # number of LoadLockedReq MSHR miss cycles
1071system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5342108500 # number of StoreCondReq MSHR miss cycles
1072system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5342108500 # number of StoreCondReq MSHR miss cycles
1073system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 8456500 # number of StoreCondFailReq MSHR miss cycles
1074system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 8456500 # number of StoreCondFailReq MSHR miss cycles
1075system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 89706140271 # number of demand (read+write) MSHR miss cycles
1076system.cpu0.dcache.demand_mshr_miss_latency::total 89706140271 # number of demand (read+write) MSHR miss cycles
1077system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 107361363771 # number of overall MSHR miss cycles
1078system.cpu0.dcache.overall_mshr_miss_latency::total 107361363771 # number of overall MSHR miss cycles
1079system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6303225000 # number of ReadReq MSHR uncacheable cycles
1080system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6303225000 # number of ReadReq MSHR uncacheable cycles
1081system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 6238855500 # number of WriteReq MSHR uncacheable cycles
1082system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6238855500 # number of WriteReq MSHR uncacheable cycles
1083system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12542080500 # number of overall MSHR uncacheable cycles
1084system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12542080500 # number of overall MSHR uncacheable cycles
1085system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037361 # mshr miss rate for ReadReq accesses
1086system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037361 # mshr miss rate for ReadReq accesses
1087system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019763 # mshr miss rate for WriteReq accesses
1088system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019763 # mshr miss rate for WriteReq accesses
1089system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.758923 # mshr miss rate for SoftPFReq accesses
1090system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.758923 # mshr miss rate for SoftPFReq accesses
1091system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.755374 # mshr miss rate for WriteLineReq accesses
1092system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.755374 # mshr miss rate for WriteLineReq accesses
1093system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061115 # mshr miss rate for LoadLockedReq accesses
1094system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061115 # mshr miss rate for LoadLockedReq accesses
1095system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098350 # mshr miss rate for StoreCondReq accesses
1096system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098350 # mshr miss rate for StoreCondReq accesses
1097system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029215 # mshr miss rate for demand accesses
1098system.cpu0.dcache.demand_mshr_miss_rate::total 0.029215 # mshr miss rate for demand accesses
1099system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.033341 # mshr miss rate for overall accesses
1100system.cpu0.dcache.overall_mshr_miss_rate::total 0.033341 # mshr miss rate for overall accesses
1101system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15759.761687 # average ReadReq mshr miss latency
1102system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15759.761687 # average ReadReq mshr miss latency
1103system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27459.581734 # average WriteReq mshr miss latency
1104system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27459.581734 # average WriteReq mshr miss latency
1105system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25876.914362 # average SoftPFReq mshr miss latency
1106system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25876.914362 # average SoftPFReq mshr miss latency
1107system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 111293.916707 # average WriteLineReq mshr miss latency
1108system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 111293.916707 # average WriteLineReq mshr miss latency
1109system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14549.064313 # average LoadLockedReq mshr miss latency
1110system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14549.064313 # average LoadLockedReq mshr miss latency
1111system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27613.361349 # average StoreCondReq mshr miss latency
1112system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27613.361349 # average StoreCondReq mshr miss latency
1113system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
1114system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1115system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19423.173458 # average overall mshr miss latency
1116system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19423.173458 # average overall mshr miss latency
1117system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20253.849762 # average overall mshr miss latency
1118system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20253.849762 # average overall mshr miss latency
1119system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191709.753946 # average ReadReq mshr uncacheable latency
1120system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191709.753946 # average ReadReq mshr uncacheable latency
1121system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189165.140535 # average WriteReq mshr uncacheable latency
1122system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189165.140535 # average WriteReq mshr uncacheable latency
1123system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190435.476769 # average overall mshr uncacheable latency
1124system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190435.476769 # average overall mshr uncacheable latency
1125system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1126system.cpu0.icache.tags.replacements 6005225 # number of replacements
1127system.cpu0.icache.tags.tagsinuse 511.936915 # Cycle average of tags in use
1128system.cpu0.icache.tags.total_refs 202641946 # Total number of references to valid blocks.
1129system.cpu0.icache.tags.sampled_refs 6005737 # Sample count of references to valid blocks.
1130system.cpu0.icache.tags.avg_refs 33.741395 # Average number of references to valid blocks.
1131system.cpu0.icache.tags.warmup_cycle 21603135000 # Cycle when the warmup percentage was hit.
1132system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.936915 # Average occupied blocks per requestor
1133system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999877 # Average percentage of cache occupancy
1134system.cpu0.icache.tags.occ_percent::total 0.999877 # Average percentage of cache occupancy
1135system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1136system.cpu0.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
1137system.cpu0.icache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id
1138system.cpu0.icache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id
1139system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1140system.cpu0.icache.tags.tag_accesses 424004104 # Number of tag accesses
1141system.cpu0.icache.tags.data_accesses 424004104 # Number of data accesses
1142system.cpu0.icache.ReadReq_hits::cpu0.inst 202641946 # number of ReadReq hits
1143system.cpu0.icache.ReadReq_hits::total 202641946 # number of ReadReq hits
1144system.cpu0.icache.demand_hits::cpu0.inst 202641946 # number of demand (read+write) hits
1145system.cpu0.icache.demand_hits::total 202641946 # number of demand (read+write) hits
1146system.cpu0.icache.overall_hits::cpu0.inst 202641946 # number of overall hits
1147system.cpu0.icache.overall_hits::total 202641946 # number of overall hits
1148system.cpu0.icache.ReadReq_misses::cpu0.inst 6357218 # number of ReadReq misses
1149system.cpu0.icache.ReadReq_misses::total 6357218 # number of ReadReq misses
1150system.cpu0.icache.demand_misses::cpu0.inst 6357218 # number of demand (read+write) misses
1151system.cpu0.icache.demand_misses::total 6357218 # number of demand (read+write) misses
1152system.cpu0.icache.overall_misses::cpu0.inst 6357218 # number of overall misses
1153system.cpu0.icache.overall_misses::total 6357218 # number of overall misses
1154system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 72002088632 # number of ReadReq miss cycles
1155system.cpu0.icache.ReadReq_miss_latency::total 72002088632 # number of ReadReq miss cycles
1156system.cpu0.icache.demand_miss_latency::cpu0.inst 72002088632 # number of demand (read+write) miss cycles
1157system.cpu0.icache.demand_miss_latency::total 72002088632 # number of demand (read+write) miss cycles
1158system.cpu0.icache.overall_miss_latency::cpu0.inst 72002088632 # number of overall miss cycles
1159system.cpu0.icache.overall_miss_latency::total 72002088632 # number of overall miss cycles
1160system.cpu0.icache.ReadReq_accesses::cpu0.inst 208999164 # number of ReadReq accesses(hits+misses)
1161system.cpu0.icache.ReadReq_accesses::total 208999164 # number of ReadReq accesses(hits+misses)
1162system.cpu0.icache.demand_accesses::cpu0.inst 208999164 # number of demand (read+write) accesses
1163system.cpu0.icache.demand_accesses::total 208999164 # number of demand (read+write) accesses
1164system.cpu0.icache.overall_accesses::cpu0.inst 208999164 # number of overall (read+write) accesses
1165system.cpu0.icache.overall_accesses::total 208999164 # number of overall (read+write) accesses
1166system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.030417 # miss rate for ReadReq accesses
1167system.cpu0.icache.ReadReq_miss_rate::total 0.030417 # miss rate for ReadReq accesses
1168system.cpu0.icache.demand_miss_rate::cpu0.inst 0.030417 # miss rate for demand accesses
1169system.cpu0.icache.demand_miss_rate::total 0.030417 # miss rate for demand accesses
1170system.cpu0.icache.overall_miss_rate::cpu0.inst 0.030417 # miss rate for overall accesses
1171system.cpu0.icache.overall_miss_rate::total 0.030417 # miss rate for overall accesses
1172system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11326.037369 # average ReadReq miss latency
1173system.cpu0.icache.ReadReq_avg_miss_latency::total 11326.037369 # average ReadReq miss latency
1174system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11326.037369 # average overall miss latency
1175system.cpu0.icache.demand_avg_miss_latency::total 11326.037369 # average overall miss latency
1176system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11326.037369 # average overall miss latency
1177system.cpu0.icache.overall_avg_miss_latency::total 11326.037369 # average overall miss latency
1178system.cpu0.icache.blocked_cycles::no_mshrs 11168048 # number of cycles access was blocked
1179system.cpu0.icache.blocked_cycles::no_targets 1595 # number of cycles access was blocked
1180system.cpu0.icache.blocked::no_mshrs 759109 # number of cycles access was blocked
1181system.cpu0.icache.blocked::no_targets 14 # number of cycles access was blocked
1182system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.712048 # average number of cycles each access was blocked
1183system.cpu0.icache.avg_blocked_cycles::no_targets 113.928571 # average number of cycles each access was blocked
1184system.cpu0.icache.fast_writes 0 # number of fast writes performed
1185system.cpu0.icache.cache_copies 0 # number of cache copies performed
1186system.cpu0.icache.writebacks::writebacks 6005225 # number of writebacks
1187system.cpu0.icache.writebacks::total 6005225 # number of writebacks
1188system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 351442 # number of ReadReq MSHR hits
1189system.cpu0.icache.ReadReq_mshr_hits::total 351442 # number of ReadReq MSHR hits
1190system.cpu0.icache.demand_mshr_hits::cpu0.inst 351442 # number of demand (read+write) MSHR hits
1191system.cpu0.icache.demand_mshr_hits::total 351442 # number of demand (read+write) MSHR hits
1192system.cpu0.icache.overall_mshr_hits::cpu0.inst 351442 # number of overall MSHR hits
1193system.cpu0.icache.overall_mshr_hits::total 351442 # number of overall MSHR hits
1194system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6005776 # number of ReadReq MSHR misses
1195system.cpu0.icache.ReadReq_mshr_misses::total 6005776 # number of ReadReq MSHR misses
1196system.cpu0.icache.demand_mshr_misses::cpu0.inst 6005776 # number of demand (read+write) MSHR misses
1197system.cpu0.icache.demand_mshr_misses::total 6005776 # number of demand (read+write) MSHR misses
1198system.cpu0.icache.overall_mshr_misses::cpu0.inst 6005776 # number of overall MSHR misses
1199system.cpu0.icache.overall_mshr_misses::total 6005776 # number of overall MSHR misses
1200system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
1201system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable
1202system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
1203system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses
1204system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64732998531 # number of ReadReq MSHR miss cycles
1205system.cpu0.icache.ReadReq_mshr_miss_latency::total 64732998531 # number of ReadReq MSHR miss cycles
1206system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64732998531 # number of demand (read+write) MSHR miss cycles
1207system.cpu0.icache.demand_mshr_miss_latency::total 64732998531 # number of demand (read+write) MSHR miss cycles
1208system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64732998531 # number of overall MSHR miss cycles
1209system.cpu0.icache.overall_mshr_miss_latency::total 64732998531 # number of overall MSHR miss cycles
1210system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of ReadReq MSHR uncacheable cycles
1211system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939780998 # number of ReadReq MSHR uncacheable cycles
1212system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of overall MSHR uncacheable cycles
1213system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939780998 # number of overall MSHR uncacheable cycles
1214system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028736 # mshr miss rate for ReadReq accesses
1215system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028736 # mshr miss rate for ReadReq accesses
1216system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028736 # mshr miss rate for demand accesses
1217system.cpu0.icache.demand_mshr_miss_rate::total 0.028736 # mshr miss rate for demand accesses
1218system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028736 # mshr miss rate for overall accesses
1219system.cpu0.icache.overall_mshr_miss_rate::total 0.028736 # mshr miss rate for overall accesses
1220system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10778.457027 # average ReadReq mshr miss latency
1221system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10778.457027 # average ReadReq mshr miss latency
1222system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10778.457027 # average overall mshr miss latency
1223system.cpu0.icache.demand_avg_mshr_miss_latency::total 10778.457027 # average overall mshr miss latency
1224system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10778.457027 # average overall mshr miss latency
1225system.cpu0.icache.overall_avg_mshr_miss_latency::total 10778.457027 # average overall mshr miss latency
1226system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average ReadReq mshr uncacheable latency
1227system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.260132 # average ReadReq mshr uncacheable latency
1228system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average overall mshr uncacheable latency
1229system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.260132 # average overall mshr uncacheable latency
1230system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1231system.cpu0.l2cache.prefetcher.num_hwpf_issued 7993443 # number of hwpf issued
1232system.cpu0.l2cache.prefetcher.pfIdentified 8002831 # number of prefetch candidates identified
1233system.cpu0.l2cache.prefetcher.pfBufferHit 8432 # number of redundant prefetches already in prefetch queue
1234system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1235system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1236system.cpu0.l2cache.prefetcher.pfSpanPage 1016241 # number of prefetches not generated due to page crossing
1237system.cpu0.l2cache.tags.replacements 2612055 # number of replacements
1238system.cpu0.l2cache.tags.tagsinuse 15872.009303 # Cycle average of tags in use
1239system.cpu0.l2cache.tags.total_refs 17309640 # Total number of references to valid blocks.
1240system.cpu0.l2cache.tags.sampled_refs 2628171 # Sample count of references to valid blocks.
1241system.cpu0.l2cache.tags.avg_refs 6.586192 # Average number of references to valid blocks.
1242system.cpu0.l2cache.tags.warmup_cycle 3536776000 # Cycle when the warmup percentage was hit.
1243system.cpu0.l2cache.tags.occ_blocks::writebacks 14904.546668 # Average occupied blocks per requestor
1244system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 64.900343 # Average occupied blocks per requestor
1245system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 63.931766 # Average occupied blocks per requestor
1246system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 838.630526 # Average occupied blocks per requestor
1247system.cpu0.l2cache.tags.occ_percent::writebacks 0.909701 # Average percentage of cache occupancy
1248system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003961 # Average percentage of cache occupancy
1249system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003902 # Average percentage of cache occupancy
1250system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.051186 # Average percentage of cache occupancy
1251system.cpu0.l2cache.tags.occ_percent::total 0.968751 # Average percentage of cache occupancy
1252system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1148 # Occupied blocks per task id
1253system.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id
1254system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14896 # Occupied blocks per task id
1255system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id
1256system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 168 # Occupied blocks per task id
1257system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 583 # Occupied blocks per task id
1258system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 378 # Occupied blocks per task id
1259system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
1260system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 39 # Occupied blocks per task id
1261system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id
1262system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id
1263system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
1264system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1338 # Occupied blocks per task id
1265system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5968 # Occupied blocks per task id
1266system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4418 # Occupied blocks per task id
1267system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3068 # Occupied blocks per task id
1268system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.070068 # Percentage of cache occupancy per task id
1269system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id
1270system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id
1271system.cpu0.l2cache.tags.tag_accesses 407586755 # Number of tag accesses
1272system.cpu0.l2cache.tags.data_accesses 407586755 # Number of data accesses
1273system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 586295 # number of ReadReq hits
1274system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 178487 # number of ReadReq hits
1275system.cpu0.l2cache.ReadReq_hits::total 764782 # number of ReadReq hits
1276system.cpu0.l2cache.WritebackDirty_hits::writebacks 3871957 # number of WritebackDirty hits
1277system.cpu0.l2cache.WritebackDirty_hits::total 3871957 # number of WritebackDirty hits
1278system.cpu0.l2cache.WritebackClean_hits::writebacks 8013001 # number of WritebackClean hits
1279system.cpu0.l2cache.WritebackClean_hits::total 8013001 # number of WritebackClean hits
1280system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 532 # number of UpgradeReq hits
1281system.cpu0.l2cache.UpgradeReq_hits::total 532 # number of UpgradeReq hits
1282system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits
1283system.cpu0.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits
1284system.cpu0.l2cache.ReadExReq_hits::cpu0.data 876856 # number of ReadExReq hits
1285system.cpu0.l2cache.ReadExReq_hits::total 876856 # number of ReadExReq hits
1286system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5449817 # number of ReadCleanReq hits
1287system.cpu0.l2cache.ReadCleanReq_hits::total 5449817 # number of ReadCleanReq hits
1288system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2990512 # number of ReadSharedReq hits
1289system.cpu0.l2cache.ReadSharedReq_hits::total 2990512 # number of ReadSharedReq hits
1290system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 195363 # number of InvalidateReq hits
1291system.cpu0.l2cache.InvalidateReq_hits::total 195363 # number of InvalidateReq hits
1292system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 586295 # number of demand (read+write) hits
1293system.cpu0.l2cache.demand_hits::cpu0.itb.walker 178487 # number of demand (read+write) hits
1294system.cpu0.l2cache.demand_hits::cpu0.inst 5449817 # number of demand (read+write) hits
1295system.cpu0.l2cache.demand_hits::cpu0.data 3867368 # number of demand (read+write) hits
1296system.cpu0.l2cache.demand_hits::total 10081967 # number of demand (read+write) hits
1297system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 586295 # number of overall hits
1298system.cpu0.l2cache.overall_hits::cpu0.itb.walker 178487 # number of overall hits
1299system.cpu0.l2cache.overall_hits::cpu0.inst 5449817 # number of overall hits
1300system.cpu0.l2cache.overall_hits::cpu0.data 3867368 # number of overall hits
1301system.cpu0.l2cache.overall_hits::total 10081967 # number of overall hits
1302system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11719 # number of ReadReq misses
1303system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8497 # number of ReadReq misses
1304system.cpu0.l2cache.ReadReq_misses::total 20216 # number of ReadReq misses
1305system.cpu0.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses
1306system.cpu0.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses
1307system.cpu0.l2cache.WritebackClean_misses::writebacks 2 # number of WritebackClean misses
1308system.cpu0.l2cache.WritebackClean_misses::total 2 # number of WritebackClean misses
1309system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 253056 # number of UpgradeReq misses
1310system.cpu0.l2cache.UpgradeReq_misses::total 253056 # number of UpgradeReq misses
1311system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 193456 # number of SCUpgradeReq misses
1312system.cpu0.l2cache.SCUpgradeReq_misses::total 193456 # number of SCUpgradeReq misses
1313system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses
1314system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses
1315system.cpu0.l2cache.ReadExReq_misses::cpu0.data 324941 # number of ReadExReq misses
1316system.cpu0.l2cache.ReadExReq_misses::total 324941 # number of ReadExReq misses
1317system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 555934 # number of ReadCleanReq misses
1318system.cpu0.l2cache.ReadCleanReq_misses::total 555934 # number of ReadCleanReq misses
1319system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 984475 # number of ReadSharedReq misses
1320system.cpu0.l2cache.ReadSharedReq_misses::total 984475 # number of ReadSharedReq misses
1321system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 615167 # number of InvalidateReq misses
1322system.cpu0.l2cache.InvalidateReq_misses::total 615167 # number of InvalidateReq misses
1323system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11719 # number of demand (read+write) misses
1324system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8497 # number of demand (read+write) misses
1325system.cpu0.l2cache.demand_misses::cpu0.inst 555934 # number of demand (read+write) misses
1326system.cpu0.l2cache.demand_misses::cpu0.data 1309416 # number of demand (read+write) misses
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1337system.cpu0.l2cache.UpgradeReq_miss_latency::total 3400771000 # number of UpgradeReq miss cycles
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1347system.cpu0.l2cache.ReadSharedReq_miss_latency::total 43523481971 # number of ReadSharedReq miss cycles
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1349system.cpu0.l2cache.InvalidateReq_miss_latency::total 86915383999 # number of InvalidateReq miss cycles
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1363system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3871959 # number of WritebackDirty accesses(hits+misses)
1364system.cpu0.l2cache.WritebackDirty_accesses::total 3871959 # number of WritebackDirty accesses(hits+misses)
1365system.cpu0.l2cache.WritebackClean_accesses::writebacks 8013003 # number of WritebackClean accesses(hits+misses)
1366system.cpu0.l2cache.WritebackClean_accesses::total 8013003 # number of WritebackClean accesses(hits+misses)
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1368system.cpu0.l2cache.UpgradeReq_accesses::total 253588 # number of UpgradeReq accesses(hits+misses)
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1372system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses)
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1378system.cpu0.l2cache.ReadSharedReq_accesses::total 3974987 # number of ReadSharedReq accesses(hits+misses)
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1380system.cpu0.l2cache.InvalidateReq_accesses::total 810530 # number of InvalidateReq accesses(hits+misses)
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1392system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.045442 # miss rate for ReadReq accesses
1393system.cpu0.l2cache.ReadReq_miss_rate::total 0.025753 # miss rate for ReadReq accesses
1394system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses
1395system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses
1396system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses
1397system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses
1398system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.997902 # miss rate for UpgradeReq accesses
1399system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.997902 # miss rate for UpgradeReq accesses
1400system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999995 # miss rate for SCUpgradeReq accesses
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1403system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
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1405system.cpu0.l2cache.ReadExReq_miss_rate::total 0.270379 # miss rate for ReadExReq accesses
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1407system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.092567 # miss rate for ReadCleanReq accesses
1408system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.247667 # miss rate for ReadSharedReq accesses
1409system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.247667 # miss rate for ReadSharedReq accesses
1410system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.758969 # miss rate for InvalidateReq accesses
1411system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.758969 # miss rate for InvalidateReq accesses
1412system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.019597 # miss rate for demand accesses
1413system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.045442 # miss rate for demand accesses
1414system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.092567 # miss rate for demand accesses
1415system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.252940 # miss rate for demand accesses
1416system.cpu0.l2cache.demand_miss_rate::total 0.157557 # miss rate for demand accesses
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1418system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.045442 # miss rate for overall accesses
1419system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.092567 # miss rate for overall accesses
1420system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.252940 # miss rate for overall accesses
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1423system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 55040.131811 # average ReadReq miss latency
1424system.cpu0.l2cache.ReadReq_avg_miss_latency::total 51068.683221 # average ReadReq miss latency
1425system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13438.808011 # average UpgradeReq miss latency
1426system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13438.808011 # average UpgradeReq miss latency
1427system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10814.810603 # average SCUpgradeReq miss latency
1428system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10814.810603 # average SCUpgradeReq miss latency
1429system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 2070874.750000 # average SCUpgradeFailReq miss latency
1430system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 2070874.750000 # average SCUpgradeFailReq miss latency
1431system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 67824.305028 # average ReadExReq miss latency
1432system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 67824.305028 # average ReadExReq miss latency
1433system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 40813.177460 # average ReadCleanReq miss latency
1434system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 40813.177460 # average ReadCleanReq miss latency
1435system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 44209.839733 # average ReadSharedReq miss latency
1436system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 44209.839733 # average ReadSharedReq miss latency
1437system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 141287.461777 # average InvalidateReq miss latency
1438system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 141287.461777 # average InvalidateReq miss latency
1439system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 48189.137298 # average overall miss latency
1440system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 55040.131811 # average overall miss latency
1441system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 40813.177460 # average overall miss latency
1442system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 50069.939172 # average overall miss latency
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1444system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 48189.137298 # average overall miss latency
1445system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 55040.131811 # average overall miss latency
1446system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 40813.177460 # average overall miss latency
1447system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 50069.939172 # average overall miss latency
1448system.cpu0.l2cache.overall_avg_miss_latency::total 47351.414360 # average overall miss latency
1449system.cpu0.l2cache.blocked_cycles::no_mshrs 3549 # number of cycles access was blocked
1450system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1451system.cpu0.l2cache.blocked::no_mshrs 15 # number of cycles access was blocked
1452system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1453system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 236.600000 # average number of cycles each access was blocked
1454system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1455system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1456system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1457system.cpu0.l2cache.writebacks::writebacks 1633377 # number of writebacks
1458system.cpu0.l2cache.writebacks::total 1633377 # number of writebacks
1459system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 5 # number of ReadReq MSHR hits
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1461system.cpu0.l2cache.ReadReq_mshr_hits::total 195 # number of ReadReq MSHR hits
1462system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 59160 # number of ReadExReq MSHR hits
1463system.cpu0.l2cache.ReadExReq_mshr_hits::total 59160 # number of ReadExReq MSHR hits
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1466system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 6628 # number of ReadSharedReq MSHR hits
1467system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 6628 # number of ReadSharedReq MSHR hits
1468system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 15 # number of InvalidateReq MSHR hits
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1481system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8307 # number of ReadReq MSHR misses
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1483system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 2 # number of WritebackDirty MSHR misses
1484system.cpu0.l2cache.WritebackDirty_mshr_misses::total 2 # number of WritebackDirty MSHR misses
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1486system.cpu0.l2cache.WritebackClean_mshr_misses::total 2 # number of WritebackClean MSHR misses
1487system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 825638 # number of HardPFReq MSHR misses
1488system.cpu0.l2cache.HardPFReq_mshr_misses::total 825638 # number of HardPFReq MSHR misses
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1490system.cpu0.l2cache.UpgradeReq_mshr_misses::total 253056 # number of UpgradeReq MSHR misses
1491system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 193456 # number of SCUpgradeReq MSHR misses
1492system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 193456 # number of SCUpgradeReq MSHR misses
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1496system.cpu0.l2cache.ReadExReq_mshr_misses::total 265781 # number of ReadExReq MSHR misses
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1498system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 555932 # number of ReadCleanReq MSHR misses
1499system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 977847 # number of ReadSharedReq MSHR misses
1500system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 977847 # number of ReadSharedReq MSHR misses
1501system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 615152 # number of InvalidateReq MSHR misses
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1505system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 555932 # number of demand (read+write) MSHR misses
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1508system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11714 # number of overall MSHR misses
1509system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8307 # number of overall MSHR misses
1510system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 555932 # number of overall MSHR misses
1511system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1243628 # number of overall MSHR misses
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1513system.cpu0.l2cache.overall_mshr_misses::total 2645219 # number of overall MSHR misses
1514system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
1515system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32879 # number of ReadReq MSHR uncacheable
1516system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 54172 # number of ReadReq MSHR uncacheable
1517system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32981 # number of WriteReq MSHR uncacheable
1518system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32981 # number of WriteReq MSHR uncacheable
1519system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
1520system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 65860 # number of overall MSHR uncacheable misses
1521system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 87153 # number of overall MSHR uncacheable misses
1522system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 494096500 # number of ReadReq MSHR miss cycles
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1524system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 902242500 # number of ReadReq MSHR miss cycles
1525system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 60235996440 # number of HardPFReq MSHR miss cycles
1526system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 60235996440 # number of HardPFReq MSHR miss cycles
1527system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7625664494 # number of UpgradeReq MSHR miss cycles
1528system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7625664494 # number of UpgradeReq MSHR miss cycles
1529system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3888505997 # number of SCUpgradeReq MSHR miss cycles
1530system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3888505997 # number of SCUpgradeReq MSHR miss cycles
1531system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 7593499 # number of SCUpgradeFailReq MSHR miss cycles
1532system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 7593499 # number of SCUpgradeFailReq MSHR miss cycles
1533system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 16722004500 # number of ReadExReq MSHR miss cycles
1534system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 16722004500 # number of ReadExReq MSHR miss cycles
1535system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 19353809498 # number of ReadCleanReq MSHR miss cycles
1536system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 19353809498 # number of ReadCleanReq MSHR miss cycles
1537system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 37185118471 # number of ReadSharedReq MSHR miss cycles
1538system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 37185118471 # number of ReadSharedReq MSHR miss cycles
1539system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 83223435999 # number of InvalidateReq MSHR miss cycles
1540system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 83223435999 # number of InvalidateReq MSHR miss cycles
1541system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 494096500 # number of demand (read+write) MSHR miss cycles
1542system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 408146000 # number of demand (read+write) MSHR miss cycles
1543system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 19353809498 # number of demand (read+write) MSHR miss cycles
1544system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 53907122971 # number of demand (read+write) MSHR miss cycles
1545system.cpu0.l2cache.demand_mshr_miss_latency::total 74163174969 # number of demand (read+write) MSHR miss cycles
1546system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 494096500 # number of overall MSHR miss cycles
1547system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 408146000 # number of overall MSHR miss cycles
1548system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 19353809498 # number of overall MSHR miss cycles
1549system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 53907122971 # number of overall MSHR miss cycles
1550system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 60235996440 # number of overall MSHR miss cycles
1551system.cpu0.l2cache.overall_mshr_miss_latency::total 134399171409 # number of overall MSHR miss cycles
1552system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780082500 # number of ReadReq MSHR uncacheable cycles
1553system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6040017000 # number of ReadReq MSHR uncacheable cycles
1554system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8820099500 # number of ReadReq MSHR uncacheable cycles
1555system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5985704467 # number of WriteReq MSHR uncacheable cycles
1556system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5985704467 # number of WriteReq MSHR uncacheable cycles
1557system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 2780082500 # number of overall MSHR uncacheable cycles
1558system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 12025721467 # number of overall MSHR uncacheable cycles
1559system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14805803967 # number of overall MSHR uncacheable cycles
1560system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.019588 # mshr miss rate for ReadReq accesses
1561system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.044426 # mshr miss rate for ReadReq accesses
1562system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.025505 # mshr miss rate for ReadReq accesses
1563system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses
1564system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses
1565system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
1566system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
1567system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1568system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1569system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997902 # mshr miss rate for UpgradeReq accesses
1570system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997902 # mshr miss rate for UpgradeReq accesses
1571system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999995 # mshr miss rate for SCUpgradeReq accesses
1572system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses
1573system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1574system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1575system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.221153 # mshr miss rate for ReadExReq accesses
1576system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.221153 # mshr miss rate for ReadExReq accesses
1577system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092567 # mshr miss rate for ReadCleanReq accesses
1578system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092567 # mshr miss rate for ReadCleanReq accesses
1579system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.246000 # mshr miss rate for ReadSharedReq accesses
1580system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.246000 # mshr miss rate for ReadSharedReq accesses
1581system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.758950 # mshr miss rate for InvalidateReq accesses
1582system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.758950 # mshr miss rate for InvalidateReq accesses
1583system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.019588 # mshr miss rate for demand accesses
1584system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.044426 # mshr miss rate for demand accesses
1585system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092567 # mshr miss rate for demand accesses
1586system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240232 # mshr miss rate for demand accesses
1587system.cpu0.l2cache.demand_mshr_miss_rate::total 0.152043 # mshr miss rate for demand accesses
1588system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.019588 # mshr miss rate for overall accesses
1589system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.044426 # mshr miss rate for overall accesses
1590system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092567 # mshr miss rate for overall accesses
1591system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240232 # mshr miss rate for overall accesses
1592system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1593system.cpu0.l2cache.overall_mshr_miss_rate::total 0.221033 # mshr miss rate for overall accesses
1594system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 42179.998293 # average ReadReq mshr miss latency
1595system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49132.779583 # average ReadReq mshr miss latency
1596system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 45064.806953 # average ReadReq mshr miss latency
1597system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 72956.909009 # average HardPFReq mshr miss latency
1598system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 72956.909009 # average HardPFReq mshr miss latency
1599system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30134.296338 # average UpgradeReq mshr miss latency
1600system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30134.296338 # average UpgradeReq mshr miss latency
1601system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20100.208818 # average SCUpgradeReq mshr miss latency
1602system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20100.208818 # average SCUpgradeReq mshr miss latency
1603system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1898374.750000 # average SCUpgradeFailReq mshr miss latency
1604system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1898374.750000 # average SCUpgradeFailReq mshr miss latency
1605system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62916.478228 # average ReadExReq mshr miss latency
1606system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62916.478228 # average ReadExReq mshr miss latency
1607system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34813.267626 # average ReadCleanReq mshr miss latency
1608system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34813.267626 # average ReadCleanReq mshr miss latency
1609system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38027.542623 # average ReadSharedReq mshr miss latency
1610system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38027.542623 # average ReadSharedReq mshr miss latency
1611system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 135289.222825 # average InvalidateReq mshr miss latency
1612system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 135289.222825 # average InvalidateReq mshr miss latency
1613system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 42179.998293 # average overall mshr miss latency
1614system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 49132.779583 # average overall mshr miss latency
1615system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34813.267626 # average overall mshr miss latency
1616system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43346.662323 # average overall mshr miss latency
1617system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40758.380621 # average overall mshr miss latency
1618system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 42179.998293 # average overall mshr miss latency
1619system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 49132.779583 # average overall mshr miss latency
1620system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34813.267626 # average overall mshr miss latency
1621system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43346.662323 # average overall mshr miss latency
1622system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 72956.909009 # average overall mshr miss latency
1623system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50808.334361 # average overall mshr miss latency
1624system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average ReadReq mshr uncacheable latency
1625system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183704.400985 # average ReadReq mshr uncacheable latency
1626system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162816.574983 # average ReadReq mshr uncacheable latency
1627system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181489.477790 # average WriteReq mshr uncacheable latency
1628system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181489.477790 # average WriteReq mshr uncacheable latency
1629system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average overall mshr uncacheable latency
1630system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 182595.224218 # average overall mshr uncacheable latency
1631system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 169882.895219 # average overall mshr uncacheable latency
1632system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1633system.cpu0.toL2Bus.snoop_filter.tot_requests 24664078 # Total number of requests made to the snoop filter.
1634system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12671171 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1635system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2283 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1636system.cpu0.toL2Bus.snoop_filter.tot_snoops 2001831 # Total number of snoops made to the snoop filter.
1637system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2001348 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1638system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 483 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1639system.cpu0.toL2Bus.trans_dist::ReadReq 921539 # Transaction distribution
1640system.cpu0.toL2Bus.trans_dist::ReadResp 11008242 # Transaction distribution
1641system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution
1642system.cpu0.toL2Bus.trans_dist::WriteReq 32982 # Transaction distribution
1643system.cpu0.toL2Bus.trans_dist::WriteResp 32981 # Transaction distribution
1644system.cpu0.toL2Bus.trans_dist::WritebackDirty 5510686 # Transaction distribution
1645system.cpu0.toL2Bus.trans_dist::WritebackClean 8013020 # Transaction distribution
1646system.cpu0.toL2Bus.trans_dist::CleanEvict 2592060 # Transaction distribution
1647system.cpu0.toL2Bus.trans_dist::HardPFReq 1056695 # Transaction distribution
1648system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution
1649system.cpu0.toL2Bus.trans_dist::UpgradeReq 478539 # Transaction distribution
1650system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 354281 # Transaction distribution
1651system.cpu0.toL2Bus.trans_dist::UpgradeResp 520874 # Transaction distribution
1652system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 100 # Transaction distribution
1653system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 211 # Transaction distribution
1654system.cpu0.toL2Bus.trans_dist::ReadExReq 1281558 # Transaction distribution
1655system.cpu0.toL2Bus.trans_dist::ReadExResp 1212477 # Transaction distribution
1656system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6005776 # Transaction distribution
1657system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4986753 # Transaction distribution
1658system.cpu0.toL2Bus.trans_dist::InvalidateReq 818816 # Transaction distribution
1659system.cpu0.toL2Bus.trans_dist::InvalidateResp 810530 # Transaction distribution
1660system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18057865 # Packet count per connected master and slave (bytes)
1661system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19072336 # Packet count per connected master and slave (bytes)
1662system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 391759 # Packet count per connected master and slave (bytes)
1663system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1260604 # Packet count per connected master and slave (bytes)
1664system.cpu0.toL2Bus.pkt_count::total 38782564 # Packet count per connected master and slave (bytes)
1665system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 768948880 # Cumulative packet size per connected master and slave (bytes)
1666system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 715383853 # Cumulative packet size per connected master and slave (bytes)
1667system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1495872 # Cumulative packet size per connected master and slave (bytes)
1668system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4784112 # Cumulative packet size per connected master and slave (bytes)
1669system.cpu0.toL2Bus.pkt_size::total 1490612717 # Cumulative packet size per connected master and slave (bytes)
1670system.cpu0.toL2Bus.snoops 7046224 # Total snoops (count)
1671system.cpu0.toL2Bus.snoop_fanout::samples 20167865 # Request fanout histogram
1672system.cpu0.toL2Bus.snoop_fanout::mean 0.116092 # Request fanout histogram
1673system.cpu0.toL2Bus.snoop_fanout::stdev 0.320411 # Request fanout histogram
1674system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1675system.cpu0.toL2Bus.snoop_fanout::0 17827011 88.39% 88.39% # Request fanout histogram
1676system.cpu0.toL2Bus.snoop_fanout::1 2340371 11.60% 100.00% # Request fanout histogram
1677system.cpu0.toL2Bus.snoop_fanout::2 483 0.00% 100.00% # Request fanout histogram
1678system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1679system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1680system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1681system.cpu0.toL2Bus.snoop_fanout::total 20167865 # Request fanout histogram
1682system.cpu0.toL2Bus.reqLayer0.occupancy 24544733928 # Layer occupancy (ticks)
1683system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1684system.cpu0.toL2Bus.snoopLayer0.occupancy 212322671 # Layer occupancy (ticks)
1685system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1686system.cpu0.toL2Bus.respLayer0.occupancy 9035902540 # Layer occupancy (ticks)
1687system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1688system.cpu0.toL2Bus.respLayer1.occupancy 8451585698 # Layer occupancy (ticks)
1689system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1690system.cpu0.toL2Bus.respLayer2.occupancy 205222100 # Layer occupancy (ticks)
1691system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1692system.cpu0.toL2Bus.respLayer3.occupancy 663162345 # Layer occupancy (ticks)
1693system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1694system.cpu1.branchPred.lookups 136771271 # Number of BP lookups
1695system.cpu1.branchPred.condPredicted 91615454 # Number of conditional branches predicted
1696system.cpu1.branchPred.condIncorrect 6699408 # Number of conditional branches incorrect
1697system.cpu1.branchPred.BTBLookups 96252672 # Number of BTB lookups
1698system.cpu1.branchPred.BTBHits 62838118 # Number of BTB hits
1699system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1700system.cpu1.branchPred.BTBHitPct 65.284544 # BTB Hit Percentage
1701system.cpu1.branchPred.usedRAS 18248077 # Number of times the RAS was used to get a target.
1702system.cpu1.branchPred.RASInCorrect 178326 # Number of incorrect RAS predictions.
1703system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1704system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1705system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1706system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1707system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1708system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1709system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1710system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

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1724system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1725system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1726system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1727system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1728system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1729system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1730system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1731system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1732system.cpu1.dtb.walker.walks 587464 # Table walker walks requested
1733system.cpu1.dtb.walker.walksLong 587464 # Table walker walks initiated with long descriptors
1734system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12287 # Level at which table walker walks with long descriptors terminate
1735system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93954 # Level at which table walker walks with long descriptors terminate
1736system.cpu1.dtb.walker.walksSquashedBefore 273243 # Table walks squashed before starting
1737system.cpu1.dtb.walker.walkWaitTime::samples 314221 # Table walker wait (enqueue to first request) latency
1738system.cpu1.dtb.walker.walkWaitTime::mean 2460.273184 # Table walker wait (enqueue to first request) latency
1739system.cpu1.dtb.walker.walkWaitTime::stdev 14941.067276 # Table walker wait (enqueue to first request) latency
1740system.cpu1.dtb.walker.walkWaitTime::0-65535 311748 99.21% 99.21% # Table walker wait (enqueue to first request) latency
1741system.cpu1.dtb.walker.walkWaitTime::65536-131071 1254 0.40% 99.61% # Table walker wait (enqueue to first request) latency
1742system.cpu1.dtb.walker.walkWaitTime::131072-196607 917 0.29% 99.90% # Table walker wait (enqueue to first request) latency
1743system.cpu1.dtb.walker.walkWaitTime::196608-262143 161 0.05% 99.96% # Table walker wait (enqueue to first request) latency
1744system.cpu1.dtb.walker.walkWaitTime::262144-327679 52 0.02% 99.97% # Table walker wait (enqueue to first request) latency
1745system.cpu1.dtb.walker.walkWaitTime::327680-393215 63 0.02% 99.99% # Table walker wait (enqueue to first request) latency
1746system.cpu1.dtb.walker.walkWaitTime::393216-458751 18 0.01% 100.00% # Table walker wait (enqueue to first request) latency
1747system.cpu1.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1748system.cpu1.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1749system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1750system.cpu1.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1751system.cpu1.dtb.walker.walkWaitTime::total 314221 # Table walker wait (enqueue to first request) latency
1752system.cpu1.dtb.walker.walkCompletionTime::samples 302969 # Table walker service (enqueue to completion) latency
1753system.cpu1.dtb.walker.walkCompletionTime::mean 20764.791117 # Table walker service (enqueue to completion) latency
1754system.cpu1.dtb.walker.walkCompletionTime::gmean 17394.458301 # Table walker service (enqueue to completion) latency
1755system.cpu1.dtb.walker.walkCompletionTime::stdev 22544.227052 # Table walker service (enqueue to completion) latency
1756system.cpu1.dtb.walker.walkCompletionTime::0-65535 299168 98.75% 98.75% # Table walker service (enqueue to completion) latency
1757system.cpu1.dtb.walker.walkCompletionTime::65536-131071 939 0.31% 99.06% # Table walker service (enqueue to completion) latency
1758system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1914 0.63% 99.69% # Table walker service (enqueue to completion) latency
1759system.cpu1.dtb.walker.walkCompletionTime::196608-262143 156 0.05% 99.74% # Table walker service (enqueue to completion) latency
1760system.cpu1.dtb.walker.walkCompletionTime::262144-327679 510 0.17% 99.91% # Table walker service (enqueue to completion) latency
1761system.cpu1.dtb.walker.walkCompletionTime::327680-393215 121 0.04% 99.95% # Table walker service (enqueue to completion) latency
1762system.cpu1.dtb.walker.walkCompletionTime::393216-458751 110 0.04% 99.98% # Table walker service (enqueue to completion) latency
1763system.cpu1.dtb.walker.walkCompletionTime::458752-524287 28 0.01% 99.99% # Table walker service (enqueue to completion) latency
1764system.cpu1.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 99.99% # Table walker service (enqueue to completion) latency
1765system.cpu1.dtb.walker.walkCompletionTime::589824-655359 9 0.00% 100.00% # Table walker service (enqueue to completion) latency
1766system.cpu1.dtb.walker.walkCompletionTime::655360-720895 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
1767system.cpu1.dtb.walker.walkCompletionTime::total 302969 # Table walker service (enqueue to completion) latency
1768system.cpu1.dtb.walker.walksPending::samples 477883045620 # Table walker pending requests distribution
1769system.cpu1.dtb.walker.walksPending::mean 0.598615 # Table walker pending requests distribution
1770system.cpu1.dtb.walker.walksPending::stdev 0.553378 # Table walker pending requests distribution
1771system.cpu1.dtb.walker.walksPending::0-1 476579478620 99.73% 99.73% # Table walker pending requests distribution
1772system.cpu1.dtb.walker.walksPending::2-3 689019500 0.14% 99.87% # Table walker pending requests distribution
1773system.cpu1.dtb.walker.walksPending::4-5 279828500 0.06% 99.93% # Table walker pending requests distribution
1774system.cpu1.dtb.walker.walksPending::6-7 139297000 0.03% 99.96% # Table walker pending requests distribution
1775system.cpu1.dtb.walker.walksPending::8-9 94668000 0.02% 99.98% # Table walker pending requests distribution
1776system.cpu1.dtb.walker.walksPending::10-11 55014500 0.01% 99.99% # Table walker pending requests distribution
1777system.cpu1.dtb.walker.walksPending::12-13 17997000 0.00% 99.99% # Table walker pending requests distribution
1778system.cpu1.dtb.walker.walksPending::14-15 27375000 0.01% 100.00% # Table walker pending requests distribution
1779system.cpu1.dtb.walker.walksPending::16-17 352000 0.00% 100.00% # Table walker pending requests distribution
1780system.cpu1.dtb.walker.walksPending::18-19 15500 0.00% 100.00% # Table walker pending requests distribution
1781system.cpu1.dtb.walker.walksPending::total 477883045620 # Table walker pending requests distribution
1782system.cpu1.dtb.walker.walkPageSizes::4K 93955 88.43% 88.43% # Table walker page sizes translated
1783system.cpu1.dtb.walker.walkPageSizes::2M 12287 11.57% 100.00% # Table walker page sizes translated
1784system.cpu1.dtb.walker.walkPageSizes::total 106242 # Table walker page sizes translated
1785system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 587464 # Table walker requests started/completed, data/inst
1786system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1787system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 587464 # Table walker requests started/completed, data/inst
1788system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 106242 # Table walker requests started/completed, data/inst
1789system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1790system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 106242 # Table walker requests started/completed, data/inst
1791system.cpu1.dtb.walker.walkRequestOrigin::total 693706 # Table walker requests started/completed, data/inst
1792system.cpu1.dtb.inst_hits 0 # ITB inst hits
1793system.cpu1.dtb.inst_misses 0 # ITB inst misses
1794system.cpu1.dtb.read_hits 101377575 # DTB read hits
1795system.cpu1.dtb.read_misses 401827 # DTB read misses
1796system.cpu1.dtb.write_hits 83690670 # DTB write hits
1797system.cpu1.dtb.write_misses 185637 # DTB write misses
1798system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1799system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1800system.cpu1.dtb.flush_tlb_mva_asid 44695 # Number of times TLB was flushed by MVA & ASID
1801system.cpu1.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
1802system.cpu1.dtb.flush_entries 39959 # Number of entries that have been flushed from TLB
1803system.cpu1.dtb.align_faults 225 # Number of TLB faults due to alignment restrictions
1804system.cpu1.dtb.prefetch_faults 6406 # Number of TLB faults due to prefetch
1805system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1806system.cpu1.dtb.perms_faults 43965 # Number of TLB faults due to permissions restrictions
1807system.cpu1.dtb.read_accesses 101779402 # DTB read accesses
1808system.cpu1.dtb.write_accesses 83876307 # DTB write accesses
1809system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1810system.cpu1.dtb.hits 185068245 # DTB hits
1811system.cpu1.dtb.misses 587464 # DTB misses
1812system.cpu1.dtb.accesses 185655709 # DTB accesses
1813system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1814system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1815system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1816system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1817system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1818system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1819system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1820system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1834system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1835system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1836system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1837system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1838system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1839system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1840system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1841system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1842system.cpu1.itb.walker.walks 92227 # Table walker walks requested
1843system.cpu1.itb.walker.walksLong 92227 # Table walker walks initiated with long descriptors
1844system.cpu1.itb.walker.walksLongTerminationLevel::Level2 973 # Level at which table walker walks with long descriptors terminate
1845system.cpu1.itb.walker.walksLongTerminationLevel::Level3 66704 # Level at which table walker walks with long descriptors terminate
1846system.cpu1.itb.walker.walksSquashedBefore 11080 # Table walks squashed before starting
1847system.cpu1.itb.walker.walkWaitTime::samples 81147 # Table walker wait (enqueue to first request) latency
1848system.cpu1.itb.walker.walkWaitTime::mean 1613.670253 # Table walker wait (enqueue to first request) latency
1849system.cpu1.itb.walker.walkWaitTime::stdev 12323.334174 # Table walker wait (enqueue to first request) latency
1850system.cpu1.itb.walker.walkWaitTime::0-32767 80305 98.96% 98.96% # Table walker wait (enqueue to first request) latency
1851system.cpu1.itb.walker.walkWaitTime::32768-65535 403 0.50% 99.46% # Table walker wait (enqueue to first request) latency
1852system.cpu1.itb.walker.walkWaitTime::65536-98303 31 0.04% 99.50% # Table walker wait (enqueue to first request) latency
1853system.cpu1.itb.walker.walkWaitTime::98304-131071 81 0.10% 99.60% # Table walker wait (enqueue to first request) latency
1854system.cpu1.itb.walker.walkWaitTime::131072-163839 234 0.29% 99.89% # Table walker wait (enqueue to first request) latency
1855system.cpu1.itb.walker.walkWaitTime::163840-196607 59 0.07% 99.96% # Table walker wait (enqueue to first request) latency
1856system.cpu1.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.97% # Table walker wait (enqueue to first request) latency
1857system.cpu1.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency
1858system.cpu1.itb.walker.walkWaitTime::262144-294911 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency
1859system.cpu1.itb.walker.walkWaitTime::294912-327679 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency
1860system.cpu1.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1861system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1862system.cpu1.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1863system.cpu1.itb.walker.walkWaitTime::total 81147 # Table walker wait (enqueue to first request) latency
1864system.cpu1.itb.walker.walkCompletionTime::samples 78757 # Table walker service (enqueue to completion) latency
1865system.cpu1.itb.walker.walkCompletionTime::mean 26873.185876 # Table walker service (enqueue to completion) latency
1866system.cpu1.itb.walker.walkCompletionTime::gmean 22946.544582 # Table walker service (enqueue to completion) latency
1867system.cpu1.itb.walker.walkCompletionTime::stdev 27397.779974 # Table walker service (enqueue to completion) latency
1868system.cpu1.itb.walker.walkCompletionTime::0-65535 76775 97.48% 97.48% # Table walker service (enqueue to completion) latency
1869system.cpu1.itb.walker.walkCompletionTime::65536-131071 153 0.19% 97.68% # Table walker service (enqueue to completion) latency
1870system.cpu1.itb.walker.walkCompletionTime::131072-196607 1519 1.93% 99.61% # Table walker service (enqueue to completion) latency
1871system.cpu1.itb.walker.walkCompletionTime::196608-262143 117 0.15% 99.75% # Table walker service (enqueue to completion) latency
1872system.cpu1.itb.walker.walkCompletionTime::262144-327679 110 0.14% 99.89% # Table walker service (enqueue to completion) latency
1873system.cpu1.itb.walker.walkCompletionTime::327680-393215 35 0.04% 99.94% # Table walker service (enqueue to completion) latency
1874system.cpu1.itb.walker.walkCompletionTime::393216-458751 36 0.05% 99.98% # Table walker service (enqueue to completion) latency
1875system.cpu1.itb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
1876system.cpu1.itb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
1877system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1878system.cpu1.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1879system.cpu1.itb.walker.walkCompletionTime::total 78757 # Table walker service (enqueue to completion) latency
1880system.cpu1.itb.walker.walksPending::samples 434901307160 # Table walker pending requests distribution
1881system.cpu1.itb.walker.walksPending::mean 0.857521 # Table walker pending requests distribution
1882system.cpu1.itb.walker.walksPending::stdev 0.349757 # Table walker pending requests distribution
1883system.cpu1.itb.walker.walksPending::0 61992873300 14.25% 14.25% # Table walker pending requests distribution
1884system.cpu1.itb.walker.walksPending::1 372883353360 85.74% 99.99% # Table walker pending requests distribution
1885system.cpu1.itb.walker.walksPending::2 22166000 0.01% 100.00% # Table walker pending requests distribution
1886system.cpu1.itb.walker.walksPending::3 2474500 0.00% 100.00% # Table walker pending requests distribution
1887system.cpu1.itb.walker.walksPending::4 253500 0.00% 100.00% # Table walker pending requests distribution
1888system.cpu1.itb.walker.walksPending::5 186500 0.00% 100.00% # Table walker pending requests distribution
1889system.cpu1.itb.walker.walksPending::total 434901307160 # Table walker pending requests distribution
1890system.cpu1.itb.walker.walkPageSizes::4K 66704 98.56% 98.56% # Table walker page sizes translated
1891system.cpu1.itb.walker.walkPageSizes::2M 973 1.44% 100.00% # Table walker page sizes translated
1892system.cpu1.itb.walker.walkPageSizes::total 67677 # Table walker page sizes translated
1893system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1894system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 92227 # Table walker requests started/completed, data/inst
1895system.cpu1.itb.walker.walkRequestOrigin_Requested::total 92227 # Table walker requests started/completed, data/inst
1896system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1897system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 67677 # Table walker requests started/completed, data/inst
1898system.cpu1.itb.walker.walkRequestOrigin_Completed::total 67677 # Table walker requests started/completed, data/inst
1899system.cpu1.itb.walker.walkRequestOrigin::total 159904 # Table walker requests started/completed, data/inst
1900system.cpu1.itb.inst_hits 215454990 # ITB inst hits
1901system.cpu1.itb.inst_misses 92227 # ITB inst misses
1902system.cpu1.itb.read_hits 0 # DTB read hits
1903system.cpu1.itb.read_misses 0 # DTB read misses
1904system.cpu1.itb.write_hits 0 # DTB write hits
1905system.cpu1.itb.write_misses 0 # DTB write misses
1906system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1907system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1908system.cpu1.itb.flush_tlb_mva_asid 44695 # Number of times TLB was flushed by MVA & ASID
1909system.cpu1.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
1910system.cpu1.itb.flush_entries 28858 # Number of entries that have been flushed from TLB
1911system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1912system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1913system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1914system.cpu1.itb.perms_faults 231246 # Number of TLB faults due to permissions restrictions
1915system.cpu1.itb.read_accesses 0 # DTB read accesses
1916system.cpu1.itb.write_accesses 0 # DTB write accesses
1917system.cpu1.itb.inst_accesses 215547217 # ITB inst accesses
1918system.cpu1.itb.hits 215454990 # DTB hits
1919system.cpu1.itb.misses 92227 # DTB misses
1920system.cpu1.itb.accesses 215547217 # DTB accesses
1921system.cpu1.numCycles 759155378 # number of cpu cycles simulated
1922system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1923system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1924system.cpu1.fetch.icacheStallCycles 87128814 # Number of cycles fetch is stalled on an Icache miss
1925system.cpu1.fetch.Insts 606063748 # Number of instructions fetch has processed
1926system.cpu1.fetch.Branches 136771271 # Number of branches that fetch encountered
1927system.cpu1.fetch.predictedBranches 81086195 # Number of branches that fetch has predicted taken
1928system.cpu1.fetch.Cycles 630037393 # Number of cycles fetch has run and was not squashing or blocked
1929system.cpu1.fetch.SquashCycles 14425462 # Number of cycles fetch has spent squashing
1930system.cpu1.fetch.TlbCycles 2172177 # Number of cycles fetch has spent waiting for tlb
1931system.cpu1.fetch.MiscStallCycles 325931 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1932system.cpu1.fetch.PendingTrapStallCycles 6736887 # Number of stall cycles due to pending traps
1933system.cpu1.fetch.PendingQuiesceStallCycles 827556 # Number of stall cycles due to pending quiesce instructions
1934system.cpu1.fetch.IcacheWaitRetryStallCycles 851702 # Number of stall cycles due to full MSHR
1935system.cpu1.fetch.CacheLines 215200214 # Number of cache lines fetched
1936system.cpu1.fetch.IcacheSquashes 1679756 # Number of outstanding Icache misses that were squashed
1937system.cpu1.fetch.ItlbSquashes 31517 # Number of outstanding ITLB misses that were squashed
1938system.cpu1.fetch.rateDist::samples 735293191 # Number of instructions fetched each cycle (Total)
1939system.cpu1.fetch.rateDist::mean 0.969104 # Number of instructions fetched each cycle (Total)
1940system.cpu1.fetch.rateDist::stdev 1.218230 # Number of instructions fetched each cycle (Total)
1941system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1942system.cpu1.fetch.rateDist::0 394185812 53.61% 53.61% # Number of instructions fetched each cycle (Total)
1943system.cpu1.fetch.rateDist::1 132782093 18.06% 71.67% # Number of instructions fetched each cycle (Total)
1944system.cpu1.fetch.rateDist::2 45182528 6.14% 77.81% # Number of instructions fetched each cycle (Total)
1945system.cpu1.fetch.rateDist::3 163142758 22.19% 100.00% # Number of instructions fetched each cycle (Total)
1946system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1947system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1948system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
1949system.cpu1.fetch.rateDist::total 735293191 # Number of instructions fetched each cycle (Total)
1950system.cpu1.fetch.branchRate 0.180162 # Number of branch fetches per cycle
1951system.cpu1.fetch.rate 0.798340 # Number of inst fetches per cycle
1952system.cpu1.decode.IdleCycles 105275670 # Number of cycles decode is idle
1953system.cpu1.decode.BlockedCycles 361149345 # Number of cycles decode is blocked
1954system.cpu1.decode.RunCycles 225652352 # Number of cycles decode is running
1955system.cpu1.decode.UnblockCycles 38094367 # Number of cycles decode is unblocking
1956system.cpu1.decode.SquashCycles 5121457 # Number of cycles decode is squashing
1957system.cpu1.decode.BranchResolved 19322389 # Number of times decode resolved a branch
1958system.cpu1.decode.BranchMispred 2132865 # Number of times decode detected a branch misprediction
1959system.cpu1.decode.DecodedInsts 630175710 # Number of instructions handled by decode
1960system.cpu1.decode.SquashedInsts 23074598 # Number of squashed instructions handled by decode
1961system.cpu1.rename.SquashCycles 5121457 # Number of cycles rename is squashing
1962system.cpu1.rename.IdleCycles 140790232 # Number of cycles rename is idle
1963system.cpu1.rename.BlockCycles 54705867 # Number of cycles rename is blocking
1964system.cpu1.rename.serializeStallCycles 237824642 # count of cycles rename stalled for serializing inst
1965system.cpu1.rename.RunCycles 227778492 # Number of cycles rename is running
1966system.cpu1.rename.UnblockCycles 69072501 # Number of cycles rename is unblocking
1967system.cpu1.rename.RenamedInsts 613335461 # Number of instructions processed by rename
1968system.cpu1.rename.SquashedInsts 5878562 # Number of squashed instructions processed by rename
1969system.cpu1.rename.ROBFullEvents 11068691 # Number of times rename has blocked due to ROB full
1970system.cpu1.rename.IQFullEvents 265258 # Number of times rename has blocked due to IQ full
1971system.cpu1.rename.LQFullEvents 344448 # Number of times rename has blocked due to LQ full
1972system.cpu1.rename.SQFullEvents 33464644 # Number of times rename has blocked due to SQ full
1973system.cpu1.rename.FullRegisterEvents 12708 # Number of times there has been no free registers
1974system.cpu1.rename.RenamedOperands 582683755 # Number of destination operands rename has renamed
1975system.cpu1.rename.RenameLookups 946463821 # Number of register rename lookups that rename has made
1976system.cpu1.rename.int_rename_lookups 725287459 # Number of integer rename lookups
1977system.cpu1.rename.fp_rename_lookups 802163 # Number of floating rename lookups
1978system.cpu1.rename.CommittedMaps 525337621 # Number of HB maps that are committed
1979system.cpu1.rename.UndoneMaps 57346134 # Number of HB maps that are undone due to squashing
1980system.cpu1.rename.serializingInsts 16349116 # count of serializing insts renamed
1981system.cpu1.rename.tempSerializingInsts 14383675 # count of temporary serializing insts renamed
1982system.cpu1.rename.skidInsts 76724538 # count of insts added to the skid buffer
1983system.cpu1.memDep0.insertedLoads 101292205 # Number of loads inserted to the mem dependence unit.
1984system.cpu1.memDep0.insertedStores 87094038 # Number of stores inserted to the mem dependence unit.
1985system.cpu1.memDep0.conflictingLoads 9603338 # Number of conflicting loads.
1986system.cpu1.memDep0.conflictingStores 8276902 # Number of conflicting stores.
1987system.cpu1.iq.iqInstsAdded 590341476 # Number of instructions added to the IQ (excludes non-spec)
1988system.cpu1.iq.iqNonSpecInstsAdded 16600780 # Number of non-speculative instructions added to the IQ
1989system.cpu1.iq.iqInstsIssued 596033149 # Number of instructions issued
1990system.cpu1.iq.iqSquashedInstsIssued 2703684 # Number of squashed instructions issued
1991system.cpu1.iq.iqSquashedInstsExamined 54441407 # Number of squashed instructions iterated over during squash; mainly for profiling
1992system.cpu1.iq.iqSquashedOperandsExamined 34942140 # Number of squashed operands that are examined and possibly removed from graph
1993system.cpu1.iq.iqSquashedNonSpecRemoved 296921 # Number of squashed non-spec instructions that were removed
1994system.cpu1.iq.issued_per_cycle::samples 735293191 # Number of insts issued each cycle
1995system.cpu1.iq.issued_per_cycle::mean 0.810606 # Number of insts issued each cycle
1996system.cpu1.iq.issued_per_cycle::stdev 1.063717 # Number of insts issued each cycle
1997system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1998system.cpu1.iq.issued_per_cycle::0 408888874 55.61% 55.61% # Number of insts issued each cycle
1999system.cpu1.iq.issued_per_cycle::1 138685440 18.86% 74.47% # Number of insts issued each cycle
2000system.cpu1.iq.issued_per_cycle::2 113812160 15.48% 89.95% # Number of insts issued each cycle
2001system.cpu1.iq.issued_per_cycle::3 65908523 8.96% 98.91% # Number of insts issued each cycle
2002system.cpu1.iq.issued_per_cycle::4 7993150 1.09% 100.00% # Number of insts issued each cycle
2003system.cpu1.iq.issued_per_cycle::5 5044 0.00% 100.00% # Number of insts issued each cycle
2004system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
2005system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
2006system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
2007system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
2008system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2009system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2010system.cpu1.iq.issued_per_cycle::total 735293191 # Number of insts issued each cycle
2011system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2012system.cpu1.iq.fu_full::IntAlu 59894815 43.89% 43.89% # attempts to use FU when none available
2013system.cpu1.iq.fu_full::IntMult 54223 0.04% 43.93% # attempts to use FU when none available
2014system.cpu1.iq.fu_full::IntDiv 19415 0.01% 43.94% # attempts to use FU when none available
2015system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.94% # attempts to use FU when none available
2016system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.94% # attempts to use FU when none available
2017system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.94% # attempts to use FU when none available
2018system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.94% # attempts to use FU when none available
2019system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.94% # attempts to use FU when none available
2020system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.94% # attempts to use FU when none available
2021system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.94% # attempts to use FU when none available
2022system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.94% # attempts to use FU when none available
2023system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.94% # attempts to use FU when none available
2024system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.94% # attempts to use FU when none available
2025system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.94% # attempts to use FU when none available
2026system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.94% # attempts to use FU when none available
2027system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.94% # attempts to use FU when none available
2028system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.94% # attempts to use FU when none available
2029system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.94% # attempts to use FU when none available
2030system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.94% # attempts to use FU when none available
2031system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.94% # attempts to use FU when none available
2032system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.94% # attempts to use FU when none available
2033system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.94% # attempts to use FU when none available
2034system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.94% # attempts to use FU when none available
2035system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.94% # attempts to use FU when none available
2036system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.94% # attempts to use FU when none available
2037system.cpu1.iq.fu_full::SimdFloatMisc 13 0.00% 43.94% # attempts to use FU when none available
2038system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.94% # attempts to use FU when none available
2039system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.94% # attempts to use FU when none available
2040system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.94% # attempts to use FU when none available
2041system.cpu1.iq.fu_full::MemRead 36698954 26.89% 70.83% # attempts to use FU when none available
2042system.cpu1.iq.fu_full::MemWrite 39811710 29.17% 100.00% # attempts to use FU when none available
2043system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
2044system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2045system.cpu1.iq.FU_type_0::No_OpClass 40 0.00% 0.00% # Type of FU issued
2046system.cpu1.iq.FU_type_0::IntAlu 405160238 67.98% 67.98% # Type of FU issued
2047system.cpu1.iq.FU_type_0::IntMult 1323587 0.22% 68.20% # Type of FU issued
2048system.cpu1.iq.FU_type_0::IntDiv 73165 0.01% 68.21% # Type of FU issued
2049system.cpu1.iq.FU_type_0::FloatAdd 6 0.00% 68.21% # Type of FU issued
2050system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued
2051system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued
2052system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued
2053system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.21% # Type of FU issued
2054system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued
2055system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued
2056system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued
2057system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued
2058system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued
2059system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued
2060system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.21% # Type of FU issued
2061system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued
2062system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued
2063system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.21% # Type of FU issued
2064system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued
2065system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued
2066system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.21% # Type of FU issued
2067system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued
2068system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.21% # Type of FU issued
2069system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.21% # Type of FU issued
2070system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued
2071system.cpu1.iq.FU_type_0::SimdFloatMisc 83635 0.01% 68.22% # Type of FU issued
2072system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued
2073system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued
2074system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued
2075system.cpu1.iq.FU_type_0::MemRead 104404803 17.52% 85.74% # Type of FU issued
2076system.cpu1.iq.FU_type_0::MemWrite 84987627 14.26% 100.00% # Type of FU issued
2077system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
2078system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2079system.cpu1.iq.FU_type_0::total 596033149 # Type of FU issued
2080system.cpu1.iq.rate 0.785127 # Inst issue rate
2081system.cpu1.iq.fu_busy_cnt 136479130 # FU busy when requested
2082system.cpu1.iq.fu_busy_rate 0.228979 # FU busy rate (busy events/executed inst)
2083system.cpu1.iq.int_inst_queue_reads 2065187396 # Number of integer instruction queue reads
2084system.cpu1.iq.int_inst_queue_writes 660997777 # Number of integer instruction queue writes
2085system.cpu1.iq.int_inst_queue_wakeup_accesses 578833453 # Number of integer instruction queue wakeup accesses
2086system.cpu1.iq.fp_inst_queue_reads 1354907 # Number of floating instruction queue reads
2087system.cpu1.iq.fp_inst_queue_writes 550149 # Number of floating instruction queue writes
2088system.cpu1.iq.fp_inst_queue_wakeup_accesses 503649 # Number of floating instruction queue wakeup accesses
2089system.cpu1.iq.int_alu_accesses 731674033 # Number of integer alu accesses
2090system.cpu1.iq.fp_alu_accesses 838206 # Number of floating point alu accesses
2091system.cpu1.iew.lsq.thread0.forwLoads 2717332 # Number of loads that had data forwarded from stores
2092system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2093system.cpu1.iew.lsq.thread0.squashedLoads 12501770 # Number of loads squashed
2094system.cpu1.iew.lsq.thread0.ignoredResponses 16793 # Number of memory responses ignored because the instruction is squashed
2095system.cpu1.iew.lsq.thread0.memOrderViolation 165759 # Number of memory ordering violations
2096system.cpu1.iew.lsq.thread0.squashedStores 5982611 # Number of stores squashed
2097system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2098system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2099system.cpu1.iew.lsq.thread0.rescheduledLoads 2801463 # Number of loads that were rescheduled
2100system.cpu1.iew.lsq.thread0.cacheBlocked 4362378 # Number of times an access to memory failed due to the cache being blocked
2101system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2102system.cpu1.iew.iewSquashCycles 5121457 # Number of cycles IEW is squashing
2103system.cpu1.iew.iewBlockCycles 6701200 # Number of cycles IEW is blocking
2104system.cpu1.iew.iewUnblockCycles 2456436 # Number of cycles IEW is unblocking
2105system.cpu1.iew.iewDispatchedInsts 607072203 # Number of instructions dispatched to IQ
2106system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2107system.cpu1.iew.iewDispLoadInsts 101292205 # Number of dispatched load instructions
2108system.cpu1.iew.iewDispStoreInsts 87094038 # Number of dispatched store instructions
2109system.cpu1.iew.iewDispNonSpecInsts 14166456 # Number of dispatched non-speculative instructions
2110system.cpu1.iew.iewIQFullEvents 66987 # Number of times the IQ has become full, causing a stall
2111system.cpu1.iew.iewLSQFullEvents 2327340 # Number of times the LSQ has become full, causing a stall
2112system.cpu1.iew.memOrderViolationEvents 165759 # Number of memory order violations
2113system.cpu1.iew.predictedTakenIncorrect 2053658 # Number of branches that were predicted taken incorrectly
2114system.cpu1.iew.predictedNotTakenIncorrect 2840126 # Number of branches that were predicted not taken incorrectly
2115system.cpu1.iew.branchMispredicts 4893784 # Number of branch mispredicts detected at execute
2116system.cpu1.iew.iewExecutedInsts 588333719 # Number of executed instructions
2117system.cpu1.iew.iewExecLoadInsts 101371104 # Number of load instructions executed
2118system.cpu1.iew.iewExecSquashedInsts 7124424 # Number of squashed instructions skipped in execute
2119system.cpu1.iew.exec_swp 0 # number of swp insts executed
2120system.cpu1.iew.exec_nop 129947 # number of nop insts executed
2121system.cpu1.iew.exec_refs 185062017 # number of memory reference insts executed
2122system.cpu1.iew.exec_branches 110209905 # Number of branches executed
2123system.cpu1.iew.exec_stores 83690913 # Number of stores executed
2124system.cpu1.iew.exec_rate 0.774985 # Inst execution rate
2125system.cpu1.iew.wb_sent 580075402 # cumulative count of insts sent to commit
2126system.cpu1.iew.wb_count 579337102 # cumulative count of insts written-back
2127system.cpu1.iew.wb_producers 280158358 # num instructions producing a value
2128system.cpu1.iew.wb_consumers 458852190 # num instructions consuming a value
2129system.cpu1.iew.wb_rate 0.763134 # insts written-back per cycle
2130system.cpu1.iew.wb_fanout 0.610563 # average fanout of values written-back
2131system.cpu1.commit.commitSquashedInsts 47675638 # The number of squashed insts skipped by commit
2132system.cpu1.commit.commitNonSpecStalls 16303859 # The number of times commit has been forced to stall to communicate backwards
2133system.cpu1.commit.branchMispredicts 4608134 # The number of times a branch was mispredicted
2134system.cpu1.commit.committed_per_cycle::samples 726275789 # Number of insts commited each cycle
2135system.cpu1.commit.committed_per_cycle::mean 0.760731 # Number of insts commited each cycle
2136system.cpu1.commit.committed_per_cycle::stdev 1.562013 # Number of insts commited each cycle
2137system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2138system.cpu1.commit.committed_per_cycle::0 483439526 66.56% 66.56% # Number of insts commited each cycle
2139system.cpu1.commit.committed_per_cycle::1 126884990 17.47% 84.03% # Number of insts commited each cycle
2140system.cpu1.commit.committed_per_cycle::2 53284484 7.34% 91.37% # Number of insts commited each cycle
2141system.cpu1.commit.committed_per_cycle::3 17968651 2.47% 93.85% # Number of insts commited each cycle
2142system.cpu1.commit.committed_per_cycle::4 12727519 1.75% 95.60% # Number of insts commited each cycle
2143system.cpu1.commit.committed_per_cycle::5 8624800 1.19% 96.79% # Number of insts commited each cycle
2144system.cpu1.commit.committed_per_cycle::6 6048440 0.83% 97.62% # Number of insts commited each cycle
2145system.cpu1.commit.committed_per_cycle::7 3562811 0.49% 98.11% # Number of insts commited each cycle
2146system.cpu1.commit.committed_per_cycle::8 13734568 1.89% 100.00% # Number of insts commited each cycle
2147system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2148system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2149system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2150system.cpu1.commit.committed_per_cycle::total 726275789 # Number of insts commited each cycle
2151system.cpu1.commit.committedInsts 468737677 # Number of instructions committed
2152system.cpu1.commit.committedOps 552500848 # Number of ops (including micro ops) committed
2153system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2154system.cpu1.commit.refs 169901862 # Number of memory references committed
2155system.cpu1.commit.loads 88790435 # Number of loads committed
2156system.cpu1.commit.membars 3923548 # Number of memory barriers committed
2157system.cpu1.commit.branches 104577420 # Number of branches committed
2158system.cpu1.commit.fp_insts 490317 # Number of committed floating point instructions.
2159system.cpu1.commit.int_insts 507351840 # Number of committed integer instructions.
2160system.cpu1.commit.function_calls 13608772 # Number of function calls committed.
2161system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2162system.cpu1.commit.op_class_0::IntAlu 381394130 69.03% 69.03% # Class of committed instruction
2163system.cpu1.commit.op_class_0::IntMult 1072293 0.19% 69.22% # Class of committed instruction
2164system.cpu1.commit.op_class_0::IntDiv 58068 0.01% 69.24% # Class of committed instruction
2165system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.24% # Class of committed instruction
2166system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.24% # Class of committed instruction
2167system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.24% # Class of committed instruction
2168system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.24% # Class of committed instruction
2169system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.24% # Class of committed instruction
2170system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.24% # Class of committed instruction
2171system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.24% # Class of committed instruction
2172system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.24% # Class of committed instruction
2173system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.24% # Class of committed instruction
2174system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.24% # Class of committed instruction
2175system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.24% # Class of committed instruction
2176system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.24% # Class of committed instruction
2177system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.24% # Class of committed instruction
2178system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.24% # Class of committed instruction
2179system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.24% # Class of committed instruction
2180system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.24% # Class of committed instruction
2181system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.24% # Class of committed instruction
2182system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.24% # Class of committed instruction
2183system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.24% # Class of committed instruction
2184system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.24% # Class of committed instruction
2185system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.24% # Class of committed instruction
2186system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.24% # Class of committed instruction
2187system.cpu1.commit.op_class_0::SimdFloatMisc 74453 0.01% 69.25% # Class of committed instruction
2188system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.25% # Class of committed instruction
2189system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.25% # Class of committed instruction
2190system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.25% # Class of committed instruction
2191system.cpu1.commit.op_class_0::MemRead 88790435 16.07% 85.32% # Class of committed instruction
2192system.cpu1.commit.op_class_0::MemWrite 81111427 14.68% 100.00% # Class of committed instruction
2193system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2194system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2195system.cpu1.commit.op_class_0::total 552500848 # Class of committed instruction
2196system.cpu1.commit.bw_lim_events 13734568 # number cycles where commit BW limit reached
2197system.cpu1.rob.rob_reads 1308834452 # The number of ROB reads
2198system.cpu1.rob.rob_writes 1209328543 # The number of ROB writes
2199system.cpu1.timesIdled 978867 # Number of times that the entire CPU went into an idle state and unscheduled itself
2200system.cpu1.idleCycles 23862187 # Total number of cycles that the CPU has spent unscheduled due to idling
2201system.cpu1.quiesceCycles 93869849108 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2202system.cpu1.committedInsts 468737677 # Number of Instructions Simulated
2203system.cpu1.committedOps 552500848 # Number of Ops (including micro ops) Simulated
2204system.cpu1.cpi 1.619574 # CPI: Cycles Per Instruction
2205system.cpu1.cpi_total 1.619574 # CPI: Total CPI of All Threads
2206system.cpu1.ipc 0.617446 # IPC: Instructions Per Cycle
2207system.cpu1.ipc_total 0.617446 # IPC: Total IPC of All Threads
2208system.cpu1.int_regfile_reads 695521161 # number of integer regfile reads
2209system.cpu1.int_regfile_writes 411377637 # number of integer regfile writes
2210system.cpu1.fp_regfile_reads 787723 # number of floating regfile reads
2211system.cpu1.fp_regfile_writes 479172 # number of floating regfile writes
2212system.cpu1.cc_regfile_reads 125942514 # number of cc regfile reads
2213system.cpu1.cc_regfile_writes 126793051 # number of cc regfile writes
2214system.cpu1.misc_regfile_reads 1299771916 # number of misc regfile reads
2215system.cpu1.misc_regfile_writes 16418490 # number of misc regfile writes
2216system.cpu1.dcache.tags.replacements 5616176 # number of replacements
2217system.cpu1.dcache.tags.tagsinuse 458.902978 # Cycle average of tags in use
2218system.cpu1.dcache.tags.total_refs 158371031 # Total number of references to valid blocks.
2219system.cpu1.dcache.tags.sampled_refs 5616685 # Sample count of references to valid blocks.
2220system.cpu1.dcache.tags.avg_refs 28.196531 # Average number of references to valid blocks.
2221system.cpu1.dcache.tags.warmup_cycle 8486277940000 # Cycle when the warmup percentage was hit.
2222system.cpu1.dcache.tags.occ_blocks::cpu1.data 458.902978 # Average occupied blocks per requestor
2223system.cpu1.dcache.tags.occ_percent::cpu1.data 0.896295 # Average percentage of cache occupancy
2224system.cpu1.dcache.tags.occ_percent::total 0.896295 # Average percentage of cache occupancy
2225system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
2226system.cpu1.dcache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id
2227system.cpu1.dcache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id
2228system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id
2229system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
2230system.cpu1.dcache.tags.tag_accesses 352316395 # Number of tag accesses
2231system.cpu1.dcache.tags.data_accesses 352316395 # Number of data accesses
2232system.cpu1.dcache.ReadReq_hits::cpu1.data 82533449 # number of ReadReq hits
2233system.cpu1.dcache.ReadReq_hits::total 82533449 # number of ReadReq hits
2234system.cpu1.dcache.WriteReq_hits::cpu1.data 71018677 # number of WriteReq hits
2235system.cpu1.dcache.WriteReq_hits::total 71018677 # number of WriteReq hits
2236system.cpu1.dcache.SoftPFReq_hits::cpu1.data 182219 # number of SoftPFReq hits
2237system.cpu1.dcache.SoftPFReq_hits::total 182219 # number of SoftPFReq hits
2238system.cpu1.dcache.WriteLineReq_hits::cpu1.data 55748 # number of WriteLineReq hits
2239system.cpu1.dcache.WriteLineReq_hits::total 55748 # number of WriteLineReq hits
2240system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1865594 # number of LoadLockedReq hits
2241system.cpu1.dcache.LoadLockedReq_hits::total 1865594 # number of LoadLockedReq hits
2242system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1903770 # number of StoreCondReq hits
2243system.cpu1.dcache.StoreCondReq_hits::total 1903770 # number of StoreCondReq hits
2244system.cpu1.dcache.demand_hits::cpu1.data 153552126 # number of demand (read+write) hits
2245system.cpu1.dcache.demand_hits::total 153552126 # number of demand (read+write) hits
2246system.cpu1.dcache.overall_hits::cpu1.data 153734345 # number of overall hits
2247system.cpu1.dcache.overall_hits::total 153734345 # number of overall hits
2248system.cpu1.dcache.ReadReq_misses::cpu1.data 6611698 # number of ReadReq misses
2249system.cpu1.dcache.ReadReq_misses::total 6611698 # number of ReadReq misses
2250system.cpu1.dcache.WriteReq_misses::cpu1.data 7495595 # number of WriteReq misses
2251system.cpu1.dcache.WriteReq_misses::total 7495595 # number of WriteReq misses
2252system.cpu1.dcache.SoftPFReq_misses::cpu1.data 706613 # number of SoftPFReq misses
2253system.cpu1.dcache.SoftPFReq_misses::total 706613 # number of SoftPFReq misses
2254system.cpu1.dcache.WriteLineReq_misses::cpu1.data 438931 # number of WriteLineReq misses
2255system.cpu1.dcache.WriteLineReq_misses::total 438931 # number of WriteLineReq misses
2256system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 288457 # number of LoadLockedReq misses
2257system.cpu1.dcache.LoadLockedReq_misses::total 288457 # number of LoadLockedReq misses
2258system.cpu1.dcache.StoreCondReq_misses::cpu1.data 203515 # number of StoreCondReq misses
2259system.cpu1.dcache.StoreCondReq_misses::total 203515 # number of StoreCondReq misses
2260system.cpu1.dcache.demand_misses::cpu1.data 14107293 # number of demand (read+write) misses
2261system.cpu1.dcache.demand_misses::total 14107293 # number of demand (read+write) misses
2262system.cpu1.dcache.overall_misses::cpu1.data 14813906 # number of overall misses
2263system.cpu1.dcache.overall_misses::total 14813906 # number of overall misses
2264system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 112950117500 # number of ReadReq miss cycles
2265system.cpu1.dcache.ReadReq_miss_latency::total 112950117500 # number of ReadReq miss cycles
2266system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 162063724604 # number of WriteReq miss cycles
2267system.cpu1.dcache.WriteReq_miss_latency::total 162063724604 # number of WriteReq miss cycles
2268system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 18729695563 # number of WriteLineReq miss cycles
2269system.cpu1.dcache.WriteLineReq_miss_latency::total 18729695563 # number of WriteLineReq miss cycles
2270system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4597585500 # number of LoadLockedReq miss cycles
2271system.cpu1.dcache.LoadLockedReq_miss_latency::total 4597585500 # number of LoadLockedReq miss cycles
2272system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5657651000 # number of StoreCondReq miss cycles
2273system.cpu1.dcache.StoreCondReq_miss_latency::total 5657651000 # number of StoreCondReq miss cycles
2274system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 7414500 # number of StoreCondFailReq miss cycles
2275system.cpu1.dcache.StoreCondFailReq_miss_latency::total 7414500 # number of StoreCondFailReq miss cycles
2276system.cpu1.dcache.demand_miss_latency::cpu1.data 275013842104 # number of demand (read+write) miss cycles
2277system.cpu1.dcache.demand_miss_latency::total 275013842104 # number of demand (read+write) miss cycles
2278system.cpu1.dcache.overall_miss_latency::cpu1.data 275013842104 # number of overall miss cycles
2279system.cpu1.dcache.overall_miss_latency::total 275013842104 # number of overall miss cycles
2280system.cpu1.dcache.ReadReq_accesses::cpu1.data 89145147 # number of ReadReq accesses(hits+misses)
2281system.cpu1.dcache.ReadReq_accesses::total 89145147 # number of ReadReq accesses(hits+misses)
2282system.cpu1.dcache.WriteReq_accesses::cpu1.data 78514272 # number of WriteReq accesses(hits+misses)
2283system.cpu1.dcache.WriteReq_accesses::total 78514272 # number of WriteReq accesses(hits+misses)
2284system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 888832 # number of SoftPFReq accesses(hits+misses)
2285system.cpu1.dcache.SoftPFReq_accesses::total 888832 # number of SoftPFReq accesses(hits+misses)
2286system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 494679 # number of WriteLineReq accesses(hits+misses)
2287system.cpu1.dcache.WriteLineReq_accesses::total 494679 # number of WriteLineReq accesses(hits+misses)
2288system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2154051 # number of LoadLockedReq accesses(hits+misses)
2289system.cpu1.dcache.LoadLockedReq_accesses::total 2154051 # number of LoadLockedReq accesses(hits+misses)
2290system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2107285 # number of StoreCondReq accesses(hits+misses)
2291system.cpu1.dcache.StoreCondReq_accesses::total 2107285 # number of StoreCondReq accesses(hits+misses)
2292system.cpu1.dcache.demand_accesses::cpu1.data 167659419 # number of demand (read+write) accesses
2293system.cpu1.dcache.demand_accesses::total 167659419 # number of demand (read+write) accesses
2294system.cpu1.dcache.overall_accesses::cpu1.data 168548251 # number of overall (read+write) accesses
2295system.cpu1.dcache.overall_accesses::total 168548251 # number of overall (read+write) accesses
2296system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074168 # miss rate for ReadReq accesses
2297system.cpu1.dcache.ReadReq_miss_rate::total 0.074168 # miss rate for ReadReq accesses
2298system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.095468 # miss rate for WriteReq accesses
2299system.cpu1.dcache.WriteReq_miss_rate::total 0.095468 # miss rate for WriteReq accesses
2300system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.794991 # miss rate for SoftPFReq accesses
2301system.cpu1.dcache.SoftPFReq_miss_rate::total 0.794991 # miss rate for SoftPFReq accesses
2302system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.887305 # miss rate for WriteLineReq accesses
2303system.cpu1.dcache.WriteLineReq_miss_rate::total 0.887305 # miss rate for WriteLineReq accesses
2304system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.133914 # miss rate for LoadLockedReq accesses
2305system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.133914 # miss rate for LoadLockedReq accesses
2306system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.096577 # miss rate for StoreCondReq accesses
2307system.cpu1.dcache.StoreCondReq_miss_rate::total 0.096577 # miss rate for StoreCondReq accesses
2308system.cpu1.dcache.demand_miss_rate::cpu1.data 0.084143 # miss rate for demand accesses
2309system.cpu1.dcache.demand_miss_rate::total 0.084143 # miss rate for demand accesses
2310system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087891 # miss rate for overall accesses
2311system.cpu1.dcache.overall_miss_rate::total 0.087891 # miss rate for overall accesses
2312system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17083.375178 # average ReadReq miss latency
2313system.cpu1.dcache.ReadReq_avg_miss_latency::total 17083.375178 # average ReadReq miss latency
2314system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21621.195463 # average WriteReq miss latency
2315system.cpu1.dcache.WriteReq_avg_miss_latency::total 21621.195463 # average WriteReq miss latency
2316system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 42671.161442 # average WriteLineReq miss latency
2317system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 42671.161442 # average WriteLineReq miss latency
2318system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15938.547166 # average LoadLockedReq miss latency
2319system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15938.547166 # average LoadLockedReq miss latency
2320system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27799.675700 # average StoreCondReq miss latency
2321system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27799.675700 # average StoreCondReq miss latency
2322system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
2323system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2324system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19494.444618 # average overall miss latency
2325system.cpu1.dcache.demand_avg_miss_latency::total 19494.444618 # average overall miss latency
2326system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18564.573186 # average overall miss latency
2327system.cpu1.dcache.overall_avg_miss_latency::total 18564.573186 # average overall miss latency
2328system.cpu1.dcache.blocked_cycles::no_mshrs 4974164 # number of cycles access was blocked
2329system.cpu1.dcache.blocked_cycles::no_targets 25867147 # number of cycles access was blocked
2330system.cpu1.dcache.blocked::no_mshrs 359446 # number of cycles access was blocked
2331system.cpu1.dcache.blocked::no_targets 756404 # number of cycles access was blocked
2332system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.838418 # average number of cycles each access was blocked
2333system.cpu1.dcache.avg_blocked_cycles::no_targets 34.197528 # average number of cycles each access was blocked
2334system.cpu1.dcache.fast_writes 0 # number of fast writes performed
2335system.cpu1.dcache.cache_copies 0 # number of cache copies performed
2336system.cpu1.dcache.writebacks::writebacks 5616192 # number of writebacks
2337system.cpu1.dcache.writebacks::total 5616192 # number of writebacks
2338system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3382349 # number of ReadReq MSHR hits
2339system.cpu1.dcache.ReadReq_mshr_hits::total 3382349 # number of ReadReq MSHR hits
2340system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6057293 # number of WriteReq MSHR hits
2341system.cpu1.dcache.WriteReq_mshr_hits::total 6057293 # number of WriteReq MSHR hits
2342system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3337 # number of WriteLineReq MSHR hits
2343system.cpu1.dcache.WriteLineReq_mshr_hits::total 3337 # number of WriteLineReq MSHR hits
2344system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 147189 # number of LoadLockedReq MSHR hits
2345system.cpu1.dcache.LoadLockedReq_mshr_hits::total 147189 # number of LoadLockedReq MSHR hits
2346system.cpu1.dcache.demand_mshr_hits::cpu1.data 9439642 # number of demand (read+write) MSHR hits
2347system.cpu1.dcache.demand_mshr_hits::total 9439642 # number of demand (read+write) MSHR hits
2348system.cpu1.dcache.overall_mshr_hits::cpu1.data 9439642 # number of overall MSHR hits
2349system.cpu1.dcache.overall_mshr_hits::total 9439642 # number of overall MSHR hits
2350system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3229349 # number of ReadReq MSHR misses
2351system.cpu1.dcache.ReadReq_mshr_misses::total 3229349 # number of ReadReq MSHR misses
2352system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1438302 # number of WriteReq MSHR misses
2353system.cpu1.dcache.WriteReq_mshr_misses::total 1438302 # number of WriteReq MSHR misses
2354system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 706535 # number of SoftPFReq MSHR misses
2355system.cpu1.dcache.SoftPFReq_mshr_misses::total 706535 # number of SoftPFReq MSHR misses
2356system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 435594 # number of WriteLineReq MSHR misses
2357system.cpu1.dcache.WriteLineReq_mshr_misses::total 435594 # number of WriteLineReq MSHR misses
2358system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 141268 # number of LoadLockedReq MSHR misses
2359system.cpu1.dcache.LoadLockedReq_mshr_misses::total 141268 # number of LoadLockedReq MSHR misses
2360system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 203504 # number of StoreCondReq MSHR misses
2361system.cpu1.dcache.StoreCondReq_mshr_misses::total 203504 # number of StoreCondReq MSHR misses
2362system.cpu1.dcache.demand_mshr_misses::cpu1.data 4667651 # number of demand (read+write) MSHR misses
2363system.cpu1.dcache.demand_mshr_misses::total 4667651 # number of demand (read+write) MSHR misses
2364system.cpu1.dcache.overall_mshr_misses::cpu1.data 5374186 # number of overall MSHR misses
2365system.cpu1.dcache.overall_mshr_misses::total 5374186 # number of overall MSHR misses
2366system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5460 # number of ReadReq MSHR uncacheable
2367system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5460 # number of ReadReq MSHR uncacheable
2368system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5292 # number of WriteReq MSHR uncacheable
2369system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5292 # number of WriteReq MSHR uncacheable
2370system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10752 # number of overall MSHR uncacheable misses
2371system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10752 # number of overall MSHR uncacheable misses
2372system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 50929568500 # number of ReadReq MSHR miss cycles
2373system.cpu1.dcache.ReadReq_mshr_miss_latency::total 50929568500 # number of ReadReq MSHR miss cycles
2374system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 34490212579 # number of WriteReq MSHR miss cycles
2375system.cpu1.dcache.WriteReq_mshr_miss_latency::total 34490212579 # number of WriteReq MSHR miss cycles
2376system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16980659000 # number of SoftPFReq MSHR miss cycles
2377system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16980659000 # number of SoftPFReq MSHR miss cycles
2378system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 18123603563 # number of WriteLineReq MSHR miss cycles
2379system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 18123603563 # number of WriteLineReq MSHR miss cycles
2380system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 2072685000 # number of LoadLockedReq MSHR miss cycles
2381system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 2072685000 # number of LoadLockedReq MSHR miss cycles
2382system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5454243000 # number of StoreCondReq MSHR miss cycles
2383system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5454243000 # number of StoreCondReq MSHR miss cycles
2384system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 7318500 # number of StoreCondFailReq MSHR miss cycles
2385system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 7318500 # number of StoreCondFailReq MSHR miss cycles
2386system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 85419781079 # number of demand (read+write) MSHR miss cycles
2387system.cpu1.dcache.demand_mshr_miss_latency::total 85419781079 # number of demand (read+write) MSHR miss cycles
2388system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 102400440079 # number of overall MSHR miss cycles
2389system.cpu1.dcache.overall_mshr_miss_latency::total 102400440079 # number of overall MSHR miss cycles
2390system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 594704500 # number of ReadReq MSHR uncacheable cycles
2391system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 594704500 # number of ReadReq MSHR uncacheable cycles
2392system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 661334500 # number of WriteReq MSHR uncacheable cycles
2393system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 661334500 # number of WriteReq MSHR uncacheable cycles
2394system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1256039000 # number of overall MSHR uncacheable cycles
2395system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1256039000 # number of overall MSHR uncacheable cycles
2396system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036226 # mshr miss rate for ReadReq accesses
2397system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036226 # mshr miss rate for ReadReq accesses
2398system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018319 # mshr miss rate for WriteReq accesses
2399system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018319 # mshr miss rate for WriteReq accesses
2400system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.794903 # mshr miss rate for SoftPFReq accesses
2401system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.794903 # mshr miss rate for SoftPFReq accesses
2402system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.880559 # mshr miss rate for WriteLineReq accesses
2403system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.880559 # mshr miss rate for WriteLineReq accesses
2404system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065582 # mshr miss rate for LoadLockedReq accesses
2405system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065582 # mshr miss rate for LoadLockedReq accesses
2406system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096572 # mshr miss rate for StoreCondReq accesses
2407system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096572 # mshr miss rate for StoreCondReq accesses
2408system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027840 # mshr miss rate for demand accesses
2409system.cpu1.dcache.demand_mshr_miss_rate::total 0.027840 # mshr miss rate for demand accesses
2410system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031885 # mshr miss rate for overall accesses
2411system.cpu1.dcache.overall_mshr_miss_rate::total 0.031885 # mshr miss rate for overall accesses
2412system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15770.846849 # average ReadReq mshr miss latency
2413system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15770.846849 # average ReadReq mshr miss latency
2414system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23979.812709 # average WriteReq mshr miss latency
2415system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23979.812709 # average WriteReq mshr miss latency
2416system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24033.712413 # average SoftPFReq mshr miss latency
2417system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24033.712413 # average SoftPFReq mshr miss latency
2418system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 41606.641880 # average WriteLineReq mshr miss latency
2419system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 41606.641880 # average WriteLineReq mshr miss latency
2420system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14672.006399 # average LoadLockedReq mshr miss latency
2421system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14672.006399 # average LoadLockedReq mshr miss latency
2422system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26801.650090 # average StoreCondReq mshr miss latency
2423system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26801.650090 # average StoreCondReq mshr miss latency
2424system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
2425system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2426system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18300.378730 # average overall mshr miss latency
2427system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18300.378730 # average overall mshr miss latency
2428system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19054.130259 # average overall mshr miss latency
2429system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19054.130259 # average overall mshr miss latency
2430system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 108920.238095 # average ReadReq mshr uncacheable latency
2431system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 108920.238095 # average ReadReq mshr uncacheable latency
2432system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 124968.726379 # average WriteReq mshr uncacheable latency
2433system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 124968.726379 # average WriteReq mshr uncacheable latency
2434system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 116819.103423 # average overall mshr uncacheable latency
2435system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 116819.103423 # average overall mshr uncacheable latency
2436system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2437system.cpu1.icache.tags.replacements 5955939 # number of replacements
2438system.cpu1.icache.tags.tagsinuse 501.596349 # Cycle average of tags in use
2439system.cpu1.icache.tags.total_refs 208888584 # Total number of references to valid blocks.
2440system.cpu1.icache.tags.sampled_refs 5956451 # Sample count of references to valid blocks.
2441system.cpu1.icache.tags.avg_refs 35.069303 # Average number of references to valid blocks.
2442system.cpu1.icache.tags.warmup_cycle 8525956583000 # Cycle when the warmup percentage was hit.
2443system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.596349 # Average occupied blocks per requestor
2444system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979680 # Average percentage of cache occupancy
2445system.cpu1.icache.tags.occ_percent::total 0.979680 # Average percentage of cache occupancy
2446system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2447system.cpu1.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id
2448system.cpu1.icache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id
2449system.cpu1.icache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id
2450system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2451system.cpu1.icache.tags.tag_accesses 436342012 # Number of tag accesses
2452system.cpu1.icache.tags.data_accesses 436342012 # Number of data accesses
2453system.cpu1.icache.ReadReq_hits::cpu1.inst 208888584 # number of ReadReq hits
2454system.cpu1.icache.ReadReq_hits::total 208888584 # number of ReadReq hits
2455system.cpu1.icache.demand_hits::cpu1.inst 208888584 # number of demand (read+write) hits
2456system.cpu1.icache.demand_hits::total 208888584 # number of demand (read+write) hits
2457system.cpu1.icache.overall_hits::cpu1.inst 208888584 # number of overall hits
2458system.cpu1.icache.overall_hits::total 208888584 # number of overall hits
2459system.cpu1.icache.ReadReq_misses::cpu1.inst 6304191 # number of ReadReq misses
2460system.cpu1.icache.ReadReq_misses::total 6304191 # number of ReadReq misses
2461system.cpu1.icache.demand_misses::cpu1.inst 6304191 # number of demand (read+write) misses
2462system.cpu1.icache.demand_misses::total 6304191 # number of demand (read+write) misses
2463system.cpu1.icache.overall_misses::cpu1.inst 6304191 # number of overall misses
2464system.cpu1.icache.overall_misses::total 6304191 # number of overall misses
2465system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 70452471315 # number of ReadReq miss cycles
2466system.cpu1.icache.ReadReq_miss_latency::total 70452471315 # number of ReadReq miss cycles
2467system.cpu1.icache.demand_miss_latency::cpu1.inst 70452471315 # number of demand (read+write) miss cycles
2468system.cpu1.icache.demand_miss_latency::total 70452471315 # number of demand (read+write) miss cycles
2469system.cpu1.icache.overall_miss_latency::cpu1.inst 70452471315 # number of overall miss cycles
2470system.cpu1.icache.overall_miss_latency::total 70452471315 # number of overall miss cycles
2471system.cpu1.icache.ReadReq_accesses::cpu1.inst 215192775 # number of ReadReq accesses(hits+misses)
2472system.cpu1.icache.ReadReq_accesses::total 215192775 # number of ReadReq accesses(hits+misses)
2473system.cpu1.icache.demand_accesses::cpu1.inst 215192775 # number of demand (read+write) accesses
2474system.cpu1.icache.demand_accesses::total 215192775 # number of demand (read+write) accesses
2475system.cpu1.icache.overall_accesses::cpu1.inst 215192775 # number of overall (read+write) accesses
2476system.cpu1.icache.overall_accesses::total 215192775 # number of overall (read+write) accesses
2477system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029296 # miss rate for ReadReq accesses
2478system.cpu1.icache.ReadReq_miss_rate::total 0.029296 # miss rate for ReadReq accesses
2479system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029296 # miss rate for demand accesses
2480system.cpu1.icache.demand_miss_rate::total 0.029296 # miss rate for demand accesses
2481system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029296 # miss rate for overall accesses
2482system.cpu1.icache.overall_miss_rate::total 0.029296 # miss rate for overall accesses
2483system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11175.497588 # average ReadReq miss latency
2484system.cpu1.icache.ReadReq_avg_miss_latency::total 11175.497588 # average ReadReq miss latency
2485system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11175.497588 # average overall miss latency
2486system.cpu1.icache.demand_avg_miss_latency::total 11175.497588 # average overall miss latency
2487system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11175.497588 # average overall miss latency
2488system.cpu1.icache.overall_avg_miss_latency::total 11175.497588 # average overall miss latency
2489system.cpu1.icache.blocked_cycles::no_mshrs 10802796 # number of cycles access was blocked
2490system.cpu1.icache.blocked_cycles::no_targets 573 # number of cycles access was blocked
2491system.cpu1.icache.blocked::no_mshrs 747541 # number of cycles access was blocked
2492system.cpu1.icache.blocked::no_targets 5 # number of cycles access was blocked
2493system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.451108 # average number of cycles each access was blocked
2494system.cpu1.icache.avg_blocked_cycles::no_targets 114.600000 # average number of cycles each access was blocked
2495system.cpu1.icache.fast_writes 0 # number of fast writes performed
2496system.cpu1.icache.cache_copies 0 # number of cache copies performed
2497system.cpu1.icache.writebacks::writebacks 5955939 # number of writebacks
2498system.cpu1.icache.writebacks::total 5955939 # number of writebacks
2499system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 347729 # number of ReadReq MSHR hits
2500system.cpu1.icache.ReadReq_mshr_hits::total 347729 # number of ReadReq MSHR hits
2501system.cpu1.icache.demand_mshr_hits::cpu1.inst 347729 # number of demand (read+write) MSHR hits
2502system.cpu1.icache.demand_mshr_hits::total 347729 # number of demand (read+write) MSHR hits
2503system.cpu1.icache.overall_mshr_hits::cpu1.inst 347729 # number of overall MSHR hits
2504system.cpu1.icache.overall_mshr_hits::total 347729 # number of overall MSHR hits
2505system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5956462 # number of ReadReq MSHR misses
2506system.cpu1.icache.ReadReq_mshr_misses::total 5956462 # number of ReadReq MSHR misses
2507system.cpu1.icache.demand_mshr_misses::cpu1.inst 5956462 # number of demand (read+write) MSHR misses
2508system.cpu1.icache.demand_mshr_misses::total 5956462 # number of demand (read+write) MSHR misses
2509system.cpu1.icache.overall_mshr_misses::cpu1.inst 5956462 # number of overall MSHR misses
2510system.cpu1.icache.overall_mshr_misses::total 5956462 # number of overall MSHR misses
2511system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
2512system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable
2513system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
2514system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses
2515system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 63484136905 # number of ReadReq MSHR miss cycles
2516system.cpu1.icache.ReadReq_mshr_miss_latency::total 63484136905 # number of ReadReq MSHR miss cycles
2517system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 63484136905 # number of demand (read+write) MSHR miss cycles
2518system.cpu1.icache.demand_mshr_miss_latency::total 63484136905 # number of demand (read+write) MSHR miss cycles
2519system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 63484136905 # number of overall MSHR miss cycles
2520system.cpu1.icache.overall_mshr_miss_latency::total 63484136905 # number of overall MSHR miss cycles
2521system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8835998 # number of ReadReq MSHR uncacheable cycles
2522system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8835998 # number of ReadReq MSHR uncacheable cycles
2523system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8835998 # number of overall MSHR uncacheable cycles
2524system.cpu1.icache.overall_mshr_uncacheable_latency::total 8835998 # number of overall MSHR uncacheable cycles
2525system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027680 # mshr miss rate for ReadReq accesses
2526system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027680 # mshr miss rate for ReadReq accesses
2527system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027680 # mshr miss rate for demand accesses
2528system.cpu1.icache.demand_mshr_miss_rate::total 0.027680 # mshr miss rate for demand accesses
2529system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027680 # mshr miss rate for overall accesses
2530system.cpu1.icache.overall_mshr_miss_rate::total 0.027680 # mshr miss rate for overall accesses
2531system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10658.027686 # average ReadReq mshr miss latency
2532system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10658.027686 # average ReadReq mshr miss latency
2533system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10658.027686 # average overall mshr miss latency
2534system.cpu1.icache.demand_avg_mshr_miss_latency::total 10658.027686 # average overall mshr miss latency
2535system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10658.027686 # average overall mshr miss latency
2536system.cpu1.icache.overall_avg_mshr_miss_latency::total 10658.027686 # average overall mshr miss latency
2537system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 131880.567164 # average ReadReq mshr uncacheable latency
2538system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 131880.567164 # average ReadReq mshr uncacheable latency
2539system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 131880.567164 # average overall mshr uncacheable latency
2540system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 131880.567164 # average overall mshr uncacheable latency
2541system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2542system.cpu1.l2cache.prefetcher.num_hwpf_issued 7807580 # number of hwpf issued
2543system.cpu1.l2cache.prefetcher.pfIdentified 7812689 # number of prefetch candidates identified
2544system.cpu1.l2cache.prefetcher.pfBufferHit 4721 # number of redundant prefetches already in prefetch queue
2545system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
2546system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2547system.cpu1.l2cache.prefetcher.pfSpanPage 919623 # number of prefetches not generated due to page crossing
2548system.cpu1.l2cache.tags.replacements 2337918 # number of replacements
2549system.cpu1.l2cache.tags.tagsinuse 13374.571842 # Cycle average of tags in use
2550system.cpu1.l2cache.tags.total_refs 17269379 # Total number of references to valid blocks.
2551system.cpu1.l2cache.tags.sampled_refs 2353639 # Sample count of references to valid blocks.
2552system.cpu1.l2cache.tags.avg_refs 7.337310 # Average number of references to valid blocks.
2553system.cpu1.l2cache.tags.warmup_cycle 10121843878000 # Cycle when the warmup percentage was hit.
2554system.cpu1.l2cache.tags.occ_blocks::writebacks 12566.070038 # Average occupied blocks per requestor
2555system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 56.667232 # Average occupied blocks per requestor
2556system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.366082 # Average occupied blocks per requestor
2557system.cpu1.l2cache.tags.occ_blocks::cpu1.data 0.000003 # Average occupied blocks per requestor
2558system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 686.468486 # Average occupied blocks per requestor
2559system.cpu1.l2cache.tags.occ_percent::writebacks 0.766972 # Average percentage of cache occupancy
2560system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003459 # Average percentage of cache occupancy
2561system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003990 # Average percentage of cache occupancy
2562system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.000000 # Average percentage of cache occupancy
2563system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.041899 # Average percentage of cache occupancy
2564system.cpu1.l2cache.tags.occ_percent::total 0.816319 # Average percentage of cache occupancy
2565system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1203 # Occupied blocks per task id
2566system.cpu1.l2cache.tags.occ_task_id_blocks::1023 84 # Occupied blocks per task id
2567system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14434 # Occupied blocks per task id
2568system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 80 # Occupied blocks per task id
2569system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 187 # Occupied blocks per task id
2570system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 549 # Occupied blocks per task id
2571system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 387 # Occupied blocks per task id
2572system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id
2573system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 65 # Occupied blocks per task id
2574system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
2575system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id
2576system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id
2577system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 840 # Occupied blocks per task id
2578system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4705 # Occupied blocks per task id
2579system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4934 # Occupied blocks per task id
2580system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3842 # Occupied blocks per task id
2581system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.073425 # Percentage of cache occupancy per task id
2582system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005127 # Percentage of cache occupancy per task id
2583system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.880981 # Percentage of cache occupancy per task id
2584system.cpu1.l2cache.tags.tag_accesses 397810098 # Number of tag accesses
2585system.cpu1.l2cache.tags.data_accesses 397810098 # Number of data accesses
2586system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 597256 # number of ReadReq hits
2587system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 208532 # number of ReadReq hits
2588system.cpu1.l2cache.ReadReq_hits::total 805788 # number of ReadReq hits
2589system.cpu1.l2cache.WritebackDirty_hits::writebacks 3539726 # number of WritebackDirty hits
2590system.cpu1.l2cache.WritebackDirty_hits::total 3539726 # number of WritebackDirty hits
2591system.cpu1.l2cache.WritebackClean_hits::writebacks 8031138 # number of WritebackClean hits
2592system.cpu1.l2cache.WritebackClean_hits::total 8031138 # number of WritebackClean hits
2593system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 945 # number of UpgradeReq hits
2594system.cpu1.l2cache.UpgradeReq_hits::total 945 # number of UpgradeReq hits
2595system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 4 # number of SCUpgradeReq hits
2596system.cpu1.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits
2597system.cpu1.l2cache.ReadExReq_hits::cpu1.data 889943 # number of ReadExReq hits
2598system.cpu1.l2cache.ReadExReq_hits::total 889943 # number of ReadExReq hits
2599system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5374664 # number of ReadCleanReq hits
2600system.cpu1.l2cache.ReadCleanReq_hits::total 5374664 # number of ReadCleanReq hits
2601system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3032294 # number of ReadSharedReq hits
2602system.cpu1.l2cache.ReadSharedReq_hits::total 3032294 # number of ReadSharedReq hits
2603system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 189660 # number of InvalidateReq hits
2604system.cpu1.l2cache.InvalidateReq_hits::total 189660 # number of InvalidateReq hits
2605system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 597256 # number of demand (read+write) hits
2606system.cpu1.l2cache.demand_hits::cpu1.itb.walker 208532 # number of demand (read+write) hits
2607system.cpu1.l2cache.demand_hits::cpu1.inst 5374664 # number of demand (read+write) hits
2608system.cpu1.l2cache.demand_hits::cpu1.data 3922237 # number of demand (read+write) hits
2609system.cpu1.l2cache.demand_hits::total 10102689 # number of demand (read+write) hits
2610system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 597256 # number of overall hits
2611system.cpu1.l2cache.overall_hits::cpu1.itb.walker 208532 # number of overall hits
2612system.cpu1.l2cache.overall_hits::cpu1.inst 5374664 # number of overall hits
2613system.cpu1.l2cache.overall_hits::cpu1.data 3922237 # number of overall hits
2614system.cpu1.l2cache.overall_hits::total 10102689 # number of overall hits
2615system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12883 # number of ReadReq misses
2616system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10252 # number of ReadReq misses
2617system.cpu1.l2cache.ReadReq_misses::total 23135 # number of ReadReq misses
2618system.cpu1.l2cache.WritebackDirty_misses::writebacks 5 # number of WritebackDirty misses
2619system.cpu1.l2cache.WritebackDirty_misses::total 5 # number of WritebackDirty misses
2620system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 246019 # number of UpgradeReq misses
2621system.cpu1.l2cache.UpgradeReq_misses::total 246019 # number of UpgradeReq misses
2622system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 203494 # number of SCUpgradeReq misses
2623system.cpu1.l2cache.SCUpgradeReq_misses::total 203494 # number of SCUpgradeReq misses
2624system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses
2625system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
2626system.cpu1.l2cache.ReadExReq_misses::cpu1.data 311077 # number of ReadExReq misses
2627system.cpu1.l2cache.ReadExReq_misses::total 311077 # number of ReadExReq misses
2628system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 581787 # number of ReadCleanReq misses
2629system.cpu1.l2cache.ReadCleanReq_misses::total 581787 # number of ReadCleanReq misses
2630system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1040673 # number of ReadSharedReq misses
2631system.cpu1.l2cache.ReadSharedReq_misses::total 1040673 # number of ReadSharedReq misses
2632system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 244105 # number of InvalidateReq misses
2633system.cpu1.l2cache.InvalidateReq_misses::total 244105 # number of InvalidateReq misses
2634system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12883 # number of demand (read+write) misses
2635system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10252 # number of demand (read+write) misses
2636system.cpu1.l2cache.demand_misses::cpu1.inst 581787 # number of demand (read+write) misses
2637system.cpu1.l2cache.demand_misses::cpu1.data 1351750 # number of demand (read+write) misses
2638system.cpu1.l2cache.demand_misses::total 1956672 # number of demand (read+write) misses
2639system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12883 # number of overall misses
2640system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10252 # number of overall misses
2641system.cpu1.l2cache.overall_misses::cpu1.inst 581787 # number of overall misses
2642system.cpu1.l2cache.overall_misses::cpu1.data 1351750 # number of overall misses
2643system.cpu1.l2cache.overall_misses::total 1956672 # number of overall misses
2644system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 705237000 # number of ReadReq miss cycles
2645system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 609311000 # number of ReadReq miss cycles
2646system.cpu1.l2cache.ReadReq_miss_latency::total 1314548000 # number of ReadReq miss cycles
2647system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3694717000 # number of UpgradeReq miss cycles
2648system.cpu1.l2cache.UpgradeReq_miss_latency::total 3694717000 # number of UpgradeReq miss cycles
2649system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1939092500 # number of SCUpgradeReq miss cycles
2650system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1939092500 # number of SCUpgradeReq miss cycles
2651system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 7171998 # number of SCUpgradeFailReq miss cycles
2652system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 7171998 # number of SCUpgradeFailReq miss cycles
2653system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 16701418499 # number of ReadExReq miss cycles
2654system.cpu1.l2cache.ReadExReq_miss_latency::total 16701418499 # number of ReadExReq miss cycles
2655system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 22000590000 # number of ReadCleanReq miss cycles
2656system.cpu1.l2cache.ReadCleanReq_miss_latency::total 22000590000 # number of ReadCleanReq miss cycles
2657system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 43617133977 # number of ReadSharedReq miss cycles
2658system.cpu1.l2cache.ReadSharedReq_miss_latency::total 43617133977 # number of ReadSharedReq miss cycles
2659system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 15757180999 # number of InvalidateReq miss cycles
2660system.cpu1.l2cache.InvalidateReq_miss_latency::total 15757180999 # number of InvalidateReq miss cycles
2661system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 705237000 # number of demand (read+write) miss cycles
2662system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 609311000 # number of demand (read+write) miss cycles
2663system.cpu1.l2cache.demand_miss_latency::cpu1.inst 22000590000 # number of demand (read+write) miss cycles
2664system.cpu1.l2cache.demand_miss_latency::cpu1.data 60318552476 # number of demand (read+write) miss cycles
2665system.cpu1.l2cache.demand_miss_latency::total 83633690476 # number of demand (read+write) miss cycles
2666system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 705237000 # number of overall miss cycles
2667system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 609311000 # number of overall miss cycles
2668system.cpu1.l2cache.overall_miss_latency::cpu1.inst 22000590000 # number of overall miss cycles
2669system.cpu1.l2cache.overall_miss_latency::cpu1.data 60318552476 # number of overall miss cycles
2670system.cpu1.l2cache.overall_miss_latency::total 83633690476 # number of overall miss cycles
2671system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 610139 # number of ReadReq accesses(hits+misses)
2672system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 218784 # number of ReadReq accesses(hits+misses)
2673system.cpu1.l2cache.ReadReq_accesses::total 828923 # number of ReadReq accesses(hits+misses)
2674system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3539731 # number of WritebackDirty accesses(hits+misses)
2675system.cpu1.l2cache.WritebackDirty_accesses::total 3539731 # number of WritebackDirty accesses(hits+misses)
2676system.cpu1.l2cache.WritebackClean_accesses::writebacks 8031138 # number of WritebackClean accesses(hits+misses)
2677system.cpu1.l2cache.WritebackClean_accesses::total 8031138 # number of WritebackClean accesses(hits+misses)
2678system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 246964 # number of UpgradeReq accesses(hits+misses)
2679system.cpu1.l2cache.UpgradeReq_accesses::total 246964 # number of UpgradeReq accesses(hits+misses)
2680system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 203498 # number of SCUpgradeReq accesses(hits+misses)
2681system.cpu1.l2cache.SCUpgradeReq_accesses::total 203498 # number of SCUpgradeReq accesses(hits+misses)
2682system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses)
2683system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
2684system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1201020 # number of ReadExReq accesses(hits+misses)
2685system.cpu1.l2cache.ReadExReq_accesses::total 1201020 # number of ReadExReq accesses(hits+misses)
2686system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5956451 # number of ReadCleanReq accesses(hits+misses)
2687system.cpu1.l2cache.ReadCleanReq_accesses::total 5956451 # number of ReadCleanReq accesses(hits+misses)
2688system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4072967 # number of ReadSharedReq accesses(hits+misses)
2689system.cpu1.l2cache.ReadSharedReq_accesses::total 4072967 # number of ReadSharedReq accesses(hits+misses)
2690system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 433765 # number of InvalidateReq accesses(hits+misses)
2691system.cpu1.l2cache.InvalidateReq_accesses::total 433765 # number of InvalidateReq accesses(hits+misses)
2692system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 610139 # number of demand (read+write) accesses
2693system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 218784 # number of demand (read+write) accesses
2694system.cpu1.l2cache.demand_accesses::cpu1.inst 5956451 # number of demand (read+write) accesses
2695system.cpu1.l2cache.demand_accesses::cpu1.data 5273987 # number of demand (read+write) accesses
2696system.cpu1.l2cache.demand_accesses::total 12059361 # number of demand (read+write) accesses
2697system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 610139 # number of overall (read+write) accesses
2698system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 218784 # number of overall (read+write) accesses
2699system.cpu1.l2cache.overall_accesses::cpu1.inst 5956451 # number of overall (read+write) accesses
2700system.cpu1.l2cache.overall_accesses::cpu1.data 5273987 # number of overall (read+write) accesses
2701system.cpu1.l2cache.overall_accesses::total 12059361 # number of overall (read+write) accesses
2702system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021115 # miss rate for ReadReq accesses
2703system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.046859 # miss rate for ReadReq accesses
2704system.cpu1.l2cache.ReadReq_miss_rate::total 0.027910 # miss rate for ReadReq accesses
2705system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses
2706system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses
2707system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.996174 # miss rate for UpgradeReq accesses
2708system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.996174 # miss rate for UpgradeReq accesses
2709system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999980 # miss rate for SCUpgradeReq accesses
2710system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999980 # miss rate for SCUpgradeReq accesses
2711system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2712system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2713system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.259011 # miss rate for ReadExReq accesses
2714system.cpu1.l2cache.ReadExReq_miss_rate::total 0.259011 # miss rate for ReadExReq accesses
2715system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097673 # miss rate for ReadCleanReq accesses
2716system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097673 # miss rate for ReadCleanReq accesses
2717system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.255507 # miss rate for ReadSharedReq accesses
2718system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.255507 # miss rate for ReadSharedReq accesses
2719system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.562759 # miss rate for InvalidateReq accesses
2720system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.562759 # miss rate for InvalidateReq accesses
2721system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021115 # miss rate for demand accesses
2722system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.046859 # miss rate for demand accesses
2723system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097673 # miss rate for demand accesses
2724system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.256305 # miss rate for demand accesses
2725system.cpu1.l2cache.demand_miss_rate::total 0.162253 # miss rate for demand accesses
2726system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021115 # miss rate for overall accesses
2727system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.046859 # miss rate for overall accesses
2728system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097673 # miss rate for overall accesses
2729system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.256305 # miss rate for overall accesses
2730system.cpu1.l2cache.overall_miss_rate::total 0.162253 # miss rate for overall accesses
2731system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 54741.675076 # average ReadReq miss latency
2732system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 59433.378853 # average ReadReq miss latency
2733system.cpu1.l2cache.ReadReq_avg_miss_latency::total 56820.747785 # average ReadReq miss latency
2734system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15018.014869 # average UpgradeReq miss latency
2735system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15018.014869 # average UpgradeReq miss latency
2736system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9528.991027 # average SCUpgradeReq miss latency
2737system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9528.991027 # average SCUpgradeReq miss latency
2738system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1195333 # average SCUpgradeFailReq miss latency
2739system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1195333 # average SCUpgradeFailReq miss latency
2740system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53689.017507 # average ReadExReq miss latency
2741system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53689.017507 # average ReadExReq miss latency
2742system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37815.540739 # average ReadCleanReq miss latency
2743system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37815.540739 # average ReadCleanReq miss latency
2744system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 41912.429723 # average ReadSharedReq miss latency
2745system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 41912.429723 # average ReadSharedReq miss latency
2746system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 64550.832629 # average InvalidateReq miss latency
2747system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 64550.832629 # average InvalidateReq miss latency
2748system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 54741.675076 # average overall miss latency
2749system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 59433.378853 # average overall miss latency
2750system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37815.540739 # average overall miss latency
2751system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 44622.565176 # average overall miss latency
2752system.cpu1.l2cache.demand_avg_miss_latency::total 42742.825816 # average overall miss latency
2753system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 54741.675076 # average overall miss latency
2754system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 59433.378853 # average overall miss latency
2755system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37815.540739 # average overall miss latency
2756system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 44622.565176 # average overall miss latency
2757system.cpu1.l2cache.overall_avg_miss_latency::total 42742.825816 # average overall miss latency
2758system.cpu1.l2cache.blocked_cycles::no_mshrs 758 # number of cycles access was blocked
2759system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2760system.cpu1.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked
2761system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2762system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 126.333333 # average number of cycles each access was blocked
2763system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2764system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2765system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2766system.cpu1.l2cache.writebacks::writebacks 1264789 # number of writebacks
2767system.cpu1.l2cache.writebacks::total 1264789 # number of writebacks
2768system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 4 # number of ReadReq MSHR hits
2769system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 169 # number of ReadReq MSHR hits
2770system.cpu1.l2cache.ReadReq_mshr_hits::total 173 # number of ReadReq MSHR hits
2771system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 44408 # number of ReadExReq MSHR hits
2772system.cpu1.l2cache.ReadExReq_mshr_hits::total 44408 # number of ReadExReq MSHR hits
2773system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 5726 # number of ReadSharedReq MSHR hits
2774system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 5726 # number of ReadSharedReq MSHR hits
2775system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 6 # number of InvalidateReq MSHR hits
2776system.cpu1.l2cache.InvalidateReq_mshr_hits::total 6 # number of InvalidateReq MSHR hits
2777system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 4 # number of demand (read+write) MSHR hits
2778system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 169 # number of demand (read+write) MSHR hits
2779system.cpu1.l2cache.demand_mshr_hits::cpu1.data 50134 # number of demand (read+write) MSHR hits
2780system.cpu1.l2cache.demand_mshr_hits::total 50307 # number of demand (read+write) MSHR hits
2781system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 4 # number of overall MSHR hits
2782system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 169 # number of overall MSHR hits
2783system.cpu1.l2cache.overall_mshr_hits::cpu1.data 50134 # number of overall MSHR hits
2784system.cpu1.l2cache.overall_mshr_hits::total 50307 # number of overall MSHR hits
2785system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12879 # number of ReadReq MSHR misses
2786system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10083 # number of ReadReq MSHR misses
2787system.cpu1.l2cache.ReadReq_mshr_misses::total 22962 # number of ReadReq MSHR misses
2788system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 5 # number of WritebackDirty MSHR misses
2789system.cpu1.l2cache.WritebackDirty_mshr_misses::total 5 # number of WritebackDirty MSHR misses
2790system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 820594 # number of HardPFReq MSHR misses
2791system.cpu1.l2cache.HardPFReq_mshr_misses::total 820594 # number of HardPFReq MSHR misses
2792system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 246019 # number of UpgradeReq MSHR misses
2793system.cpu1.l2cache.UpgradeReq_mshr_misses::total 246019 # number of UpgradeReq MSHR misses
2794system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 203494 # number of SCUpgradeReq MSHR misses
2795system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 203494 # number of SCUpgradeReq MSHR misses
2796system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses
2797system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses
2798system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 266669 # number of ReadExReq MSHR misses
2799system.cpu1.l2cache.ReadExReq_mshr_misses::total 266669 # number of ReadExReq MSHR misses
2800system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 581787 # number of ReadCleanReq MSHR misses
2801system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 581787 # number of ReadCleanReq MSHR misses
2802system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 1034947 # number of ReadSharedReq MSHR misses
2803system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 1034947 # number of ReadSharedReq MSHR misses
2804system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 244099 # number of InvalidateReq MSHR misses
2805system.cpu1.l2cache.InvalidateReq_mshr_misses::total 244099 # number of InvalidateReq MSHR misses
2806system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12879 # number of demand (read+write) MSHR misses
2807system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10083 # number of demand (read+write) MSHR misses
2808system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 581787 # number of demand (read+write) MSHR misses
2809system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1301616 # number of demand (read+write) MSHR misses
2810system.cpu1.l2cache.demand_mshr_misses::total 1906365 # number of demand (read+write) MSHR misses
2811system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12879 # number of overall MSHR misses
2812system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10083 # number of overall MSHR misses
2813system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 581787 # number of overall MSHR misses
2814system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1301616 # number of overall MSHR misses
2815system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 820594 # number of overall MSHR misses
2816system.cpu1.l2cache.overall_mshr_misses::total 2726959 # number of overall MSHR misses
2817system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
2818system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5460 # number of ReadReq MSHR uncacheable
2819system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5527 # number of ReadReq MSHR uncacheable
2820system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5292 # number of WriteReq MSHR uncacheable
2821system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5292 # number of WriteReq MSHR uncacheable
2822system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
2823system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10752 # number of overall MSHR uncacheable misses
2824system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10819 # number of overall MSHR uncacheable misses
2825system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 627888000 # number of ReadReq MSHR miss cycles
2826system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 537691500 # number of ReadReq MSHR miss cycles
2827system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1165579500 # number of ReadReq MSHR miss cycles
2828system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 49091164625 # number of HardPFReq MSHR miss cycles
2829system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 49091164625 # number of HardPFReq MSHR miss cycles
2830system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7718588995 # number of UpgradeReq MSHR miss cycles
2831system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7718588995 # number of UpgradeReq MSHR miss cycles
2832system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3925065997 # number of SCUpgradeReq MSHR miss cycles
2833system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3925065997 # number of SCUpgradeReq MSHR miss cycles
2834system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 6595998 # number of SCUpgradeFailReq MSHR miss cycles
2835system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6595998 # number of SCUpgradeFailReq MSHR miss cycles
2836system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 12865032499 # number of ReadExReq MSHR miss cycles
2837system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 12865032499 # number of ReadExReq MSHR miss cycles
2838system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 18509868000 # number of ReadCleanReq MSHR miss cycles
2839system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 18509868000 # number of ReadCleanReq MSHR miss cycles
2840system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 37054911477 # number of ReadSharedReq MSHR miss cycles
2841system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 37054911477 # number of ReadSharedReq MSHR miss cycles
2842system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 14292006999 # number of InvalidateReq MSHR miss cycles
2843system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 14292006999 # number of InvalidateReq MSHR miss cycles
2844system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 627888000 # number of demand (read+write) MSHR miss cycles
2845system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 537691500 # number of demand (read+write) MSHR miss cycles
2846system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 18509868000 # number of demand (read+write) MSHR miss cycles
2847system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 49919943976 # number of demand (read+write) MSHR miss cycles
2848system.cpu1.l2cache.demand_mshr_miss_latency::total 69595391476 # number of demand (read+write) MSHR miss cycles
2849system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 627888000 # number of overall MSHR miss cycles
2850system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 537691500 # number of overall MSHR miss cycles
2851system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 18509868000 # number of overall MSHR miss cycles
2852system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 49919943976 # number of overall MSHR miss cycles
2853system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 49091164625 # number of overall MSHR miss cycles
2854system.cpu1.l2cache.overall_mshr_miss_latency::total 118686556101 # number of overall MSHR miss cycles
2855system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8332500 # number of ReadReq MSHR uncacheable cycles
2856system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 550904000 # number of ReadReq MSHR uncacheable cycles
2857system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 559236500 # number of ReadReq MSHR uncacheable cycles
2858system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 621567000 # number of WriteReq MSHR uncacheable cycles
2859system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 621567000 # number of WriteReq MSHR uncacheable cycles
2860system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8332500 # number of overall MSHR uncacheable cycles
2861system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1172471000 # number of overall MSHR uncacheable cycles
2862system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1180803500 # number of overall MSHR uncacheable cycles
2863system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021108 # mshr miss rate for ReadReq accesses
2864system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046087 # mshr miss rate for ReadReq accesses
2865system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027701 # mshr miss rate for ReadReq accesses
2866system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses
2867system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses
2868system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2869system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2870system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996174 # mshr miss rate for UpgradeReq accesses
2871system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996174 # mshr miss rate for UpgradeReq accesses
2872system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999980 # mshr miss rate for SCUpgradeReq accesses
2873system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999980 # mshr miss rate for SCUpgradeReq accesses
2874system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2875system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2876system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.222035 # mshr miss rate for ReadExReq accesses
2877system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.222035 # mshr miss rate for ReadExReq accesses
2878system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.097673 # mshr miss rate for ReadCleanReq accesses
2879system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097673 # mshr miss rate for ReadCleanReq accesses
2880system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.254101 # mshr miss rate for ReadSharedReq accesses
2881system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254101 # mshr miss rate for ReadSharedReq accesses
2882system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.562745 # mshr miss rate for InvalidateReq accesses
2883system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.562745 # mshr miss rate for InvalidateReq accesses
2884system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021108 # mshr miss rate for demand accesses
2885system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046087 # mshr miss rate for demand accesses
2886system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.097673 # mshr miss rate for demand accesses
2887system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.246799 # mshr miss rate for demand accesses
2888system.cpu1.l2cache.demand_mshr_miss_rate::total 0.158082 # mshr miss rate for demand accesses
2889system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021108 # mshr miss rate for overall accesses
2890system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046087 # mshr miss rate for overall accesses
2891system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.097673 # mshr miss rate for overall accesses
2892system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.246799 # mshr miss rate for overall accesses
2893system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2894system.cpu1.l2cache.overall_mshr_miss_rate::total 0.226128 # mshr miss rate for overall accesses
2895system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 48752.853482 # average ReadReq mshr miss latency
2896system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 53326.539720 # average ReadReq mshr miss latency
2897system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 50761.235955 # average ReadReq mshr miss latency
2898system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59823.938056 # average HardPFReq mshr miss latency
2899system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 59823.938056 # average HardPFReq mshr miss latency
2900system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31373.954837 # average UpgradeReq mshr miss latency
2901system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31373.954837 # average UpgradeReq mshr miss latency
2902system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19288.362296 # average SCUpgradeReq mshr miss latency
2903system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19288.362296 # average SCUpgradeReq mshr miss latency
2904system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1099333 # average SCUpgradeFailReq mshr miss latency
2905system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1099333 # average SCUpgradeFailReq mshr miss latency
2906system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 48243.449741 # average ReadExReq mshr miss latency
2907system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 48243.449741 # average ReadExReq mshr miss latency
2908system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31815.540739 # average ReadCleanReq mshr miss latency
2909system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31815.540739 # average ReadCleanReq mshr miss latency
2910system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 35803.680263 # average ReadSharedReq mshr miss latency
2911system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35803.680263 # average ReadSharedReq mshr miss latency
2912system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 58550.043216 # average InvalidateReq mshr miss latency
2913system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 58550.043216 # average InvalidateReq mshr miss latency
2914system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 48752.853482 # average overall mshr miss latency
2915system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 53326.539720 # average overall mshr miss latency
2916system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31815.540739 # average overall mshr miss latency
2917system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 38352.282068 # average overall mshr miss latency
2918system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 36506.855443 # average overall mshr miss latency
2919system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 48752.853482 # average overall mshr miss latency
2920system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 53326.539720 # average overall mshr miss latency
2921system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31815.540739 # average overall mshr miss latency
2922system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 38352.282068 # average overall mshr miss latency
2923system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59823.938056 # average overall mshr miss latency
2924system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 43523.410547 # average overall mshr miss latency
2925system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124365.671642 # average ReadReq mshr uncacheable latency
2926system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 100898.168498 # average ReadReq mshr uncacheable latency
2927system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 101182.648815 # average ReadReq mshr uncacheable latency
2928system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117454.081633 # average WriteReq mshr uncacheable latency
2929system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117454.081633 # average WriteReq mshr uncacheable latency
2930system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124365.671642 # average overall mshr uncacheable latency
2931system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 109046.781994 # average overall mshr uncacheable latency
2932system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 109141.648951 # average overall mshr uncacheable latency
2933system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2934system.cpu1.toL2Bus.snoop_filter.tot_requests 24065952 # Total number of requests made to the snoop filter.
2935system.cpu1.toL2Bus.snoop_filter.hit_single_requests 12401926 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2936system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1256 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2937system.cpu1.toL2Bus.snoop_filter.tot_snoops 2060689 # Total number of snoops made to the snoop filter.
2938system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2060329 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2939system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 360 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2940system.cpu1.toL2Bus.trans_dist::ReadReq 934376 # Transaction distribution
2941system.cpu1.toL2Bus.trans_dist::ReadResp 11053796 # Transaction distribution
2942system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution
2943system.cpu1.toL2Bus.trans_dist::WriteReq 5292 # Transaction distribution
2944system.cpu1.toL2Bus.trans_dist::WriteResp 5292 # Transaction distribution
2945system.cpu1.toL2Bus.trans_dist::WritebackDirty 4812576 # Transaction distribution
2946system.cpu1.toL2Bus.trans_dist::WritebackClean 8031153 # Transaction distribution
2947system.cpu1.toL2Bus.trans_dist::CleanEvict 2767424 # Transaction distribution
2948system.cpu1.toL2Bus.trans_dist::HardPFReq 1034593 # Transaction distribution
2949system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
2950system.cpu1.toL2Bus.trans_dist::UpgradeReq 454030 # Transaction distribution
2951system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 361772 # Transaction distribution
2952system.cpu1.toL2Bus.trans_dist::UpgradeResp 513435 # Transaction distribution
2953system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 121 # Transaction distribution
2954system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 211 # Transaction distribution
2955system.cpu1.toL2Bus.trans_dist::ReadExReq 1276992 # Transaction distribution
2956system.cpu1.toL2Bus.trans_dist::ReadExResp 1207288 # Transaction distribution
2957system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5956462 # Transaction distribution
2958system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5025648 # Transaction distribution
2959system.cpu1.toL2Bus.trans_dist::InvalidateReq 440267 # Transaction distribution
2960system.cpu1.toL2Bus.trans_dist::InvalidateResp 433765 # Transaction distribution
2961system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17868522 # Packet count per connected master and slave (bytes)
2962system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18112795 # Packet count per connected master and slave (bytes)
2963system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 459206 # Packet count per connected master and slave (bytes)
2964system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1298566 # Packet count per connected master and slave (bytes)
2965system.cpu1.toL2Bus.pkt_count::total 37739089 # Packet count per connected master and slave (bytes)
2966system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 762364336 # Cumulative packet size per connected master and slave (bytes)
2967system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 703129592 # Cumulative packet size per connected master and slave (bytes)
2968system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1750272 # Cumulative packet size per connected master and slave (bytes)
2969system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4881112 # Cumulative packet size per connected master and slave (bytes)
2970system.cpu1.toL2Bus.pkt_size::total 1472125312 # Cumulative packet size per connected master and slave (bytes)
2971system.cpu1.toL2Bus.snoops 6734851 # Total snoops (count)
2972system.cpu1.toL2Bus.snoop_fanout::samples 19529823 # Request fanout histogram
2973system.cpu1.toL2Bus.snoop_fanout::mean 0.125012 # Request fanout histogram
2974system.cpu1.toL2Bus.snoop_fanout::stdev 0.330788 # Request fanout histogram
2975system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2976system.cpu1.toL2Bus.snoop_fanout::0 17088727 87.50% 87.50% # Request fanout histogram
2977system.cpu1.toL2Bus.snoop_fanout::1 2440736 12.50% 100.00% # Request fanout histogram
2978system.cpu1.toL2Bus.snoop_fanout::2 360 0.00% 100.00% # Request fanout histogram
2979system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2980system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2981system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2982system.cpu1.toL2Bus.snoop_fanout::total 19529823 # Request fanout histogram
2983system.cpu1.toL2Bus.reqLayer0.occupancy 23888032965 # Layer occupancy (ticks)
2984system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2985system.cpu1.toL2Bus.snoopLayer0.occupancy 176197847 # Layer occupancy (ticks)
2986system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2987system.cpu1.toL2Bus.respLayer0.occupancy 8940771887 # Layer occupancy (ticks)
2988system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2989system.cpu1.toL2Bus.respLayer1.occupancy 8370756543 # Layer occupancy (ticks)
2990system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2991system.cpu1.toL2Bus.respLayer2.occupancy 240887058 # Layer occupancy (ticks)
2992system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2993system.cpu1.toL2Bus.respLayer3.occupancy 689185473 # Layer occupancy (ticks)
2994system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2995system.iobus.trans_dist::ReadReq 40298 # Transaction distribution
2996system.iobus.trans_dist::ReadResp 40298 # Transaction distribution
2997system.iobus.trans_dist::WriteReq 136623 # Transaction distribution
2998system.iobus.trans_dist::WriteResp 136623 # Transaction distribution
2999system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47620 # Packet count per connected master and slave (bytes)
3000system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
3001system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
3002system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
3003system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
3004system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
3005system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
3006system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
3007system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
3008system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
3009system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
3010system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
3011system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
3012system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
3013system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
3014system.iobus.pkt_count_system.bridge.master::total 122554 # Packet count per connected master and slave (bytes)
3015system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes)
3016system.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes)
3017system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
3018system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
3019system.iobus.pkt_count::total 353842 # Packet count per connected master and slave (bytes)
3020system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47640 # Cumulative packet size per connected master and slave (bytes)
3021system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
3022system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
3023system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
3024system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
3025system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
3026system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
3027system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
3028system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
3029system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
3030system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
3031system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
3032system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
3033system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
3034system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
3035system.iobus.pkt_size_system.bridge.master::total 155661 # Cumulative packet size per connected master and slave (bytes)
3036system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes)
3037system.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes)
3038system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
3039system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
3040system.iobus.pkt_size::total 7496595 # Cumulative packet size per connected master and slave (bytes)
3041system.iobus.reqLayer0.occupancy 36904500 # Layer occupancy (ticks)
3042system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
3043system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
3044system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
3045system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks)
3046system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
3047system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks)
3048system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
3049system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks)
3050system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
3051system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks)
3052system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
3053system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks)
3054system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
3055system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks)
3056system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
3057system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks)
3058system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
3059system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks)
3060system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
3061system.iobus.reqLayer23.occupancy 24719501 # Layer occupancy (ticks)
3062system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
3063system.iobus.reqLayer24.occupancy 169000 # Layer occupancy (ticks)
3064system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
3065system.iobus.reqLayer25.occupancy 36445000 # Layer occupancy (ticks)
3066system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
3067system.iobus.reqLayer26.occupancy 115000 # Layer occupancy (ticks)
3068system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
3069system.iobus.reqLayer27.occupancy 565389979 # Layer occupancy (ticks)
3070system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
3071system.iobus.reqLayer28.occupancy 44500 # Layer occupancy (ticks)
3072system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
3073system.iobus.respLayer0.occupancy 92662000 # Layer occupancy (ticks)
3074system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
3075system.iobus.respLayer3.occupancy 147904000 # Layer occupancy (ticks)
3076system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
3077system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
3078system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
3079system.iocache.tags.replacements 115596 # number of replacements
3080system.iocache.tags.tagsinuse 11.294963 # Cycle average of tags in use
3081system.iocache.tags.total_refs 4 # Total number of references to valid blocks.
3082system.iocache.tags.sampled_refs 115612 # Sample count of references to valid blocks.
3083system.iocache.tags.avg_refs 0.000035 # Average number of references to valid blocks.
3084system.iocache.tags.warmup_cycle 9125681000000 # Cycle when the warmup percentage was hit.
3085system.iocache.tags.occ_blocks::realview.ethernet 7.424342 # Average occupied blocks per requestor
3086system.iocache.tags.occ_blocks::realview.ide 3.870620 # Average occupied blocks per requestor
3087system.iocache.tags.occ_percent::realview.ethernet 0.464021 # Average percentage of cache occupancy
3088system.iocache.tags.occ_percent::realview.ide 0.241914 # Average percentage of cache occupancy
3089system.iocache.tags.occ_percent::total 0.705935 # Average percentage of cache occupancy
3090system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
3091system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
3092system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
3093system.iocache.tags.tag_accesses 1040789 # Number of tag accesses
3094system.iocache.tags.data_accesses 1040789 # Number of data accesses
3095system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
3096system.iocache.ReadReq_misses::realview.ide 8876 # number of ReadReq misses
3097system.iocache.ReadReq_misses::total 8913 # number of ReadReq misses
3098system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
3099system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
3100system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
3101system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
3102system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
3103system.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses
3104system.iocache.demand_misses::total 8916 # number of demand (read+write) misses
3105system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
3106system.iocache.overall_misses::realview.ide 8876 # number of overall misses
3107system.iocache.overall_misses::total 8916 # number of overall misses
3108system.iocache.ReadReq_miss_latency::realview.ethernet 5200000 # number of ReadReq miss cycles
3109system.iocache.ReadReq_miss_latency::realview.ide 1711011512 # number of ReadReq miss cycles
3110system.iocache.ReadReq_miss_latency::total 1716211512 # number of ReadReq miss cycles
3111system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
3112system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
3113system.iocache.WriteLineReq_miss_latency::realview.ide 13978863467 # number of WriteLineReq miss cycles
3114system.iocache.WriteLineReq_miss_latency::total 13978863467 # number of WriteLineReq miss cycles
3115system.iocache.demand_miss_latency::realview.ethernet 5569000 # number of demand (read+write) miss cycles
3116system.iocache.demand_miss_latency::realview.ide 1711011512 # number of demand (read+write) miss cycles
3117system.iocache.demand_miss_latency::total 1716580512 # number of demand (read+write) miss cycles
3118system.iocache.overall_miss_latency::realview.ethernet 5569000 # number of overall miss cycles
3119system.iocache.overall_miss_latency::realview.ide 1711011512 # number of overall miss cycles
3120system.iocache.overall_miss_latency::total 1716580512 # number of overall miss cycles
3121system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
3122system.iocache.ReadReq_accesses::realview.ide 8876 # number of ReadReq accesses(hits+misses)
3123system.iocache.ReadReq_accesses::total 8913 # number of ReadReq accesses(hits+misses)
3124system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
3125system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
3126system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
3127system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
3128system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
3129system.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses
3130system.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses
3131system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
3132system.iocache.overall_accesses::realview.ide 8876 # number of overall (read+write) accesses
3133system.iocache.overall_accesses::total 8916 # number of overall (read+write) accesses
3134system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
3135system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
3136system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
3137system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
3138system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
3139system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
3140system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
3141system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
3142system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
3143system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
3144system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
3145system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
3146system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
3147system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541 # average ReadReq miss latency
3148system.iocache.ReadReq_avg_miss_latency::realview.ide 192768.309148 # average ReadReq miss latency
3149system.iocache.ReadReq_avg_miss_latency::total 192551.499159 # average ReadReq miss latency
3150system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
3151system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
3152system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130976.533496 # average WriteLineReq miss latency
3153system.iocache.WriteLineReq_avg_miss_latency::total 130976.533496 # average WriteLineReq miss latency
3154system.iocache.demand_avg_miss_latency::realview.ethernet 139225 # average overall miss latency
3155system.iocache.demand_avg_miss_latency::realview.ide 192768.309148 # average overall miss latency
3156system.iocache.demand_avg_miss_latency::total 192528.096904 # average overall miss latency
3157system.iocache.overall_avg_miss_latency::realview.ethernet 139225 # average overall miss latency
3158system.iocache.overall_avg_miss_latency::realview.ide 192768.309148 # average overall miss latency
3159system.iocache.overall_avg_miss_latency::total 192528.096904 # average overall miss latency
3160system.iocache.blocked_cycles::no_mshrs 36708 # number of cycles access was blocked
3161system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
3162system.iocache.blocked::no_mshrs 3726 # number of cycles access was blocked
3163system.iocache.blocked::no_targets 0 # number of cycles access was blocked
3164system.iocache.avg_blocked_cycles::no_mshrs 9.851852 # average number of cycles each access was blocked
3165system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3166system.iocache.fast_writes 0 # number of fast writes performed
3167system.iocache.cache_copies 0 # number of cache copies performed
3168system.iocache.writebacks::writebacks 106693 # number of writebacks
3169system.iocache.writebacks::total 106693 # number of writebacks
3170system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
3171system.iocache.ReadReq_mshr_misses::realview.ide 8876 # number of ReadReq MSHR misses
3172system.iocache.ReadReq_mshr_misses::total 8913 # number of ReadReq MSHR misses
3173system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
3174system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
3175system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
3176system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
3177system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
3178system.iocache.demand_mshr_misses::realview.ide 8876 # number of demand (read+write) MSHR misses
3179system.iocache.demand_mshr_misses::total 8916 # number of demand (read+write) MSHR misses
3180system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
3181system.iocache.overall_mshr_misses::realview.ide 8876 # number of overall MSHR misses
3182system.iocache.overall_mshr_misses::total 8916 # number of overall MSHR misses
3183system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3350000 # number of ReadReq MSHR miss cycles
3184system.iocache.ReadReq_mshr_miss_latency::realview.ide 1267211512 # number of ReadReq MSHR miss cycles
3185system.iocache.ReadReq_mshr_miss_latency::total 1270561512 # number of ReadReq MSHR miss cycles
3186system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
3187system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
3188system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8642463467 # number of WriteLineReq MSHR miss cycles
3189system.iocache.WriteLineReq_mshr_miss_latency::total 8642463467 # number of WriteLineReq MSHR miss cycles
3190system.iocache.demand_mshr_miss_latency::realview.ethernet 3569000 # number of demand (read+write) MSHR miss cycles
3191system.iocache.demand_mshr_miss_latency::realview.ide 1267211512 # number of demand (read+write) MSHR miss cycles
3192system.iocache.demand_mshr_miss_latency::total 1270780512 # number of demand (read+write) MSHR miss cycles
3193system.iocache.overall_mshr_miss_latency::realview.ethernet 3569000 # number of overall MSHR miss cycles
3194system.iocache.overall_mshr_miss_latency::realview.ide 1267211512 # number of overall MSHR miss cycles
3195system.iocache.overall_mshr_miss_latency::total 1270780512 # number of overall MSHR miss cycles
3196system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
3197system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
3198system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
3199system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
3200system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
3201system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
3202system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
3203system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
3204system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
3205system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
3206system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
3207system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
3208system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
3209system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541 # average ReadReq mshr miss latency
3210system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142768.309148 # average ReadReq mshr miss latency
3211system.iocache.ReadReq_avg_mshr_miss_latency::total 142551.499159 # average ReadReq mshr miss latency
3212system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
3213system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
3214system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80976.533496 # average WriteLineReq mshr miss latency
3215system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80976.533496 # average WriteLineReq mshr miss latency
3216system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency
3217system.iocache.demand_avg_mshr_miss_latency::realview.ide 142768.309148 # average overall mshr miss latency
3218system.iocache.demand_avg_mshr_miss_latency::total 142528.096904 # average overall mshr miss latency
3219system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency
3220system.iocache.overall_avg_mshr_miss_latency::realview.ide 142768.309148 # average overall mshr miss latency
3221system.iocache.overall_avg_mshr_miss_latency::total 142528.096904 # average overall mshr miss latency
3222system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
3223system.l2c.tags.replacements 1583129 # number of replacements
3224system.l2c.tags.tagsinuse 63158.639853 # Cycle average of tags in use
3225system.l2c.tags.total_refs 6207421 # Total number of references to valid blocks.
3226system.l2c.tags.sampled_refs 1642739 # Sample count of references to valid blocks.
3227system.l2c.tags.avg_refs 3.778702 # Average number of references to valid blocks.
3228system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
3229system.l2c.tags.occ_blocks::writebacks 20395.624897 # Average occupied blocks per requestor
3230system.l2c.tags.occ_blocks::cpu0.dtb.walker 35.797068 # Average occupied blocks per requestor
3231system.l2c.tags.occ_blocks::cpu0.itb.walker 37.096794 # Average occupied blocks per requestor
3232system.l2c.tags.occ_blocks::cpu0.inst 3244.022805 # Average occupied blocks per requestor
3233system.l2c.tags.occ_blocks::cpu0.data 4223.269206 # Average occupied blocks per requestor
3234system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3404.413573 # Average occupied blocks per requestor
3235system.l2c.tags.occ_blocks::cpu1.dtb.walker 297.158145 # Average occupied blocks per requestor
3236system.l2c.tags.occ_blocks::cpu1.itb.walker 465.494648 # Average occupied blocks per requestor
3237system.l2c.tags.occ_blocks::cpu1.inst 3968.740099 # Average occupied blocks per requestor
3238system.l2c.tags.occ_blocks::cpu1.data 9359.576527 # Average occupied blocks per requestor
3239system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17727.446091 # Average occupied blocks per requestor
3240system.l2c.tags.occ_percent::writebacks 0.311213 # Average percentage of cache occupancy
3241system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000546 # Average percentage of cache occupancy
3242system.l2c.tags.occ_percent::cpu0.itb.walker 0.000566 # Average percentage of cache occupancy
3243system.l2c.tags.occ_percent::cpu0.inst 0.049500 # Average percentage of cache occupancy
3244system.l2c.tags.occ_percent::cpu0.data 0.064442 # Average percentage of cache occupancy
3245system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.051947 # Average percentage of cache occupancy
3246system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004534 # Average percentage of cache occupancy
3247system.l2c.tags.occ_percent::cpu1.itb.walker 0.007103 # Average percentage of cache occupancy
3248system.l2c.tags.occ_percent::cpu1.inst 0.060558 # Average percentage of cache occupancy
3249system.l2c.tags.occ_percent::cpu1.data 0.142816 # Average percentage of cache occupancy
3250system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.270499 # Average percentage of cache occupancy
3251system.l2c.tags.occ_percent::total 0.963724 # Average percentage of cache occupancy
3252system.l2c.tags.occ_task_id_blocks::1022 10142 # Occupied blocks per task id
3253system.l2c.tags.occ_task_id_blocks::1023 206 # Occupied blocks per task id
3254system.l2c.tags.occ_task_id_blocks::1024 49262 # Occupied blocks per task id
3255system.l2c.tags.age_task_id_blocks_1022::2 1206 # Occupied blocks per task id
3256system.l2c.tags.age_task_id_blocks_1022::3 394 # Occupied blocks per task id
3257system.l2c.tags.age_task_id_blocks_1022::4 8542 # Occupied blocks per task id
3258system.l2c.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
3259system.l2c.tags.age_task_id_blocks_1023::4 205 # Occupied blocks per task id
3260system.l2c.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
3261system.l2c.tags.age_task_id_blocks_1024::1 375 # Occupied blocks per task id
3262system.l2c.tags.age_task_id_blocks_1024::2 3055 # Occupied blocks per task id
3263system.l2c.tags.age_task_id_blocks_1024::3 5795 # Occupied blocks per task id
3264system.l2c.tags.age_task_id_blocks_1024::4 39993 # Occupied blocks per task id
3265system.l2c.tags.occ_task_id_percent::1022 0.154755 # Percentage of cache occupancy per task id
3266system.l2c.tags.occ_task_id_percent::1023 0.003143 # Percentage of cache occupancy per task id
3267system.l2c.tags.occ_task_id_percent::1024 0.751678 # Percentage of cache occupancy per task id
3268system.l2c.tags.tag_accesses 79196544 # Number of tag accesses
3269system.l2c.tags.data_accesses 79196544 # Number of data accesses
3270system.l2c.WritebackDirty_hits::writebacks 2898173 # number of WritebackDirty hits
3271system.l2c.WritebackDirty_hits::total 2898173 # number of WritebackDirty hits
3272system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits
3273system.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits
3274system.l2c.UpgradeReq_hits::cpu0.data 160488 # number of UpgradeReq hits
3275system.l2c.UpgradeReq_hits::cpu1.data 150342 # number of UpgradeReq hits
3276system.l2c.UpgradeReq_hits::total 310830 # number of UpgradeReq hits
3277system.l2c.SCUpgradeReq_hits::cpu0.data 37186 # number of SCUpgradeReq hits
3278system.l2c.SCUpgradeReq_hits::cpu1.data 44723 # number of SCUpgradeReq hits
3279system.l2c.SCUpgradeReq_hits::total 81909 # number of SCUpgradeReq hits
3280system.l2c.ReadExReq_hits::cpu0.data 154261 # number of ReadExReq hits
3281system.l2c.ReadExReq_hits::cpu1.data 179531 # number of ReadExReq hits
3282system.l2c.ReadExReq_hits::total 333792 # number of ReadExReq hits
3283system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5731 # number of ReadSharedReq hits
3284system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3658 # number of ReadSharedReq hits
3285system.l2c.ReadSharedReq_hits::cpu0.inst 494823 # number of ReadSharedReq hits
3286system.l2c.ReadSharedReq_hits::cpu0.data 574885 # number of ReadSharedReq hits
3287system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 276090 # number of ReadSharedReq hits
3288system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6999 # number of ReadSharedReq hits
3289system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5287 # number of ReadSharedReq hits
3290system.l2c.ReadSharedReq_hits::cpu1.inst 532007 # number of ReadSharedReq hits
3291system.l2c.ReadSharedReq_hits::cpu1.data 626878 # number of ReadSharedReq hits
3292system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 326161 # number of ReadSharedReq hits
3293system.l2c.ReadSharedReq_hits::total 2852519 # number of ReadSharedReq hits
3294system.l2c.demand_hits::cpu0.dtb.walker 5731 # number of demand (read+write) hits
3295system.l2c.demand_hits::cpu0.itb.walker 3658 # number of demand (read+write) hits
3296system.l2c.demand_hits::cpu0.inst 494823 # number of demand (read+write) hits
3297system.l2c.demand_hits::cpu0.data 729146 # number of demand (read+write) hits
3298system.l2c.demand_hits::cpu0.l2cache.prefetcher 276090 # number of demand (read+write) hits
3299system.l2c.demand_hits::cpu1.dtb.walker 6999 # number of demand (read+write) hits
3300system.l2c.demand_hits::cpu1.itb.walker 5287 # number of demand (read+write) hits
3301system.l2c.demand_hits::cpu1.inst 532007 # number of demand (read+write) hits
3302system.l2c.demand_hits::cpu1.data 806409 # number of demand (read+write) hits
3303system.l2c.demand_hits::cpu1.l2cache.prefetcher 326161 # number of demand (read+write) hits
3304system.l2c.demand_hits::total 3186311 # number of demand (read+write) hits
3305system.l2c.overall_hits::cpu0.dtb.walker 5731 # number of overall hits
3306system.l2c.overall_hits::cpu0.itb.walker 3658 # number of overall hits
3307system.l2c.overall_hits::cpu0.inst 494823 # number of overall hits
3308system.l2c.overall_hits::cpu0.data 729146 # number of overall hits
3309system.l2c.overall_hits::cpu0.l2cache.prefetcher 276090 # number of overall hits
3310system.l2c.overall_hits::cpu1.dtb.walker 6999 # number of overall hits
3311system.l2c.overall_hits::cpu1.itb.walker 5287 # number of overall hits
3312system.l2c.overall_hits::cpu1.inst 532007 # number of overall hits
3313system.l2c.overall_hits::cpu1.data 806409 # number of overall hits
3314system.l2c.overall_hits::cpu1.l2cache.prefetcher 326161 # number of overall hits
3315system.l2c.overall_hits::total 3186311 # number of overall hits
3316system.l2c.UpgradeReq_misses::cpu0.data 60003 # number of UpgradeReq misses
3317system.l2c.UpgradeReq_misses::cpu1.data 64185 # number of UpgradeReq misses
3318system.l2c.UpgradeReq_misses::total 124188 # number of UpgradeReq misses
3319system.l2c.SCUpgradeReq_misses::cpu0.data 13364 # number of SCUpgradeReq misses
3320system.l2c.SCUpgradeReq_misses::cpu1.data 11770 # number of SCUpgradeReq misses
3321system.l2c.SCUpgradeReq_misses::total 25134 # number of SCUpgradeReq misses
3322system.l2c.ReadExReq_misses::cpu0.data 540709 # number of ReadExReq misses
3323system.l2c.ReadExReq_misses::cpu1.data 127504 # number of ReadExReq misses
3324system.l2c.ReadExReq_misses::total 668213 # number of ReadExReq misses
3325system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2216 # number of ReadSharedReq misses
3326system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2032 # number of ReadSharedReq misses
3327system.l2c.ReadSharedReq_misses::cpu0.inst 61109 # number of ReadSharedReq misses
3328system.l2c.ReadSharedReq_misses::cpu0.data 146627 # number of ReadSharedReq misses
3329system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 303108 # number of ReadSharedReq misses
3330system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3029 # number of ReadSharedReq misses
3331system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2795 # number of ReadSharedReq misses
3332system.l2c.ReadSharedReq_misses::cpu1.inst 49780 # number of ReadSharedReq misses
3333system.l2c.ReadSharedReq_misses::cpu1.data 138724 # number of ReadSharedReq misses
3334system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 244242 # number of ReadSharedReq misses
3335system.l2c.ReadSharedReq_misses::total 953662 # number of ReadSharedReq misses
3336system.l2c.demand_misses::cpu0.dtb.walker 2216 # number of demand (read+write) misses
3337system.l2c.demand_misses::cpu0.itb.walker 2032 # number of demand (read+write) misses
3338system.l2c.demand_misses::cpu0.inst 61109 # number of demand (read+write) misses
3339system.l2c.demand_misses::cpu0.data 687336 # number of demand (read+write) misses
3340system.l2c.demand_misses::cpu0.l2cache.prefetcher 303108 # number of demand (read+write) misses
3341system.l2c.demand_misses::cpu1.dtb.walker 3029 # number of demand (read+write) misses
3342system.l2c.demand_misses::cpu1.itb.walker 2795 # number of demand (read+write) misses
3343system.l2c.demand_misses::cpu1.inst 49780 # number of demand (read+write) misses
3344system.l2c.demand_misses::cpu1.data 266228 # number of demand (read+write) misses
3345system.l2c.demand_misses::cpu1.l2cache.prefetcher 244242 # number of demand (read+write) misses
3346system.l2c.demand_misses::total 1621875 # number of demand (read+write) misses
3347system.l2c.overall_misses::cpu0.dtb.walker 2216 # number of overall misses
3348system.l2c.overall_misses::cpu0.itb.walker 2032 # number of overall misses
3349system.l2c.overall_misses::cpu0.inst 61109 # number of overall misses
3350system.l2c.overall_misses::cpu0.data 687336 # number of overall misses
3351system.l2c.overall_misses::cpu0.l2cache.prefetcher 303108 # number of overall misses
3352system.l2c.overall_misses::cpu1.dtb.walker 3029 # number of overall misses
3353system.l2c.overall_misses::cpu1.itb.walker 2795 # number of overall misses
3354system.l2c.overall_misses::cpu1.inst 49780 # number of overall misses
3355system.l2c.overall_misses::cpu1.data 266228 # number of overall misses
3356system.l2c.overall_misses::cpu1.l2cache.prefetcher 244242 # number of overall misses
3357system.l2c.overall_misses::total 1621875 # number of overall misses
3358system.l2c.UpgradeReq_miss_latency::cpu0.data 974602500 # number of UpgradeReq miss cycles
3359system.l2c.UpgradeReq_miss_latency::cpu1.data 1153364500 # number of UpgradeReq miss cycles
3360system.l2c.UpgradeReq_miss_latency::total 2127967000 # number of UpgradeReq miss cycles
3361system.l2c.SCUpgradeReq_miss_latency::cpu0.data 208392500 # number of SCUpgradeReq miss cycles
3362system.l2c.SCUpgradeReq_miss_latency::cpu1.data 213995000 # number of SCUpgradeReq miss cycles
3363system.l2c.SCUpgradeReq_miss_latency::total 422387500 # number of SCUpgradeReq miss cycles
3364system.l2c.ReadExReq_miss_latency::cpu0.data 89500490493 # number of ReadExReq miss cycles
3365system.l2c.ReadExReq_miss_latency::cpu1.data 18793488998 # number of ReadExReq miss cycles
3366system.l2c.ReadExReq_miss_latency::total 108293979491 # number of ReadExReq miss cycles
3367system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 316188000 # number of ReadSharedReq miss cycles
3368system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 293419000 # number of ReadSharedReq miss cycles
3369system.l2c.ReadSharedReq_miss_latency::cpu0.inst 8381886002 # number of ReadSharedReq miss cycles
3370system.l2c.ReadSharedReq_miss_latency::cpu0.data 21271080498 # number of ReadSharedReq miss cycles
3371system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 54991951248 # number of ReadSharedReq miss cycles
3372system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 433939500 # number of ReadSharedReq miss cycles
3373system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 397141000 # number of ReadSharedReq miss cycles
3374system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6825711500 # number of ReadSharedReq miss cycles
3375system.l2c.ReadSharedReq_miss_latency::cpu1.data 19972888998 # number of ReadSharedReq miss cycles
3376system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 43219182868 # number of ReadSharedReq miss cycles
3377system.l2c.ReadSharedReq_miss_latency::total 156103388614 # number of ReadSharedReq miss cycles
3378system.l2c.demand_miss_latency::cpu0.dtb.walker 316188000 # number of demand (read+write) miss cycles
3379system.l2c.demand_miss_latency::cpu0.itb.walker 293419000 # number of demand (read+write) miss cycles
3380system.l2c.demand_miss_latency::cpu0.inst 8381886002 # number of demand (read+write) miss cycles
3381system.l2c.demand_miss_latency::cpu0.data 110771570991 # number of demand (read+write) miss cycles
3382system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 54991951248 # number of demand (read+write) miss cycles
3383system.l2c.demand_miss_latency::cpu1.dtb.walker 433939500 # number of demand (read+write) miss cycles
3384system.l2c.demand_miss_latency::cpu1.itb.walker 397141000 # number of demand (read+write) miss cycles
3385system.l2c.demand_miss_latency::cpu1.inst 6825711500 # number of demand (read+write) miss cycles
3386system.l2c.demand_miss_latency::cpu1.data 38766377996 # number of demand (read+write) miss cycles
3387system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 43219182868 # number of demand (read+write) miss cycles
3388system.l2c.demand_miss_latency::total 264397368105 # number of demand (read+write) miss cycles
3389system.l2c.overall_miss_latency::cpu0.dtb.walker 316188000 # number of overall miss cycles
3390system.l2c.overall_miss_latency::cpu0.itb.walker 293419000 # number of overall miss cycles
3391system.l2c.overall_miss_latency::cpu0.inst 8381886002 # number of overall miss cycles
3392system.l2c.overall_miss_latency::cpu0.data 110771570991 # number of overall miss cycles
3393system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 54991951248 # number of overall miss cycles
3394system.l2c.overall_miss_latency::cpu1.dtb.walker 433939500 # number of overall miss cycles
3395system.l2c.overall_miss_latency::cpu1.itb.walker 397141000 # number of overall miss cycles
3396system.l2c.overall_miss_latency::cpu1.inst 6825711500 # number of overall miss cycles
3397system.l2c.overall_miss_latency::cpu1.data 38766377996 # number of overall miss cycles
3398system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 43219182868 # number of overall miss cycles
3399system.l2c.overall_miss_latency::total 264397368105 # number of overall miss cycles
3400system.l2c.WritebackDirty_accesses::writebacks 2898173 # number of WritebackDirty accesses(hits+misses)
3401system.l2c.WritebackDirty_accesses::total 2898173 # number of WritebackDirty accesses(hits+misses)
3402system.l2c.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses)
3403system.l2c.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses)
3404system.l2c.UpgradeReq_accesses::cpu0.data 220491 # number of UpgradeReq accesses(hits+misses)
3405system.l2c.UpgradeReq_accesses::cpu1.data 214527 # number of UpgradeReq accesses(hits+misses)
3406system.l2c.UpgradeReq_accesses::total 435018 # number of UpgradeReq accesses(hits+misses)
3407system.l2c.SCUpgradeReq_accesses::cpu0.data 50550 # number of SCUpgradeReq accesses(hits+misses)
3408system.l2c.SCUpgradeReq_accesses::cpu1.data 56493 # number of SCUpgradeReq accesses(hits+misses)
3409system.l2c.SCUpgradeReq_accesses::total 107043 # number of SCUpgradeReq accesses(hits+misses)
3410system.l2c.ReadExReq_accesses::cpu0.data 694970 # number of ReadExReq accesses(hits+misses)
3411system.l2c.ReadExReq_accesses::cpu1.data 307035 # number of ReadExReq accesses(hits+misses)
3412system.l2c.ReadExReq_accesses::total 1002005 # number of ReadExReq accesses(hits+misses)
3413system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7947 # number of ReadSharedReq accesses(hits+misses)
3414system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5690 # number of ReadSharedReq accesses(hits+misses)
3415system.l2c.ReadSharedReq_accesses::cpu0.inst 555932 # number of ReadSharedReq accesses(hits+misses)
3416system.l2c.ReadSharedReq_accesses::cpu0.data 721512 # number of ReadSharedReq accesses(hits+misses)
3417system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 579198 # number of ReadSharedReq accesses(hits+misses)
3418system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 10028 # number of ReadSharedReq accesses(hits+misses)
3419system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 8082 # number of ReadSharedReq accesses(hits+misses)
3420system.l2c.ReadSharedReq_accesses::cpu1.inst 581787 # number of ReadSharedReq accesses(hits+misses)
3421system.l2c.ReadSharedReq_accesses::cpu1.data 765602 # number of ReadSharedReq accesses(hits+misses)
3422system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 570403 # number of ReadSharedReq accesses(hits+misses)
3423system.l2c.ReadSharedReq_accesses::total 3806181 # number of ReadSharedReq accesses(hits+misses)
3424system.l2c.demand_accesses::cpu0.dtb.walker 7947 # number of demand (read+write) accesses
3425system.l2c.demand_accesses::cpu0.itb.walker 5690 # number of demand (read+write) accesses
3426system.l2c.demand_accesses::cpu0.inst 555932 # number of demand (read+write) accesses
3427system.l2c.demand_accesses::cpu0.data 1416482 # number of demand (read+write) accesses
3428system.l2c.demand_accesses::cpu0.l2cache.prefetcher 579198 # number of demand (read+write) accesses
3429system.l2c.demand_accesses::cpu1.dtb.walker 10028 # number of demand (read+write) accesses
3430system.l2c.demand_accesses::cpu1.itb.walker 8082 # number of demand (read+write) accesses
3431system.l2c.demand_accesses::cpu1.inst 581787 # number of demand (read+write) accesses
3432system.l2c.demand_accesses::cpu1.data 1072637 # number of demand (read+write) accesses
3433system.l2c.demand_accesses::cpu1.l2cache.prefetcher 570403 # number of demand (read+write) accesses
3434system.l2c.demand_accesses::total 4808186 # number of demand (read+write) accesses
3435system.l2c.overall_accesses::cpu0.dtb.walker 7947 # number of overall (read+write) accesses
3436system.l2c.overall_accesses::cpu0.itb.walker 5690 # number of overall (read+write) accesses
3437system.l2c.overall_accesses::cpu0.inst 555932 # number of overall (read+write) accesses
3438system.l2c.overall_accesses::cpu0.data 1416482 # number of overall (read+write) accesses
3439system.l2c.overall_accesses::cpu0.l2cache.prefetcher 579198 # number of overall (read+write) accesses
3440system.l2c.overall_accesses::cpu1.dtb.walker 10028 # number of overall (read+write) accesses
3441system.l2c.overall_accesses::cpu1.itb.walker 8082 # number of overall (read+write) accesses
3442system.l2c.overall_accesses::cpu1.inst 581787 # number of overall (read+write) accesses
3443system.l2c.overall_accesses::cpu1.data 1072637 # number of overall (read+write) accesses
3444system.l2c.overall_accesses::cpu1.l2cache.prefetcher 570403 # number of overall (read+write) accesses
3445system.l2c.overall_accesses::total 4808186 # number of overall (read+write) accesses
3446system.l2c.UpgradeReq_miss_rate::cpu0.data 0.272134 # miss rate for UpgradeReq accesses
3447system.l2c.UpgradeReq_miss_rate::cpu1.data 0.299193 # miss rate for UpgradeReq accesses
3448system.l2c.UpgradeReq_miss_rate::total 0.285478 # miss rate for UpgradeReq accesses
3449system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.264372 # miss rate for SCUpgradeReq accesses
3450system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.208344 # miss rate for SCUpgradeReq accesses
3451system.l2c.SCUpgradeReq_miss_rate::total 0.234803 # miss rate for SCUpgradeReq accesses
3452system.l2c.ReadExReq_miss_rate::cpu0.data 0.778032 # miss rate for ReadExReq accesses
3453system.l2c.ReadExReq_miss_rate::cpu1.data 0.415275 # miss rate for ReadExReq accesses
3454system.l2c.ReadExReq_miss_rate::total 0.666876 # miss rate for ReadExReq accesses
3455system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.278847 # miss rate for ReadSharedReq accesses
3456system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.357118 # miss rate for ReadSharedReq accesses
3457system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.109922 # miss rate for ReadSharedReq accesses
3458system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.203222 # miss rate for ReadSharedReq accesses
3459system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.523324 # miss rate for ReadSharedReq accesses
3460system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.302054 # miss rate for ReadSharedReq accesses
3461system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.345830 # miss rate for ReadSharedReq accesses
3462system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.085564 # miss rate for ReadSharedReq accesses
3463system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.181196 # miss rate for ReadSharedReq accesses
3464system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.428192 # miss rate for ReadSharedReq accesses
3465system.l2c.ReadSharedReq_miss_rate::total 0.250556 # miss rate for ReadSharedReq accesses
3466system.l2c.demand_miss_rate::cpu0.dtb.walker 0.278847 # miss rate for demand accesses
3467system.l2c.demand_miss_rate::cpu0.itb.walker 0.357118 # miss rate for demand accesses
3468system.l2c.demand_miss_rate::cpu0.inst 0.109922 # miss rate for demand accesses
3469system.l2c.demand_miss_rate::cpu0.data 0.485242 # miss rate for demand accesses
3470system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.523324 # miss rate for demand accesses
3471system.l2c.demand_miss_rate::cpu1.dtb.walker 0.302054 # miss rate for demand accesses
3472system.l2c.demand_miss_rate::cpu1.itb.walker 0.345830 # miss rate for demand accesses
3473system.l2c.demand_miss_rate::cpu1.inst 0.085564 # miss rate for demand accesses
3474system.l2c.demand_miss_rate::cpu1.data 0.248200 # miss rate for demand accesses
3475system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.428192 # miss rate for demand accesses
3476system.l2c.demand_miss_rate::total 0.337315 # miss rate for demand accesses
3477system.l2c.overall_miss_rate::cpu0.dtb.walker 0.278847 # miss rate for overall accesses
3478system.l2c.overall_miss_rate::cpu0.itb.walker 0.357118 # miss rate for overall accesses
3479system.l2c.overall_miss_rate::cpu0.inst 0.109922 # miss rate for overall accesses
3480system.l2c.overall_miss_rate::cpu0.data 0.485242 # miss rate for overall accesses
3481system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.523324 # miss rate for overall accesses
3482system.l2c.overall_miss_rate::cpu1.dtb.walker 0.302054 # miss rate for overall accesses
3483system.l2c.overall_miss_rate::cpu1.itb.walker 0.345830 # miss rate for overall accesses
3484system.l2c.overall_miss_rate::cpu1.inst 0.085564 # miss rate for overall accesses
3485system.l2c.overall_miss_rate::cpu1.data 0.248200 # miss rate for overall accesses
3486system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.428192 # miss rate for overall accesses
3487system.l2c.overall_miss_rate::total 0.337315 # miss rate for overall accesses
3488system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16242.562872 # average UpgradeReq miss latency
3489system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17969.377580 # average UpgradeReq miss latency
3490system.l2c.UpgradeReq_avg_miss_latency::total 17135.045254 # average UpgradeReq miss latency
3491system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15593.572284 # average SCUpgradeReq miss latency
3492system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 18181.393373 # average SCUpgradeReq miss latency
3493system.l2c.SCUpgradeReq_avg_miss_latency::total 16805.422933 # average SCUpgradeReq miss latency
3494system.l2c.ReadExReq_avg_miss_latency::cpu0.data 165524.321757 # average ReadExReq miss latency
3495system.l2c.ReadExReq_avg_miss_latency::cpu1.data 147395.289544 # average ReadExReq miss latency
3496system.l2c.ReadExReq_avg_miss_latency::total 162065.059331 # average ReadExReq miss latency
3497system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 142684.115523 # average ReadSharedReq miss latency
3498system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 144399.114173 # average ReadSharedReq miss latency
3499system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 137162.872932 # average ReadSharedReq miss latency
3500system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 145069.328964 # average ReadSharedReq miss latency
3501system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 181426.921256 # average ReadSharedReq miss latency
3502system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 143261.637504 # average ReadSharedReq miss latency
3503system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 142089.803220 # average ReadSharedReq miss latency
3504system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137117.547208 # average ReadSharedReq miss latency
3505system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 143975.728771 # average ReadSharedReq miss latency
3506system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 176952.296771 # average ReadSharedReq miss latency
3507system.l2c.ReadSharedReq_avg_miss_latency::total 163688.380804 # average ReadSharedReq miss latency
3508system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 142684.115523 # average overall miss latency
3509system.l2c.demand_avg_miss_latency::cpu0.itb.walker 144399.114173 # average overall miss latency
3510system.l2c.demand_avg_miss_latency::cpu0.inst 137162.872932 # average overall miss latency
3511system.l2c.demand_avg_miss_latency::cpu0.data 161160.729237 # average overall miss latency
3512system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 181426.921256 # average overall miss latency
3513system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 143261.637504 # average overall miss latency
3514system.l2c.demand_avg_miss_latency::cpu1.itb.walker 142089.803220 # average overall miss latency
3515system.l2c.demand_avg_miss_latency::cpu1.inst 137117.547208 # average overall miss latency
3516system.l2c.demand_avg_miss_latency::cpu1.data 145613.451613 # average overall miss latency
3517system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 176952.296771 # average overall miss latency
3518system.l2c.demand_avg_miss_latency::total 163019.571857 # average overall miss latency
3519system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 142684.115523 # average overall miss latency
3520system.l2c.overall_avg_miss_latency::cpu0.itb.walker 144399.114173 # average overall miss latency
3521system.l2c.overall_avg_miss_latency::cpu0.inst 137162.872932 # average overall miss latency
3522system.l2c.overall_avg_miss_latency::cpu0.data 161160.729237 # average overall miss latency
3523system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 181426.921256 # average overall miss latency
3524system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 143261.637504 # average overall miss latency
3525system.l2c.overall_avg_miss_latency::cpu1.itb.walker 142089.803220 # average overall miss latency
3526system.l2c.overall_avg_miss_latency::cpu1.inst 137117.547208 # average overall miss latency
3527system.l2c.overall_avg_miss_latency::cpu1.data 145613.451613 # average overall miss latency
3528system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 176952.296771 # average overall miss latency
3529system.l2c.overall_avg_miss_latency::total 163019.571857 # average overall miss latency
3530system.l2c.blocked_cycles::no_mshrs 10461 # number of cycles access was blocked
3531system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
3532system.l2c.blocked::no_mshrs 107 # number of cycles access was blocked
3533system.l2c.blocked::no_targets 0 # number of cycles access was blocked
3534system.l2c.avg_blocked_cycles::no_mshrs 97.766355 # average number of cycles each access was blocked
3535system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3536system.l2c.fast_writes 0 # number of fast writes performed
3537system.l2c.cache_copies 0 # number of cache copies performed
3538system.l2c.writebacks::writebacks 1242151 # number of writebacks
3539system.l2c.writebacks::total 1242151 # number of writebacks
3540system.l2c.ReadExReq_mshr_hits::cpu0.data 1 # number of ReadExReq MSHR hits
3541system.l2c.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits
3542system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 210 # number of ReadSharedReq MSHR hits
3543system.l2c.ReadSharedReq_mshr_hits::cpu0.data 653 # number of ReadSharedReq MSHR hits
3544system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 13 # number of ReadSharedReq MSHR hits
3545system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 244 # number of ReadSharedReq MSHR hits
3546system.l2c.ReadSharedReq_mshr_hits::cpu1.data 263 # number of ReadSharedReq MSHR hits
3547system.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadSharedReq MSHR hits
3548system.l2c.ReadSharedReq_mshr_hits::total 1384 # number of ReadSharedReq MSHR hits
3549system.l2c.demand_mshr_hits::cpu0.inst 210 # number of demand (read+write) MSHR hits
3550system.l2c.demand_mshr_hits::cpu0.data 654 # number of demand (read+write) MSHR hits
3551system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 13 # number of demand (read+write) MSHR hits
3552system.l2c.demand_mshr_hits::cpu1.inst 244 # number of demand (read+write) MSHR hits
3553system.l2c.demand_mshr_hits::cpu1.data 263 # number of demand (read+write) MSHR hits
3554system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits
3555system.l2c.demand_mshr_hits::total 1385 # number of demand (read+write) MSHR hits
3556system.l2c.overall_mshr_hits::cpu0.inst 210 # number of overall MSHR hits
3557system.l2c.overall_mshr_hits::cpu0.data 654 # number of overall MSHR hits
3558system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 13 # number of overall MSHR hits
3559system.l2c.overall_mshr_hits::cpu1.inst 244 # number of overall MSHR hits
3560system.l2c.overall_mshr_hits::cpu1.data 263 # number of overall MSHR hits
3561system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits
3562system.l2c.overall_mshr_hits::total 1385 # number of overall MSHR hits
3563system.l2c.CleanEvict_mshr_misses::writebacks 60824 # number of CleanEvict MSHR misses
3564system.l2c.CleanEvict_mshr_misses::total 60824 # number of CleanEvict MSHR misses
3565system.l2c.UpgradeReq_mshr_misses::cpu0.data 60003 # number of UpgradeReq MSHR misses
3566system.l2c.UpgradeReq_mshr_misses::cpu1.data 64185 # number of UpgradeReq MSHR misses
3567system.l2c.UpgradeReq_mshr_misses::total 124188 # number of UpgradeReq MSHR misses
3568system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 13364 # number of SCUpgradeReq MSHR misses
3569system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11770 # number of SCUpgradeReq MSHR misses
3570system.l2c.SCUpgradeReq_mshr_misses::total 25134 # number of SCUpgradeReq MSHR misses
3571system.l2c.ReadExReq_mshr_misses::cpu0.data 540708 # number of ReadExReq MSHR misses
3572system.l2c.ReadExReq_mshr_misses::cpu1.data 127504 # number of ReadExReq MSHR misses
3573system.l2c.ReadExReq_mshr_misses::total 668212 # number of ReadExReq MSHR misses
3574system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2216 # number of ReadSharedReq MSHR misses
3575system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2032 # number of ReadSharedReq MSHR misses
3576system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 60899 # number of ReadSharedReq MSHR misses
3577system.l2c.ReadSharedReq_mshr_misses::cpu0.data 145974 # number of ReadSharedReq MSHR misses
3578system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 303095 # number of ReadSharedReq MSHR misses
3579system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 3029 # number of ReadSharedReq MSHR misses
3580system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2795 # number of ReadSharedReq MSHR misses
3581system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 49536 # number of ReadSharedReq MSHR misses
3582system.l2c.ReadSharedReq_mshr_misses::cpu1.data 138461 # number of ReadSharedReq MSHR misses
3583system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 244241 # number of ReadSharedReq MSHR misses
3584system.l2c.ReadSharedReq_mshr_misses::total 952278 # number of ReadSharedReq MSHR misses
3585system.l2c.demand_mshr_misses::cpu0.dtb.walker 2216 # number of demand (read+write) MSHR misses
3586system.l2c.demand_mshr_misses::cpu0.itb.walker 2032 # number of demand (read+write) MSHR misses
3587system.l2c.demand_mshr_misses::cpu0.inst 60899 # number of demand (read+write) MSHR misses
3588system.l2c.demand_mshr_misses::cpu0.data 686682 # number of demand (read+write) MSHR misses
3589system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 303095 # number of demand (read+write) MSHR misses
3590system.l2c.demand_mshr_misses::cpu1.dtb.walker 3029 # number of demand (read+write) MSHR misses
3591system.l2c.demand_mshr_misses::cpu1.itb.walker 2795 # number of demand (read+write) MSHR misses
3592system.l2c.demand_mshr_misses::cpu1.inst 49536 # number of demand (read+write) MSHR misses
3593system.l2c.demand_mshr_misses::cpu1.data 265965 # number of demand (read+write) MSHR misses
3594system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 244241 # number of demand (read+write) MSHR misses
3595system.l2c.demand_mshr_misses::total 1620490 # number of demand (read+write) MSHR misses
3596system.l2c.overall_mshr_misses::cpu0.dtb.walker 2216 # number of overall MSHR misses
3597system.l2c.overall_mshr_misses::cpu0.itb.walker 2032 # number of overall MSHR misses
3598system.l2c.overall_mshr_misses::cpu0.inst 60899 # number of overall MSHR misses
3599system.l2c.overall_mshr_misses::cpu0.data 686682 # number of overall MSHR misses
3600system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 303095 # number of overall MSHR misses
3601system.l2c.overall_mshr_misses::cpu1.dtb.walker 3029 # number of overall MSHR misses
3602system.l2c.overall_mshr_misses::cpu1.itb.walker 2795 # number of overall MSHR misses
3603system.l2c.overall_mshr_misses::cpu1.inst 49536 # number of overall MSHR misses
3604system.l2c.overall_mshr_misses::cpu1.data 265965 # number of overall MSHR misses
3605system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 244241 # number of overall MSHR misses
3606system.l2c.overall_mshr_misses::total 1620490 # number of overall MSHR misses
3607system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
3608system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32879 # number of ReadReq MSHR uncacheable
3609system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
3610system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5458 # number of ReadReq MSHR uncacheable
3611system.l2c.ReadReq_mshr_uncacheable::total 59697 # number of ReadReq MSHR uncacheable
3612system.l2c.WriteReq_mshr_uncacheable::cpu0.data 32981 # number of WriteReq MSHR uncacheable
3613system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5292 # number of WriteReq MSHR uncacheable
3614system.l2c.WriteReq_mshr_uncacheable::total 38273 # number of WriteReq MSHR uncacheable
3615system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
3616system.l2c.overall_mshr_uncacheable_misses::cpu0.data 65860 # number of overall MSHR uncacheable misses
3617system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
3618system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10750 # number of overall MSHR uncacheable misses
3619system.l2c.overall_mshr_uncacheable_misses::total 97970 # number of overall MSHR uncacheable misses
3620system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4411059004 # number of UpgradeReq MSHR miss cycles
3621system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4718897004 # number of UpgradeReq MSHR miss cycles
3622system.l2c.UpgradeReq_mshr_miss_latency::total 9129956008 # number of UpgradeReq MSHR miss cycles
3623system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 1022873502 # number of SCUpgradeReq MSHR miss cycles
3624system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 899918499 # number of SCUpgradeReq MSHR miss cycles
3625system.l2c.SCUpgradeReq_mshr_miss_latency::total 1922792001 # number of SCUpgradeReq MSHR miss cycles
3626system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 84093329493 # number of ReadExReq MSHR miss cycles
3627system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 17518448998 # number of ReadExReq MSHR miss cycles
3628system.l2c.ReadExReq_mshr_miss_latency::total 101611778491 # number of ReadExReq MSHR miss cycles
3629system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 294028000 # number of ReadSharedReq MSHR miss cycles
3630system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 273099000 # number of ReadSharedReq MSHR miss cycles
3631system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 7748135502 # number of ReadSharedReq MSHR miss cycles
3632system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19727243498 # number of ReadSharedReq MSHR miss cycles
3633system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 51959564758 # number of ReadSharedReq MSHR miss cycles
3634system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 403649500 # number of ReadSharedReq MSHR miss cycles
3635system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 369191000 # number of ReadSharedReq MSHR miss cycles
3636system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 6300483000 # number of ReadSharedReq MSHR miss cycles
3637system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 18553666498 # number of ReadSharedReq MSHR miss cycles
3638system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 40776701375 # number of ReadSharedReq MSHR miss cycles
3639system.l2c.ReadSharedReq_mshr_miss_latency::total 146405762131 # number of ReadSharedReq MSHR miss cycles
3640system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 294028000 # number of demand (read+write) MSHR miss cycles
3641system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 273099000 # number of demand (read+write) MSHR miss cycles
3642system.l2c.demand_mshr_miss_latency::cpu0.inst 7748135502 # number of demand (read+write) MSHR miss cycles
3643system.l2c.demand_mshr_miss_latency::cpu0.data 103820572991 # number of demand (read+write) MSHR miss cycles
3644system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 51959564758 # number of demand (read+write) MSHR miss cycles
3645system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 403649500 # number of demand (read+write) MSHR miss cycles
3646system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 369191000 # number of demand (read+write) MSHR miss cycles
3647system.l2c.demand_mshr_miss_latency::cpu1.inst 6300483000 # number of demand (read+write) MSHR miss cycles
3648system.l2c.demand_mshr_miss_latency::cpu1.data 36072115496 # number of demand (read+write) MSHR miss cycles
3649system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 40776701375 # number of demand (read+write) MSHR miss cycles
3650system.l2c.demand_mshr_miss_latency::total 248017540622 # number of demand (read+write) MSHR miss cycles
3651system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 294028000 # number of overall MSHR miss cycles
3652system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 273099000 # number of overall MSHR miss cycles
3653system.l2c.overall_mshr_miss_latency::cpu0.inst 7748135502 # number of overall MSHR miss cycles
3654system.l2c.overall_mshr_miss_latency::cpu0.data 103820572991 # number of overall MSHR miss cycles
3655system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 51959564758 # number of overall MSHR miss cycles
3656system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 403649500 # number of overall MSHR miss cycles
3657system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 369191000 # number of overall MSHR miss cycles
3658system.l2c.overall_mshr_miss_latency::cpu1.inst 6300483000 # number of overall MSHR miss cycles
3659system.l2c.overall_mshr_miss_latency::cpu1.data 36072115496 # number of overall MSHR miss cycles
3660system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 40776701375 # number of overall MSHR miss cycles
3661system.l2c.overall_mshr_miss_latency::total 248017540622 # number of overall MSHR miss cycles
3662system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2396808000 # number of ReadReq MSHR uncacheable cycles
3663system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5447961500 # number of ReadReq MSHR uncacheable cycles
3664system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7124500 # number of ReadReq MSHR uncacheable cycles
3665system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 452516500 # number of ReadReq MSHR uncacheable cycles
3666system.l2c.ReadReq_mshr_uncacheable_latency::total 8304410500 # number of ReadReq MSHR uncacheable cycles
3667system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 5424521033 # number of WriteReq MSHR uncacheable cycles
3668system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 531333000 # number of WriteReq MSHR uncacheable cycles
3669system.l2c.WriteReq_mshr_uncacheable_latency::total 5955854033 # number of WriteReq MSHR uncacheable cycles
3670system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2396808000 # number of overall MSHR uncacheable cycles
3671system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10872482533 # number of overall MSHR uncacheable cycles
3672system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7124500 # number of overall MSHR uncacheable cycles
3673system.l2c.overall_mshr_uncacheable_latency::cpu1.data 983849500 # number of overall MSHR uncacheable cycles
3674system.l2c.overall_mshr_uncacheable_latency::total 14260264533 # number of overall MSHR uncacheable cycles
3675system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3676system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3677system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.272134 # mshr miss rate for UpgradeReq accesses
3678system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.299193 # mshr miss rate for UpgradeReq accesses
3679system.l2c.UpgradeReq_mshr_miss_rate::total 0.285478 # mshr miss rate for UpgradeReq accesses
3680system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.264372 # mshr miss rate for SCUpgradeReq accesses
3681system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.208344 # mshr miss rate for SCUpgradeReq accesses
3682system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.234803 # mshr miss rate for SCUpgradeReq accesses
3683system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.778031 # mshr miss rate for ReadExReq accesses
3684system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.415275 # mshr miss rate for ReadExReq accesses
3685system.l2c.ReadExReq_mshr_miss_rate::total 0.666875 # mshr miss rate for ReadExReq accesses
3686system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.278847 # mshr miss rate for ReadSharedReq accesses
3687system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.357118 # mshr miss rate for ReadSharedReq accesses
3688system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.109544 # mshr miss rate for ReadSharedReq accesses
3689system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.202317 # mshr miss rate for ReadSharedReq accesses
3690system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.523301 # mshr miss rate for ReadSharedReq accesses
3691system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.302054 # mshr miss rate for ReadSharedReq accesses
3692system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.345830 # mshr miss rate for ReadSharedReq accesses
3693system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.085145 # mshr miss rate for ReadSharedReq accesses
3694system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.180852 # mshr miss rate for ReadSharedReq accesses
3695system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.428190 # mshr miss rate for ReadSharedReq accesses
3696system.l2c.ReadSharedReq_mshr_miss_rate::total 0.250193 # mshr miss rate for ReadSharedReq accesses
3697system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.278847 # mshr miss rate for demand accesses
3698system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.357118 # mshr miss rate for demand accesses
3699system.l2c.demand_mshr_miss_rate::cpu0.inst 0.109544 # mshr miss rate for demand accesses
3700system.l2c.demand_mshr_miss_rate::cpu0.data 0.484780 # mshr miss rate for demand accesses
3701system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.523301 # mshr miss rate for demand accesses
3702system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.302054 # mshr miss rate for demand accesses
3703system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.345830 # mshr miss rate for demand accesses
3704system.l2c.demand_mshr_miss_rate::cpu1.inst 0.085145 # mshr miss rate for demand accesses
3705system.l2c.demand_mshr_miss_rate::cpu1.data 0.247954 # mshr miss rate for demand accesses
3706system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.428190 # mshr miss rate for demand accesses
3707system.l2c.demand_mshr_miss_rate::total 0.337027 # mshr miss rate for demand accesses
3708system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.278847 # mshr miss rate for overall accesses
3709system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.357118 # mshr miss rate for overall accesses
3710system.l2c.overall_mshr_miss_rate::cpu0.inst 0.109544 # mshr miss rate for overall accesses
3711system.l2c.overall_mshr_miss_rate::cpu0.data 0.484780 # mshr miss rate for overall accesses
3712system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.523301 # mshr miss rate for overall accesses
3713system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.302054 # mshr miss rate for overall accesses
3714system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.345830 # mshr miss rate for overall accesses
3715system.l2c.overall_mshr_miss_rate::cpu1.inst 0.085145 # mshr miss rate for overall accesses
3716system.l2c.overall_mshr_miss_rate::cpu1.data 0.247954 # mshr miss rate for overall accesses
3717system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.428190 # mshr miss rate for overall accesses
3718system.l2c.overall_mshr_miss_rate::total 0.337027 # mshr miss rate for overall accesses
3719system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73513.974368 # average UpgradeReq mshr miss latency
3720system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73520.246226 # average UpgradeReq mshr miss latency
3721system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73517.215898 # average UpgradeReq mshr miss latency
3722system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76539.471865 # average SCUpgradeReq mshr miss latency
3723system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76458.666015 # average SCUpgradeReq mshr miss latency
3724system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76501.631296 # average SCUpgradeReq mshr miss latency
3725system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 155524.478079 # average ReadExReq mshr miss latency
3726system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 137395.289544 # average ReadExReq mshr miss latency
3727system.l2c.ReadExReq_avg_mshr_miss_latency::total 152065.180648 # average ReadExReq mshr miss latency
3728system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 132684.115523 # average ReadSharedReq mshr miss latency
3729system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 134399.114173 # average ReadSharedReq mshr miss latency
3730system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127229.273092 # average ReadSharedReq mshr miss latency
3731system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 135142.172565 # average ReadSharedReq mshr miss latency
3732system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 171429.963404 # average ReadSharedReq mshr miss latency
3733system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 133261.637504 # average ReadSharedReq mshr miss latency
3734system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 132089.803220 # average ReadSharedReq mshr miss latency
3735system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127189.983043 # average ReadSharedReq mshr miss latency
3736system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 133999.223594 # average ReadSharedReq mshr miss latency
3737system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166952.728555 # average ReadSharedReq mshr miss latency
3738system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 153742.669820 # average ReadSharedReq mshr miss latency
3739system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132684.115523 # average overall mshr miss latency
3740system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 134399.114173 # average overall mshr miss latency
3741system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127229.273092 # average overall mshr miss latency
3742system.l2c.demand_avg_mshr_miss_latency::cpu0.data 151191.633086 # average overall mshr miss latency
3743system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 171429.963404 # average overall mshr miss latency
3744system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 133261.637504 # average overall mshr miss latency
3745system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 132089.803220 # average overall mshr miss latency
3746system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127189.983043 # average overall mshr miss latency
3747system.l2c.demand_avg_mshr_miss_latency::cpu1.data 135627.302450 # average overall mshr miss latency
3748system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166952.728555 # average overall mshr miss latency
3749system.l2c.demand_avg_mshr_miss_latency::total 153050.954108 # average overall mshr miss latency
3750system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132684.115523 # average overall mshr miss latency
3751system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 134399.114173 # average overall mshr miss latency
3752system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127229.273092 # average overall mshr miss latency
3753system.l2c.overall_avg_mshr_miss_latency::cpu0.data 151191.633086 # average overall mshr miss latency
3754system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 171429.963404 # average overall mshr miss latency
3755system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 133261.637504 # average overall mshr miss latency
3756system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 132089.803220 # average overall mshr miss latency
3757system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127189.983043 # average overall mshr miss latency
3758system.l2c.overall_avg_mshr_miss_latency::cpu1.data 135627.302450 # average overall mshr miss latency
3759system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166952.728555 # average overall mshr miss latency
3760system.l2c.overall_avg_mshr_miss_latency::total 153050.954108 # average overall mshr miss latency
3761system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average ReadReq mshr uncacheable latency
3762system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165697.299188 # average ReadReq mshr uncacheable latency
3763system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106335.820896 # average ReadReq mshr uncacheable latency
3764system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 82908.849395 # average ReadReq mshr uncacheable latency
3765system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 139109.343853 # average ReadReq mshr uncacheable latency
3766system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164474.122464 # average WriteReq mshr uncacheable latency
3767system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100403.061224 # average WriteReq mshr uncacheable latency
3768system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155615.029734 # average WriteReq mshr uncacheable latency
3769system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average overall mshr uncacheable latency
3770system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 165084.763635 # average overall mshr uncacheable latency
3771system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106335.820896 # average overall mshr uncacheable latency
3772system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91520.883721 # average overall mshr uncacheable latency
3773system.l2c.overall_avg_mshr_uncacheable_latency::total 145557.461805 # average overall mshr uncacheable latency
3774system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
3775system.membus.trans_dist::ReadReq 59697 # Transaction distribution
3776system.membus.trans_dist::ReadResp 1020888 # Transaction distribution
3777system.membus.trans_dist::WriteReq 38273 # Transaction distribution
3778system.membus.trans_dist::WriteResp 38273 # Transaction distribution
3779system.membus.trans_dist::WritebackDirty 1348844 # Transaction distribution
3780system.membus.trans_dist::CleanEvict 267564 # Transaction distribution
3781system.membus.trans_dist::UpgradeReq 448101 # Transaction distribution
3782system.membus.trans_dist::SCUpgradeReq 314840 # Transaction distribution
3783system.membus.trans_dist::UpgradeResp 158230 # Transaction distribution
3784system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
3785system.membus.trans_dist::ReadExReq 678893 # Transaction distribution
3786system.membus.trans_dist::ReadExResp 659308 # Transaction distribution
3787system.membus.trans_dist::ReadSharedReq 961191 # Transaction distribution
3788system.membus.trans_dist::InvalidateReq 106727 # Transaction distribution
3789system.membus.trans_dist::InvalidateResp 106727 # Transaction distribution
3790system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122554 # Packet count per connected master and slave (bytes)
3791system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes)
3792system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25446 # Packet count per connected master and slave (bytes)
3793system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5713992 # Packet count per connected master and slave (bytes)
3794system.membus.pkt_count_system.l2c.mem_side::total 5862068 # Packet count per connected master and slave (bytes)
3795system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342759 # Packet count per connected master and slave (bytes)
3796system.membus.pkt_count_system.iocache.mem_side::total 342759 # Packet count per connected master and slave (bytes)
3797system.membus.pkt_count::total 6204827 # Packet count per connected master and slave (bytes)
3798system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155661 # Cumulative packet size per connected master and slave (bytes)
3799system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes)
3800system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50892 # Cumulative packet size per connected master and slave (bytes)
3801system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 182954368 # Cumulative packet size per connected master and slave (bytes)
3802system.membus.pkt_size_system.l2c.mem_side::total 183161477 # Cumulative packet size per connected master and slave (bytes)
3803system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7272320 # Cumulative packet size per connected master and slave (bytes)
3804system.membus.pkt_size_system.iocache.mem_side::total 7272320 # Cumulative packet size per connected master and slave (bytes)
3805system.membus.pkt_size::total 190433797 # Cumulative packet size per connected master and slave (bytes)
3806system.membus.snoops 627031 # Total snoops (count)
3807system.membus.snoop_fanout::samples 4226315 # Request fanout histogram
3808system.membus.snoop_fanout::mean 1 # Request fanout histogram
3809system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3810system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3811system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3812system.membus.snoop_fanout::1 4226315 100.00% 100.00% # Request fanout histogram
3813system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3814system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3815system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3816system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3817system.membus.snoop_fanout::total 4226315 # Request fanout histogram
3818system.membus.reqLayer0.occupancy 98488499 # Layer occupancy (ticks)
3819system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3820system.membus.reqLayer1.occupancy 53000 # Layer occupancy (ticks)
3821system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3822system.membus.reqLayer2.occupancy 21525971 # Layer occupancy (ticks)
3823system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3824system.membus.reqLayer5.occupancy 9456985184 # Layer occupancy (ticks)
3825system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3826system.membus.respLayer2.occupancy 8888143010 # Layer occupancy (ticks)
3827system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3828system.membus.respLayer3.occupancy 228798971 # Layer occupancy (ticks)
3829system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3830system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3831system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3832system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3833system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3834system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3835system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3836system.realview.ethernet.txBytes 966 # Bytes Transmitted

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3874system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3875system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3876system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3877system.realview.ethernet.droppedPackets 0 # number of packets dropped
3878system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3879system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3880system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3881system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3882system.toL2Bus.snoop_filter.tot_requests 12205155 # Total number of requests made to the snoop filter.
3883system.toL2Bus.snoop_filter.hit_single_requests 6621083 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3884system.toL2Bus.snoop_filter.hit_multi_requests 1960564 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3885system.toL2Bus.snoop_filter.tot_snoops 171525 # Total number of snoops made to the snoop filter.
3886system.toL2Bus.snoop_filter.hit_single_snoops 155955 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3887system.toL2Bus.snoop_filter.hit_multi_snoops 15570 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3888system.toL2Bus.trans_dist::ReadReq 59699 # Transaction distribution
3889system.toL2Bus.trans_dist::ReadResp 4664873 # Transaction distribution
3890system.toL2Bus.trans_dist::WriteReq 38273 # Transaction distribution
3891system.toL2Bus.trans_dist::WriteResp 38273 # Transaction distribution
3892system.toL2Bus.trans_dist::WritebackDirty 4247047 # Transaction distribution
3893system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
3894system.toL2Bus.trans_dist::CleanEvict 1614803 # Transaction distribution
3895system.toL2Bus.trans_dist::UpgradeReq 750027 # Transaction distribution
3896system.toL2Bus.trans_dist::SCUpgradeReq 396749 # Transaction distribution
3897system.toL2Bus.trans_dist::UpgradeResp 1146775 # Transaction distribution
3898system.toL2Bus.trans_dist::SCUpgradeFailReq 211 # Transaction distribution
3899system.toL2Bus.trans_dist::UpgradeFailResp 211 # Transaction distribution
3900system.toL2Bus.trans_dist::ReadExReq 1140836 # Transaction distribution
3901system.toL2Bus.trans_dist::ReadExResp 1140836 # Transaction distribution
3902system.toL2Bus.trans_dist::ReadSharedReq 4612412 # Transaction distribution
3903system.toL2Bus.trans_dist::InvalidateReq 106727 # Transaction distribution
3904system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8853195 # Packet count per connected master and slave (bytes)
3905system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7749082 # Packet count per connected master and slave (bytes)
3906system.toL2Bus.pkt_count::total 16602277 # Packet count per connected master and slave (bytes)
3907system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 269317869 # Cumulative packet size per connected master and slave (bytes)
3908system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 224565592 # Cumulative packet size per connected master and slave (bytes)
3909system.toL2Bus.pkt_size::total 493883461 # Cumulative packet size per connected master and slave (bytes)
3910system.toL2Bus.snoops 3357154 # Total snoops (count)
3911system.toL2Bus.snoop_fanout::samples 8803755 # Request fanout histogram
3912system.toL2Bus.snoop_fanout::mean 0.347401 # Request fanout histogram
3913system.toL2Bus.snoop_fanout::stdev 0.479844 # Request fanout histogram
3914system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3915system.toL2Bus.snoop_fanout::0 5760896 65.44% 65.44% # Request fanout histogram
3916system.toL2Bus.snoop_fanout::1 3027289 34.39% 99.82% # Request fanout histogram
3917system.toL2Bus.snoop_fanout::2 15570 0.18% 100.00% # Request fanout histogram
3918system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3919system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3920system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3921system.toL2Bus.snoop_fanout::total 8803755 # Request fanout histogram
3922system.toL2Bus.reqLayer0.occupancy 9517655622 # Layer occupancy (ticks)
3923system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3924system.toL2Bus.snoopLayer0.occupancy 2614297 # Layer occupancy (ticks)
3925system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3926system.toL2Bus.respLayer0.occupancy 4898920623 # Layer occupancy (ticks)
3927system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3928system.toL2Bus.respLayer1.occupancy 4389147401 # Layer occupancy (ticks)
3929system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3930system.cpu0.kern.inst.arm 0 # number of arm instructions executed
3931system.cpu0.kern.inst.quiesce 12586 # number of quiesce instructions executed
3932system.cpu1.kern.inst.arm 0 # number of arm instructions executed
3933system.cpu1.kern.inst.quiesce 5763 # number of quiesce instructions executed
3934
3935---------- End Simulation Statistics ----------