1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.345385 # Number of seconds simulated
4sim_ticks 47345385235500 # Number of ticks simulated
5final_tick 47345385235500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 106392 # Simulator instruction rate (inst/s)
8host_op_rate 125133 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 5453309126 # Simulator tick rate (ticks/s)
10host_mem_usage 767036 # Number of bytes of host memory used
11host_seconds 8681.96 # Real time elapsed on the host
12sim_insts 923688991 # Number of instructions simulated
13sim_ops 1086395427 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 161152 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 146432 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 4268768 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 16023832 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 20180672 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 179840 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 156416 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 3463536 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 11559072 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 14510464 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 437312 # Number of bytes read from this memory
27system.physmem.bytes_read::total 71087496 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 4268768 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 3463536 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 7732304 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 86253568 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
34system.physmem.bytes_written::total 86274384 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 2518 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 2288 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 82652 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 250394 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 315323 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 2810 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.itb.walker 2444 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.inst 54162 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.data 180625 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.l2cache.prefetcher 226726 # Number of read requests responded to by this memory
45system.physmem.num_reads::realview.ide 6833 # Number of read requests responded to by this memory
46system.physmem.num_reads::total 1126775 # Number of read requests responded to by this memory
47system.physmem.num_writes::writebacks 1347712 # Number of write requests responded to by this memory
48system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
50system.physmem.num_writes::total 1350315 # Number of write requests responded to by this memory
51system.physmem.bw_read::cpu0.dtb.walker 3404 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.itb.walker 3093 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.inst 90162 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.data 338445 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.l2cache.prefetcher 426244 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.dtb.walker 3798 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.itb.walker 3304 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.inst 73155 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.data 244144 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.l2cache.prefetcher 306481 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::realview.ide 9237 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::total 1501466 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::cpu0.inst 90162 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu1.inst 73155 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::total 163317 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_write::writebacks 1821795 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::cpu0.data 440 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::total 1822234 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_total::writebacks 1821795 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.dtb.walker 3404 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.itb.walker 3093 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.inst 90162 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.data 338885 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.l2cache.prefetcher 426244 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.dtb.walker 3798 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.itb.walker 3304 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.inst 73155 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.data 244144 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.l2cache.prefetcher 306481 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.ide 9237 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::total 3323700 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.readReqs 1126775 # Number of read requests accepted
84system.physmem.writeReqs 2040290 # Number of write requests accepted
85system.physmem.readBursts 1126775 # Number of DRAM read bursts, including those serviced by the write queue
86system.physmem.writeBursts 2040290 # Number of DRAM write bursts, including those merged in the write queue
87system.physmem.bytesReadDRAM 72094336 # Total number of bytes read from DRAM
88system.physmem.bytesReadWrQ 19264 # Total number of bytes read from write queue
89system.physmem.bytesWritten 130093376 # Total number of bytes written to DRAM
90system.physmem.bytesReadSys 71087496 # Total read bytes from the system interface side
91system.physmem.bytesWrittenSys 130432784 # Total written bytes from the system interface side
92system.physmem.servicedByWrQ 301 # Number of DRAM read bursts serviced by the write queue
93system.physmem.mergedWrBursts 7556 # Number of DRAM write bursts merged with an existing one
94system.physmem.neitherReadNorWriteReqs 121134 # Number of requests that are neither read nor write
95system.physmem.perBankRdBursts::0 65675 # Per bank write bursts
96system.physmem.perBankRdBursts::1 75833 # Per bank write bursts
97system.physmem.perBankRdBursts::2 67256 # Per bank write bursts
98system.physmem.perBankRdBursts::3 67290 # Per bank write bursts
99system.physmem.perBankRdBursts::4 71240 # Per bank write bursts
100system.physmem.perBankRdBursts::5 82191 # Per bank write bursts
101system.physmem.perBankRdBursts::6 67013 # Per bank write bursts
102system.physmem.perBankRdBursts::7 67787 # Per bank write bursts
103system.physmem.perBankRdBursts::8 61707 # Per bank write bursts
104system.physmem.perBankRdBursts::9 85775 # Per bank write bursts
105system.physmem.perBankRdBursts::10 61014 # Per bank write bursts
106system.physmem.perBankRdBursts::11 72520 # Per bank write bursts
107system.physmem.perBankRdBursts::12 65793 # Per bank write bursts
108system.physmem.perBankRdBursts::13 74631 # Per bank write bursts
109system.physmem.perBankRdBursts::14 69278 # Per bank write bursts
110system.physmem.perBankRdBursts::15 71471 # Per bank write bursts
111system.physmem.perBankWrBursts::0 122526 # Per bank write bursts
112system.physmem.perBankWrBursts::1 130111 # Per bank write bursts
113system.physmem.perBankWrBursts::2 125889 # Per bank write bursts
114system.physmem.perBankWrBursts::3 127486 # Per bank write bursts
115system.physmem.perBankWrBursts::4 126972 # Per bank write bursts
116system.physmem.perBankWrBursts::5 136977 # Per bank write bursts
117system.physmem.perBankWrBursts::6 126845 # Per bank write bursts
118system.physmem.perBankWrBursts::7 128268 # Per bank write bursts
119system.physmem.perBankWrBursts::8 123854 # Per bank write bursts
120system.physmem.perBankWrBursts::9 125736 # Per bank write bursts
121system.physmem.perBankWrBursts::10 125360 # Per bank write bursts
122system.physmem.perBankWrBursts::11 131761 # Per bank write bursts
123system.physmem.perBankWrBursts::12 119984 # Per bank write bursts
124system.physmem.perBankWrBursts::13 126166 # Per bank write bursts
125system.physmem.perBankWrBursts::14 125889 # Per bank write bursts
126system.physmem.perBankWrBursts::15 128885 # Per bank write bursts
127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
128system.physmem.numWrRetry 614 # Number of times write queue was full causing retry
129system.physmem.totGap 47345383810500 # Total gap between requests
130system.physmem.readPktSize::0 0 # Read request sizes (log2)
131system.physmem.readPktSize::1 0 # Read request sizes (log2)
132system.physmem.readPktSize::2 0 # Read request sizes (log2)
133system.physmem.readPktSize::3 37 # Read request sizes (log2)
134system.physmem.readPktSize::4 21334 # Read request sizes (log2)
135system.physmem.readPktSize::5 0 # Read request sizes (log2)
136system.physmem.readPktSize::6 1105404 # Read request sizes (log2)
137system.physmem.writePktSize::0 0 # Write request sizes (log2)
138system.physmem.writePktSize::1 0 # Write request sizes (log2)
139system.physmem.writePktSize::2 2 # Write request sizes (log2)
140system.physmem.writePktSize::3 2601 # Write request sizes (log2)
141system.physmem.writePktSize::4 0 # Write request sizes (log2)
142system.physmem.writePktSize::5 0 # Write request sizes (log2)
143system.physmem.writePktSize::6 2037687 # Write request sizes (log2)
144system.physmem.rdQLenPdf::0 495851 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::1 234383 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::2 118863 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::3 70028 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::4 51854 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::5 39852 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::6 34830 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::7 31890 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::8 28010 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::9 7930 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::10 4174 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::11 2742 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::12 1780 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::13 1381 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::14 844 # What read queue length does an incoming req see
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161system.physmem.rdQLenPdf::17 457 # What read queue length does an incoming req see
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164system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see
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183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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192system.physmem.wrQLenPdf::16 44920 # What write queue length does an incoming req see
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195system.physmem.wrQLenPdf::19 77864 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::20 89177 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::21 97306 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::22 106336 # What write queue length does an incoming req see
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201system.physmem.wrQLenPdf::25 121861 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::26 124135 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::27 125483 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::28 131449 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::29 118558 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::30 117002 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::31 113440 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::32 105060 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::33 29238 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::34 25813 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::35 22998 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::36 20720 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::37 18797 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::38 16980 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::39 15279 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::40 13444 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::41 11652 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::42 10311 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::43 9180 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::44 8124 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::45 7426 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::46 6654 # What write queue length does an incoming req see
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224system.physmem.wrQLenPdf::48 5597 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::49 5145 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::50 4620 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::51 4249 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::52 3863 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::53 3550 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::54 3131 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::55 2559 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::56 2104 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::57 1878 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::58 1591 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::59 1280 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::60 1141 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::61 1049 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::62 1018 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::63 1502 # What write queue length does an incoming req see
240system.physmem.bytesPerActivate::samples 1131657 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::mean 178.664737 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::gmean 108.493979 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::stdev 249.059793 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::0-127 718344 63.48% 63.48% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::128-255 219262 19.38% 82.85% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::256-383 56669 5.01% 87.86% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::384-511 25497 2.25% 90.11% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::512-639 20148 1.78% 91.89% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::640-767 11584 1.02% 92.92% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::768-895 9545 0.84% 93.76% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::896-1023 8895 0.79% 94.55% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::1024-1151 61713 5.45% 100.00% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::total 1131657 # Bytes accessed per row activation
254system.physmem.rdPerTurnAround::samples 74075 # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::mean 15.207155 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::stdev 65.468886 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::0-511 74072 100.00% 100.00% # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::512-1023 1 0.00% 100.00% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::total 74075 # Reads before turning the bus around for writes
262system.physmem.wrPerTurnAround::samples 74075 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::mean 27.441228 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::gmean 19.793858 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::stdev 451.068024 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::0-1023 74039 99.95% 99.95% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::1024-2047 13 0.02% 99.97% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::2048-3071 9 0.01% 99.98% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::3072-4095 5 0.01% 99.99% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::4096-5119 2 0.00% 99.99% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::5120-6143 2 0.00% 99.99% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::26624-27647 1 0.00% 99.99% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::33792-34815 1 0.00% 100.00% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::64512-65535 3 0.00% 100.00% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::total 74075 # Writes before turning the bus around for reads
276system.physmem.totQLat 56140564025 # Total ticks spent queuing
277system.physmem.totMemAccLat 77261951525 # Total ticks spent from burst creation until serviced by the DRAM
278system.physmem.totBusLat 5632370000 # Total ticks spent in databus transfers
279system.physmem.avgQLat 49837.43 # Average queueing delay per DRAM burst
280system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
281system.physmem.avgMemAccLat 68587.43 # Average memory access latency per DRAM burst
282system.physmem.avgRdBW 1.52 # Average DRAM read bandwidth in MiByte/s
283system.physmem.avgWrBW 2.75 # Average achieved write bandwidth in MiByte/s
284system.physmem.avgRdBWSys 1.50 # Average system read bandwidth in MiByte/s
285system.physmem.avgWrBWSys 2.75 # Average system write bandwidth in MiByte/s
286system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
287system.physmem.busUtil 0.03 # Data bus utilization in percentage
288system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
289system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
290system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing
291system.physmem.avgWrQLen 24.34 # Average write queue length when enqueuing
292system.physmem.readRowHits 851046 # Number of row buffer hits during reads
293system.physmem.writeRowHits 1176475 # Number of row buffer hits during writes
294system.physmem.readRowHitRate 75.55 # Row buffer hit rate for reads
295system.physmem.writeRowHitRate 57.88 # Row buffer hit rate for writes
296system.physmem.avgGap 14949293.37 # Average gap between requests
297system.physmem.pageHitRate 64.18 # Row buffer hit rate, read and write combined
298system.physmem_0.actEnergy 4318120800 # Energy for activate commands per rank (pJ)
299system.physmem_0.preEnergy 2356117500 # Energy for precharge commands per rank (pJ)
300system.physmem_0.readEnergy 4401423000 # Energy for read commands per rank (pJ)
301system.physmem_0.writeEnergy 6642421200 # Energy for write commands per rank (pJ)
302system.physmem_0.refreshEnergy 3092370278400 # Energy for refresh commands per rank (pJ)
303system.physmem_0.actBackEnergy 1163515422960 # Energy for active background per rank (pJ)
304system.physmem_0.preBackEnergy 27386602512000 # Energy for precharge background per rank (pJ)
305system.physmem_0.totalEnergy 31660206295860 # Total energy per rank (pJ)
306system.physmem_0.averagePower 668.707358 # Core power per rank (mW)
307system.physmem_0.memoryStateTime::IDLE 45559855793000 # Time in different power states
308system.physmem_0.memoryStateTime::REF 1580966400000 # Time in different power states
309system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
310system.physmem_0.memoryStateTime::ACT 204562609000 # Time in different power states
311system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
312system.physmem_1.actEnergy 4237153200 # Energy for activate commands per rank (pJ)
313system.physmem_1.preEnergy 2311938750 # Energy for precharge commands per rank (pJ)
314system.physmem_1.readEnergy 4385027400 # Energy for read commands per rank (pJ)
315system.physmem_1.writeEnergy 6529429440 # Energy for write commands per rank (pJ)
316system.physmem_1.refreshEnergy 3092370278400 # Energy for refresh commands per rank (pJ)
317system.physmem_1.actBackEnergy 1165548686490 # Energy for active background per rank (pJ)
318system.physmem_1.preBackEnergy 27384818947500 # Energy for precharge background per rank (pJ)
319system.physmem_1.totalEnergy 31660201461180 # Total energy per rank (pJ)
320system.physmem_1.averagePower 668.707256 # Core power per rank (mW)
321system.physmem_1.memoryStateTime::IDLE 45556862760500 # Time in different power states
322system.physmem_1.memoryStateTime::REF 1580966400000 # Time in different power states
323system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
324system.physmem_1.memoryStateTime::ACT 207555509500 # Time in different power states
325system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
326system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory
327system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
328system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
329system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
330system.realview.nvmem.bytes_read::total 572 # Number of bytes read from this memory
331system.realview.nvmem.bytes_inst_read::cpu0.inst 384 # Number of instructions bytes read from this memory
332system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory

--- 17 unchanged lines hidden (view full) ---

350system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
351system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
352system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
353system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
354system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
355system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
356system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
357system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
358system.cpu0.branchPred.lookups 145356452 # Number of BP lookups
359system.cpu0.branchPred.condPredicted 96435082 # Number of conditional branches predicted
360system.cpu0.branchPred.condIncorrect 7088203 # Number of conditional branches incorrect
361system.cpu0.branchPred.BTBLookups 101789401 # Number of BTB lookups
362system.cpu0.branchPred.BTBHits 67765064 # Number of BTB hits
363system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
364system.cpu0.branchPred.BTBHitPct 66.573792 # BTB Hit Percentage
365system.cpu0.branchPred.usedRAS 20004195 # Number of times the RAS was used to get a target.
366system.cpu0.branchPred.RASInCorrect 205158 # Number of incorrect RAS predictions.
367system.cpu_clk_domain.clock 500 # Clock period in ticks
368system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
369system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
370system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
371system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
372system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
373system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
374system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

389system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
390system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
391system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
392system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
393system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
394system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
395system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
396system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
397system.cpu0.dtb.walker.walks 580611 # Table walker walks requested
398system.cpu0.dtb.walker.walksLong 580611 # Table walker walks initiated with long descriptors
399system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13679 # Level at which table walker walks with long descriptors terminate
400system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 93135 # Level at which table walker walks with long descriptors terminate
401system.cpu0.dtb.walker.walksSquashedBefore 259311 # Table walks squashed before starting
402system.cpu0.dtb.walker.walkWaitTime::samples 321300 # Table walker wait (enqueue to first request) latency
403system.cpu0.dtb.walker.walkWaitTime::mean 1669.368192 # Table walker wait (enqueue to first request) latency
404system.cpu0.dtb.walker.walkWaitTime::stdev 10492.971715 # Table walker wait (enqueue to first request) latency
405system.cpu0.dtb.walker.walkWaitTime::0-32767 317448 98.80% 98.80% # Table walker wait (enqueue to first request) latency
406system.cpu0.dtb.walker.walkWaitTime::32768-65535 2037 0.63% 99.44% # Table walker wait (enqueue to first request) latency
407system.cpu0.dtb.walker.walkWaitTime::65536-98303 845 0.26% 99.70% # Table walker wait (enqueue to first request) latency
408system.cpu0.dtb.walker.walkWaitTime::98304-131071 576 0.18% 99.88% # Table walker wait (enqueue to first request) latency
409system.cpu0.dtb.walker.walkWaitTime::131072-163839 232 0.07% 99.95% # Table walker wait (enqueue to first request) latency
410system.cpu0.dtb.walker.walkWaitTime::163840-196607 45 0.01% 99.96% # Table walker wait (enqueue to first request) latency
411system.cpu0.dtb.walker.walkWaitTime::196608-229375 28 0.01% 99.97% # Table walker wait (enqueue to first request) latency
412system.cpu0.dtb.walker.walkWaitTime::229376-262143 26 0.01% 99.98% # Table walker wait (enqueue to first request) latency
413system.cpu0.dtb.walker.walkWaitTime::262144-294911 42 0.01% 99.99% # Table walker wait (enqueue to first request) latency
414system.cpu0.dtb.walker.walkWaitTime::294912-327679 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency
415system.cpu0.dtb.walker.walkWaitTime::327680-360447 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency
416system.cpu0.dtb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
417system.cpu0.dtb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
418system.cpu0.dtb.walker.walkWaitTime::425984-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
419system.cpu0.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
420system.cpu0.dtb.walker.walkWaitTime::total 321300 # Table walker wait (enqueue to first request) latency
421system.cpu0.dtb.walker.walkCompletionTime::samples 293805 # Table walker service (enqueue to completion) latency
422system.cpu0.dtb.walker.walkCompletionTime::mean 15781.864128 # Table walker service (enqueue to completion) latency
423system.cpu0.dtb.walker.walkCompletionTime::gmean 13334.413537 # Table walker service (enqueue to completion) latency
424system.cpu0.dtb.walker.walkCompletionTime::stdev 14277.098383 # Table walker service (enqueue to completion) latency
425system.cpu0.dtb.walker.walkCompletionTime::0-65535 291279 99.14% 99.14% # Table walker service (enqueue to completion) latency
426system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1809 0.62% 99.76% # Table walker service (enqueue to completion) latency
427system.cpu0.dtb.walker.walkCompletionTime::131072-196607 367 0.12% 99.88% # Table walker service (enqueue to completion) latency
428system.cpu0.dtb.walker.walkCompletionTime::196608-262143 189 0.06% 99.95% # Table walker service (enqueue to completion) latency
429system.cpu0.dtb.walker.walkCompletionTime::262144-327679 105 0.04% 99.98% # Table walker service (enqueue to completion) latency
430system.cpu0.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency
431system.cpu0.dtb.walker.walkCompletionTime::393216-458751 21 0.01% 100.00% # Table walker service (enqueue to completion) latency
432system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
433system.cpu0.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
434system.cpu0.dtb.walker.walkCompletionTime::total 293805 # Table walker service (enqueue to completion) latency
435system.cpu0.dtb.walker.walksPending::samples 521650035508 # Table walker pending requests distribution
436system.cpu0.dtb.walker.walksPending::mean 0.610400 # Table walker pending requests distribution
437system.cpu0.dtb.walker.walksPending::stdev 0.526555 # Table walker pending requests distribution
438system.cpu0.dtb.walker.walksPending::0-1 520697119508 99.82% 99.82% # Table walker pending requests distribution
439system.cpu0.dtb.walker.walksPending::2-3 543124000 0.10% 99.92% # Table walker pending requests distribution
440system.cpu0.dtb.walker.walksPending::4-5 195186500 0.04% 99.96% # Table walker pending requests distribution
441system.cpu0.dtb.walker.walksPending::6-7 85165500 0.02% 99.98% # Table walker pending requests distribution
442system.cpu0.dtb.walker.walksPending::8-9 70245500 0.01% 99.99% # Table walker pending requests distribution
443system.cpu0.dtb.walker.walksPending::10-11 34070500 0.01% 100.00% # Table walker pending requests distribution
444system.cpu0.dtb.walker.walksPending::12-13 11934000 0.00% 100.00% # Table walker pending requests distribution
445system.cpu0.dtb.walker.walksPending::14-15 12740000 0.00% 100.00% # Table walker pending requests distribution
446system.cpu0.dtb.walker.walksPending::16-17 448500 0.00% 100.00% # Table walker pending requests distribution
447system.cpu0.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution
448system.cpu0.dtb.walker.walksPending::total 521650035508 # Table walker pending requests distribution
449system.cpu0.dtb.walker.walkPageSizes::4K 93135 87.19% 87.19% # Table walker page sizes translated
450system.cpu0.dtb.walker.walkPageSizes::2M 13679 12.81% 100.00% # Table walker page sizes translated
451system.cpu0.dtb.walker.walkPageSizes::total 106814 # Table walker page sizes translated
452system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 580611 # Table walker requests started/completed, data/inst
453system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
454system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 580611 # Table walker requests started/completed, data/inst
455system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106814 # Table walker requests started/completed, data/inst
456system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
457system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106814 # Table walker requests started/completed, data/inst
458system.cpu0.dtb.walker.walkRequestOrigin::total 687425 # Table walker requests started/completed, data/inst
459system.cpu0.dtb.inst_hits 0 # ITB inst hits
460system.cpu0.dtb.inst_misses 0 # ITB inst misses
461system.cpu0.dtb.read_hits 105404836 # DTB read hits
462system.cpu0.dtb.read_misses 420652 # DTB read misses
463system.cpu0.dtb.write_hits 86890500 # DTB write hits
464system.cpu0.dtb.write_misses 159959 # DTB write misses
465system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
466system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
467system.cpu0.dtb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID
468system.cpu0.dtb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID
469system.cpu0.dtb.flush_entries 40944 # Number of entries that have been flushed from TLB
470system.cpu0.dtb.align_faults 605 # Number of TLB faults due to alignment restrictions
471system.cpu0.dtb.prefetch_faults 8089 # Number of TLB faults due to prefetch
472system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
473system.cpu0.dtb.perms_faults 40127 # Number of TLB faults due to permissions restrictions
474system.cpu0.dtb.read_accesses 105825488 # DTB read accesses
475system.cpu0.dtb.write_accesses 87050459 # DTB write accesses
476system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
477system.cpu0.dtb.hits 192295336 # DTB hits
478system.cpu0.dtb.misses 580611 # DTB misses
479system.cpu0.dtb.accesses 192875947 # DTB accesses
480system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
481system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

501system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
502system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
503system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
504system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
505system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
506system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
507system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
508system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
509system.cpu0.itb.walker.walks 84622 # Table walker walks requested
510system.cpu0.itb.walker.walksLong 84622 # Table walker walks initiated with long descriptors
511system.cpu0.itb.walker.walksLongTerminationLevel::Level2 994 # Level at which table walker walks with long descriptors terminate
512system.cpu0.itb.walker.walksLongTerminationLevel::Level3 61729 # Level at which table walker walks with long descriptors terminate
513system.cpu0.itb.walker.walksSquashedBefore 9515 # Table walks squashed before starting
514system.cpu0.itb.walker.walkWaitTime::samples 75107 # Table walker wait (enqueue to first request) latency
515system.cpu0.itb.walker.walkWaitTime::mean 1146.297948 # Table walker wait (enqueue to first request) latency
516system.cpu0.itb.walker.walkWaitTime::stdev 8819.384812 # Table walker wait (enqueue to first request) latency
517system.cpu0.itb.walker.walkWaitTime::0-32767 74551 99.26% 99.26% # Table walker wait (enqueue to first request) latency
518system.cpu0.itb.walker.walkWaitTime::32768-65535 182 0.24% 99.50% # Table walker wait (enqueue to first request) latency
519system.cpu0.itb.walker.walkWaitTime::65536-98303 223 0.30% 99.80% # Table walker wait (enqueue to first request) latency
520system.cpu0.itb.walker.walkWaitTime::98304-131071 112 0.15% 99.95% # Table walker wait (enqueue to first request) latency
521system.cpu0.itb.walker.walkWaitTime::131072-163839 5 0.01% 99.95% # Table walker wait (enqueue to first request) latency
522system.cpu0.itb.walker.walkWaitTime::163840-196607 9 0.01% 99.97% # Table walker wait (enqueue to first request) latency
523system.cpu0.itb.walker.walkWaitTime::196608-229375 12 0.02% 99.98% # Table walker wait (enqueue to first request) latency
524system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
525system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
526system.cpu0.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
527system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
528system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
529system.cpu0.itb.walker.walkWaitTime::total 75107 # Table walker wait (enqueue to first request) latency
530system.cpu0.itb.walker.walkCompletionTime::samples 72238 # Table walker service (enqueue to completion) latency
531system.cpu0.itb.walker.walkCompletionTime::mean 20242.257302 # Table walker service (enqueue to completion) latency
532system.cpu0.itb.walker.walkCompletionTime::gmean 17307.169845 # Table walker service (enqueue to completion) latency
533system.cpu0.itb.walker.walkCompletionTime::stdev 18587.015651 # Table walker service (enqueue to completion) latency
534system.cpu0.itb.walker.walkCompletionTime::0-65535 70635 97.78% 97.78% # Table walker service (enqueue to completion) latency
535system.cpu0.itb.walker.walkCompletionTime::65536-131071 1318 1.82% 99.61% # Table walker service (enqueue to completion) latency
536system.cpu0.itb.walker.walkCompletionTime::131072-196607 148 0.20% 99.81% # Table walker service (enqueue to completion) latency
537system.cpu0.itb.walker.walkCompletionTime::196608-262143 80 0.11% 99.92% # Table walker service (enqueue to completion) latency
538system.cpu0.itb.walker.walkCompletionTime::262144-327679 29 0.04% 99.96% # Table walker service (enqueue to completion) latency
539system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.98% # Table walker service (enqueue to completion) latency
540system.cpu0.itb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
541system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
542system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
543system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
544system.cpu0.itb.walker.walkCompletionTime::total 72238 # Table walker service (enqueue to completion) latency
545system.cpu0.itb.walker.walksPending::samples 405678068016 # Table walker pending requests distribution
546system.cpu0.itb.walker.walksPending::mean 0.851697 # Table walker pending requests distribution
547system.cpu0.itb.walker.walksPending::stdev 0.355553 # Table walker pending requests distribution
548system.cpu0.itb.walker.walksPending::0 60184359568 14.84% 14.84% # Table walker pending requests distribution
549system.cpu0.itb.walker.walksPending::1 345473805948 85.16% 100.00% # Table walker pending requests distribution
550system.cpu0.itb.walker.walksPending::2 18871000 0.00% 100.00% # Table walker pending requests distribution
551system.cpu0.itb.walker.walksPending::3 1025500 0.00% 100.00% # Table walker pending requests distribution
552system.cpu0.itb.walker.walksPending::4 6000 0.00% 100.00% # Table walker pending requests distribution
553system.cpu0.itb.walker.walksPending::total 405678068016 # Table walker pending requests distribution
554system.cpu0.itb.walker.walkPageSizes::4K 61729 98.42% 98.42% # Table walker page sizes translated
555system.cpu0.itb.walker.walkPageSizes::2M 994 1.58% 100.00% # Table walker page sizes translated
556system.cpu0.itb.walker.walkPageSizes::total 62723 # Table walker page sizes translated
557system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
558system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 84622 # Table walker requests started/completed, data/inst
559system.cpu0.itb.walker.walkRequestOrigin_Requested::total 84622 # Table walker requests started/completed, data/inst
560system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
561system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 62723 # Table walker requests started/completed, data/inst
562system.cpu0.itb.walker.walkRequestOrigin_Completed::total 62723 # Table walker requests started/completed, data/inst
563system.cpu0.itb.walker.walkRequestOrigin::total 147345 # Table walker requests started/completed, data/inst
564system.cpu0.itb.inst_hits 229226252 # ITB inst hits
565system.cpu0.itb.inst_misses 84622 # ITB inst misses
566system.cpu0.itb.read_hits 0 # DTB read hits
567system.cpu0.itb.read_misses 0 # DTB read misses
568system.cpu0.itb.write_hits 0 # DTB write hits
569system.cpu0.itb.write_misses 0 # DTB write misses
570system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
571system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
572system.cpu0.itb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID
573system.cpu0.itb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID
574system.cpu0.itb.flush_entries 29308 # Number of entries that have been flushed from TLB
575system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
576system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
577system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
578system.cpu0.itb.perms_faults 225641 # Number of TLB faults due to permissions restrictions
579system.cpu0.itb.read_accesses 0 # DTB read accesses
580system.cpu0.itb.write_accesses 0 # DTB write accesses
581system.cpu0.itb.inst_accesses 229310874 # ITB inst accesses
582system.cpu0.itb.hits 229226252 # DTB hits
583system.cpu0.itb.misses 84622 # DTB misses
584system.cpu0.itb.accesses 229310874 # DTB accesses
585system.cpu0.numCycles 787784387 # number of cpu cycles simulated
586system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
587system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
588system.cpu0.fetch.icacheStallCycles 93175923 # Number of cycles fetch is stalled on an Icache miss
589system.cpu0.fetch.Insts 642526185 # Number of instructions fetch has processed
590system.cpu0.fetch.Branches 145356452 # Number of branches that fetch encountered
591system.cpu0.fetch.predictedBranches 87769259 # Number of branches that fetch has predicted taken
592system.cpu0.fetch.Cycles 654798115 # Number of cycles fetch has run and was not squashing or blocked
593system.cpu0.fetch.SquashCycles 15283958 # Number of cycles fetch has spent squashing
594system.cpu0.fetch.TlbCycles 1702071 # Number of cycles fetch has spent waiting for tlb
595system.cpu0.fetch.MiscStallCycles 255624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
596system.cpu0.fetch.PendingTrapStallCycles 6308926 # Number of stall cycles due to pending traps
597system.cpu0.fetch.PendingQuiesceStallCycles 745987 # Number of stall cycles due to pending quiesce instructions
598system.cpu0.fetch.IcacheWaitRetryStallCycles 671334 # Number of stall cycles due to full MSHR
599system.cpu0.fetch.CacheLines 229000663 # Number of cache lines fetched
600system.cpu0.fetch.IcacheSquashes 1782311 # Number of outstanding Icache misses that were squashed
601system.cpu0.fetch.ItlbSquashes 27660 # Number of outstanding ITLB misses that were squashed
602system.cpu0.fetch.rateDist::samples 765299959 # Number of instructions fetched each cycle (Total)
603system.cpu0.fetch.rateDist::mean 0.983676 # Number of instructions fetched each cycle (Total)
604system.cpu0.fetch.rateDist::stdev 1.220176 # Number of instructions fetched each cycle (Total)
605system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
606system.cpu0.fetch.rateDist::0 404626902 52.87% 52.87% # Number of instructions fetched each cycle (Total)
607system.cpu0.fetch.rateDist::1 139960190 18.29% 71.16% # Number of instructions fetched each cycle (Total)
608system.cpu0.fetch.rateDist::2 49291261 6.44% 77.60% # Number of instructions fetched each cycle (Total)
609system.cpu0.fetch.rateDist::3 171421606 22.40% 100.00% # Number of instructions fetched each cycle (Total)
610system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
611system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
612system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
613system.cpu0.fetch.rateDist::total 765299959 # Number of instructions fetched each cycle (Total)
614system.cpu0.fetch.branchRate 0.184513 # Number of branch fetches per cycle
615system.cpu0.fetch.rate 0.815612 # Number of inst fetches per cycle
616system.cpu0.decode.IdleCycles 110781464 # Number of cycles decode is idle
617system.cpu0.decode.BlockedCycles 368356745 # Number of cycles decode is blocked
618system.cpu0.decode.RunCycles 241543971 # Number of cycles decode is running
619system.cpu0.decode.UnblockCycles 39160465 # Number of cycles decode is unblocking
620system.cpu0.decode.SquashCycles 5457314 # Number of cycles decode is squashing
621system.cpu0.decode.BranchResolved 20998766 # Number of times decode resolved a branch
622system.cpu0.decode.BranchMispred 2230758 # Number of times decode detected a branch misprediction
623system.cpu0.decode.DecodedInsts 666506782 # Number of instructions handled by decode
624system.cpu0.decode.SquashedInsts 24554495 # Number of squashed instructions handled by decode
625system.cpu0.rename.SquashCycles 5457314 # Number of cycles rename is squashing
626system.cpu0.rename.IdleCycles 147799214 # Number of cycles rename is idle
627system.cpu0.rename.BlockCycles 53385858 # Number of cycles rename is blocking
628system.cpu0.rename.serializeStallCycles 247347968 # count of cycles rename stalled for serializing inst
629system.cpu0.rename.RunCycles 243020975 # Number of cycles rename is running
630system.cpu0.rename.UnblockCycles 68288630 # Number of cycles rename is unblocking
631system.cpu0.rename.RenamedInsts 648373688 # Number of instructions processed by rename
632system.cpu0.rename.SquashedInsts 6354822 # Number of squashed instructions processed by rename
633system.cpu0.rename.ROBFullEvents 9340488 # Number of times rename has blocked due to ROB full
634system.cpu0.rename.IQFullEvents 358878 # Number of times rename has blocked due to IQ full
635system.cpu0.rename.LQFullEvents 691420 # Number of times rename has blocked due to LQ full
636system.cpu0.rename.SQFullEvents 31770877 # Number of times rename has blocked due to SQ full
637system.cpu0.rename.FullRegisterEvents 13042 # Number of times there has been no free registers
638system.cpu0.rename.RenamedOperands 618836498 # Number of destination operands rename has renamed
639system.cpu0.rename.RenameLookups 1000163983 # Number of register rename lookups that rename has made
640system.cpu0.rename.int_rename_lookups 765756832 # Number of integer rename lookups
641system.cpu0.rename.fp_rename_lookups 980941 # Number of floating rename lookups
642system.cpu0.rename.CommittedMaps 557557100 # Number of HB maps that are committed
643system.cpu0.rename.UndoneMaps 61279388 # Number of HB maps that are undone due to squashing
644system.cpu0.rename.serializingInsts 16104693 # count of serializing insts renamed
645system.cpu0.rename.tempSerializingInsts 13959035 # count of temporary serializing insts renamed
646system.cpu0.rename.skidInsts 79116837 # count of insts added to the skid buffer
647system.cpu0.memDep0.insertedLoads 106280749 # Number of loads inserted to the mem dependence unit.
648system.cpu0.memDep0.insertedStores 90455195 # Number of stores inserted to the mem dependence unit.
649system.cpu0.memDep0.conflictingLoads 9698755 # Number of conflicting loads.
650system.cpu0.memDep0.conflictingStores 8363084 # Number of conflicting stores.
651system.cpu0.iq.iqInstsAdded 625354037 # Number of instructions added to the IQ (excludes non-spec)
652system.cpu0.iq.iqNonSpecInstsAdded 16149817 # Number of non-speculative instructions added to the IQ
653system.cpu0.iq.iqInstsIssued 628774014 # Number of instructions issued
654system.cpu0.iq.iqSquashedInstsIssued 2896491 # Number of squashed instructions issued
655system.cpu0.iq.iqSquashedInstsExamined 54006760 # Number of squashed instructions iterated over during squash; mainly for profiling
656system.cpu0.iq.iqSquashedOperandsExamined 37569824 # Number of squashed operands that are examined and possibly removed from graph
657system.cpu0.iq.iqSquashedNonSpecRemoved 287316 # Number of squashed non-spec instructions that were removed
658system.cpu0.iq.issued_per_cycle::samples 765299959 # Number of insts issued each cycle
659system.cpu0.iq.issued_per_cycle::mean 0.821605 # Number of insts issued each cycle
660system.cpu0.iq.issued_per_cycle::stdev 1.068919 # Number of insts issued each cycle
661system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
662system.cpu0.iq.issued_per_cycle::0 423230722 55.30% 55.30% # Number of insts issued each cycle
663system.cpu0.iq.issued_per_cycle::1 141522259 18.49% 73.79% # Number of insts issued each cycle
664system.cpu0.iq.issued_per_cycle::2 122647115 16.03% 89.82% # Number of insts issued each cycle
665system.cpu0.iq.issued_per_cycle::3 69647275 9.10% 98.92% # Number of insts issued each cycle
666system.cpu0.iq.issued_per_cycle::4 8247243 1.08% 100.00% # Number of insts issued each cycle
667system.cpu0.iq.issued_per_cycle::5 5342 0.00% 100.00% # Number of insts issued each cycle
668system.cpu0.iq.issued_per_cycle::6 3 0.00% 100.00% # Number of insts issued each cycle
669system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
670system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
671system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
672system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
673system.cpu0.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
674system.cpu0.iq.issued_per_cycle::total 765299959 # Number of insts issued each cycle
675system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
676system.cpu0.iq.fu_full::IntAlu 65414267 45.68% 45.68% # attempts to use FU when none available
677system.cpu0.iq.fu_full::IntMult 59912 0.04% 45.72% # attempts to use FU when none available
678system.cpu0.iq.fu_full::IntDiv 17829 0.01% 45.73% # attempts to use FU when none available
679system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.73% # attempts to use FU when none available
680system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.73% # attempts to use FU when none available
681system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.73% # attempts to use FU when none available
682system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.73% # attempts to use FU when none available
683system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.73% # attempts to use FU when none available
684system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.73% # attempts to use FU when none available
685system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.73% # attempts to use FU when none available
686system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.73% # attempts to use FU when none available
687system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.73% # attempts to use FU when none available
688system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.73% # attempts to use FU when none available
689system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.73% # attempts to use FU when none available
690system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.73% # attempts to use FU when none available
691system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.73% # attempts to use FU when none available
692system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.73% # attempts to use FU when none available
693system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.73% # attempts to use FU when none available
694system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.73% # attempts to use FU when none available
695system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.73% # attempts to use FU when none available
696system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.73% # attempts to use FU when none available
697system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.73% # attempts to use FU when none available
698system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.73% # attempts to use FU when none available
699system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.73% # attempts to use FU when none available
700system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.73% # attempts to use FU when none available
701system.cpu0.iq.fu_full::SimdFloatMisc 19 0.00% 45.73% # attempts to use FU when none available
702system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.73% # attempts to use FU when none available
703system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.73% # attempts to use FU when none available
704system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.73% # attempts to use FU when none available
705system.cpu0.iq.fu_full::MemRead 37349884 26.08% 71.81% # attempts to use FU when none available
706system.cpu0.iq.fu_full::MemWrite 40363750 28.19% 100.00% # attempts to use FU when none available
707system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
708system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
709system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
710system.cpu0.iq.FU_type_0::IntAlu 430163495 68.41% 68.41% # Type of FU issued
711system.cpu0.iq.FU_type_0::IntMult 1578221 0.25% 68.66% # Type of FU issued
712system.cpu0.iq.FU_type_0::IntDiv 81407 0.01% 68.68% # Type of FU issued
713system.cpu0.iq.FU_type_0::FloatAdd 125 0.00% 68.68% # Type of FU issued
714system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.68% # Type of FU issued
715system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.68% # Type of FU issued
716system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.68% # Type of FU issued
717system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.68% # Type of FU issued
718system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.68% # Type of FU issued
719system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.68% # Type of FU issued
720system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.68% # Type of FU issued
721system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.68% # Type of FU issued
722system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.68% # Type of FU issued
723system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.68% # Type of FU issued
724system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.68% # Type of FU issued
725system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.68% # Type of FU issued
726system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.68% # Type of FU issued
727system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.68% # Type of FU issued
728system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.68% # Type of FU issued
729system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.68% # Type of FU issued
730system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.68% # Type of FU issued
731system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.68% # Type of FU issued
732system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.68% # Type of FU issued
733system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.68% # Type of FU issued
734system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.68% # Type of FU issued
735system.cpu0.iq.FU_type_0::SimdFloatMisc 78656 0.01% 68.69% # Type of FU issued
736system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued
737system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued
738system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued
739system.cpu0.iq.FU_type_0::MemRead 108646479 17.28% 85.97% # Type of FU issued
740system.cpu0.iq.FU_type_0::MemWrite 88225631 14.03% 100.00% # Type of FU issued
741system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
742system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
743system.cpu0.iq.FU_type_0::total 628774014 # Type of FU issued
744system.cpu0.iq.rate 0.798155 # Inst issue rate
745system.cpu0.iq.fu_busy_cnt 143205661 # FU busy when requested
746system.cpu0.iq.fu_busy_rate 0.227754 # FU busy rate (busy events/executed inst)
747system.cpu0.iq.int_inst_queue_reads 2167577171 # Number of integer instruction queue reads
748system.cpu0.iq.int_inst_queue_writes 695106277 # Number of integer instruction queue writes
749system.cpu0.iq.int_inst_queue_wakeup_accesses 611404783 # Number of integer instruction queue wakeup accesses
750system.cpu0.iq.fp_inst_queue_reads 1372966 # Number of floating instruction queue reads
751system.cpu0.iq.fp_inst_queue_writes 554126 # Number of floating instruction queue writes
752system.cpu0.iq.fp_inst_queue_wakeup_accesses 508083 # Number of floating instruction queue wakeup accesses
753system.cpu0.iq.int_alu_accesses 771129089 # Number of integer alu accesses
754system.cpu0.iq.fp_alu_accesses 850586 # Number of floating point alu accesses
755system.cpu0.iew.lsq.thread0.forwLoads 2930031 # Number of loads that had data forwarded from stores
756system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
757system.cpu0.iew.lsq.thread0.squashedLoads 13213228 # Number of loads squashed
758system.cpu0.iew.lsq.thread0.ignoredResponses 17078 # Number of memory responses ignored because the instruction is squashed
759system.cpu0.iew.lsq.thread0.memOrderViolation 150900 # Number of memory ordering violations
760system.cpu0.iew.lsq.thread0.squashedStores 6091069 # Number of stores squashed
761system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
762system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
763system.cpu0.iew.lsq.thread0.rescheduledLoads 2819130 # Number of loads that were rescheduled
764system.cpu0.iew.lsq.thread0.cacheBlocked 4221569 # Number of times an access to memory failed due to the cache being blocked
765system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
766system.cpu0.iew.iewSquashCycles 5457314 # Number of cycles IEW is squashing
767system.cpu0.iew.iewBlockCycles 7826815 # Number of cycles IEW is blocking
768system.cpu0.iew.iewUnblockCycles 3783393 # Number of cycles IEW is unblocking
769system.cpu0.iew.iewDispatchedInsts 641629807 # Number of instructions dispatched to IQ
770system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
771system.cpu0.iew.iewDispLoadInsts 106280749 # Number of dispatched load instructions
772system.cpu0.iew.iewDispStoreInsts 90455195 # Number of dispatched store instructions
773system.cpu0.iew.iewDispNonSpecInsts 13677015 # Number of dispatched non-speculative instructions
774system.cpu0.iew.iewIQFullEvents 59030 # Number of times the IQ has become full, causing a stall
775system.cpu0.iew.iewLSQFullEvents 3651240 # Number of times the LSQ has become full, causing a stall
776system.cpu0.iew.memOrderViolationEvents 150900 # Number of memory order violations
777system.cpu0.iew.predictedTakenIncorrect 2214888 # Number of branches that were predicted taken incorrectly
778system.cpu0.iew.predictedNotTakenIncorrect 3025224 # Number of branches that were predicted not taken incorrectly
779system.cpu0.iew.branchMispredicts 5240112 # Number of branch mispredicts detected at execute
780system.cpu0.iew.iewExecutedInsts 620548589 # Number of executed instructions
781system.cpu0.iew.iewExecLoadInsts 105398618 # Number of load instructions executed
782system.cpu0.iew.iewExecSquashedInsts 7653008 # Number of squashed instructions skipped in execute
783system.cpu0.iew.exec_swp 0 # number of swp insts executed
784system.cpu0.iew.exec_nop 125953 # number of nop insts executed
785system.cpu0.iew.exec_refs 192287971 # number of memory reference insts executed
786system.cpu0.iew.exec_branches 117275797 # Number of branches executed
787system.cpu0.iew.exec_stores 86889353 # Number of stores executed
788system.cpu0.iew.exec_rate 0.787714 # Inst execution rate
789system.cpu0.iew.wb_sent 612710943 # cumulative count of insts sent to commit
790system.cpu0.iew.wb_count 611912866 # cumulative count of insts written-back
791system.cpu0.iew.wb_producers 297952907 # num instructions producing a value
792system.cpu0.iew.wb_consumers 488842231 # num instructions consuming a value
793system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
794system.cpu0.iew.wb_rate 0.776752 # insts written-back per cycle
795system.cpu0.iew.wb_fanout 0.609507 # average fanout of values written-back
796system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
797system.cpu0.commit.commitSquashedInsts 50177444 # The number of squashed insts skipped by commit
798system.cpu0.commit.commitNonSpecStalls 15862501 # The number of times commit has been forced to stall to communicate backwards
799system.cpu0.commit.branchMispredicts 4903538 # The number of times a branch was mispredicted
800system.cpu0.commit.committed_per_cycle::samples 755787028 # Number of insts commited each cycle
801system.cpu0.commit.committed_per_cycle::mean 0.772749 # Number of insts commited each cycle
802system.cpu0.commit.committed_per_cycle::stdev 1.571704 # Number of insts commited each cycle
803system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
804system.cpu0.commit.committed_per_cycle::0 501065306 66.30% 66.30% # Number of insts commited each cycle
805system.cpu0.commit.committed_per_cycle::1 130810768 17.31% 83.61% # Number of insts commited each cycle
806system.cpu0.commit.committed_per_cycle::2 56911365 7.53% 91.14% # Number of insts commited each cycle
807system.cpu0.commit.committed_per_cycle::3 19253126 2.55% 93.68% # Number of insts commited each cycle
808system.cpu0.commit.committed_per_cycle::4 13929285 1.84% 95.53% # Number of insts commited each cycle
809system.cpu0.commit.committed_per_cycle::5 9339201 1.24% 96.76% # Number of insts commited each cycle
810system.cpu0.commit.committed_per_cycle::6 6281388 0.83% 97.59% # Number of insts commited each cycle
811system.cpu0.commit.committed_per_cycle::7 4033068 0.53% 98.13% # Number of insts commited each cycle
812system.cpu0.commit.committed_per_cycle::8 14163521 1.87% 100.00% # Number of insts commited each cycle
813system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
814system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
815system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
816system.cpu0.commit.committed_per_cycle::total 755787028 # Number of insts commited each cycle
817system.cpu0.commit.committedInsts 497564314 # Number of instructions committed
818system.cpu0.commit.committedOps 584033993 # Number of ops (including micro ops) committed
819system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
820system.cpu0.commit.refs 177431645 # Number of memory references committed
821system.cpu0.commit.loads 93067519 # Number of loads committed
822system.cpu0.commit.membars 3925399 # Number of memory barriers committed
823system.cpu0.commit.branches 111370146 # Number of branches committed
824system.cpu0.commit.fp_insts 496516 # Number of committed floating point instructions.
825system.cpu0.commit.int_insts 535821487 # Number of committed integer instructions.
826system.cpu0.commit.function_calls 14891305 # Number of function calls committed.
827system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
828system.cpu0.commit.op_class_0::IntAlu 405157799 69.37% 69.37% # Class of committed instruction
829system.cpu0.commit.op_class_0::IntMult 1311833 0.22% 69.60% # Class of committed instruction
830system.cpu0.commit.op_class_0::IntDiv 63039 0.01% 69.61% # Class of committed instruction
831system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction
832system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction
833system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction
834system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction
835system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction
836system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction
837system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction
838system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction
839system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction
840system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction
841system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction
842system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction
843system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction
844system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction
845system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction
846system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction
847system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction
848system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction
849system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction
850system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction
851system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction
852system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction
853system.cpu0.commit.op_class_0::SimdFloatMisc 69677 0.01% 69.62% # Class of committed instruction
854system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction
855system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction
856system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction
857system.cpu0.commit.op_class_0::MemRead 93067519 15.94% 85.55% # Class of committed instruction
858system.cpu0.commit.op_class_0::MemWrite 84364126 14.45% 100.00% # Class of committed instruction
859system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
860system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
861system.cpu0.commit.op_class_0::total 584033993 # Class of committed instruction
862system.cpu0.commit.bw_lim_events 14163521 # number cycles where commit BW limit reached
863system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
864system.cpu0.rob.rob_reads 1371348086 # The number of ROB reads
865system.cpu0.rob.rob_writes 1277898548 # The number of ROB writes
866system.cpu0.timesIdled 1050969 # Number of times that the entire CPU went into an idle state and unscheduled itself
867system.cpu0.idleCycles 22484428 # Total number of cycles that the CPU has spent unscheduled due to idling
868system.cpu0.quiesceCycles 93902986117 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
869system.cpu0.committedInsts 497564314 # Number of Instructions Simulated
870system.cpu0.committedOps 584033993 # Number of Ops (including micro ops) Simulated
871system.cpu0.cpi 1.583282 # CPI: Cycles Per Instruction
872system.cpu0.cpi_total 1.583282 # CPI: Total CPI of All Threads
873system.cpu0.ipc 0.631600 # IPC: Instructions Per Cycle
874system.cpu0.ipc_total 0.631600 # IPC: Total IPC of All Threads
875system.cpu0.int_regfile_reads 732616408 # number of integer regfile reads
876system.cpu0.int_regfile_writes 435784003 # number of integer regfile writes
877system.cpu0.fp_regfile_reads 812591 # number of floating regfile reads
878system.cpu0.fp_regfile_writes 450624 # number of floating regfile writes
879system.cpu0.cc_regfile_reads 135724425 # number of cc regfile reads
880system.cpu0.cc_regfile_writes 136350840 # number of cc regfile writes
881system.cpu0.misc_regfile_reads 3048491910 # number of misc regfile reads
882system.cpu0.misc_regfile_writes 15942846 # number of misc regfile writes
883system.cpu0.dcache.tags.replacements 6332598 # number of replacements
884system.cpu0.dcache.tags.tagsinuse 484.098749 # Cycle average of tags in use
885system.cpu0.dcache.tags.total_refs 164710199 # Total number of references to valid blocks.
886system.cpu0.dcache.tags.sampled_refs 6333110 # Sample count of references to valid blocks.
887system.cpu0.dcache.tags.avg_refs 26.007791 # Average number of references to valid blocks.
888system.cpu0.dcache.tags.warmup_cycle 1750140500 # Cycle when the warmup percentage was hit.
889system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.098749 # Average occupied blocks per requestor
890system.cpu0.dcache.tags.occ_percent::cpu0.data 0.945505 # Average percentage of cache occupancy
891system.cpu0.dcache.tags.occ_percent::total 0.945505 # Average percentage of cache occupancy
892system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
893system.cpu0.dcache.tags.age_task_id_blocks_1024::0 275 # Occupied blocks per task id
894system.cpu0.dcache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id
895system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
896system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
897system.cpu0.dcache.tags.tag_accesses 368140426 # Number of tag accesses
898system.cpu0.dcache.tags.data_accesses 368140426 # Number of data accesses
899system.cpu0.dcache.ReadReq_hits::cpu0.data 86285504 # number of ReadReq hits
900system.cpu0.dcache.ReadReq_hits::total 86285504 # number of ReadReq hits
901system.cpu0.dcache.WriteReq_hits::cpu0.data 73342402 # number of WriteReq hits
902system.cpu0.dcache.WriteReq_hits::total 73342402 # number of WriteReq hits
903system.cpu0.dcache.SoftPFReq_hits::cpu0.data 227851 # number of SoftPFReq hits
904system.cpu0.dcache.SoftPFReq_hits::total 227851 # number of SoftPFReq hits
905system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 264480 # number of WriteInvalidateReq hits
906system.cpu0.dcache.WriteInvalidateReq_hits::total 264480 # number of WriteInvalidateReq hits
907system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1878345 # number of LoadLockedReq hits
908system.cpu0.dcache.LoadLockedReq_hits::total 1878345 # number of LoadLockedReq hits
909system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1911240 # number of StoreCondReq hits
910system.cpu0.dcache.StoreCondReq_hits::total 1911240 # number of StoreCondReq hits
911system.cpu0.dcache.demand_hits::cpu0.data 159627906 # number of demand (read+write) hits
912system.cpu0.dcache.demand_hits::total 159627906 # number of demand (read+write) hits
913system.cpu0.dcache.overall_hits::cpu0.data 159855757 # number of overall hits
914system.cpu0.dcache.overall_hits::total 159855757 # number of overall hits
915system.cpu0.dcache.ReadReq_misses::cpu0.data 7088092 # number of ReadReq misses
916system.cpu0.dcache.ReadReq_misses::total 7088092 # number of ReadReq misses
917system.cpu0.dcache.WriteReq_misses::cpu0.data 7774496 # number of WriteReq misses
918system.cpu0.dcache.WriteReq_misses::total 7774496 # number of WriteReq misses
919system.cpu0.dcache.SoftPFReq_misses::cpu0.data 746133 # number of SoftPFReq misses
920system.cpu0.dcache.SoftPFReq_misses::total 746133 # number of SoftPFReq misses
921system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 842824 # number of WriteInvalidateReq misses
922system.cpu0.dcache.WriteInvalidateReq_misses::total 842824 # number of WriteInvalidateReq misses
923system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 281020 # number of LoadLockedReq misses
924system.cpu0.dcache.LoadLockedReq_misses::total 281020 # number of LoadLockedReq misses
925system.cpu0.dcache.StoreCondReq_misses::cpu0.data 209055 # number of StoreCondReq misses
926system.cpu0.dcache.StoreCondReq_misses::total 209055 # number of StoreCondReq misses
927system.cpu0.dcache.demand_misses::cpu0.data 14862588 # number of demand (read+write) misses
928system.cpu0.dcache.demand_misses::total 14862588 # number of demand (read+write) misses
929system.cpu0.dcache.overall_misses::cpu0.data 15608721 # number of overall misses
930system.cpu0.dcache.overall_misses::total 15608721 # number of overall misses
931system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 105859717159 # number of ReadReq miss cycles
932system.cpu0.dcache.ReadReq_miss_latency::total 105859717159 # number of ReadReq miss cycles
933system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 137077029934 # number of WriteReq miss cycles
934system.cpu0.dcache.WriteReq_miss_latency::total 137077029934 # number of WriteReq miss cycles
935system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 45622327717 # number of WriteInvalidateReq miss cycles
936system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 45622327717 # number of WriteInvalidateReq miss cycles
937system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4025426932 # number of LoadLockedReq miss cycles
938system.cpu0.dcache.LoadLockedReq_miss_latency::total 4025426932 # number of LoadLockedReq miss cycles
939system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4395434712 # number of StoreCondReq miss cycles
940system.cpu0.dcache.StoreCondReq_miss_latency::total 4395434712 # number of StoreCondReq miss cycles
941system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3232000 # number of StoreCondFailReq miss cycles
942system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3232000 # number of StoreCondFailReq miss cycles
943system.cpu0.dcache.demand_miss_latency::cpu0.data 242936747093 # number of demand (read+write) miss cycles
944system.cpu0.dcache.demand_miss_latency::total 242936747093 # number of demand (read+write) miss cycles
945system.cpu0.dcache.overall_miss_latency::cpu0.data 242936747093 # number of overall miss cycles
946system.cpu0.dcache.overall_miss_latency::total 242936747093 # number of overall miss cycles
947system.cpu0.dcache.ReadReq_accesses::cpu0.data 93373596 # number of ReadReq accesses(hits+misses)
948system.cpu0.dcache.ReadReq_accesses::total 93373596 # number of ReadReq accesses(hits+misses)
949system.cpu0.dcache.WriteReq_accesses::cpu0.data 81116898 # number of WriteReq accesses(hits+misses)
950system.cpu0.dcache.WriteReq_accesses::total 81116898 # number of WriteReq accesses(hits+misses)
951system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 973984 # number of SoftPFReq accesses(hits+misses)
952system.cpu0.dcache.SoftPFReq_accesses::total 973984 # number of SoftPFReq accesses(hits+misses)
953system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1107304 # number of WriteInvalidateReq accesses(hits+misses)
954system.cpu0.dcache.WriteInvalidateReq_accesses::total 1107304 # number of WriteInvalidateReq accesses(hits+misses)
955system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2159365 # number of LoadLockedReq accesses(hits+misses)
956system.cpu0.dcache.LoadLockedReq_accesses::total 2159365 # number of LoadLockedReq accesses(hits+misses)
957system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2120295 # number of StoreCondReq accesses(hits+misses)
958system.cpu0.dcache.StoreCondReq_accesses::total 2120295 # number of StoreCondReq accesses(hits+misses)
959system.cpu0.dcache.demand_accesses::cpu0.data 174490494 # number of demand (read+write) accesses
960system.cpu0.dcache.demand_accesses::total 174490494 # number of demand (read+write) accesses
961system.cpu0.dcache.overall_accesses::cpu0.data 175464478 # number of overall (read+write) accesses
962system.cpu0.dcache.overall_accesses::total 175464478 # number of overall (read+write) accesses
963system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075911 # miss rate for ReadReq accesses
964system.cpu0.dcache.ReadReq_miss_rate::total 0.075911 # miss rate for ReadReq accesses
965system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.095843 # miss rate for WriteReq accesses
966system.cpu0.dcache.WriteReq_miss_rate::total 0.095843 # miss rate for WriteReq accesses
967system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.766063 # miss rate for SoftPFReq accesses
968system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766063 # miss rate for SoftPFReq accesses
969system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.761150 # miss rate for WriteInvalidateReq accesses
970system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.761150 # miss rate for WriteInvalidateReq accesses
971system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.130140 # miss rate for LoadLockedReq accesses
972system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.130140 # miss rate for LoadLockedReq accesses
973system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098597 # miss rate for StoreCondReq accesses
974system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098597 # miss rate for StoreCondReq accesses
975system.cpu0.dcache.demand_miss_rate::cpu0.data 0.085177 # miss rate for demand accesses
976system.cpu0.dcache.demand_miss_rate::total 0.085177 # miss rate for demand accesses
977system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088957 # miss rate for overall accesses
978system.cpu0.dcache.overall_miss_rate::total 0.088957 # miss rate for overall accesses
979system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14934.867826 # average ReadReq miss latency
980system.cpu0.dcache.ReadReq_avg_miss_latency::total 14934.867826 # average ReadReq miss latency
981system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17631.629103 # average WriteReq miss latency
982system.cpu0.dcache.WriteReq_avg_miss_latency::total 17631.629103 # average WriteReq miss latency
983system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 54130.313941 # average WriteInvalidateReq miss latency
984system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 54130.313941 # average WriteInvalidateReq miss latency
985system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14324.343221 # average LoadLockedReq miss latency
986system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14324.343221 # average LoadLockedReq miss latency
987system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21025.255134 # average StoreCondReq miss latency
988system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21025.255134 # average StoreCondReq miss latency
989system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
990system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
991system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16345.521190 # average overall miss latency
992system.cpu0.dcache.demand_avg_miss_latency::total 16345.521190 # average overall miss latency
993system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15564.167435 # average overall miss latency
994system.cpu0.dcache.overall_avg_miss_latency::total 15564.167435 # average overall miss latency
995system.cpu0.dcache.blocked_cycles::no_mshrs 13488103 # number of cycles access was blocked
996system.cpu0.dcache.blocked_cycles::no_targets 19786702 # number of cycles access was blocked
997system.cpu0.dcache.blocked::no_mshrs 752105 # number of cycles access was blocked
998system.cpu0.dcache.blocked::no_targets 757651 # number of cycles access was blocked
999system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.933803 # average number of cycles each access was blocked
1000system.cpu0.dcache.avg_blocked_cycles::no_targets 26.115853 # average number of cycles each access was blocked
1001system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1002system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1003system.cpu0.dcache.writebacks::writebacks 4276528 # number of writebacks
1004system.cpu0.dcache.writebacks::total 4276528 # number of writebacks
1005system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3664529 # number of ReadReq MSHR hits
1006system.cpu0.dcache.ReadReq_mshr_hits::total 3664529 # number of ReadReq MSHR hits
1007system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6233308 # number of WriteReq MSHR hits
1008system.cpu0.dcache.WriteReq_mshr_hits::total 6233308 # number of WriteReq MSHR hits
1009system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 4741 # number of WriteInvalidateReq MSHR hits
1010system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4741 # number of WriteInvalidateReq MSHR hits
1011system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 141328 # number of LoadLockedReq MSHR hits
1012system.cpu0.dcache.LoadLockedReq_mshr_hits::total 141328 # number of LoadLockedReq MSHR hits
1013system.cpu0.dcache.demand_mshr_hits::cpu0.data 9897837 # number of demand (read+write) MSHR hits
1014system.cpu0.dcache.demand_mshr_hits::total 9897837 # number of demand (read+write) MSHR hits
1015system.cpu0.dcache.overall_mshr_hits::cpu0.data 9897837 # number of overall MSHR hits
1016system.cpu0.dcache.overall_mshr_hits::total 9897837 # number of overall MSHR hits
1017system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3423563 # number of ReadReq MSHR misses
1018system.cpu0.dcache.ReadReq_mshr_misses::total 3423563 # number of ReadReq MSHR misses
1019system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1541188 # number of WriteReq MSHR misses
1020system.cpu0.dcache.WriteReq_mshr_misses::total 1541188 # number of WriteReq MSHR misses
1021system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 739665 # number of SoftPFReq MSHR misses
1022system.cpu0.dcache.SoftPFReq_mshr_misses::total 739665 # number of SoftPFReq MSHR misses
1023system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 838083 # number of WriteInvalidateReq MSHR misses
1024system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 838083 # number of WriteInvalidateReq MSHR misses
1025system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 139692 # number of LoadLockedReq MSHR misses
1026system.cpu0.dcache.LoadLockedReq_mshr_misses::total 139692 # number of LoadLockedReq MSHR misses
1027system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 209050 # number of StoreCondReq MSHR misses
1028system.cpu0.dcache.StoreCondReq_mshr_misses::total 209050 # number of StoreCondReq MSHR misses
1029system.cpu0.dcache.demand_mshr_misses::cpu0.data 4964751 # number of demand (read+write) MSHR misses
1030system.cpu0.dcache.demand_mshr_misses::total 4964751 # number of demand (read+write) MSHR misses
1031system.cpu0.dcache.overall_mshr_misses::cpu0.data 5704416 # number of overall MSHR misses
1032system.cpu0.dcache.overall_mshr_misses::total 5704416 # number of overall MSHR misses
1033system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44975748199 # number of ReadReq MSHR miss cycles
1034system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44975748199 # number of ReadReq MSHR miss cycles
1035system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 28501279892 # number of WriteReq MSHR miss cycles
1036system.cpu0.dcache.WriteReq_mshr_miss_latency::total 28501279892 # number of WriteReq MSHR miss cycles
1037system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16804666332 # number of SoftPFReq MSHR miss cycles
1038system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16804666332 # number of SoftPFReq MSHR miss cycles
1039system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 43773018566 # number of WriteInvalidateReq MSHR miss cycles
1040system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 43773018566 # number of WriteInvalidateReq MSHR miss cycles
1041system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1737566757 # number of LoadLockedReq MSHR miss cycles
1042system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1737566757 # number of LoadLockedReq MSHR miss cycles
1043system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3967184288 # number of StoreCondReq MSHR miss cycles
1044system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3967184288 # number of StoreCondReq MSHR miss cycles
1045system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3082000 # number of StoreCondFailReq MSHR miss cycles
1046system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3082000 # number of StoreCondFailReq MSHR miss cycles
1047system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 73477028091 # number of demand (read+write) MSHR miss cycles
1048system.cpu0.dcache.demand_mshr_miss_latency::total 73477028091 # number of demand (read+write) MSHR miss cycles
1049system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 90281694423 # number of overall MSHR miss cycles
1050system.cpu0.dcache.overall_mshr_miss_latency::total 90281694423 # number of overall MSHR miss cycles
1051system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5575976491 # number of ReadReq MSHR uncacheable cycles
1052system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5575976491 # number of ReadReq MSHR uncacheable cycles
1053system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5325987989 # number of WriteReq MSHR uncacheable cycles
1054system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5325987989 # number of WriteReq MSHR uncacheable cycles
1055system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10901964480 # number of overall MSHR uncacheable cycles
1056system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10901964480 # number of overall MSHR uncacheable cycles
1057system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036665 # mshr miss rate for ReadReq accesses
1058system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036665 # mshr miss rate for ReadReq accesses
1059system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019000 # mshr miss rate for WriteReq accesses
1060system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019000 # mshr miss rate for WriteReq accesses
1061system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759422 # mshr miss rate for SoftPFReq accesses
1062system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759422 # mshr miss rate for SoftPFReq accesses
1063system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.756868 # mshr miss rate for WriteInvalidateReq accesses
1064system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.756868 # mshr miss rate for WriteInvalidateReq accesses
1065system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064691 # mshr miss rate for LoadLockedReq accesses
1066system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064691 # mshr miss rate for LoadLockedReq accesses
1067system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098595 # mshr miss rate for StoreCondReq accesses
1068system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098595 # mshr miss rate for StoreCondReq accesses
1069system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028453 # mshr miss rate for demand accesses
1070system.cpu0.dcache.demand_mshr_miss_rate::total 0.028453 # mshr miss rate for demand accesses
1071system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032510 # mshr miss rate for overall accesses
1072system.cpu0.dcache.overall_mshr_miss_rate::total 0.032510 # mshr miss rate for overall accesses
1073system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13137.117149 # average ReadReq mshr miss latency
1074system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13137.117149 # average ReadReq mshr miss latency
1075system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18493.058531 # average WriteReq mshr miss latency
1076system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18493.058531 # average WriteReq mshr miss latency
1077system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22719.293642 # average SoftPFReq mshr miss latency
1078system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22719.293642 # average SoftPFReq mshr miss latency
1079system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 52229.932556 # average WriteInvalidateReq mshr miss latency
1080system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 52229.932556 # average WriteInvalidateReq mshr miss latency
1081system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12438.555945 # average LoadLockedReq mshr miss latency
1082system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12438.555945 # average LoadLockedReq mshr miss latency
1083system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18977.203004 # average StoreCondReq mshr miss latency
1084system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18977.203004 # average StoreCondReq mshr miss latency
1085system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
1086system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1087system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14799.740831 # average overall mshr miss latency
1088system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14799.740831 # average overall mshr miss latency
1089system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15826.632283 # average overall mshr miss latency
1090system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15826.632283 # average overall mshr miss latency
1091system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1092system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1093system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1094system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1095system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1096system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1097system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1098system.cpu0.icache.tags.replacements 6368542 # number of replacements
1099system.cpu0.icache.tags.tagsinuse 511.961816 # Cycle average of tags in use
1100system.cpu0.icache.tags.total_refs 222275153 # Total number of references to valid blocks.
1101system.cpu0.icache.tags.sampled_refs 6369054 # Sample count of references to valid blocks.
1102system.cpu0.icache.tags.avg_refs 34.899241 # Average number of references to valid blocks.
1103system.cpu0.icache.tags.warmup_cycle 14184385750 # Cycle when the warmup percentage was hit.
1104system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.961816 # Average occupied blocks per requestor
1105system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999925 # Average percentage of cache occupancy
1106system.cpu0.icache.tags.occ_percent::total 0.999925 # Average percentage of cache occupancy
1107system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1108system.cpu0.icache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id
1109system.cpu0.icache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id
1110system.cpu0.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
1111system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1112system.cpu0.icache.tags.tag_accesses 464315009 # Number of tag accesses
1113system.cpu0.icache.tags.data_accesses 464315009 # Number of data accesses
1114system.cpu0.icache.ReadReq_hits::cpu0.inst 222275153 # number of ReadReq hits
1115system.cpu0.icache.ReadReq_hits::total 222275153 # number of ReadReq hits
1116system.cpu0.icache.demand_hits::cpu0.inst 222275153 # number of demand (read+write) hits
1117system.cpu0.icache.demand_hits::total 222275153 # number of demand (read+write) hits
1118system.cpu0.icache.overall_hits::cpu0.inst 222275153 # number of overall hits
1119system.cpu0.icache.overall_hits::total 222275153 # number of overall hits
1120system.cpu0.icache.ReadReq_misses::cpu0.inst 6697664 # number of ReadReq misses
1121system.cpu0.icache.ReadReq_misses::total 6697664 # number of ReadReq misses
1122system.cpu0.icache.demand_misses::cpu0.inst 6697664 # number of demand (read+write) misses
1123system.cpu0.icache.demand_misses::total 6697664 # number of demand (read+write) misses
1124system.cpu0.icache.overall_misses::cpu0.inst 6697664 # number of overall misses
1125system.cpu0.icache.overall_misses::total 6697664 # number of overall misses
1126system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 70928372732 # number of ReadReq miss cycles
1127system.cpu0.icache.ReadReq_miss_latency::total 70928372732 # number of ReadReq miss cycles
1128system.cpu0.icache.demand_miss_latency::cpu0.inst 70928372732 # number of demand (read+write) miss cycles
1129system.cpu0.icache.demand_miss_latency::total 70928372732 # number of demand (read+write) miss cycles
1130system.cpu0.icache.overall_miss_latency::cpu0.inst 70928372732 # number of overall miss cycles
1131system.cpu0.icache.overall_miss_latency::total 70928372732 # number of overall miss cycles
1132system.cpu0.icache.ReadReq_accesses::cpu0.inst 228972817 # number of ReadReq accesses(hits+misses)
1133system.cpu0.icache.ReadReq_accesses::total 228972817 # number of ReadReq accesses(hits+misses)
1134system.cpu0.icache.demand_accesses::cpu0.inst 228972817 # number of demand (read+write) accesses
1135system.cpu0.icache.demand_accesses::total 228972817 # number of demand (read+write) accesses
1136system.cpu0.icache.overall_accesses::cpu0.inst 228972817 # number of overall (read+write) accesses
1137system.cpu0.icache.overall_accesses::total 228972817 # number of overall (read+write) accesses
1138system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029251 # miss rate for ReadReq accesses
1139system.cpu0.icache.ReadReq_miss_rate::total 0.029251 # miss rate for ReadReq accesses
1140system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029251 # miss rate for demand accesses
1141system.cpu0.icache.demand_miss_rate::total 0.029251 # miss rate for demand accesses
1142system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029251 # miss rate for overall accesses
1143system.cpu0.icache.overall_miss_rate::total 0.029251 # miss rate for overall accesses
1144system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10590.016569 # average ReadReq miss latency
1145system.cpu0.icache.ReadReq_avg_miss_latency::total 10590.016569 # average ReadReq miss latency
1146system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10590.016569 # average overall miss latency
1147system.cpu0.icache.demand_avg_miss_latency::total 10590.016569 # average overall miss latency
1148system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10590.016569 # average overall miss latency
1149system.cpu0.icache.overall_avg_miss_latency::total 10590.016569 # average overall miss latency
1150system.cpu0.icache.blocked_cycles::no_mshrs 8781241 # number of cycles access was blocked
1151system.cpu0.icache.blocked_cycles::no_targets 821 # number of cycles access was blocked
1152system.cpu0.icache.blocked::no_mshrs 708037 # number of cycles access was blocked
1153system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked
1154system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.402235 # average number of cycles each access was blocked
1155system.cpu0.icache.avg_blocked_cycles::no_targets 74.636364 # average number of cycles each access was blocked
1156system.cpu0.icache.fast_writes 0 # number of fast writes performed
1157system.cpu0.icache.cache_copies 0 # number of cache copies performed
1158system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 328289 # number of ReadReq MSHR hits
1159system.cpu0.icache.ReadReq_mshr_hits::total 328289 # number of ReadReq MSHR hits
1160system.cpu0.icache.demand_mshr_hits::cpu0.inst 328289 # number of demand (read+write) MSHR hits
1161system.cpu0.icache.demand_mshr_hits::total 328289 # number of demand (read+write) MSHR hits
1162system.cpu0.icache.overall_mshr_hits::cpu0.inst 328289 # number of overall MSHR hits
1163system.cpu0.icache.overall_mshr_hits::total 328289 # number of overall MSHR hits
1164system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6369375 # number of ReadReq MSHR misses
1165system.cpu0.icache.ReadReq_mshr_misses::total 6369375 # number of ReadReq MSHR misses
1166system.cpu0.icache.demand_mshr_misses::cpu0.inst 6369375 # number of demand (read+write) MSHR misses
1167system.cpu0.icache.demand_mshr_misses::total 6369375 # number of demand (read+write) MSHR misses
1168system.cpu0.icache.overall_mshr_misses::cpu0.inst 6369375 # number of overall MSHR misses
1169system.cpu0.icache.overall_mshr_misses::total 6369375 # number of overall MSHR misses
1170system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 57966761800 # number of ReadReq MSHR miss cycles
1171system.cpu0.icache.ReadReq_mshr_miss_latency::total 57966761800 # number of ReadReq MSHR miss cycles
1172system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 57966761800 # number of demand (read+write) MSHR miss cycles
1173system.cpu0.icache.demand_mshr_miss_latency::total 57966761800 # number of demand (read+write) MSHR miss cycles
1174system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 57966761800 # number of overall MSHR miss cycles
1175system.cpu0.icache.overall_mshr_miss_latency::total 57966761800 # number of overall MSHR miss cycles
1176system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1699560248 # number of ReadReq MSHR uncacheable cycles
1177system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1699560248 # number of ReadReq MSHR uncacheable cycles
1178system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1699560248 # number of overall MSHR uncacheable cycles
1179system.cpu0.icache.overall_mshr_uncacheable_latency::total 1699560248 # number of overall MSHR uncacheable cycles
1180system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027817 # mshr miss rate for ReadReq accesses
1181system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027817 # mshr miss rate for ReadReq accesses
1182system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027817 # mshr miss rate for demand accesses
1183system.cpu0.icache.demand_mshr_miss_rate::total 0.027817 # mshr miss rate for demand accesses
1184system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027817 # mshr miss rate for overall accesses
1185system.cpu0.icache.overall_mshr_miss_rate::total 0.027817 # mshr miss rate for overall accesses
1186system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9100.855547 # average ReadReq mshr miss latency
1187system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9100.855547 # average ReadReq mshr miss latency
1188system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9100.855547 # average overall mshr miss latency
1189system.cpu0.icache.demand_avg_mshr_miss_latency::total 9100.855547 # average overall mshr miss latency
1190system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9100.855547 # average overall mshr miss latency
1191system.cpu0.icache.overall_avg_mshr_miss_latency::total 9100.855547 # average overall mshr miss latency
1192system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1193system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1194system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1195system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1196system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1197system.cpu0.l2cache.prefetcher.num_hwpf_issued 8232125 # number of hwpf issued
1198system.cpu0.l2cache.prefetcher.pfIdentified 8569505 # number of prefetch candidates identified
1199system.cpu0.l2cache.prefetcher.pfBufferHit 292099 # number of redundant prefetches already in prefetch queue
1200system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1201system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1202system.cpu0.l2cache.prefetcher.pfSpanPage 1116447 # number of prefetches not generated due to page crossing
1203system.cpu0.l2cache.tags.replacements 2928300 # number of replacements
1204system.cpu0.l2cache.tags.tagsinuse 16202.554411 # Cycle average of tags in use
1205system.cpu0.l2cache.tags.total_refs 13089790 # Total number of references to valid blocks.
1206system.cpu0.l2cache.tags.sampled_refs 2944355 # Sample count of references to valid blocks.
1207system.cpu0.l2cache.tags.avg_refs 4.445724 # Average number of references to valid blocks.
1208system.cpu0.l2cache.tags.warmup_cycle 2067342500 # Cycle when the warmup percentage was hit.
1209system.cpu0.l2cache.tags.occ_blocks::writebacks 7528.605833 # Average occupied blocks per requestor
1210system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 71.466332 # Average occupied blocks per requestor
1211system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 91.040507 # Average occupied blocks per requestor
1212system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3487.680197 # Average occupied blocks per requestor
1213system.cpu0.l2cache.tags.occ_blocks::cpu0.data 4098.714387 # Average occupied blocks per requestor
1214system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 925.047154 # Average occupied blocks per requestor
1215system.cpu0.l2cache.tags.occ_percent::writebacks 0.459510 # Average percentage of cache occupancy
1216system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004362 # Average percentage of cache occupancy
1217system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005557 # Average percentage of cache occupancy
1218system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.212871 # Average percentage of cache occupancy
1219system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.250166 # Average percentage of cache occupancy
1220system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056460 # Average percentage of cache occupancy
1221system.cpu0.l2cache.tags.occ_percent::total 0.988925 # Average percentage of cache occupancy
1222system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1513 # Occupied blocks per task id
1223system.cpu0.l2cache.tags.occ_task_id_blocks::1023 121 # Occupied blocks per task id
1224system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14421 # Occupied blocks per task id
1225system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 66 # Occupied blocks per task id
1226system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id
1227system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 709 # Occupied blocks per task id
1228system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 196 # Occupied blocks per task id
1229system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 537 # Occupied blocks per task id
1230system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 13 # Occupied blocks per task id
1231system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 70 # Occupied blocks per task id
1232system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id
1233system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id
1234system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
1235system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 818 # Occupied blocks per task id
1236system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6042 # Occupied blocks per task id
1237system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2879 # Occupied blocks per task id
1238system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4513 # Occupied blocks per task id
1239system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.092346 # Percentage of cache occupancy per task id
1240system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.007385 # Percentage of cache occupancy per task id
1241system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.880188 # Percentage of cache occupancy per task id
1242system.cpu0.l2cache.tags.tag_accesses 298616625 # Number of tag accesses
1243system.cpu0.l2cache.tags.data_accesses 298616625 # Number of data accesses
1244system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 582155 # number of ReadReq hits
1245system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 182687 # number of ReadReq hits
1246system.cpu0.l2cache.ReadReq_hits::cpu0.inst 5666433 # number of ReadReq hits
1247system.cpu0.l2cache.ReadReq_hits::cpu0.data 3184946 # number of ReadReq hits
1248system.cpu0.l2cache.ReadReq_hits::total 9616221 # number of ReadReq hits
1249system.cpu0.l2cache.Writeback_hits::writebacks 4276521 # number of Writeback hits
1250system.cpu0.l2cache.Writeback_hits::total 4276521 # number of Writeback hits
1251system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 198743 # number of WriteInvalidateReq hits
1252system.cpu0.l2cache.WriteInvalidateReq_hits::total 198743 # number of WriteInvalidateReq hits
1253system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 114761 # number of UpgradeReq hits
1254system.cpu0.l2cache.UpgradeReq_hits::total 114761 # number of UpgradeReq hits
1255system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 36815 # number of SCUpgradeReq hits
1256system.cpu0.l2cache.SCUpgradeReq_hits::total 36815 # number of SCUpgradeReq hits
1257system.cpu0.l2cache.ReadExReq_hits::cpu0.data 991246 # number of ReadExReq hits
1258system.cpu0.l2cache.ReadExReq_hits::total 991246 # number of ReadExReq hits
1259system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 582155 # number of demand (read+write) hits
1260system.cpu0.l2cache.demand_hits::cpu0.itb.walker 182687 # number of demand (read+write) hits
1261system.cpu0.l2cache.demand_hits::cpu0.inst 5666433 # number of demand (read+write) hits
1262system.cpu0.l2cache.demand_hits::cpu0.data 4176192 # number of demand (read+write) hits
1263system.cpu0.l2cache.demand_hits::total 10607467 # number of demand (read+write) hits
1264system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 582155 # number of overall hits
1265system.cpu0.l2cache.overall_hits::cpu0.itb.walker 182687 # number of overall hits
1266system.cpu0.l2cache.overall_hits::cpu0.inst 5666433 # number of overall hits
1267system.cpu0.l2cache.overall_hits::cpu0.data 4176192 # number of overall hits
1268system.cpu0.l2cache.overall_hits::total 10607467 # number of overall hits
1269system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12607 # number of ReadReq misses
1270system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9261 # number of ReadReq misses
1271system.cpu0.l2cache.ReadReq_misses::cpu0.inst 702626 # number of ReadReq misses
1272system.cpu0.l2cache.ReadReq_misses::cpu0.data 1115482 # number of ReadReq misses
1273system.cpu0.l2cache.ReadReq_misses::total 1839976 # number of ReadReq misses
1274system.cpu0.l2cache.Writeback_misses::writebacks 4 # number of Writeback misses
1275system.cpu0.l2cache.Writeback_misses::total 4 # number of Writeback misses
1276system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 637762 # number of WriteInvalidateReq misses
1277system.cpu0.l2cache.WriteInvalidateReq_misses::total 637762 # number of WriteInvalidateReq misses
1278system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 138114 # number of UpgradeReq misses
1279system.cpu0.l2cache.UpgradeReq_misses::total 138114 # number of UpgradeReq misses
1280system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 172230 # number of SCUpgradeReq misses
1281system.cpu0.l2cache.SCUpgradeReq_misses::total 172230 # number of SCUpgradeReq misses
1282system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses
1283system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses
1284system.cpu0.l2cache.ReadExReq_misses::cpu0.data 309290 # number of ReadExReq misses
1285system.cpu0.l2cache.ReadExReq_misses::total 309290 # number of ReadExReq misses
1286system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12607 # number of demand (read+write) misses
1287system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9261 # number of demand (read+write) misses
1288system.cpu0.l2cache.demand_misses::cpu0.inst 702626 # number of demand (read+write) misses
1289system.cpu0.l2cache.demand_misses::cpu0.data 1424772 # number of demand (read+write) misses
1290system.cpu0.l2cache.demand_misses::total 2149266 # number of demand (read+write) misses
1291system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12607 # number of overall misses
1292system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9261 # number of overall misses
1293system.cpu0.l2cache.overall_misses::cpu0.inst 702626 # number of overall misses
1294system.cpu0.l2cache.overall_misses::cpu0.data 1424772 # number of overall misses
1295system.cpu0.l2cache.overall_misses::total 2149266 # number of overall misses
1296system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 468497682 # number of ReadReq miss cycles
1297system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 383886915 # number of ReadReq miss cycles
1298system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 20661944862 # number of ReadReq miss cycles
1299system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 39743352793 # number of ReadReq miss cycles
1300system.cpu0.l2cache.ReadReq_miss_latency::total 61257682252 # number of ReadReq miss cycles
1301system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 212101792 # number of WriteInvalidateReq miss cycles
1302system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 212101792 # number of WriteInvalidateReq miss cycles
1303system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2828322980 # number of UpgradeReq miss cycles
1304system.cpu0.l2cache.UpgradeReq_miss_latency::total 2828322980 # number of UpgradeReq miss cycles
1305system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3448129857 # number of SCUpgradeReq miss cycles
1306system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3448129857 # number of SCUpgradeReq miss cycles
1307system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3007000 # number of SCUpgradeFailReq miss cycles
1308system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3007000 # number of SCUpgradeFailReq miss cycles
1309system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16311576734 # number of ReadExReq miss cycles
1310system.cpu0.l2cache.ReadExReq_miss_latency::total 16311576734 # number of ReadExReq miss cycles
1311system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 468497682 # number of demand (read+write) miss cycles
1312system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 383886915 # number of demand (read+write) miss cycles
1313system.cpu0.l2cache.demand_miss_latency::cpu0.inst 20661944862 # number of demand (read+write) miss cycles
1314system.cpu0.l2cache.demand_miss_latency::cpu0.data 56054929527 # number of demand (read+write) miss cycles
1315system.cpu0.l2cache.demand_miss_latency::total 77569258986 # number of demand (read+write) miss cycles
1316system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 468497682 # number of overall miss cycles
1317system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 383886915 # number of overall miss cycles
1318system.cpu0.l2cache.overall_miss_latency::cpu0.inst 20661944862 # number of overall miss cycles
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1325system.cpu0.l2cache.ReadReq_accesses::total 11456197 # number of ReadReq accesses(hits+misses)
1326system.cpu0.l2cache.Writeback_accesses::writebacks 4276525 # number of Writeback accesses(hits+misses)
1327system.cpu0.l2cache.Writeback_accesses::total 4276525 # number of Writeback accesses(hits+misses)
1328system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 836505 # number of WriteInvalidateReq accesses(hits+misses)
1329system.cpu0.l2cache.WriteInvalidateReq_accesses::total 836505 # number of WriteInvalidateReq accesses(hits+misses)
1330system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 252875 # number of UpgradeReq accesses(hits+misses)
1331system.cpu0.l2cache.UpgradeReq_accesses::total 252875 # number of UpgradeReq accesses(hits+misses)
1332system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 209045 # number of SCUpgradeReq accesses(hits+misses)
1333system.cpu0.l2cache.SCUpgradeReq_accesses::total 209045 # number of SCUpgradeReq accesses(hits+misses)
1334system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses)
1335system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses)
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1337system.cpu0.l2cache.ReadExReq_accesses::total 1300536 # number of ReadExReq accesses(hits+misses)
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1339system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 191948 # number of demand (read+write) accesses
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1344system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 191948 # number of overall (read+write) accesses
1345system.cpu0.l2cache.overall_accesses::cpu0.inst 6369059 # number of overall (read+write) accesses
1346system.cpu0.l2cache.overall_accesses::cpu0.data 5600964 # number of overall (read+write) accesses
1347system.cpu0.l2cache.overall_accesses::total 12756733 # number of overall (read+write) accesses
1348system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021197 # miss rate for ReadReq accesses
1349system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.048247 # miss rate for ReadReq accesses
1350system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.110319 # miss rate for ReadReq accesses
1351system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.259389 # miss rate for ReadReq accesses
1352system.cpu0.l2cache.ReadReq_miss_rate::total 0.160610 # miss rate for ReadReq accesses
1353system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000001 # miss rate for Writeback accesses
1354system.cpu0.l2cache.Writeback_miss_rate::total 0.000001 # miss rate for Writeback accesses
1355system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.762413 # miss rate for WriteInvalidateReq accesses
1356system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.762413 # miss rate for WriteInvalidateReq accesses
1357system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.546175 # miss rate for UpgradeReq accesses
1358system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.546175 # miss rate for UpgradeReq accesses
1359system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.823890 # miss rate for SCUpgradeReq accesses
1360system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.823890 # miss rate for SCUpgradeReq accesses
1361system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1362system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1363system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.237817 # miss rate for ReadExReq accesses
1364system.cpu0.l2cache.ReadExReq_miss_rate::total 0.237817 # miss rate for ReadExReq accesses
1365system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021197 # miss rate for demand accesses
1366system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.048247 # miss rate for demand accesses
1367system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.110319 # miss rate for demand accesses
1368system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.254380 # miss rate for demand accesses
1369system.cpu0.l2cache.demand_miss_rate::total 0.168481 # miss rate for demand accesses
1370system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021197 # miss rate for overall accesses
1371system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.048247 # miss rate for overall accesses
1372system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.110319 # miss rate for overall accesses
1373system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.254380 # miss rate for overall accesses
1374system.cpu0.l2cache.overall_miss_rate::total 0.168481 # miss rate for overall accesses
1375system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 37161.710320 # average ReadReq miss latency
1376system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41451.993845 # average ReadReq miss latency
1377system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 29406.746779 # average ReadReq miss latency
1378system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 35628.860701 # average ReadReq miss latency
1379system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33292.652867 # average ReadReq miss latency
1380system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 332.572013 # average WriteInvalidateReq miss latency
1381system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 332.572013 # average WriteInvalidateReq miss latency
1382system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 20478.177303 # average UpgradeReq miss latency
1383system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 20478.177303 # average UpgradeReq miss latency
1384system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20020.495018 # average SCUpgradeReq miss latency
1385system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20020.495018 # average SCUpgradeReq miss latency
1386system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 601400 # average SCUpgradeFailReq miss latency
1387system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 601400 # average SCUpgradeFailReq miss latency
1388system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 52738.778279 # average ReadExReq miss latency
1389system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 52738.778279 # average ReadExReq miss latency
1390system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 37161.710320 # average overall miss latency
1391system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41451.993845 # average overall miss latency
1392system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29406.746779 # average overall miss latency
1393system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 39343.087545 # average overall miss latency
1394system.cpu0.l2cache.demand_avg_miss_latency::total 36091.046425 # average overall miss latency
1395system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 37161.710320 # average overall miss latency
1396system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41451.993845 # average overall miss latency
1397system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29406.746779 # average overall miss latency
1398system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 39343.087545 # average overall miss latency
1399system.cpu0.l2cache.overall_avg_miss_latency::total 36091.046425 # average overall miss latency
1400system.cpu0.l2cache.blocked_cycles::no_mshrs 272 # number of cycles access was blocked
1401system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1402system.cpu0.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked
1403system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1404system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 38.857143 # average number of cycles each access was blocked
1405system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1406system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1407system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1408system.cpu0.l2cache.writebacks::writebacks 1592666 # number of writebacks
1409system.cpu0.l2cache.writebacks::total 1592666 # number of writebacks
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1413system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 5842 # number of ReadReq MSHR hits
1414system.cpu0.l2cache.ReadReq_mshr_hits::total 6026 # number of ReadReq MSHR hits
1415system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 65 # number of WriteInvalidateReq MSHR hits
1416system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 65 # number of WriteInvalidateReq MSHR hits
1417system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 39394 # number of ReadExReq MSHR hits
1418system.cpu0.l2cache.ReadExReq_mshr_hits::total 39394 # number of ReadExReq MSHR hits
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1430system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9083 # number of ReadReq MSHR misses
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1435system.cpu0.l2cache.Writeback_mshr_misses::total 4 # number of Writeback MSHR misses
1436system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 823501 # number of HardPFReq MSHR misses
1437system.cpu0.l2cache.HardPFReq_mshr_misses::total 823501 # number of HardPFReq MSHR misses
1438system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 637697 # number of WriteInvalidateReq MSHR misses
1439system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 637697 # number of WriteInvalidateReq MSHR misses
1440system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 138114 # number of UpgradeReq MSHR misses
1441system.cpu0.l2cache.UpgradeReq_mshr_misses::total 138114 # number of UpgradeReq MSHR misses
1442system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 172230 # number of SCUpgradeReq MSHR misses
1443system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 172230 # number of SCUpgradeReq MSHR misses
1444system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses
1445system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses
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1448system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12604 # number of demand (read+write) MSHR misses
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1453system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12604 # number of overall MSHR misses
1454system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9083 # number of overall MSHR misses
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1458system.cpu0.l2cache.overall_mshr_misses::total 2927347 # number of overall MSHR misses
1459system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 379527210 # number of ReadReq MSHR miss cycles
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1461system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 15722901634 # number of ReadReq MSHR miss cycles
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1463system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 48028791660 # number of ReadReq MSHR miss cycles
1464system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 55041075389 # number of HardPFReq MSHR miss cycles
1465system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 55041075389 # number of HardPFReq MSHR miss cycles
1466system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 36305734974 # number of WriteInvalidateReq MSHR miss cycles
1467system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 36305734974 # number of WriteInvalidateReq MSHR miss cycles
1468system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2408365451 # number of UpgradeReq MSHR miss cycles
1469system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2408365451 # number of UpgradeReq MSHR miss cycles
1470system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2333282169 # number of SCUpgradeReq MSHR miss cycles
1471system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2333282169 # number of SCUpgradeReq MSHR miss cycles
1472system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2482000 # number of SCUpgradeFailReq MSHR miss cycles
1473system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2482000 # number of SCUpgradeFailReq MSHR miss cycles
1474system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11186143543 # number of ReadExReq MSHR miss cycles
1475system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11186143543 # number of ReadExReq MSHR miss cycles
1476system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 379527210 # number of demand (read+write) MSHR miss cycles
1477system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 312895441 # number of demand (read+write) MSHR miss cycles
1478system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 15722901634 # number of demand (read+write) MSHR miss cycles
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1480system.cpu0.l2cache.demand_mshr_miss_latency::total 59214935203 # number of demand (read+write) MSHR miss cycles
1481system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 379527210 # number of overall MSHR miss cycles
1482system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 312895441 # number of overall MSHR miss cycles
1483system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 15722901634 # number of overall MSHR miss cycles
1484system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 42799610918 # number of overall MSHR miss cycles
1485system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 55041075389 # number of overall MSHR miss cycles
1486system.cpu0.l2cache.overall_mshr_miss_latency::total 114256010592 # number of overall MSHR miss cycles
1487system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1519174250 # number of ReadReq MSHR uncacheable cycles
1488system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5322353508 # number of ReadReq MSHR uncacheable cycles
1489system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6841527758 # number of ReadReq MSHR uncacheable cycles
1490system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5082599974 # number of WriteReq MSHR uncacheable cycles
1491system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5082599974 # number of WriteReq MSHR uncacheable cycles
1492system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1519174250 # number of overall MSHR uncacheable cycles
1493system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10404953482 # number of overall MSHR uncacheable cycles
1494system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11924127732 # number of overall MSHR uncacheable cycles
1495system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021192 # mshr miss rate for ReadReq accesses
1496system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.047320 # mshr miss rate for ReadReq accesses
1497system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.110318 # mshr miss rate for ReadReq accesses
1498system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.258030 # mshr miss rate for ReadReq accesses
1499system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.160084 # mshr miss rate for ReadReq accesses
1500system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for Writeback accesses
1501system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000001 # mshr miss rate for Writeback accesses
1502system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1503system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1504system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.762335 # mshr miss rate for WriteInvalidateReq accesses
1505system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.762335 # mshr miss rate for WriteInvalidateReq accesses
1506system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.546175 # mshr miss rate for UpgradeReq accesses
1507system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.546175 # mshr miss rate for UpgradeReq accesses
1508system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.823890 # mshr miss rate for SCUpgradeReq accesses
1509system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.823890 # mshr miss rate for SCUpgradeReq accesses
1510system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1511system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1512system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.207527 # mshr miss rate for ReadExReq accesses
1513system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.207527 # mshr miss rate for ReadExReq accesses
1514system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021192 # mshr miss rate for demand accesses
1515system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.047320 # mshr miss rate for demand accesses
1516system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.110318 # mshr miss rate for demand accesses
1517system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.246303 # mshr miss rate for demand accesses
1518system.cpu0.l2cache.demand_mshr_miss_rate::total 0.164920 # mshr miss rate for demand accesses
1519system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021192 # mshr miss rate for overall accesses
1520system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.047320 # mshr miss rate for overall accesses
1521system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.110318 # mshr miss rate for overall accesses
1522system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.246303 # mshr miss rate for overall accesses
1523system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1524system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229475 # mshr miss rate for overall accesses
1525system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890 # average ReadReq mshr miss latency
1526system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678 # average ReadReq mshr miss latency
1527system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22377.436597 # average ReadReq mshr miss latency
1528system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 28489.841187 # average ReadReq mshr miss latency
1529system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26188.713793 # average ReadReq mshr miss latency
1530system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66837.897451 # average HardPFReq mshr miss latency
1531system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 66837.897451 # average HardPFReq mshr miss latency
1532system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 56932.579225 # average WriteInvalidateReq mshr miss latency
1533system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 56932.579225 # average WriteInvalidateReq mshr miss latency
1534system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17437.518651 # average UpgradeReq mshr miss latency
1535system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17437.518651 # average UpgradeReq mshr miss latency
1536system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13547.478192 # average SCUpgradeReq mshr miss latency
1537system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13547.478192 # average SCUpgradeReq mshr miss latency
1538system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 496400 # average SCUpgradeFailReq mshr miss latency
1539system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 496400 # average SCUpgradeFailReq mshr miss latency
1540system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41446.125704 # average ReadExReq mshr miss latency
1541system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41446.125704 # average ReadExReq mshr miss latency
1542system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890 # average overall mshr miss latency
1543system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678 # average overall mshr miss latency
1544system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22377.436597 # average overall mshr miss latency
1545system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31024.642284 # average overall mshr miss latency
1546system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28146.040729 # average overall mshr miss latency
1547system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890 # average overall mshr miss latency
1548system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678 # average overall mshr miss latency
1549system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22377.436597 # average overall mshr miss latency
1550system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31024.642284 # average overall mshr miss latency
1551system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66837.897451 # average overall mshr miss latency
1552system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39030.566104 # average overall mshr miss latency
1553system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1554system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1555system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1556system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1557system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1558system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1559system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1560system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1561system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1562system.cpu0.toL2Bus.trans_dist::ReadReq 13921371 # Transaction distribution
1563system.cpu0.toL2Bus.trans_dist::ReadResp 11750633 # Transaction distribution
1564system.cpu0.toL2Bus.trans_dist::WriteReq 31686 # Transaction distribution
1565system.cpu0.toL2Bus.trans_dist::WriteResp 31686 # Transaction distribution
1566system.cpu0.toL2Bus.trans_dist::Writeback 4276525 # Transaction distribution
1567system.cpu0.toL2Bus.trans_dist::HardPFReq 1274288 # Transaction distribution
1568system.cpu0.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution
1569system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1162561 # Transaction distribution
1570system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 836505 # Transaction distribution
1571system.cpu0.toL2Bus.trans_dist::UpgradeReq 509905 # Transaction distribution
1572system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 381643 # Transaction distribution
1573system.cpu0.toL2Bus.trans_dist::UpgradeResp 535354 # Transaction distribution
1574system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 87 # Transaction distribution
1575system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 157 # Transaction distribution
1576system.cpu0.toL2Bus.trans_dist::ReadExReq 1437620 # Transaction distribution
1577system.cpu0.toL2Bus.trans_dist::ReadExResp 1309284 # Transaction distribution
1578system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12781022 # Packet count per connected master and slave (bytes)
1579system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18390339 # Packet count per connected master and slave (bytes)
1580system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 414542 # Packet count per connected master and slave (bytes)
1581system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1294088 # Packet count per connected master and slave (bytes)
1582system.cpu0.toL2Bus.pkt_count::total 32879991 # Packet count per connected master and slave (bytes)
1583system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 407960480 # Cumulative packet size per connected master and slave (bytes)
1584system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 693234728 # Cumulative packet size per connected master and slave (bytes)
1585system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1535584 # Cumulative packet size per connected master and slave (bytes)
1586system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4758096 # Cumulative packet size per connected master and slave (bytes)
1587system.cpu0.toL2Bus.pkt_size::total 1107488888 # Cumulative packet size per connected master and slave (bytes)
1588system.cpu0.toL2Bus.snoops 4767578 # Total snoops (count)
1589system.cpu0.toL2Bus.snoop_fanout::samples 22911203 # Request fanout histogram
1590system.cpu0.toL2Bus.snoop_fanout::mean 5.193957 # Request fanout histogram
1591system.cpu0.toL2Bus.snoop_fanout::stdev 0.395396 # Request fanout histogram
1592system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1593system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1594system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1595system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1596system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
1597system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
1598system.cpu0.toL2Bus.snoop_fanout::5 18467409 80.60% 80.60% # Request fanout histogram
1599system.cpu0.toL2Bus.snoop_fanout::6 4443794 19.40% 100.00% # Request fanout histogram
1600system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1601system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
1602system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
1603system.cpu0.toL2Bus.snoop_fanout::total 22911203 # Request fanout histogram
1604system.cpu0.toL2Bus.reqLayer0.occupancy 14408211332 # Layer occupancy (ticks)
1605system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1606system.cpu0.toL2Bus.snoopLayer0.occupancy 208870495 # Layer occupancy (ticks)
1607system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1608system.cpu0.toL2Bus.respLayer0.occupancy 9596174213 # Layer occupancy (ticks)
1609system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1610system.cpu0.toL2Bus.respLayer1.occupancy 9165770534 # Layer occupancy (ticks)
1611system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1612system.cpu0.toL2Bus.respLayer2.occupancy 223497560 # Layer occupancy (ticks)
1613system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1614system.cpu0.toL2Bus.respLayer3.occupancy 700918244 # Layer occupancy (ticks)
1615system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1616system.cpu1.branchPred.lookups 124370032 # Number of BP lookups
1617system.cpu1.branchPred.condPredicted 83075187 # Number of conditional branches predicted
1618system.cpu1.branchPred.condIncorrect 6189003 # Number of conditional branches incorrect
1619system.cpu1.branchPred.BTBLookups 87824878 # Number of BTB lookups
1620system.cpu1.branchPred.BTBHits 56905034 # Number of BTB hits
1621system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1622system.cpu1.branchPred.BTBHitPct 64.793752 # BTB Hit Percentage
1623system.cpu1.branchPred.usedRAS 16687776 # Number of times the RAS was used to get a target.
1624system.cpu1.branchPred.RASInCorrect 168367 # Number of incorrect RAS predictions.
1625system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1626system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1627system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1628system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1629system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1630system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1631system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1632system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1646system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1647system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1648system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1649system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1650system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1651system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1652system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1653system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1654system.cpu1.dtb.walker.walks 538943 # Table walker walks requested
1655system.cpu1.dtb.walker.walksLong 538943 # Table walker walks initiated with long descriptors
1656system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11373 # Level at which table walker walks with long descriptors terminate
1657system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 87574 # Level at which table walker walks with long descriptors terminate
1658system.cpu1.dtb.walker.walksSquashedBefore 237839 # Table walks squashed before starting
1659system.cpu1.dtb.walker.walkWaitTime::samples 301104 # Table walker wait (enqueue to first request) latency
1660system.cpu1.dtb.walker.walkWaitTime::mean 1852.353340 # Table walker wait (enqueue to first request) latency
1661system.cpu1.dtb.walker.walkWaitTime::stdev 11107.804354 # Table walker wait (enqueue to first request) latency
1662system.cpu1.dtb.walker.walkWaitTime::0-32767 297190 98.70% 98.70% # Table walker wait (enqueue to first request) latency
1663system.cpu1.dtb.walker.walkWaitTime::32768-65535 2030 0.67% 99.37% # Table walker wait (enqueue to first request) latency
1664system.cpu1.dtb.walker.walkWaitTime::65536-98303 795 0.26% 99.64% # Table walker wait (enqueue to first request) latency
1665system.cpu1.dtb.walker.walkWaitTime::98304-131071 637 0.21% 99.85% # Table walker wait (enqueue to first request) latency
1666system.cpu1.dtb.walker.walkWaitTime::131072-163839 257 0.09% 99.94% # Table walker wait (enqueue to first request) latency
1667system.cpu1.dtb.walker.walkWaitTime::163840-196607 66 0.02% 99.96% # Table walker wait (enqueue to first request) latency
1668system.cpu1.dtb.walker.walkWaitTime::196608-229375 39 0.01% 99.97% # Table walker wait (enqueue to first request) latency
1669system.cpu1.dtb.walker.walkWaitTime::229376-262143 29 0.01% 99.98% # Table walker wait (enqueue to first request) latency
1670system.cpu1.dtb.walker.walkWaitTime::262144-294911 48 0.02% 100.00% # Table walker wait (enqueue to first request) latency
1671system.cpu1.dtb.walker.walkWaitTime::294912-327679 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1672system.cpu1.dtb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1673system.cpu1.dtb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1674system.cpu1.dtb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1675system.cpu1.dtb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1676system.cpu1.dtb.walker.walkWaitTime::total 301104 # Table walker wait (enqueue to first request) latency
1677system.cpu1.dtb.walker.walkCompletionTime::samples 268131 # Table walker service (enqueue to completion) latency
1678system.cpu1.dtb.walker.walkCompletionTime::mean 15772.437909 # Table walker service (enqueue to completion) latency
1679system.cpu1.dtb.walker.walkCompletionTime::gmean 12981.371112 # Table walker service (enqueue to completion) latency
1680system.cpu1.dtb.walker.walkCompletionTime::stdev 15992.673962 # Table walker service (enqueue to completion) latency
1681system.cpu1.dtb.walker.walkCompletionTime::0-65535 265367 98.97% 98.97% # Table walker service (enqueue to completion) latency
1682system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1941 0.72% 99.69% # Table walker service (enqueue to completion) latency
1683system.cpu1.dtb.walker.walkCompletionTime::131072-196607 396 0.15% 99.84% # Table walker service (enqueue to completion) latency
1684system.cpu1.dtb.walker.walkCompletionTime::196608-262143 232 0.09% 99.93% # Table walker service (enqueue to completion) latency
1685system.cpu1.dtb.walker.walkCompletionTime::262144-327679 106 0.04% 99.97% # Table walker service (enqueue to completion) latency
1686system.cpu1.dtb.walker.walkCompletionTime::327680-393215 37 0.01% 99.98% # Table walker service (enqueue to completion) latency
1687system.cpu1.dtb.walker.walkCompletionTime::393216-458751 35 0.01% 99.99% # Table walker service (enqueue to completion) latency
1688system.cpu1.dtb.walker.walkCompletionTime::458752-524287 12 0.00% 100.00% # Table walker service (enqueue to completion) latency
1689system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1690system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1691system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1692system.cpu1.dtb.walker.walkCompletionTime::total 268131 # Table walker service (enqueue to completion) latency
1693system.cpu1.dtb.walker.walksPending::samples 435751861088 # Table walker pending requests distribution
1694system.cpu1.dtb.walker.walksPending::mean 0.614829 # Table walker pending requests distribution
1695system.cpu1.dtb.walker.walksPending::stdev 0.532518 # Table walker pending requests distribution
1696system.cpu1.dtb.walker.walksPending::0-1 434859464588 99.80% 99.80% # Table walker pending requests distribution
1697system.cpu1.dtb.walker.walksPending::2-3 474800000 0.11% 99.90% # Table walker pending requests distribution
1698system.cpu1.dtb.walker.walksPending::4-5 202701000 0.05% 99.95% # Table walker pending requests distribution
1699system.cpu1.dtb.walker.walksPending::6-7 89682000 0.02% 99.97% # Table walker pending requests distribution
1700system.cpu1.dtb.walker.walksPending::8-9 62866500 0.01% 99.99% # Table walker pending requests distribution
1701system.cpu1.dtb.walker.walksPending::10-11 34103000 0.01% 99.99% # Table walker pending requests distribution
1702system.cpu1.dtb.walker.walksPending::12-13 13310500 0.00% 100.00% # Table walker pending requests distribution
1703system.cpu1.dtb.walker.walksPending::14-15 14713000 0.00% 100.00% # Table walker pending requests distribution
1704system.cpu1.dtb.walker.walksPending::16-17 214000 0.00% 100.00% # Table walker pending requests distribution
1705system.cpu1.dtb.walker.walksPending::18-19 6500 0.00% 100.00% # Table walker pending requests distribution
1706system.cpu1.dtb.walker.walksPending::total 435751861088 # Table walker pending requests distribution
1707system.cpu1.dtb.walker.walkPageSizes::4K 87574 88.51% 88.51% # Table walker page sizes translated
1708system.cpu1.dtb.walker.walkPageSizes::2M 11373 11.49% 100.00% # Table walker page sizes translated
1709system.cpu1.dtb.walker.walkPageSizes::total 98947 # Table walker page sizes translated
1710system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 538943 # Table walker requests started/completed, data/inst
1711system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1712system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 538943 # Table walker requests started/completed, data/inst
1713system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 98947 # Table walker requests started/completed, data/inst
1714system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1715system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 98947 # Table walker requests started/completed, data/inst
1716system.cpu1.dtb.walker.walkRequestOrigin::total 637890 # Table walker requests started/completed, data/inst
1717system.cpu1.dtb.inst_hits 0 # ITB inst hits
1718system.cpu1.dtb.inst_misses 0 # ITB inst misses
1719system.cpu1.dtb.read_hits 91392867 # DTB read hits
1720system.cpu1.dtb.read_misses 373745 # DTB read misses
1721system.cpu1.dtb.write_hits 75805429 # DTB write hits
1722system.cpu1.dtb.write_misses 165198 # DTB write misses
1723system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1724system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1725system.cpu1.dtb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID
1726system.cpu1.dtb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID
1727system.cpu1.dtb.flush_entries 37451 # Number of entries that have been flushed from TLB
1728system.cpu1.dtb.align_faults 309 # Number of TLB faults due to alignment restrictions
1729system.cpu1.dtb.prefetch_faults 5879 # Number of TLB faults due to prefetch
1730system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1731system.cpu1.dtb.perms_faults 40297 # Number of TLB faults due to permissions restrictions
1732system.cpu1.dtb.read_accesses 91766612 # DTB read accesses
1733system.cpu1.dtb.write_accesses 75970627 # DTB write accesses
1734system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1735system.cpu1.dtb.hits 167198296 # DTB hits
1736system.cpu1.dtb.misses 538943 # DTB misses
1737system.cpu1.dtb.accesses 167737239 # DTB accesses
1738system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1739system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1740system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1741system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1742system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1743system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1744system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1745system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1759system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1760system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1761system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1762system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1763system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1764system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1765system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1766system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1767system.cpu1.itb.walker.walks 85244 # Table walker walks requested
1768system.cpu1.itb.walker.walksLong 85244 # Table walker walks initiated with long descriptors
1769system.cpu1.itb.walker.walksLongTerminationLevel::Level2 675 # Level at which table walker walks with long descriptors terminate
1770system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61262 # Level at which table walker walks with long descriptors terminate
1771system.cpu1.itb.walker.walksSquashedBefore 9941 # Table walks squashed before starting
1772system.cpu1.itb.walker.walkWaitTime::samples 75303 # Table walker wait (enqueue to first request) latency
1773system.cpu1.itb.walker.walkWaitTime::mean 1139.330438 # Table walker wait (enqueue to first request) latency
1774system.cpu1.itb.walker.walkWaitTime::stdev 8399.837182 # Table walker wait (enqueue to first request) latency
1775system.cpu1.itb.walker.walkWaitTime::0-32767 74771 99.29% 99.29% # Table walker wait (enqueue to first request) latency
1776system.cpu1.itb.walker.walkWaitTime::32768-65535 180 0.24% 99.53% # Table walker wait (enqueue to first request) latency
1777system.cpu1.itb.walker.walkWaitTime::65536-98303 193 0.26% 99.79% # Table walker wait (enqueue to first request) latency
1778system.cpu1.itb.walker.walkWaitTime::98304-131071 128 0.17% 99.96% # Table walker wait (enqueue to first request) latency
1779system.cpu1.itb.walker.walkWaitTime::131072-163839 12 0.02% 99.97% # Table walker wait (enqueue to first request) latency
1780system.cpu1.itb.walker.walkWaitTime::163840-196607 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency
1781system.cpu1.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency
1782system.cpu1.itb.walker.walkWaitTime::262144-294911 6 0.01% 100.00% # Table walker wait (enqueue to first request) latency
1783system.cpu1.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1784system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1785system.cpu1.itb.walker.walkWaitTime::total 75303 # Table walker wait (enqueue to first request) latency
1786system.cpu1.itb.walker.walkCompletionTime::samples 71878 # Table walker service (enqueue to completion) latency
1787system.cpu1.itb.walker.walkCompletionTime::mean 20268.763168 # Table walker service (enqueue to completion) latency
1788system.cpu1.itb.walker.walkCompletionTime::gmean 17115.147893 # Table walker service (enqueue to completion) latency
1789system.cpu1.itb.walker.walkCompletionTime::stdev 19721.935997 # Table walker service (enqueue to completion) latency
1790system.cpu1.itb.walker.walkCompletionTime::0-65535 70231 97.71% 97.71% # Table walker service (enqueue to completion) latency
1791system.cpu1.itb.walker.walkCompletionTime::65536-131071 1324 1.84% 99.55% # Table walker service (enqueue to completion) latency
1792system.cpu1.itb.walker.walkCompletionTime::131072-196607 179 0.25% 99.80% # Table walker service (enqueue to completion) latency
1793system.cpu1.itb.walker.walkCompletionTime::196608-262143 68 0.09% 99.89% # Table walker service (enqueue to completion) latency
1794system.cpu1.itb.walker.walkCompletionTime::262144-327679 46 0.06% 99.96% # Table walker service (enqueue to completion) latency
1795system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.98% # Table walker service (enqueue to completion) latency
1796system.cpu1.itb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency
1797system.cpu1.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
1798system.cpu1.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
1799system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1800system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1801system.cpu1.itb.walker.walkCompletionTime::total 71878 # Table walker service (enqueue to completion) latency
1802system.cpu1.itb.walker.walksPending::samples 397094361424 # Table walker pending requests distribution
1803system.cpu1.itb.walker.walksPending::mean 0.878531 # Table walker pending requests distribution
1804system.cpu1.itb.walker.walksPending::stdev 0.326828 # Table walker pending requests distribution
1805system.cpu1.itb.walker.walksPending::0 48253813024 12.15% 12.15% # Table walker pending requests distribution
1806system.cpu1.itb.walker.walksPending::1 348822790900 87.84% 100.00% # Table walker pending requests distribution
1807system.cpu1.itb.walker.walksPending::2 16535000 0.00% 100.00% # Table walker pending requests distribution
1808system.cpu1.itb.walker.walksPending::3 1219500 0.00% 100.00% # Table walker pending requests distribution
1809system.cpu1.itb.walker.walksPending::4 3000 0.00% 100.00% # Table walker pending requests distribution
1810system.cpu1.itb.walker.walksPending::total 397094361424 # Table walker pending requests distribution
1811system.cpu1.itb.walker.walkPageSizes::4K 61262 98.91% 98.91% # Table walker page sizes translated
1812system.cpu1.itb.walker.walkPageSizes::2M 675 1.09% 100.00% # Table walker page sizes translated
1813system.cpu1.itb.walker.walkPageSizes::total 61937 # Table walker page sizes translated
1814system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1815system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 85244 # Table walker requests started/completed, data/inst
1816system.cpu1.itb.walker.walkRequestOrigin_Requested::total 85244 # Table walker requests started/completed, data/inst
1817system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1818system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61937 # Table walker requests started/completed, data/inst
1819system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61937 # Table walker requests started/completed, data/inst
1820system.cpu1.itb.walker.walkRequestOrigin::total 147181 # Table walker requests started/completed, data/inst
1821system.cpu1.itb.inst_hits 196146030 # ITB inst hits
1822system.cpu1.itb.inst_misses 85244 # ITB inst misses
1823system.cpu1.itb.read_hits 0 # DTB read hits
1824system.cpu1.itb.read_misses 0 # DTB read misses
1825system.cpu1.itb.write_hits 0 # DTB write hits
1826system.cpu1.itb.write_misses 0 # DTB write misses
1827system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1828system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1829system.cpu1.itb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID
1830system.cpu1.itb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID
1831system.cpu1.itb.flush_entries 26780 # Number of entries that have been flushed from TLB
1832system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1833system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1834system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1835system.cpu1.itb.perms_faults 213163 # Number of TLB faults due to permissions restrictions
1836system.cpu1.itb.read_accesses 0 # DTB read accesses
1837system.cpu1.itb.write_accesses 0 # DTB write accesses
1838system.cpu1.itb.inst_accesses 196231274 # ITB inst accesses
1839system.cpu1.itb.hits 196146030 # DTB hits
1840system.cpu1.itb.misses 85244 # DTB misses
1841system.cpu1.itb.accesses 196231274 # DTB accesses
1842system.cpu1.numCycles 664388878 # number of cpu cycles simulated
1843system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1844system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1845system.cpu1.fetch.icacheStallCycles 79880322 # Number of cycles fetch is stalled on an Icache miss
1846system.cpu1.fetch.Insts 552169788 # Number of instructions fetch has processed
1847system.cpu1.fetch.Branches 124370032 # Number of branches that fetch encountered
1848system.cpu1.fetch.predictedBranches 73592810 # Number of branches that fetch has predicted taken
1849system.cpu1.fetch.Cycles 551328487 # Number of cycles fetch has run and was not squashing or blocked
1850system.cpu1.fetch.SquashCycles 13340182 # Number of cycles fetch has spent squashing
1851system.cpu1.fetch.TlbCycles 1707326 # Number of cycles fetch has spent waiting for tlb
1852system.cpu1.fetch.MiscStallCycles 246511 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1853system.cpu1.fetch.PendingTrapStallCycles 6080767 # Number of stall cycles due to pending traps
1854system.cpu1.fetch.PendingQuiesceStallCycles 727313 # Number of stall cycles due to pending quiesce instructions
1855system.cpu1.fetch.IcacheWaitRetryStallCycles 602439 # Number of stall cycles due to full MSHR
1856system.cpu1.fetch.CacheLines 195911596 # Number of cache lines fetched
1857system.cpu1.fetch.IcacheSquashes 1586691 # Number of outstanding Icache misses that were squashed
1858system.cpu1.fetch.ItlbSquashes 28723 # Number of outstanding ITLB misses that were squashed
1859system.cpu1.fetch.rateDist::samples 647243256 # Number of instructions fetched each cycle (Total)
1860system.cpu1.fetch.rateDist::mean 1.003235 # Number of instructions fetched each cycle (Total)
1861system.cpu1.fetch.rateDist::stdev 1.226187 # Number of instructions fetched each cycle (Total)
1862system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1863system.cpu1.fetch.rateDist::0 336573756 52.00% 52.00% # Number of instructions fetched each cycle (Total)
1864system.cpu1.fetch.rateDist::1 120960986 18.69% 70.69% # Number of instructions fetched each cycle (Total)
1865system.cpu1.fetch.rateDist::2 40749741 6.30% 76.99% # Number of instructions fetched each cycle (Total)
1866system.cpu1.fetch.rateDist::3 148958773 23.01% 100.00% # Number of instructions fetched each cycle (Total)
1867system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1868system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1869system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
1870system.cpu1.fetch.rateDist::total 647243256 # Number of instructions fetched each cycle (Total)
1871system.cpu1.fetch.branchRate 0.187195 # Number of branch fetches per cycle
1872system.cpu1.fetch.rate 0.831094 # Number of inst fetches per cycle
1873system.cpu1.decode.IdleCycles 96356177 # Number of cycles decode is idle
1874system.cpu1.decode.BlockedCycles 306396299 # Number of cycles decode is blocked
1875system.cpu1.decode.RunCycles 204571849 # Number of cycles decode is running
1876system.cpu1.decode.UnblockCycles 35206357 # Number of cycles decode is unblocking
1877system.cpu1.decode.SquashCycles 4712574 # Number of cycles decode is squashing
1878system.cpu1.decode.BranchResolved 17589142 # Number of times decode resolved a branch
1879system.cpu1.decode.BranchMispred 1996203 # Number of times decode detected a branch misprediction
1880system.cpu1.decode.DecodedInsts 573391383 # Number of instructions handled by decode
1881system.cpu1.decode.SquashedInsts 21361954 # Number of squashed instructions handled by decode
1882system.cpu1.rename.SquashCycles 4712574 # Number of cycles rename is squashing
1883system.cpu1.rename.IdleCycles 129172911 # Number of cycles rename is idle
1884system.cpu1.rename.BlockCycles 40460241 # Number of cycles rename is blocking
1885system.cpu1.rename.serializeStallCycles 212107385 # count of cycles rename stalled for serializing inst
1886system.cpu1.rename.RunCycles 206565063 # Number of cycles rename is running
1887system.cpu1.rename.UnblockCycles 54225082 # Number of cycles rename is unblocking
1888system.cpu1.rename.RenamedInsts 557977037 # Number of instructions processed by rename
1889system.cpu1.rename.SquashedInsts 5352379 # Number of squashed instructions processed by rename
1890system.cpu1.rename.ROBFullEvents 8193976 # Number of times rename has blocked due to ROB full
1891system.cpu1.rename.IQFullEvents 222351 # Number of times rename has blocked due to IQ full
1892system.cpu1.rename.LQFullEvents 303036 # Number of times rename has blocked due to LQ full
1893system.cpu1.rename.SQFullEvents 21276416 # Number of times rename has blocked due to SQ full
1894system.cpu1.rename.FullRegisterEvents 13923 # Number of times there has been no free registers
1895system.cpu1.rename.RenamedOperands 530659712 # Number of destination operands rename has renamed
1896system.cpu1.rename.RenameLookups 862978619 # Number of register rename lookups that rename has made
1897system.cpu1.rename.int_rename_lookups 659902858 # Number of integer rename lookups
1898system.cpu1.rename.fp_rename_lookups 766208 # Number of floating rename lookups
1899system.cpu1.rename.CommittedMaps 478267677 # Number of HB maps that are committed
1900system.cpu1.rename.UndoneMaps 52392029 # Number of HB maps that are undone due to squashing
1901system.cpu1.rename.serializingInsts 15246817 # count of serializing insts renamed
1902system.cpu1.rename.tempSerializingInsts 13453544 # count of temporary serializing insts renamed
1903system.cpu1.rename.skidInsts 71065053 # count of insts added to the skid buffer
1904system.cpu1.memDep0.insertedLoads 91863812 # Number of loads inserted to the mem dependence unit.
1905system.cpu1.memDep0.insertedStores 78915989 # Number of stores inserted to the mem dependence unit.
1906system.cpu1.memDep0.conflictingLoads 8629555 # Number of conflicting loads.
1907system.cpu1.memDep0.conflictingStores 7664780 # Number of conflicting stores.
1908system.cpu1.iq.iqInstsAdded 536633802 # Number of instructions added to the IQ (excludes non-spec)
1909system.cpu1.iq.iqNonSpecInstsAdded 15513444 # Number of non-speculative instructions added to the IQ
1910system.cpu1.iq.iqInstsIssued 541699362 # Number of instructions issued
1911system.cpu1.iq.iqSquashedInstsIssued 2485495 # Number of squashed instructions issued
1912system.cpu1.iq.iqSquashedInstsExamined 46695905 # Number of squashed instructions iterated over during squash; mainly for profiling
1913system.cpu1.iq.iqSquashedOperandsExamined 31776612 # Number of squashed operands that are examined and possibly removed from graph
1914system.cpu1.iq.iqSquashedNonSpecRemoved 271399 # Number of squashed non-spec instructions that were removed
1915system.cpu1.iq.issued_per_cycle::samples 647243256 # Number of insts issued each cycle
1916system.cpu1.iq.issued_per_cycle::mean 0.836933 # Number of insts issued each cycle
1917system.cpu1.iq.issued_per_cycle::stdev 1.069144 # Number of insts issued each cycle
1918system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1919system.cpu1.iq.issued_per_cycle::0 349912497 54.06% 54.06% # Number of insts issued each cycle
1920system.cpu1.iq.issued_per_cycle::1 127097301 19.64% 73.70% # Number of insts issued each cycle
1921system.cpu1.iq.issued_per_cycle::2 103346931 15.97% 89.67% # Number of insts issued each cycle
1922system.cpu1.iq.issued_per_cycle::3 59640858 9.21% 98.88% # Number of insts issued each cycle
1923system.cpu1.iq.issued_per_cycle::4 7242720 1.12% 100.00% # Number of insts issued each cycle
1924system.cpu1.iq.issued_per_cycle::5 2949 0.00% 100.00% # Number of insts issued each cycle
1925system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
1926system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
1927system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
1928system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1929system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1930system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
1931system.cpu1.iq.issued_per_cycle::total 647243256 # Number of insts issued each cycle
1932system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1933system.cpu1.iq.fu_full::IntAlu 54464030 43.99% 43.99% # attempts to use FU when none available
1934system.cpu1.iq.fu_full::IntMult 55578 0.04% 44.03% # attempts to use FU when none available
1935system.cpu1.iq.fu_full::IntDiv 15828 0.01% 44.05% # attempts to use FU when none available
1936system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.05% # attempts to use FU when none available
1937system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.05% # attempts to use FU when none available
1938system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.05% # attempts to use FU when none available
1939system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.05% # attempts to use FU when none available
1940system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.05% # attempts to use FU when none available
1941system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.05% # attempts to use FU when none available
1942system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.05% # attempts to use FU when none available
1943system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.05% # attempts to use FU when none available
1944system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.05% # attempts to use FU when none available
1945system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.05% # attempts to use FU when none available
1946system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.05% # attempts to use FU when none available
1947system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.05% # attempts to use FU when none available
1948system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.05% # attempts to use FU when none available
1949system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.05% # attempts to use FU when none available
1950system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.05% # attempts to use FU when none available
1951system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.05% # attempts to use FU when none available
1952system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.05% # attempts to use FU when none available
1953system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.05% # attempts to use FU when none available
1954system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.05% # attempts to use FU when none available
1955system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.05% # attempts to use FU when none available
1956system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.05% # attempts to use FU when none available
1957system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.05% # attempts to use FU when none available
1958system.cpu1.iq.fu_full::SimdFloatMisc 9 0.00% 44.05% # attempts to use FU when none available
1959system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.05% # attempts to use FU when none available
1960system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.05% # attempts to use FU when none available
1961system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.05% # attempts to use FU when none available
1962system.cpu1.iq.fu_full::MemRead 33234382 26.84% 70.89% # attempts to use FU when none available
1963system.cpu1.iq.fu_full::MemWrite 36043585 29.11% 100.00% # attempts to use FU when none available
1964system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1965system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1966system.cpu1.iq.FU_type_0::No_OpClass 12 0.00% 0.00% # Type of FU issued
1967system.cpu1.iq.FU_type_0::IntAlu 369233279 68.16% 68.16% # Type of FU issued
1968system.cpu1.iq.FU_type_0::IntMult 1193564 0.22% 68.38% # Type of FU issued
1969system.cpu1.iq.FU_type_0::IntDiv 69127 0.01% 68.40% # Type of FU issued
1970system.cpu1.iq.FU_type_0::FloatAdd 2 0.00% 68.40% # Type of FU issued
1971system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.40% # Type of FU issued
1972system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.40% # Type of FU issued
1973system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.40% # Type of FU issued
1974system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.40% # Type of FU issued
1975system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued
1976system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued
1977system.cpu1.iq.FU_type_0::SimdAddAcc 1 0.00% 68.40% # Type of FU issued
1978system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.40% # Type of FU issued
1979system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.40% # Type of FU issued
1980system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.40% # Type of FU issued
1981system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.40% # Type of FU issued
1982system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.40% # Type of FU issued
1983system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.40% # Type of FU issued
1984system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.40% # Type of FU issued
1985system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.40% # Type of FU issued
1986system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.40% # Type of FU issued
1987system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.40% # Type of FU issued
1988system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.40% # Type of FU issued
1989system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.40% # Type of FU issued
1990system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.40% # Type of FU issued
1991system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.40% # Type of FU issued
1992system.cpu1.iq.FU_type_0::SimdFloatMisc 46847 0.01% 68.40% # Type of FU issued
1993system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.40% # Type of FU issued
1994system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.40% # Type of FU issued
1995system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.40% # Type of FU issued
1996system.cpu1.iq.FU_type_0::MemRead 94164053 17.38% 85.79% # Type of FU issued
1997system.cpu1.iq.FU_type_0::MemWrite 76992429 14.21% 100.00% # Type of FU issued
1998system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1999system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2000system.cpu1.iq.FU_type_0::total 541699362 # Type of FU issued
2001system.cpu1.iq.rate 0.815335 # Inst issue rate
2002system.cpu1.iq.fu_busy_cnt 123813412 # FU busy when requested
2003system.cpu1.iq.fu_busy_rate 0.228565 # FU busy rate (busy events/executed inst)
2004system.cpu1.iq.int_inst_queue_reads 1855831634 # Number of integer instruction queue reads
2005system.cpu1.iq.int_inst_queue_writes 598546046 # Number of integer instruction queue writes
2006system.cpu1.iq.int_inst_queue_wakeup_accesses 526634223 # Number of integer instruction queue wakeup accesses
2007system.cpu1.iq.fp_inst_queue_reads 1109251 # Number of floating instruction queue reads
2008system.cpu1.iq.fp_inst_queue_writes 439129 # Number of floating instruction queue writes
2009system.cpu1.iq.fp_inst_queue_wakeup_accesses 408402 # Number of floating instruction queue wakeup accesses
2010system.cpu1.iq.int_alu_accesses 664822270 # Number of integer alu accesses
2011system.cpu1.iq.fp_alu_accesses 690492 # Number of floating point alu accesses
2012system.cpu1.iew.lsq.thread0.forwLoads 2431611 # Number of loads that had data forwarded from stores
2013system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2014system.cpu1.iew.lsq.thread0.squashedLoads 11396985 # Number of loads squashed
2015system.cpu1.iew.lsq.thread0.ignoredResponses 16347 # Number of memory responses ignored because the instruction is squashed
2016system.cpu1.iew.lsq.thread0.memOrderViolation 143339 # Number of memory ordering violations
2017system.cpu1.iew.lsq.thread0.squashedStores 5491640 # Number of stores squashed
2018system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2019system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2020system.cpu1.iew.lsq.thread0.rescheduledLoads 2526857 # Number of loads that were rescheduled
2021system.cpu1.iew.lsq.thread0.cacheBlocked 3486247 # Number of times an access to memory failed due to the cache being blocked
2022system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2023system.cpu1.iew.iewSquashCycles 4712574 # Number of cycles IEW is squashing
2024system.cpu1.iew.iewBlockCycles 5829545 # Number of cycles IEW is blocking
2025system.cpu1.iew.iewUnblockCycles 1427417 # Number of cycles IEW is unblocking
2026system.cpu1.iew.iewDispatchedInsts 552265728 # Number of instructions dispatched to IQ
2027system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2028system.cpu1.iew.iewDispLoadInsts 91863812 # Number of dispatched load instructions
2029system.cpu1.iew.iewDispStoreInsts 78915989 # Number of dispatched store instructions
2030system.cpu1.iew.iewDispNonSpecInsts 13236985 # Number of dispatched non-speculative instructions
2031system.cpu1.iew.iewIQFullEvents 56254 # Number of times the IQ has become full, causing a stall
2032system.cpu1.iew.iewLSQFullEvents 1314129 # Number of times the LSQ has become full, causing a stall
2033system.cpu1.iew.memOrderViolationEvents 143339 # Number of memory order violations
2034system.cpu1.iew.predictedTakenIncorrect 1858186 # Number of branches that were predicted taken incorrectly
2035system.cpu1.iew.predictedNotTakenIncorrect 2653609 # Number of branches that were predicted not taken incorrectly
2036system.cpu1.iew.branchMispredicts 4511795 # Number of branch mispredicts detected at execute
2037system.cpu1.iew.iewExecutedInsts 534690067 # Number of executed instructions
2038system.cpu1.iew.iewExecLoadInsts 91388435 # Number of load instructions executed
2039system.cpu1.iew.iewExecSquashedInsts 6481283 # Number of squashed instructions skipped in execute
2040system.cpu1.iew.exec_swp 0 # number of swp insts executed
2041system.cpu1.iew.exec_nop 118482 # number of nop insts executed
2042system.cpu1.iew.exec_refs 167194328 # number of memory reference insts executed
2043system.cpu1.iew.exec_branches 100087893 # Number of branches executed
2044system.cpu1.iew.exec_stores 75805893 # Number of stores executed
2045system.cpu1.iew.exec_rate 0.804785 # Inst execution rate
2046system.cpu1.iew.wb_sent 527704335 # cumulative count of insts sent to commit
2047system.cpu1.iew.wb_count 527042625 # cumulative count of insts written-back
2048system.cpu1.iew.wb_producers 254576573 # num instructions producing a value
2049system.cpu1.iew.wb_consumers 416898701 # num instructions consuming a value
2050system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
2051system.cpu1.iew.wb_rate 0.793274 # insts written-back per cycle
2052system.cpu1.iew.wb_fanout 0.610644 # average fanout of values written-back
2053system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
2054system.cpu1.commit.commitSquashedInsts 43642021 # The number of squashed insts skipped by commit
2055system.cpu1.commit.commitNonSpecStalls 15242045 # The number of times commit has been forced to stall to communicate backwards
2056system.cpu1.commit.branchMispredicts 4231486 # The number of times a branch was mispredicted
2057system.cpu1.commit.committed_per_cycle::samples 638973832 # Number of insts commited each cycle
2058system.cpu1.commit.committed_per_cycle::mean 0.786200 # Number of insts commited each cycle
2059system.cpu1.commit.committed_per_cycle::stdev 1.579868 # Number of insts commited each cycle
2060system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2061system.cpu1.commit.committed_per_cycle::0 417556945 65.35% 65.35% # Number of insts commited each cycle
2062system.cpu1.commit.committed_per_cycle::1 116379063 18.21% 83.56% # Number of insts commited each cycle
2063system.cpu1.commit.committed_per_cycle::2 48152991 7.54% 91.10% # Number of insts commited each cycle
2064system.cpu1.commit.committed_per_cycle::3 16068254 2.51% 93.61% # Number of insts commited each cycle
2065system.cpu1.commit.committed_per_cycle::4 11811974 1.85% 95.46% # Number of insts commited each cycle
2066system.cpu1.commit.committed_per_cycle::5 7886914 1.23% 96.70% # Number of insts commited each cycle
2067system.cpu1.commit.committed_per_cycle::6 5403679 0.85% 97.54% # Number of insts commited each cycle
2068system.cpu1.commit.committed_per_cycle::7 3345009 0.52% 98.06% # Number of insts commited each cycle
2069system.cpu1.commit.committed_per_cycle::8 12369003 1.94% 100.00% # Number of insts commited each cycle
2070system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2071system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2072system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2073system.cpu1.commit.committed_per_cycle::total 638973832 # Number of insts commited each cycle
2074system.cpu1.commit.committedInsts 426124677 # Number of instructions committed
2075system.cpu1.commit.committedOps 502361434 # Number of ops (including micro ops) committed
2076system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2077system.cpu1.commit.refs 153891175 # Number of memory references committed
2078system.cpu1.commit.loads 80466826 # Number of loads committed
2079system.cpu1.commit.membars 3635433 # Number of memory barriers committed
2080system.cpu1.commit.branches 94895008 # Number of branches committed
2081system.cpu1.commit.fp_insts 399904 # Number of committed floating point instructions.
2082system.cpu1.commit.int_insts 461321486 # Number of committed integer instructions.
2083system.cpu1.commit.function_calls 12405087 # Number of function calls committed.
2084system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2085system.cpu1.commit.op_class_0::IntAlu 347396188 69.15% 69.15% # Class of committed instruction
2086system.cpu1.commit.op_class_0::IntMult 977319 0.19% 69.35% # Class of committed instruction
2087system.cpu1.commit.op_class_0::IntDiv 55389 0.01% 69.36% # Class of committed instruction
2088system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.36% # Class of committed instruction
2089system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.36% # Class of committed instruction
2090system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.36% # Class of committed instruction
2091system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.36% # Class of committed instruction
2092system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.36% # Class of committed instruction
2093system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.36% # Class of committed instruction
2094system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.36% # Class of committed instruction
2095system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.36% # Class of committed instruction
2096system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.36% # Class of committed instruction
2097system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.36% # Class of committed instruction
2098system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.36% # Class of committed instruction
2099system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.36% # Class of committed instruction
2100system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.36% # Class of committed instruction
2101system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.36% # Class of committed instruction
2102system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.36% # Class of committed instruction
2103system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.36% # Class of committed instruction
2104system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.36% # Class of committed instruction
2105system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.36% # Class of committed instruction
2106system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.36% # Class of committed instruction
2107system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.36% # Class of committed instruction
2108system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.36% # Class of committed instruction
2109system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.36% # Class of committed instruction
2110system.cpu1.commit.op_class_0::SimdFloatMisc 41321 0.01% 69.37% # Class of committed instruction
2111system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.37% # Class of committed instruction
2112system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.37% # Class of committed instruction
2113system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.37% # Class of committed instruction
2114system.cpu1.commit.op_class_0::MemRead 80466826 16.02% 85.38% # Class of committed instruction
2115system.cpu1.commit.op_class_0::MemWrite 73424349 14.62% 100.00% # Class of committed instruction
2116system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2117system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2118system.cpu1.commit.op_class_0::total 502361434 # Class of committed instruction
2119system.cpu1.commit.bw_lim_events 12369003 # number cycles where commit BW limit reached
2120system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
2121system.cpu1.rob.rob_reads 1168820475 # The number of ROB reads
2122system.cpu1.rob.rob_writes 1100237743 # The number of ROB writes
2123system.cpu1.timesIdled 913492 # Number of times that the entire CPU went into an idle state and unscheduled itself
2124system.cpu1.idleCycles 17145622 # Total number of cycles that the CPU has spent unscheduled due to idling
2125system.cpu1.quiesceCycles 94026381638 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2126system.cpu1.committedInsts 426124677 # Number of Instructions Simulated
2127system.cpu1.committedOps 502361434 # Number of Ops (including micro ops) Simulated
2128system.cpu1.cpi 1.559142 # CPI: Cycles Per Instruction
2129system.cpu1.cpi_total 1.559142 # CPI: Total CPI of All Threads
2130system.cpu1.ipc 0.641378 # IPC: Instructions Per Cycle
2131system.cpu1.ipc_total 0.641378 # IPC: Total IPC of All Threads
2132system.cpu1.int_regfile_reads 632226075 # number of integer regfile reads
2133system.cpu1.int_regfile_writes 374528717 # number of integer regfile writes
2134system.cpu1.fp_regfile_reads 661926 # number of floating regfile reads
2135system.cpu1.fp_regfile_writes 331836 # number of floating regfile writes
2136system.cpu1.cc_regfile_reads 114587184 # number of cc regfile reads
2137system.cpu1.cc_regfile_writes 115385602 # number of cc regfile writes
2138system.cpu1.misc_regfile_reads 2619636946 # number of misc regfile reads
2139system.cpu1.misc_regfile_writes 15333141 # number of misc regfile writes
2140system.cpu1.dcache.tags.replacements 5236220 # number of replacements
2141system.cpu1.dcache.tags.tagsinuse 457.332610 # Cycle average of tags in use
2142system.cpu1.dcache.tags.total_refs 143091306 # Total number of references to valid blocks.
2143system.cpu1.dcache.tags.sampled_refs 5236730 # Sample count of references to valid blocks.
2144system.cpu1.dcache.tags.avg_refs 27.324553 # Average number of references to valid blocks.
2145system.cpu1.dcache.tags.warmup_cycle 8478701081000 # Cycle when the warmup percentage was hit.
2146system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.332610 # Average occupied blocks per requestor
2147system.cpu1.dcache.tags.occ_percent::cpu1.data 0.893228 # Average percentage of cache occupancy
2148system.cpu1.dcache.tags.occ_percent::total 0.893228 # Average percentage of cache occupancy
2149system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
2150system.cpu1.dcache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id
2151system.cpu1.dcache.tags.age_task_id_blocks_1024::1 334 # Occupied blocks per task id
2152system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
2153system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
2154system.cpu1.dcache.tags.tag_accesses 319394188 # Number of tag accesses
2155system.cpu1.dcache.tags.data_accesses 319394188 # Number of data accesses
2156system.cpu1.dcache.ReadReq_hits::cpu1.data 74655263 # number of ReadReq hits
2157system.cpu1.dcache.ReadReq_hits::total 74655263 # number of ReadReq hits
2158system.cpu1.dcache.WriteReq_hits::cpu1.data 64023189 # number of WriteReq hits
2159system.cpu1.dcache.WriteReq_hits::total 64023189 # number of WriteReq hits
2160system.cpu1.dcache.SoftPFReq_hits::cpu1.data 163779 # number of SoftPFReq hits
2161system.cpu1.dcache.SoftPFReq_hits::total 163779 # number of SoftPFReq hits
2162system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 39797 # number of WriteInvalidateReq hits
2163system.cpu1.dcache.WriteInvalidateReq_hits::total 39797 # number of WriteInvalidateReq hits
2164system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1738928 # number of LoadLockedReq hits
2165system.cpu1.dcache.LoadLockedReq_hits::total 1738928 # number of LoadLockedReq hits
2166system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1751406 # number of StoreCondReq hits
2167system.cpu1.dcache.StoreCondReq_hits::total 1751406 # number of StoreCondReq hits
2168system.cpu1.dcache.demand_hits::cpu1.data 138678452 # number of demand (read+write) hits
2169system.cpu1.dcache.demand_hits::total 138678452 # number of demand (read+write) hits
2170system.cpu1.dcache.overall_hits::cpu1.data 138842231 # number of overall hits
2171system.cpu1.dcache.overall_hits::total 138842231 # number of overall hits
2172system.cpu1.dcache.ReadReq_misses::cpu1.data 6126939 # number of ReadReq misses
2173system.cpu1.dcache.ReadReq_misses::total 6126939 # number of ReadReq misses
2174system.cpu1.dcache.WriteReq_misses::cpu1.data 6982821 # number of WriteReq misses
2175system.cpu1.dcache.WriteReq_misses::total 6982821 # number of WriteReq misses
2176system.cpu1.dcache.SoftPFReq_misses::cpu1.data 659533 # number of SoftPFReq misses
2177system.cpu1.dcache.SoftPFReq_misses::total 659533 # number of SoftPFReq misses
2178system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 425377 # number of WriteInvalidateReq misses
2179system.cpu1.dcache.WriteInvalidateReq_misses::total 425377 # number of WriteInvalidateReq misses
2180system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 260578 # number of LoadLockedReq misses
2181system.cpu1.dcache.LoadLockedReq_misses::total 260578 # number of LoadLockedReq misses
2182system.cpu1.dcache.StoreCondReq_misses::cpu1.data 204152 # number of StoreCondReq misses
2183system.cpu1.dcache.StoreCondReq_misses::total 204152 # number of StoreCondReq misses
2184system.cpu1.dcache.demand_misses::cpu1.data 13109760 # number of demand (read+write) misses
2185system.cpu1.dcache.demand_misses::total 13109760 # number of demand (read+write) misses
2186system.cpu1.dcache.overall_misses::cpu1.data 13769293 # number of overall misses
2187system.cpu1.dcache.overall_misses::total 13769293 # number of overall misses
2188system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 92549514245 # number of ReadReq miss cycles
2189system.cpu1.dcache.ReadReq_miss_latency::total 92549514245 # number of ReadReq miss cycles
2190system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 116311286360 # number of WriteReq miss cycles
2191system.cpu1.dcache.WriteReq_miss_latency::total 116311286360 # number of WriteReq miss cycles
2192system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11708163921 # number of WriteInvalidateReq miss cycles
2193system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11708163921 # number of WriteInvalidateReq miss cycles
2194system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3758503444 # number of LoadLockedReq miss cycles
2195system.cpu1.dcache.LoadLockedReq_miss_latency::total 3758503444 # number of LoadLockedReq miss cycles
2196system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4320848660 # number of StoreCondReq miss cycles
2197system.cpu1.dcache.StoreCondReq_miss_latency::total 4320848660 # number of StoreCondReq miss cycles
2198system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3489000 # number of StoreCondFailReq miss cycles
2199system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3489000 # number of StoreCondFailReq miss cycles
2200system.cpu1.dcache.demand_miss_latency::cpu1.data 208860800605 # number of demand (read+write) miss cycles
2201system.cpu1.dcache.demand_miss_latency::total 208860800605 # number of demand (read+write) miss cycles
2202system.cpu1.dcache.overall_miss_latency::cpu1.data 208860800605 # number of overall miss cycles
2203system.cpu1.dcache.overall_miss_latency::total 208860800605 # number of overall miss cycles
2204system.cpu1.dcache.ReadReq_accesses::cpu1.data 80782202 # number of ReadReq accesses(hits+misses)
2205system.cpu1.dcache.ReadReq_accesses::total 80782202 # number of ReadReq accesses(hits+misses)
2206system.cpu1.dcache.WriteReq_accesses::cpu1.data 71006010 # number of WriteReq accesses(hits+misses)
2207system.cpu1.dcache.WriteReq_accesses::total 71006010 # number of WriteReq accesses(hits+misses)
2208system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 823312 # number of SoftPFReq accesses(hits+misses)
2209system.cpu1.dcache.SoftPFReq_accesses::total 823312 # number of SoftPFReq accesses(hits+misses)
2210system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 465174 # number of WriteInvalidateReq accesses(hits+misses)
2211system.cpu1.dcache.WriteInvalidateReq_accesses::total 465174 # number of WriteInvalidateReq accesses(hits+misses)
2212system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1999506 # number of LoadLockedReq accesses(hits+misses)
2213system.cpu1.dcache.LoadLockedReq_accesses::total 1999506 # number of LoadLockedReq accesses(hits+misses)
2214system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1955558 # number of StoreCondReq accesses(hits+misses)
2215system.cpu1.dcache.StoreCondReq_accesses::total 1955558 # number of StoreCondReq accesses(hits+misses)
2216system.cpu1.dcache.demand_accesses::cpu1.data 151788212 # number of demand (read+write) accesses
2217system.cpu1.dcache.demand_accesses::total 151788212 # number of demand (read+write) accesses
2218system.cpu1.dcache.overall_accesses::cpu1.data 152611524 # number of overall (read+write) accesses
2219system.cpu1.dcache.overall_accesses::total 152611524 # number of overall (read+write) accesses
2220system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.075845 # miss rate for ReadReq accesses
2221system.cpu1.dcache.ReadReq_miss_rate::total 0.075845 # miss rate for ReadReq accesses
2222system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.098341 # miss rate for WriteReq accesses
2223system.cpu1.dcache.WriteReq_miss_rate::total 0.098341 # miss rate for WriteReq accesses
2224system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.801073 # miss rate for SoftPFReq accesses
2225system.cpu1.dcache.SoftPFReq_miss_rate::total 0.801073 # miss rate for SoftPFReq accesses
2226system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.914447 # miss rate for WriteInvalidateReq accesses
2227system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.914447 # miss rate for WriteInvalidateReq accesses
2228system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.130321 # miss rate for LoadLockedReq accesses
2229system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.130321 # miss rate for LoadLockedReq accesses
2230system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104396 # miss rate for StoreCondReq accesses
2231system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104396 # miss rate for StoreCondReq accesses
2232system.cpu1.dcache.demand_miss_rate::cpu1.data 0.086369 # miss rate for demand accesses
2233system.cpu1.dcache.demand_miss_rate::total 0.086369 # miss rate for demand accesses
2234system.cpu1.dcache.overall_miss_rate::cpu1.data 0.090224 # miss rate for overall accesses
2235system.cpu1.dcache.overall_miss_rate::total 0.090224 # miss rate for overall accesses
2236system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15105.342855 # average ReadReq miss latency
2237system.cpu1.dcache.ReadReq_avg_miss_latency::total 15105.342855 # average ReadReq miss latency
2238system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16656.776160 # average WriteReq miss latency
2239system.cpu1.dcache.WriteReq_avg_miss_latency::total 16656.776160 # average WriteReq miss latency
2240system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27524.205401 # average WriteInvalidateReq miss latency
2241system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27524.205401 # average WriteInvalidateReq miss latency
2242system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14423.717444 # average LoadLockedReq miss latency
2243system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14423.717444 # average LoadLockedReq miss latency
2244system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21164.860790 # average StoreCondReq miss latency
2245system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21164.860790 # average StoreCondReq miss latency
2246system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
2247system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2248system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15931.702839 # average overall miss latency
2249system.cpu1.dcache.demand_avg_miss_latency::total 15931.702839 # average overall miss latency
2250system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15168.592941 # average overall miss latency
2251system.cpu1.dcache.overall_avg_miss_latency::total 15168.592941 # average overall miss latency
2252system.cpu1.dcache.blocked_cycles::no_mshrs 2855420 # number of cycles access was blocked
2253system.cpu1.dcache.blocked_cycles::no_targets 17544431 # number of cycles access was blocked
2254system.cpu1.dcache.blocked::no_mshrs 337066 # number of cycles access was blocked
2255system.cpu1.dcache.blocked::no_targets 700468 # number of cycles access was blocked
2256system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.471397 # average number of cycles each access was blocked
2257system.cpu1.dcache.avg_blocked_cycles::no_targets 25.046727 # average number of cycles each access was blocked
2258system.cpu1.dcache.fast_writes 0 # number of fast writes performed
2259system.cpu1.dcache.cache_copies 0 # number of cache copies performed
2260system.cpu1.dcache.writebacks::writebacks 3392584 # number of writebacks
2261system.cpu1.dcache.writebacks::total 3392584 # number of writebacks
2262system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3127909 # number of ReadReq MSHR hits
2263system.cpu1.dcache.ReadReq_mshr_hits::total 3127909 # number of ReadReq MSHR hits
2264system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5647115 # number of WriteReq MSHR hits
2265system.cpu1.dcache.WriteReq_mshr_hits::total 5647115 # number of WriteReq MSHR hits
2266system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3296 # number of WriteInvalidateReq MSHR hits
2267system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3296 # number of WriteInvalidateReq MSHR hits
2268system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 132105 # number of LoadLockedReq MSHR hits
2269system.cpu1.dcache.LoadLockedReq_mshr_hits::total 132105 # number of LoadLockedReq MSHR hits
2270system.cpu1.dcache.demand_mshr_hits::cpu1.data 8775024 # number of demand (read+write) MSHR hits
2271system.cpu1.dcache.demand_mshr_hits::total 8775024 # number of demand (read+write) MSHR hits
2272system.cpu1.dcache.overall_mshr_hits::cpu1.data 8775024 # number of overall MSHR hits
2273system.cpu1.dcache.overall_mshr_hits::total 8775024 # number of overall MSHR hits
2274system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2999030 # number of ReadReq MSHR misses
2275system.cpu1.dcache.ReadReq_mshr_misses::total 2999030 # number of ReadReq MSHR misses
2276system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1335706 # number of WriteReq MSHR misses
2277system.cpu1.dcache.WriteReq_mshr_misses::total 1335706 # number of WriteReq MSHR misses
2278system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 659449 # number of SoftPFReq MSHR misses
2279system.cpu1.dcache.SoftPFReq_mshr_misses::total 659449 # number of SoftPFReq MSHR misses
2280system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 422081 # number of WriteInvalidateReq MSHR misses
2281system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 422081 # number of WriteInvalidateReq MSHR misses
2282system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 128473 # number of LoadLockedReq MSHR misses
2283system.cpu1.dcache.LoadLockedReq_mshr_misses::total 128473 # number of LoadLockedReq MSHR misses
2284system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 204145 # number of StoreCondReq MSHR misses
2285system.cpu1.dcache.StoreCondReq_mshr_misses::total 204145 # number of StoreCondReq MSHR misses
2286system.cpu1.dcache.demand_mshr_misses::cpu1.data 4334736 # number of demand (read+write) MSHR misses
2287system.cpu1.dcache.demand_mshr_misses::total 4334736 # number of demand (read+write) MSHR misses
2288system.cpu1.dcache.overall_mshr_misses::cpu1.data 4994185 # number of overall MSHR misses
2289system.cpu1.dcache.overall_mshr_misses::total 4994185 # number of overall MSHR misses
2290system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38225367292 # number of ReadReq MSHR miss cycles
2291system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38225367292 # number of ReadReq MSHR miss cycles
2292system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21845579142 # number of WriteReq MSHR miss cycles
2293system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21845579142 # number of WriteReq MSHR miss cycles
2294system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15240654080 # number of SoftPFReq MSHR miss cycles
2295system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15240654080 # number of SoftPFReq MSHR miss cycles
2296system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 10753431338 # number of WriteInvalidateReq MSHR miss cycles
2297system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 10753431338 # number of WriteInvalidateReq MSHR miss cycles
2298system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1629520255 # number of LoadLockedReq MSHR miss cycles
2299system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1629520255 # number of LoadLockedReq MSHR miss cycles
2300system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3904363340 # number of StoreCondReq MSHR miss cycles
2301system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3904363340 # number of StoreCondReq MSHR miss cycles
2302system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3325000 # number of StoreCondFailReq MSHR miss cycles
2303system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3325000 # number of StoreCondFailReq MSHR miss cycles
2304system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 60070946434 # number of demand (read+write) MSHR miss cycles
2305system.cpu1.dcache.demand_mshr_miss_latency::total 60070946434 # number of demand (read+write) MSHR miss cycles
2306system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 75311600514 # number of overall MSHR miss cycles
2307system.cpu1.dcache.overall_mshr_miss_latency::total 75311600514 # number of overall MSHR miss cycles
2308system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 796916503 # number of ReadReq MSHR uncacheable cycles
2309system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 796916503 # number of ReadReq MSHR uncacheable cycles
2310system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 897774501 # number of WriteReq MSHR uncacheable cycles
2311system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 897774501 # number of WriteReq MSHR uncacheable cycles
2312system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1694691004 # number of overall MSHR uncacheable cycles
2313system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1694691004 # number of overall MSHR uncacheable cycles
2314system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037125 # mshr miss rate for ReadReq accesses
2315system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037125 # mshr miss rate for ReadReq accesses
2316system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018811 # mshr miss rate for WriteReq accesses
2317system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018811 # mshr miss rate for WriteReq accesses
2318system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.800971 # mshr miss rate for SoftPFReq accesses
2319system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.800971 # mshr miss rate for SoftPFReq accesses
2320system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.907362 # mshr miss rate for WriteInvalidateReq accesses
2321system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.907362 # mshr miss rate for WriteInvalidateReq accesses
2322system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064252 # mshr miss rate for LoadLockedReq accesses
2323system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064252 # mshr miss rate for LoadLockedReq accesses
2324system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104392 # mshr miss rate for StoreCondReq accesses
2325system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104392 # mshr miss rate for StoreCondReq accesses
2326system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028558 # mshr miss rate for demand accesses
2327system.cpu1.dcache.demand_mshr_miss_rate::total 0.028558 # mshr miss rate for demand accesses
2328system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032725 # mshr miss rate for overall accesses
2329system.cpu1.dcache.overall_mshr_miss_rate::total 0.032725 # mshr miss rate for overall accesses
2330system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12745.910275 # average ReadReq mshr miss latency
2331system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12745.910275 # average ReadReq mshr miss latency
2332system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16355.080491 # average WriteReq mshr miss latency
2333system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16355.080491 # average WriteReq mshr miss latency
2334system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23111.194467 # average SoftPFReq mshr miss latency
2335system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23111.194467 # average SoftPFReq mshr miss latency
2336system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25477.174613 # average WriteInvalidateReq mshr miss latency
2337system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25477.174613 # average WriteInvalidateReq mshr miss latency
2338system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12683.756548 # average LoadLockedReq mshr miss latency
2339system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12683.756548 # average LoadLockedReq mshr miss latency
2340system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19125.441916 # average StoreCondReq mshr miss latency
2341system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19125.441916 # average StoreCondReq mshr miss latency
2342system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
2343system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2344system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13858.040359 # average overall mshr miss latency
2345system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13858.040359 # average overall mshr miss latency
2346system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15079.857978 # average overall mshr miss latency
2347system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15079.857978 # average overall mshr miss latency
2348system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
2349system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2350system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
2351system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
2352system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
2353system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2354system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2355system.cpu1.icache.tags.replacements 5522406 # number of replacements
2356system.cpu1.icache.tags.tagsinuse 501.856310 # Cycle average of tags in use
2357system.cpu1.icache.tags.total_refs 190094169 # Total number of references to valid blocks.
2358system.cpu1.icache.tags.sampled_refs 5522918 # Sample count of references to valid blocks.
2359system.cpu1.icache.tags.avg_refs 34.419155 # Average number of references to valid blocks.
2360system.cpu1.icache.tags.warmup_cycle 8518418347000 # Cycle when the warmup percentage was hit.
2361system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.856310 # Average occupied blocks per requestor
2362system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980188 # Average percentage of cache occupancy
2363system.cpu1.icache.tags.occ_percent::total 0.980188 # Average percentage of cache occupancy
2364system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2365system.cpu1.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
2366system.cpu1.icache.tags.age_task_id_blocks_1024::1 335 # Occupied blocks per task id
2367system.cpu1.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id
2368system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2369system.cpu1.icache.tags.tag_accesses 397333844 # Number of tag accesses
2370system.cpu1.icache.tags.data_accesses 397333844 # Number of data accesses
2371system.cpu1.icache.ReadReq_hits::cpu1.inst 190094169 # number of ReadReq hits
2372system.cpu1.icache.ReadReq_hits::total 190094169 # number of ReadReq hits
2373system.cpu1.icache.demand_hits::cpu1.inst 190094169 # number of demand (read+write) hits
2374system.cpu1.icache.demand_hits::total 190094169 # number of demand (read+write) hits
2375system.cpu1.icache.overall_hits::cpu1.inst 190094169 # number of overall hits
2376system.cpu1.icache.overall_hits::total 190094169 # number of overall hits
2377system.cpu1.icache.ReadReq_misses::cpu1.inst 5811281 # number of ReadReq misses
2378system.cpu1.icache.ReadReq_misses::total 5811281 # number of ReadReq misses
2379system.cpu1.icache.demand_misses::cpu1.inst 5811281 # number of demand (read+write) misses
2380system.cpu1.icache.demand_misses::total 5811281 # number of demand (read+write) misses
2381system.cpu1.icache.overall_misses::cpu1.inst 5811281 # number of overall misses
2382system.cpu1.icache.overall_misses::total 5811281 # number of overall misses
2383system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 61520167992 # number of ReadReq miss cycles
2384system.cpu1.icache.ReadReq_miss_latency::total 61520167992 # number of ReadReq miss cycles
2385system.cpu1.icache.demand_miss_latency::cpu1.inst 61520167992 # number of demand (read+write) miss cycles
2386system.cpu1.icache.demand_miss_latency::total 61520167992 # number of demand (read+write) miss cycles
2387system.cpu1.icache.overall_miss_latency::cpu1.inst 61520167992 # number of overall miss cycles
2388system.cpu1.icache.overall_miss_latency::total 61520167992 # number of overall miss cycles
2389system.cpu1.icache.ReadReq_accesses::cpu1.inst 195905450 # number of ReadReq accesses(hits+misses)
2390system.cpu1.icache.ReadReq_accesses::total 195905450 # number of ReadReq accesses(hits+misses)
2391system.cpu1.icache.demand_accesses::cpu1.inst 195905450 # number of demand (read+write) accesses
2392system.cpu1.icache.demand_accesses::total 195905450 # number of demand (read+write) accesses
2393system.cpu1.icache.overall_accesses::cpu1.inst 195905450 # number of overall (read+write) accesses
2394system.cpu1.icache.overall_accesses::total 195905450 # number of overall (read+write) accesses
2395system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029664 # miss rate for ReadReq accesses
2396system.cpu1.icache.ReadReq_miss_rate::total 0.029664 # miss rate for ReadReq accesses
2397system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029664 # miss rate for demand accesses
2398system.cpu1.icache.demand_miss_rate::total 0.029664 # miss rate for demand accesses
2399system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029664 # miss rate for overall accesses
2400system.cpu1.icache.overall_miss_rate::total 0.029664 # miss rate for overall accesses
2401system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10586.335094 # average ReadReq miss latency
2402system.cpu1.icache.ReadReq_avg_miss_latency::total 10586.335094 # average ReadReq miss latency
2403system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10586.335094 # average overall miss latency
2404system.cpu1.icache.demand_avg_miss_latency::total 10586.335094 # average overall miss latency
2405system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10586.335094 # average overall miss latency
2406system.cpu1.icache.overall_avg_miss_latency::total 10586.335094 # average overall miss latency
2407system.cpu1.icache.blocked_cycles::no_mshrs 7857995 # number of cycles access was blocked
2408system.cpu1.icache.blocked_cycles::no_targets 39 # number of cycles access was blocked
2409system.cpu1.icache.blocked::no_mshrs 642168 # number of cycles access was blocked
2410system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
2411system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.236665 # average number of cycles each access was blocked
2412system.cpu1.icache.avg_blocked_cycles::no_targets 39 # average number of cycles each access was blocked
2413system.cpu1.icache.fast_writes 0 # number of fast writes performed
2414system.cpu1.icache.cache_copies 0 # number of cache copies performed
2415system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 288337 # number of ReadReq MSHR hits
2416system.cpu1.icache.ReadReq_mshr_hits::total 288337 # number of ReadReq MSHR hits
2417system.cpu1.icache.demand_mshr_hits::cpu1.inst 288337 # number of demand (read+write) MSHR hits
2418system.cpu1.icache.demand_mshr_hits::total 288337 # number of demand (read+write) MSHR hits
2419system.cpu1.icache.overall_mshr_hits::cpu1.inst 288337 # number of overall MSHR hits
2420system.cpu1.icache.overall_mshr_hits::total 288337 # number of overall MSHR hits
2421system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5522944 # number of ReadReq MSHR misses
2422system.cpu1.icache.ReadReq_mshr_misses::total 5522944 # number of ReadReq MSHR misses
2423system.cpu1.icache.demand_mshr_misses::cpu1.inst 5522944 # number of demand (read+write) MSHR misses
2424system.cpu1.icache.demand_mshr_misses::total 5522944 # number of demand (read+write) MSHR misses
2425system.cpu1.icache.overall_mshr_misses::cpu1.inst 5522944 # number of overall MSHR misses
2426system.cpu1.icache.overall_mshr_misses::total 5522944 # number of overall MSHR misses
2427system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 50254087338 # number of ReadReq MSHR miss cycles
2428system.cpu1.icache.ReadReq_mshr_miss_latency::total 50254087338 # number of ReadReq MSHR miss cycles
2429system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 50254087338 # number of demand (read+write) MSHR miss cycles
2430system.cpu1.icache.demand_mshr_miss_latency::total 50254087338 # number of demand (read+write) MSHR miss cycles
2431system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 50254087338 # number of overall MSHR miss cycles
2432system.cpu1.icache.overall_mshr_miss_latency::total 50254087338 # number of overall MSHR miss cycles
2433system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5802498 # number of ReadReq MSHR uncacheable cycles
2434system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5802498 # number of ReadReq MSHR uncacheable cycles
2435system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5802498 # number of overall MSHR uncacheable cycles
2436system.cpu1.icache.overall_mshr_uncacheable_latency::total 5802498 # number of overall MSHR uncacheable cycles
2437system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028192 # mshr miss rate for ReadReq accesses
2438system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028192 # mshr miss rate for ReadReq accesses
2439system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028192 # mshr miss rate for demand accesses
2440system.cpu1.icache.demand_mshr_miss_rate::total 0.028192 # mshr miss rate for demand accesses
2441system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028192 # mshr miss rate for overall accesses
2442system.cpu1.icache.overall_mshr_miss_rate::total 0.028192 # mshr miss rate for overall accesses
2443system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9099.148450 # average ReadReq mshr miss latency
2444system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9099.148450 # average ReadReq mshr miss latency
2445system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9099.148450 # average overall mshr miss latency
2446system.cpu1.icache.demand_avg_mshr_miss_latency::total 9099.148450 # average overall mshr miss latency
2447system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9099.148450 # average overall mshr miss latency
2448system.cpu1.icache.overall_avg_mshr_miss_latency::total 9099.148450 # average overall mshr miss latency
2449system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
2450system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2451system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
2452system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2453system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2454system.cpu1.l2cache.prefetcher.num_hwpf_issued 7021877 # number of hwpf issued
2455system.cpu1.l2cache.prefetcher.pfIdentified 7194867 # number of prefetch candidates identified
2456system.cpu1.l2cache.prefetcher.pfBufferHit 149461 # number of redundant prefetches already in prefetch queue
2457system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
2458system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2459system.cpu1.l2cache.prefetcher.pfSpanPage 884477 # number of prefetches not generated due to page crossing
2460system.cpu1.l2cache.tags.replacements 2159012 # number of replacements
2461system.cpu1.l2cache.tags.tagsinuse 13531.891931 # Cycle average of tags in use
2462system.cpu1.l2cache.tags.total_refs 11463233 # Total number of references to valid blocks.
2463system.cpu1.l2cache.tags.sampled_refs 2175036 # Sample count of references to valid blocks.
2464system.cpu1.l2cache.tags.avg_refs 5.270365 # Average number of references to valid blocks.
2465system.cpu1.l2cache.tags.warmup_cycle 9606894527000 # Cycle when the warmup percentage was hit.
2466system.cpu1.l2cache.tags.occ_blocks::writebacks 5515.011217 # Average occupied blocks per requestor
2467system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 81.352016 # Average occupied blocks per requestor
2468system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 87.650961 # Average occupied blocks per requestor
2469system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3854.550779 # Average occupied blocks per requestor
2470system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3125.340880 # Average occupied blocks per requestor
2471system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 867.986079 # Average occupied blocks per requestor
2472system.cpu1.l2cache.tags.occ_percent::writebacks 0.336610 # Average percentage of cache occupancy
2473system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004965 # Average percentage of cache occupancy
2474system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005350 # Average percentage of cache occupancy
2475system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.235263 # Average percentage of cache occupancy
2476system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.190756 # Average percentage of cache occupancy
2477system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.052978 # Average percentage of cache occupancy
2478system.cpu1.l2cache.tags.occ_percent::total 0.825921 # Average percentage of cache occupancy
2479system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1495 # Occupied blocks per task id
2480system.cpu1.l2cache.tags.occ_task_id_blocks::1023 53 # Occupied blocks per task id
2481system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14476 # Occupied blocks per task id
2482system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
2483system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 35 # Occupied blocks per task id
2484system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 465 # Occupied blocks per task id
2485system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 510 # Occupied blocks per task id
2486system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 477 # Occupied blocks per task id
2487system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
2488system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id
2489system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
2490system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id
2491system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
2492system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1150 # Occupied blocks per task id
2493system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5680 # Occupied blocks per task id
2494system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4086 # Occupied blocks per task id
2495system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3438 # Occupied blocks per task id
2496system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.091248 # Percentage of cache occupancy per task id
2497system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003235 # Percentage of cache occupancy per task id
2498system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.883545 # Percentage of cache occupancy per task id
2499system.cpu1.l2cache.tags.tag_accesses 250860566 # Number of tag accesses
2500system.cpu1.l2cache.tags.data_accesses 250860566 # Number of data accesses
2501system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 536921 # number of ReadReq hits
2502system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 182584 # number of ReadReq hits
2503system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4917912 # number of ReadReq hits
2504system.cpu1.l2cache.ReadReq_hits::cpu1.data 2781477 # number of ReadReq hits
2505system.cpu1.l2cache.ReadReq_hits::total 8418894 # number of ReadReq hits
2506system.cpu1.l2cache.Writeback_hits::writebacks 3392565 # number of Writeback hits
2507system.cpu1.l2cache.Writeback_hits::total 3392565 # number of Writeback hits
2508system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 191757 # number of WriteInvalidateReq hits
2509system.cpu1.l2cache.WriteInvalidateReq_hits::total 191757 # number of WriteInvalidateReq hits
2510system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 71744 # number of UpgradeReq hits
2511system.cpu1.l2cache.UpgradeReq_hits::total 71744 # number of UpgradeReq hits
2512system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 31465 # number of SCUpgradeReq hits
2513system.cpu1.l2cache.SCUpgradeReq_hits::total 31465 # number of SCUpgradeReq hits
2514system.cpu1.l2cache.ReadExReq_hits::cpu1.data 867581 # number of ReadExReq hits
2515system.cpu1.l2cache.ReadExReq_hits::total 867581 # number of ReadExReq hits
2516system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 536921 # number of demand (read+write) hits
2517system.cpu1.l2cache.demand_hits::cpu1.itb.walker 182584 # number of demand (read+write) hits
2518system.cpu1.l2cache.demand_hits::cpu1.inst 4917912 # number of demand (read+write) hits
2519system.cpu1.l2cache.demand_hits::cpu1.data 3649058 # number of demand (read+write) hits
2520system.cpu1.l2cache.demand_hits::total 9286475 # number of demand (read+write) hits
2521system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 536921 # number of overall hits
2522system.cpu1.l2cache.overall_hits::cpu1.itb.walker 182584 # number of overall hits
2523system.cpu1.l2cache.overall_hits::cpu1.inst 4917912 # number of overall hits
2524system.cpu1.l2cache.overall_hits::cpu1.data 3649058 # number of overall hits
2525system.cpu1.l2cache.overall_hits::total 9286475 # number of overall hits
2526system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12339 # number of ReadReq misses
2527system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9008 # number of ReadReq misses
2528system.cpu1.l2cache.ReadReq_misses::cpu1.inst 605020 # number of ReadReq misses
2529system.cpu1.l2cache.ReadReq_misses::cpu1.data 1001664 # number of ReadReq misses
2530system.cpu1.l2cache.ReadReq_misses::total 1628031 # number of ReadReq misses
2531system.cpu1.l2cache.Writeback_misses::writebacks 17 # number of Writeback misses
2532system.cpu1.l2cache.Writeback_misses::total 17 # number of Writeback misses
2533system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 228944 # number of WriteInvalidateReq misses
2534system.cpu1.l2cache.WriteInvalidateReq_misses::total 228944 # number of WriteInvalidateReq misses
2535system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 145584 # number of UpgradeReq misses
2536system.cpu1.l2cache.UpgradeReq_misses::total 145584 # number of UpgradeReq misses
2537system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 172667 # number of SCUpgradeReq misses
2538system.cpu1.l2cache.SCUpgradeReq_misses::total 172667 # number of SCUpgradeReq misses
2539system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 13 # number of SCUpgradeFailReq misses
2540system.cpu1.l2cache.SCUpgradeFailReq_misses::total 13 # number of SCUpgradeFailReq misses
2541system.cpu1.l2cache.ReadExReq_misses::cpu1.data 259180 # number of ReadExReq misses
2542system.cpu1.l2cache.ReadExReq_misses::total 259180 # number of ReadExReq misses
2543system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12339 # number of demand (read+write) misses
2544system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9008 # number of demand (read+write) misses
2545system.cpu1.l2cache.demand_misses::cpu1.inst 605020 # number of demand (read+write) misses
2546system.cpu1.l2cache.demand_misses::cpu1.data 1260844 # number of demand (read+write) misses
2547system.cpu1.l2cache.demand_misses::total 1887211 # number of demand (read+write) misses
2548system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12339 # number of overall misses
2549system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9008 # number of overall misses
2550system.cpu1.l2cache.overall_misses::cpu1.inst 605020 # number of overall misses
2551system.cpu1.l2cache.overall_misses::cpu1.data 1260844 # number of overall misses
2552system.cpu1.l2cache.overall_misses::total 1887211 # number of overall misses
2553system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 492758189 # number of ReadReq miss cycles
2554system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 397546188 # number of ReadReq miss cycles
2555system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 17874502757 # number of ReadReq miss cycles
2556system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 34268686598 # number of ReadReq miss cycles
2557system.cpu1.l2cache.ReadReq_miss_latency::total 53033493732 # number of ReadReq miss cycles
2558system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 241449363 # number of WriteInvalidateReq miss cycles
2559system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 241449363 # number of WriteInvalidateReq miss cycles
2560system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2956550746 # number of UpgradeReq miss cycles
2561system.cpu1.l2cache.UpgradeReq_miss_latency::total 2956550746 # number of UpgradeReq miss cycles
2562system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3438458831 # number of SCUpgradeReq miss cycles
2563system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3438458831 # number of SCUpgradeReq miss cycles
2564system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3243000 # number of SCUpgradeFailReq miss cycles
2565system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3243000 # number of SCUpgradeFailReq miss cycles
2566system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10870225593 # number of ReadExReq miss cycles
2567system.cpu1.l2cache.ReadExReq_miss_latency::total 10870225593 # number of ReadExReq miss cycles
2568system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 492758189 # number of demand (read+write) miss cycles
2569system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 397546188 # number of demand (read+write) miss cycles
2570system.cpu1.l2cache.demand_miss_latency::cpu1.inst 17874502757 # number of demand (read+write) miss cycles
2571system.cpu1.l2cache.demand_miss_latency::cpu1.data 45138912191 # number of demand (read+write) miss cycles
2572system.cpu1.l2cache.demand_miss_latency::total 63903719325 # number of demand (read+write) miss cycles
2573system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 492758189 # number of overall miss cycles
2574system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 397546188 # number of overall miss cycles
2575system.cpu1.l2cache.overall_miss_latency::cpu1.inst 17874502757 # number of overall miss cycles
2576system.cpu1.l2cache.overall_miss_latency::cpu1.data 45138912191 # number of overall miss cycles
2577system.cpu1.l2cache.overall_miss_latency::total 63903719325 # number of overall miss cycles
2578system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 549260 # number of ReadReq accesses(hits+misses)
2579system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 191592 # number of ReadReq accesses(hits+misses)
2580system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5522932 # number of ReadReq accesses(hits+misses)
2581system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3783141 # number of ReadReq accesses(hits+misses)
2582system.cpu1.l2cache.ReadReq_accesses::total 10046925 # number of ReadReq accesses(hits+misses)
2583system.cpu1.l2cache.Writeback_accesses::writebacks 3392582 # number of Writeback accesses(hits+misses)
2584system.cpu1.l2cache.Writeback_accesses::total 3392582 # number of Writeback accesses(hits+misses)
2585system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 420701 # number of WriteInvalidateReq accesses(hits+misses)
2586system.cpu1.l2cache.WriteInvalidateReq_accesses::total 420701 # number of WriteInvalidateReq accesses(hits+misses)
2587system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 217328 # number of UpgradeReq accesses(hits+misses)
2588system.cpu1.l2cache.UpgradeReq_accesses::total 217328 # number of UpgradeReq accesses(hits+misses)
2589system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 204132 # number of SCUpgradeReq accesses(hits+misses)
2590system.cpu1.l2cache.SCUpgradeReq_accesses::total 204132 # number of SCUpgradeReq accesses(hits+misses)
2591system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 13 # number of SCUpgradeFailReq accesses(hits+misses)
2592system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 13 # number of SCUpgradeFailReq accesses(hits+misses)
2593system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1126761 # number of ReadExReq accesses(hits+misses)
2594system.cpu1.l2cache.ReadExReq_accesses::total 1126761 # number of ReadExReq accesses(hits+misses)
2595system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 549260 # number of demand (read+write) accesses
2596system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 191592 # number of demand (read+write) accesses
2597system.cpu1.l2cache.demand_accesses::cpu1.inst 5522932 # number of demand (read+write) accesses
2598system.cpu1.l2cache.demand_accesses::cpu1.data 4909902 # number of demand (read+write) accesses
2599system.cpu1.l2cache.demand_accesses::total 11173686 # number of demand (read+write) accesses
2600system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 549260 # number of overall (read+write) accesses
2601system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 191592 # number of overall (read+write) accesses
2602system.cpu1.l2cache.overall_accesses::cpu1.inst 5522932 # number of overall (read+write) accesses
2603system.cpu1.l2cache.overall_accesses::cpu1.data 4909902 # number of overall (read+write) accesses
2604system.cpu1.l2cache.overall_accesses::total 11173686 # number of overall (read+write) accesses
2605system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022465 # miss rate for ReadReq accesses
2606system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.047017 # miss rate for ReadReq accesses
2607system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.109547 # miss rate for ReadReq accesses
2608system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.264770 # miss rate for ReadReq accesses
2609system.cpu1.l2cache.ReadReq_miss_rate::total 0.162043 # miss rate for ReadReq accesses
2610system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000005 # miss rate for Writeback accesses
2611system.cpu1.l2cache.Writeback_miss_rate::total 0.000005 # miss rate for Writeback accesses
2612system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.544196 # miss rate for WriteInvalidateReq accesses
2613system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.544196 # miss rate for WriteInvalidateReq accesses
2614system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.669881 # miss rate for UpgradeReq accesses
2615system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.669881 # miss rate for UpgradeReq accesses
2616system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.845860 # miss rate for SCUpgradeReq accesses
2617system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.845860 # miss rate for SCUpgradeReq accesses
2618system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2619system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2620system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.230022 # miss rate for ReadExReq accesses
2621system.cpu1.l2cache.ReadExReq_miss_rate::total 0.230022 # miss rate for ReadExReq accesses
2622system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022465 # miss rate for demand accesses
2623system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.047017 # miss rate for demand accesses
2624system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.109547 # miss rate for demand accesses
2625system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.256796 # miss rate for demand accesses
2626system.cpu1.l2cache.demand_miss_rate::total 0.168898 # miss rate for demand accesses
2627system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022465 # miss rate for overall accesses
2628system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.047017 # miss rate for overall accesses
2629system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.109547 # miss rate for overall accesses
2630system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.256796 # miss rate for overall accesses
2631system.cpu1.l2cache.overall_miss_rate::total 0.168898 # miss rate for overall accesses
2632system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39935.018154 # average ReadReq miss latency
2633system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 44132.569716 # average ReadReq miss latency
2634system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29543.656006 # average ReadReq miss latency
2635system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 34211.758232 # average ReadReq miss latency
2636system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32575.235811 # average ReadReq miss latency
2637system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 1054.621929 # average WriteInvalidateReq miss latency
2638system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 1054.621929 # average WriteInvalidateReq miss latency
2639system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20308.212070 # average UpgradeReq miss latency
2640system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20308.212070 # average UpgradeReq miss latency
2641system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19913.815790 # average SCUpgradeReq miss latency
2642system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19913.815790 # average SCUpgradeReq miss latency
2643system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 249461.538462 # average SCUpgradeFailReq miss latency
2644system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 249461.538462 # average SCUpgradeFailReq miss latency
2645system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 41940.834914 # average ReadExReq miss latency
2646system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41940.834914 # average ReadExReq miss latency
2647system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39935.018154 # average overall miss latency
2648system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 44132.569716 # average overall miss latency
2649system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29543.656006 # average overall miss latency
2650system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35800.552797 # average overall miss latency
2651system.cpu1.l2cache.demand_avg_miss_latency::total 33861.459755 # average overall miss latency
2652system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39935.018154 # average overall miss latency
2653system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 44132.569716 # average overall miss latency
2654system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29543.656006 # average overall miss latency
2655system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35800.552797 # average overall miss latency
2656system.cpu1.l2cache.overall_avg_miss_latency::total 33861.459755 # average overall miss latency
2657system.cpu1.l2cache.blocked_cycles::no_mshrs 9 # number of cycles access was blocked
2658system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2659system.cpu1.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked
2660system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2661system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 4.500000 # average number of cycles each access was blocked
2662system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2663system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2664system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2665system.cpu1.l2cache.writebacks::writebacks 971322 # number of writebacks
2666system.cpu1.l2cache.writebacks::total 971322 # number of writebacks
2667system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 2 # number of ReadReq MSHR hits
2668system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 153 # number of ReadReq MSHR hits
2669system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits
2670system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 6612 # number of ReadReq MSHR hits
2671system.cpu1.l2cache.ReadReq_mshr_hits::total 6768 # number of ReadReq MSHR hits
2672system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 63 # number of WriteInvalidateReq MSHR hits
2673system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 63 # number of WriteInvalidateReq MSHR hits
2674system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 20490 # number of ReadExReq MSHR hits
2675system.cpu1.l2cache.ReadExReq_mshr_hits::total 20490 # number of ReadExReq MSHR hits
2676system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 2 # number of demand (read+write) MSHR hits
2677system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 153 # number of demand (read+write) MSHR hits
2678system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
2679system.cpu1.l2cache.demand_mshr_hits::cpu1.data 27102 # number of demand (read+write) MSHR hits
2680system.cpu1.l2cache.demand_mshr_hits::total 27258 # number of demand (read+write) MSHR hits
2681system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 2 # number of overall MSHR hits
2682system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 153 # number of overall MSHR hits
2683system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
2684system.cpu1.l2cache.overall_mshr_hits::cpu1.data 27102 # number of overall MSHR hits
2685system.cpu1.l2cache.overall_mshr_hits::total 27258 # number of overall MSHR hits
2686system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12337 # number of ReadReq MSHR misses
2687system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8855 # number of ReadReq MSHR misses
2688system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 605019 # number of ReadReq MSHR misses
2689system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 995052 # number of ReadReq MSHR misses
2690system.cpu1.l2cache.ReadReq_mshr_misses::total 1621263 # number of ReadReq MSHR misses
2691system.cpu1.l2cache.Writeback_mshr_misses::writebacks 17 # number of Writeback MSHR misses
2692system.cpu1.l2cache.Writeback_mshr_misses::total 17 # number of Writeback MSHR misses
2693system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 705681 # number of HardPFReq MSHR misses
2694system.cpu1.l2cache.HardPFReq_mshr_misses::total 705681 # number of HardPFReq MSHR misses
2695system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 228881 # number of WriteInvalidateReq MSHR misses
2696system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 228881 # number of WriteInvalidateReq MSHR misses
2697system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 145584 # number of UpgradeReq MSHR misses
2698system.cpu1.l2cache.UpgradeReq_mshr_misses::total 145584 # number of UpgradeReq MSHR misses
2699system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 172667 # number of SCUpgradeReq MSHR misses
2700system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 172667 # number of SCUpgradeReq MSHR misses
2701system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 13 # number of SCUpgradeFailReq MSHR misses
2702system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 13 # number of SCUpgradeFailReq MSHR misses
2703system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 238690 # number of ReadExReq MSHR misses
2704system.cpu1.l2cache.ReadExReq_mshr_misses::total 238690 # number of ReadExReq MSHR misses
2705system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12337 # number of demand (read+write) MSHR misses
2706system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8855 # number of demand (read+write) MSHR misses
2707system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 605019 # number of demand (read+write) MSHR misses
2708system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1233742 # number of demand (read+write) MSHR misses
2709system.cpu1.l2cache.demand_mshr_misses::total 1859953 # number of demand (read+write) MSHR misses
2710system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12337 # number of overall MSHR misses
2711system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8855 # number of overall MSHR misses
2712system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 605019 # number of overall MSHR misses
2713system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1233742 # number of overall MSHR misses
2714system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 705681 # number of overall MSHR misses
2715system.cpu1.l2cache.overall_mshr_misses::total 2565634 # number of overall MSHR misses
2716system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 405599231 # number of ReadReq MSHR miss cycles
2717system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 327287462 # number of ReadReq MSHR miss cycles
2718system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 13621135743 # number of ReadReq MSHR miss cycles
2719system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 26954578760 # number of ReadReq MSHR miss cycles
2720system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 41308601196 # number of ReadReq MSHR miss cycles
2721system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 39485552404 # number of HardPFReq MSHR miss cycles
2722system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 39485552404 # number of HardPFReq MSHR miss cycles
2723system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 6916972959 # number of WriteInvalidateReq MSHR miss cycles
2724system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 6916972959 # number of WriteInvalidateReq MSHR miss cycles
2725system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2477712924 # number of UpgradeReq MSHR miss cycles
2726system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2477712924 # number of UpgradeReq MSHR miss cycles
2727system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2304203121 # number of SCUpgradeReq MSHR miss cycles
2728system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2304203121 # number of SCUpgradeReq MSHR miss cycles
2729system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2669000 # number of SCUpgradeFailReq MSHR miss cycles
2730system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2669000 # number of SCUpgradeFailReq MSHR miss cycles
2731system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7509818481 # number of ReadExReq MSHR miss cycles
2732system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7509818481 # number of ReadExReq MSHR miss cycles
2733system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 405599231 # number of demand (read+write) MSHR miss cycles
2734system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 327287462 # number of demand (read+write) MSHR miss cycles
2735system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 13621135743 # number of demand (read+write) MSHR miss cycles
2736system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 34464397241 # number of demand (read+write) MSHR miss cycles
2737system.cpu1.l2cache.demand_mshr_miss_latency::total 48818419677 # number of demand (read+write) MSHR miss cycles
2738system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 405599231 # number of overall MSHR miss cycles
2739system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 327287462 # number of overall MSHR miss cycles
2740system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 13621135743 # number of overall MSHR miss cycles
2741system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 34464397241 # number of overall MSHR miss cycles
2742system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 39485552404 # number of overall MSHR miss cycles
2743system.cpu1.l2cache.overall_mshr_miss_latency::total 88303972081 # number of overall MSHR miss cycles
2744system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5233250 # number of ReadReq MSHR uncacheable cycles
2745system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 741632996 # number of ReadReq MSHR uncacheable cycles
2746system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 746866246 # number of ReadReq MSHR uncacheable cycles
2747system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 846035990 # number of WriteReq MSHR uncacheable cycles
2748system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 846035990 # number of WriteReq MSHR uncacheable cycles
2749system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 5233250 # number of overall MSHR uncacheable cycles
2750system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1587668986 # number of overall MSHR uncacheable cycles
2751system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1592902236 # number of overall MSHR uncacheable cycles
2752system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022461 # mshr miss rate for ReadReq accesses
2753system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046218 # mshr miss rate for ReadReq accesses
2754system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.109547 # mshr miss rate for ReadReq accesses
2755system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.263023 # mshr miss rate for ReadReq accesses
2756system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.161369 # mshr miss rate for ReadReq accesses
2757system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000005 # mshr miss rate for Writeback accesses
2758system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000005 # mshr miss rate for Writeback accesses
2759system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2760system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2761system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.544047 # mshr miss rate for WriteInvalidateReq accesses
2762system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.544047 # mshr miss rate for WriteInvalidateReq accesses
2763system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.669881 # mshr miss rate for UpgradeReq accesses
2764system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.669881 # mshr miss rate for UpgradeReq accesses
2765system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.845860 # mshr miss rate for SCUpgradeReq accesses
2766system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.845860 # mshr miss rate for SCUpgradeReq accesses
2767system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2768system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2769system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.211837 # mshr miss rate for ReadExReq accesses
2770system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.211837 # mshr miss rate for ReadExReq accesses
2771system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022461 # mshr miss rate for demand accesses
2772system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046218 # mshr miss rate for demand accesses
2773system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.109547 # mshr miss rate for demand accesses
2774system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.251276 # mshr miss rate for demand accesses
2775system.cpu1.l2cache.demand_mshr_miss_rate::total 0.166458 # mshr miss rate for demand accesses
2776system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022461 # mshr miss rate for overall accesses
2777system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046218 # mshr miss rate for overall accesses
2778system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.109547 # mshr miss rate for overall accesses
2779system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.251276 # mshr miss rate for overall accesses
2780system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2781system.cpu1.l2cache.overall_mshr_miss_rate::total 0.229614 # mshr miss rate for overall accesses
2782system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996 # average ReadReq mshr miss latency
2783system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343 # average ReadReq mshr miss latency
2784system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22513.566918 # average ReadReq mshr miss latency
2785system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 27088.613218 # average ReadReq mshr miss latency
2786system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25479.272145 # average ReadReq mshr miss latency
2787system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55953.826735 # average HardPFReq mshr miss latency
2788system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55953.826735 # average HardPFReq mshr miss latency
2789system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30220.826364 # average WriteInvalidateReq mshr miss latency
2790system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 30220.826364 # average WriteInvalidateReq mshr miss latency
2791system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17019.129327 # average UpgradeReq mshr miss latency
2792system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17019.129327 # average UpgradeReq mshr miss latency
2793system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13344.779958 # average SCUpgradeReq mshr miss latency
2794system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13344.779958 # average SCUpgradeReq mshr miss latency
2795system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 205307.692308 # average SCUpgradeFailReq mshr miss latency
2796system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 205307.692308 # average SCUpgradeFailReq mshr miss latency
2797system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31462.643936 # average ReadExReq mshr miss latency
2798system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31462.643936 # average ReadExReq mshr miss latency
2799system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996 # average overall mshr miss latency
2800system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343 # average overall mshr miss latency
2801system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22513.566918 # average overall mshr miss latency
2802system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27934.849621 # average overall mshr miss latency
2803system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26247.125426 # average overall mshr miss latency
2804system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996 # average overall mshr miss latency
2805system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343 # average overall mshr miss latency
2806system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22513.566918 # average overall mshr miss latency
2807system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27934.849621 # average overall mshr miss latency
2808system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55953.826735 # average overall mshr miss latency
2809system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34417.992621 # average overall mshr miss latency
2810system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
2811system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
2812system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2813system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
2814system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
2815system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
2816system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
2817system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2818system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2819system.cpu1.toL2Bus.trans_dist::ReadReq 12802922 # Transaction distribution
2820system.cpu1.toL2Bus.trans_dist::ReadResp 10291743 # Transaction distribution
2821system.cpu1.toL2Bus.trans_dist::WriteReq 6895 # Transaction distribution
2822system.cpu1.toL2Bus.trans_dist::WriteResp 6895 # Transaction distribution
2823system.cpu1.toL2Bus.trans_dist::Writeback 3392582 # Transaction distribution
2824system.cpu1.toL2Bus.trans_dist::HardPFReq 1076196 # Transaction distribution
2825system.cpu1.toL2Bus.trans_dist::HardPFResp 13 # Transaction distribution
2826system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1156933 # Transaction distribution
2827system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 420701 # Transaction distribution
2828system.cpu1.toL2Bus.trans_dist::UpgradeReq 464615 # Transaction distribution
2829system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 376292 # Transaction distribution
2830system.cpu1.toL2Bus.trans_dist::UpgradeResp 486818 # Transaction distribution
2831system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 88 # Transaction distribution
2832system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 157 # Transaction distribution
2833system.cpu1.toL2Bus.trans_dist::ReadExReq 1296360 # Transaction distribution
2834system.cpu1.toL2Bus.trans_dist::ReadExResp 1132878 # Transaction distribution
2835system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11046012 # Packet count per connected master and slave (bytes)
2836system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15089863 # Packet count per connected master and slave (bytes)
2837system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 415115 # Packet count per connected master and slave (bytes)
2838system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1210522 # Packet count per connected master and slave (bytes)
2839system.cpu1.toL2Bus.pkt_count::total 27761512 # Packet count per connected master and slave (bytes)
2840system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 353468736 # Cumulative packet size per connected master and slave (bytes)
2841system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 564735319 # Cumulative packet size per connected master and slave (bytes)
2842system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1532736 # Cumulative packet size per connected master and slave (bytes)
2843system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4394080 # Cumulative packet size per connected master and slave (bytes)
2844system.cpu1.toL2Bus.pkt_size::total 924130871 # Cumulative packet size per connected master and slave (bytes)
2845system.cpu1.toL2Bus.snoops 5316111 # Total snoops (count)
2846system.cpu1.toL2Bus.snoop_fanout::samples 20559073 # Request fanout histogram
2847system.cpu1.toL2Bus.snoop_fanout::mean 5.243524 # Request fanout histogram
2848system.cpu1.toL2Bus.snoop_fanout::stdev 0.429209 # Request fanout histogram
2849system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2850system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2851system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
2852system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
2853system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
2854system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
2855system.cpu1.toL2Bus.snoop_fanout::5 15552442 75.65% 75.65% # Request fanout histogram
2856system.cpu1.toL2Bus.snoop_fanout::6 5006631 24.35% 100.00% # Request fanout histogram
2857system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2858system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
2859system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
2860system.cpu1.toL2Bus.snoop_fanout::total 20559073 # Request fanout histogram
2861system.cpu1.toL2Bus.reqLayer0.occupancy 11602796673 # Layer occupancy (ticks)
2862system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2863system.cpu1.toL2Bus.snoopLayer0.occupancy 182870488 # Layer occupancy (ticks)
2864system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2865system.cpu1.toL2Bus.respLayer0.occupancy 8299279905 # Layer occupancy (ticks)
2866system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2867system.cpu1.toL2Bus.respLayer1.occupancy 7848510644 # Layer occupancy (ticks)
2868system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2869system.cpu1.toL2Bus.respLayer2.occupancy 224378946 # Layer occupancy (ticks)
2870system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2871system.cpu1.toL2Bus.respLayer3.occupancy 662954125 # Layer occupancy (ticks)
2872system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2873system.iobus.trans_dist::ReadReq 40399 # Transaction distribution
2874system.iobus.trans_dist::ReadResp 40399 # Transaction distribution
2875system.iobus.trans_dist::WriteReq 136785 # Transaction distribution
2876system.iobus.trans_dist::WriteResp 30057 # Transaction distribution
2877system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
2878system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48154 # Packet count per connected master and slave (bytes)
2879system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2880system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2881system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2882system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2883system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2884system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2885system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2886system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2887system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2888system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
2889system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
2890system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2891system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
2892system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
2893system.iobus.pkt_count_system.bridge.master::total 123088 # Packet count per connected master and slave (bytes)
2894system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231200 # Packet count per connected master and slave (bytes)
2895system.iobus.pkt_count_system.realview.ide.dma::total 231200 # Packet count per connected master and slave (bytes)
2896system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2897system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2898system.iobus.pkt_count::total 354368 # Packet count per connected master and slave (bytes)
2899system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48174 # Cumulative packet size per connected master and slave (bytes)
2900system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2901system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2902system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2903system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2904system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2905system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2906system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2907system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
2908system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2909system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
2910system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
2911system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2912system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
2913system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
2914system.iobus.pkt_size_system.bridge.master::total 156195 # Cumulative packet size per connected master and slave (bytes)
2915system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338816 # Cumulative packet size per connected master and slave (bytes)
2916system.iobus.pkt_size_system.realview.ide.dma::total 7338816 # Cumulative packet size per connected master and slave (bytes)
2917system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
2918system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2919system.iobus.pkt_size::total 7497097 # Cumulative packet size per connected master and slave (bytes)
2920system.iobus.reqLayer0.occupancy 36604000 # Layer occupancy (ticks)
2921system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2922system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
2923system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2924system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
2925system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2926system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
2927system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2928system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
2929system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
2930system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
2931system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
2932system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
2933system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
2934system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
2935system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
2936system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
2937system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
2938system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
2939system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
2940system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks)
2941system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2942system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
2943system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2944system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
2945system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2946system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
2947system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2948system.iobus.reqLayer27.occupancy 1043087367 # Layer occupancy (ticks)
2949system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2950system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
2951system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
2952system.iobus.respLayer0.occupancy 93034000 # Layer occupancy (ticks)
2953system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2954system.iobus.respLayer3.occupancy 179187461 # Layer occupancy (ticks)
2955system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2956system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
2957system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2958system.iocache.tags.replacements 115604 # number of replacements
2959system.iocache.tags.tagsinuse 11.301402 # Cycle average of tags in use
2960system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2961system.iocache.tags.sampled_refs 115620 # Sample count of references to valid blocks.
2962system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2963system.iocache.tags.warmup_cycle 9117040369000 # Cycle when the warmup percentage was hit.
2964system.iocache.tags.occ_blocks::realview.ethernet 7.419209 # Average occupied blocks per requestor
2965system.iocache.tags.occ_blocks::realview.ide 3.882193 # Average occupied blocks per requestor
2966system.iocache.tags.occ_percent::realview.ethernet 0.463701 # Average percentage of cache occupancy
2967system.iocache.tags.occ_percent::realview.ide 0.242637 # Average percentage of cache occupancy
2968system.iocache.tags.occ_percent::total 0.706338 # Average percentage of cache occupancy
2969system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2970system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2971system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2972system.iocache.tags.tag_accesses 1040757 # Number of tag accesses
2973system.iocache.tags.data_accesses 1040757 # Number of data accesses
2974system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2975system.iocache.ReadReq_misses::realview.ide 8872 # number of ReadReq misses
2976system.iocache.ReadReq_misses::total 8909 # number of ReadReq misses
2977system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2978system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2979system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses
2980system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses
2981system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2982system.iocache.demand_misses::realview.ide 8872 # number of demand (read+write) misses
2983system.iocache.demand_misses::total 8912 # number of demand (read+write) misses
2984system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2985system.iocache.overall_misses::realview.ide 8872 # number of overall misses
2986system.iocache.overall_misses::total 8912 # number of overall misses
2987system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles
2988system.iocache.ReadReq_miss_latency::realview.ide 1954318592 # number of ReadReq miss cycles
2989system.iocache.ReadReq_miss_latency::total 1960025592 # number of ReadReq miss cycles
2990system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles
2991system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles
2992system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28939092314 # number of WriteInvalidateReq miss cycles
2993system.iocache.WriteInvalidateReq_miss_latency::total 28939092314 # number of WriteInvalidateReq miss cycles
2994system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles
2995system.iocache.demand_miss_latency::realview.ide 1954318592 # number of demand (read+write) miss cycles
2996system.iocache.demand_miss_latency::total 1960382592 # number of demand (read+write) miss cycles
2997system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles
2998system.iocache.overall_miss_latency::realview.ide 1954318592 # number of overall miss cycles
2999system.iocache.overall_miss_latency::total 1960382592 # number of overall miss cycles
3000system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
3001system.iocache.ReadReq_accesses::realview.ide 8872 # number of ReadReq accesses(hits+misses)
3002system.iocache.ReadReq_accesses::total 8909 # number of ReadReq accesses(hits+misses)
3003system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
3004system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
3005system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses)
3006system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses)
3007system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
3008system.iocache.demand_accesses::realview.ide 8872 # number of demand (read+write) accesses
3009system.iocache.demand_accesses::total 8912 # number of demand (read+write) accesses
3010system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
3011system.iocache.overall_accesses::realview.ide 8872 # number of overall (read+write) accesses
3012system.iocache.overall_accesses::total 8912 # number of overall (read+write) accesses
3013system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
3014system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
3015system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
3016system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
3017system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
3018system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
3019system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
3020system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
3021system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
3022system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
3023system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
3024system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
3025system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
3026system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency
3027system.iocache.ReadReq_avg_miss_latency::realview.ide 220279.372408 # average ReadReq miss latency
3028system.iocache.ReadReq_avg_miss_latency::total 220005.117522 # average ReadReq miss latency
3029system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency
3030system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency
3031system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271148.080298 # average WriteInvalidateReq miss latency
3032system.iocache.WriteInvalidateReq_avg_miss_latency::total 271148.080298 # average WriteInvalidateReq miss latency
3033system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency
3034system.iocache.demand_avg_miss_latency::realview.ide 220279.372408 # average overall miss latency
3035system.iocache.demand_avg_miss_latency::total 219971.116697 # average overall miss latency
3036system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency
3037system.iocache.overall_avg_miss_latency::realview.ide 220279.372408 # average overall miss latency
3038system.iocache.overall_avg_miss_latency::total 219971.116697 # average overall miss latency
3039system.iocache.blocked_cycles::no_mshrs 228427 # number of cycles access was blocked
3040system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
3041system.iocache.blocked::no_mshrs 27535 # number of cycles access was blocked
3042system.iocache.blocked::no_targets 0 # number of cycles access was blocked
3043system.iocache.avg_blocked_cycles::no_mshrs 8.295878 # average number of cycles each access was blocked
3044system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3045system.iocache.fast_writes 0 # number of fast writes performed
3046system.iocache.cache_copies 0 # number of cache copies performed
3047system.iocache.writebacks::writebacks 106702 # number of writebacks
3048system.iocache.writebacks::total 106702 # number of writebacks
3049system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
3050system.iocache.ReadReq_mshr_misses::realview.ide 8872 # number of ReadReq MSHR misses
3051system.iocache.ReadReq_mshr_misses::total 8909 # number of ReadReq MSHR misses
3052system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
3053system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
3054system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses
3055system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses
3056system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
3057system.iocache.demand_mshr_misses::realview.ide 8872 # number of demand (read+write) MSHR misses
3058system.iocache.demand_mshr_misses::total 8912 # number of demand (read+write) MSHR misses
3059system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
3060system.iocache.overall_mshr_misses::realview.ide 8872 # number of overall MSHR misses
3061system.iocache.overall_mshr_misses::total 8912 # number of overall MSHR misses
3062system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles
3063system.iocache.ReadReq_mshr_miss_latency::realview.ide 1492830122 # number of ReadReq MSHR miss cycles
3064system.iocache.ReadReq_mshr_miss_latency::total 1496613122 # number of ReadReq MSHR miss cycles
3065system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
3066system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
3067system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23388843706 # number of WriteInvalidateReq MSHR miss cycles
3068system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23388843706 # number of WriteInvalidateReq MSHR miss cycles
3069system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles
3070system.iocache.demand_mshr_miss_latency::realview.ide 1492830122 # number of demand (read+write) MSHR miss cycles
3071system.iocache.demand_mshr_miss_latency::total 1496814122 # number of demand (read+write) MSHR miss cycles
3072system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles
3073system.iocache.overall_mshr_miss_latency::realview.ide 1492830122 # number of overall MSHR miss cycles
3074system.iocache.overall_mshr_miss_latency::total 1496814122 # number of overall MSHR miss cycles
3075system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
3076system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
3077system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
3078system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
3079system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
3080system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
3081system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
3082system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
3083system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
3084system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
3085system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
3086system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
3087system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
3088system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency
3089system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168263.088593 # average ReadReq mshr miss latency
3090system.iocache.ReadReq_avg_mshr_miss_latency::total 167988.901336 # average ReadReq mshr miss latency
3091system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
3092system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
3093system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219144.401713 # average WriteInvalidateReq mshr miss latency
3094system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219144.401713 # average WriteInvalidateReq mshr miss latency
3095system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency
3096system.iocache.demand_avg_mshr_miss_latency::realview.ide 168263.088593 # average overall mshr miss latency
3097system.iocache.demand_avg_mshr_miss_latency::total 167954.905969 # average overall mshr miss latency
3098system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency
3099system.iocache.overall_avg_mshr_miss_latency::realview.ide 168263.088593 # average overall mshr miss latency
3100system.iocache.overall_avg_mshr_miss_latency::total 167954.905969 # average overall mshr miss latency
3101system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
3102system.l2c.tags.replacements 1613331 # number of replacements
3103system.l2c.tags.tagsinuse 64339.343113 # Cycle average of tags in use
3104system.l2c.tags.total_refs 4797018 # Total number of references to valid blocks.
3105system.l2c.tags.sampled_refs 1673818 # Sample count of references to valid blocks.
3106system.l2c.tags.avg_refs 2.865914 # Average number of references to valid blocks.
3107system.l2c.tags.warmup_cycle 3243842500 # Cycle when the warmup percentage was hit.
3108system.l2c.tags.occ_blocks::writebacks 19101.398352 # Average occupied blocks per requestor
3109system.l2c.tags.occ_blocks::cpu0.dtb.walker 185.742619 # Average occupied blocks per requestor
3110system.l2c.tags.occ_blocks::cpu0.itb.walker 228.186438 # Average occupied blocks per requestor
3111system.l2c.tags.occ_blocks::cpu0.inst 3981.341018 # Average occupied blocks per requestor
3112system.l2c.tags.occ_blocks::cpu0.data 11353.199987 # Average occupied blocks per requestor
3113system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11643.208368 # Average occupied blocks per requestor
3114system.l2c.tags.occ_blocks::cpu1.dtb.walker 179.349370 # Average occupied blocks per requestor
3115system.l2c.tags.occ_blocks::cpu1.itb.walker 266.651363 # Average occupied blocks per requestor
3116system.l2c.tags.occ_blocks::cpu1.inst 3248.685748 # Average occupied blocks per requestor
3117system.l2c.tags.occ_blocks::cpu1.data 4974.329517 # Average occupied blocks per requestor
3118system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9177.250333 # Average occupied blocks per requestor
3119system.l2c.tags.occ_percent::writebacks 0.291464 # Average percentage of cache occupancy
3120system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002834 # Average percentage of cache occupancy
3121system.l2c.tags.occ_percent::cpu0.itb.walker 0.003482 # Average percentage of cache occupancy
3122system.l2c.tags.occ_percent::cpu0.inst 0.060750 # Average percentage of cache occupancy
3123system.l2c.tags.occ_percent::cpu0.data 0.173236 # Average percentage of cache occupancy
3124system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.177661 # Average percentage of cache occupancy
3125system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002737 # Average percentage of cache occupancy
3126system.l2c.tags.occ_percent::cpu1.itb.walker 0.004069 # Average percentage of cache occupancy
3127system.l2c.tags.occ_percent::cpu1.inst 0.049571 # Average percentage of cache occupancy
3128system.l2c.tags.occ_percent::cpu1.data 0.075902 # Average percentage of cache occupancy
3129system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.140034 # Average percentage of cache occupancy
3130system.l2c.tags.occ_percent::total 0.981740 # Average percentage of cache occupancy
3131system.l2c.tags.occ_task_id_blocks::1022 10683 # Occupied blocks per task id
3132system.l2c.tags.occ_task_id_blocks::1023 245 # Occupied blocks per task id
3133system.l2c.tags.occ_task_id_blocks::1024 49559 # Occupied blocks per task id
3134system.l2c.tags.age_task_id_blocks_1022::0 76 # Occupied blocks per task id
3135system.l2c.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id
3136system.l2c.tags.age_task_id_blocks_1022::2 157 # Occupied blocks per task id
3137system.l2c.tags.age_task_id_blocks_1022::3 995 # Occupied blocks per task id
3138system.l2c.tags.age_task_id_blocks_1022::4 9444 # Occupied blocks per task id
3139system.l2c.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id
3140system.l2c.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id
3141system.l2c.tags.age_task_id_blocks_1023::4 227 # Occupied blocks per task id
3142system.l2c.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id
3143system.l2c.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id
3144system.l2c.tags.age_task_id_blocks_1024::2 3090 # Occupied blocks per task id
3145system.l2c.tags.age_task_id_blocks_1024::3 3968 # Occupied blocks per task id
3146system.l2c.tags.age_task_id_blocks_1024::4 42149 # Occupied blocks per task id
3147system.l2c.tags.occ_task_id_percent::1022 0.163010 # Percentage of cache occupancy per task id
3148system.l2c.tags.occ_task_id_percent::1023 0.003738 # Percentage of cache occupancy per task id
3149system.l2c.tags.occ_task_id_percent::1024 0.756210 # Percentage of cache occupancy per task id
3150system.l2c.tags.tag_accesses 64781750 # Number of tag accesses
3151system.l2c.tags.data_accesses 64781750 # Number of data accesses
3152system.l2c.ReadReq_hits::cpu0.dtb.walker 6508 # number of ReadReq hits
3153system.l2c.ReadReq_hits::cpu0.itb.walker 4319 # number of ReadReq hits
3154system.l2c.ReadReq_hits::cpu0.inst 640995 # number of ReadReq hits
3155system.l2c.ReadReq_hits::cpu0.data 651108 # number of ReadReq hits
3156system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 307248 # number of ReadReq hits
3157system.l2c.ReadReq_hits::cpu1.dtb.walker 6236 # number of ReadReq hits
3158system.l2c.ReadReq_hits::cpu1.itb.walker 4043 # number of ReadReq hits
3159system.l2c.ReadReq_hits::cpu1.inst 550704 # number of ReadReq hits
3160system.l2c.ReadReq_hits::cpu1.data 545723 # number of ReadReq hits
3161system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 278481 # number of ReadReq hits
3162system.l2c.ReadReq_hits::total 2995365 # number of ReadReq hits
3163system.l2c.Writeback_hits::writebacks 2564009 # number of Writeback hits
3164system.l2c.Writeback_hits::total 2564009 # number of Writeback hits
3165system.l2c.WriteInvalidateReq_hits::cpu0.data 138658 # number of WriteInvalidateReq hits
3166system.l2c.WriteInvalidateReq_hits::cpu1.data 123170 # number of WriteInvalidateReq hits
3167system.l2c.WriteInvalidateReq_hits::total 261828 # number of WriteInvalidateReq hits
3168system.l2c.UpgradeReq_hits::cpu0.data 30955 # number of UpgradeReq hits
3169system.l2c.UpgradeReq_hits::cpu1.data 32781 # number of UpgradeReq hits
3170system.l2c.UpgradeReq_hits::total 63736 # number of UpgradeReq hits
3171system.l2c.SCUpgradeReq_hits::cpu0.data 6525 # number of SCUpgradeReq hits
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3278system.l2c.overall_miss_latency::cpu0.dtb.walker 214285749 # number of overall miss cycles
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3288system.l2c.overall_miss_latency::total 132050878349 # number of overall miss cycles
3289system.l2c.ReadReq_accesses::cpu0.dtb.walker 9026 # number of ReadReq accesses(hits+misses)
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3299system.l2c.ReadReq_accesses::total 3959363 # number of ReadReq accesses(hits+misses)
3300system.l2c.Writeback_accesses::writebacks 2564009 # number of Writeback accesses(hits+misses)
3301system.l2c.Writeback_accesses::total 2564009 # number of Writeback accesses(hits+misses)
3302system.l2c.WriteInvalidateReq_accesses::cpu0.data 629019 # number of WriteInvalidateReq accesses(hits+misses)
3303system.l2c.WriteInvalidateReq_accesses::cpu1.data 219274 # number of WriteInvalidateReq accesses(hits+misses)
3304system.l2c.WriteInvalidateReq_accesses::total 848293 # number of WriteInvalidateReq accesses(hits+misses)
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3309system.l2c.SCUpgradeReq_accesses::cpu1.data 14293 # number of SCUpgradeReq accesses(hits+misses)
3310system.l2c.SCUpgradeReq_accesses::total 31260 # number of SCUpgradeReq accesses(hits+misses)
3311system.l2c.ReadExReq_accesses::cpu0.data 141828 # number of ReadExReq accesses(hits+misses)
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3314system.l2c.demand_accesses::cpu0.dtb.walker 9026 # number of demand (read+write) accesses
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3325system.l2c.overall_accesses::cpu0.dtb.walker 9026 # number of overall (read+write) accesses
3326system.l2c.overall_accesses::cpu0.itb.walker 6607 # number of overall (read+write) accesses
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3331system.l2c.overall_accesses::cpu1.itb.walker 6487 # number of overall (read+write) accesses
3332system.l2c.overall_accesses::cpu1.inst 605017 # number of overall (read+write) accesses
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3335system.l2c.overall_accesses::total 4207043 # number of overall (read+write) accesses
3336system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.278972 # miss rate for ReadReq accesses
3337system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.346299 # miss rate for ReadReq accesses
3338system.l2c.ReadReq_miss_rate::cpu0.inst 0.087709 # miss rate for ReadReq accesses
3339system.l2c.ReadReq_miss_rate::cpu0.data 0.202206 # miss rate for ReadReq accesses
3340system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.506634 # miss rate for ReadReq accesses
3341system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.310635 # miss rate for ReadReq accesses
3342system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.376754 # miss rate for ReadReq accesses
3343system.l2c.ReadReq_miss_rate::cpu1.inst 0.089771 # miss rate for ReadReq accesses
3344system.l2c.ReadReq_miss_rate::cpu1.data 0.193196 # miss rate for ReadReq accesses
3345system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.448841 # miss rate for ReadReq accesses
3346system.l2c.ReadReq_miss_rate::total 0.243473 # miss rate for ReadReq accesses
3347system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.779565 # miss rate for WriteInvalidateReq accesses
3348system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.438283 # miss rate for WriteInvalidateReq accesses
3349system.l2c.WriteInvalidateReq_miss_rate::total 0.691347 # miss rate for WriteInvalidateReq accesses
3350system.l2c.UpgradeReq_miss_rate::cpu0.data 0.608561 # miss rate for UpgradeReq accesses
3351system.l2c.UpgradeReq_miss_rate::cpu1.data 0.587728 # miss rate for UpgradeReq accesses
3352system.l2c.UpgradeReq_miss_rate::total 0.598116 # miss rate for UpgradeReq accesses
3353system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.615430 # miss rate for SCUpgradeReq accesses
3354system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.590919 # miss rate for SCUpgradeReq accesses
3355system.l2c.SCUpgradeReq_miss_rate::total 0.604223 # miss rate for SCUpgradeReq accesses
3356system.l2c.ReadExReq_miss_rate::cpu0.data 0.618848 # miss rate for ReadExReq accesses
3357system.l2c.ReadExReq_miss_rate::cpu1.data 0.494171 # miss rate for ReadExReq accesses
3358system.l2c.ReadExReq_miss_rate::total 0.565564 # miss rate for ReadExReq accesses
3359system.l2c.demand_miss_rate::cpu0.dtb.walker 0.278972 # miss rate for demand accesses
3360system.l2c.demand_miss_rate::cpu0.itb.walker 0.346299 # miss rate for demand accesses
3361system.l2c.demand_miss_rate::cpu0.inst 0.087709 # miss rate for demand accesses
3362system.l2c.demand_miss_rate::cpu0.data 0.263890 # miss rate for demand accesses
3363system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.506634 # miss rate for demand accesses
3364system.l2c.demand_miss_rate::cpu1.dtb.walker 0.310635 # miss rate for demand accesses
3365system.l2c.demand_miss_rate::cpu1.itb.walker 0.376754 # miss rate for demand accesses
3366system.l2c.demand_miss_rate::cpu1.inst 0.089771 # miss rate for demand accesses
3367system.l2c.demand_miss_rate::cpu1.data 0.233923 # miss rate for demand accesses
3368system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.448841 # miss rate for demand accesses
3369system.l2c.demand_miss_rate::total 0.262435 # miss rate for demand accesses
3370system.l2c.overall_miss_rate::cpu0.dtb.walker 0.278972 # miss rate for overall accesses
3371system.l2c.overall_miss_rate::cpu0.itb.walker 0.346299 # miss rate for overall accesses
3372system.l2c.overall_miss_rate::cpu0.inst 0.087709 # miss rate for overall accesses
3373system.l2c.overall_miss_rate::cpu0.data 0.263890 # miss rate for overall accesses
3374system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.506634 # miss rate for overall accesses
3375system.l2c.overall_miss_rate::cpu1.dtb.walker 0.310635 # miss rate for overall accesses
3376system.l2c.overall_miss_rate::cpu1.itb.walker 0.376754 # miss rate for overall accesses
3377system.l2c.overall_miss_rate::cpu1.inst 0.089771 # miss rate for overall accesses
3378system.l2c.overall_miss_rate::cpu1.data 0.233923 # miss rate for overall accesses
3379system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.448841 # miss rate for overall accesses
3380system.l2c.overall_miss_rate::total 0.262435 # miss rate for overall accesses
3381system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 85101.568308 # average ReadReq miss latency
3382system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 86813.154283 # average ReadReq miss latency
3383system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80393.193733 # average ReadReq miss latency
3384system.l2c.ReadReq_avg_miss_latency::cpu0.data 94839.459967 # average ReadReq miss latency
3385system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 152868.475159 # average ReadReq miss latency
3386system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87681.670463 # average ReadReq miss latency
3387system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89059.019640 # average ReadReq miss latency
3388system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80261.557104 # average ReadReq miss latency
3389system.l2c.ReadReq_avg_miss_latency::cpu1.data 97242.091561 # average ReadReq miss latency
3390system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 146336.775252 # average ReadReq miss latency
3391system.l2c.ReadReq_avg_miss_latency::total 124447.736262 # average ReadReq miss latency
3392system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 77.724572 # average WriteInvalidateReq miss latency
3393system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 409.780072 # average WriteInvalidateReq miss latency
3394system.l2c.WriteInvalidateReq_avg_miss_latency::total 132.138496 # average WriteInvalidateReq miss latency
3395system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 4296.060156 # average UpgradeReq miss latency
3396system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4600.594946 # average UpgradeReq miss latency
3397system.l2c.UpgradeReq_avg_miss_latency::total 4446.091464 # average UpgradeReq miss latency
3398system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3825.447903 # average SCUpgradeReq miss latency
3399system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4271.781080 # average SCUpgradeReq miss latency
3400system.l2c.SCUpgradeReq_avg_miss_latency::total 4025.031237 # average SCUpgradeReq miss latency
3401system.l2c.ReadExReq_avg_miss_latency::cpu0.data 88845.110038 # average ReadExReq miss latency
3402system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81928.046416 # average ReadExReq miss latency
3403system.l2c.ReadExReq_avg_miss_latency::total 86262.105583 # average ReadExReq miss latency
3404system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85101.568308 # average overall miss latency
3405system.l2c.demand_avg_miss_latency::cpu0.itb.walker 86813.154283 # average overall miss latency
3406system.l2c.demand_avg_miss_latency::cpu0.inst 80393.193733 # average overall miss latency
3407system.l2c.demand_avg_miss_latency::cpu0.data 92758.248191 # average overall miss latency
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3409system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87681.670463 # average overall miss latency
3410system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89059.019640 # average overall miss latency
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3417system.l2c.overall_avg_miss_latency::cpu0.inst 80393.193733 # average overall miss latency
3418system.l2c.overall_avg_miss_latency::cpu0.data 92758.248191 # average overall miss latency
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3420system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87681.670463 # average overall miss latency
3421system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89059.019640 # average overall miss latency
3422system.l2c.overall_avg_miss_latency::cpu1.inst 80261.557104 # average overall miss latency
3423system.l2c.overall_avg_miss_latency::cpu1.data 92864.390481 # average overall miss latency
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3425system.l2c.overall_avg_miss_latency::total 119602.960979 # average overall miss latency
3426system.l2c.blocked_cycles::no_mshrs 13381 # number of cycles access was blocked
3427system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
3428system.l2c.blocked::no_mshrs 234 # number of cycles access was blocked
3429system.l2c.blocked::no_targets 0 # number of cycles access was blocked
3430system.l2c.avg_blocked_cycles::no_mshrs 57.183761 # average number of cycles each access was blocked
3431system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3432system.l2c.fast_writes 0 # number of fast writes performed
3433system.l2c.cache_copies 0 # number of cache copies performed
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3435system.l2c.writebacks::total 1241010 # number of writebacks
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3511system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 479520804 # number of UpgradeReq MSHR miss cycles
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3514system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 85816866 # number of SCUpgradeReq MSHR miss cycles
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3544system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 616502003 # number of ReadReq MSHR uncacheable cycles
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3546system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4542606997 # number of WriteReq MSHR uncacheable cycles
3547system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 728363997 # number of WriteReq MSHR uncacheable cycles
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3550system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9293179493 # number of overall MSHR uncacheable cycles
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3552system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1344866000 # number of overall MSHR uncacheable cycles
3553system.l2c.overall_mshr_uncacheable_latency::total 11745150993 # number of overall MSHR uncacheable cycles
3554system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.278972 # mshr miss rate for ReadReq accesses
3555system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.346299 # mshr miss rate for ReadReq accesses
3556system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.087381 # mshr miss rate for ReadReq accesses
3557system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.202122 # mshr miss rate for ReadReq accesses
3558system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.506634 # mshr miss rate for ReadReq accesses
3559system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.310635 # mshr miss rate for ReadReq accesses
3560system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.376754 # mshr miss rate for ReadReq accesses
3561system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.089424 # mshr miss rate for ReadReq accesses
3562system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.193073 # mshr miss rate for ReadReq accesses
3563system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448841 # mshr miss rate for ReadReq accesses
3564system.l2c.ReadReq_mshr_miss_rate::total 0.243324 # mshr miss rate for ReadReq accesses
3565system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.779565 # mshr miss rate for WriteInvalidateReq accesses
3566system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.438283 # mshr miss rate for WriteInvalidateReq accesses
3567system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.691347 # mshr miss rate for WriteInvalidateReq accesses
3568system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.608561 # mshr miss rate for UpgradeReq accesses
3569system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.587728 # mshr miss rate for UpgradeReq accesses
3570system.l2c.UpgradeReq_mshr_miss_rate::total 0.598116 # mshr miss rate for UpgradeReq accesses
3571system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.615430 # mshr miss rate for SCUpgradeReq accesses
3572system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.590919 # mshr miss rate for SCUpgradeReq accesses
3573system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.604223 # mshr miss rate for SCUpgradeReq accesses
3574system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.618848 # mshr miss rate for ReadExReq accesses
3575system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.494171 # mshr miss rate for ReadExReq accesses
3576system.l2c.ReadExReq_mshr_miss_rate::total 0.565564 # mshr miss rate for ReadExReq accesses
3577system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.278972 # mshr miss rate for demand accesses
3578system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.346299 # mshr miss rate for demand accesses
3579system.l2c.demand_mshr_miss_rate::cpu0.inst 0.087381 # mshr miss rate for demand accesses
3580system.l2c.demand_mshr_miss_rate::cpu0.data 0.263819 # mshr miss rate for demand accesses
3581system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.506634 # mshr miss rate for demand accesses
3582system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.310635 # mshr miss rate for demand accesses
3583system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.376754 # mshr miss rate for demand accesses
3584system.l2c.demand_mshr_miss_rate::cpu1.inst 0.089424 # mshr miss rate for demand accesses
3585system.l2c.demand_mshr_miss_rate::cpu1.data 0.233817 # mshr miss rate for demand accesses
3586system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448841 # mshr miss rate for demand accesses
3587system.l2c.demand_mshr_miss_rate::total 0.262295 # mshr miss rate for demand accesses
3588system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.278972 # mshr miss rate for overall accesses
3589system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.346299 # mshr miss rate for overall accesses
3590system.l2c.overall_mshr_miss_rate::cpu0.inst 0.087381 # mshr miss rate for overall accesses
3591system.l2c.overall_mshr_miss_rate::cpu0.data 0.263819 # mshr miss rate for overall accesses
3592system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.506634 # mshr miss rate for overall accesses
3593system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.310635 # mshr miss rate for overall accesses
3594system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.376754 # mshr miss rate for overall accesses
3595system.l2c.overall_mshr_miss_rate::cpu1.inst 0.089424 # mshr miss rate for overall accesses
3596system.l2c.overall_mshr_miss_rate::cpu1.data 0.233817 # mshr miss rate for overall accesses
3597system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448841 # mshr miss rate for overall accesses
3598system.l2c.overall_mshr_miss_rate::total 0.262295 # mshr miss rate for overall accesses
3599system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 72610.305401 # average ReadReq mshr miss latency
3600system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 74335.007430 # average ReadReq mshr miss latency
3601system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67911.455258 # average ReadReq mshr miss latency
3602system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 82417.381349 # average ReadReq mshr miss latency
3603system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140724.568925 # average ReadReq mshr miss latency
3604system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75197.862633 # average ReadReq mshr miss latency
3605system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76589.297872 # average ReadReq mshr miss latency
3606system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67772.830989 # average ReadReq mshr miss latency
3607system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 84846.955925 # average ReadReq mshr miss latency
3608system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134178.399201 # average ReadReq mshr miss latency
3609system.l2c.ReadReq_avg_mshr_miss_latency::total 112198.907686 # average ReadReq mshr miss latency
3610system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 48918.341561 # average WriteInvalidateReq mshr miss latency
3611system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27337.914593 # average WriteInvalidateReq mshr miss latency
3612system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 45381.957713 # average WriteInvalidateReq mshr miss latency
3613system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10183.407896 # average UpgradeReq mshr miss latency
3614system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10261.080288 # average UpgradeReq mshr miss latency
3615system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10221.673772 # average UpgradeReq mshr miss latency
3616system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10188.880770 # average SCUpgradeReq mshr miss latency
3617system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10160.651906 # average SCUpgradeReq mshr miss latency
3618system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10176.257889 # average SCUpgradeReq mshr miss latency
3619system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76299.327310 # average ReadExReq mshr miss latency
3620system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69458.395878 # average ReadExReq mshr miss latency
3621system.l2c.ReadExReq_avg_mshr_miss_latency::total 73744.752518 # average ReadExReq mshr miss latency
3622system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 72610.305401 # average overall mshr miss latency
3623system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74335.007430 # average overall mshr miss latency
3624system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67911.455258 # average overall mshr miss latency
3625system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80292.648521 # average overall mshr miss latency
3626system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140724.568925 # average overall mshr miss latency
3627system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75197.862633 # average overall mshr miss latency
3628system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76589.297872 # average overall mshr miss latency
3629system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67772.830989 # average overall mshr miss latency
3630system.l2c.demand_avg_mshr_miss_latency::cpu1.data 80445.957655 # average overall mshr miss latency
3631system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134178.399201 # average overall mshr miss latency
3632system.l2c.demand_avg_mshr_miss_latency::total 107317.450557 # average overall mshr miss latency
3633system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 72610.305401 # average overall mshr miss latency
3634system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74335.007430 # average overall mshr miss latency
3635system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67911.455258 # average overall mshr miss latency
3636system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80292.648521 # average overall mshr miss latency
3637system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140724.568925 # average overall mshr miss latency
3638system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75197.862633 # average overall mshr miss latency
3639system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76589.297872 # average overall mshr miss latency
3640system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67772.830989 # average overall mshr miss latency
3641system.l2c.overall_avg_mshr_miss_latency::cpu1.data 80445.957655 # average overall mshr miss latency
3642system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134178.399201 # average overall mshr miss latency
3643system.l2c.overall_avg_mshr_miss_latency::total 107317.450557 # average overall mshr miss latency
3644system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
3645system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
3646system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
3647system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
3648system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
3649system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
3650system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
3651system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
3652system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
3653system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
3654system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
3655system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
3656system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
3657system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
3658system.membus.trans_dist::ReadReq 1032278 # Transaction distribution
3659system.membus.trans_dist::ReadResp 1032278 # Transaction distribution
3660system.membus.trans_dist::WriteReq 38581 # Transaction distribution
3661system.membus.trans_dist::WriteResp 38581 # Transaction distribution
3662system.membus.trans_dist::Writeback 1347712 # Transaction distribution
3663system.membus.trans_dist::WriteInvalidateReq 689975 # Transaction distribution
3664system.membus.trans_dist::WriteInvalidateResp 689975 # Transaction distribution
3665system.membus.trans_dist::UpgradeReq 447979 # Transaction distribution
3666system.membus.trans_dist::SCUpgradeReq 332386 # Transaction distribution
3667system.membus.trans_dist::UpgradeResp 121150 # Transaction distribution
3668system.membus.trans_dist::ReadExReq 152231 # Transaction distribution
3669system.membus.trans_dist::ReadExResp 135895 # Transaction distribution
3670system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123088 # Packet count per connected master and slave (bytes)
3671system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes)
3672system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25972 # Packet count per connected master and slave (bytes)
3673system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5571157 # Packet count per connected master and slave (bytes)
3674system.membus.pkt_count_system.l2c.mem_side::total 5720295 # Packet count per connected master and slave (bytes)
3675system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335903 # Packet count per connected master and slave (bytes)
3676system.membus.pkt_count_system.iocache.mem_side::total 335903 # Packet count per connected master and slave (bytes)
3677system.membus.pkt_count::total 6056198 # Packet count per connected master and slave (bytes)
3678system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156195 # Cumulative packet size per connected master and slave (bytes)
3679system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes)
3680system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51944 # Cumulative packet size per connected master and slave (bytes)
3681system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 187423448 # Cumulative packet size per connected master and slave (bytes)
3682system.membus.pkt_size_system.l2c.mem_side::total 187632159 # Cumulative packet size per connected master and slave (bytes)
3683system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14096832 # Cumulative packet size per connected master and slave (bytes)
3684system.membus.pkt_size_system.iocache.mem_side::total 14096832 # Cumulative packet size per connected master and slave (bytes)
3685system.membus.pkt_size::total 201728991 # Cumulative packet size per connected master and slave (bytes)
3686system.membus.snoops 678374 # Total snoops (count)
3687system.membus.snoop_fanout::samples 3943213 # Request fanout histogram
3688system.membus.snoop_fanout::mean 1 # Request fanout histogram
3689system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3690system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3691system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3692system.membus.snoop_fanout::1 3943213 100.00% 100.00% # Request fanout histogram
3693system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3694system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3695system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3696system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3697system.membus.snoop_fanout::total 3943213 # Request fanout histogram
3698system.membus.reqLayer0.occupancy 98700492 # Layer occupancy (ticks)
3699system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3700system.membus.reqLayer1.occupancy 45500 # Layer occupancy (ticks)
3701system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3702system.membus.reqLayer2.occupancy 21600991 # Layer occupancy (ticks)
3703system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3704system.membus.reqLayer5.occupancy 19952700228 # Layer occupancy (ticks)
3705system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3706system.membus.respLayer2.occupancy 11115498245 # Layer occupancy (ticks)
3707system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3708system.membus.respLayer3.occupancy 187180539 # Layer occupancy (ticks)
3709system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3710system.realview.ethernet.txBytes 966 # Bytes Transmitted
3711system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3712system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3713system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3714system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3715system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3716system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA

--- 27 unchanged lines hidden (view full) ---

3744system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
3745system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3746system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3747system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
3748system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3749system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3750system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3751system.realview.ethernet.droppedPackets 0 # number of packets dropped
3752system.toL2Bus.trans_dist::ReadReq 4932840 # Transaction distribution
3753system.toL2Bus.trans_dist::ReadResp 4925609 # Transaction distribution
3754system.toL2Bus.trans_dist::WriteReq 38581 # Transaction distribution
3755system.toL2Bus.trans_dist::WriteResp 38581 # Transaction distribution
3756system.toL2Bus.trans_dist::Writeback 2564009 # Transaction distribution
3757system.toL2Bus.trans_dist::WriteInvalidateReq 955023 # Transaction distribution
3758system.toL2Bus.trans_dist::WriteInvalidateResp 848293 # Transaction distribution
3759system.toL2Bus.trans_dist::UpgradeReq 504313 # Transaction distribution
3760system.toL2Bus.trans_dist::SCUpgradeReq 344758 # Transaction distribution
3761system.toL2Bus.trans_dist::UpgradeResp 849071 # Transaction distribution
3762system.toL2Bus.trans_dist::SCUpgradeFailReq 157 # Transaction distribution
3763system.toL2Bus.trans_dist::UpgradeFailResp 157 # Transaction distribution
3764system.toL2Bus.trans_dist::ReadExReq 306644 # Transaction distribution
3765system.toL2Bus.trans_dist::ReadExResp 306644 # Transaction distribution
3766system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8600677 # Packet count per connected master and slave (bytes)
3767system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6275419 # Packet count per connected master and slave (bytes)
3768system.toL2Bus.pkt_count::total 14876096 # Packet count per connected master and slave (bytes)
3769system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 289885704 # Cumulative packet size per connected master and slave (bytes)
3770system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 198430935 # Cumulative packet size per connected master and slave (bytes)
3771system.toL2Bus.pkt_size::total 488316639 # Cumulative packet size per connected master and slave (bytes)
3772system.toL2Bus.snoops 1740265 # Total snoops (count)
3773system.toL2Bus.snoop_fanout::samples 9550575 # Request fanout histogram
3774system.toL2Bus.snoop_fanout::mean 1.012108 # Request fanout histogram
3775system.toL2Bus.snoop_fanout::stdev 0.109370 # Request fanout histogram
3776system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3777system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3778system.toL2Bus.snoop_fanout::1 9434933 98.79% 98.79% # Request fanout histogram
3779system.toL2Bus.snoop_fanout::2 115642 1.21% 100.00% # Request fanout histogram
3780system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3781system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
3782system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3783system.toL2Bus.snoop_fanout::total 9550575 # Request fanout histogram
3784system.toL2Bus.reqLayer0.occupancy 18722164156 # Layer occupancy (ticks)
3785system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3786system.toL2Bus.snoopLayer0.occupancy 7552500 # Layer occupancy (ticks)
3787system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3788system.toL2Bus.respLayer0.occupancy 13115425494 # Layer occupancy (ticks)
3789system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3790system.toL2Bus.respLayer1.occupancy 11201753623 # Layer occupancy (ticks)
3791system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3792system.cpu0.kern.inst.arm 0 # number of arm instructions executed
3793system.cpu0.kern.inst.quiesce 13602 # number of quiesce instructions executed
3794system.cpu1.kern.inst.arm 0 # number of arm instructions executed
3795system.cpu1.kern.inst.quiesce 5345 # number of quiesce instructions executed
3796
3797---------- End Simulation Statistics ----------