1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.379675 # Number of seconds simulated
4sim_ticks 47379674621500 # Number of ticks simulated
5final_tick 47379674621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 105231 # Simulator instruction rate (inst/s)
8host_op_rate 123773 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 5339286706 # Simulator tick rate (ticks/s)
10host_mem_usage 910192 # Number of bytes of host memory used
11host_seconds 8873.78 # Real time elapsed on the host
12sim_insts 933798389 # Number of instructions simulated
13sim_ops 1098335322 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 353088 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 523648 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 1152800 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 18354072 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 38298624 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 338240 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 462784 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 532064 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 12967328 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 29162240 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 472128 # Number of bytes read from this memory
27system.physmem.bytes_read::total 102617016 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 1152800 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 532064 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 1684864 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 56488832 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 66623564 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 34275268 # Number of bytes written to this memory
34system.physmem.bytes_written::realview.ide 6830592 # Number of bytes written to this memory
35system.physmem.bytes_written::total 164218256 # Number of bytes written to this memory
36system.physmem.num_reads::cpu0.dtb.walker 5517 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.itb.walker 8182 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.inst 33965 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.data 286804 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu0.l2cache.prefetcher 598416 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.dtb.walker 5285 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.itb.walker 7231 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.inst 8357 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.data 202629 # Number of read requests responded to by this memory
45system.physmem.num_reads::cpu1.l2cache.prefetcher 455660 # Number of read requests responded to by this memory
46system.physmem.num_reads::realview.ide 7377 # Number of read requests responded to by this memory
47system.physmem.num_reads::total 1619423 # Number of read requests responded to by this memory
48system.physmem.num_writes::writebacks 882638 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu0.data 1043270 # Number of write requests responded to by this memory
50system.physmem.num_writes::cpu1.data 535552 # Number of write requests responded to by this memory
51system.physmem.num_writes::realview.ide 106728 # Number of write requests responded to by this memory
52system.physmem.num_writes::total 2568188 # Number of write requests responded to by this memory
53system.physmem.bw_read::cpu0.dtb.walker 7452 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.itb.walker 11052 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.inst 24331 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu0.data 387383 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu0.l2cache.prefetcher 808334 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.dtb.walker 7139 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.itb.walker 9768 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.inst 11230 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::cpu1.data 273690 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::cpu1.l2cache.prefetcher 615501 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_read::realview.ide 9965 # Total read bandwidth from this memory (bytes/s)
64system.physmem.bw_read::total 2165845 # Total read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::cpu0.inst 24331 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_inst_read::cpu1.inst 11230 # Instruction read bandwidth from this memory (bytes/s)
67system.physmem.bw_inst_read::total 35561 # Instruction read bandwidth from this memory (bytes/s)
68system.physmem.bw_write::writebacks 1192259 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::cpu0.data 1406163 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_write::cpu1.data 723417 # Write bandwidth from this memory (bytes/s)
71system.physmem.bw_write::realview.ide 144167 # Write bandwidth from this memory (bytes/s)
72system.physmem.bw_write::total 3466006 # Write bandwidth from this memory (bytes/s)
73system.physmem.bw_total::writebacks 1192259 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.dtb.walker 7452 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.itb.walker 11052 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu0.inst 24331 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu0.data 1793546 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu0.l2cache.prefetcher 808334 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.dtb.walker 7139 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.itb.walker 9768 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::cpu1.inst 11230 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::cpu1.data 997107 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.bw_total::cpu1.l2cache.prefetcher 615501 # Total bandwidth to/from this memory (bytes/s)
84system.physmem.bw_total::realview.ide 154132 # Total bandwidth to/from this memory (bytes/s)
85system.physmem.bw_total::total 5631851 # Total bandwidth to/from this memory (bytes/s)
86system.physmem.readReqs 1619423 # Number of read requests accepted
87system.physmem.writeReqs 2568188 # Number of write requests accepted
88system.physmem.readBursts 1619423 # Number of DRAM read bursts, including those serviced by the write queue
89system.physmem.writeBursts 2568188 # Number of DRAM write bursts, including those merged in the write queue
90system.physmem.bytesReadDRAM 103371328 # Total number of bytes read from DRAM
91system.physmem.bytesReadWrQ 271744 # Total number of bytes read from write queue
92system.physmem.bytesWritten 158872640 # Total number of bytes written to DRAM
93system.physmem.bytesReadSys 102617016 # Total read bytes from the system interface side
94system.physmem.bytesWrittenSys 164218256 # Total written bytes from the system interface side
95system.physmem.servicedByWrQ 4246 # Number of DRAM read bursts serviced by the write queue
96system.physmem.mergedWrBursts 85771 # Number of DRAM write bursts merged with an existing one
97system.physmem.neitherReadNorWriteReqs 103144 # Number of requests that are neither read nor write
98system.physmem.perBankRdBursts::0 111705 # Per bank write bursts
99system.physmem.perBankRdBursts::1 107185 # Per bank write bursts
100system.physmem.perBankRdBursts::2 95216 # Per bank write bursts
101system.physmem.perBankRdBursts::3 93593 # Per bank write bursts
102system.physmem.perBankRdBursts::4 97040 # Per bank write bursts
103system.physmem.perBankRdBursts::5 109538 # Per bank write bursts
104system.physmem.perBankRdBursts::6 103640 # Per bank write bursts
105system.physmem.perBankRdBursts::7 104459 # Per bank write bursts
106system.physmem.perBankRdBursts::8 87345 # Per bank write bursts
107system.physmem.perBankRdBursts::9 119689 # Per bank write bursts
108system.physmem.perBankRdBursts::10 87550 # Per bank write bursts
109system.physmem.perBankRdBursts::11 102455 # Per bank write bursts
110system.physmem.perBankRdBursts::12 98167 # Per bank write bursts
111system.physmem.perBankRdBursts::13 96293 # Per bank write bursts
112system.physmem.perBankRdBursts::14 97699 # Per bank write bursts
113system.physmem.perBankRdBursts::15 103603 # Per bank write bursts
114system.physmem.perBankWrBursts::0 151797 # Per bank write bursts
115system.physmem.perBankWrBursts::1 157102 # Per bank write bursts
116system.physmem.perBankWrBursts::2 173467 # Per bank write bursts
117system.physmem.perBankWrBursts::3 129226 # Per bank write bursts
118system.physmem.perBankWrBursts::4 217724 # Per bank write bursts
119system.physmem.perBankWrBursts::5 151423 # Per bank write bursts
120system.physmem.perBankWrBursts::6 153455 # Per bank write bursts
121system.physmem.perBankWrBursts::7 181552 # Per bank write bursts
122system.physmem.perBankWrBursts::8 127836 # Per bank write bursts
123system.physmem.perBankWrBursts::9 166575 # Per bank write bursts
124system.physmem.perBankWrBursts::10 140595 # Per bank write bursts
125system.physmem.perBankWrBursts::11 139064 # Per bank write bursts
126system.physmem.perBankWrBursts::12 135611 # Per bank write bursts
127system.physmem.perBankWrBursts::13 129688 # Per bank write bursts
128system.physmem.perBankWrBursts::14 173219 # Per bank write bursts
129system.physmem.perBankWrBursts::15 154051 # Per bank write bursts
130system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
131system.physmem.numWrRetry 280 # Number of times write queue was full causing retry
132system.physmem.totGap 47379673169000 # Total gap between requests
133system.physmem.readPktSize::0 0 # Read request sizes (log2)
134system.physmem.readPktSize::1 0 # Read request sizes (log2)
135system.physmem.readPktSize::2 0 # Read request sizes (log2)
136system.physmem.readPktSize::3 37 # Read request sizes (log2)
137system.physmem.readPktSize::4 21333 # Read request sizes (log2)
138system.physmem.readPktSize::5 0 # Read request sizes (log2)
139system.physmem.readPktSize::6 1598053 # Read request sizes (log2)
140system.physmem.writePktSize::0 0 # Write request sizes (log2)
141system.physmem.writePktSize::1 0 # Write request sizes (log2)
142system.physmem.writePktSize::2 2 # Write request sizes (log2)
143system.physmem.writePktSize::3 2601 # Write request sizes (log2)
144system.physmem.writePktSize::4 0 # Write request sizes (log2)
145system.physmem.writePktSize::5 0 # Write request sizes (log2)
146system.physmem.writePktSize::6 2565585 # Write request sizes (log2)
147system.physmem.rdQLenPdf::0 575288 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::1 378276 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::2 198870 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::3 124070 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::4 84552 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::5 66107 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::6 57559 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::7 49842 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::8 42131 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::9 14414 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::10 7965 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::11 5242 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::12 3374 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::13 2598 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::14 1882 # What read queue length does an incoming req see
162system.physmem.rdQLenPdf::15 1439 # What read queue length does an incoming req see
163system.physmem.rdQLenPdf::16 715 # What read queue length does an incoming req see
164system.physmem.rdQLenPdf::17 512 # What read queue length does an incoming req see
165system.physmem.rdQLenPdf::18 199 # What read queue length does an incoming req see
166system.physmem.rdQLenPdf::19 135 # What read queue length does an incoming req see
167system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see
168system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
169system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
170system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
171system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
172system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
173system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
174system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
175system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
176system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
177system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
178system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
179system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::15 50077 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::16 80336 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::17 91349 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::18 103691 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::19 113552 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::20 135687 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::21 144994 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::22 161556 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::23 168861 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::24 188844 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::25 173768 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::26 166459 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::27 153274 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::28 157126 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::29 123678 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::30 118188 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::31 114281 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::32 106686 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::33 15195 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::34 11268 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::35 9055 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::36 7628 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::37 7057 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::38 6378 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::39 5840 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::40 5400 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::41 5192 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::42 4660 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::43 4389 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::44 4093 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::45 4040 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::46 3814 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::47 3583 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::48 3430 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::49 3546 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::50 3135 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::51 3036 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::52 2997 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::53 2927 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::54 2444 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::55 2152 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::56 1911 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::57 1704 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::58 1382 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::59 1113 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::60 878 # What write queue length does an incoming req see
240system.physmem.wrQLenPdf::61 602 # What write queue length does an incoming req see
241system.physmem.wrQLenPdf::62 472 # What write queue length does an incoming req see
242system.physmem.wrQLenPdf::63 674 # What write queue length does an incoming req see
243system.physmem.bytesPerActivate::samples 968355 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::mean 270.813741 # Bytes accessed per row activation
245system.physmem.bytesPerActivate::gmean 146.322670 # Bytes accessed per row activation
246system.physmem.bytesPerActivate::stdev 334.242545 # Bytes accessed per row activation
247system.physmem.bytesPerActivate::0-127 500729 51.71% 51.71% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::128-255 182951 18.89% 70.60% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::256-383 62910 6.50% 77.10% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::384-511 30320 3.13% 80.23% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::512-639 27676 2.86% 83.09% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::640-767 15651 1.62% 84.70% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::768-895 12433 1.28% 85.99% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::896-1023 15606 1.61% 87.60% # Bytes accessed per row activation
255system.physmem.bytesPerActivate::1024-1151 120079 12.40% 100.00% # Bytes accessed per row activation
256system.physmem.bytesPerActivate::total 968355 # Bytes accessed per row activation
257system.physmem.rdPerTurnAround::samples 90300 # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::mean 17.886467 # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::stdev 201.343157 # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::0-2047 90297 100.00% 100.00% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
262system.physmem.rdPerTurnAround::14336-16383 1 0.00% 100.00% # Reads before turning the bus around for writes
263system.physmem.rdPerTurnAround::57344-59391 1 0.00% 100.00% # Reads before turning the bus around for writes
264system.physmem.rdPerTurnAround::total 90300 # Reads before turning the bus around for writes
265system.physmem.wrPerTurnAround::samples 90300 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::mean 27.490421 # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::gmean 23.640759 # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::stdev 19.748039 # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::16-23 56859 62.97% 62.97% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::24-31 8057 8.92% 71.89% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::32-39 12273 13.59% 85.48% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::40-47 3990 4.42% 89.90% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::48-55 1898 2.10% 92.00% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::56-63 944 1.05% 93.05% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::64-71 2681 2.97% 96.02% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::72-79 1258 1.39% 97.41% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::80-87 729 0.81% 98.22% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::88-95 233 0.26% 98.47% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::96-103 328 0.36% 98.84% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::104-111 174 0.19% 99.03% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::112-119 473 0.52% 99.55% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::120-127 16 0.02% 99.57% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::128-135 44 0.05% 99.62% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::136-143 33 0.04% 99.66% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::144-151 16 0.02% 99.67% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::152-159 34 0.04% 99.71% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::160-167 77 0.09% 99.80% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::168-175 57 0.06% 99.86% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::176-183 40 0.04% 99.90% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::184-191 6 0.01% 99.91% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::192-199 21 0.02% 99.93% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::208-215 22 0.02% 99.96% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::216-223 2 0.00% 99.96% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::224-231 4 0.00% 99.97% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::232-239 3 0.00% 99.97% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::240-247 7 0.01% 99.98% # Writes before turning the bus around for reads
297system.physmem.wrPerTurnAround::248-255 9 0.01% 99.99% # Writes before turning the bus around for reads
298system.physmem.wrPerTurnAround::256-263 3 0.00% 99.99% # Writes before turning the bus around for reads
299system.physmem.wrPerTurnAround::264-271 6 0.01% 100.00% # Writes before turning the bus around for reads
300system.physmem.wrPerTurnAround::272-279 3 0.00% 100.00% # Writes before turning the bus around for reads
301system.physmem.wrPerTurnAround::total 90300 # Writes before turning the bus around for reads
302system.physmem.totQLat 65880977516 # Total ticks spent queuing
303system.physmem.totMemAccLat 96165546266 # Total ticks spent from burst creation until serviced by the DRAM
304system.physmem.totBusLat 8075885000 # Total ticks spent in databus transfers
305system.physmem.avgQLat 40788.70 # Average queueing delay per DRAM burst
306system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
307system.physmem.avgMemAccLat 59538.70 # Average memory access latency per DRAM burst
308system.physmem.avgRdBW 2.18 # Average DRAM read bandwidth in MiByte/s
309system.physmem.avgWrBW 3.35 # Average achieved write bandwidth in MiByte/s
310system.physmem.avgRdBWSys 2.17 # Average system read bandwidth in MiByte/s
311system.physmem.avgWrBWSys 3.47 # Average system write bandwidth in MiByte/s
312system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
313system.physmem.busUtil 0.04 # Data bus utilization in percentage
314system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
315system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
316system.physmem.avgRdQLen 3.63 # Average read queue length when enqueuing
317system.physmem.avgWrQLen 25.06 # Average write queue length when enqueuing
318system.physmem.readRowHits 1266207 # Number of row buffer hits during reads
319system.physmem.writeRowHits 1862998 # Number of row buffer hits during writes
320system.physmem.readRowHitRate 78.39 # Row buffer hit rate for reads
321system.physmem.writeRowHitRate 75.05 # Row buffer hit rate for writes
322system.physmem.avgGap 11314248.90 # Average gap between requests
323system.physmem.pageHitRate 76.37 # Row buffer hit rate, read and write combined
324system.physmem.memoryStateTime::IDLE 45458713155000 # Time in different power states
325system.physmem.memoryStateTime::REF 1582111440000 # Time in different power states
326system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
327system.physmem.memoryStateTime::ACT 338849669500 # Time in different power states
328system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
329system.physmem.actEnergy::0 3771472320 # Energy for activate commands per rank (pJ)
330system.physmem.actEnergy::1 3549283920 # Energy for activate commands per rank (pJ)
331system.physmem.preEnergy::0 2057847000 # Energy for precharge commands per rank (pJ)
332system.physmem.preEnergy::1 1936613250 # Energy for precharge commands per rank (pJ)
333system.physmem.readEnergy::0 6414501600 # Energy for read commands per rank (pJ)
334system.physmem.readEnergy::1 6183847800 # Energy for read commands per rank (pJ)
335system.physmem.writeEnergy::0 8526034080 # Energy for write commands per rank (pJ)
336system.physmem.writeEnergy::1 7559820720 # Energy for write commands per rank (pJ)
337system.physmem.refreshEnergy::0 3094609976640 # Energy for refresh commands per rank (pJ)
338system.physmem.refreshEnergy::1 3094609976640 # Energy for refresh commands per rank (pJ)
339system.physmem.actBackEnergy::0 1215510046335 # Energy for active background per rank (pJ)
340system.physmem.actBackEnergy::1 1201972779180 # Energy for active background per rank (pJ)
341system.physmem.preBackEnergy::0 27361567580250 # Energy for precharge background per rank (pJ)
342system.physmem.preBackEnergy::1 27373442376000 # Energy for precharge background per rank (pJ)
343system.physmem.totalEnergy::0 31692457458225 # Total energy per rank (pJ)
344system.physmem.totalEnergy::1 31689254697510 # Total energy per rank (pJ)
345system.physmem.averagePower::0 668.904083 # Core power per rank (mW)
346system.physmem.averagePower::1 668.836485 # Core power per rank (mW)
347system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory
348system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
349system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
350system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
351system.realview.nvmem.bytes_read::total 572 # Number of bytes read from this memory
352system.realview.nvmem.bytes_inst_read::cpu0.inst 384 # Number of instructions bytes read from this memory
353system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory
354system.realview.nvmem.bytes_inst_read::total 528 # Number of instructions bytes read from this memory

--- 16 unchanged lines hidden (view full) ---

371system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
372system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
373system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
374system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
375system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
376system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
377system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
378system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
379system.cpu0.branchPred.lookups 146587108 # Number of BP lookups
380system.cpu0.branchPred.condPredicted 96932064 # Number of conditional branches predicted
381system.cpu0.branchPred.condIncorrect 7164901 # Number of conditional branches incorrect
382system.cpu0.branchPred.BTBLookups 103453764 # Number of BTB lookups
383system.cpu0.branchPred.BTBHits 67642054 # Number of BTB hits
384system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
385system.cpu0.branchPred.BTBHitPct 65.383850 # BTB Hit Percentage
386system.cpu0.branchPred.usedRAS 20270932 # Number of times the RAS was used to get a target.
387system.cpu0.branchPred.RASInCorrect 203679 # Number of incorrect RAS predictions.
388system.cpu_clk_domain.clock 500 # Clock period in ticks
389system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
390system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
391system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
392system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
393system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
394system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
395system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed

--- 8 unchanged lines hidden (view full) ---

404system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
405system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
406system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
407system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
408system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
409system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
410system.cpu0.dtb.inst_hits 0 # ITB inst hits
411system.cpu0.dtb.inst_misses 0 # ITB inst misses
412system.cpu0.dtb.read_hits 106134781 # DTB read hits
413system.cpu0.dtb.read_misses 438400 # DTB read misses
414system.cpu0.dtb.write_hits 87107060 # DTB write hits
415system.cpu0.dtb.write_misses 166320 # DTB write misses
416system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
417system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
418system.cpu0.dtb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID
419system.cpu0.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID
420system.cpu0.dtb.flush_entries 41289 # Number of entries that have been flushed from TLB
421system.cpu0.dtb.align_faults 449 # Number of TLB faults due to alignment restrictions
422system.cpu0.dtb.prefetch_faults 7213 # Number of TLB faults due to prefetch
423system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
424system.cpu0.dtb.perms_faults 39737 # Number of TLB faults due to permissions restrictions
425system.cpu0.dtb.read_accesses 106573181 # DTB read accesses
426system.cpu0.dtb.write_accesses 87273380 # DTB write accesses
427system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
428system.cpu0.dtb.hits 193241841 # DTB hits
429system.cpu0.dtb.misses 604720 # DTB misses
430system.cpu0.dtb.accesses 193846561 # DTB accesses
431system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
432system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
433system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
434system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
435system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
436system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
437system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
438system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 5 unchanged lines hidden (view full) ---

444system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
445system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
446system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
447system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
448system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
449system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
450system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
451system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
452system.cpu0.itb.inst_hits 230537480 # ITB inst hits
453system.cpu0.itb.inst_misses 86000 # ITB inst misses
454system.cpu0.itb.read_hits 0 # DTB read hits
455system.cpu0.itb.read_misses 0 # DTB read misses
456system.cpu0.itb.write_hits 0 # DTB write hits
457system.cpu0.itb.write_misses 0 # DTB write misses
458system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
459system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
460system.cpu0.itb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID
461system.cpu0.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID
462system.cpu0.itb.flush_entries 29668 # Number of entries that have been flushed from TLB
463system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
464system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
465system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
466system.cpu0.itb.perms_faults 226388 # Number of TLB faults due to permissions restrictions
467system.cpu0.itb.read_accesses 0 # DTB read accesses
468system.cpu0.itb.write_accesses 0 # DTB write accesses
469system.cpu0.itb.inst_accesses 230623480 # ITB inst accesses
470system.cpu0.itb.hits 230537480 # DTB hits
471system.cpu0.itb.misses 86000 # DTB misses
472system.cpu0.itb.accesses 230623480 # DTB accesses
473system.cpu0.numCycles 786965482 # number of cpu cycles simulated
474system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
475system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
476system.cpu0.fetch.icacheStallCycles 90387711 # Number of cycles fetch is stalled on an Icache miss
477system.cpu0.fetch.Insts 647691070 # Number of instructions fetch has processed
478system.cpu0.fetch.Branches 146587108 # Number of branches that fetch encountered
479system.cpu0.fetch.predictedBranches 87912986 # Number of branches that fetch has predicted taken
480system.cpu0.fetch.Cycles 665690431 # Number of cycles fetch has run and was not squashing or blocked
481system.cpu0.fetch.SquashCycles 15471710 # Number of cycles fetch has spent squashing
482system.cpu0.fetch.TlbCycles 1846295 # Number of cycles fetch has spent waiting for tlb
483system.cpu0.fetch.MiscStallCycles 143165 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
484system.cpu0.fetch.PendingTrapStallCycles 6476529 # Number of stall cycles due to pending traps
485system.cpu0.fetch.PendingQuiesceStallCycles 786234 # Number of stall cycles due to pending quiesce instructions
486system.cpu0.fetch.IcacheWaitRetryStallCycles 320116 # Number of stall cycles due to full MSHR
487system.cpu0.fetch.CacheLines 230311190 # Number of cache lines fetched
488system.cpu0.fetch.IcacheSquashes 1742140 # Number of outstanding Icache misses that were squashed
489system.cpu0.fetch.ItlbSquashes 28723 # Number of outstanding ITLB misses that were squashed
490system.cpu0.fetch.rateDist::samples 773386336 # Number of instructions fetched each cycle (Total)
491system.cpu0.fetch.rateDist::mean 0.980975 # Number of instructions fetched each cycle (Total)
492system.cpu0.fetch.rateDist::stdev 1.219702 # Number of instructions fetched each cycle (Total)
493system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
494system.cpu0.fetch.rateDist::0 409957196 53.01% 53.01% # Number of instructions fetched each cycle (Total)
495system.cpu0.fetch.rateDist::1 140998975 18.23% 71.24% # Number of instructions fetched each cycle (Total)
496system.cpu0.fetch.rateDist::2 49617031 6.42% 77.66% # Number of instructions fetched each cycle (Total)
497system.cpu0.fetch.rateDist::3 172813134 22.34% 100.00% # Number of instructions fetched each cycle (Total)
498system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
499system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
500system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
501system.cpu0.fetch.rateDist::total 773386336 # Number of instructions fetched each cycle (Total)
502system.cpu0.fetch.branchRate 0.186269 # Number of branch fetches per cycle
503system.cpu0.fetch.rate 0.823023 # Number of inst fetches per cycle
504system.cpu0.decode.IdleCycles 108593313 # Number of cycles decode is idle
505system.cpu0.decode.BlockedCycles 378356513 # Number of cycles decode is blocked
506system.cpu0.decode.RunCycles 240969730 # Number of cycles decode is running
507system.cpu0.decode.UnblockCycles 39977542 # Number of cycles decode is unblocking
508system.cpu0.decode.SquashCycles 5489238 # Number of cycles decode is squashing
509system.cpu0.decode.BranchResolved 21224089 # Number of times decode resolved a branch
510system.cpu0.decode.BranchMispred 2292433 # Number of times decode detected a branch misprediction
511system.cpu0.decode.DecodedInsts 668689408 # Number of instructions handled by decode
512system.cpu0.decode.SquashedInsts 25030555 # Number of squashed instructions handled by decode
513system.cpu0.rename.SquashCycles 5489238 # Number of cycles rename is squashing
514system.cpu0.rename.IdleCycles 146312922 # Number of cycles rename is idle
515system.cpu0.rename.BlockCycles 57383456 # Number of cycles rename is blocking
516system.cpu0.rename.serializeStallCycles 250430469 # count of cycles rename stalled for serializing inst
517system.cpu0.rename.RunCycles 242520551 # Number of cycles rename is running
518system.cpu0.rename.UnblockCycles 71249700 # Number of cycles rename is unblocking
519system.cpu0.rename.RenamedInsts 650266707 # Number of instructions processed by rename
520system.cpu0.rename.SquashedInsts 6336504 # Number of squashed instructions processed by rename
521system.cpu0.rename.ROBFullEvents 9477139 # Number of times rename has blocked due to ROB full
522system.cpu0.rename.IQFullEvents 381865 # Number of times rename has blocked due to IQ full
523system.cpu0.rename.LQFullEvents 840506 # Number of times rename has blocked due to LQ full
524system.cpu0.rename.SQFullEvents 33815177 # Number of times rename has blocked due to SQ full
525system.cpu0.rename.FullRegisterEvents 14484 # Number of times there has been no free registers
526system.cpu0.rename.RenamedOperands 619540415 # Number of destination operands rename has renamed
527system.cpu0.rename.RenameLookups 1001273329 # Number of register rename lookups that rename has made
528system.cpu0.rename.int_rename_lookups 768127423 # Number of integer rename lookups
529system.cpu0.rename.fp_rename_lookups 806411 # Number of floating rename lookups
530system.cpu0.rename.CommittedMaps 558016180 # Number of HB maps that are committed
531system.cpu0.rename.UndoneMaps 61524234 # Number of HB maps that are undone due to squashing
532system.cpu0.rename.serializingInsts 16309942 # count of serializing insts renamed
533system.cpu0.rename.tempSerializingInsts 14158531 # count of temporary serializing insts renamed
534system.cpu0.rename.skidInsts 81487680 # count of insts added to the skid buffer
535system.cpu0.memDep0.insertedLoads 106551444 # Number of loads inserted to the mem dependence unit.
536system.cpu0.memDep0.insertedStores 90697387 # Number of stores inserted to the mem dependence unit.
537system.cpu0.memDep0.conflictingLoads 9851628 # Number of conflicting loads.
538system.cpu0.memDep0.conflictingStores 8566406 # Number of conflicting stores.
539system.cpu0.iq.iqInstsAdded 626998472 # Number of instructions added to the IQ (excludes non-spec)
540system.cpu0.iq.iqNonSpecInstsAdded 16435650 # Number of non-speculative instructions added to the IQ
541system.cpu0.iq.iqInstsIssued 631073777 # Number of instructions issued
542system.cpu0.iq.iqSquashedInstsIssued 2910747 # Number of squashed instructions issued
543system.cpu0.iq.iqSquashedInstsExamined 54340762 # Number of squashed instructions iterated over during squash; mainly for profiling
544system.cpu0.iq.iqSquashedOperandsExamined 37568320 # Number of squashed operands that are examined and possibly removed from graph
545system.cpu0.iq.iqSquashedNonSpecRemoved 303534 # Number of squashed non-spec instructions that were removed
546system.cpu0.iq.issued_per_cycle::samples 773386336 # Number of insts issued each cycle
547system.cpu0.iq.issued_per_cycle::mean 0.815988 # Number of insts issued each cycle
548system.cpu0.iq.issued_per_cycle::stdev 1.066561 # Number of insts issued each cycle
549system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
550system.cpu0.iq.issued_per_cycle::0 429333552 55.51% 55.51% # Number of insts issued each cycle
551system.cpu0.iq.issued_per_cycle::1 143479671 18.55% 74.07% # Number of insts issued each cycle
552system.cpu0.iq.issued_per_cycle::2 122471651 15.84% 89.90% # Number of insts issued each cycle
553system.cpu0.iq.issued_per_cycle::3 69760577 9.02% 98.92% # Number of insts issued each cycle
554system.cpu0.iq.issued_per_cycle::4 8335355 1.08% 100.00% # Number of insts issued each cycle
555system.cpu0.iq.issued_per_cycle::5 5527 0.00% 100.00% # Number of insts issued each cycle
556system.cpu0.iq.issued_per_cycle::6 3 0.00% 100.00% # Number of insts issued each cycle
557system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
558system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
559system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
560system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
561system.cpu0.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
562system.cpu0.iq.issued_per_cycle::total 773386336 # Number of insts issued each cycle
563system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
564system.cpu0.iq.fu_full::IntAlu 65856729 45.73% 45.73% # attempts to use FU when none available
565system.cpu0.iq.fu_full::IntMult 73447 0.05% 45.78% # attempts to use FU when none available
566system.cpu0.iq.fu_full::IntDiv 22232 0.02% 45.79% # attempts to use FU when none available
567system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.79% # attempts to use FU when none available
568system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.79% # attempts to use FU when none available
569system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.79% # attempts to use FU when none available
570system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.79% # attempts to use FU when none available
571system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.79% # attempts to use FU when none available
572system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.79% # attempts to use FU when none available
573system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.79% # attempts to use FU when none available
574system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.79% # attempts to use FU when none available
575system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.79% # attempts to use FU when none available
576system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.79% # attempts to use FU when none available
577system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.79% # attempts to use FU when none available
578system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.79% # attempts to use FU when none available
579system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.79% # attempts to use FU when none available
580system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.79% # attempts to use FU when none available
581system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.79% # attempts to use FU when none available
582system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.79% # attempts to use FU when none available
583system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.79% # attempts to use FU when none available
584system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.79% # attempts to use FU when none available
585system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.79% # attempts to use FU when none available
586system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.79% # attempts to use FU when none available
587system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.79% # attempts to use FU when none available
588system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.79% # attempts to use FU when none available
589system.cpu0.iq.fu_full::SimdFloatMisc 47 0.00% 45.79% # attempts to use FU when none available
590system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.79% # attempts to use FU when none available
591system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.79% # attempts to use FU when none available
592system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.79% # attempts to use FU when none available
593system.cpu0.iq.fu_full::MemRead 37876967 26.30% 72.09% # attempts to use FU when none available
594system.cpu0.iq.fu_full::MemWrite 40192311 27.91% 100.00% # attempts to use FU when none available
595system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
596system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
597system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
598system.cpu0.iq.FU_type_0::IntAlu 431505224 68.38% 68.38% # Type of FU issued
599system.cpu0.iq.FU_type_0::IntMult 1606072 0.25% 68.63% # Type of FU issued
600system.cpu0.iq.FU_type_0::IntDiv 80666 0.01% 68.64% # Type of FU issued
601system.cpu0.iq.FU_type_0::FloatAdd 12 0.00% 68.64% # Type of FU issued
602system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued
603system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued
604system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued
605system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued
606system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued
607system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued
608system.cpu0.iq.FU_type_0::SimdAddAcc 1 0.00% 68.64% # Type of FU issued
609system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued
610system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.64% # Type of FU issued
611system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued
612system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued
613system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued
614system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued
615system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued
616system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued
617system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued
618system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.64% # Type of FU issued
619system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued
620system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.64% # Type of FU issued
621system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.64% # Type of FU issued
622system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued
623system.cpu0.iq.FU_type_0::SimdFloatMisc 46680 0.01% 68.65% # Type of FU issued
624system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.65% # Type of FU issued
625system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.65% # Type of FU issued
626system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.65% # Type of FU issued
627system.cpu0.iq.FU_type_0::MemRead 109370672 17.33% 85.98% # Type of FU issued
628system.cpu0.iq.FU_type_0::MemWrite 88464450 14.02% 100.00% # Type of FU issued
629system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
630system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
631system.cpu0.iq.FU_type_0::total 631073777 # Type of FU issued
632system.cpu0.iq.rate 0.801908 # Inst issue rate
633system.cpu0.iq.fu_busy_cnt 144021733 # FU busy when requested
634system.cpu0.iq.fu_busy_rate 0.228217 # FU busy rate (busy events/executed inst)
635system.cpu0.iq.int_inst_queue_reads 2181305203 # Number of integer instruction queue reads
636system.cpu0.iq.int_inst_queue_writes 697468177 # Number of integer instruction queue writes
637system.cpu0.iq.int_inst_queue_wakeup_accesses 613392938 # Number of integer instruction queue wakeup accesses
638system.cpu0.iq.fp_inst_queue_reads 1161167 # Number of floating instruction queue reads
639system.cpu0.iq.fp_inst_queue_writes 463347 # Number of floating instruction queue writes
640system.cpu0.iq.fp_inst_queue_wakeup_accesses 426941 # Number of floating instruction queue wakeup accesses
641system.cpu0.iq.int_alu_accesses 774373560 # Number of integer alu accesses
642system.cpu0.iq.fp_alu_accesses 721950 # Number of floating point alu accesses
643system.cpu0.iew.lsq.thread0.forwLoads 2923759 # Number of loads that had data forwarded from stores
644system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
645system.cpu0.iew.lsq.thread0.squashedLoads 13150556 # Number of loads squashed
646system.cpu0.iew.lsq.thread0.ignoredResponses 17424 # Number of memory responses ignored because the instruction is squashed
647system.cpu0.iew.lsq.thread0.memOrderViolation 157648 # Number of memory ordering violations
648system.cpu0.iew.lsq.thread0.squashedStores 6172607 # Number of stores squashed
649system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
650system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
651system.cpu0.iew.lsq.thread0.rescheduledLoads 2931375 # Number of loads that were rescheduled
652system.cpu0.iew.lsq.thread0.cacheBlocked 4759724 # Number of times an access to memory failed due to the cache being blocked
653system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
654system.cpu0.iew.iewSquashCycles 5489238 # Number of cycles IEW is squashing
655system.cpu0.iew.iewBlockCycles 8266633 # Number of cycles IEW is blocking
656system.cpu0.iew.iewUnblockCycles 4717216 # Number of cycles IEW is unblocking
657system.cpu0.iew.iewDispatchedInsts 643560247 # Number of instructions dispatched to IQ
658system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
659system.cpu0.iew.iewDispLoadInsts 106551444 # Number of dispatched load instructions
660system.cpu0.iew.iewDispStoreInsts 90697387 # Number of dispatched store instructions
661system.cpu0.iew.iewDispNonSpecInsts 13867290 # Number of dispatched non-speculative instructions
662system.cpu0.iew.iewIQFullEvents 61805 # Number of times the IQ has become full, causing a stall
663system.cpu0.iew.iewLSQFullEvents 4582618 # Number of times the LSQ has become full, causing a stall
664system.cpu0.iew.memOrderViolationEvents 157648 # Number of memory order violations
665system.cpu0.iew.predictedTakenIncorrect 2155844 # Number of branches that were predicted taken incorrectly
666system.cpu0.iew.predictedNotTakenIncorrect 3101202 # Number of branches that were predicted not taken incorrectly
667system.cpu0.iew.branchMispredicts 5257046 # Number of branch mispredicts detected at execute
668system.cpu0.iew.iewExecutedInsts 622852330 # Number of executed instructions
669system.cpu0.iew.iewExecLoadInsts 106129153 # Number of load instructions executed
670system.cpu0.iew.iewExecSquashedInsts 7624905 # Number of squashed instructions skipped in execute
671system.cpu0.iew.exec_swp 0 # number of swp insts executed
672system.cpu0.iew.exec_nop 126125 # number of nop insts executed
673system.cpu0.iew.exec_refs 193235409 # number of memory reference insts executed
674system.cpu0.iew.exec_branches 117777762 # Number of branches executed
675system.cpu0.iew.exec_stores 87106256 # Number of stores executed
676system.cpu0.iew.exec_rate 0.791461 # Inst execution rate
677system.cpu0.iew.wb_sent 614619625 # cumulative count of insts sent to commit
678system.cpu0.iew.wb_count 613819879 # cumulative count of insts written-back
679system.cpu0.iew.wb_producers 298670143 # num instructions producing a value
680system.cpu0.iew.wb_consumers 489758313 # num instructions consuming a value
681system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
682system.cpu0.iew.wb_rate 0.779983 # insts written-back per cycle
683system.cpu0.iew.wb_fanout 0.609832 # average fanout of values written-back
684system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
685system.cpu0.commit.commitSquashedInsts 50622338 # The number of squashed insts skipped by commit
686system.cpu0.commit.commitNonSpecStalls 16132116 # The number of times commit has been forced to stall to communicate backwards
687system.cpu0.commit.branchMispredicts 4918284 # The number of times a branch was mispredicted
688system.cpu0.commit.committed_per_cycle::samples 763797135 # Number of insts commited each cycle
689system.cpu0.commit.committed_per_cycle::mean 0.766621 # Number of insts commited each cycle
690system.cpu0.commit.committed_per_cycle::stdev 1.569865 # Number of insts commited each cycle
691system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
692system.cpu0.commit.committed_per_cycle::0 508551807 66.58% 66.58% # Number of insts commited each cycle
693system.cpu0.commit.committed_per_cycle::1 131505056 17.22% 83.80% # Number of insts commited each cycle
694system.cpu0.commit.committed_per_cycle::2 56862924 7.44% 91.24% # Number of insts commited each cycle
695system.cpu0.commit.committed_per_cycle::3 18814885 2.46% 93.71% # Number of insts commited each cycle
696system.cpu0.commit.committed_per_cycle::4 13980697 1.83% 95.54% # Number of insts commited each cycle
697system.cpu0.commit.committed_per_cycle::5 9342143 1.22% 96.76% # Number of insts commited each cycle
698system.cpu0.commit.committed_per_cycle::6 6309382 0.83% 97.59% # Number of insts commited each cycle
699system.cpu0.commit.committed_per_cycle::7 4063980 0.53% 98.12% # Number of insts commited each cycle
700system.cpu0.commit.committed_per_cycle::8 14366261 1.88% 100.00% # Number of insts commited each cycle
701system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
702system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
703system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
704system.cpu0.commit.committed_per_cycle::total 763797135 # Number of insts commited each cycle
705system.cpu0.commit.committedInsts 498729441 # Number of instructions committed
706system.cpu0.commit.committedOps 585543302 # Number of ops (including micro ops) committed
707system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
708system.cpu0.commit.refs 177925668 # Number of memory references committed
709system.cpu0.commit.loads 93400888 # Number of loads committed
710system.cpu0.commit.membars 4075726 # Number of memory barriers committed
711system.cpu0.commit.branches 111746625 # Number of branches committed
712system.cpu0.commit.fp_insts 417930 # Number of committed floating point instructions.
713system.cpu0.commit.int_insts 537600399 # Number of committed integer instructions.
714system.cpu0.commit.function_calls 15117239 # Number of function calls committed.
715system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
716system.cpu0.commit.op_class_0::IntAlu 406177320 69.37% 69.37% # Class of committed instruction
717system.cpu0.commit.op_class_0::IntMult 1336444 0.23% 69.60% # Class of committed instruction
718system.cpu0.commit.op_class_0::IntDiv 63141 0.01% 69.61% # Class of committed instruction
719system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction
720system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction
721system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction
722system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction
723system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction
724system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction
725system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction
726system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction
727system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction
728system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction
729system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction
730system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction
731system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction
732system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction
733system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction
734system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction
735system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction
736system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction
737system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction
738system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction
739system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction
740system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction
741system.cpu0.commit.op_class_0::SimdFloatMisc 40729 0.01% 69.61% # Class of committed instruction
742system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.61% # Class of committed instruction
743system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.61% # Class of committed instruction
744system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.61% # Class of committed instruction
745system.cpu0.commit.op_class_0::MemRead 93400888 15.95% 85.56% # Class of committed instruction
746system.cpu0.commit.op_class_0::MemWrite 84524780 14.44% 100.00% # Class of committed instruction
747system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
748system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
749system.cpu0.commit.op_class_0::total 585543302 # Class of committed instruction
750system.cpu0.commit.bw_lim_events 14366261 # number cycles where commit BW limit reached
751system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
752system.cpu0.rob.rob_reads 1380974813 # The number of ROB reads
753system.cpu0.rob.rob_writes 1281884282 # The number of ROB writes
754system.cpu0.timesIdled 846185 # Number of times that the entire CPU went into an idle state and unscheduled itself
755system.cpu0.idleCycles 13579146 # Total number of cycles that the CPU has spent unscheduled due to idling
756system.cpu0.quiesceCycles 93972383800 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
757system.cpu0.committedInsts 498729441 # Number of Instructions Simulated
758system.cpu0.committedOps 585543302 # Number of Ops (including micro ops) Simulated
759system.cpu0.cpi 1.577941 # CPI: Cycles Per Instruction
760system.cpu0.cpi_total 1.577941 # CPI: Total CPI of All Threads
761system.cpu0.ipc 0.633737 # IPC: Instructions Per Cycle
762system.cpu0.ipc_total 0.633737 # IPC: Total IPC of All Threads
763system.cpu0.int_regfile_reads 735405419 # number of integer regfile reads
764system.cpu0.int_regfile_writes 437369435 # number of integer regfile writes
765system.cpu0.fp_regfile_reads 697220 # number of floating regfile reads
766system.cpu0.fp_regfile_writes 340900 # number of floating regfile writes
767system.cpu0.cc_regfile_reads 134840784 # number of cc regfile reads
768system.cpu0.cc_regfile_writes 135500502 # number of cc regfile writes
769system.cpu0.misc_regfile_reads 3071586051 # number of misc regfile reads
770system.cpu0.misc_regfile_writes 16203449 # number of misc regfile writes
771system.cpu0.dcache.tags.replacements 6421778 # number of replacements
772system.cpu0.dcache.tags.tagsinuse 503.783649 # Cycle average of tags in use
773system.cpu0.dcache.tags.total_refs 165065902 # Total number of references to valid blocks.
774system.cpu0.dcache.tags.sampled_refs 6422290 # Sample count of references to valid blocks.
775system.cpu0.dcache.tags.avg_refs 25.702032 # Average number of references to valid blocks.
776system.cpu0.dcache.tags.warmup_cycle 1750084500 # Cycle when the warmup percentage was hit.
777system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.783649 # Average occupied blocks per requestor
778system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983952 # Average percentage of cache occupancy
779system.cpu0.dcache.tags.occ_percent::total 0.983952 # Average percentage of cache occupancy
780system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
781system.cpu0.dcache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
782system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id
783system.cpu0.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id
784system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
785system.cpu0.dcache.tags.tag_accesses 369226254 # Number of tag accesses
786system.cpu0.dcache.tags.data_accesses 369226254 # Number of data accesses
787system.cpu0.dcache.ReadReq_hits::cpu0.data 86280065 # number of ReadReq hits
788system.cpu0.dcache.ReadReq_hits::total 86280065 # number of ReadReq hits
789system.cpu0.dcache.WriteReq_hits::cpu0.data 73574281 # number of WriteReq hits
790system.cpu0.dcache.WriteReq_hits::total 73574281 # number of WriteReq hits
791system.cpu0.dcache.SoftPFReq_hits::cpu0.data 230862 # number of SoftPFReq hits
792system.cpu0.dcache.SoftPFReq_hits::total 230862 # number of SoftPFReq hits
793system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 1040668 # number of WriteInvalidateReq hits
794system.cpu0.dcache.WriteInvalidateReq_hits::total 1040668 # number of WriteInvalidateReq hits
795system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1948592 # number of LoadLockedReq hits
796system.cpu0.dcache.LoadLockedReq_hits::total 1948592 # number of LoadLockedReq hits
797system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1987329 # number of StoreCondReq hits
798system.cpu0.dcache.StoreCondReq_hits::total 1987329 # number of StoreCondReq hits
799system.cpu0.dcache.demand_hits::cpu0.data 159854346 # number of demand (read+write) hits
800system.cpu0.dcache.demand_hits::total 159854346 # number of demand (read+write) hits
801system.cpu0.dcache.overall_hits::cpu0.data 160085208 # number of overall hits
802system.cpu0.dcache.overall_hits::total 160085208 # number of overall hits
803system.cpu0.dcache.ReadReq_misses::cpu0.data 7331765 # number of ReadReq misses
804system.cpu0.dcache.ReadReq_misses::total 7331765 # number of ReadReq misses
805system.cpu0.dcache.WriteReq_misses::cpu0.data 7708797 # number of WriteReq misses
806system.cpu0.dcache.WriteReq_misses::total 7708797 # number of WriteReq misses
807system.cpu0.dcache.SoftPFReq_misses::cpu0.data 740087 # number of SoftPFReq misses
808system.cpu0.dcache.SoftPFReq_misses::total 740087 # number of SoftPFReq misses
809system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 294779 # number of LoadLockedReq misses
810system.cpu0.dcache.LoadLockedReq_misses::total 294779 # number of LoadLockedReq misses
811system.cpu0.dcache.StoreCondReq_misses::cpu0.data 214098 # number of StoreCondReq misses
812system.cpu0.dcache.StoreCondReq_misses::total 214098 # number of StoreCondReq misses
813system.cpu0.dcache.demand_misses::cpu0.data 15040562 # number of demand (read+write) misses
814system.cpu0.dcache.demand_misses::total 15040562 # number of demand (read+write) misses
815system.cpu0.dcache.overall_misses::cpu0.data 15780649 # number of overall misses
816system.cpu0.dcache.overall_misses::total 15780649 # number of overall misses
817system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 115068880578 # number of ReadReq miss cycles
818system.cpu0.dcache.ReadReq_miss_latency::total 115068880578 # number of ReadReq miss cycles
819system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 135208359707 # number of WriteReq miss cycles
820system.cpu0.dcache.WriteReq_miss_latency::total 135208359707 # number of WriteReq miss cycles
821system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4223400082 # number of LoadLockedReq miss cycles
822system.cpu0.dcache.LoadLockedReq_miss_latency::total 4223400082 # number of LoadLockedReq miss cycles
823system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4534810216 # number of StoreCondReq miss cycles
824system.cpu0.dcache.StoreCondReq_miss_latency::total 4534810216 # number of StoreCondReq miss cycles
825system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4219500 # number of StoreCondFailReq miss cycles
826system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4219500 # number of StoreCondFailReq miss cycles
827system.cpu0.dcache.demand_miss_latency::cpu0.data 250277240285 # number of demand (read+write) miss cycles
828system.cpu0.dcache.demand_miss_latency::total 250277240285 # number of demand (read+write) miss cycles
829system.cpu0.dcache.overall_miss_latency::cpu0.data 250277240285 # number of overall miss cycles
830system.cpu0.dcache.overall_miss_latency::total 250277240285 # number of overall miss cycles
831system.cpu0.dcache.ReadReq_accesses::cpu0.data 93611830 # number of ReadReq accesses(hits+misses)
832system.cpu0.dcache.ReadReq_accesses::total 93611830 # number of ReadReq accesses(hits+misses)
833system.cpu0.dcache.WriteReq_accesses::cpu0.data 81283078 # number of WriteReq accesses(hits+misses)
834system.cpu0.dcache.WriteReq_accesses::total 81283078 # number of WriteReq accesses(hits+misses)
835system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 970949 # number of SoftPFReq accesses(hits+misses)
836system.cpu0.dcache.SoftPFReq_accesses::total 970949 # number of SoftPFReq accesses(hits+misses)
837system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1040668 # number of WriteInvalidateReq accesses(hits+misses)
838system.cpu0.dcache.WriteInvalidateReq_accesses::total 1040668 # number of WriteInvalidateReq accesses(hits+misses)
839system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2243371 # number of LoadLockedReq accesses(hits+misses)
840system.cpu0.dcache.LoadLockedReq_accesses::total 2243371 # number of LoadLockedReq accesses(hits+misses)
841system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2201427 # number of StoreCondReq accesses(hits+misses)
842system.cpu0.dcache.StoreCondReq_accesses::total 2201427 # number of StoreCondReq accesses(hits+misses)
843system.cpu0.dcache.demand_accesses::cpu0.data 174894908 # number of demand (read+write) accesses
844system.cpu0.dcache.demand_accesses::total 174894908 # number of demand (read+write) accesses
845system.cpu0.dcache.overall_accesses::cpu0.data 175865857 # number of overall (read+write) accesses
846system.cpu0.dcache.overall_accesses::total 175865857 # number of overall (read+write) accesses
847system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.078321 # miss rate for ReadReq accesses
848system.cpu0.dcache.ReadReq_miss_rate::total 0.078321 # miss rate for ReadReq accesses
849system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.094839 # miss rate for WriteReq accesses
850system.cpu0.dcache.WriteReq_miss_rate::total 0.094839 # miss rate for WriteReq accesses
851system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.762231 # miss rate for SoftPFReq accesses
852system.cpu0.dcache.SoftPFReq_miss_rate::total 0.762231 # miss rate for SoftPFReq accesses
853system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.131400 # miss rate for LoadLockedReq accesses
854system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.131400 # miss rate for LoadLockedReq accesses
855system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097254 # miss rate for StoreCondReq accesses
856system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097254 # miss rate for StoreCondReq accesses
857system.cpu0.dcache.demand_miss_rate::cpu0.data 0.085998 # miss rate for demand accesses
858system.cpu0.dcache.demand_miss_rate::total 0.085998 # miss rate for demand accesses
859system.cpu0.dcache.overall_miss_rate::cpu0.data 0.089731 # miss rate for overall accesses
860system.cpu0.dcache.overall_miss_rate::total 0.089731 # miss rate for overall accesses
861system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15694.567485 # average ReadReq miss latency
862system.cpu0.dcache.ReadReq_avg_miss_latency::total 15694.567485 # average ReadReq miss latency
863system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17539.488938 # average WriteReq miss latency
864system.cpu0.dcache.WriteReq_avg_miss_latency::total 17539.488938 # average WriteReq miss latency
865system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14327.343814 # average LoadLockedReq miss latency
866system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14327.343814 # average LoadLockedReq miss latency
867system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21181.002233 # average StoreCondReq miss latency
868system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21181.002233 # average StoreCondReq miss latency
869system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
870system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
871system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16640.152162 # average overall miss latency
872system.cpu0.dcache.demand_avg_miss_latency::total 16640.152162 # average overall miss latency
873system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15859.755849 # average overall miss latency
874system.cpu0.dcache.overall_avg_miss_latency::total 15859.755849 # average overall miss latency
875system.cpu0.dcache.blocked_cycles::no_mshrs 17082084 # number of cycles access was blocked
876system.cpu0.dcache.blocked_cycles::no_targets 19003690 # number of cycles access was blocked
877system.cpu0.dcache.blocked::no_mshrs 950552 # number of cycles access was blocked
878system.cpu0.dcache.blocked::no_targets 748671 # number of cycles access was blocked
879system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.970699 # average number of cycles each access was blocked
880system.cpu0.dcache.avg_blocked_cycles::no_targets 25.383232 # average number of cycles each access was blocked
881system.cpu0.dcache.fast_writes 1040668 # number of fast writes performed
882system.cpu0.dcache.cache_copies 0 # number of cache copies performed
883system.cpu0.dcache.writebacks::writebacks 3548346 # number of writebacks
884system.cpu0.dcache.writebacks::total 3548346 # number of writebacks
885system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3808172 # number of ReadReq MSHR hits
886system.cpu0.dcache.ReadReq_mshr_hits::total 3808172 # number of ReadReq MSHR hits
887system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6155071 # number of WriteReq MSHR hits
888system.cpu0.dcache.WriteReq_mshr_hits::total 6155071 # number of WriteReq MSHR hits
889system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 150940 # number of LoadLockedReq MSHR hits
890system.cpu0.dcache.LoadLockedReq_mshr_hits::total 150940 # number of LoadLockedReq MSHR hits
891system.cpu0.dcache.demand_mshr_hits::cpu0.data 9963243 # number of demand (read+write) MSHR hits
892system.cpu0.dcache.demand_mshr_hits::total 9963243 # number of demand (read+write) MSHR hits
893system.cpu0.dcache.overall_mshr_hits::cpu0.data 9963243 # number of overall MSHR hits
894system.cpu0.dcache.overall_mshr_hits::total 9963243 # number of overall MSHR hits
895system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3523593 # number of ReadReq MSHR misses
896system.cpu0.dcache.ReadReq_mshr_misses::total 3523593 # number of ReadReq MSHR misses
897system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1532184 # number of WriteReq MSHR misses
898system.cpu0.dcache.WriteReq_mshr_misses::total 1532184 # number of WriteReq MSHR misses
899system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 733570 # number of SoftPFReq MSHR misses
900system.cpu0.dcache.SoftPFReq_mshr_misses::total 733570 # number of SoftPFReq MSHR misses
901system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 143839 # number of LoadLockedReq MSHR misses
902system.cpu0.dcache.LoadLockedReq_mshr_misses::total 143839 # number of LoadLockedReq MSHR misses
903system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 214091 # number of StoreCondReq MSHR misses
904system.cpu0.dcache.StoreCondReq_mshr_misses::total 214091 # number of StoreCondReq MSHR misses
905system.cpu0.dcache.demand_mshr_misses::cpu0.data 5055777 # number of demand (read+write) MSHR misses
906system.cpu0.dcache.demand_mshr_misses::total 5055777 # number of demand (read+write) MSHR misses
907system.cpu0.dcache.overall_mshr_misses::cpu0.data 5789347 # number of overall MSHR misses
908system.cpu0.dcache.overall_mshr_misses::total 5789347 # number of overall MSHR misses
909system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 48006705459 # number of ReadReq MSHR miss cycles
910system.cpu0.dcache.ReadReq_mshr_miss_latency::total 48006705459 # number of ReadReq MSHR miss cycles
911system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 27570008615 # number of WriteReq MSHR miss cycles
912system.cpu0.dcache.WriteReq_mshr_miss_latency::total 27570008615 # number of WriteReq MSHR miss cycles
913system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18661725527 # number of SoftPFReq MSHR miss cycles
914system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18661725527 # number of SoftPFReq MSHR miss cycles
915system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 57519686561 # number of WriteInvalidateReq MSHR miss cycles
916system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 57519686561 # number of WriteInvalidateReq MSHR miss cycles
917system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1764532424 # number of LoadLockedReq MSHR miss cycles
918system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1764532424 # number of LoadLockedReq MSHR miss cycles
919system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4095364784 # number of StoreCondReq MSHR miss cycles
920system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4095364784 # number of StoreCondReq MSHR miss cycles
921system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4027500 # number of StoreCondFailReq MSHR miss cycles
922system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4027500 # number of StoreCondFailReq MSHR miss cycles
923system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 75576714074 # number of demand (read+write) MSHR miss cycles
924system.cpu0.dcache.demand_mshr_miss_latency::total 75576714074 # number of demand (read+write) MSHR miss cycles
925system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94238439601 # number of overall MSHR miss cycles
926system.cpu0.dcache.overall_mshr_miss_latency::total 94238439601 # number of overall MSHR miss cycles
927system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5807383412 # number of ReadReq MSHR uncacheable cycles
928system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5807383412 # number of ReadReq MSHR uncacheable cycles
929system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5600359921 # number of WriteReq MSHR uncacheable cycles
930system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5600359921 # number of WriteReq MSHR uncacheable cycles
931system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11407743333 # number of overall MSHR uncacheable cycles
932system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11407743333 # number of overall MSHR uncacheable cycles
933system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037640 # mshr miss rate for ReadReq accesses
934system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037640 # mshr miss rate for ReadReq accesses
935system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018850 # mshr miss rate for WriteReq accesses
936system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018850 # mshr miss rate for WriteReq accesses
937system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.755519 # mshr miss rate for SoftPFReq accesses
938system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.755519 # mshr miss rate for SoftPFReq accesses
939system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064117 # mshr miss rate for LoadLockedReq accesses
940system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064117 # mshr miss rate for LoadLockedReq accesses
941system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097251 # mshr miss rate for StoreCondReq accesses
942system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097251 # mshr miss rate for StoreCondReq accesses
943system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028908 # mshr miss rate for demand accesses
944system.cpu0.dcache.demand_mshr_miss_rate::total 0.028908 # mshr miss rate for demand accesses
945system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032919 # mshr miss rate for overall accesses
946system.cpu0.dcache.overall_mshr_miss_rate::total 0.032919 # mshr miss rate for overall accesses
947system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13624.361684 # average ReadReq mshr miss latency
948system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13624.361684 # average ReadReq mshr miss latency
949system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17993.928024 # average WriteReq mshr miss latency
950system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17993.928024 # average WriteReq mshr miss latency
951system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25439.597485 # average SoftPFReq mshr miss latency
952system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25439.597485 # average SoftPFReq mshr miss latency
953system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency
954system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
955system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12267.413038 # average LoadLockedReq mshr miss latency
956system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12267.413038 # average LoadLockedReq mshr miss latency
957system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19129.084287 # average StoreCondReq mshr miss latency
958system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19129.084287 # average StoreCondReq mshr miss latency
959system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
960system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
961system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14948.585366 # average overall mshr miss latency
962system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14948.585366 # average overall mshr miss latency
963system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16277.904849 # average overall mshr miss latency
964system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16277.904849 # average overall mshr miss latency
965system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
966system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
967system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
968system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
969system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
970system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
971system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
972system.cpu0.icache.tags.replacements 6503720 # number of replacements
973system.cpu0.icache.tags.tagsinuse 511.971418 # Cycle average of tags in use
974system.cpu0.icache.tags.total_refs 223511778 # Total number of references to valid blocks.
975system.cpu0.icache.tags.sampled_refs 6504232 # Sample count of references to valid blocks.
976system.cpu0.icache.tags.avg_refs 34.364054 # Average number of references to valid blocks.
977system.cpu0.icache.tags.warmup_cycle 8400074750 # Cycle when the warmup percentage was hit.
978system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.971418 # Average occupied blocks per requestor
979system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999944 # Average percentage of cache occupancy
980system.cpu0.icache.tags.occ_percent::total 0.999944 # Average percentage of cache occupancy
981system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
982system.cpu0.icache.tags.age_task_id_blocks_1024::0 266 # Occupied blocks per task id
983system.cpu0.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id
984system.cpu0.icache.tags.age_task_id_blocks_1024::2 184 # Occupied blocks per task id
985system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
986system.cpu0.icache.tags.tag_accesses 467078613 # Number of tag accesses
987system.cpu0.icache.tags.data_accesses 467078613 # Number of data accesses
988system.cpu0.icache.ReadReq_hits::cpu0.inst 223511778 # number of ReadReq hits
989system.cpu0.icache.ReadReq_hits::total 223511778 # number of ReadReq hits
990system.cpu0.icache.demand_hits::cpu0.inst 223511778 # number of demand (read+write) hits
991system.cpu0.icache.demand_hits::total 223511778 # number of demand (read+write) hits
992system.cpu0.icache.overall_hits::cpu0.inst 223511778 # number of overall hits
993system.cpu0.icache.overall_hits::total 223511778 # number of overall hits
994system.cpu0.icache.ReadReq_misses::cpu0.inst 6775226 # number of ReadReq misses
995system.cpu0.icache.ReadReq_misses::total 6775226 # number of ReadReq misses
996system.cpu0.icache.demand_misses::cpu0.inst 6775226 # number of demand (read+write) misses
997system.cpu0.icache.demand_misses::total 6775226 # number of demand (read+write) misses
998system.cpu0.icache.overall_misses::cpu0.inst 6775226 # number of overall misses
999system.cpu0.icache.overall_misses::total 6775226 # number of overall misses
1000system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 58809305620 # number of ReadReq miss cycles
1001system.cpu0.icache.ReadReq_miss_latency::total 58809305620 # number of ReadReq miss cycles
1002system.cpu0.icache.demand_miss_latency::cpu0.inst 58809305620 # number of demand (read+write) miss cycles
1003system.cpu0.icache.demand_miss_latency::total 58809305620 # number of demand (read+write) miss cycles
1004system.cpu0.icache.overall_miss_latency::cpu0.inst 58809305620 # number of overall miss cycles
1005system.cpu0.icache.overall_miss_latency::total 58809305620 # number of overall miss cycles
1006system.cpu0.icache.ReadReq_accesses::cpu0.inst 230287004 # number of ReadReq accesses(hits+misses)
1007system.cpu0.icache.ReadReq_accesses::total 230287004 # number of ReadReq accesses(hits+misses)
1008system.cpu0.icache.demand_accesses::cpu0.inst 230287004 # number of demand (read+write) accesses
1009system.cpu0.icache.demand_accesses::total 230287004 # number of demand (read+write) accesses
1010system.cpu0.icache.overall_accesses::cpu0.inst 230287004 # number of overall (read+write) accesses
1011system.cpu0.icache.overall_accesses::total 230287004 # number of overall (read+write) accesses
1012system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029421 # miss rate for ReadReq accesses
1013system.cpu0.icache.ReadReq_miss_rate::total 0.029421 # miss rate for ReadReq accesses
1014system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029421 # miss rate for demand accesses
1015system.cpu0.icache.demand_miss_rate::total 0.029421 # miss rate for demand accesses
1016system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029421 # miss rate for overall accesses
1017system.cpu0.icache.overall_miss_rate::total 0.029421 # miss rate for overall accesses
1018system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8680.050764 # average ReadReq miss latency
1019system.cpu0.icache.ReadReq_avg_miss_latency::total 8680.050764 # average ReadReq miss latency
1020system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8680.050764 # average overall miss latency
1021system.cpu0.icache.demand_avg_miss_latency::total 8680.050764 # average overall miss latency
1022system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8680.050764 # average overall miss latency
1023system.cpu0.icache.overall_avg_miss_latency::total 8680.050764 # average overall miss latency
1024system.cpu0.icache.blocked_cycles::no_mshrs 4711788 # number of cycles access was blocked
1025system.cpu0.icache.blocked_cycles::no_targets 167 # number of cycles access was blocked
1026system.cpu0.icache.blocked::no_mshrs 607280 # number of cycles access was blocked
1027system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked
1028system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.758839 # average number of cycles each access was blocked
1029system.cpu0.icache.avg_blocked_cycles::no_targets 167 # average number of cycles each access was blocked
1030system.cpu0.icache.fast_writes 0 # number of fast writes performed
1031system.cpu0.icache.cache_copies 0 # number of cache copies performed
1032system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 270621 # number of ReadReq MSHR hits
1033system.cpu0.icache.ReadReq_mshr_hits::total 270621 # number of ReadReq MSHR hits
1034system.cpu0.icache.demand_mshr_hits::cpu0.inst 270621 # number of demand (read+write) MSHR hits
1035system.cpu0.icache.demand_mshr_hits::total 270621 # number of demand (read+write) MSHR hits
1036system.cpu0.icache.overall_mshr_hits::cpu0.inst 270621 # number of overall MSHR hits
1037system.cpu0.icache.overall_mshr_hits::total 270621 # number of overall MSHR hits
1038system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6504605 # number of ReadReq MSHR misses
1039system.cpu0.icache.ReadReq_mshr_misses::total 6504605 # number of ReadReq MSHR misses
1040system.cpu0.icache.demand_mshr_misses::cpu0.inst 6504605 # number of demand (read+write) MSHR misses
1041system.cpu0.icache.demand_mshr_misses::total 6504605 # number of demand (read+write) MSHR misses
1042system.cpu0.icache.overall_mshr_misses::cpu0.inst 6504605 # number of overall MSHR misses
1043system.cpu0.icache.overall_mshr_misses::total 6504605 # number of overall MSHR misses
1044system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 47647231055 # number of ReadReq MSHR miss cycles
1045system.cpu0.icache.ReadReq_mshr_miss_latency::total 47647231055 # number of ReadReq MSHR miss cycles
1046system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 47647231055 # number of demand (read+write) MSHR miss cycles
1047system.cpu0.icache.demand_mshr_miss_latency::total 47647231055 # number of demand (read+write) MSHR miss cycles
1048system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 47647231055 # number of overall MSHR miss cycles
1049system.cpu0.icache.overall_mshr_miss_latency::total 47647231055 # number of overall MSHR miss cycles
1050system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1699559498 # number of ReadReq MSHR uncacheable cycles
1051system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1699559498 # number of ReadReq MSHR uncacheable cycles
1052system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1699559498 # number of overall MSHR uncacheable cycles
1053system.cpu0.icache.overall_mshr_uncacheable_latency::total 1699559498 # number of overall MSHR uncacheable cycles
1054system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028246 # mshr miss rate for ReadReq accesses
1055system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028246 # mshr miss rate for ReadReq accesses
1056system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028246 # mshr miss rate for demand accesses
1057system.cpu0.icache.demand_mshr_miss_rate::total 0.028246 # mshr miss rate for demand accesses
1058system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028246 # mshr miss rate for overall accesses
1059system.cpu0.icache.overall_mshr_miss_rate::total 0.028246 # mshr miss rate for overall accesses
1060system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7325.153650 # average ReadReq mshr miss latency
1061system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7325.153650 # average ReadReq mshr miss latency
1062system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7325.153650 # average overall mshr miss latency
1063system.cpu0.icache.demand_avg_mshr_miss_latency::total 7325.153650 # average overall mshr miss latency
1064system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7325.153650 # average overall mshr miss latency
1065system.cpu0.icache.overall_avg_mshr_miss_latency::total 7325.153650 # average overall mshr miss latency
1066system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1067system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1068system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1069system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1070system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1071system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 59245032 # number of hwpf identified
1072system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2351166 # number of hwpf that were already in mshr
1073system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 52469358 # number of hwpf that were already in the cache
1074system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1249562 # number of hwpf that were already in the prefetch queue
1075system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
1076system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 200789 # number of hwpf removed because MSHR allocated
1077system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 2974157 # number of hwpf issued
1078system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4925432 # number of hwpf spanning a virtual page
1079system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
1080system.cpu0.l2cache.tags.replacements 3747306 # number of replacements
1081system.cpu0.l2cache.tags.tagsinuse 16276.136731 # Cycle average of tags in use
1082system.cpu0.l2cache.tags.total_refs 13593053 # Total number of references to valid blocks.
1083system.cpu0.l2cache.tags.sampled_refs 3763332 # Sample count of references to valid blocks.
1084system.cpu0.l2cache.tags.avg_refs 3.611973 # Average number of references to valid blocks.
1085system.cpu0.l2cache.tags.warmup_cycle 6997709500 # Cycle when the warmup percentage was hit.
1086system.cpu0.l2cache.tags.occ_blocks::writebacks 4266.822439 # Average occupied blocks per requestor
1087system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 59.073583 # Average occupied blocks per requestor
1088system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 61.998615 # Average occupied blocks per requestor
1089system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 875.814301 # Average occupied blocks per requestor
1090system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3003.067946 # Average occupied blocks per requestor
1091system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8009.359846 # Average occupied blocks per requestor
1092system.cpu0.l2cache.tags.occ_percent::writebacks 0.260426 # Average percentage of cache occupancy
1093system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003606 # Average percentage of cache occupancy
1094system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003784 # Average percentage of cache occupancy
1095system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.053455 # Average percentage of cache occupancy
1096system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.183293 # Average percentage of cache occupancy
1097system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.488853 # Average percentage of cache occupancy
1098system.cpu0.l2cache.tags.occ_percent::total 0.993417 # Average percentage of cache occupancy
1099system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8909 # Occupied blocks per task id
1100system.cpu0.l2cache.tags.occ_task_id_blocks::1023 95 # Occupied blocks per task id
1101system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7022 # Occupied blocks per task id
1102system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 203 # Occupied blocks per task id
1103system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 252 # Occupied blocks per task id
1104system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3635 # Occupied blocks per task id
1105system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 3246 # Occupied blocks per task id
1106system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1573 # Occupied blocks per task id
1107system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id
1108system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 11 # Occupied blocks per task id
1109system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 72 # Occupied blocks per task id
1110system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id
1111system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
1112system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
1113system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 759 # Occupied blocks per task id
1114system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2892 # Occupied blocks per task id
1115system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2491 # Occupied blocks per task id
1116system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 768 # Occupied blocks per task id
1117system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.543762 # Percentage of cache occupancy per task id
1118system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005798 # Percentage of cache occupancy per task id
1119system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.428589 # Percentage of cache occupancy per task id
1120system.cpu0.l2cache.tags.tag_accesses 294843936 # Number of tag accesses
1121system.cpu0.l2cache.tags.data_accesses 294843936 # Number of data accesses
1122system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 600493 # number of ReadReq hits
1123system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 179726 # number of ReadReq hits
1124system.cpu0.l2cache.ReadReq_hits::cpu0.inst 6257574 # number of ReadReq hits
1125system.cpu0.l2cache.ReadReq_hits::cpu0.data 3196043 # number of ReadReq hits
1126system.cpu0.l2cache.ReadReq_hits::total 10233836 # number of ReadReq hits
1127system.cpu0.l2cache.Writeback_hits::writebacks 3548335 # number of Writeback hits
1128system.cpu0.l2cache.Writeback_hits::total 3548335 # number of Writeback hits
1129system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 119384 # number of UpgradeReq hits
1130system.cpu0.l2cache.UpgradeReq_hits::total 119384 # number of UpgradeReq hits
1131system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 38955 # number of SCUpgradeReq hits
1132system.cpu0.l2cache.SCUpgradeReq_hits::total 38955 # number of SCUpgradeReq hits
1133system.cpu0.l2cache.ReadExReq_hits::cpu0.data 985595 # number of ReadExReq hits
1134system.cpu0.l2cache.ReadExReq_hits::total 985595 # number of ReadExReq hits
1135system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 600493 # number of demand (read+write) hits
1136system.cpu0.l2cache.demand_hits::cpu0.itb.walker 179726 # number of demand (read+write) hits
1137system.cpu0.l2cache.demand_hits::cpu0.inst 6257574 # number of demand (read+write) hits
1138system.cpu0.l2cache.demand_hits::cpu0.data 4181638 # number of demand (read+write) hits
1139system.cpu0.l2cache.demand_hits::total 11219431 # number of demand (read+write) hits
1140system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 600493 # number of overall hits
1141system.cpu0.l2cache.overall_hits::cpu0.itb.walker 179726 # number of overall hits
1142system.cpu0.l2cache.overall_hits::cpu0.inst 6257574 # number of overall hits
1143system.cpu0.l2cache.overall_hits::cpu0.data 4181638 # number of overall hits
1144system.cpu0.l2cache.overall_hits::total 11219431 # number of overall hits
1145system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 16370 # number of ReadReq misses
1146system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 12947 # number of ReadReq misses
1147system.cpu0.l2cache.ReadReq_misses::cpu0.inst 246684 # number of ReadReq misses
1148system.cpu0.l2cache.ReadReq_misses::cpu0.data 1202213 # number of ReadReq misses
1149system.cpu0.l2cache.ReadReq_misses::total 1478214 # number of ReadReq misses
1150system.cpu0.l2cache.Writeback_misses::writebacks 9 # number of Writeback misses
1151system.cpu0.l2cache.Writeback_misses::total 9 # number of Writeback misses
1152system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 131869 # number of UpgradeReq misses
1153system.cpu0.l2cache.UpgradeReq_misses::total 131869 # number of UpgradeReq misses
1154system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 175118 # number of SCUpgradeReq misses
1155system.cpu0.l2cache.SCUpgradeReq_misses::total 175118 # number of SCUpgradeReq misses
1156system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 18 # number of SCUpgradeFailReq misses
1157system.cpu0.l2cache.SCUpgradeFailReq_misses::total 18 # number of SCUpgradeFailReq misses
1158system.cpu0.l2cache.ReadExReq_misses::cpu0.data 304338 # number of ReadExReq misses
1159system.cpu0.l2cache.ReadExReq_misses::total 304338 # number of ReadExReq misses
1160system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 16370 # number of demand (read+write) misses
1161system.cpu0.l2cache.demand_misses::cpu0.itb.walker 12947 # number of demand (read+write) misses
1162system.cpu0.l2cache.demand_misses::cpu0.inst 246684 # number of demand (read+write) misses
1163system.cpu0.l2cache.demand_misses::cpu0.data 1506551 # number of demand (read+write) misses
1164system.cpu0.l2cache.demand_misses::total 1782552 # number of demand (read+write) misses
1165system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 16370 # number of overall misses
1166system.cpu0.l2cache.overall_misses::cpu0.itb.walker 12947 # number of overall misses
1167system.cpu0.l2cache.overall_misses::cpu0.inst 246684 # number of overall misses
1168system.cpu0.l2cache.overall_misses::cpu0.data 1506551 # number of overall misses
1169system.cpu0.l2cache.overall_misses::total 1782552 # number of overall misses
1170system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 782711292 # number of ReadReq miss cycles
1171system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 885174343 # number of ReadReq miss cycles
1172system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 6713721698 # number of ReadReq miss cycles
1173system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 44470699734 # number of ReadReq miss cycles
1174system.cpu0.l2cache.ReadReq_miss_latency::total 52852307067 # number of ReadReq miss cycles
1175system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2670586208 # number of UpgradeReq miss cycles
1176system.cpu0.l2cache.UpgradeReq_miss_latency::total 2670586208 # number of UpgradeReq miss cycles
1177system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3556484886 # number of SCUpgradeReq miss cycles
1178system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3556484886 # number of SCUpgradeReq miss cycles
1179system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3931499 # number of SCUpgradeFailReq miss cycles
1180system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3931499 # number of SCUpgradeFailReq miss cycles
1181system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 15577643529 # number of ReadExReq miss cycles
1182system.cpu0.l2cache.ReadExReq_miss_latency::total 15577643529 # number of ReadExReq miss cycles
1183system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 782711292 # number of demand (read+write) miss cycles
1184system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 885174343 # number of demand (read+write) miss cycles
1185system.cpu0.l2cache.demand_miss_latency::cpu0.inst 6713721698 # number of demand (read+write) miss cycles
1186system.cpu0.l2cache.demand_miss_latency::cpu0.data 60048343263 # number of demand (read+write) miss cycles
1187system.cpu0.l2cache.demand_miss_latency::total 68429950596 # number of demand (read+write) miss cycles
1188system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 782711292 # number of overall miss cycles
1189system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 885174343 # number of overall miss cycles
1190system.cpu0.l2cache.overall_miss_latency::cpu0.inst 6713721698 # number of overall miss cycles
1191system.cpu0.l2cache.overall_miss_latency::cpu0.data 60048343263 # number of overall miss cycles
1192system.cpu0.l2cache.overall_miss_latency::total 68429950596 # number of overall miss cycles
1193system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 616863 # number of ReadReq accesses(hits+misses)
1194system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 192673 # number of ReadReq accesses(hits+misses)
1195system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 6504258 # number of ReadReq accesses(hits+misses)
1196system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4398256 # number of ReadReq accesses(hits+misses)
1197system.cpu0.l2cache.ReadReq_accesses::total 11712050 # number of ReadReq accesses(hits+misses)
1198system.cpu0.l2cache.Writeback_accesses::writebacks 3548344 # number of Writeback accesses(hits+misses)
1199system.cpu0.l2cache.Writeback_accesses::total 3548344 # number of Writeback accesses(hits+misses)
1200system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 251253 # number of UpgradeReq accesses(hits+misses)
1201system.cpu0.l2cache.UpgradeReq_accesses::total 251253 # number of UpgradeReq accesses(hits+misses)
1202system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 214073 # number of SCUpgradeReq accesses(hits+misses)
1203system.cpu0.l2cache.SCUpgradeReq_accesses::total 214073 # number of SCUpgradeReq accesses(hits+misses)
1204system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 18 # number of SCUpgradeFailReq accesses(hits+misses)
1205system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 18 # number of SCUpgradeFailReq accesses(hits+misses)
1206system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1289933 # number of ReadExReq accesses(hits+misses)
1207system.cpu0.l2cache.ReadExReq_accesses::total 1289933 # number of ReadExReq accesses(hits+misses)
1208system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 616863 # number of demand (read+write) accesses
1209system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 192673 # number of demand (read+write) accesses
1210system.cpu0.l2cache.demand_accesses::cpu0.inst 6504258 # number of demand (read+write) accesses
1211system.cpu0.l2cache.demand_accesses::cpu0.data 5688189 # number of demand (read+write) accesses
1212system.cpu0.l2cache.demand_accesses::total 13001983 # number of demand (read+write) accesses
1213system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 616863 # number of overall (read+write) accesses
1214system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 192673 # number of overall (read+write) accesses
1215system.cpu0.l2cache.overall_accesses::cpu0.inst 6504258 # number of overall (read+write) accesses
1216system.cpu0.l2cache.overall_accesses::cpu0.data 5688189 # number of overall (read+write) accesses
1217system.cpu0.l2cache.overall_accesses::total 13001983 # number of overall (read+write) accesses
1218system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026537 # miss rate for ReadReq accesses
1219system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.067197 # miss rate for ReadReq accesses
1220system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.037927 # miss rate for ReadReq accesses
1221system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.273339 # miss rate for ReadReq accesses
1222system.cpu0.l2cache.ReadReq_miss_rate::total 0.126213 # miss rate for ReadReq accesses
1223system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000003 # miss rate for Writeback accesses
1224system.cpu0.l2cache.Writeback_miss_rate::total 0.000003 # miss rate for Writeback accesses
1225system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.524845 # miss rate for UpgradeReq accesses
1226system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.524845 # miss rate for UpgradeReq accesses
1227system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.818029 # miss rate for SCUpgradeReq accesses
1228system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.818029 # miss rate for SCUpgradeReq accesses
1229system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1230system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1231system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.235933 # miss rate for ReadExReq accesses
1232system.cpu0.l2cache.ReadExReq_miss_rate::total 0.235933 # miss rate for ReadExReq accesses
1233system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026537 # miss rate for demand accesses
1234system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.067197 # miss rate for demand accesses
1235system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037927 # miss rate for demand accesses
1236system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.264856 # miss rate for demand accesses
1237system.cpu0.l2cache.demand_miss_rate::total 0.137098 # miss rate for demand accesses
1238system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026537 # miss rate for overall accesses
1239system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.067197 # miss rate for overall accesses
1240system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037927 # miss rate for overall accesses
1241system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.264856 # miss rate for overall accesses
1242system.cpu0.l2cache.overall_miss_rate::total 0.137098 # miss rate for overall accesses
1243system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 47813.762492 # average ReadReq miss latency
1244system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 68369.069514 # average ReadReq miss latency
1245system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 27215.878200 # average ReadReq miss latency
1246system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 36990.699430 # average ReadReq miss latency
1247system.cpu0.l2cache.ReadReq_avg_miss_latency::total 35754.164869 # average ReadReq miss latency
1248system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 20251.812086 # average UpgradeReq miss latency
1249system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 20251.812086 # average UpgradeReq miss latency
1250system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20309.076657 # average SCUpgradeReq miss latency
1251system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20309.076657 # average SCUpgradeReq miss latency
1252system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 218416.611111 # average SCUpgradeFailReq miss latency
1253system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 218416.611111 # average SCUpgradeFailReq miss latency
1254system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 51185.338436 # average ReadExReq miss latency
1255system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 51185.338436 # average ReadExReq miss latency
1256system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 47813.762492 # average overall miss latency
1257system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 68369.069514 # average overall miss latency
1258system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 27215.878200 # average overall miss latency
1259system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 39858.154993 # average overall miss latency
1260system.cpu0.l2cache.demand_avg_miss_latency::total 38388.754211 # average overall miss latency
1261system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 47813.762492 # average overall miss latency
1262system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 68369.069514 # average overall miss latency
1263system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 27215.878200 # average overall miss latency
1264system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 39858.154993 # average overall miss latency
1265system.cpu0.l2cache.overall_avg_miss_latency::total 38388.754211 # average overall miss latency
1266system.cpu0.l2cache.blocked_cycles::no_mshrs 218783 # number of cycles access was blocked
1267system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1268system.cpu0.l2cache.blocked::no_mshrs 9480 # number of cycles access was blocked
1269system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1270system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 23.078376 # average number of cycles each access was blocked
1271system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1272system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1273system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1274system.cpu0.l2cache.writebacks::writebacks 1237814 # number of writebacks
1275system.cpu0.l2cache.writebacks::total 1237814 # number of writebacks
1276system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits
1277system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 175 # number of ReadReq MSHR hits
1278system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 63962 # number of ReadReq MSHR hits
1279system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 31981 # number of ReadReq MSHR hits
1280system.cpu0.l2cache.ReadReq_mshr_hits::total 96119 # number of ReadReq MSHR hits
1281system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 46326 # number of ReadExReq MSHR hits
1282system.cpu0.l2cache.ReadExReq_mshr_hits::total 46326 # number of ReadExReq MSHR hits
1283system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits
1284system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 175 # number of demand (read+write) MSHR hits
1285system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 63962 # number of demand (read+write) MSHR hits
1286system.cpu0.l2cache.demand_mshr_hits::cpu0.data 78307 # number of demand (read+write) MSHR hits
1287system.cpu0.l2cache.demand_mshr_hits::total 142445 # number of demand (read+write) MSHR hits
1288system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits
1289system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 175 # number of overall MSHR hits
1290system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 63962 # number of overall MSHR hits
1291system.cpu0.l2cache.overall_mshr_hits::cpu0.data 78307 # number of overall MSHR hits
1292system.cpu0.l2cache.overall_mshr_hits::total 142445 # number of overall MSHR hits
1293system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 16369 # number of ReadReq MSHR misses
1294system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 12772 # number of ReadReq MSHR misses
1295system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 182722 # number of ReadReq MSHR misses
1296system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 1170232 # number of ReadReq MSHR misses
1297system.cpu0.l2cache.ReadReq_mshr_misses::total 1382095 # number of ReadReq MSHR misses
1298system.cpu0.l2cache.Writeback_mshr_misses::writebacks 9 # number of Writeback MSHR misses
1299system.cpu0.l2cache.Writeback_mshr_misses::total 9 # number of Writeback MSHR misses
1300system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 2973803 # number of HardPFReq MSHR misses
1301system.cpu0.l2cache.HardPFReq_mshr_misses::total 2973803 # number of HardPFReq MSHR misses
1302system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 131869 # number of UpgradeReq MSHR misses
1303system.cpu0.l2cache.UpgradeReq_mshr_misses::total 131869 # number of UpgradeReq MSHR misses
1304system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 175118 # number of SCUpgradeReq MSHR misses
1305system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 175118 # number of SCUpgradeReq MSHR misses
1306system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 18 # number of SCUpgradeFailReq MSHR misses
1307system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 18 # number of SCUpgradeFailReq MSHR misses
1308system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 258012 # number of ReadExReq MSHR misses
1309system.cpu0.l2cache.ReadExReq_mshr_misses::total 258012 # number of ReadExReq MSHR misses
1310system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 16369 # number of demand (read+write) MSHR misses
1311system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 12772 # number of demand (read+write) MSHR misses
1312system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 182722 # number of demand (read+write) MSHR misses
1313system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1428244 # number of demand (read+write) MSHR misses
1314system.cpu0.l2cache.demand_mshr_misses::total 1640107 # number of demand (read+write) MSHR misses
1315system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 16369 # number of overall MSHR misses
1316system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 12772 # number of overall MSHR misses
1317system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 182722 # number of overall MSHR misses
1318system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1428244 # number of overall MSHR misses
1319system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 2973803 # number of overall MSHR misses
1320system.cpu0.l2cache.overall_mshr_misses::total 4613910 # number of overall MSHR misses
1321system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 666806046 # number of ReadReq MSHR miss cycles
1322system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 787298272 # number of ReadReq MSHR miss cycles
1323system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 4308962053 # number of ReadReq MSHR miss cycles
1324system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 35252745968 # number of ReadReq MSHR miss cycles
1325system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 41015812339 # number of ReadReq MSHR miss cycles
1326system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 105871670375 # number of HardPFReq MSHR miss cycles
1327system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 105871670375 # number of HardPFReq MSHR miss cycles
1328system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 49106078519 # number of WriteInvalidateReq MSHR miss cycles
1329system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 49106078519 # number of WriteInvalidateReq MSHR miss cycles
1330system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2297414257 # number of UpgradeReq MSHR miss cycles
1331system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2297414257 # number of UpgradeReq MSHR miss cycles
1332system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2423172140 # number of SCUpgradeReq MSHR miss cycles
1333system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2423172140 # number of SCUpgradeReq MSHR miss cycles
1334system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 3259499 # number of SCUpgradeFailReq MSHR miss cycles
1335system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3259499 # number of SCUpgradeFailReq MSHR miss cycles
1336system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10568500938 # number of ReadExReq MSHR miss cycles
1337system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10568500938 # number of ReadExReq MSHR miss cycles
1338system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 666806046 # number of demand (read+write) MSHR miss cycles
1339system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 787298272 # number of demand (read+write) MSHR miss cycles
1340system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 4308962053 # number of demand (read+write) MSHR miss cycles
1341system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 45821246906 # number of demand (read+write) MSHR miss cycles
1342system.cpu0.l2cache.demand_mshr_miss_latency::total 51584313277 # number of demand (read+write) MSHR miss cycles
1343system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 666806046 # number of overall MSHR miss cycles
1344system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 787298272 # number of overall MSHR miss cycles
1345system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 4308962053 # number of overall MSHR miss cycles
1346system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 45821246906 # number of overall MSHR miss cycles
1347system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 105871670375 # number of overall MSHR miss cycles
1348system.cpu0.l2cache.overall_mshr_miss_latency::total 157455983652 # number of overall MSHR miss cycles
1349system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1519173000 # number of ReadReq MSHR uncacheable cycles
1350system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5544879586 # number of ReadReq MSHR uncacheable cycles
1351system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7064052586 # number of ReadReq MSHR uncacheable cycles
1352system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5346512529 # number of WriteReq MSHR uncacheable cycles
1353system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5346512529 # number of WriteReq MSHR uncacheable cycles
1354system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1519173000 # number of overall MSHR uncacheable cycles
1355system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10891392115 # number of overall MSHR uncacheable cycles
1356system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12410565115 # number of overall MSHR uncacheable cycles
1357system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.026536 # mshr miss rate for ReadReq accesses
1358system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.066288 # mshr miss rate for ReadReq accesses
1359system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.028093 # mshr miss rate for ReadReq accesses
1360system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.266067 # mshr miss rate for ReadReq accesses
1361system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.118006 # mshr miss rate for ReadReq accesses
1362system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000003 # mshr miss rate for Writeback accesses
1363system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000003 # mshr miss rate for Writeback accesses
1364system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1365system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1366system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.524845 # mshr miss rate for UpgradeReq accesses
1367system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.524845 # mshr miss rate for UpgradeReq accesses
1368system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.818029 # mshr miss rate for SCUpgradeReq accesses
1369system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.818029 # mshr miss rate for SCUpgradeReq accesses
1370system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1371system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1372system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.200020 # mshr miss rate for ReadExReq accesses
1373system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.200020 # mshr miss rate for ReadExReq accesses
1374system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.026536 # mshr miss rate for demand accesses
1375system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.066288 # mshr miss rate for demand accesses
1376system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.028093 # mshr miss rate for demand accesses
1377system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.251089 # mshr miss rate for demand accesses
1378system.cpu0.l2cache.demand_mshr_miss_rate::total 0.126143 # mshr miss rate for demand accesses
1379system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.026536 # mshr miss rate for overall accesses
1380system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.066288 # mshr miss rate for overall accesses
1381system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.028093 # mshr miss rate for overall accesses
1382system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.251089 # mshr miss rate for overall accesses
1383system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1384system.cpu0.l2cache.overall_mshr_miss_rate::total 0.354862 # mshr miss rate for overall accesses
1385system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40735.906042 # average ReadReq mshr miss latency
1386system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 61642.520514 # average ReadReq mshr miss latency
1387system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23582.064847 # average ReadReq mshr miss latency
1388system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 30124.578689 # average ReadReq mshr miss latency
1389system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29676.550699 # average ReadReq mshr miss latency
1390system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 35601.440437 # average HardPFReq mshr miss latency
1391system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 35601.440437 # average HardPFReq mshr miss latency
1392system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency
1393system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
1394system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17421.943421 # average UpgradeReq mshr miss latency
1395system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17421.943421 # average UpgradeReq mshr miss latency
1396system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13837.367604 # average SCUpgradeReq mshr miss latency
1397system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13837.367604 # average SCUpgradeReq mshr miss latency
1398system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 181083.277778 # average SCUpgradeFailReq mshr miss latency
1399system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 181083.277778 # average SCUpgradeFailReq mshr miss latency
1400system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40961.276755 # average ReadExReq mshr miss latency
1401system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40961.276755 # average ReadExReq mshr miss latency
1402system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40735.906042 # average overall mshr miss latency
1403system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 61642.520514 # average overall mshr miss latency
1404system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23582.064847 # average overall mshr miss latency
1405system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32082.226080 # average overall mshr miss latency
1406system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31451.797521 # average overall mshr miss latency
1407system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40735.906042 # average overall mshr miss latency
1408system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 61642.520514 # average overall mshr miss latency
1409system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23582.064847 # average overall mshr miss latency
1410system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32082.226080 # average overall mshr miss latency
1411system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 35601.440437 # average overall mshr miss latency
1412system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34126.366499 # average overall mshr miss latency
1413system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
1414system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
1415system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1416system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
1417system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1418system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
1419system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
1420system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1421system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1422system.cpu0.toL2Bus.trans_dist::ReadReq 15637085 # Transaction distribution
1423system.cpu0.toL2Bus.trans_dist::ReadResp 12009481 # Transaction distribution
1424system.cpu0.toL2Bus.trans_dist::WriteReq 33046 # Transaction distribution
1425system.cpu0.toL2Bus.trans_dist::WriteResp 33046 # Transaction distribution
1426system.cpu0.toL2Bus.trans_dist::Writeback 3548344 # Transaction distribution
1427system.cpu0.toL2Bus.trans_dist::HardPFReq 4365503 # Transaction distribution
1428system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution
1429system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1683195 # Transaction distribution
1430system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 1040668 # Transaction distribution
1431system.cpu0.toL2Bus.trans_dist::UpgradeReq 461767 # Transaction distribution
1432system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 386684 # Transaction distribution
1433system.cpu0.toL2Bus.trans_dist::UpgradeResp 535373 # Transaction distribution
1434system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 113 # Transaction distribution
1435system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution
1436system.cpu0.toL2Bus.trans_dist::ReadExReq 1436156 # Transaction distribution
1437system.cpu0.toL2Bus.trans_dist::ReadExResp 1297014 # Transaction distribution
1438system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 13051451 # Packet count per connected master and slave (bytes)
1439system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18246800 # Packet count per connected master and slave (bytes)
1440system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 419537 # Packet count per connected master and slave (bytes)
1441system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1341455 # Packet count per connected master and slave (bytes)
1442system.cpu0.toL2Bus.pkt_count::total 33059243 # Packet count per connected master and slave (bytes)
1443system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 416613216 # Cumulative packet size per connected master and slave (bytes)
1444system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 664873226 # Cumulative packet size per connected master and slave (bytes)
1445system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1541384 # Cumulative packet size per connected master and slave (bytes)
1446system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4934904 # Cumulative packet size per connected master and slave (bytes)
1447system.cpu0.toL2Bus.pkt_size::total 1087962730 # Cumulative packet size per connected master and slave (bytes)
1448system.cpu0.toL2Bus.snoops 9586812 # Total snoops (count)
1449system.cpu0.toL2Bus.snoop_fanout::samples 27467610 # Request fanout histogram
1450system.cpu0.toL2Bus.snoop_fanout::mean 5.337349 # Request fanout histogram
1451system.cpu0.toL2Bus.snoop_fanout::stdev 0.472805 # Request fanout histogram
1452system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1453system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1454system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1455system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1456system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
1457system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
1458system.cpu0.toL2Bus.snoop_fanout::5 18201451 66.27% 66.27% # Request fanout histogram
1459system.cpu0.toL2Bus.snoop_fanout::6 9266159 33.73% 100.00% # Request fanout histogram
1460system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1461system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
1462system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
1463system.cpu0.toL2Bus.snoop_fanout::total 27467610 # Request fanout histogram
1464system.cpu0.toL2Bus.reqLayer0.occupancy 13754094390 # Layer occupancy (ticks)
1465system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1466system.cpu0.toL2Bus.snoopLayer0.occupancy 197445482 # Layer occupancy (ticks)
1467system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1468system.cpu0.toL2Bus.respLayer0.occupancy 9792438220 # Layer occupancy (ticks)
1469system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1470system.cpu0.toL2Bus.respLayer1.occupancy 9396795912 # Layer occupancy (ticks)
1471system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1472system.cpu0.toL2Bus.respLayer2.occupancy 228193109 # Layer occupancy (ticks)
1473system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1474system.cpu0.toL2Bus.respLayer3.occupancy 726243001 # Layer occupancy (ticks)
1475system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1476system.cpu1.branchPred.lookups 126883394 # Number of BP lookups
1477system.cpu1.branchPred.condPredicted 85166335 # Number of conditional branches predicted
1478system.cpu1.branchPred.condIncorrect 6223569 # Number of conditional branches incorrect
1479system.cpu1.branchPred.BTBLookups 90014178 # Number of BTB lookups
1480system.cpu1.branchPred.BTBHits 58475937 # Number of BTB hits
1481system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1482system.cpu1.branchPred.BTBHitPct 64.963029 # BTB Hit Percentage
1483system.cpu1.branchPred.usedRAS 16774062 # Number of times the RAS was used to get a target.
1484system.cpu1.branchPred.RASInCorrect 171946 # Number of incorrect RAS predictions.
1485system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1486system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1487system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1488system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1489system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1490system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1491system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1492system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

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1500system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1501system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1502system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1503system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1504system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1505system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1506system.cpu1.dtb.inst_hits 0 # ITB inst hits
1507system.cpu1.dtb.inst_misses 0 # ITB inst misses
1508system.cpu1.dtb.read_hits 93423769 # DTB read hits
1509system.cpu1.dtb.read_misses 385141 # DTB read misses
1510system.cpu1.dtb.write_hits 77506370 # DTB write hits
1511system.cpu1.dtb.write_misses 166753 # DTB write misses
1512system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
1513system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1514system.cpu1.dtb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID
1515system.cpu1.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID
1516system.cpu1.dtb.flush_entries 38053 # Number of entries that have been flushed from TLB
1517system.cpu1.dtb.align_faults 411 # Number of TLB faults due to alignment restrictions
1518system.cpu1.dtb.prefetch_faults 6413 # Number of TLB faults due to prefetch
1519system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1520system.cpu1.dtb.perms_faults 42956 # Number of TLB faults due to permissions restrictions
1521system.cpu1.dtb.read_accesses 93808910 # DTB read accesses
1522system.cpu1.dtb.write_accesses 77673123 # DTB write accesses
1523system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1524system.cpu1.dtb.hits 170930139 # DTB hits
1525system.cpu1.dtb.misses 551894 # DTB misses
1526system.cpu1.dtb.accesses 171482033 # DTB accesses
1527system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
1528system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
1529system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
1530system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
1531system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
1532system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
1533system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
1534system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

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1540system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1541system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1542system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1543system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1544system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1545system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1546system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1547system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1548system.cpu1.itb.inst_hits 200532583 # ITB inst hits
1549system.cpu1.itb.inst_misses 85074 # ITB inst misses
1550system.cpu1.itb.read_hits 0 # DTB read hits
1551system.cpu1.itb.read_misses 0 # DTB read misses
1552system.cpu1.itb.write_hits 0 # DTB write hits
1553system.cpu1.itb.write_misses 0 # DTB write misses
1554system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
1555system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1556system.cpu1.itb.flush_tlb_mva_asid 46078 # Number of times TLB was flushed by MVA & ASID
1557system.cpu1.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID
1558system.cpu1.itb.flush_entries 26827 # Number of entries that have been flushed from TLB
1559system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1560system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1561system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1562system.cpu1.itb.perms_faults 221691 # Number of TLB faults due to permissions restrictions
1563system.cpu1.itb.read_accesses 0 # DTB read accesses
1564system.cpu1.itb.write_accesses 0 # DTB write accesses
1565system.cpu1.itb.inst_accesses 200617657 # ITB inst accesses
1566system.cpu1.itb.hits 200532583 # DTB hits
1567system.cpu1.itb.misses 85074 # DTB misses
1568system.cpu1.itb.accesses 200617657 # DTB accesses
1569system.cpu1.numCycles 671498045 # number of cpu cycles simulated
1570system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1571system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1572system.cpu1.fetch.icacheStallCycles 76057268 # Number of cycles fetch is stalled on an Icache miss
1573system.cpu1.fetch.Insts 563958948 # Number of instructions fetch has processed
1574system.cpu1.fetch.Branches 126883394 # Number of branches that fetch encountered
1575system.cpu1.fetch.predictedBranches 75249999 # Number of branches that fetch has predicted taken
1576system.cpu1.fetch.Cycles 570112426 # Number of cycles fetch has run and was not squashing or blocked
1577system.cpu1.fetch.SquashCycles 13401984 # Number of cycles fetch has spent squashing
1578system.cpu1.fetch.TlbCycles 1796129 # Number of cycles fetch has spent waiting for tlb
1579system.cpu1.fetch.MiscStallCycles 140886 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1580system.cpu1.fetch.PendingTrapStallCycles 6366912 # Number of stall cycles due to pending traps
1581system.cpu1.fetch.PendingQuiesceStallCycles 711415 # Number of stall cycles due to pending quiesce instructions
1582system.cpu1.fetch.IcacheWaitRetryStallCycles 284551 # Number of stall cycles due to full MSHR
1583system.cpu1.fetch.CacheLines 200289545 # Number of cache lines fetched
1584system.cpu1.fetch.IcacheSquashes 1511940 # Number of outstanding Icache misses that were squashed
1585system.cpu1.fetch.ItlbSquashes 28568 # Number of outstanding ITLB misses that were squashed
1586system.cpu1.fetch.rateDist::samples 662170579 # Number of instructions fetched each cycle (Total)
1587system.cpu1.fetch.rateDist::mean 1.001134 # Number of instructions fetched each cycle (Total)
1588system.cpu1.fetch.rateDist::stdev 1.225253 # Number of instructions fetched each cycle (Total)
1589system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1590system.cpu1.fetch.rateDist::0 344731960 52.06% 52.06% # Number of instructions fetched each cycle (Total)
1591system.cpu1.fetch.rateDist::1 123888404 18.71% 70.77% # Number of instructions fetched each cycle (Total)
1592system.cpu1.fetch.rateDist::2 41617512 6.29% 77.06% # Number of instructions fetched each cycle (Total)
1593system.cpu1.fetch.rateDist::3 151932703 22.94% 100.00% # Number of instructions fetched each cycle (Total)
1594system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1595system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1596system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
1597system.cpu1.fetch.rateDist::total 662170579 # Number of instructions fetched each cycle (Total)
1598system.cpu1.fetch.branchRate 0.188956 # Number of branch fetches per cycle
1599system.cpu1.fetch.rate 0.839852 # Number of inst fetches per cycle
1600system.cpu1.decode.IdleCycles 93652150 # Number of cycles decode is idle
1601system.cpu1.decode.BlockedCycles 319101856 # Number of cycles decode is blocked
1602system.cpu1.decode.RunCycles 208055943 # Number of cycles decode is running
1603system.cpu1.decode.UnblockCycles 36600277 # Number of cycles decode is unblocking
1604system.cpu1.decode.SquashCycles 4760353 # Number of cycles decode is squashing
1605system.cpu1.decode.BranchResolved 17735520 # Number of times decode resolved a branch
1606system.cpu1.decode.BranchMispred 1981049 # Number of times decode detected a branch misprediction
1607system.cpu1.decode.DecodedInsts 585316730 # Number of instructions handled by decode
1608system.cpu1.decode.SquashedInsts 21686226 # Number of squashed instructions handled by decode
1609system.cpu1.rename.SquashCycles 4760353 # Number of cycles rename is squashing
1610system.cpu1.rename.IdleCycles 127273008 # Number of cycles rename is idle
1611system.cpu1.rename.BlockCycles 44978505 # Number of cycles rename is blocking
1612system.cpu1.rename.serializeStallCycles 215016897 # count of cycles rename stalled for serializing inst
1613system.cpu1.rename.RunCycles 210494675 # Number of cycles rename is running
1614system.cpu1.rename.UnblockCycles 59647141 # Number of cycles rename is unblocking
1615system.cpu1.rename.RenamedInsts 569572737 # Number of instructions processed by rename
1616system.cpu1.rename.SquashedInsts 5483527 # Number of squashed instructions processed by rename
1617system.cpu1.rename.ROBFullEvents 8310630 # Number of times rename has blocked due to ROB full
1618system.cpu1.rename.IQFullEvents 236317 # Number of times rename has blocked due to IQ full
1619system.cpu1.rename.LQFullEvents 296206 # Number of times rename has blocked due to LQ full
1620system.cpu1.rename.SQFullEvents 25698514 # Number of times rename has blocked due to SQ full
1621system.cpu1.rename.FullRegisterEvents 13591 # Number of times there has been no free registers
1622system.cpu1.rename.RenamedOperands 543172602 # Number of destination operands rename has renamed
1623system.cpu1.rename.RenameLookups 884661173 # Number of register rename lookups that rename has made
1624system.cpu1.rename.int_rename_lookups 673765883 # Number of integer rename lookups
1625system.cpu1.rename.fp_rename_lookups 933137 # Number of floating rename lookups
1626system.cpu1.rename.CommittedMaps 489609146 # Number of HB maps that are committed
1627system.cpu1.rename.UndoneMaps 53563450 # Number of HB maps that are undone due to squashing
1628system.cpu1.rename.serializingInsts 15680851 # count of serializing insts renamed
1629system.cpu1.rename.tempSerializingInsts 13859127 # count of temporary serializing insts renamed
1630system.cpu1.rename.skidInsts 73666324 # count of insts added to the skid buffer
1631system.cpu1.memDep0.insertedLoads 93680638 # Number of loads inserted to the mem dependence unit.
1632system.cpu1.memDep0.insertedStores 80687792 # Number of stores inserted to the mem dependence unit.
1633system.cpu1.memDep0.conflictingLoads 8658535 # Number of conflicting loads.
1634system.cpu1.memDep0.conflictingStores 7660349 # Number of conflicting stores.
1635system.cpu1.iq.iqInstsAdded 547737456 # Number of instructions added to the IQ (excludes non-spec)
1636system.cpu1.iq.iqNonSpecInstsAdded 15869030 # Number of non-speculative instructions added to the IQ
1637system.cpu1.iq.iqInstsIssued 553093233 # Number of instructions issued
1638system.cpu1.iq.iqSquashedInstsIssued 2542275 # Number of squashed instructions issued
1639system.cpu1.iq.iqSquashedInstsExamined 47705580 # Number of squashed instructions iterated over during squash; mainly for profiling
1640system.cpu1.iq.iqSquashedOperandsExamined 32628806 # Number of squashed operands that are examined and possibly removed from graph
1641system.cpu1.iq.iqSquashedNonSpecRemoved 263861 # Number of squashed non-spec instructions that were removed
1642system.cpu1.iq.issued_per_cycle::samples 662170579 # Number of insts issued each cycle
1643system.cpu1.iq.issued_per_cycle::mean 0.835273 # Number of insts issued each cycle
1644system.cpu1.iq.issued_per_cycle::stdev 1.067651 # Number of insts issued each cycle
1645system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1646system.cpu1.iq.issued_per_cycle::0 358036858 54.07% 54.07% # Number of insts issued each cycle
1647system.cpu1.iq.issued_per_cycle::1 130663379 19.73% 73.80% # Number of insts issued each cycle
1648system.cpu1.iq.issued_per_cycle::2 105371554 15.91% 89.72% # Number of insts issued each cycle
1649system.cpu1.iq.issued_per_cycle::3 60712008 9.17% 98.88% # Number of insts issued each cycle
1650system.cpu1.iq.issued_per_cycle::4 7383178 1.11% 100.00% # Number of insts issued each cycle
1651system.cpu1.iq.issued_per_cycle::5 3602 0.00% 100.00% # Number of insts issued each cycle
1652system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
1653system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
1654system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
1655system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1656system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1657system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
1658system.cpu1.iq.issued_per_cycle::total 662170579 # Number of insts issued each cycle
1659system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1660system.cpu1.iq.fu_full::IntAlu 55137578 43.73% 43.73% # attempts to use FU when none available
1661system.cpu1.iq.fu_full::IntMult 43337 0.03% 43.76% # attempts to use FU when none available
1662system.cpu1.iq.fu_full::IntDiv 11462 0.01% 43.77% # attempts to use FU when none available
1663system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.77% # attempts to use FU when none available
1664system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.77% # attempts to use FU when none available
1665system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.77% # attempts to use FU when none available
1666system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.77% # attempts to use FU when none available
1667system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.77% # attempts to use FU when none available
1668system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.77% # attempts to use FU when none available
1669system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.77% # attempts to use FU when none available
1670system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.77% # attempts to use FU when none available
1671system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.77% # attempts to use FU when none available
1672system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.77% # attempts to use FU when none available
1673system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.77% # attempts to use FU when none available
1674system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.77% # attempts to use FU when none available
1675system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.77% # attempts to use FU when none available
1676system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.77% # attempts to use FU when none available
1677system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.77% # attempts to use FU when none available
1678system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.77% # attempts to use FU when none available
1679system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.77% # attempts to use FU when none available
1680system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.77% # attempts to use FU when none available
1681system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.77% # attempts to use FU when none available
1682system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.77% # attempts to use FU when none available
1683system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.77% # attempts to use FU when none available
1684system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.77% # attempts to use FU when none available
1685system.cpu1.iq.fu_full::SimdFloatMisc 21 0.00% 43.77% # attempts to use FU when none available
1686system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.77% # attempts to use FU when none available
1687system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.77% # attempts to use FU when none available
1688system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.77% # attempts to use FU when none available
1689system.cpu1.iq.fu_full::MemRead 33948572 26.92% 70.70% # attempts to use FU when none available
1690system.cpu1.iq.fu_full::MemWrite 36949037 29.30% 100.00% # attempts to use FU when none available
1691system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1692system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1693system.cpu1.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
1694system.cpu1.iq.FU_type_0::IntAlu 376818141 68.13% 68.13% # Type of FU issued
1695system.cpu1.iq.FU_type_0::IntMult 1181294 0.21% 68.34% # Type of FU issued
1696system.cpu1.iq.FU_type_0::IntDiv 70304 0.01% 68.36% # Type of FU issued
1697system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.36% # Type of FU issued
1698system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.36% # Type of FU issued
1699system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.36% # Type of FU issued
1700system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.36% # Type of FU issued
1701system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.36% # Type of FU issued
1702system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.36% # Type of FU issued
1703system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.36% # Type of FU issued
1704system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.36% # Type of FU issued
1705system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.36% # Type of FU issued
1706system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.36% # Type of FU issued
1707system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.36% # Type of FU issued
1708system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.36% # Type of FU issued
1709system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.36% # Type of FU issued
1710system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.36% # Type of FU issued
1711system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.36% # Type of FU issued
1712system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.36% # Type of FU issued
1713system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.36% # Type of FU issued
1714system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.36% # Type of FU issued
1715system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.36% # Type of FU issued
1716system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.36% # Type of FU issued
1717system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.36% # Type of FU issued
1718system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.36% # Type of FU issued
1719system.cpu1.iq.FU_type_0::SimdFloatMisc 78003 0.01% 68.37% # Type of FU issued
1720system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.37% # Type of FU issued
1721system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.37% # Type of FU issued
1722system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.37% # Type of FU issued
1723system.cpu1.iq.FU_type_0::MemRead 96248927 17.40% 85.77% # Type of FU issued
1724system.cpu1.iq.FU_type_0::MemWrite 78696516 14.23% 100.00% # Type of FU issued
1725system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1726system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
1727system.cpu1.iq.FU_type_0::total 553093233 # Type of FU issued
1728system.cpu1.iq.rate 0.823671 # Inst issue rate
1729system.cpu1.iq.fu_busy_cnt 126090007 # FU busy when requested
1730system.cpu1.iq.fu_busy_rate 0.227972 # FU busy rate (busy events/executed inst)
1731system.cpu1.iq.int_inst_queue_reads 1895671563 # Number of integer instruction queue reads
1732system.cpu1.iq.int_inst_queue_writes 610922154 # Number of integer instruction queue writes
1733system.cpu1.iq.int_inst_queue_wakeup_accesses 537423673 # Number of integer instruction queue wakeup accesses
1734system.cpu1.iq.fp_inst_queue_reads 1317762 # Number of floating instruction queue reads
1735system.cpu1.iq.fp_inst_queue_writes 530370 # Number of floating instruction queue writes
1736system.cpu1.iq.fp_inst_queue_wakeup_accesses 489519 # Number of floating instruction queue wakeup accesses
1737system.cpu1.iq.int_alu_accesses 678367586 # Number of integer alu accesses
1738system.cpu1.iq.fp_alu_accesses 815653 # Number of floating point alu accesses
1739system.cpu1.iew.lsq.thread0.forwLoads 2464833 # Number of loads that had data forwarded from stores
1740system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
1741system.cpu1.iew.lsq.thread0.squashedLoads 11666973 # Number of loads squashed
1742system.cpu1.iew.lsq.thread0.ignoredResponses 15967 # Number of memory responses ignored because the instruction is squashed
1743system.cpu1.iew.lsq.thread0.memOrderViolation 141534 # Number of memory ordering violations
1744system.cpu1.iew.lsq.thread0.squashedStores 5620813 # Number of stores squashed
1745system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
1746system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
1747system.cpu1.iew.lsq.thread0.rescheduledLoads 2485085 # Number of loads that were rescheduled
1748system.cpu1.iew.lsq.thread0.cacheBlocked 4066782 # Number of times an access to memory failed due to the cache being blocked
1749system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
1750system.cpu1.iew.iewSquashCycles 4760353 # Number of cycles IEW is squashing
1751system.cpu1.iew.iewBlockCycles 6088373 # Number of cycles IEW is blocking
1752system.cpu1.iew.iewUnblockCycles 2643428 # Number of cycles IEW is unblocking
1753system.cpu1.iew.iewDispatchedInsts 563729528 # Number of instructions dispatched to IQ
1754system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
1755system.cpu1.iew.iewDispLoadInsts 93680638 # Number of dispatched load instructions
1756system.cpu1.iew.iewDispStoreInsts 80687792 # Number of dispatched store instructions
1757system.cpu1.iew.iewDispNonSpecInsts 13644540 # Number of dispatched non-speculative instructions
1758system.cpu1.iew.iewIQFullEvents 61293 # Number of times the IQ has become full, causing a stall
1759system.cpu1.iew.iewLSQFullEvents 2520664 # Number of times the LSQ has become full, causing a stall
1760system.cpu1.iew.memOrderViolationEvents 141534 # Number of memory order violations
1761system.cpu1.iew.predictedTakenIncorrect 1916152 # Number of branches that were predicted taken incorrectly
1762system.cpu1.iew.predictedNotTakenIncorrect 2651693 # Number of branches that were predicted not taken incorrectly
1763system.cpu1.iew.branchMispredicts 4567845 # Number of branch mispredicts detected at execute
1764system.cpu1.iew.iewExecutedInsts 545961284 # Number of executed instructions
1765system.cpu1.iew.iewExecLoadInsts 93419699 # Number of load instructions executed
1766system.cpu1.iew.iewExecSquashedInsts 6590982 # Number of squashed instructions skipped in execute
1767system.cpu1.iew.exec_swp 0 # number of swp insts executed
1768system.cpu1.iew.exec_nop 123042 # number of nop insts executed
1769system.cpu1.iew.exec_refs 170926883 # number of memory reference insts executed
1770system.cpu1.iew.exec_branches 102016204 # Number of branches executed
1771system.cpu1.iew.exec_stores 77507184 # Number of stores executed
1772system.cpu1.iew.exec_rate 0.813050 # Inst execution rate
1773system.cpu1.iew.wb_sent 538581721 # cumulative count of insts sent to commit
1774system.cpu1.iew.wb_count 537913192 # cumulative count of insts written-back
1775system.cpu1.iew.wb_producers 259879872 # num instructions producing a value
1776system.cpu1.iew.wb_consumers 425846883 # num instructions consuming a value
1777system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
1778system.cpu1.iew.wb_rate 0.801064 # insts written-back per cycle
1779system.cpu1.iew.wb_fanout 0.610266 # average fanout of values written-back
1780system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
1781system.cpu1.commit.commitSquashedInsts 44555907 # The number of squashed insts skipped by commit
1782system.cpu1.commit.commitNonSpecStalls 15605169 # The number of times commit has been forced to stall to communicate backwards
1783system.cpu1.commit.branchMispredicts 4282930 # The number of times a branch was mispredicted
1784system.cpu1.commit.committed_per_cycle::samples 653744993 # Number of insts commited each cycle
1785system.cpu1.commit.committed_per_cycle::mean 0.784392 # Number of insts commited each cycle
1786system.cpu1.commit.committed_per_cycle::stdev 1.576833 # Number of insts commited each cycle
1787system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
1788system.cpu1.commit.committed_per_cycle::0 427404365 65.38% 65.38% # Number of insts commited each cycle
1789system.cpu1.commit.committed_per_cycle::1 119117281 18.22% 83.60% # Number of insts commited each cycle
1790system.cpu1.commit.committed_per_cycle::2 49133324 7.52% 91.11% # Number of insts commited each cycle
1791system.cpu1.commit.committed_per_cycle::3 16524443 2.53% 93.64% # Number of insts commited each cycle
1792system.cpu1.commit.committed_per_cycle::4 11998035 1.84% 95.48% # Number of insts commited each cycle
1793system.cpu1.commit.committed_per_cycle::5 8093886 1.24% 96.72% # Number of insts commited each cycle
1794system.cpu1.commit.committed_per_cycle::6 5471403 0.84% 97.55% # Number of insts commited each cycle
1795system.cpu1.commit.committed_per_cycle::7 3473274 0.53% 98.08% # Number of insts commited each cycle
1796system.cpu1.commit.committed_per_cycle::8 12528982 1.92% 100.00% # Number of insts commited each cycle
1797system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
1798system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
1799system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
1800system.cpu1.commit.committed_per_cycle::total 653744993 # Number of insts commited each cycle
1801system.cpu1.commit.committedInsts 435068948 # Number of instructions committed
1802system.cpu1.commit.committedOps 512792020 # Number of ops (including micro ops) committed
1803system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
1804system.cpu1.commit.refs 157080643 # Number of memory references committed
1805system.cpu1.commit.loads 82013664 # Number of loads committed
1806system.cpu1.commit.membars 3580423 # Number of memory barriers committed
1807system.cpu1.commit.branches 96770677 # Number of branches committed
1808system.cpu1.commit.fp_insts 477739 # Number of committed floating point instructions.
1809system.cpu1.commit.int_insts 470356347 # Number of committed integer instructions.
1810system.cpu1.commit.function_calls 12430117 # Number of function calls committed.
1811system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
1812system.cpu1.commit.op_class_0::IntAlu 354618766 69.15% 69.15% # Class of committed instruction
1813system.cpu1.commit.op_class_0::IntMult 966577 0.19% 69.34% # Class of committed instruction
1814system.cpu1.commit.op_class_0::IntDiv 56200 0.01% 69.35% # Class of committed instruction
1815system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.35% # Class of committed instruction
1816system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.35% # Class of committed instruction
1817system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.35% # Class of committed instruction
1818system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.35% # Class of committed instruction
1819system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.35% # Class of committed instruction
1820system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.35% # Class of committed instruction
1821system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.35% # Class of committed instruction
1822system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.35% # Class of committed instruction
1823system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.35% # Class of committed instruction
1824system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.35% # Class of committed instruction
1825system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.35% # Class of committed instruction
1826system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.35% # Class of committed instruction
1827system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.35% # Class of committed instruction
1828system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.35% # Class of committed instruction
1829system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.35% # Class of committed instruction
1830system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.35% # Class of committed instruction
1831system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.35% # Class of committed instruction
1832system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.35% # Class of committed instruction
1833system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.35% # Class of committed instruction
1834system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.35% # Class of committed instruction
1835system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.35% # Class of committed instruction
1836system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.35% # Class of committed instruction
1837system.cpu1.commit.op_class_0::SimdFloatMisc 69792 0.01% 69.37% # Class of committed instruction
1838system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.37% # Class of committed instruction
1839system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.37% # Class of committed instruction
1840system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.37% # Class of committed instruction
1841system.cpu1.commit.op_class_0::MemRead 82013664 15.99% 85.36% # Class of committed instruction
1842system.cpu1.commit.op_class_0::MemWrite 75066979 14.64% 100.00% # Class of committed instruction
1843system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
1844system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
1845system.cpu1.commit.op_class_0::total 512792020 # Class of committed instruction
1846system.cpu1.commit.bw_lim_events 12528982 # number cycles where commit BW limit reached
1847system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
1848system.cpu1.rob.rob_reads 1194813735 # The number of ROB reads
1849system.cpu1.rob.rob_writes 1123082959 # The number of ROB writes
1850system.cpu1.timesIdled 724798 # Number of times that the entire CPU went into an idle state and unscheduled itself
1851system.cpu1.idleCycles 9327466 # Total number of cycles that the CPU has spent unscheduled due to idling
1852system.cpu1.quiesceCycles 94087851225 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
1853system.cpu1.committedInsts 435068948 # Number of Instructions Simulated
1854system.cpu1.committedOps 512792020 # Number of Ops (including micro ops) Simulated
1855system.cpu1.cpi 1.543429 # CPI: Cycles Per Instruction
1856system.cpu1.cpi_total 1.543429 # CPI: Total CPI of All Threads
1857system.cpu1.ipc 0.647908 # IPC: Instructions Per Cycle
1858system.cpu1.ipc_total 0.647908 # IPC: Total IPC of All Threads
1859system.cpu1.int_regfile_reads 645605353 # number of integer regfile reads
1860system.cpu1.int_regfile_writes 381721004 # number of integer regfile writes
1861system.cpu1.fp_regfile_reads 775313 # number of floating regfile reads
1862system.cpu1.fp_regfile_writes 445860 # number of floating regfile writes
1863system.cpu1.cc_regfile_reads 118711593 # number of cc regfile reads
1864system.cpu1.cc_regfile_writes 119446570 # number of cc regfile writes
1865system.cpu1.misc_regfile_reads 2680324661 # number of misc regfile reads
1866system.cpu1.misc_regfile_writes 15740060 # number of misc regfile writes
1867system.cpu1.dcache.tags.replacements 5270583 # number of replacements
1868system.cpu1.dcache.tags.tagsinuse 418.735038 # Cycle average of tags in use
1869system.cpu1.dcache.tags.total_refs 145844611 # Total number of references to valid blocks.
1870system.cpu1.dcache.tags.sampled_refs 5271093 # Sample count of references to valid blocks.
1871system.cpu1.dcache.tags.avg_refs 27.668761 # Average number of references to valid blocks.
1872system.cpu1.dcache.tags.warmup_cycle 8472891797000 # Cycle when the warmup percentage was hit.
1873system.cpu1.dcache.tags.occ_blocks::cpu1.data 418.735038 # Average occupied blocks per requestor
1874system.cpu1.dcache.tags.occ_percent::cpu1.data 0.817842 # Average percentage of cache occupancy
1875system.cpu1.dcache.tags.occ_percent::total 0.817842 # Average percentage of cache occupancy
1876system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
1877system.cpu1.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
1878system.cpu1.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id
1879system.cpu1.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id
1880system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
1881system.cpu1.dcache.tags.tag_accesses 326008687 # Number of tag accesses
1882system.cpu1.dcache.tags.data_accesses 326008687 # Number of data accesses
1883system.cpu1.dcache.ReadReq_hits::cpu1.data 76031229 # number of ReadReq hits
1884system.cpu1.dcache.ReadReq_hits::total 76031229 # number of ReadReq hits
1885system.cpu1.dcache.WriteReq_hits::cpu1.data 65289331 # number of WriteReq hits
1886system.cpu1.dcache.WriteReq_hits::total 65289331 # number of WriteReq hits
1887system.cpu1.dcache.SoftPFReq_hits::cpu1.data 171825 # number of SoftPFReq hits
1888system.cpu1.dcache.SoftPFReq_hits::total 171825 # number of SoftPFReq hits
1889system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 535551 # number of WriteInvalidateReq hits
1890system.cpu1.dcache.WriteInvalidateReq_hits::total 535551 # number of WriteInvalidateReq hits
1891system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1744878 # number of LoadLockedReq hits
1892system.cpu1.dcache.LoadLockedReq_hits::total 1744878 # number of LoadLockedReq hits
1893system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1734724 # number of StoreCondReq hits
1894system.cpu1.dcache.StoreCondReq_hits::total 1734724 # number of StoreCondReq hits
1895system.cpu1.dcache.demand_hits::cpu1.data 141320560 # number of demand (read+write) hits
1896system.cpu1.dcache.demand_hits::total 141320560 # number of demand (read+write) hits
1897system.cpu1.dcache.overall_hits::cpu1.data 141492385 # number of overall hits
1898system.cpu1.dcache.overall_hits::total 141492385 # number of overall hits
1899system.cpu1.dcache.ReadReq_misses::cpu1.data 6360074 # number of ReadReq misses
1900system.cpu1.dcache.ReadReq_misses::total 6360074 # number of ReadReq misses
1901system.cpu1.dcache.WriteReq_misses::cpu1.data 7315323 # number of WriteReq misses
1902system.cpu1.dcache.WriteReq_misses::total 7315323 # number of WriteReq misses
1903system.cpu1.dcache.SoftPFReq_misses::cpu1.data 690767 # number of SoftPFReq misses
1904system.cpu1.dcache.SoftPFReq_misses::total 690767 # number of SoftPFReq misses
1905system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 239985 # number of LoadLockedReq misses
1906system.cpu1.dcache.LoadLockedReq_misses::total 239985 # number of LoadLockedReq misses
1907system.cpu1.dcache.StoreCondReq_misses::cpu1.data 206300 # number of StoreCondReq misses
1908system.cpu1.dcache.StoreCondReq_misses::total 206300 # number of StoreCondReq misses
1909system.cpu1.dcache.demand_misses::cpu1.data 13675397 # number of demand (read+write) misses
1910system.cpu1.dcache.demand_misses::total 13675397 # number of demand (read+write) misses
1911system.cpu1.dcache.overall_misses::cpu1.data 14366164 # number of overall misses
1912system.cpu1.dcache.overall_misses::total 14366164 # number of overall misses
1913system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96502365280 # number of ReadReq miss cycles
1914system.cpu1.dcache.ReadReq_miss_latency::total 96502365280 # number of ReadReq miss cycles
1915system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 122289774326 # number of WriteReq miss cycles
1916system.cpu1.dcache.WriteReq_miss_latency::total 122289774326 # number of WriteReq miss cycles
1917system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3384586861 # number of LoadLockedReq miss cycles
1918system.cpu1.dcache.LoadLockedReq_miss_latency::total 3384586861 # number of LoadLockedReq miss cycles
1919system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4391846948 # number of StoreCondReq miss cycles
1920system.cpu1.dcache.StoreCondReq_miss_latency::total 4391846948 # number of StoreCondReq miss cycles
1921system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4067000 # number of StoreCondFailReq miss cycles
1922system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4067000 # number of StoreCondFailReq miss cycles
1923system.cpu1.dcache.demand_miss_latency::cpu1.data 218792139606 # number of demand (read+write) miss cycles
1924system.cpu1.dcache.demand_miss_latency::total 218792139606 # number of demand (read+write) miss cycles
1925system.cpu1.dcache.overall_miss_latency::cpu1.data 218792139606 # number of overall miss cycles
1926system.cpu1.dcache.overall_miss_latency::total 218792139606 # number of overall miss cycles
1927system.cpu1.dcache.ReadReq_accesses::cpu1.data 82391303 # number of ReadReq accesses(hits+misses)
1928system.cpu1.dcache.ReadReq_accesses::total 82391303 # number of ReadReq accesses(hits+misses)
1929system.cpu1.dcache.WriteReq_accesses::cpu1.data 72604654 # number of WriteReq accesses(hits+misses)
1930system.cpu1.dcache.WriteReq_accesses::total 72604654 # number of WriteReq accesses(hits+misses)
1931system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 862592 # number of SoftPFReq accesses(hits+misses)
1932system.cpu1.dcache.SoftPFReq_accesses::total 862592 # number of SoftPFReq accesses(hits+misses)
1933system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 535551 # number of WriteInvalidateReq accesses(hits+misses)
1934system.cpu1.dcache.WriteInvalidateReq_accesses::total 535551 # number of WriteInvalidateReq accesses(hits+misses)
1935system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1984863 # number of LoadLockedReq accesses(hits+misses)
1936system.cpu1.dcache.LoadLockedReq_accesses::total 1984863 # number of LoadLockedReq accesses(hits+misses)
1937system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1941024 # number of StoreCondReq accesses(hits+misses)
1938system.cpu1.dcache.StoreCondReq_accesses::total 1941024 # number of StoreCondReq accesses(hits+misses)
1939system.cpu1.dcache.demand_accesses::cpu1.data 154995957 # number of demand (read+write) accesses
1940system.cpu1.dcache.demand_accesses::total 154995957 # number of demand (read+write) accesses
1941system.cpu1.dcache.overall_accesses::cpu1.data 155858549 # number of overall (read+write) accesses
1942system.cpu1.dcache.overall_accesses::total 155858549 # number of overall (read+write) accesses
1943system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.077194 # miss rate for ReadReq accesses
1944system.cpu1.dcache.ReadReq_miss_rate::total 0.077194 # miss rate for ReadReq accesses
1945system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.100756 # miss rate for WriteReq accesses
1946system.cpu1.dcache.WriteReq_miss_rate::total 0.100756 # miss rate for WriteReq accesses
1947system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.800804 # miss rate for SoftPFReq accesses
1948system.cpu1.dcache.SoftPFReq_miss_rate::total 0.800804 # miss rate for SoftPFReq accesses
1949system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120908 # miss rate for LoadLockedReq accesses
1950system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120908 # miss rate for LoadLockedReq accesses
1951system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106284 # miss rate for StoreCondReq accesses
1952system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106284 # miss rate for StoreCondReq accesses
1953system.cpu1.dcache.demand_miss_rate::cpu1.data 0.088231 # miss rate for demand accesses
1954system.cpu1.dcache.demand_miss_rate::total 0.088231 # miss rate for demand accesses
1955system.cpu1.dcache.overall_miss_rate::cpu1.data 0.092174 # miss rate for overall accesses
1956system.cpu1.dcache.overall_miss_rate::total 0.092174 # miss rate for overall accesses
1957system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15173.151331 # average ReadReq miss latency
1958system.cpu1.dcache.ReadReq_avg_miss_latency::total 15173.151331 # average ReadReq miss latency
1959system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16716.934348 # average WriteReq miss latency
1960system.cpu1.dcache.WriteReq_avg_miss_latency::total 16716.934348 # average WriteReq miss latency
1961system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14103.326712 # average LoadLockedReq miss latency
1962system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14103.326712 # average LoadLockedReq miss latency
1963system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21288.642501 # average StoreCondReq miss latency
1964system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21288.642501 # average StoreCondReq miss latency
1965system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
1966system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1967system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15998.960733 # average overall miss latency
1968system.cpu1.dcache.demand_avg_miss_latency::total 15998.960733 # average overall miss latency
1969system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15229.684111 # average overall miss latency
1970system.cpu1.dcache.overall_avg_miss_latency::total 15229.684111 # average overall miss latency
1971system.cpu1.dcache.blocked_cycles::no_mshrs 8615413 # number of cycles access was blocked
1972system.cpu1.dcache.blocked_cycles::no_targets 17976416 # number of cycles access was blocked
1973system.cpu1.dcache.blocked::no_mshrs 462301 # number of cycles access was blocked
1974system.cpu1.dcache.blocked::no_targets 741969 # number of cycles access was blocked
1975system.cpu1.dcache.avg_blocked_cycles::no_mshrs 18.635938 # average number of cycles each access was blocked
1976system.cpu1.dcache.avg_blocked_cycles::no_targets 24.227988 # average number of cycles each access was blocked
1977system.cpu1.dcache.fast_writes 535551 # number of fast writes performed
1978system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1979system.cpu1.dcache.writebacks::writebacks 3043634 # number of writebacks
1980system.cpu1.dcache.writebacks::total 3043634 # number of writebacks
1981system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3366977 # number of ReadReq MSHR hits
1982system.cpu1.dcache.ReadReq_mshr_hits::total 3366977 # number of ReadReq MSHR hits
1983system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5934775 # number of WriteReq MSHR hits
1984system.cpu1.dcache.WriteReq_mshr_hits::total 5934775 # number of WriteReq MSHR hits
1985system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 123858 # number of LoadLockedReq MSHR hits
1986system.cpu1.dcache.LoadLockedReq_mshr_hits::total 123858 # number of LoadLockedReq MSHR hits
1987system.cpu1.dcache.demand_mshr_hits::cpu1.data 9301752 # number of demand (read+write) MSHR hits
1988system.cpu1.dcache.demand_mshr_hits::total 9301752 # number of demand (read+write) MSHR hits
1989system.cpu1.dcache.overall_mshr_hits::cpu1.data 9301752 # number of overall MSHR hits
1990system.cpu1.dcache.overall_mshr_hits::total 9301752 # number of overall MSHR hits
1991system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2993097 # number of ReadReq MSHR misses
1992system.cpu1.dcache.ReadReq_mshr_misses::total 2993097 # number of ReadReq MSHR misses
1993system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1369794 # number of WriteReq MSHR misses
1994system.cpu1.dcache.WriteReq_mshr_misses::total 1369794 # number of WriteReq MSHR misses
1995system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 690691 # number of SoftPFReq MSHR misses
1996system.cpu1.dcache.SoftPFReq_mshr_misses::total 690691 # number of SoftPFReq MSHR misses
1997system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116127 # number of LoadLockedReq MSHR misses
1998system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116127 # number of LoadLockedReq MSHR misses
1999system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 206288 # number of StoreCondReq MSHR misses
2000system.cpu1.dcache.StoreCondReq_mshr_misses::total 206288 # number of StoreCondReq MSHR misses
2001system.cpu1.dcache.demand_mshr_misses::cpu1.data 4362891 # number of demand (read+write) MSHR misses
2002system.cpu1.dcache.demand_mshr_misses::total 4362891 # number of demand (read+write) MSHR misses
2003system.cpu1.dcache.overall_mshr_misses::cpu1.data 5053582 # number of overall MSHR misses
2004system.cpu1.dcache.overall_mshr_misses::total 5053582 # number of overall MSHR misses
2005system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38940153004 # number of ReadReq MSHR miss cycles
2006system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38940153004 # number of ReadReq MSHR miss cycles
2007system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23265516814 # number of WriteReq MSHR miss cycles
2008system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23265516814 # number of WriteReq MSHR miss cycles
2009system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16955467787 # number of SoftPFReq MSHR miss cycles
2010system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16955467787 # number of SoftPFReq MSHR miss cycles
2011system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 29882890933 # number of WriteInvalidateReq MSHR miss cycles
2012system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 29882890933 # number of WriteInvalidateReq MSHR miss cycles
2013system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1431846930 # number of LoadLockedReq MSHR miss cycles
2014system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1431846930 # number of LoadLockedReq MSHR miss cycles
2015system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3970245052 # number of StoreCondReq MSHR miss cycles
2016system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3970245052 # number of StoreCondReq MSHR miss cycles
2017system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3877000 # number of StoreCondFailReq MSHR miss cycles
2018system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3877000 # number of StoreCondFailReq MSHR miss cycles
2019system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62205669818 # number of demand (read+write) MSHR miss cycles
2020system.cpu1.dcache.demand_mshr_miss_latency::total 62205669818 # number of demand (read+write) MSHR miss cycles
2021system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 79161137605 # number of overall MSHR miss cycles
2022system.cpu1.dcache.overall_mshr_miss_latency::total 79161137605 # number of overall MSHR miss cycles
2023system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 568928684 # number of ReadReq MSHR uncacheable cycles
2024system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 568928684 # number of ReadReq MSHR uncacheable cycles
2025system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 634602446 # number of WriteReq MSHR uncacheable cycles
2026system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 634602446 # number of WriteReq MSHR uncacheable cycles
2027system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1203531130 # number of overall MSHR uncacheable cycles
2028system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1203531130 # number of overall MSHR uncacheable cycles
2029system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036328 # mshr miss rate for ReadReq accesses
2030system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036328 # mshr miss rate for ReadReq accesses
2031system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018866 # mshr miss rate for WriteReq accesses
2032system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018866 # mshr miss rate for WriteReq accesses
2033system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.800716 # mshr miss rate for SoftPFReq accesses
2034system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.800716 # mshr miss rate for SoftPFReq accesses
2035system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058506 # mshr miss rate for LoadLockedReq accesses
2036system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058506 # mshr miss rate for LoadLockedReq accesses
2037system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106278 # mshr miss rate for StoreCondReq accesses
2038system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106278 # mshr miss rate for StoreCondReq accesses
2039system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028148 # mshr miss rate for demand accesses
2040system.cpu1.dcache.demand_mshr_miss_rate::total 0.028148 # mshr miss rate for demand accesses
2041system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032424 # mshr miss rate for overall accesses
2042system.cpu1.dcache.overall_mshr_miss_rate::total 0.032424 # mshr miss rate for overall accesses
2043system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13009.986981 # average ReadReq mshr miss latency
2044system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13009.986981 # average ReadReq mshr miss latency
2045system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16984.682963 # average WriteReq mshr miss latency
2046system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16984.682963 # average WriteReq mshr miss latency
2047system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24548.557585 # average SoftPFReq mshr miss latency
2048system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24548.557585 # average SoftPFReq mshr miss latency
2049system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency
2050system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
2051system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12330.008783 # average LoadLockedReq mshr miss latency
2052system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12330.008783 # average LoadLockedReq mshr miss latency
2053system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19246.127026 # average StoreCondReq mshr miss latency
2054system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19246.127026 # average StoreCondReq mshr miss latency
2055system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
2056system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2057system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14257.901428 # average overall mshr miss latency
2058system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14257.901428 # average overall mshr miss latency
2059system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15664.361953 # average overall mshr miss latency
2060system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15664.361953 # average overall mshr miss latency
2061system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
2062system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2063system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
2064system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
2065system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
2066system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2067system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2068system.cpu1.icache.tags.replacements 5515063 # number of replacements
2069system.cpu1.icache.tags.tagsinuse 501.927395 # Cycle average of tags in use
2070system.cpu1.icache.tags.total_refs 194540892 # Total number of references to valid blocks.
2071system.cpu1.icache.tags.sampled_refs 5515575 # Sample count of references to valid blocks.
2072system.cpu1.icache.tags.avg_refs 35.271190 # Average number of references to valid blocks.
2073system.cpu1.icache.tags.warmup_cycle 8512592975000 # Cycle when the warmup percentage was hit.
2074system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.927395 # Average occupied blocks per requestor
2075system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980327 # Average percentage of cache occupancy
2076system.cpu1.icache.tags.occ_percent::total 0.980327 # Average percentage of cache occupancy
2077system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2078system.cpu1.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id
2079system.cpu1.icache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id
2080system.cpu1.icache.tags.age_task_id_blocks_1024::2 87 # Occupied blocks per task id
2081system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2082system.cpu1.icache.tags.tag_accesses 406089111 # Number of tag accesses
2083system.cpu1.icache.tags.data_accesses 406089111 # Number of data accesses
2084system.cpu1.icache.ReadReq_hits::cpu1.inst 194540892 # number of ReadReq hits
2085system.cpu1.icache.ReadReq_hits::total 194540892 # number of ReadReq hits
2086system.cpu1.icache.demand_hits::cpu1.inst 194540892 # number of demand (read+write) hits
2087system.cpu1.icache.demand_hits::total 194540892 # number of demand (read+write) hits
2088system.cpu1.icache.overall_hits::cpu1.inst 194540892 # number of overall hits
2089system.cpu1.icache.overall_hits::total 194540892 # number of overall hits
2090system.cpu1.icache.ReadReq_misses::cpu1.inst 5745874 # number of ReadReq misses
2091system.cpu1.icache.ReadReq_misses::total 5745874 # number of ReadReq misses
2092system.cpu1.icache.demand_misses::cpu1.inst 5745874 # number of demand (read+write) misses
2093system.cpu1.icache.demand_misses::total 5745874 # number of demand (read+write) misses
2094system.cpu1.icache.overall_misses::cpu1.inst 5745874 # number of overall misses
2095system.cpu1.icache.overall_misses::total 5745874 # number of overall misses
2096system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 49972720911 # number of ReadReq miss cycles
2097system.cpu1.icache.ReadReq_miss_latency::total 49972720911 # number of ReadReq miss cycles
2098system.cpu1.icache.demand_miss_latency::cpu1.inst 49972720911 # number of demand (read+write) miss cycles
2099system.cpu1.icache.demand_miss_latency::total 49972720911 # number of demand (read+write) miss cycles
2100system.cpu1.icache.overall_miss_latency::cpu1.inst 49972720911 # number of overall miss cycles
2101system.cpu1.icache.overall_miss_latency::total 49972720911 # number of overall miss cycles
2102system.cpu1.icache.ReadReq_accesses::cpu1.inst 200286766 # number of ReadReq accesses(hits+misses)
2103system.cpu1.icache.ReadReq_accesses::total 200286766 # number of ReadReq accesses(hits+misses)
2104system.cpu1.icache.demand_accesses::cpu1.inst 200286766 # number of demand (read+write) accesses
2105system.cpu1.icache.demand_accesses::total 200286766 # number of demand (read+write) accesses
2106system.cpu1.icache.overall_accesses::cpu1.inst 200286766 # number of overall (read+write) accesses
2107system.cpu1.icache.overall_accesses::total 200286766 # number of overall (read+write) accesses
2108system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028688 # miss rate for ReadReq accesses
2109system.cpu1.icache.ReadReq_miss_rate::total 0.028688 # miss rate for ReadReq accesses
2110system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028688 # miss rate for demand accesses
2111system.cpu1.icache.demand_miss_rate::total 0.028688 # miss rate for demand accesses
2112system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028688 # miss rate for overall accesses
2113system.cpu1.icache.overall_miss_rate::total 0.028688 # miss rate for overall accesses
2114system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8697.148756 # average ReadReq miss latency
2115system.cpu1.icache.ReadReq_avg_miss_latency::total 8697.148756 # average ReadReq miss latency
2116system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8697.148756 # average overall miss latency
2117system.cpu1.icache.demand_avg_miss_latency::total 8697.148756 # average overall miss latency
2118system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8697.148756 # average overall miss latency
2119system.cpu1.icache.overall_avg_miss_latency::total 8697.148756 # average overall miss latency
2120system.cpu1.icache.blocked_cycles::no_mshrs 4058036 # number of cycles access was blocked
2121system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2122system.cpu1.icache.blocked::no_mshrs 525950 # number of cycles access was blocked
2123system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
2124system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.715631 # average number of cycles each access was blocked
2125system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2126system.cpu1.icache.fast_writes 0 # number of fast writes performed
2127system.cpu1.icache.cache_copies 0 # number of cache copies performed
2128system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 230295 # number of ReadReq MSHR hits
2129system.cpu1.icache.ReadReq_mshr_hits::total 230295 # number of ReadReq MSHR hits
2130system.cpu1.icache.demand_mshr_hits::cpu1.inst 230295 # number of demand (read+write) MSHR hits
2131system.cpu1.icache.demand_mshr_hits::total 230295 # number of demand (read+write) MSHR hits
2132system.cpu1.icache.overall_mshr_hits::cpu1.inst 230295 # number of overall MSHR hits
2133system.cpu1.icache.overall_mshr_hits::total 230295 # number of overall MSHR hits
2134system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5515579 # number of ReadReq MSHR misses
2135system.cpu1.icache.ReadReq_mshr_misses::total 5515579 # number of ReadReq MSHR misses
2136system.cpu1.icache.demand_mshr_misses::cpu1.inst 5515579 # number of demand (read+write) MSHR misses
2137system.cpu1.icache.demand_mshr_misses::total 5515579 # number of demand (read+write) MSHR misses
2138system.cpu1.icache.overall_mshr_misses::cpu1.inst 5515579 # number of overall MSHR misses
2139system.cpu1.icache.overall_mshr_misses::total 5515579 # number of overall MSHR misses
2140system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 40507461081 # number of ReadReq MSHR miss cycles
2141system.cpu1.icache.ReadReq_mshr_miss_latency::total 40507461081 # number of ReadReq MSHR miss cycles
2142system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 40507461081 # number of demand (read+write) MSHR miss cycles
2143system.cpu1.icache.demand_mshr_miss_latency::total 40507461081 # number of demand (read+write) MSHR miss cycles
2144system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 40507461081 # number of overall MSHR miss cycles
2145system.cpu1.icache.overall_mshr_miss_latency::total 40507461081 # number of overall MSHR miss cycles
2146system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6176248 # number of ReadReq MSHR uncacheable cycles
2147system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6176248 # number of ReadReq MSHR uncacheable cycles
2148system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6176248 # number of overall MSHR uncacheable cycles
2149system.cpu1.icache.overall_mshr_uncacheable_latency::total 6176248 # number of overall MSHR uncacheable cycles
2150system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027538 # mshr miss rate for ReadReq accesses
2151system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027538 # mshr miss rate for ReadReq accesses
2152system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027538 # mshr miss rate for demand accesses
2153system.cpu1.icache.demand_mshr_miss_rate::total 0.027538 # mshr miss rate for demand accesses
2154system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027538 # mshr miss rate for overall accesses
2155system.cpu1.icache.overall_mshr_miss_rate::total 0.027538 # mshr miss rate for overall accesses
2156system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7344.190171 # average ReadReq mshr miss latency
2157system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7344.190171 # average ReadReq mshr miss latency
2158system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7344.190171 # average overall mshr miss latency
2159system.cpu1.icache.demand_avg_mshr_miss_latency::total 7344.190171 # average overall mshr miss latency
2160system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7344.190171 # average overall mshr miss latency
2161system.cpu1.icache.overall_avg_mshr_miss_latency::total 7344.190171 # average overall mshr miss latency
2162system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
2163system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2164system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
2165system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2166system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2167system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 50505684 # number of hwpf identified
2168system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 2064047 # number of hwpf that were already in mshr
2169system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 44628493 # number of hwpf that were already in the cache
2170system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 907161 # number of hwpf that were already in the prefetch queue
2171system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
2172system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 133845 # number of hwpf removed because MSHR allocated
2173system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 2772138 # number of hwpf issued
2174system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 4283124 # number of hwpf spanning a virtual page
2175system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
2176system.cpu1.l2cache.tags.replacements 3436745 # number of replacements
2177system.cpu1.l2cache.tags.tagsinuse 13730.844001 # Cycle average of tags in use
2178system.cpu1.l2cache.tags.total_refs 11600969 # Total number of references to valid blocks.
2179system.cpu1.l2cache.tags.sampled_refs 3452900 # Sample count of references to valid blocks.
2180system.cpu1.l2cache.tags.avg_refs 3.359776 # Average number of references to valid blocks.
2181system.cpu1.l2cache.tags.warmup_cycle 9794240275500 # Cycle when the warmup percentage was hit.
2182system.cpu1.l2cache.tags.occ_blocks::writebacks 4681.996556 # Average occupied blocks per requestor
2183system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 70.505551 # Average occupied blocks per requestor
2184system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 81.585621 # Average occupied blocks per requestor
2185system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 599.676687 # Average occupied blocks per requestor
2186system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2582.188700 # Average occupied blocks per requestor
2187system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 5714.890886 # Average occupied blocks per requestor
2188system.cpu1.l2cache.tags.occ_percent::writebacks 0.285766 # Average percentage of cache occupancy
2189system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004303 # Average percentage of cache occupancy
2190system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004980 # Average percentage of cache occupancy
2191system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.036601 # Average percentage of cache occupancy
2192system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.157604 # Average percentage of cache occupancy
2193system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.348809 # Average percentage of cache occupancy
2194system.cpu1.l2cache.tags.occ_percent::total 0.838064 # Average percentage of cache occupancy
2195system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9001 # Occupied blocks per task id
2196system.cpu1.l2cache.tags.occ_task_id_blocks::1023 85 # Occupied blocks per task id
2197system.cpu1.l2cache.tags.occ_task_id_blocks::1024 7069 # Occupied blocks per task id
2198system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 110 # Occupied blocks per task id
2199system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 838 # Occupied blocks per task id
2200system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 3805 # Occupied blocks per task id
2201system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 2947 # Occupied blocks per task id
2202system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1301 # Occupied blocks per task id
2203system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id
2204system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 61 # Occupied blocks per task id
2205system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id
2206system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id
2207system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
2208system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 786 # Occupied blocks per task id
2209system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 3475 # Occupied blocks per task id
2210system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2116 # Occupied blocks per task id
2211system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 647 # Occupied blocks per task id
2212system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.549377 # Percentage of cache occupancy per task id
2213system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id
2214system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.431458 # Percentage of cache occupancy per task id
2215system.cpu1.l2cache.tags.tag_accesses 248779915 # Number of tag accesses
2216system.cpu1.l2cache.tags.data_accesses 248779915 # Number of data accesses
2217system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 532626 # number of ReadReq hits
2218system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 172045 # number of ReadReq hits
2219system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5284751 # number of ReadReq hits
2220system.cpu1.l2cache.ReadReq_hits::cpu1.data 2703668 # number of ReadReq hits
2221system.cpu1.l2cache.ReadReq_hits::total 8693090 # number of ReadReq hits
2222system.cpu1.l2cache.Writeback_hits::writebacks 3043623 # number of Writeback hits
2223system.cpu1.l2cache.Writeback_hits::total 3043623 # number of Writeback hits
2224system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 90999 # number of UpgradeReq hits
2225system.cpu1.l2cache.UpgradeReq_hits::total 90999 # number of UpgradeReq hits
2226system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 33582 # number of SCUpgradeReq hits
2227system.cpu1.l2cache.SCUpgradeReq_hits::total 33582 # number of SCUpgradeReq hits
2228system.cpu1.l2cache.ReadExReq_hits::cpu1.data 896481 # number of ReadExReq hits
2229system.cpu1.l2cache.ReadExReq_hits::total 896481 # number of ReadExReq hits
2230system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 532626 # number of demand (read+write) hits
2231system.cpu1.l2cache.demand_hits::cpu1.itb.walker 172045 # number of demand (read+write) hits
2232system.cpu1.l2cache.demand_hits::cpu1.inst 5284751 # number of demand (read+write) hits
2233system.cpu1.l2cache.demand_hits::cpu1.data 3600149 # number of demand (read+write) hits
2234system.cpu1.l2cache.demand_hits::total 9589571 # number of demand (read+write) hits
2235system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 532626 # number of overall hits
2236system.cpu1.l2cache.overall_hits::cpu1.itb.walker 172045 # number of overall hits
2237system.cpu1.l2cache.overall_hits::cpu1.inst 5284751 # number of overall hits
2238system.cpu1.l2cache.overall_hits::cpu1.data 3600149 # number of overall hits
2239system.cpu1.l2cache.overall_hits::total 9589571 # number of overall hits
2240system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 15803 # number of ReadReq misses
2241system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 12743 # number of ReadReq misses
2242system.cpu1.l2cache.ReadReq_misses::cpu1.inst 230826 # number of ReadReq misses
2243system.cpu1.l2cache.ReadReq_misses::cpu1.data 1092537 # number of ReadReq misses
2244system.cpu1.l2cache.ReadReq_misses::total 1351909 # number of ReadReq misses
2245system.cpu1.l2cache.Writeback_misses::writebacks 10 # number of Writeback misses
2246system.cpu1.l2cache.Writeback_misses::total 10 # number of Writeback misses
2247system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 129352 # number of UpgradeReq misses
2248system.cpu1.l2cache.UpgradeReq_misses::total 129352 # number of UpgradeReq misses
2249system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 172689 # number of SCUpgradeReq misses
2250system.cpu1.l2cache.SCUpgradeReq_misses::total 172689 # number of SCUpgradeReq misses
2251system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 17 # number of SCUpgradeFailReq misses
2252system.cpu1.l2cache.SCUpgradeFailReq_misses::total 17 # number of SCUpgradeFailReq misses
2253system.cpu1.l2cache.ReadExReq_misses::cpu1.data 259572 # number of ReadExReq misses
2254system.cpu1.l2cache.ReadExReq_misses::total 259572 # number of ReadExReq misses
2255system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 15803 # number of demand (read+write) misses
2256system.cpu1.l2cache.demand_misses::cpu1.itb.walker 12743 # number of demand (read+write) misses
2257system.cpu1.l2cache.demand_misses::cpu1.inst 230826 # number of demand (read+write) misses
2258system.cpu1.l2cache.demand_misses::cpu1.data 1352109 # number of demand (read+write) misses
2259system.cpu1.l2cache.demand_misses::total 1611481 # number of demand (read+write) misses
2260system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 15803 # number of overall misses
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2271system.cpu1.l2cache.UpgradeReq_miss_latency::total 2628732175 # number of UpgradeReq miss cycles
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2285system.cpu1.l2cache.overall_miss_latency::cpu1.inst 5925678894 # number of overall miss cycles
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2293system.cpu1.l2cache.Writeback_accesses::writebacks 3043633 # number of Writeback accesses(hits+misses)
2294system.cpu1.l2cache.Writeback_accesses::total 3043633 # number of Writeback accesses(hits+misses)
2295system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 220351 # number of UpgradeReq accesses(hits+misses)
2296system.cpu1.l2cache.UpgradeReq_accesses::total 220351 # number of UpgradeReq accesses(hits+misses)
2297system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 206271 # number of SCUpgradeReq accesses(hits+misses)
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2314system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.068960 # miss rate for ReadReq accesses
2315system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.041850 # miss rate for ReadReq accesses
2316system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.287797 # miss rate for ReadReq accesses
2317system.cpu1.l2cache.ReadReq_miss_rate::total 0.134585 # miss rate for ReadReq accesses
2318system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000003 # miss rate for Writeback accesses
2319system.cpu1.l2cache.Writeback_miss_rate::total 0.000003 # miss rate for Writeback accesses
2320system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.587027 # miss rate for UpgradeReq accesses
2321system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.587027 # miss rate for UpgradeReq accesses
2322system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.837195 # miss rate for SCUpgradeReq accesses
2323system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.837195 # miss rate for SCUpgradeReq accesses
2324system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2325system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2326system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.224533 # miss rate for ReadExReq accesses
2327system.cpu1.l2cache.ReadExReq_miss_rate::total 0.224533 # miss rate for ReadExReq accesses
2328system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.028815 # miss rate for demand accesses
2329system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.068960 # miss rate for demand accesses
2330system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.041850 # miss rate for demand accesses
2331system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.273029 # miss rate for demand accesses
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2333system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.028815 # miss rate for overall accesses
2334system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.068960 # miss rate for overall accesses
2335system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.041850 # miss rate for overall accesses
2336system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.273029 # miss rate for overall accesses
2337system.cpu1.l2cache.overall_miss_rate::total 0.143869 # miss rate for overall accesses
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2339system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 65202.823432 # average ReadReq miss latency
2340system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 25671.626654 # average ReadReq miss latency
2341system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 33839.443623 # average ReadReq miss latency
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2343system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20322.315658 # average UpgradeReq miss latency
2344system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20322.315658 # average UpgradeReq miss latency
2345system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20137.317791 # average SCUpgradeReq miss latency
2346system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20137.317791 # average SCUpgradeReq miss latency
2347system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 222470.588235 # average SCUpgradeFailReq miss latency
2348system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 222470.588235 # average SCUpgradeFailReq miss latency
2349system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 47147.517213 # average ReadExReq miss latency
2350system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 47147.517213 # average ReadExReq miss latency
2351system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 47951.848573 # average overall miss latency
2352system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 65202.823432 # average overall miss latency
2353system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 25671.626654 # average overall miss latency
2354system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36394.269659 # average overall miss latency
2355system.cpu1.l2cache.demand_avg_miss_latency::total 35199.522111 # average overall miss latency
2356system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 47951.848573 # average overall miss latency
2357system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 65202.823432 # average overall miss latency
2358system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 25671.626654 # average overall miss latency
2359system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36394.269659 # average overall miss latency
2360system.cpu1.l2cache.overall_avg_miss_latency::total 35199.522111 # average overall miss latency
2361system.cpu1.l2cache.blocked_cycles::no_mshrs 100701 # number of cycles access was blocked
2362system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2363system.cpu1.l2cache.blocked::no_mshrs 5340 # number of cycles access was blocked
2364system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2365system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 18.857865 # average number of cycles each access was blocked
2366system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2367system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2368system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2369system.cpu1.l2cache.writebacks::writebacks 1046487 # number of writebacks
2370system.cpu1.l2cache.writebacks::total 1046487 # number of writebacks
2371system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 8 # number of ReadReq MSHR hits
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2373system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 60238 # number of ReadReq MSHR hits
2374system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 6632 # number of ReadReq MSHR hits
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2376system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 32310 # number of ReadExReq MSHR hits
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2378system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 8 # number of demand (read+write) MSHR hits
2379system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 151 # number of demand (read+write) MSHR hits
2380system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 60238 # number of demand (read+write) MSHR hits
2381system.cpu1.l2cache.demand_mshr_hits::cpu1.data 38942 # number of demand (read+write) MSHR hits
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2384system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 151 # number of overall MSHR hits
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2393system.cpu1.l2cache.Writeback_mshr_misses::writebacks 10 # number of Writeback MSHR misses
2394system.cpu1.l2cache.Writeback_mshr_misses::total 10 # number of Writeback MSHR misses
2395system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 2771770 # number of HardPFReq MSHR misses
2396system.cpu1.l2cache.HardPFReq_mshr_misses::total 2771770 # number of HardPFReq MSHR misses
2397system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 129352 # number of UpgradeReq MSHR misses
2398system.cpu1.l2cache.UpgradeReq_mshr_misses::total 129352 # number of UpgradeReq MSHR misses
2399system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 172689 # number of SCUpgradeReq MSHR misses
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2401system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 17 # number of SCUpgradeFailReq MSHR misses
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2405system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 15795 # number of demand (read+write) MSHR misses
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2408system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1313167 # number of demand (read+write) MSHR misses
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2410system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 15795 # number of overall MSHR misses
2411system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 12592 # number of overall MSHR misses
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2413system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1313167 # number of overall MSHR misses
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2418system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 3707806163 # number of ReadReq MSHR miss cycles
2419system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 29075430940 # number of ReadReq MSHR miss cycles
2420system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 34162743693 # number of ReadReq MSHR miss cycles
2421system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 88845492183 # number of HardPFReq MSHR miss cycles
2422system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 88845492183 # number of HardPFReq MSHR miss cycles
2423system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 25545271269 # number of WriteInvalidateReq MSHR miss cycles
2424system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 25545271269 # number of WriteInvalidateReq MSHR miss cycles
2425system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2271880441 # number of UpgradeReq MSHR miss cycles
2426system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2271880441 # number of UpgradeReq MSHR miss cycles
2427system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2355036377 # number of SCUpgradeReq MSHR miss cycles
2428system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2355036377 # number of SCUpgradeReq MSHR miss cycles
2429system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3117000 # number of SCUpgradeFailReq MSHR miss cycles
2430system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3117000 # number of SCUpgradeFailReq MSHR miss cycles
2431system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8386609809 # number of ReadExReq MSHR miss cycles
2432system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8386609809 # number of ReadExReq MSHR miss cycles
2433system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 645813787 # number of demand (read+write) MSHR miss cycles
2434system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 733692803 # number of demand (read+write) MSHR miss cycles
2435system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 3707806163 # number of demand (read+write) MSHR miss cycles
2436system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 37462040749 # number of demand (read+write) MSHR miss cycles
2437system.cpu1.l2cache.demand_mshr_miss_latency::total 42549353502 # number of demand (read+write) MSHR miss cycles
2438system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 645813787 # number of overall MSHR miss cycles
2439system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 733692803 # number of overall MSHR miss cycles
2440system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 3707806163 # number of overall MSHR miss cycles
2441system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 37462040749 # number of overall MSHR miss cycles
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2443system.cpu1.l2cache.overall_mshr_miss_latency::total 131394845685 # number of overall MSHR miss cycles
2444system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5617250 # number of ReadReq MSHR uncacheable cycles
2445system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 522273803 # number of ReadReq MSHR uncacheable cycles
2446system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 527891053 # number of ReadReq MSHR uncacheable cycles
2447system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 592984543 # number of WriteReq MSHR uncacheable cycles
2448system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 592984543 # number of WriteReq MSHR uncacheable cycles
2449system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 5617250 # number of overall MSHR uncacheable cycles
2450system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1115258346 # number of overall MSHR uncacheable cycles
2451system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1120875596 # number of overall MSHR uncacheable cycles
2452system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028800 # mshr miss rate for ReadReq accesses
2453system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.068143 # mshr miss rate for ReadReq accesses
2454system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.030928 # mshr miss rate for ReadReq accesses
2455system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.286050 # mshr miss rate for ReadReq accesses
2456system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.127912 # mshr miss rate for ReadReq accesses
2457system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000003 # mshr miss rate for Writeback accesses
2458system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000003 # mshr miss rate for Writeback accesses
2459system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2460system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2461system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.587027 # mshr miss rate for UpgradeReq accesses
2462system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.587027 # mshr miss rate for UpgradeReq accesses
2463system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.837195 # mshr miss rate for SCUpgradeReq accesses
2464system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.837195 # mshr miss rate for SCUpgradeReq accesses
2465system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2466system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2467system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.196584 # mshr miss rate for ReadExReq accesses
2468system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.196584 # mshr miss rate for ReadExReq accesses
2469system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028800 # mshr miss rate for demand accesses
2470system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.068143 # mshr miss rate for demand accesses
2471system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.030928 # mshr miss rate for demand accesses
2472system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.265165 # mshr miss rate for demand accesses
2473system.cpu1.l2cache.demand_mshr_miss_rate::total 0.135000 # mshr miss rate for demand accesses
2474system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028800 # mshr miss rate for overall accesses
2475system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.068143 # mshr miss rate for overall accesses
2476system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.030928 # mshr miss rate for overall accesses
2477system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.265165 # mshr miss rate for overall accesses
2478system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2479system.cpu1.l2cache.overall_mshr_miss_rate::total 0.382456 # mshr miss rate for overall accesses
2480system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40887.229313 # average ReadReq mshr miss latency
2481system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 58266.582195 # average ReadReq mshr miss latency
2482system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21735.445418 # average ReadReq mshr miss latency
2483system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26775.298889 # average ReadReq mshr miss latency
2484system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 26588.275709 # average ReadReq mshr miss latency
2485system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 32053.702935 # average HardPFReq mshr miss latency
2486system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 32053.702935 # average HardPFReq mshr miss latency
2487system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency
2488system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
2489system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17563.550939 # average UpgradeReq mshr miss latency
2490system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17563.550939 # average UpgradeReq mshr miss latency
2491system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13637.442900 # average SCUpgradeReq mshr miss latency
2492system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13637.442900 # average SCUpgradeReq mshr miss latency
2493system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 183352.941176 # average SCUpgradeFailReq mshr miss latency
2494system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183352.941176 # average SCUpgradeFailReq mshr miss latency
2495system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36902.824973 # average ReadExReq mshr miss latency
2496system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36902.824973 # average ReadExReq mshr miss latency
2497system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40887.229313 # average overall mshr miss latency
2498system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 58266.582195 # average overall mshr miss latency
2499system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21735.445418 # average overall mshr miss latency
2500system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28528.009575 # average overall mshr miss latency
2501system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 28138.464180 # average overall mshr miss latency
2502system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40887.229313 # average overall mshr miss latency
2503system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 58266.582195 # average overall mshr miss latency
2504system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21735.445418 # average overall mshr miss latency
2505system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28528.009575 # average overall mshr miss latency
2506system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 32053.702935 # average overall mshr miss latency
2507system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30671.695797 # average overall mshr miss latency
2508system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
2509system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
2510system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
2511system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
2512system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
2513system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
2514system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
2515system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
2516system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2517system.cpu1.toL2Bus.trans_dist::ReadReq 14195138 # Transaction distribution
2518system.cpu1.toL2Bus.trans_dist::ReadResp 10319504 # Transaction distribution
2519system.cpu1.toL2Bus.trans_dist::WriteReq 5540 # Transaction distribution
2520system.cpu1.toL2Bus.trans_dist::WriteResp 5540 # Transaction distribution
2521system.cpu1.toL2Bus.trans_dist::Writeback 3043633 # Transaction distribution
2522system.cpu1.toL2Bus.trans_dist::HardPFReq 4072942 # Transaction distribution
2523system.cpu1.toL2Bus.trans_dist::HardPFResp 7 # Transaction distribution
2524system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1683351 # Transaction distribution
2525system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 535551 # Transaction distribution
2526system.cpu1.toL2Bus.trans_dist::UpgradeReq 440112 # Transaction distribution
2527system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 381311 # Transaction distribution
2528system.cpu1.toL2Bus.trans_dist::UpgradeResp 495883 # Transaction distribution
2529system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 113 # Transaction distribution
2530system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution
2531system.cpu1.toL2Bus.trans_dist::ReadExReq 1326326 # Transaction distribution
2532system.cpu1.toL2Bus.trans_dist::ReadExResp 1162072 # Transaction distribution
2533system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11031290 # Packet count per connected master and slave (bytes)
2534system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15072798 # Packet count per connected master and slave (bytes)
2535system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 408972 # Packet count per connected master and slave (bytes)
2536system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1223990 # Packet count per connected master and slave (bytes)
2537system.cpu1.toL2Bus.pkt_count::total 27737050 # Packet count per connected master and slave (bytes)
2538system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 352998000 # Cumulative packet size per connected master and slave (bytes)
2539system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 552975725 # Cumulative packet size per connected master and slave (bytes)
2540system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1478304 # Cumulative packet size per connected master and slave (bytes)
2541system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4387432 # Cumulative packet size per connected master and slave (bytes)
2542system.cpu1.toL2Bus.pkt_size::total 911839461 # Cumulative packet size per connected master and slave (bytes)
2543system.cpu1.toL2Bus.snoops 10107713 # Total snoops (count)
2544system.cpu1.toL2Bus.snoop_fanout::samples 25138246 # Request fanout histogram
2545system.cpu1.toL2Bus.snoop_fanout::mean 5.388398 # Request fanout histogram
2546system.cpu1.toL2Bus.snoop_fanout::stdev 0.487386 # Request fanout histogram
2547system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2548system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2549system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
2550system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
2551system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
2552system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
2553system.cpu1.toL2Bus.snoop_fanout::5 15374612 61.16% 61.16% # Request fanout histogram
2554system.cpu1.toL2Bus.snoop_fanout::6 9763634 38.84% 100.00% # Request fanout histogram
2555system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2556system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
2557system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
2558system.cpu1.toL2Bus.snoop_fanout::total 25138246 # Request fanout histogram
2559system.cpu1.toL2Bus.reqLayer0.occupancy 11278575992 # Layer occupancy (ticks)
2560system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2561system.cpu1.toL2Bus.snoopLayer0.occupancy 196968741 # Layer occupancy (ticks)
2562system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2563system.cpu1.toL2Bus.respLayer0.occupancy 8281966249 # Layer occupancy (ticks)
2564system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2565system.cpu1.toL2Bus.respLayer1.occupancy 7967439656 # Layer occupancy (ticks)
2566system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2567system.cpu1.toL2Bus.respLayer2.occupancy 225433169 # Layer occupancy (ticks)
2568system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2569system.cpu1.toL2Bus.respLayer3.occupancy 677266087 # Layer occupancy (ticks)
2570system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2571system.iobus.trans_dist::ReadReq 40417 # Transaction distribution
2572system.iobus.trans_dist::ReadResp 40417 # Transaction distribution
2573system.iobus.trans_dist::WriteReq 136643 # Transaction distribution
2574system.iobus.trans_dist::WriteResp 136782 # Transaction distribution
2575system.iobus.trans_dist::WriteInvalidateReq 139 # Transaction distribution
2576system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48150 # Packet count per connected master and slave (bytes)
2577system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2578system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2579system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2580system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2581system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2582system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2583system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2584system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2585system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2586system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
2587system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
2588system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2589system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
2590system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
2591system.iobus.pkt_count_system.bridge.master::total 123084 # Packet count per connected master and slave (bytes)
2592system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231234 # Packet count per connected master and slave (bytes)
2593system.iobus.pkt_count_system.realview.ide.dma::total 231234 # Packet count per connected master and slave (bytes)
2594system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2595system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2596system.iobus.pkt_count::total 354398 # Packet count per connected master and slave (bytes)
2597system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48170 # Cumulative packet size per connected master and slave (bytes)
2598system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2599system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2600system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2601system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2602system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2603system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2604system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2605system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
2606system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2607system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
2608system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
2609system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2610system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
2611system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
2612system.iobus.pkt_size_system.bridge.master::total 156191 # Cumulative packet size per connected master and slave (bytes)
2613system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338952 # Cumulative packet size per connected master and slave (bytes)
2614system.iobus.pkt_size_system.realview.ide.dma::total 7338952 # Cumulative packet size per connected master and slave (bytes)
2615system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
2616system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2617system.iobus.pkt_size::total 7497229 # Cumulative packet size per connected master and slave (bytes)
2618system.iobus.reqLayer0.occupancy 36599000 # Layer occupancy (ticks)
2619system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2620system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
2621system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2622system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
2623system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2624system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
2625system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2626system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)

--- 11 unchanged lines hidden (view full) ---

2638system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks)
2639system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2640system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
2641system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2642system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
2643system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2644system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
2645system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2646system.iobus.reqLayer27.occupancy 982013630 # Layer occupancy (ticks)
2647system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2648system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
2649system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
2650system.iobus.respLayer0.occupancy 93033000 # Layer occupancy (ticks)
2651system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2652system.iobus.respLayer3.occupancy 179230570 # Layer occupancy (ticks)
2653system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2654system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
2655system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2656system.iocache.tags.replacements 115615 # number of replacements
2657system.iocache.tags.tagsinuse 11.386738 # Cycle average of tags in use
2658system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2659system.iocache.tags.sampled_refs 115631 # Sample count of references to valid blocks.
2660system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2661system.iocache.tags.warmup_cycle 9111214571000 # Cycle when the warmup percentage was hit.
2662system.iocache.tags.occ_blocks::realview.ethernet 3.838966 # Average occupied blocks per requestor
2663system.iocache.tags.occ_blocks::realview.ide 7.547771 # Average occupied blocks per requestor
2664system.iocache.tags.occ_percent::realview.ethernet 0.239935 # Average percentage of cache occupancy
2665system.iocache.tags.occ_percent::realview.ide 0.471736 # Average percentage of cache occupancy
2666system.iocache.tags.occ_percent::total 0.711671 # Average percentage of cache occupancy
2667system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2668system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2669system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2670system.iocache.tags.tag_accesses 1042022 # Number of tag accesses
2671system.iocache.tags.data_accesses 1042022 # Number of data accesses
2672system.iocache.WriteInvalidateReq_hits::realview.ide 106728 # number of WriteInvalidateReq hits
2673system.iocache.WriteInvalidateReq_hits::total 106728 # number of WriteInvalidateReq hits
2674system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2675system.iocache.ReadReq_misses::realview.ide 8889 # number of ReadReq misses
2676system.iocache.ReadReq_misses::total 8926 # number of ReadReq misses
2677system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2678system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2679system.iocache.WriteInvalidateReq_misses::realview.ide 139 # number of WriteInvalidateReq misses
2680system.iocache.WriteInvalidateReq_misses::total 139 # number of WriteInvalidateReq misses
2681system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2682system.iocache.demand_misses::realview.ide 8889 # number of demand (read+write) misses
2683system.iocache.demand_misses::total 8929 # number of demand (read+write) misses
2684system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2685system.iocache.overall_misses::realview.ide 8889 # number of overall misses
2686system.iocache.overall_misses::total 8929 # number of overall misses
2687system.iocache.ReadReq_miss_latency::realview.ethernet 5695000 # number of ReadReq miss cycles
2688system.iocache.ReadReq_miss_latency::realview.ide 1981823591 # number of ReadReq miss cycles
2689system.iocache.ReadReq_miss_latency::total 1987518591 # number of ReadReq miss cycles
2690system.iocache.WriteReq_miss_latency::realview.ethernet 365000 # number of WriteReq miss cycles
2691system.iocache.WriteReq_miss_latency::total 365000 # number of WriteReq miss cycles
2692system.iocache.demand_miss_latency::realview.ethernet 6060000 # number of demand (read+write) miss cycles
2693system.iocache.demand_miss_latency::realview.ide 1981823591 # number of demand (read+write) miss cycles
2694system.iocache.demand_miss_latency::total 1987883591 # number of demand (read+write) miss cycles
2695system.iocache.overall_miss_latency::realview.ethernet 6060000 # number of overall miss cycles
2696system.iocache.overall_miss_latency::realview.ide 1981823591 # number of overall miss cycles
2697system.iocache.overall_miss_latency::total 1987883591 # number of overall miss cycles
2698system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
2699system.iocache.ReadReq_accesses::realview.ide 8889 # number of ReadReq accesses(hits+misses)
2700system.iocache.ReadReq_accesses::total 8926 # number of ReadReq accesses(hits+misses)
2701system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
2702system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
2703system.iocache.WriteInvalidateReq_accesses::realview.ide 106867 # number of WriteInvalidateReq accesses(hits+misses)
2704system.iocache.WriteInvalidateReq_accesses::total 106867 # number of WriteInvalidateReq accesses(hits+misses)
2705system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
2706system.iocache.demand_accesses::realview.ide 8889 # number of demand (read+write) accesses
2707system.iocache.demand_accesses::total 8929 # number of demand (read+write) accesses
2708system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
2709system.iocache.overall_accesses::realview.ide 8889 # number of overall (read+write) accesses
2710system.iocache.overall_accesses::total 8929 # number of overall (read+write) accesses
2711system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
2712system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
2713system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
2714system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
2715system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
2716system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.001301 # miss rate for WriteInvalidateReq accesses
2717system.iocache.WriteInvalidateReq_miss_rate::total 0.001301 # miss rate for WriteInvalidateReq accesses
2718system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
2719system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
2720system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
2721system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
2722system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
2723system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
2724system.iocache.ReadReq_avg_miss_latency::realview.ethernet 153918.918919 # average ReadReq miss latency
2725system.iocache.ReadReq_avg_miss_latency::realview.ide 222952.367083 # average ReadReq miss latency
2726system.iocache.ReadReq_avg_miss_latency::total 222666.210060 # average ReadReq miss latency
2727system.iocache.WriteReq_avg_miss_latency::realview.ethernet 121666.666667 # average WriteReq miss latency
2728system.iocache.WriteReq_avg_miss_latency::total 121666.666667 # average WriteReq miss latency
2729system.iocache.demand_avg_miss_latency::realview.ethernet 151500 # average overall miss latency
2730system.iocache.demand_avg_miss_latency::realview.ide 222952.367083 # average overall miss latency
2731system.iocache.demand_avg_miss_latency::total 222632.275843 # average overall miss latency
2732system.iocache.overall_avg_miss_latency::realview.ethernet 151500 # average overall miss latency
2733system.iocache.overall_avg_miss_latency::realview.ide 222952.367083 # average overall miss latency
2734system.iocache.overall_avg_miss_latency::total 222632.275843 # average overall miss latency
2735system.iocache.blocked_cycles::no_mshrs 55347 # number of cycles access was blocked
2736system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2737system.iocache.blocked::no_mshrs 5490 # number of cycles access was blocked
2738system.iocache.blocked::no_targets 0 # number of cycles access was blocked
2739system.iocache.avg_blocked_cycles::no_mshrs 10.081421 # average number of cycles each access was blocked
2740system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2741system.iocache.fast_writes 106728 # number of fast writes performed
2742system.iocache.cache_copies 0 # number of cache copies performed
2743system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
2744system.iocache.ReadReq_mshr_misses::realview.ide 8889 # number of ReadReq MSHR misses
2745system.iocache.ReadReq_mshr_misses::total 8926 # number of ReadReq MSHR misses
2746system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
2747system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
2748system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
2749system.iocache.demand_mshr_misses::realview.ide 8889 # number of demand (read+write) MSHR misses
2750system.iocache.demand_mshr_misses::total 8929 # number of demand (read+write) MSHR misses
2751system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
2752system.iocache.overall_mshr_misses::realview.ide 8889 # number of overall MSHR misses
2753system.iocache.overall_mshr_misses::total 8929 # number of overall MSHR misses
2754system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3771000 # number of ReadReq MSHR miss cycles
2755system.iocache.ReadReq_mshr_miss_latency::realview.ide 1519438621 # number of ReadReq MSHR miss cycles
2756system.iocache.ReadReq_mshr_miss_latency::total 1523209621 # number of ReadReq MSHR miss cycles
2757system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 209000 # number of WriteReq MSHR miss cycles
2758system.iocache.WriteReq_mshr_miss_latency::total 209000 # number of WriteReq MSHR miss cycles
2759system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 6630698579 # number of WriteInvalidateReq MSHR miss cycles
2760system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6630698579 # number of WriteInvalidateReq MSHR miss cycles
2761system.iocache.demand_mshr_miss_latency::realview.ethernet 3980000 # number of demand (read+write) MSHR miss cycles
2762system.iocache.demand_mshr_miss_latency::realview.ide 1519438621 # number of demand (read+write) MSHR miss cycles
2763system.iocache.demand_mshr_miss_latency::total 1523418621 # number of demand (read+write) MSHR miss cycles
2764system.iocache.overall_mshr_miss_latency::realview.ethernet 3980000 # number of overall MSHR miss cycles
2765system.iocache.overall_mshr_miss_latency::realview.ide 1519438621 # number of overall MSHR miss cycles
2766system.iocache.overall_mshr_miss_latency::total 1523418621 # number of overall MSHR miss cycles
2767system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
2768system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
2769system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
2770system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
2771system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
2772system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
2773system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
2774system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
2775system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
2776system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
2777system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
2778system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 101918.918919 # average ReadReq mshr miss latency
2779system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 170934.708179 # average ReadReq mshr miss latency
2780system.iocache.ReadReq_avg_mshr_miss_latency::total 170648.624356 # average ReadReq mshr miss latency
2781system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 69666.666667 # average WriteReq mshr miss latency
2782system.iocache.WriteReq_avg_mshr_miss_latency::total 69666.666667 # average WriteReq mshr miss latency
2783system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
2784system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
2785system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99500 # average overall mshr miss latency
2786system.iocache.demand_avg_mshr_miss_latency::realview.ide 170934.708179 # average overall mshr miss latency
2787system.iocache.demand_avg_mshr_miss_latency::total 170614.696047 # average overall mshr miss latency
2788system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99500 # average overall mshr miss latency
2789system.iocache.overall_avg_mshr_miss_latency::realview.ide 170934.708179 # average overall mshr miss latency
2790system.iocache.overall_avg_mshr_miss_latency::total 170614.696047 # average overall mshr miss latency
2791system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
2792system.l2c.tags.replacements 1387044 # number of replacements
2793system.l2c.tags.tagsinuse 64427.808632 # Cycle average of tags in use
2794system.l2c.tags.total_refs 7620997 # Total number of references to valid blocks.
2795system.l2c.tags.sampled_refs 1449367 # Sample count of references to valid blocks.
2796system.l2c.tags.avg_refs 5.258155 # Average number of references to valid blocks.
2797system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2798system.l2c.tags.occ_blocks::writebacks 10003.170740 # Average occupied blocks per requestor
2799system.l2c.tags.occ_blocks::cpu0.dtb.walker 188.441651 # Average occupied blocks per requestor
2800system.l2c.tags.occ_blocks::cpu0.itb.walker 243.424548 # Average occupied blocks per requestor
2801system.l2c.tags.occ_blocks::cpu0.inst 921.507825 # Average occupied blocks per requestor
2802system.l2c.tags.occ_blocks::cpu0.data 8419.959281 # Average occupied blocks per requestor
2803system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 24297.060802 # Average occupied blocks per requestor
2804system.l2c.tags.occ_blocks::cpu1.dtb.walker 189.151688 # Average occupied blocks per requestor
2805system.l2c.tags.occ_blocks::cpu1.itb.walker 259.454485 # Average occupied blocks per requestor
2806system.l2c.tags.occ_blocks::cpu1.inst 442.813505 # Average occupied blocks per requestor
2807system.l2c.tags.occ_blocks::cpu1.data 5057.928398 # Average occupied blocks per requestor
2808system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 14404.895708 # Average occupied blocks per requestor
2809system.l2c.tags.occ_percent::writebacks 0.152636 # Average percentage of cache occupancy
2810system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002875 # Average percentage of cache occupancy
2811system.l2c.tags.occ_percent::cpu0.itb.walker 0.003714 # Average percentage of cache occupancy
2812system.l2c.tags.occ_percent::cpu0.inst 0.014061 # Average percentage of cache occupancy
2813system.l2c.tags.occ_percent::cpu0.data 0.128478 # Average percentage of cache occupancy
2814system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.370744 # Average percentage of cache occupancy
2815system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002886 # Average percentage of cache occupancy
2816system.l2c.tags.occ_percent::cpu1.itb.walker 0.003959 # Average percentage of cache occupancy
2817system.l2c.tags.occ_percent::cpu1.inst 0.006757 # Average percentage of cache occupancy
2818system.l2c.tags.occ_percent::cpu1.data 0.077178 # Average percentage of cache occupancy
2819system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.219801 # Average percentage of cache occupancy
2820system.l2c.tags.occ_percent::total 0.983090 # Average percentage of cache occupancy
2821system.l2c.tags.occ_task_id_blocks::1022 33631 # Occupied blocks per task id
2822system.l2c.tags.occ_task_id_blocks::1023 302 # Occupied blocks per task id
2823system.l2c.tags.occ_task_id_blocks::1024 28390 # Occupied blocks per task id
2824system.l2c.tags.age_task_id_blocks_1022::0 18 # Occupied blocks per task id
2825system.l2c.tags.age_task_id_blocks_1022::1 86 # Occupied blocks per task id
2826system.l2c.tags.age_task_id_blocks_1022::2 2393 # Occupied blocks per task id
2827system.l2c.tags.age_task_id_blocks_1022::3 1787 # Occupied blocks per task id
2828system.l2c.tags.age_task_id_blocks_1022::4 29347 # Occupied blocks per task id
2829system.l2c.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
2830system.l2c.tags.age_task_id_blocks_1023::1 16 # Occupied blocks per task id
2831system.l2c.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id
2832system.l2c.tags.age_task_id_blocks_1023::3 34 # Occupied blocks per task id
2833system.l2c.tags.age_task_id_blocks_1023::4 216 # Occupied blocks per task id
2834system.l2c.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
2835system.l2c.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id
2836system.l2c.tags.age_task_id_blocks_1024::2 2265 # Occupied blocks per task id
2837system.l2c.tags.age_task_id_blocks_1024::3 4264 # Occupied blocks per task id
2838system.l2c.tags.age_task_id_blocks_1024::4 21604 # Occupied blocks per task id
2839system.l2c.tags.occ_task_id_percent::1022 0.513168 # Percentage of cache occupancy per task id
2840system.l2c.tags.occ_task_id_percent::1023 0.004608 # Percentage of cache occupancy per task id
2841system.l2c.tags.occ_task_id_percent::1024 0.433197 # Percentage of cache occupancy per task id
2842system.l2c.tags.tag_accesses 91165244 # Number of tag accesses
2843system.l2c.tags.data_accesses 91165244 # Number of data accesses
2844system.l2c.ReadReq_hits::cpu0.dtb.walker 7553 # number of ReadReq hits
2845system.l2c.ReadReq_hits::cpu0.itb.walker 4301 # number of ReadReq hits
2846system.l2c.ReadReq_hits::cpu0.inst 170694 # number of ReadReq hits
2847system.l2c.ReadReq_hits::cpu0.data 696092 # number of ReadReq hits
2848system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 1825935 # number of ReadReq hits
2849system.l2c.ReadReq_hits::cpu1.dtb.walker 8223 # number of ReadReq hits
2850system.l2c.ReadReq_hits::cpu1.itb.walker 5157 # number of ReadReq hits
2851system.l2c.ReadReq_hits::cpu1.inst 162945 # number of ReadReq hits
2852system.l2c.ReadReq_hits::cpu1.data 691200 # number of ReadReq hits
2853system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1816536 # number of ReadReq hits
2854system.l2c.ReadReq_hits::total 5388636 # number of ReadReq hits
2855system.l2c.Writeback_hits::writebacks 2284318 # number of Writeback hits
2856system.l2c.Writeback_hits::total 2284318 # number of Writeback hits
2857system.l2c.UpgradeReq_hits::cpu0.data 28567 # number of UpgradeReq hits
2858system.l2c.UpgradeReq_hits::cpu1.data 31425 # number of UpgradeReq hits
2859system.l2c.UpgradeReq_hits::total 59992 # number of UpgradeReq hits
2860system.l2c.SCUpgradeReq_hits::cpu0.data 8944 # number of SCUpgradeReq hits
2861system.l2c.SCUpgradeReq_hits::cpu1.data 7440 # number of SCUpgradeReq hits
2862system.l2c.SCUpgradeReq_hits::total 16384 # number of SCUpgradeReq hits
2863system.l2c.ReadExReq_hits::cpu0.data 53362 # number of ReadExReq hits
2864system.l2c.ReadExReq_hits::cpu1.data 53750 # number of ReadExReq hits
2865system.l2c.ReadExReq_hits::total 107112 # number of ReadExReq hits
2866system.l2c.demand_hits::cpu0.dtb.walker 7553 # number of demand (read+write) hits
2867system.l2c.demand_hits::cpu0.itb.walker 4301 # number of demand (read+write) hits
2868system.l2c.demand_hits::cpu0.inst 170694 # number of demand (read+write) hits
2869system.l2c.demand_hits::cpu0.data 749454 # number of demand (read+write) hits
2870system.l2c.demand_hits::cpu0.l2cache.prefetcher 1825935 # number of demand (read+write) hits
2871system.l2c.demand_hits::cpu1.dtb.walker 8223 # number of demand (read+write) hits
2872system.l2c.demand_hits::cpu1.itb.walker 5157 # number of demand (read+write) hits
2873system.l2c.demand_hits::cpu1.inst 162945 # number of demand (read+write) hits
2874system.l2c.demand_hits::cpu1.data 744950 # number of demand (read+write) hits
2875system.l2c.demand_hits::cpu1.l2cache.prefetcher 1816536 # number of demand (read+write) hits
2876system.l2c.demand_hits::total 5495748 # number of demand (read+write) hits
2877system.l2c.overall_hits::cpu0.dtb.walker 7553 # number of overall hits
2878system.l2c.overall_hits::cpu0.itb.walker 4301 # number of overall hits
2879system.l2c.overall_hits::cpu0.inst 170694 # number of overall hits
2880system.l2c.overall_hits::cpu0.data 749454 # number of overall hits
2881system.l2c.overall_hits::cpu0.l2cache.prefetcher 1825935 # number of overall hits
2882system.l2c.overall_hits::cpu1.dtb.walker 8223 # number of overall hits
2883system.l2c.overall_hits::cpu1.itb.walker 5157 # number of overall hits
2884system.l2c.overall_hits::cpu1.inst 162945 # number of overall hits
2885system.l2c.overall_hits::cpu1.data 744950 # number of overall hits
2886system.l2c.overall_hits::cpu1.l2cache.prefetcher 1816536 # number of overall hits
2887system.l2c.overall_hits::total 5495748 # number of overall hits
2888system.l2c.ReadReq_misses::cpu0.dtb.walker 5517 # number of ReadReq misses
2889system.l2c.ReadReq_misses::cpu0.itb.walker 8182 # number of ReadReq misses
2890system.l2c.ReadReq_misses::cpu0.inst 12718 # number of ReadReq misses
2891system.l2c.ReadReq_misses::cpu0.data 197063 # number of ReadReq misses
2892system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 598730 # number of ReadReq misses
2893system.l2c.ReadReq_misses::cpu1.dtb.walker 5285 # number of ReadReq misses
2894system.l2c.ReadReq_misses::cpu1.itb.walker 7231 # number of ReadReq misses
2895system.l2c.ReadReq_misses::cpu1.inst 8328 # number of ReadReq misses
2896system.l2c.ReadReq_misses::cpu1.data 136549 # number of ReadReq misses
2897system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 456002 # number of ReadReq misses
2898system.l2c.ReadReq_misses::total 1435605 # number of ReadReq misses
2899system.l2c.UpgradeReq_misses::cpu0.data 38751 # number of UpgradeReq misses
2900system.l2c.UpgradeReq_misses::cpu1.data 39177 # number of UpgradeReq misses
2901system.l2c.UpgradeReq_misses::total 77928 # number of UpgradeReq misses
2902system.l2c.SCUpgradeReq_misses::cpu0.data 11922 # number of SCUpgradeReq misses
2903system.l2c.SCUpgradeReq_misses::cpu1.data 9604 # number of SCUpgradeReq misses
2904system.l2c.SCUpgradeReq_misses::total 21526 # number of SCUpgradeReq misses
2905system.l2c.ReadExReq_misses::cpu0.data 91592 # number of ReadExReq misses
2906system.l2c.ReadExReq_misses::cpu1.data 67962 # number of ReadExReq misses
2907system.l2c.ReadExReq_misses::total 159554 # number of ReadExReq misses
2908system.l2c.demand_misses::cpu0.dtb.walker 5517 # number of demand (read+write) misses
2909system.l2c.demand_misses::cpu0.itb.walker 8182 # number of demand (read+write) misses
2910system.l2c.demand_misses::cpu0.inst 12718 # number of demand (read+write) misses
2911system.l2c.demand_misses::cpu0.data 288655 # number of demand (read+write) misses
2912system.l2c.demand_misses::cpu0.l2cache.prefetcher 598730 # number of demand (read+write) misses
2913system.l2c.demand_misses::cpu1.dtb.walker 5285 # number of demand (read+write) misses
2914system.l2c.demand_misses::cpu1.itb.walker 7231 # number of demand (read+write) misses
2915system.l2c.demand_misses::cpu1.inst 8328 # number of demand (read+write) misses
2916system.l2c.demand_misses::cpu1.data 204511 # number of demand (read+write) misses
2917system.l2c.demand_misses::cpu1.l2cache.prefetcher 456002 # number of demand (read+write) misses
2918system.l2c.demand_misses::total 1595159 # number of demand (read+write) misses
2919system.l2c.overall_misses::cpu0.dtb.walker 5517 # number of overall misses
2920system.l2c.overall_misses::cpu0.itb.walker 8182 # number of overall misses
2921system.l2c.overall_misses::cpu0.inst 12718 # number of overall misses
2922system.l2c.overall_misses::cpu0.data 288655 # number of overall misses
2923system.l2c.overall_misses::cpu0.l2cache.prefetcher 598730 # number of overall misses
2924system.l2c.overall_misses::cpu1.dtb.walker 5285 # number of overall misses
2925system.l2c.overall_misses::cpu1.itb.walker 7231 # number of overall misses
2926system.l2c.overall_misses::cpu1.inst 8328 # number of overall misses
2927system.l2c.overall_misses::cpu1.data 204511 # number of overall misses
2928system.l2c.overall_misses::cpu1.l2cache.prefetcher 456002 # number of overall misses
2929system.l2c.overall_misses::total 1595159 # number of overall misses
2930system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 458859494 # number of ReadReq miss cycles
2931system.l2c.ReadReq_miss_latency::cpu0.itb.walker 660185236 # number of ReadReq miss cycles
2932system.l2c.ReadReq_miss_latency::cpu0.inst 1228334988 # number of ReadReq miss cycles
2933system.l2c.ReadReq_miss_latency::cpu0.data 18297393453 # number of ReadReq miss cycles
2934system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 72887603477 # number of ReadReq miss cycles
2935system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 440607992 # number of ReadReq miss cycles
2936system.l2c.ReadReq_miss_latency::cpu1.itb.walker 598540979 # number of ReadReq miss cycles
2937system.l2c.ReadReq_miss_latency::cpu1.inst 788794491 # number of ReadReq miss cycles
2938system.l2c.ReadReq_miss_latency::cpu1.data 12800911061 # number of ReadReq miss cycles
2939system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 55801999034 # number of ReadReq miss cycles
2940system.l2c.ReadReq_miss_latency::total 163963230205 # number of ReadReq miss cycles
2941system.l2c.UpgradeReq_miss_latency::cpu0.data 163981726 # number of UpgradeReq miss cycles
2942system.l2c.UpgradeReq_miss_latency::cpu1.data 172729371 # number of UpgradeReq miss cycles
2943system.l2c.UpgradeReq_miss_latency::total 336711097 # number of UpgradeReq miss cycles
2944system.l2c.SCUpgradeReq_miss_latency::cpu0.data 59985022 # number of SCUpgradeReq miss cycles
2945system.l2c.SCUpgradeReq_miss_latency::cpu1.data 52908784 # number of SCUpgradeReq miss cycles
2946system.l2c.SCUpgradeReq_miss_latency::total 112893806 # number of SCUpgradeReq miss cycles
2947system.l2c.ReadExReq_miss_latency::cpu0.data 7434747873 # number of ReadExReq miss cycles
2948system.l2c.ReadExReq_miss_latency::cpu1.data 5448950117 # number of ReadExReq miss cycles
2949system.l2c.ReadExReq_miss_latency::total 12883697990 # number of ReadExReq miss cycles
2950system.l2c.demand_miss_latency::cpu0.dtb.walker 458859494 # number of demand (read+write) miss cycles
2951system.l2c.demand_miss_latency::cpu0.itb.walker 660185236 # number of demand (read+write) miss cycles
2952system.l2c.demand_miss_latency::cpu0.inst 1228334988 # number of demand (read+write) miss cycles
2953system.l2c.demand_miss_latency::cpu0.data 25732141326 # number of demand (read+write) miss cycles
2954system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 72887603477 # number of demand (read+write) miss cycles
2955system.l2c.demand_miss_latency::cpu1.dtb.walker 440607992 # number of demand (read+write) miss cycles
2956system.l2c.demand_miss_latency::cpu1.itb.walker 598540979 # number of demand (read+write) miss cycles
2957system.l2c.demand_miss_latency::cpu1.inst 788794491 # number of demand (read+write) miss cycles
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2959system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 55801999034 # number of demand (read+write) miss cycles
2960system.l2c.demand_miss_latency::total 176846928195 # number of demand (read+write) miss cycles
2961system.l2c.overall_miss_latency::cpu0.dtb.walker 458859494 # number of overall miss cycles
2962system.l2c.overall_miss_latency::cpu0.itb.walker 660185236 # number of overall miss cycles
2963system.l2c.overall_miss_latency::cpu0.inst 1228334988 # number of overall miss cycles
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2965system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 72887603477 # number of overall miss cycles
2966system.l2c.overall_miss_latency::cpu1.dtb.walker 440607992 # number of overall miss cycles
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2968system.l2c.overall_miss_latency::cpu1.inst 788794491 # number of overall miss cycles
2969system.l2c.overall_miss_latency::cpu1.data 18249861178 # number of overall miss cycles
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2971system.l2c.overall_miss_latency::total 176846928195 # number of overall miss cycles
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2973system.l2c.ReadReq_accesses::cpu0.itb.walker 12483 # number of ReadReq accesses(hits+misses)
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2975system.l2c.ReadReq_accesses::cpu0.data 893155 # number of ReadReq accesses(hits+misses)
2976system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 2424665 # number of ReadReq accesses(hits+misses)
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2978system.l2c.ReadReq_accesses::cpu1.itb.walker 12388 # number of ReadReq accesses(hits+misses)
2979system.l2c.ReadReq_accesses::cpu1.inst 171273 # number of ReadReq accesses(hits+misses)
2980system.l2c.ReadReq_accesses::cpu1.data 827749 # number of ReadReq accesses(hits+misses)
2981system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 2272538 # number of ReadReq accesses(hits+misses)
2982system.l2c.ReadReq_accesses::total 6824241 # number of ReadReq accesses(hits+misses)
2983system.l2c.Writeback_accesses::writebacks 2284318 # number of Writeback accesses(hits+misses)
2984system.l2c.Writeback_accesses::total 2284318 # number of Writeback accesses(hits+misses)
2985system.l2c.UpgradeReq_accesses::cpu0.data 67318 # number of UpgradeReq accesses(hits+misses)
2986system.l2c.UpgradeReq_accesses::cpu1.data 70602 # number of UpgradeReq accesses(hits+misses)
2987system.l2c.UpgradeReq_accesses::total 137920 # number of UpgradeReq accesses(hits+misses)
2988system.l2c.SCUpgradeReq_accesses::cpu0.data 20866 # number of SCUpgradeReq accesses(hits+misses)
2989system.l2c.SCUpgradeReq_accesses::cpu1.data 17044 # number of SCUpgradeReq accesses(hits+misses)
2990system.l2c.SCUpgradeReq_accesses::total 37910 # number of SCUpgradeReq accesses(hits+misses)
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2992system.l2c.ReadExReq_accesses::cpu1.data 121712 # number of ReadExReq accesses(hits+misses)
2993system.l2c.ReadExReq_accesses::total 266666 # number of ReadExReq accesses(hits+misses)
2994system.l2c.demand_accesses::cpu0.dtb.walker 13070 # number of demand (read+write) accesses
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3000system.l2c.demand_accesses::cpu1.itb.walker 12388 # number of demand (read+write) accesses
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3005system.l2c.overall_accesses::cpu0.dtb.walker 13070 # number of overall (read+write) accesses
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3007system.l2c.overall_accesses::cpu0.inst 183412 # number of overall (read+write) accesses
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3010system.l2c.overall_accesses::cpu1.dtb.walker 13508 # number of overall (read+write) accesses
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3012system.l2c.overall_accesses::cpu1.inst 171273 # number of overall (read+write) accesses
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3015system.l2c.overall_accesses::total 7090907 # number of overall (read+write) accesses
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3017system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.655451 # miss rate for ReadReq accesses
3018system.l2c.ReadReq_miss_rate::cpu0.inst 0.069341 # miss rate for ReadReq accesses
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3020system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.246933 # miss rate for ReadReq accesses
3021system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.391250 # miss rate for ReadReq accesses
3022system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.583710 # miss rate for ReadReq accesses
3023system.l2c.ReadReq_miss_rate::cpu1.inst 0.048624 # miss rate for ReadReq accesses
3024system.l2c.ReadReq_miss_rate::cpu1.data 0.164964 # miss rate for ReadReq accesses
3025system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.200658 # miss rate for ReadReq accesses
3026system.l2c.ReadReq_miss_rate::total 0.210368 # miss rate for ReadReq accesses
3027system.l2c.UpgradeReq_miss_rate::cpu0.data 0.575641 # miss rate for UpgradeReq accesses
3028system.l2c.UpgradeReq_miss_rate::cpu1.data 0.554899 # miss rate for UpgradeReq accesses
3029system.l2c.UpgradeReq_miss_rate::total 0.565023 # miss rate for UpgradeReq accesses
3030system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.571360 # miss rate for SCUpgradeReq accesses
3031system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.563483 # miss rate for SCUpgradeReq accesses
3032system.l2c.SCUpgradeReq_miss_rate::total 0.567819 # miss rate for SCUpgradeReq accesses
3033system.l2c.ReadExReq_miss_rate::cpu0.data 0.631869 # miss rate for ReadExReq accesses
3034system.l2c.ReadExReq_miss_rate::cpu1.data 0.558384 # miss rate for ReadExReq accesses
3035system.l2c.ReadExReq_miss_rate::total 0.598329 # miss rate for ReadExReq accesses
3036system.l2c.demand_miss_rate::cpu0.dtb.walker 0.422112 # miss rate for demand accesses
3037system.l2c.demand_miss_rate::cpu0.itb.walker 0.655451 # miss rate for demand accesses
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3039system.l2c.demand_miss_rate::cpu0.data 0.278058 # miss rate for demand accesses
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3041system.l2c.demand_miss_rate::cpu1.dtb.walker 0.391250 # miss rate for demand accesses
3042system.l2c.demand_miss_rate::cpu1.itb.walker 0.583710 # miss rate for demand accesses
3043system.l2c.demand_miss_rate::cpu1.inst 0.048624 # miss rate for demand accesses
3044system.l2c.demand_miss_rate::cpu1.data 0.215397 # miss rate for demand accesses
3045system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.200658 # miss rate for demand accesses
3046system.l2c.demand_miss_rate::total 0.224958 # miss rate for demand accesses
3047system.l2c.overall_miss_rate::cpu0.dtb.walker 0.422112 # miss rate for overall accesses
3048system.l2c.overall_miss_rate::cpu0.itb.walker 0.655451 # miss rate for overall accesses
3049system.l2c.overall_miss_rate::cpu0.inst 0.069341 # miss rate for overall accesses
3050system.l2c.overall_miss_rate::cpu0.data 0.278058 # miss rate for overall accesses
3051system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.246933 # miss rate for overall accesses
3052system.l2c.overall_miss_rate::cpu1.dtb.walker 0.391250 # miss rate for overall accesses
3053system.l2c.overall_miss_rate::cpu1.itb.walker 0.583710 # miss rate for overall accesses
3054system.l2c.overall_miss_rate::cpu1.inst 0.048624 # miss rate for overall accesses
3055system.l2c.overall_miss_rate::cpu1.data 0.215397 # miss rate for overall accesses
3056system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.200658 # miss rate for overall accesses
3057system.l2c.overall_miss_rate::total 0.224958 # miss rate for overall accesses
3058system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83171.922059 # average ReadReq miss latency
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3060system.l2c.ReadReq_avg_miss_latency::cpu0.inst 96582.401950 # average ReadReq miss latency
3061system.l2c.ReadReq_avg_miss_latency::cpu0.data 92850.476513 # average ReadReq miss latency
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3063system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 83369.534910 # average ReadReq miss latency
3064system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 82774.302171 # average ReadReq miss latency
3065system.l2c.ReadReq_avg_miss_latency::cpu1.inst 94715.957133 # average ReadReq miss latency
3066system.l2c.ReadReq_avg_miss_latency::cpu1.data 93745.915832 # average ReadReq miss latency
3067system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 122372.268179 # average ReadReq miss latency
3068system.l2c.ReadReq_avg_miss_latency::total 114211.938663 # average ReadReq miss latency
3069system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 4231.677273 # average UpgradeReq miss latency
3070system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4408.948388 # average UpgradeReq miss latency
3071system.l2c.UpgradeReq_avg_miss_latency::total 4320.797364 # average UpgradeReq miss latency
3072system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5031.456299 # average SCUpgradeReq miss latency
3073system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5509.036235 # average SCUpgradeReq miss latency
3074system.l2c.SCUpgradeReq_avg_miss_latency::total 5244.532472 # average SCUpgradeReq miss latency
3075system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81172.459090 # average ReadExReq miss latency
3076system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80176.423840 # average ReadExReq miss latency
3077system.l2c.ReadExReq_avg_miss_latency::total 80748.198040 # average ReadExReq miss latency
3078system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83171.922059 # average overall miss latency
3079system.l2c.demand_avg_miss_latency::cpu0.itb.walker 80687.513566 # average overall miss latency
3080system.l2c.demand_avg_miss_latency::cpu0.inst 96582.401950 # average overall miss latency
3081system.l2c.demand_avg_miss_latency::cpu0.data 89144.970037 # average overall miss latency
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3083system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 83369.534910 # average overall miss latency
3084system.l2c.demand_avg_miss_latency::cpu1.itb.walker 82774.302171 # average overall miss latency
3085system.l2c.demand_avg_miss_latency::cpu1.inst 94715.957133 # average overall miss latency
3086system.l2c.demand_avg_miss_latency::cpu1.data 89236.574942 # average overall miss latency
3087system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 122372.268179 # average overall miss latency
3088system.l2c.demand_avg_miss_latency::total 110864.765327 # average overall miss latency
3089system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83171.922059 # average overall miss latency
3090system.l2c.overall_avg_miss_latency::cpu0.itb.walker 80687.513566 # average overall miss latency
3091system.l2c.overall_avg_miss_latency::cpu0.inst 96582.401950 # average overall miss latency
3092system.l2c.overall_avg_miss_latency::cpu0.data 89144.970037 # average overall miss latency
3093system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 121737.015812 # average overall miss latency
3094system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 83369.534910 # average overall miss latency
3095system.l2c.overall_avg_miss_latency::cpu1.itb.walker 82774.302171 # average overall miss latency
3096system.l2c.overall_avg_miss_latency::cpu1.inst 94715.957133 # average overall miss latency
3097system.l2c.overall_avg_miss_latency::cpu1.data 89236.574942 # average overall miss latency
3098system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 122372.268179 # average overall miss latency
3099system.l2c.overall_avg_miss_latency::total 110864.765327 # average overall miss latency
3100system.l2c.blocked_cycles::no_mshrs 23951 # number of cycles access was blocked
3101system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
3102system.l2c.blocked::no_mshrs 978 # number of cycles access was blocked
3103system.l2c.blocked::no_targets 0 # number of cycles access was blocked
3104system.l2c.avg_blocked_cycles::no_mshrs 24.489775 # average number of cycles each access was blocked
3105system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3106system.l2c.fast_writes 0 # number of fast writes performed
3107system.l2c.cache_copies 0 # number of cache copies performed
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3109system.l2c.writebacks::total 882638 # number of writebacks
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3111system.l2c.ReadReq_mshr_hits::cpu0.data 44 # number of ReadReq MSHR hits
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3114system.l2c.ReadReq_mshr_hits::cpu1.data 35 # number of ReadReq MSHR hits
3115system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 342 # number of ReadReq MSHR hits
3116system.l2c.ReadReq_mshr_hits::total 787 # number of ReadReq MSHR hits
3117system.l2c.demand_mshr_hits::cpu0.inst 23 # number of demand (read+write) MSHR hits
3118system.l2c.demand_mshr_hits::cpu0.data 44 # number of demand (read+write) MSHR hits
3119system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 314 # number of demand (read+write) MSHR hits
3120system.l2c.demand_mshr_hits::cpu1.inst 29 # number of demand (read+write) MSHR hits
3121system.l2c.demand_mshr_hits::cpu1.data 35 # number of demand (read+write) MSHR hits
3122system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 342 # number of demand (read+write) MSHR hits
3123system.l2c.demand_mshr_hits::total 787 # number of demand (read+write) MSHR hits
3124system.l2c.overall_mshr_hits::cpu0.inst 23 # number of overall MSHR hits
3125system.l2c.overall_mshr_hits::cpu0.data 44 # number of overall MSHR hits
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3141system.l2c.ReadReq_mshr_misses::total 1434818 # number of ReadReq MSHR misses
3142system.l2c.UpgradeReq_mshr_misses::cpu0.data 38751 # number of UpgradeReq MSHR misses
3143system.l2c.UpgradeReq_mshr_misses::cpu1.data 39177 # number of UpgradeReq MSHR misses
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3182system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 50212096787 # number of ReadReq MSHR miss cycles
3183system.l2c.ReadReq_mshr_miss_latency::total 146316086137 # number of ReadReq MSHR miss cycles
3184system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 30535463126 # number of WriteInvalidateReq MSHR miss cycles
3185system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 15845549899 # number of WriteInvalidateReq MSHR miss cycles
3186system.l2c.WriteInvalidateReq_mshr_miss_latency::total 46381013025 # number of WriteInvalidateReq MSHR miss cycles
3187system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 399321668 # number of UpgradeReq MSHR miss cycles
3188system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 406522254 # number of UpgradeReq MSHR miss cycles
3189system.l2c.UpgradeReq_mshr_miss_latency::total 805843922 # number of UpgradeReq MSHR miss cycles
3190system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 123605642 # number of SCUpgradeReq MSHR miss cycles
3191system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 99686358 # number of SCUpgradeReq MSHR miss cycles
3192system.l2c.SCUpgradeReq_mshr_miss_latency::total 223292000 # number of SCUpgradeReq MSHR miss cycles
3193system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6293776443 # number of ReadExReq MSHR miss cycles
3194system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4602629757 # number of ReadExReq MSHR miss cycles
3195system.l2c.ReadExReq_mshr_miss_latency::total 10896406200 # number of ReadExReq MSHR miss cycles
3196system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 390191994 # number of demand (read+write) MSHR miss cycles
3197system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 558414736 # number of demand (read+write) MSHR miss cycles
3198system.l2c.demand_mshr_miss_latency::cpu0.inst 1068365744 # number of demand (read+write) MSHR miss cycles
3199system.l2c.demand_mshr_miss_latency::cpu0.data 22144244298 # number of demand (read+write) MSHR miss cycles
3200system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 65563016998 # number of demand (read+write) MSHR miss cycles
3201system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 374801992 # number of demand (read+write) MSHR miss cycles
3202system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 508508979 # number of demand (read+write) MSHR miss cycles
3203system.l2c.demand_mshr_miss_latency::cpu1.inst 683514241 # number of demand (read+write) MSHR miss cycles
3204system.l2c.demand_mshr_miss_latency::cpu1.data 15709336568 # number of demand (read+write) MSHR miss cycles
3205system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 50212096787 # number of demand (read+write) MSHR miss cycles
3206system.l2c.demand_mshr_miss_latency::total 157212492337 # number of demand (read+write) MSHR miss cycles
3207system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 390191994 # number of overall MSHR miss cycles
3208system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 558414736 # number of overall MSHR miss cycles
3209system.l2c.overall_mshr_miss_latency::cpu0.inst 1068365744 # number of overall MSHR miss cycles
3210system.l2c.overall_mshr_miss_latency::cpu0.data 22144244298 # number of overall MSHR miss cycles
3211system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 65563016998 # number of overall MSHR miss cycles
3212system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 374801992 # number of overall MSHR miss cycles
3213system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 508508979 # number of overall MSHR miss cycles
3214system.l2c.overall_mshr_miss_latency::cpu1.inst 683514241 # number of overall MSHR miss cycles
3215system.l2c.overall_mshr_miss_latency::cpu1.data 15709336568 # number of overall MSHR miss cycles
3216system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 50212096787 # number of overall MSHR miss cycles
3217system.l2c.overall_mshr_miss_latency::total 157212492337 # number of overall MSHR miss cycles
3218system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1103207000 # number of ReadReq MSHR uncacheable cycles
3219system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4952355997 # number of ReadReq MSHR uncacheable cycles
3220system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4307750 # number of ReadReq MSHR uncacheable cycles
3221system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 415818753 # number of ReadReq MSHR uncacheable cycles
3222system.l2c.ReadReq_mshr_uncacheable_latency::total 6475689500 # number of ReadReq MSHR uncacheable cycles
3223system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4782466503 # number of WriteReq MSHR uncacheable cycles
3224system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 497465997 # number of WriteReq MSHR uncacheable cycles
3225system.l2c.WriteReq_mshr_uncacheable_latency::total 5279932500 # number of WriteReq MSHR uncacheable cycles
3226system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1103207000 # number of overall MSHR uncacheable cycles
3227system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9734822500 # number of overall MSHR uncacheable cycles
3228system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4307750 # number of overall MSHR uncacheable cycles
3229system.l2c.overall_mshr_uncacheable_latency::cpu1.data 913284750 # number of overall MSHR uncacheable cycles
3230system.l2c.overall_mshr_uncacheable_latency::total 11755622000 # number of overall MSHR uncacheable cycles
3231system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.422112 # mshr miss rate for ReadReq accesses
3232system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.655451 # mshr miss rate for ReadReq accesses
3233system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.069216 # mshr miss rate for ReadReq accesses
3234system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.220588 # mshr miss rate for ReadReq accesses
3235system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.246804 # mshr miss rate for ReadReq accesses
3236system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.391250 # mshr miss rate for ReadReq accesses
3237system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.583710 # mshr miss rate for ReadReq accesses
3238system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.048455 # mshr miss rate for ReadReq accesses
3239system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.164922 # mshr miss rate for ReadReq accesses
3240system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.200507 # mshr miss rate for ReadReq accesses
3241system.l2c.ReadReq_mshr_miss_rate::total 0.210253 # mshr miss rate for ReadReq accesses
3242system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.575641 # mshr miss rate for UpgradeReq accesses
3243system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.554899 # mshr miss rate for UpgradeReq accesses
3244system.l2c.UpgradeReq_mshr_miss_rate::total 0.565023 # mshr miss rate for UpgradeReq accesses
3245system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.571360 # mshr miss rate for SCUpgradeReq accesses
3246system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.563483 # mshr miss rate for SCUpgradeReq accesses
3247system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.567819 # mshr miss rate for SCUpgradeReq accesses
3248system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.631869 # mshr miss rate for ReadExReq accesses
3249system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.558384 # mshr miss rate for ReadExReq accesses
3250system.l2c.ReadExReq_mshr_miss_rate::total 0.598329 # mshr miss rate for ReadExReq accesses
3251system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.422112 # mshr miss rate for demand accesses
3252system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.655451 # mshr miss rate for demand accesses
3253system.l2c.demand_mshr_miss_rate::cpu0.inst 0.069216 # mshr miss rate for demand accesses
3254system.l2c.demand_mshr_miss_rate::cpu0.data 0.278016 # mshr miss rate for demand accesses
3255system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.246804 # mshr miss rate for demand accesses
3256system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.391250 # mshr miss rate for demand accesses
3257system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.583710 # mshr miss rate for demand accesses
3258system.l2c.demand_mshr_miss_rate::cpu1.inst 0.048455 # mshr miss rate for demand accesses
3259system.l2c.demand_mshr_miss_rate::cpu1.data 0.215360 # mshr miss rate for demand accesses
3260system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.200507 # mshr miss rate for demand accesses
3261system.l2c.demand_mshr_miss_rate::total 0.224847 # mshr miss rate for demand accesses
3262system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.422112 # mshr miss rate for overall accesses
3263system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.655451 # mshr miss rate for overall accesses
3264system.l2c.overall_mshr_miss_rate::cpu0.inst 0.069216 # mshr miss rate for overall accesses
3265system.l2c.overall_mshr_miss_rate::cpu0.data 0.278016 # mshr miss rate for overall accesses
3266system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.246804 # mshr miss rate for overall accesses
3267system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.391250 # mshr miss rate for overall accesses
3268system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.583710 # mshr miss rate for overall accesses
3269system.l2c.overall_mshr_miss_rate::cpu1.inst 0.048455 # mshr miss rate for overall accesses
3270system.l2c.overall_mshr_miss_rate::cpu1.data 0.215360 # mshr miss rate for overall accesses
3271system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.200507 # mshr miss rate for overall accesses
3272system.l2c.overall_mshr_miss_rate::total 0.224847 # mshr miss rate for overall accesses
3273system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 70725.393148 # average ReadReq mshr miss latency
3274system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 68249.173307 # average ReadReq mshr miss latency
3275system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 84156.419378 # average ReadReq mshr miss latency
3276system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80451.468412 # average ReadReq mshr miss latency
3277system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109560.935867 # average ReadReq mshr miss latency
3278system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70918.068496 # average ReadReq mshr miss latency
3279system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70323.465496 # average ReadReq mshr miss latency
3280system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 82361.036390 # average ReadReq mshr miss latency
3281system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 81359.470904 # average ReadReq mshr miss latency
3282system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110196.411331 # average ReadReq mshr miss latency
3283system.l2c.ReadReq_avg_mshr_miss_latency::total 101975.362824 # average ReadReq mshr miss latency
3284system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency
3285system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency
3286system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
3287system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10304.809373 # average UpgradeReq mshr miss latency
3288system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10376.553947 # average UpgradeReq mshr miss latency
3289system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10340.877759 # average UpgradeReq mshr miss latency
3290system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10367.861265 # average SCUpgradeReq mshr miss latency
3291system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10379.670762 # average SCUpgradeReq mshr miss latency
3292system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10373.130168 # average SCUpgradeReq mshr miss latency
3293system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68715.351155 # average ReadExReq mshr miss latency
3294system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67723.577249 # average ReadExReq mshr miss latency
3295system.l2c.ReadExReq_avg_mshr_miss_latency::total 68292.905223 # average ReadExReq mshr miss latency
3296system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70725.393148 # average overall mshr miss latency
3297system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 68249.173307 # average overall mshr miss latency
3298system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 84156.419378 # average overall mshr miss latency
3299system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76726.958771 # average overall mshr miss latency
3300system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109560.935867 # average overall mshr miss latency
3301system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70918.068496 # average overall mshr miss latency
3302system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70323.465496 # average overall mshr miss latency
3303system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 82361.036390 # average overall mshr miss latency
3304system.l2c.demand_avg_mshr_miss_latency::cpu1.data 76827.288132 # average overall mshr miss latency
3305system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110196.411331 # average overall mshr miss latency
3306system.l2c.demand_avg_mshr_miss_latency::total 98604.649565 # average overall mshr miss latency
3307system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70725.393148 # average overall mshr miss latency
3308system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 68249.173307 # average overall mshr miss latency
3309system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 84156.419378 # average overall mshr miss latency
3310system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76726.958771 # average overall mshr miss latency
3311system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109560.935867 # average overall mshr miss latency
3312system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70918.068496 # average overall mshr miss latency
3313system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70323.465496 # average overall mshr miss latency
3314system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 82361.036390 # average overall mshr miss latency
3315system.l2c.overall_avg_mshr_miss_latency::cpu1.data 76827.288132 # average overall mshr miss latency
3316system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110196.411331 # average overall mshr miss latency
3317system.l2c.overall_avg_mshr_miss_latency::total 98604.649565 # average overall mshr miss latency
3318system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
3319system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
3320system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
3321system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
3322system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
3323system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
3324system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
3325system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
3326system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
3327system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
3328system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
3329system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
3330system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
3331system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
3332system.membus.trans_dist::ReadReq 1503713 # Transaction distribution
3333system.membus.trans_dist::ReadResp 1503713 # Transaction distribution
3334system.membus.trans_dist::WriteReq 38586 # Transaction distribution
3335system.membus.trans_dist::WriteResp 38586 # Transaction distribution
3336system.membus.trans_dist::Writeback 882638 # Transaction distribution
3337system.membus.trans_dist::WriteInvalidateReq 1682947 # Transaction distribution
3338system.membus.trans_dist::WriteInvalidateResp 1682947 # Transaction distribution
3339system.membus.trans_dist::UpgradeReq 373970 # Transaction distribution
3340system.membus.trans_dist::SCUpgradeReq 331267 # Transaction distribution
3341system.membus.trans_dist::UpgradeResp 103150 # Transaction distribution
3342system.membus.trans_dist::ReadExReq 170539 # Transaction distribution
3343system.membus.trans_dist::ReadExResp 155861 # Transaction distribution
3344system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123084 # Packet count per connected master and slave (bytes)
3345system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes)
3346system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26002 # Packet count per connected master and slave (bytes)
3347system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 8087433 # Packet count per connected master and slave (bytes)
3348system.membus.pkt_count_system.l2c.mem_side::total 8236597 # Packet count per connected master and slave (bytes)
3349system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229762 # Packet count per connected master and slave (bytes)
3350system.membus.pkt_count_system.iocache.mem_side::total 229762 # Packet count per connected master and slave (bytes)
3351system.membus.pkt_count::total 8466359 # Packet count per connected master and slave (bytes)
3352system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156191 # Cumulative packet size per connected master and slave (bytes)
3353system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes)
3354system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52004 # Cumulative packet size per connected master and slave (bytes)
3355system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 259532552 # Cumulative packet size per connected master and slave (bytes)
3356system.membus.pkt_size_system.l2c.mem_side::total 259741319 # Cumulative packet size per connected master and slave (bytes)
3357system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7302720 # Cumulative packet size per connected master and slave (bytes)
3358system.membus.pkt_size_system.iocache.mem_side::total 7302720 # Cumulative packet size per connected master and slave (bytes)
3359system.membus.pkt_size::total 267044039 # Cumulative packet size per connected master and slave (bytes)
3360system.membus.snoops 618323 # Total snoops (count)
3361system.membus.snoop_fanout::samples 4885385 # Request fanout histogram
3362system.membus.snoop_fanout::mean 1 # Request fanout histogram
3363system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3364system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3365system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3366system.membus.snoop_fanout::1 4885385 100.00% 100.00% # Request fanout histogram
3367system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3368system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3369system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3370system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3371system.membus.snoop_fanout::total 4885385 # Request fanout histogram
3372system.membus.reqLayer0.occupancy 98770920 # Layer occupancy (ticks)
3373system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3374system.membus.reqLayer1.occupancy 45500 # Layer occupancy (ticks)
3375system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3376system.membus.reqLayer2.occupancy 21644945 # Layer occupancy (ticks)
3377system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3378system.membus.reqLayer5.occupancy 25191464236 # Layer occupancy (ticks)
3379system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
3380system.membus.respLayer2.occupancy 16556458898 # Layer occupancy (ticks)
3381system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3382system.membus.respLayer3.occupancy 187451430 # Layer occupancy (ticks)
3383system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3384system.realview.ethernet.txBytes 966 # Bytes Transmitted
3385system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3386system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3387system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3388system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3389system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3390system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA

--- 27 unchanged lines hidden (view full) ---

3418system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
3419system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3420system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3421system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
3422system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3423system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3424system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3425system.realview.ethernet.droppedPackets 0 # number of packets dropped
3426system.toL2Bus.trans_dist::ReadReq 7757807 # Transaction distribution
3427system.toL2Bus.trans_dist::ReadResp 7750243 # Transaction distribution
3428system.toL2Bus.trans_dist::WriteReq 38586 # Transaction distribution
3429system.toL2Bus.trans_dist::WriteResp 38586 # Transaction distribution
3430system.toL2Bus.trans_dist::Writeback 2284318 # Transaction distribution
3431system.toL2Bus.trans_dist::WriteInvalidateReq 1682954 # Transaction distribution
3432system.toL2Bus.trans_dist::WriteInvalidateResp 1576219 # Transaction distribution
3433system.toL2Bus.trans_dist::UpgradeReq 430271 # Transaction distribution
3434system.toL2Bus.trans_dist::SCUpgradeReq 347651 # Transaction distribution
3435system.toL2Bus.trans_dist::UpgradeResp 777922 # Transaction distribution
3436system.toL2Bus.trans_dist::SCUpgradeFailReq 191 # Transaction distribution
3437system.toL2Bus.trans_dist::UpgradeFailResp 191 # Transaction distribution
3438system.toL2Bus.trans_dist::ReadExReq 316482 # Transaction distribution
3439system.toL2Bus.trans_dist::ReadExResp 316482 # Transaction distribution
3440system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 11788342 # Packet count per connected master and slave (bytes)
3441system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9897130 # Packet count per connected master and slave (bytes)
3442system.toL2Bus.pkt_count::total 21685472 # Packet count per connected master and slave (bytes)
3443system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 381410986 # Cumulative packet size per connected master and slave (bytes)
3444system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 320139805 # Cumulative packet size per connected master and slave (bytes)
3445system.toL2Bus.pkt_size::total 701550791 # Cumulative packet size per connected master and slave (bytes)
3446system.toL2Bus.snoops 1633796 # Total snoops (count)
3447system.toL2Bus.snoop_fanout::samples 12761522 # Request fanout histogram
3448system.toL2Bus.snoop_fanout::mean 1.009063 # Request fanout histogram
3449system.toL2Bus.snoop_fanout::stdev 0.094770 # Request fanout histogram
3450system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3451system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3452system.toL2Bus.snoop_fanout::1 12645858 99.09% 99.09% # Request fanout histogram
3453system.toL2Bus.snoop_fanout::2 115664 0.91% 100.00% # Request fanout histogram
3454system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3455system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
3456system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3457system.toL2Bus.snoop_fanout::total 12761522 # Request fanout histogram
3458system.toL2Bus.reqLayer0.occupancy 21862906503 # Layer occupancy (ticks)
3459system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3460system.toL2Bus.snoopLayer0.occupancy 6130500 # Layer occupancy (ticks)
3461system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3462system.toL2Bus.respLayer0.occupancy 19509958221 # Layer occupancy (ticks)
3463system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3464system.toL2Bus.respLayer1.occupancy 17925237290 # Layer occupancy (ticks)
3465system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3466system.cpu0.kern.inst.arm 0 # number of arm instructions executed
3467system.cpu0.kern.inst.quiesce 14096 # number of quiesce instructions executed
3468system.cpu1.kern.inst.arm 0 # number of arm instructions executed
3469system.cpu1.kern.inst.quiesce 4921 # number of quiesce instructions executed
3470
3471---------- End Simulation Statistics ----------