1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.384940 # Number of seconds simulated
4sim_ticks 47384940455000 # Number of ticks simulated
5final_tick 47384940455000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 206357 # Simulator instruction rate (inst/s)
8host_op_rate 242664 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 10614318936 # Simulator tick rate (ticks/s)
10host_mem_usage 793572 # Number of bytes of host memory used
11host_seconds 4464.25 # Real time elapsed on the host
12sim_insts 921230293 # Number of instructions simulated
13sim_ops 1083311023 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu0.dtb.walker 222656 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.itb.walker 215552 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.inst 4481312 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.data 16941064 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu0.l2cache.prefetcher 21659840 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.dtb.walker 116096 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.itb.walker 80000 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.inst 2978912 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.data 10395024 # Number of bytes read from this memory
26system.physmem.bytes_read::cpu1.l2cache.prefetcher 12881984 # Number of bytes read from this memory
27system.physmem.bytes_read::realview.ide 421760 # Number of bytes read from this memory
28system.physmem.bytes_read::total 70394200 # Number of bytes read from this memory
29system.physmem.bytes_inst_read::cpu0.inst 4481312 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::cpu1.inst 2978912 # Number of instructions bytes read from this memory
31system.physmem.bytes_inst_read::total 7460224 # Number of instructions bytes read from this memory
32system.physmem.bytes_written::writebacks 86479488 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
34system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
35system.physmem.bytes_written::total 86500072 # Number of bytes written to this memory
36system.physmem.num_reads::cpu0.dtb.walker 3479 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.itb.walker 3368 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.inst 85973 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.data 264717 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu0.l2cache.prefetcher 338435 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.dtb.walker 1814 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.itb.walker 1250 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.inst 46589 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.data 162435 # Number of read requests responded to by this memory
45system.physmem.num_reads::cpu1.l2cache.prefetcher 201281 # Number of read requests responded to by this memory
46system.physmem.num_reads::realview.ide 6590 # Number of read requests responded to by this memory
47system.physmem.num_reads::total 1115931 # Number of read requests responded to by this memory
48system.physmem.num_writes::writebacks 1351242 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
50system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
51system.physmem.num_writes::total 1353816 # Number of write requests responded to by this memory
52system.physmem.bw_read::cpu0.dtb.walker 4699 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.itb.walker 4549 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.inst 94572 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.data 357520 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu0.l2cache.prefetcher 457104 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.dtb.walker 2450 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.itb.walker 1688 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.inst 62866 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.data 219374 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::cpu1.l2cache.prefetcher 271858 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::realview.ide 8901 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_read::total 1485582 # Total read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu0.inst 94572 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::cpu1.inst 62866 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_inst_read::total 157439 # Instruction read bandwidth from this memory (bytes/s)
67system.physmem.bw_write::writebacks 1825042 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_write::total 1825476 # Write bandwidth from this memory (bytes/s)
71system.physmem.bw_total::writebacks 1825042 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.dtb.walker 4699 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.itb.walker 4549 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.inst 94572 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.data 357954 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu0.l2cache.prefetcher 457104 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.dtb.walker 2450 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.itb.walker 1688 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.inst 62866 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.data 219374 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::cpu1.l2cache.prefetcher 271858 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::realview.ide 8901 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.bw_total::total 3311058 # Total bandwidth to/from this memory (bytes/s)
84system.physmem.readReqs 1115931 # Number of read requests accepted
85system.physmem.writeReqs 1353816 # Number of write requests accepted
86system.physmem.readBursts 1115931 # Number of DRAM read bursts, including those serviced by the write queue
87system.physmem.writeBursts 1353816 # Number of DRAM write bursts, including those merged in the write queue
88system.physmem.bytesReadDRAM 71392384 # Total number of bytes read from DRAM
89system.physmem.bytesReadWrQ 27200 # Total number of bytes read from write queue
90system.physmem.bytesWritten 86499392 # Total number of bytes written to DRAM
91system.physmem.bytesReadSys 70394200 # Total read bytes from the system interface side
92system.physmem.bytesWrittenSys 86500072 # Total written bytes from the system interface side
93system.physmem.servicedByWrQ 425 # Number of DRAM read bursts serviced by the write queue
94system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
96system.physmem.perBankRdBursts::0 66640 # Per bank write bursts
97system.physmem.perBankRdBursts::1 69755 # Per bank write bursts
98system.physmem.perBankRdBursts::2 65507 # Per bank write bursts
99system.physmem.perBankRdBursts::3 67407 # Per bank write bursts
100system.physmem.perBankRdBursts::4 65920 # Per bank write bursts
101system.physmem.perBankRdBursts::5 70505 # Per bank write bursts
102system.physmem.perBankRdBursts::6 65125 # Per bank write bursts
103system.physmem.perBankRdBursts::7 71371 # Per bank write bursts
104system.physmem.perBankRdBursts::8 68061 # Per bank write bursts
105system.physmem.perBankRdBursts::9 95897 # Per bank write bursts
106system.physmem.perBankRdBursts::10 65782 # Per bank write bursts
107system.physmem.perBankRdBursts::11 68970 # Per bank write bursts
108system.physmem.perBankRdBursts::12 60174 # Per bank write bursts
109system.physmem.perBankRdBursts::13 71971 # Per bank write bursts
110system.physmem.perBankRdBursts::14 71235 # Per bank write bursts
111system.physmem.perBankRdBursts::15 71186 # Per bank write bursts
112system.physmem.perBankWrBursts::0 81261 # Per bank write bursts
113system.physmem.perBankWrBursts::1 86034 # Per bank write bursts
114system.physmem.perBankWrBursts::2 81926 # Per bank write bursts
115system.physmem.perBankWrBursts::3 83311 # Per bank write bursts
116system.physmem.perBankWrBursts::4 82546 # Per bank write bursts
117system.physmem.perBankWrBursts::5 86081 # Per bank write bursts
118system.physmem.perBankWrBursts::6 81799 # Per bank write bursts
119system.physmem.perBankWrBursts::7 86537 # Per bank write bursts
120system.physmem.perBankWrBursts::8 86254 # Per bank write bursts
121system.physmem.perBankWrBursts::9 89944 # Per bank write bursts
122system.physmem.perBankWrBursts::10 82817 # Per bank write bursts
123system.physmem.perBankWrBursts::11 84554 # Per bank write bursts
124system.physmem.perBankWrBursts::12 78968 # Per bank write bursts
125system.physmem.perBankWrBursts::13 86566 # Per bank write bursts
126system.physmem.perBankWrBursts::14 86628 # Per bank write bursts
127system.physmem.perBankWrBursts::15 86327 # Per bank write bursts
128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
129system.physmem.numWrRetry 51513 # Number of times write queue was full causing retry
130system.physmem.totGap 47384938876500 # Total gap between requests
131system.physmem.readPktSize::0 0 # Read request sizes (log2)
132system.physmem.readPktSize::1 0 # Read request sizes (log2)
133system.physmem.readPktSize::2 0 # Read request sizes (log2)
134system.physmem.readPktSize::3 25 # Read request sizes (log2)
135system.physmem.readPktSize::4 21333 # Read request sizes (log2)
136system.physmem.readPktSize::5 0 # Read request sizes (log2)
137system.physmem.readPktSize::6 1094573 # Read request sizes (log2)
138system.physmem.writePktSize::0 0 # Write request sizes (log2)
139system.physmem.writePktSize::1 0 # Write request sizes (log2)
140system.physmem.writePktSize::2 2 # Write request sizes (log2)
141system.physmem.writePktSize::3 2572 # Write request sizes (log2)
142system.physmem.writePktSize::4 0 # Write request sizes (log2)
143system.physmem.writePktSize::5 0 # Write request sizes (log2)
144system.physmem.writePktSize::6 1351242 # Write request sizes (log2)
145system.physmem.rdQLenPdf::0 480312 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::1 254385 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::2 111988 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::3 68856 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::4 44885 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::5 37588 # What read queue length does an incoming req see
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184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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207system.physmem.wrQLenPdf::30 91218 # What write queue length does an incoming req see
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209system.physmem.wrQLenPdf::32 75935 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::33 8194 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::34 4666 # What write queue length does an incoming req see
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214system.physmem.wrQLenPdf::37 2176 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::38 1885 # What write queue length does an incoming req see
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217system.physmem.wrQLenPdf::40 1719 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::41 1469 # What write queue length does an incoming req see
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228system.physmem.wrQLenPdf::51 1999 # What write queue length does an incoming req see
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230system.physmem.wrQLenPdf::53 2498 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::54 2690 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::55 2884 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::56 3113 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::57 3416 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::58 3559 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::59 3969 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::60 4586 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::61 5969 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::62 24986 # What write queue length does an incoming req see
240system.physmem.wrQLenPdf::63 120772 # What write queue length does an incoming req see
241system.physmem.bytesPerActivate::samples 1035166 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::mean 152.526679 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::gmean 102.371009 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::stdev 198.170623 # Bytes accessed per row activation
245system.physmem.bytesPerActivate::0-127 664281 64.17% 64.17% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::128-255 215041 20.77% 84.95% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::256-383 59106 5.71% 90.65% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::384-511 25397 2.45% 93.11% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::512-639 20542 1.98% 95.09% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::640-767 11502 1.11% 96.20% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::768-895 7604 0.73% 96.94% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::896-1023 6193 0.60% 97.54% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::1024-1151 25500 2.46% 100.00% # Bytes accessed per row activation
254system.physmem.bytesPerActivate::total 1035166 # Bytes accessed per row activation
255system.physmem.rdPerTurnAround::samples 63814 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::mean 17.480459 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::stdev 70.581857 # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::0-511 63808 99.99% 99.99% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
262system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
263system.physmem.rdPerTurnAround::total 63814 # Reads before turning the bus around for writes
264system.physmem.wrPerTurnAround::samples 63814 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::mean 21.179569 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::gmean 17.530322 # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::stdev 597.849869 # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::0-4095 63812 100.00% 100.00% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::40960-45055 1 0.00% 100.00% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::143360-147455 1 0.00% 100.00% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::total 63814 # Writes before turning the bus around for reads
272system.physmem.totQLat 67332860089 # Total ticks spent queuing
273system.physmem.totMemAccLat 88248597589 # Total ticks spent from burst creation until serviced by the DRAM
274system.physmem.totBusLat 5577530000 # Total ticks spent in databus transfers
275system.physmem.avgQLat 60360.82 # Average queueing delay per DRAM burst
276system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
277system.physmem.avgMemAccLat 79110.82 # Average memory access latency per DRAM burst
278system.physmem.avgRdBW 1.51 # Average DRAM read bandwidth in MiByte/s
279system.physmem.avgWrBW 1.83 # Average achieved write bandwidth in MiByte/s
280system.physmem.avgRdBWSys 1.49 # Average system read bandwidth in MiByte/s
281system.physmem.avgWrBWSys 1.83 # Average system write bandwidth in MiByte/s
282system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
283system.physmem.busUtil 0.03 # Data bus utilization in percentage
284system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
285system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
286system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
287system.physmem.avgWrQLen 25.79 # Average write queue length when enqueuing
288system.physmem.readRowHits 837889 # Number of row buffer hits during reads
289system.physmem.writeRowHits 593994 # Number of row buffer hits during writes
290system.physmem.readRowHitRate 75.11 # Row buffer hit rate for reads
291system.physmem.writeRowHitRate 43.95 # Row buffer hit rate for writes
292system.physmem.avgGap 19186151.00 # Average gap between requests
293system.physmem.pageHitRate 58.04 # Row buffer hit rate, read and write combined
294system.physmem_0.actEnergy 3662384460 # Energy for activate commands per rank (pJ)
295system.physmem_0.preEnergy 1946584530 # Energy for precharge commands per rank (pJ)
296system.physmem_0.readEnergy 3871522200 # Energy for read commands per rank (pJ)
297system.physmem_0.writeEnergy 3494763900 # Energy for write commands per rank (pJ)
298system.physmem_0.refreshEnergy 31929318720.000008 # Energy for refresh commands per rank (pJ)
299system.physmem_0.actBackEnergy 40834926540 # Energy for active background per rank (pJ)
300system.physmem_0.preBackEnergy 1598586240 # Energy for precharge background per rank (pJ)
301system.physmem_0.actPowerDownEnergy 62046559410 # Energy for active power-down per rank (pJ)
302system.physmem_0.prePowerDownEnergy 43455299520 # Energy for precharge power-down per rank (pJ)
303system.physmem_0.selfRefreshEnergy 11294770338285 # Energy for self refresh per rank (pJ)
304system.physmem_0.totalEnergy 11487626755995 # Total energy per rank (pJ)
305system.physmem_0.averagePower 242.432018 # Core power per rank (mW)
306system.physmem_0.totalIdleTime 47291190900816 # Total Idle time Per DRAM Rank
307system.physmem_0.memoryStateTime::IDLE 2771331378 # Time in different power states
308system.physmem_0.memoryStateTime::REF 13558872000 # Time in different power states
309system.physmem_0.memoryStateTime::SREF 47041958774500 # Time in different power states
310system.physmem_0.memoryStateTime::PRE_PDN 113164787559 # Time in different power states
311system.physmem_0.memoryStateTime::ACT 77419210306 # Time in different power states
312system.physmem_0.memoryStateTime::ACT_PDN 136067479257 # Time in different power states
313system.physmem_1.actEnergy 3728772180 # Energy for activate commands per rank (pJ)
314system.physmem_1.preEnergy 1981870440 # Energy for precharge commands per rank (pJ)
315system.physmem_1.readEnergy 4093190640 # Energy for read commands per rank (pJ)
316system.physmem_1.writeEnergy 3560342760 # Energy for write commands per rank (pJ)
317system.physmem_1.refreshEnergy 33599910240.000008 # Energy for refresh commands per rank (pJ)
318system.physmem_1.actBackEnergy 42188393820 # Energy for active background per rank (pJ)
319system.physmem_1.preBackEnergy 1621939680 # Energy for precharge background per rank (pJ)
320system.physmem_1.actPowerDownEnergy 66725147910 # Energy for active power-down per rank (pJ)
321system.physmem_1.prePowerDownEnergy 45519792000 # Energy for precharge power-down per rank (pJ)
322system.physmem_1.selfRefreshEnergy 11290481164380 # Energy for self refresh per rank (pJ)
323system.physmem_1.totalEnergy 11493516343440 # Total energy per rank (pJ)
324system.physmem_1.averagePower 242.556311 # Core power per rank (mW)
325system.physmem_1.totalIdleTime 47288162727367 # Total Idle time Per DRAM Rank
326system.physmem_1.memoryStateTime::IDLE 2732090205 # Time in different power states
327system.physmem_1.memoryStateTime::REF 14267508000 # Time in different power states
328system.physmem_1.memoryStateTime::SREF 47023294872500 # Time in different power states
329system.physmem_1.memoryStateTime::PRE_PDN 118540781222 # Time in different power states
330system.physmem_1.memoryStateTime::ACT 79778077178 # Time in different power states
331system.physmem_1.memoryStateTime::ACT_PDN 146327125895 # Time in different power states
332system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
333system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory
334system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
335system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
336system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
337system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory
338system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory
339system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory
340system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory

--- 10 unchanged lines hidden (view full) ---

351system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
352system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s)
353system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s)
354system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
355system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
356system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s)
357system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
358system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
359system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
360system.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
361system.bridge.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
362system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
363system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
364system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
365system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
366system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
367system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
368system.cpu0.branchPred.lookups 139151101 # Number of BP lookups
369system.cpu0.branchPred.condPredicted 91634411 # Number of conditional branches predicted
370system.cpu0.branchPred.condIncorrect 6732234 # Number of conditional branches incorrect
371system.cpu0.branchPred.BTBLookups 97916993 # Number of BTB lookups
372system.cpu0.branchPred.BTBHits 61670085 # Number of BTB hits
373system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
374system.cpu0.branchPred.BTBHitPct 62.982005 # BTB Hit Percentage
375system.cpu0.branchPred.usedRAS 19220371 # Number of times the RAS was used to get a target.
376system.cpu0.branchPred.RASInCorrect 194045 # Number of incorrect RAS predictions.
377system.cpu0.branchPred.indirectLookups 4187621 # Number of indirect predictor lookups.
378system.cpu0.branchPred.indirectHits 2676103 # Number of indirect target hits.
379system.cpu0.branchPred.indirectMisses 1511518 # Number of indirect misses.
380system.cpu0.branchPredindirectMispredicted 384250 # Number of mispredicted indirect branches.
381system.cpu_clk_domain.clock 500 # Clock period in ticks
382system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
383system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
384system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
388system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

404system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
405system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
406system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
407system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
408system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
409system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
410system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
411system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
412system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
413system.cpu0.dtb.walker.walks 608743 # Table walker walks requested
414system.cpu0.dtb.walker.walksLong 608743 # Table walker walks initiated with long descriptors
415system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13705 # Level at which table walker walks with long descriptors terminate
416system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 96942 # Level at which table walker walks with long descriptors terminate
417system.cpu0.dtb.walker.walksSquashedBefore 292908 # Table walks squashed before starting
418system.cpu0.dtb.walker.walkWaitTime::samples 315835 # Table walker wait (enqueue to first request) latency
419system.cpu0.dtb.walker.walkWaitTime::mean 2627.591939 # Table walker wait (enqueue to first request) latency
420system.cpu0.dtb.walker.walkWaitTime::stdev 15089.582893 # Table walker wait (enqueue to first request) latency
421system.cpu0.dtb.walker.walkWaitTime::0-65535 312900 99.07% 99.07% # Table walker wait (enqueue to first request) latency
422system.cpu0.dtb.walker.walkWaitTime::65536-131071 2131 0.67% 99.75% # Table walker wait (enqueue to first request) latency
423system.cpu0.dtb.walker.walkWaitTime::131072-196607 548 0.17% 99.92% # Table walker wait (enqueue to first request) latency
424system.cpu0.dtb.walker.walkWaitTime::196608-262143 139 0.04% 99.96% # Table walker wait (enqueue to first request) latency
425system.cpu0.dtb.walker.walkWaitTime::262144-327679 36 0.01% 99.97% # Table walker wait (enqueue to first request) latency
426system.cpu0.dtb.walker.walkWaitTime::327680-393215 50 0.02% 99.99% # Table walker wait (enqueue to first request) latency
427system.cpu0.dtb.walker.walkWaitTime::393216-458751 5 0.00% 99.99% # Table walker wait (enqueue to first request) latency
428system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
429system.cpu0.dtb.walker.walkWaitTime::589824-655359 23 0.01% 100.00% # Table walker wait (enqueue to first request) latency
430system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
431system.cpu0.dtb.walker.walkWaitTime::total 315835 # Table walker wait (enqueue to first request) latency
432system.cpu0.dtb.walker.walkCompletionTime::samples 324732 # Table walker service (enqueue to completion) latency
433system.cpu0.dtb.walker.walkCompletionTime::mean 22165.202382 # Table walker service (enqueue to completion) latency
434system.cpu0.dtb.walker.walkCompletionTime::gmean 18853.631715 # Table walker service (enqueue to completion) latency
435system.cpu0.dtb.walker.walkCompletionTime::stdev 18861.810606 # Table walker service (enqueue to completion) latency
436system.cpu0.dtb.walker.walkCompletionTime::0-65535 320100 98.57% 98.57% # Table walker service (enqueue to completion) latency
437system.cpu0.dtb.walker.walkCompletionTime::65536-131071 3009 0.93% 99.50% # Table walker service (enqueue to completion) latency
438system.cpu0.dtb.walker.walkCompletionTime::131072-196607 694 0.21% 99.71% # Table walker service (enqueue to completion) latency
439system.cpu0.dtb.walker.walkCompletionTime::196608-262143 681 0.21% 99.92% # Table walker service (enqueue to completion) latency
440system.cpu0.dtb.walker.walkCompletionTime::262144-327679 132 0.04% 99.96% # Table walker service (enqueue to completion) latency
441system.cpu0.dtb.walker.walkCompletionTime::327680-393215 68 0.02% 99.99% # Table walker service (enqueue to completion) latency
442system.cpu0.dtb.walker.walkCompletionTime::393216-458751 19 0.01% 99.99% # Table walker service (enqueue to completion) latency
443system.cpu0.dtb.walker.walkCompletionTime::458752-524287 13 0.00% 100.00% # Table walker service (enqueue to completion) latency
444system.cpu0.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency
445system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
446system.cpu0.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
447system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
448system.cpu0.dtb.walker.walkCompletionTime::total 324732 # Table walker service (enqueue to completion) latency
449system.cpu0.dtb.walker.walksPending::samples 522550016344 # Table walker pending requests distribution
450system.cpu0.dtb.walker.walksPending::mean 0.577122 # Table walker pending requests distribution
451system.cpu0.dtb.walker.walksPending::stdev 0.559179 # Table walker pending requests distribution
452system.cpu0.dtb.walker.walksPending::0-1 521035310844 99.71% 99.71% # Table walker pending requests distribution
453system.cpu0.dtb.walker.walksPending::2-3 819753000 0.16% 99.87% # Table walker pending requests distribution
454system.cpu0.dtb.walker.walksPending::4-5 323762500 0.06% 99.93% # Table walker pending requests distribution
455system.cpu0.dtb.walker.walksPending::6-7 144297000 0.03% 99.96% # Table walker pending requests distribution
456system.cpu0.dtb.walker.walksPending::8-9 115791000 0.02% 99.98% # Table walker pending requests distribution
457system.cpu0.dtb.walker.walksPending::10-11 61783500 0.01% 99.99% # Table walker pending requests distribution
458system.cpu0.dtb.walker.walksPending::12-13 19805000 0.00% 99.99% # Table walker pending requests distribution
459system.cpu0.dtb.walker.walksPending::14-15 28515500 0.01% 100.00% # Table walker pending requests distribution
460system.cpu0.dtb.walker.walksPending::16-17 990500 0.00% 100.00% # Table walker pending requests distribution
461system.cpu0.dtb.walker.walksPending::18-19 7500 0.00% 100.00% # Table walker pending requests distribution
462system.cpu0.dtb.walker.walksPending::total 522550016344 # Table walker pending requests distribution
463system.cpu0.dtb.walker.walkPageSizes::4K 96943 87.61% 87.61% # Table walker page sizes translated
464system.cpu0.dtb.walker.walkPageSizes::2M 13705 12.39% 100.00% # Table walker page sizes translated
465system.cpu0.dtb.walker.walkPageSizes::total 110648 # Table walker page sizes translated
466system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 608743 # Table walker requests started/completed, data/inst
467system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
468system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 608743 # Table walker requests started/completed, data/inst
469system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 110648 # Table walker requests started/completed, data/inst
470system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
471system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 110648 # Table walker requests started/completed, data/inst
472system.cpu0.dtb.walker.walkRequestOrigin::total 719391 # Table walker requests started/completed, data/inst
473system.cpu0.dtb.inst_hits 0 # ITB inst hits
474system.cpu0.dtb.inst_misses 0 # ITB inst misses
475system.cpu0.dtb.read_hits 101564011 # DTB read hits
476system.cpu0.dtb.read_misses 439385 # DTB read misses
477system.cpu0.dtb.write_hits 82403711 # DTB write hits
478system.cpu0.dtb.write_misses 169358 # DTB write misses
479system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
480system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
481system.cpu0.dtb.flush_tlb_mva_asid 44658 # Number of times TLB was flushed by MVA & ASID
482system.cpu0.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
483system.cpu0.dtb.flush_entries 43119 # Number of entries that have been flushed from TLB
484system.cpu0.dtb.align_faults 431 # Number of TLB faults due to alignment restrictions
485system.cpu0.dtb.prefetch_faults 7683 # Number of TLB faults due to prefetch
486system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
487system.cpu0.dtb.perms_faults 39881 # Number of TLB faults due to permissions restrictions
488system.cpu0.dtb.read_accesses 102003396 # DTB read accesses
489system.cpu0.dtb.write_accesses 82573069 # DTB write accesses
490system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
491system.cpu0.dtb.hits 183967722 # DTB hits
492system.cpu0.dtb.misses 608743 # DTB misses
493system.cpu0.dtb.accesses 184576465 # DTB accesses
494system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
495system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
496system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
497system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
498system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
499system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
500system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
501system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
502system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

516system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
517system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
518system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
519system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
520system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
521system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
522system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
523system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
524system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
525system.cpu0.itb.walker.walks 85247 # Table walker walks requested
526system.cpu0.itb.walker.walksLong 85247 # Table walker walks initiated with long descriptors
527system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1031 # Level at which table walker walks with long descriptors terminate
528system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58619 # Level at which table walker walks with long descriptors terminate
529system.cpu0.itb.walker.walksSquashedBefore 10594 # Table walks squashed before starting
530system.cpu0.itb.walker.walkWaitTime::samples 74653 # Table walker wait (enqueue to first request) latency
531system.cpu0.itb.walker.walkWaitTime::mean 1640.215397 # Table walker wait (enqueue to first request) latency
532system.cpu0.itb.walker.walkWaitTime::stdev 15358.310447 # Table walker wait (enqueue to first request) latency
533system.cpu0.itb.walker.walkWaitTime::0-65535 74120 99.29% 99.29% # Table walker wait (enqueue to first request) latency
534system.cpu0.itb.walker.walkWaitTime::65536-131071 439 0.59% 99.87% # Table walker wait (enqueue to first request) latency
535system.cpu0.itb.walker.walkWaitTime::131072-196607 37 0.05% 99.92% # Table walker wait (enqueue to first request) latency
536system.cpu0.itb.walker.walkWaitTime::196608-262143 19 0.03% 99.95% # Table walker wait (enqueue to first request) latency
537system.cpu0.itb.walker.walkWaitTime::262144-327679 10 0.01% 99.96% # Table walker wait (enqueue to first request) latency
538system.cpu0.itb.walker.walkWaitTime::327680-393215 2 0.00% 99.97% # Table walker wait (enqueue to first request) latency
539system.cpu0.itb.walker.walkWaitTime::458752-524287 1 0.00% 99.97% # Table walker wait (enqueue to first request) latency
540system.cpu0.itb.walker.walkWaitTime::524288-589823 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency
541system.cpu0.itb.walker.walkWaitTime::589824-655359 19 0.03% 100.00% # Table walker wait (enqueue to first request) latency
542system.cpu0.itb.walker.walkWaitTime::total 74653 # Table walker wait (enqueue to first request) latency
543system.cpu0.itb.walker.walkCompletionTime::samples 70244 # Table walker service (enqueue to completion) latency
544system.cpu0.itb.walker.walkCompletionTime::mean 27495.914242 # Table walker service (enqueue to completion) latency
545system.cpu0.itb.walker.walkCompletionTime::gmean 23588.322709 # Table walker service (enqueue to completion) latency
546system.cpu0.itb.walker.walkCompletionTime::stdev 27529.617952 # Table walker service (enqueue to completion) latency
547system.cpu0.itb.walker.walkCompletionTime::0-65535 67750 96.45% 96.45% # Table walker service (enqueue to completion) latency
548system.cpu0.itb.walker.walkCompletionTime::65536-131071 1764 2.51% 98.96% # Table walker service (enqueue to completion) latency
549system.cpu0.itb.walker.walkCompletionTime::131072-196607 417 0.59% 99.55% # Table walker service (enqueue to completion) latency
550system.cpu0.itb.walker.walkCompletionTime::196608-262143 170 0.24% 99.80% # Table walker service (enqueue to completion) latency
551system.cpu0.itb.walker.walkCompletionTime::262144-327679 48 0.07% 99.86% # Table walker service (enqueue to completion) latency
552system.cpu0.itb.walker.walkCompletionTime::327680-393215 42 0.06% 99.92% # Table walker service (enqueue to completion) latency
553system.cpu0.itb.walker.walkCompletionTime::393216-458751 15 0.02% 99.95% # Table walker service (enqueue to completion) latency
554system.cpu0.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.95% # Table walker service (enqueue to completion) latency
555system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.96% # Table walker service (enqueue to completion) latency
556system.cpu0.itb.walker.walkCompletionTime::589824-655359 26 0.04% 99.99% # Table walker service (enqueue to completion) latency
557system.cpu0.itb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
558system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
559system.cpu0.itb.walker.walkCompletionTime::total 70244 # Table walker service (enqueue to completion) latency
560system.cpu0.itb.walker.walksPending::samples 419443065740 # Table walker pending requests distribution
561system.cpu0.itb.walker.walksPending::mean 0.871284 # Table walker pending requests distribution
562system.cpu0.itb.walker.walksPending::stdev 0.335229 # Table walker pending requests distribution
563system.cpu0.itb.walker.walksPending::0 54034549916 12.88% 12.88% # Table walker pending requests distribution
564system.cpu0.itb.walker.walksPending::1 365365302324 87.11% 99.99% # Table walker pending requests distribution
565system.cpu0.itb.walker.walksPending::2 40992500 0.01% 100.00% # Table walker pending requests distribution
566system.cpu0.itb.walker.walksPending::3 2004000 0.00% 100.00% # Table walker pending requests distribution
567system.cpu0.itb.walker.walksPending::4 217000 0.00% 100.00% # Table walker pending requests distribution
568system.cpu0.itb.walker.walksPending::total 419443065740 # Table walker pending requests distribution
569system.cpu0.itb.walker.walkPageSizes::4K 58619 98.27% 98.27% # Table walker page sizes translated
570system.cpu0.itb.walker.walkPageSizes::2M 1031 1.73% 100.00% # Table walker page sizes translated
571system.cpu0.itb.walker.walkPageSizes::total 59650 # Table walker page sizes translated
572system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
573system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85247 # Table walker requests started/completed, data/inst
574system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85247 # Table walker requests started/completed, data/inst
575system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
576system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59650 # Table walker requests started/completed, data/inst
577system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59650 # Table walker requests started/completed, data/inst
578system.cpu0.itb.walker.walkRequestOrigin::total 144897 # Table walker requests started/completed, data/inst
579system.cpu0.itb.inst_hits 219469803 # ITB inst hits
580system.cpu0.itb.inst_misses 85247 # ITB inst misses
581system.cpu0.itb.read_hits 0 # DTB read hits
582system.cpu0.itb.read_misses 0 # DTB read misses
583system.cpu0.itb.write_hits 0 # DTB write hits
584system.cpu0.itb.write_misses 0 # DTB write misses
585system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
586system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
587system.cpu0.itb.flush_tlb_mva_asid 44658 # Number of times TLB was flushed by MVA & ASID
588system.cpu0.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
589system.cpu0.itb.flush_entries 31398 # Number of entries that have been flushed from TLB
590system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
591system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
592system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
593system.cpu0.itb.perms_faults 204530 # Number of TLB faults due to permissions restrictions
594system.cpu0.itb.read_accesses 0 # DTB read accesses
595system.cpu0.itb.write_accesses 0 # DTB write accesses
596system.cpu0.itb.inst_accesses 219555050 # ITB inst accesses
597system.cpu0.itb.hits 219469803 # DTB hits
598system.cpu0.itb.misses 85247 # DTB misses
599system.cpu0.itb.accesses 219555050 # DTB accesses
600system.cpu0.numPwrStateTransitions 27212 # Number of power state transitions
601system.cpu0.pwrStateClkGateDist::samples 13606 # Distribution of time spent in the clock gated state
602system.cpu0.pwrStateClkGateDist::mean 3453780783.684036 # Distribution of time spent in the clock gated state
603system.cpu0.pwrStateClkGateDist::stdev 93985708249.621262 # Distribution of time spent in the clock gated state
604system.cpu0.pwrStateClkGateDist::underflows 3589 26.38% 26.38% # Distribution of time spent in the clock gated state
605system.cpu0.pwrStateClkGateDist::1000-5e+10 9986 73.39% 99.77% # Distribution of time spent in the clock gated state
606system.cpu0.pwrStateClkGateDist::5e+10-1e+11 12 0.09% 99.86% # Distribution of time spent in the clock gated state
607system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.88% # Distribution of time spent in the clock gated state
608system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
609system.cpu0.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
610system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
611system.cpu0.pwrStateClkGateDist::overflows 13 0.10% 100.00% # Distribution of time spent in the clock gated state
612system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
613system.cpu0.pwrStateClkGateDist::max_value 6914083139000 # Distribution of time spent in the clock gated state
614system.cpu0.pwrStateClkGateDist::total 13606 # Distribution of time spent in the clock gated state
615system.cpu0.pwrStateResidencyTicks::ON 392799112195 # Cumulative time (in ticks) in various power states
616system.cpu0.pwrStateResidencyTicks::CLK_GATED 46992141342805 # Cumulative time (in ticks) in various power states
617system.cpu0.numCycles 785608211 # number of cpu cycles simulated
618system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
619system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
620system.cpu0.fetch.icacheStallCycles 89154333 # Number of cycles fetch is stalled on an Icache miss
621system.cpu0.fetch.Insts 616347679 # Number of instructions fetch has processed
622system.cpu0.fetch.Branches 139151101 # Number of branches that fetch encountered
623system.cpu0.fetch.predictedBranches 83566559 # Number of branches that fetch has predicted taken
624system.cpu0.fetch.Cycles 651741352 # Number of cycles fetch has run and was not squashing or blocked
625system.cpu0.fetch.SquashCycles 14592652 # Number of cycles fetch has spent squashing
626system.cpu0.fetch.TlbCycles 2033431 # Number of cycles fetch has spent waiting for tlb
627system.cpu0.fetch.MiscStallCycles 298378 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
628system.cpu0.fetch.PendingTrapStallCycles 6056906 # Number of stall cycles due to pending traps
629system.cpu0.fetch.PendingQuiesceStallCycles 755254 # Number of stall cycles due to pending quiesce instructions
630system.cpu0.fetch.IcacheWaitRetryStallCycles 834704 # Number of stall cycles due to full MSHR
631system.cpu0.fetch.CacheLines 219265865 # Number of cache lines fetched
632system.cpu0.fetch.IcacheSquashes 1675112 # Number of outstanding Icache misses that were squashed
633system.cpu0.fetch.ItlbSquashes 28029 # Number of outstanding ITLB misses that were squashed
634system.cpu0.fetch.rateDist::samples 758170684 # Number of instructions fetched each cycle (Total)
635system.cpu0.fetch.rateDist::mean 0.951385 # Number of instructions fetched each cycle (Total)
636system.cpu0.fetch.rateDist::stdev 1.212910 # Number of instructions fetched each cycle (Total)
637system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
638system.cpu0.fetch.rateDist::0 412487393 54.41% 54.41% # Number of instructions fetched each cycle (Total)
639system.cpu0.fetch.rateDist::1 134584185 17.75% 72.16% # Number of instructions fetched each cycle (Total)
640system.cpu0.fetch.rateDist::2 46569297 6.14% 78.30% # Number of instructions fetched each cycle (Total)
641system.cpu0.fetch.rateDist::3 164529809 21.70% 100.00% # Number of instructions fetched each cycle (Total)
642system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
643system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
644system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
645system.cpu0.fetch.rateDist::total 758170684 # Number of instructions fetched each cycle (Total)
646system.cpu0.fetch.branchRate 0.177125 # Number of branch fetches per cycle
647system.cpu0.fetch.rate 0.784548 # Number of inst fetches per cycle
648system.cpu0.decode.IdleCycles 107249627 # Number of cycles decode is idle
649system.cpu0.decode.BlockedCycles 379334150 # Number of cycles decode is blocked
650system.cpu0.decode.RunCycles 227390625 # Number of cycles decode is running
651system.cpu0.decode.UnblockCycles 38947644 # Number of cycles decode is unblocking
652system.cpu0.decode.SquashCycles 5248638 # Number of cycles decode is squashing
653system.cpu0.decode.BranchResolved 19981467 # Number of times decode resolved a branch
654system.cpu0.decode.BranchMispred 2087891 # Number of times decode detected a branch misprediction
655system.cpu0.decode.DecodedInsts 636989334 # Number of instructions handled by decode
656system.cpu0.decode.SquashedInsts 23191131 # Number of squashed instructions handled by decode
657system.cpu0.rename.SquashCycles 5248638 # Number of cycles rename is squashing
658system.cpu0.rename.IdleCycles 143394034 # Number of cycles rename is idle
659system.cpu0.rename.BlockCycles 56142021 # Number of cycles rename is blocking
660system.cpu0.rename.serializeStallCycles 253850770 # count of cycles rename stalled for serializing inst
661system.cpu0.rename.RunCycles 229681319 # Number of cycles rename is running
662system.cpu0.rename.UnblockCycles 69853902 # Number of cycles rename is unblocking
663system.cpu0.rename.RenamedInsts 619319594 # Number of instructions processed by rename
664system.cpu0.rename.SquashedInsts 6178554 # Number of squashed instructions processed by rename
665system.cpu0.rename.ROBFullEvents 10862186 # Number of times rename has blocked due to ROB full
666system.cpu0.rename.IQFullEvents 388792 # Number of times rename has blocked due to IQ full
667system.cpu0.rename.LQFullEvents 930621 # Number of times rename has blocked due to LQ full
668system.cpu0.rename.SQFullEvents 33162716 # Number of times rename has blocked due to SQ full
669system.cpu0.rename.FullRegisterEvents 11693 # Number of times there has been no free registers
670system.cpu0.rename.RenamedOperands 591176589 # Number of destination operands rename has renamed
671system.cpu0.rename.RenameLookups 957415604 # Number of register rename lookups that rename has made
672system.cpu0.rename.int_rename_lookups 731049781 # Number of integer rename lookups
673system.cpu0.rename.fp_rename_lookups 649204 # Number of floating rename lookups
674system.cpu0.rename.CommittedMaps 532948721 # Number of HB maps that are committed
675system.cpu0.rename.UndoneMaps 58227868 # Number of HB maps that are undone due to squashing
676system.cpu0.rename.serializingInsts 16256269 # count of serializing insts renamed
677system.cpu0.rename.tempSerializingInsts 14199870 # count of temporary serializing insts renamed
678system.cpu0.rename.skidInsts 78279720 # count of insts added to the skid buffer
679system.cpu0.memDep0.insertedLoads 101593087 # Number of loads inserted to the mem dependence unit.
680system.cpu0.memDep0.insertedStores 85666218 # Number of stores inserted to the mem dependence unit.
681system.cpu0.memDep0.conflictingLoads 9630459 # Number of conflicting loads.
682system.cpu0.memDep0.conflictingStores 8075180 # Number of conflicting stores.
683system.cpu0.iq.iqInstsAdded 596126359 # Number of instructions added to the IQ (excludes non-spec)
684system.cpu0.iq.iqNonSpecInstsAdded 16460453 # Number of non-speculative instructions added to the IQ
685system.cpu0.iq.iqInstsIssued 601474893 # Number of instructions issued
686system.cpu0.iq.iqSquashedInstsIssued 2699291 # Number of squashed instructions issued
687system.cpu0.iq.iqSquashedInstsExamined 54684336 # Number of squashed instructions iterated over during squash; mainly for profiling
688system.cpu0.iq.iqSquashedOperandsExamined 35421563 # Number of squashed operands that are examined and possibly removed from graph
689system.cpu0.iq.iqSquashedNonSpecRemoved 283328 # Number of squashed non-spec instructions that were removed
690system.cpu0.iq.issued_per_cycle::samples 758170684 # Number of insts issued each cycle
691system.cpu0.iq.issued_per_cycle::mean 0.793324 # Number of insts issued each cycle
692system.cpu0.iq.issued_per_cycle::stdev 1.057959 # Number of insts issued each cycle
693system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
694system.cpu0.iq.issued_per_cycle::0 428799597 56.56% 56.56% # Number of insts issued each cycle
695system.cpu0.iq.issued_per_cycle::1 139371286 18.38% 74.94% # Number of insts issued each cycle
696system.cpu0.iq.issued_per_cycle::2 115828942 15.28% 90.22% # Number of insts issued each cycle
697system.cpu0.iq.issued_per_cycle::3 66243104 8.74% 98.95% # Number of insts issued each cycle
698system.cpu0.iq.issued_per_cycle::4 7922364 1.04% 100.00% # Number of insts issued each cycle
699system.cpu0.iq.issued_per_cycle::5 5391 0.00% 100.00% # Number of insts issued each cycle
700system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
701system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
702system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
703system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
704system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
705system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
706system.cpu0.iq.issued_per_cycle::total 758170684 # Number of insts issued each cycle
707system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
708system.cpu0.iq.fu_full::IntAlu 61955212 45.30% 45.30% # attempts to use FU when none available
709system.cpu0.iq.fu_full::IntMult 62513 0.05% 45.34% # attempts to use FU when none available
710system.cpu0.iq.fu_full::IntDiv 16729 0.01% 45.36% # attempts to use FU when none available
711system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.36% # attempts to use FU when none available
712system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.36% # attempts to use FU when none available
713system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.36% # attempts to use FU when none available
714system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.36% # attempts to use FU when none available
715system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 45.36% # attempts to use FU when none available
716system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.36% # attempts to use FU when none available
717system.cpu0.iq.fu_full::FloatMisc 21 0.00% 45.36% # attempts to use FU when none available
718system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.36% # attempts to use FU when none available
719system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.36% # attempts to use FU when none available
720system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.36% # attempts to use FU when none available
721system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.36% # attempts to use FU when none available
722system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.36% # attempts to use FU when none available
723system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.36% # attempts to use FU when none available
724system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.36% # attempts to use FU when none available
725system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.36% # attempts to use FU when none available
726system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.36% # attempts to use FU when none available
727system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.36% # attempts to use FU when none available
728system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.36% # attempts to use FU when none available
729system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.36% # attempts to use FU when none available
730system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.36% # attempts to use FU when none available
731system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.36% # attempts to use FU when none available
732system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.36% # attempts to use FU when none available
733system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.36% # attempts to use FU when none available
734system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.36% # attempts to use FU when none available
735system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 45.36% # attempts to use FU when none available
736system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.36% # attempts to use FU when none available
737system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.36% # attempts to use FU when none available
738system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.36% # attempts to use FU when none available
739system.cpu0.iq.fu_full::MemRead 36421436 26.63% 71.99% # attempts to use FU when none available
740system.cpu0.iq.fu_full::MemWrite 37996782 27.78% 99.77% # attempts to use FU when none available
741system.cpu0.iq.fu_full::FloatMemRead 31053 0.02% 99.79% # attempts to use FU when none available
742system.cpu0.iq.fu_full::FloatMemWrite 287360 0.21% 100.00% # attempts to use FU when none available
743system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
744system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
745system.cpu0.iq.FU_type_0::No_OpClass 30 0.00% 0.00% # Type of FU issued
746system.cpu0.iq.FU_type_0::IntAlu 411361741 68.39% 68.39% # Type of FU issued
747system.cpu0.iq.FU_type_0::IntMult 1567778 0.26% 68.65% # Type of FU issued
748system.cpu0.iq.FU_type_0::IntDiv 78948 0.01% 68.67% # Type of FU issued
749system.cpu0.iq.FU_type_0::FloatAdd 15 0.00% 68.67% # Type of FU issued
750system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.67% # Type of FU issued
751system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.67% # Type of FU issued
752system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.67% # Type of FU issued
753system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 68.67% # Type of FU issued
754system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.67% # Type of FU issued
755system.cpu0.iq.FU_type_0::FloatMisc 39915 0.01% 68.67% # Type of FU issued
756system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.67% # Type of FU issued
757system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.67% # Type of FU issued
758system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.67% # Type of FU issued
759system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.67% # Type of FU issued
760system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.67% # Type of FU issued
761system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.67% # Type of FU issued
762system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.67% # Type of FU issued
763system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.67% # Type of FU issued
764system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.67% # Type of FU issued
765system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.67% # Type of FU issued
766system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.67% # Type of FU issued
767system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.67% # Type of FU issued
768system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.67% # Type of FU issued
769system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.67% # Type of FU issued
770system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.67% # Type of FU issued
771system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.67% # Type of FU issued
772system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.67% # Type of FU issued
773system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.67% # Type of FU issued
774system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.67% # Type of FU issued
775system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.67% # Type of FU issued
776system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.67% # Type of FU issued
777system.cpu0.iq.FU_type_0::MemRead 104723474 17.41% 86.08% # Type of FU issued
778system.cpu0.iq.FU_type_0::MemWrite 83352955 13.86% 99.94% # Type of FU issued
779system.cpu0.iq.FU_type_0::FloatMemRead 49350 0.01% 99.95% # Type of FU issued
780system.cpu0.iq.FU_type_0::FloatMemWrite 300687 0.05% 100.00% # Type of FU issued
781system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
782system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
783system.cpu0.iq.FU_type_0::total 601474893 # Type of FU issued
784system.cpu0.iq.rate 0.765617 # Inst issue rate
785system.cpu0.iq.fu_busy_cnt 136771106 # FU busy when requested
786system.cpu0.iq.fu_busy_rate 0.227393 # FU busy rate (busy events/executed inst)
787system.cpu0.iq.int_inst_queue_reads 2099488112 # Number of integer instruction queue reads
788system.cpu0.iq.int_inst_queue_writes 667007258 # Number of integer instruction queue writes
789system.cpu0.iq.int_inst_queue_wakeup_accesses 583889559 # Number of integer instruction queue wakeup accesses
790system.cpu0.iq.fp_inst_queue_reads 1102755 # Number of floating instruction queue reads
791system.cpu0.iq.fp_inst_queue_writes 413748 # Number of floating instruction queue writes
792system.cpu0.iq.fp_inst_queue_wakeup_accesses 385073 # Number of floating instruction queue wakeup accesses
793system.cpu0.iq.int_alu_accesses 737537568 # Number of integer alu accesses
794system.cpu0.iq.fp_alu_accesses 708401 # Number of floating point alu accesses
795system.cpu0.iew.lsq.thread0.forwLoads 2768605 # Number of loads that had data forwarded from stores
796system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
797system.cpu0.iew.lsq.thread0.squashedLoads 12684669 # Number of loads squashed
798system.cpu0.iew.lsq.thread0.ignoredResponses 17846 # Number of memory responses ignored because the instruction is squashed
799system.cpu0.iew.lsq.thread0.memOrderViolation 151274 # Number of memory ordering violations
800system.cpu0.iew.lsq.thread0.squashedStores 5522197 # Number of stores squashed
801system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
802system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
803system.cpu0.iew.lsq.thread0.rescheduledLoads 2796342 # Number of loads that were rescheduled
804system.cpu0.iew.lsq.thread0.cacheBlocked 4797484 # Number of times an access to memory failed due to the cache being blocked
805system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
806system.cpu0.iew.iewSquashCycles 5248638 # Number of cycles IEW is squashing
807system.cpu0.iew.iewBlockCycles 8055865 # Number of cycles IEW is blocking
808system.cpu0.iew.iewUnblockCycles 1895421 # Number of cycles IEW is unblocking
809system.cpu0.iew.iewDispatchedInsts 612718172 # Number of instructions dispatched to IQ
810system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
811system.cpu0.iew.iewDispLoadInsts 101593087 # Number of dispatched load instructions
812system.cpu0.iew.iewDispStoreInsts 85666218 # Number of dispatched store instructions
813system.cpu0.iew.iewDispNonSpecInsts 13907446 # Number of dispatched non-speculative instructions
814system.cpu0.iew.iewIQFullEvents 58112 # Number of times the IQ has become full, causing a stall
815system.cpu0.iew.iewLSQFullEvents 1764578 # Number of times the LSQ has become full, causing a stall
816system.cpu0.iew.memOrderViolationEvents 151274 # Number of memory order violations
817system.cpu0.iew.predictedTakenIncorrect 1949210 # Number of branches that were predicted taken incorrectly
818system.cpu0.iew.predictedNotTakenIncorrect 3085558 # Number of branches that were predicted not taken incorrectly
819system.cpu0.iew.branchMispredicts 5034768 # Number of branch mispredicts detected at execute
820system.cpu0.iew.iewExecutedInsts 593488019 # Number of executed instructions
821system.cpu0.iew.iewExecLoadInsts 101560351 # Number of load instructions executed
822system.cpu0.iew.iewExecSquashedInsts 7385409 # Number of squashed instructions skipped in execute
823system.cpu0.iew.exec_swp 0 # number of swp insts executed
824system.cpu0.iew.exec_nop 131360 # number of nop insts executed
825system.cpu0.iew.exec_refs 183963466 # number of memory reference insts executed
826system.cpu0.iew.exec_branches 111638269 # Number of branches executed
827system.cpu0.iew.exec_stores 82403115 # Number of stores executed
828system.cpu0.iew.exec_rate 0.755450 # Inst execution rate
829system.cpu0.iew.wb_sent 585082868 # cumulative count of insts sent to commit
830system.cpu0.iew.wb_count 584274632 # cumulative count of insts written-back
831system.cpu0.iew.wb_producers 284506732 # num instructions producing a value
832system.cpu0.iew.wb_consumers 466304278 # num instructions consuming a value
833system.cpu0.iew.wb_rate 0.743723 # insts written-back per cycle
834system.cpu0.iew.wb_fanout 0.610131 # average fanout of values written-back
835system.cpu0.commit.commitSquashedInsts 47796807 # The number of squashed insts skipped by commit
836system.cpu0.commit.commitNonSpecStalls 16177125 # The number of times commit has been forced to stall to communicate backwards
837system.cpu0.commit.branchMispredicts 4684546 # The number of times a branch was mispredicted
838system.cpu0.commit.committed_per_cycle::samples 749065087 # Number of insts commited each cycle
839system.cpu0.commit.committed_per_cycle::mean 0.744798 # Number of insts commited each cycle
840system.cpu0.commit.committed_per_cycle::stdev 1.551758 # Number of insts commited each cycle
841system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
842system.cpu0.commit.committed_per_cycle::0 504468440 67.35% 67.35% # Number of insts commited each cycle
843system.cpu0.commit.committed_per_cycle::1 127495809 17.02% 84.37% # Number of insts commited each cycle
844system.cpu0.commit.committed_per_cycle::2 53846196 7.19% 91.56% # Number of insts commited each cycle
845system.cpu0.commit.committed_per_cycle::3 17894232 2.39% 93.94% # Number of insts commited each cycle
846system.cpu0.commit.committed_per_cycle::4 12874355 1.72% 95.66% # Number of insts commited each cycle
847system.cpu0.commit.committed_per_cycle::5 8922431 1.19% 96.85% # Number of insts commited each cycle
848system.cpu0.commit.committed_per_cycle::6 5996417 0.80% 97.65% # Number of insts commited each cycle
849system.cpu0.commit.committed_per_cycle::7 3594154 0.48% 98.13% # Number of insts commited each cycle
850system.cpu0.commit.committed_per_cycle::8 13973053 1.87% 100.00% # Number of insts commited each cycle
851system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
852system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
853system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
854system.cpu0.commit.committed_per_cycle::total 749065087 # Number of insts commited each cycle
855system.cpu0.commit.committedInsts 475226157 # Number of instructions committed
856system.cpu0.commit.committedOps 557902476 # Number of ops (including micro ops) committed
857system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
858system.cpu0.commit.refs 169052439 # Number of memory references committed
859system.cpu0.commit.loads 88908418 # Number of loads committed
860system.cpu0.commit.membars 3969625 # Number of memory barriers committed
861system.cpu0.commit.branches 106090436 # Number of branches committed
862system.cpu0.commit.fp_insts 377224 # Number of committed floating point instructions.
863system.cpu0.commit.int_insts 511981133 # Number of committed integer instructions.
864system.cpu0.commit.function_calls 14308761 # Number of function calls committed.
865system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
866system.cpu0.commit.op_class_0::IntAlu 387443640 69.45% 69.45% # Class of committed instruction
867system.cpu0.commit.op_class_0::IntMult 1310567 0.23% 69.68% # Class of committed instruction
868system.cpu0.commit.op_class_0::IntDiv 61901 0.01% 69.69% # Class of committed instruction
869system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.69% # Class of committed instruction
870system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.69% # Class of committed instruction
871system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.69% # Class of committed instruction
872system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.69% # Class of committed instruction
873system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 69.69% # Class of committed instruction
874system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.69% # Class of committed instruction
875system.cpu0.commit.op_class_0::FloatMisc 33929 0.01% 69.70% # Class of committed instruction
876system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction
877system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction
878system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction
879system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction
880system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction
881system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction
882system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction
883system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction
884system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction
885system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction
886system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction
887system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction
888system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.70% # Class of committed instruction
889system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction
890system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.70% # Class of committed instruction
891system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.70% # Class of committed instruction
892system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction
893system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 69.70% # Class of committed instruction
894system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.70% # Class of committed instruction
895system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.70% # Class of committed instruction
896system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.70% # Class of committed instruction
897system.cpu0.commit.op_class_0::MemRead 88862033 15.93% 85.63% # Class of committed instruction
898system.cpu0.commit.op_class_0::MemWrite 79847111 14.31% 99.94% # Class of committed instruction
899system.cpu0.commit.op_class_0::FloatMemRead 46385 0.01% 99.95% # Class of committed instruction
900system.cpu0.commit.op_class_0::FloatMemWrite 296910 0.05% 100.00% # Class of committed instruction
901system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
902system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
903system.cpu0.commit.op_class_0::total 557902476 # Class of committed instruction
904system.cpu0.commit.bw_lim_events 13973053 # number cycles where commit BW limit reached
905system.cpu0.rob.rob_reads 1336174255 # The number of ROB reads
906system.cpu0.rob.rob_writes 1220466867 # The number of ROB writes
907system.cpu0.timesIdled 1005352 # Number of times that the entire CPU went into an idle state and unscheduled itself
908system.cpu0.idleCycles 27437527 # Total number of cycles that the CPU has spent unscheduled due to idling
909system.cpu0.quiesceCycles 93984272695 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
910system.cpu0.committedInsts 475226157 # Number of Instructions Simulated
911system.cpu0.committedOps 557902476 # Number of Ops (including micro ops) Simulated
912system.cpu0.cpi 1.653125 # CPI: Cycles Per Instruction
913system.cpu0.cpi_total 1.653125 # CPI: Total CPI of All Threads
914system.cpu0.ipc 0.604915 # IPC: Instructions Per Cycle
915system.cpu0.ipc_total 0.604915 # IPC: Total IPC of All Threads
916system.cpu0.int_regfile_reads 700618930 # number of integer regfile reads
917system.cpu0.int_regfile_writes 416450651 # number of integer regfile writes
918system.cpu0.fp_regfile_reads 634669 # number of floating regfile reads
919system.cpu0.fp_regfile_writes 293776 # number of floating regfile writes
920system.cpu0.cc_regfile_reads 128889270 # number of cc regfile reads
921system.cpu0.cc_regfile_writes 129563151 # number of cc regfile writes
922system.cpu0.misc_regfile_reads 1347671553 # number of misc regfile reads
923system.cpu0.misc_regfile_writes 16172806 # number of misc regfile writes
924system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
925system.cpu0.dcache.tags.replacements 6286438 # number of replacements
926system.cpu0.dcache.tags.tagsinuse 484.582319 # Cycle average of tags in use
927system.cpu0.dcache.tags.total_refs 156315528 # Total number of references to valid blocks.
928system.cpu0.dcache.tags.sampled_refs 6286950 # Sample count of references to valid blocks.
929system.cpu0.dcache.tags.avg_refs 24.863492 # Average number of references to valid blocks.
930system.cpu0.dcache.tags.warmup_cycle 2049282000 # Cycle when the warmup percentage was hit.
931system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.582319 # Average occupied blocks per requestor
932system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946450 # Average percentage of cache occupancy
933system.cpu0.dcache.tags.occ_percent::total 0.946450 # Average percentage of cache occupancy
934system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
935system.cpu0.dcache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id
936system.cpu0.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id
937system.cpu0.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id
938system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
939system.cpu0.dcache.tags.tag_accesses 351060755 # Number of tag accesses
940system.cpu0.dcache.tags.data_accesses 351060755 # Number of data accesses
941system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
942system.cpu0.dcache.ReadReq_hits::cpu0.data 82089512 # number of ReadReq hits
943system.cpu0.dcache.ReadReq_hits::total 82089512 # number of ReadReq hits
944system.cpu0.dcache.WriteReq_hits::cpu0.data 69232216 # number of WriteReq hits
945system.cpu0.dcache.WriteReq_hits::total 69232216 # number of WriteReq hits
946system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209823 # number of SoftPFReq hits
947system.cpu0.dcache.SoftPFReq_hits::total 209823 # number of SoftPFReq hits
948system.cpu0.dcache.WriteLineReq_hits::cpu0.data 173405 # number of WriteLineReq hits
949system.cpu0.dcache.WriteLineReq_hits::total 173405 # number of WriteLineReq hits
950system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1868090 # number of LoadLockedReq hits
951system.cpu0.dcache.LoadLockedReq_hits::total 1868090 # number of LoadLockedReq hits
952system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1930069 # number of StoreCondReq hits
953system.cpu0.dcache.StoreCondReq_hits::total 1930069 # number of StoreCondReq hits
954system.cpu0.dcache.demand_hits::cpu0.data 151495133 # number of demand (read+write) hits
955system.cpu0.dcache.demand_hits::total 151495133 # number of demand (read+write) hits
956system.cpu0.dcache.overall_hits::cpu0.data 151704956 # number of overall hits
957system.cpu0.dcache.overall_hits::total 151704956 # number of overall hits
958system.cpu0.dcache.ReadReq_misses::cpu0.data 7010414 # number of ReadReq misses
959system.cpu0.dcache.ReadReq_misses::total 7010414 # number of ReadReq misses
960system.cpu0.dcache.WriteReq_misses::cpu0.data 7797174 # number of WriteReq misses
961system.cpu0.dcache.WriteReq_misses::total 7797174 # number of WriteReq misses
962system.cpu0.dcache.SoftPFReq_misses::cpu0.data 751824 # number of SoftPFReq misses
963system.cpu0.dcache.SoftPFReq_misses::total 751824 # number of SoftPFReq misses
964system.cpu0.dcache.WriteLineReq_misses::cpu0.data 805427 # number of WriteLineReq misses
965system.cpu0.dcache.WriteLineReq_misses::total 805427 # number of WriteLineReq misses
966system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 284725 # number of LoadLockedReq misses
967system.cpu0.dcache.LoadLockedReq_misses::total 284725 # number of LoadLockedReq misses
968system.cpu0.dcache.StoreCondReq_misses::cpu0.data 186829 # number of StoreCondReq misses
969system.cpu0.dcache.StoreCondReq_misses::total 186829 # number of StoreCondReq misses
970system.cpu0.dcache.demand_misses::cpu0.data 15613015 # number of demand (read+write) misses
971system.cpu0.dcache.demand_misses::total 15613015 # number of demand (read+write) misses
972system.cpu0.dcache.overall_misses::cpu0.data 16364839 # number of overall misses
973system.cpu0.dcache.overall_misses::total 16364839 # number of overall misses
974system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 112159926000 # number of ReadReq miss cycles
975system.cpu0.dcache.ReadReq_miss_latency::total 112159926000 # number of ReadReq miss cycles
976system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 158052575270 # number of WriteReq miss cycles
977system.cpu0.dcache.WriteReq_miss_latency::total 158052575270 # number of WriteReq miss cycles
978system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 29573159898 # number of WriteLineReq miss cycles
979system.cpu0.dcache.WriteLineReq_miss_latency::total 29573159898 # number of WriteLineReq miss cycles
980system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4301491500 # number of LoadLockedReq miss cycles
981system.cpu0.dcache.LoadLockedReq_miss_latency::total 4301491500 # number of LoadLockedReq miss cycles
982system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4484661500 # number of StoreCondReq miss cycles
983system.cpu0.dcache.StoreCondReq_miss_latency::total 4484661500 # number of StoreCondReq miss cycles
984system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2134500 # number of StoreCondFailReq miss cycles
985system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2134500 # number of StoreCondFailReq miss cycles
986system.cpu0.dcache.demand_miss_latency::cpu0.data 299785661168 # number of demand (read+write) miss cycles
987system.cpu0.dcache.demand_miss_latency::total 299785661168 # number of demand (read+write) miss cycles
988system.cpu0.dcache.overall_miss_latency::cpu0.data 299785661168 # number of overall miss cycles
989system.cpu0.dcache.overall_miss_latency::total 299785661168 # number of overall miss cycles
990system.cpu0.dcache.ReadReq_accesses::cpu0.data 89099926 # number of ReadReq accesses(hits+misses)
991system.cpu0.dcache.ReadReq_accesses::total 89099926 # number of ReadReq accesses(hits+misses)
992system.cpu0.dcache.WriteReq_accesses::cpu0.data 77029390 # number of WriteReq accesses(hits+misses)
993system.cpu0.dcache.WriteReq_accesses::total 77029390 # number of WriteReq accesses(hits+misses)
994system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 961647 # number of SoftPFReq accesses(hits+misses)
995system.cpu0.dcache.SoftPFReq_accesses::total 961647 # number of SoftPFReq accesses(hits+misses)
996system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 978832 # number of WriteLineReq accesses(hits+misses)
997system.cpu0.dcache.WriteLineReq_accesses::total 978832 # number of WriteLineReq accesses(hits+misses)
998system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2152815 # number of LoadLockedReq accesses(hits+misses)
999system.cpu0.dcache.LoadLockedReq_accesses::total 2152815 # number of LoadLockedReq accesses(hits+misses)
1000system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2116898 # number of StoreCondReq accesses(hits+misses)
1001system.cpu0.dcache.StoreCondReq_accesses::total 2116898 # number of StoreCondReq accesses(hits+misses)
1002system.cpu0.dcache.demand_accesses::cpu0.data 167108148 # number of demand (read+write) accesses
1003system.cpu0.dcache.demand_accesses::total 167108148 # number of demand (read+write) accesses
1004system.cpu0.dcache.overall_accesses::cpu0.data 168069795 # number of overall (read+write) accesses
1005system.cpu0.dcache.overall_accesses::total 168069795 # number of overall (read+write) accesses
1006system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.078680 # miss rate for ReadReq accesses
1007system.cpu0.dcache.ReadReq_miss_rate::total 0.078680 # miss rate for ReadReq accesses
1008system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.101223 # miss rate for WriteReq accesses
1009system.cpu0.dcache.WriteReq_miss_rate::total 0.101223 # miss rate for WriteReq accesses
1010system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781809 # miss rate for SoftPFReq accesses
1011system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781809 # miss rate for SoftPFReq accesses
1012system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.822845 # miss rate for WriteLineReq accesses
1013system.cpu0.dcache.WriteLineReq_miss_rate::total 0.822845 # miss rate for WriteLineReq accesses
1014system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.132257 # miss rate for LoadLockedReq accesses
1015system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.132257 # miss rate for LoadLockedReq accesses
1016system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.088256 # miss rate for StoreCondReq accesses
1017system.cpu0.dcache.StoreCondReq_miss_rate::total 0.088256 # miss rate for StoreCondReq accesses
1018system.cpu0.dcache.demand_miss_rate::cpu0.data 0.093431 # miss rate for demand accesses
1019system.cpu0.dcache.demand_miss_rate::total 0.093431 # miss rate for demand accesses
1020system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097369 # miss rate for overall accesses
1021system.cpu0.dcache.overall_miss_rate::total 0.097369 # miss rate for overall accesses
1022system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15999.044564 # average ReadReq miss latency
1023system.cpu0.dcache.ReadReq_avg_miss_latency::total 15999.044564 # average ReadReq miss latency
1024system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20270.494832 # average WriteReq miss latency
1025system.cpu0.dcache.WriteReq_avg_miss_latency::total 20270.494832 # average WriteReq miss latency
1026system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 36717.368424 # average WriteLineReq miss latency
1027system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 36717.368424 # average WriteLineReq miss latency
1028system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15107.530073 # average LoadLockedReq miss latency
1029system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15107.530073 # average LoadLockedReq miss latency
1030system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24004.097330 # average StoreCondReq miss latency
1031system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24004.097330 # average StoreCondReq miss latency
1032system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
1033system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1034system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19201.010258 # average overall miss latency
1035system.cpu0.dcache.demand_avg_miss_latency::total 19201.010258 # average overall miss latency
1036system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18318.888513 # average overall miss latency
1037system.cpu0.dcache.overall_avg_miss_latency::total 18318.888513 # average overall miss latency
1038system.cpu0.dcache.blocked_cycles::no_mshrs 8999058 # number of cycles access was blocked
1039system.cpu0.dcache.blocked_cycles::no_targets 24447381 # number of cycles access was blocked
1040system.cpu0.dcache.blocked::no_mshrs 751224 # number of cycles access was blocked
1041system.cpu0.dcache.blocked::no_targets 774000 # number of cycles access was blocked
1042system.cpu0.dcache.avg_blocked_cycles::no_mshrs 11.979194 # average number of cycles each access was blocked
1043system.cpu0.dcache.avg_blocked_cycles::no_targets 31.585764 # average number of cycles each access was blocked
1044system.cpu0.dcache.writebacks::writebacks 6286527 # number of writebacks
1045system.cpu0.dcache.writebacks::total 6286527 # number of writebacks
1046system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3589298 # number of ReadReq MSHR hits
1047system.cpu0.dcache.ReadReq_mshr_hits::total 3589298 # number of ReadReq MSHR hits
1048system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6265824 # number of WriteReq MSHR hits
1049system.cpu0.dcache.WriteReq_mshr_hits::total 6265824 # number of WriteReq MSHR hits
1050system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4129 # number of WriteLineReq MSHR hits
1051system.cpu0.dcache.WriteLineReq_mshr_hits::total 4129 # number of WriteLineReq MSHR hits
1052system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 147493 # number of LoadLockedReq MSHR hits
1053system.cpu0.dcache.LoadLockedReq_mshr_hits::total 147493 # number of LoadLockedReq MSHR hits
1054system.cpu0.dcache.demand_mshr_hits::cpu0.data 9859251 # number of demand (read+write) MSHR hits
1055system.cpu0.dcache.demand_mshr_hits::total 9859251 # number of demand (read+write) MSHR hits
1056system.cpu0.dcache.overall_mshr_hits::cpu0.data 9859251 # number of overall MSHR hits
1057system.cpu0.dcache.overall_mshr_hits::total 9859251 # number of overall MSHR hits
1058system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3421116 # number of ReadReq MSHR misses
1059system.cpu0.dcache.ReadReq_mshr_misses::total 3421116 # number of ReadReq MSHR misses
1060system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1531350 # number of WriteReq MSHR misses
1061system.cpu0.dcache.WriteReq_mshr_misses::total 1531350 # number of WriteReq MSHR misses
1062system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 745052 # number of SoftPFReq MSHR misses
1063system.cpu0.dcache.SoftPFReq_mshr_misses::total 745052 # number of SoftPFReq MSHR misses
1064system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 801298 # number of WriteLineReq MSHR misses
1065system.cpu0.dcache.WriteLineReq_mshr_misses::total 801298 # number of WriteLineReq MSHR misses
1066system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 137232 # number of LoadLockedReq MSHR misses
1067system.cpu0.dcache.LoadLockedReq_mshr_misses::total 137232 # number of LoadLockedReq MSHR misses
1068system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 186825 # number of StoreCondReq MSHR misses
1069system.cpu0.dcache.StoreCondReq_mshr_misses::total 186825 # number of StoreCondReq MSHR misses
1070system.cpu0.dcache.demand_mshr_misses::cpu0.data 5753764 # number of demand (read+write) MSHR misses
1071system.cpu0.dcache.demand_mshr_misses::total 5753764 # number of demand (read+write) MSHR misses
1072system.cpu0.dcache.overall_mshr_misses::cpu0.data 6498816 # number of overall MSHR misses
1073system.cpu0.dcache.overall_mshr_misses::total 6498816 # number of overall MSHR misses
1074system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29615 # number of ReadReq MSHR uncacheable
1075system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29615 # number of ReadReq MSHR uncacheable
1076system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 29691 # number of WriteReq MSHR uncacheable
1077system.cpu0.dcache.WriteReq_mshr_uncacheable::total 29691 # number of WriteReq MSHR uncacheable
1078system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 59306 # number of overall MSHR uncacheable misses
1079system.cpu0.dcache.overall_mshr_uncacheable_misses::total 59306 # number of overall MSHR uncacheable misses
1080system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 51678055000 # number of ReadReq MSHR miss cycles
1081system.cpu0.dcache.ReadReq_mshr_miss_latency::total 51678055000 # number of ReadReq MSHR miss cycles
1082system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 34197879948 # number of WriteReq MSHR miss cycles
1083system.cpu0.dcache.WriteReq_mshr_miss_latency::total 34197879948 # number of WriteReq MSHR miss cycles
1084system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17704904500 # number of SoftPFReq MSHR miss cycles
1085system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17704904500 # number of SoftPFReq MSHR miss cycles
1086system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28602356899 # number of WriteLineReq MSHR miss cycles
1087system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28602356899 # number of WriteLineReq MSHR miss cycles
1088system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1885182000 # number of LoadLockedReq MSHR miss cycles
1089system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1885182000 # number of LoadLockedReq MSHR miss cycles
1090system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4297888500 # number of StoreCondReq MSHR miss cycles
1091system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4297888500 # number of StoreCondReq MSHR miss cycles
1092system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2082500 # number of StoreCondFailReq MSHR miss cycles
1093system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2082500 # number of StoreCondFailReq MSHR miss cycles
1094system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 114478291847 # number of demand (read+write) MSHR miss cycles
1095system.cpu0.dcache.demand_mshr_miss_latency::total 114478291847 # number of demand (read+write) MSHR miss cycles
1096system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 132183196347 # number of overall MSHR miss cycles
1097system.cpu0.dcache.overall_mshr_miss_latency::total 132183196347 # number of overall MSHR miss cycles
1098system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5594868000 # number of ReadReq MSHR uncacheable cycles
1099system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5594868000 # number of ReadReq MSHR uncacheable cycles
1100system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5594868000 # number of overall MSHR uncacheable cycles
1101system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5594868000 # number of overall MSHR uncacheable cycles
1102system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.038396 # mshr miss rate for ReadReq accesses
1103system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038396 # mshr miss rate for ReadReq accesses
1104system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019880 # mshr miss rate for WriteReq accesses
1105system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019880 # mshr miss rate for WriteReq accesses
1106system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.774767 # mshr miss rate for SoftPFReq accesses
1107system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.774767 # mshr miss rate for SoftPFReq accesses
1108system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.818627 # mshr miss rate for WriteLineReq accesses
1109system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.818627 # mshr miss rate for WriteLineReq accesses
1110system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063745 # mshr miss rate for LoadLockedReq accesses
1111system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063745 # mshr miss rate for LoadLockedReq accesses
1112system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.088254 # mshr miss rate for StoreCondReq accesses
1113system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.088254 # mshr miss rate for StoreCondReq accesses
1114system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034431 # mshr miss rate for demand accesses
1115system.cpu0.dcache.demand_mshr_miss_rate::total 0.034431 # mshr miss rate for demand accesses
1116system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038667 # mshr miss rate for overall accesses
1117system.cpu0.dcache.overall_mshr_miss_rate::total 0.038667 # mshr miss rate for overall accesses
1118system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15105.613198 # average ReadReq mshr miss latency
1119system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15105.613198 # average ReadReq mshr miss latency
1120system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22331.850947 # average WriteReq mshr miss latency
1121system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22331.850947 # average WriteReq mshr miss latency
1122system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23763.313836 # average SoftPFReq mshr miss latency
1123system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23763.313836 # average SoftPFReq mshr miss latency
1124system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 35695.030936 # average WriteLineReq mshr miss latency
1125system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 35695.030936 # average WriteLineReq mshr miss latency
1126system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13737.189577 # average LoadLockedReq mshr miss latency
1127system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13737.189577 # average LoadLockedReq mshr miss latency
1128system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23004.889603 # average StoreCondReq mshr miss latency
1129system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23004.889603 # average StoreCondReq mshr miss latency
1130system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
1131system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1132system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19896.243893 # average overall mshr miss latency
1133system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19896.243893 # average overall mshr miss latency
1134system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20339.581294 # average overall mshr miss latency
1135system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20339.581294 # average overall mshr miss latency
1136system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188920.074287 # average ReadReq mshr uncacheable latency
1137system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188920.074287 # average ReadReq mshr uncacheable latency
1138system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 94338.987624 # average overall mshr uncacheable latency
1139system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 94338.987624 # average overall mshr uncacheable latency
1140system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
1141system.cpu0.icache.tags.replacements 5974428 # number of replacements
1142system.cpu0.icache.tags.tagsinuse 511.960293 # Cycle average of tags in use
1143system.cpu0.icache.tags.total_refs 212911456 # Total number of references to valid blocks.
1144system.cpu0.icache.tags.sampled_refs 5974940 # Sample count of references to valid blocks.
1145system.cpu0.icache.tags.avg_refs 35.634074 # Average number of references to valid blocks.
1146system.cpu0.icache.tags.warmup_cycle 13477910000 # Cycle when the warmup percentage was hit.
1147system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960293 # Average occupied blocks per requestor
1148system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999922 # Average percentage of cache occupancy
1149system.cpu0.icache.tags.occ_percent::total 0.999922 # Average percentage of cache occupancy
1150system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1151system.cpu0.icache.tags.age_task_id_blocks_1024::0 293 # Occupied blocks per task id
1152system.cpu0.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
1153system.cpu0.icache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id
1154system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1155system.cpu0.icache.tags.tag_accesses 444450377 # Number of tag accesses
1156system.cpu0.icache.tags.data_accesses 444450377 # Number of data accesses
1157system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
1158system.cpu0.icache.ReadReq_hits::cpu0.inst 212911456 # number of ReadReq hits
1159system.cpu0.icache.ReadReq_hits::total 212911456 # number of ReadReq hits
1160system.cpu0.icache.demand_hits::cpu0.inst 212911456 # number of demand (read+write) hits
1161system.cpu0.icache.demand_hits::total 212911456 # number of demand (read+write) hits
1162system.cpu0.icache.overall_hits::cpu0.inst 212911456 # number of overall hits
1163system.cpu0.icache.overall_hits::total 212911456 # number of overall hits
1164system.cpu0.icache.ReadReq_misses::cpu0.inst 6326229 # number of ReadReq misses
1165system.cpu0.icache.ReadReq_misses::total 6326229 # number of ReadReq misses
1166system.cpu0.icache.demand_misses::cpu0.inst 6326229 # number of demand (read+write) misses
1167system.cpu0.icache.demand_misses::total 6326229 # number of demand (read+write) misses
1168system.cpu0.icache.overall_misses::cpu0.inst 6326229 # number of overall misses
1169system.cpu0.icache.overall_misses::total 6326229 # number of overall misses
1170system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 70930890398 # number of ReadReq miss cycles
1171system.cpu0.icache.ReadReq_miss_latency::total 70930890398 # number of ReadReq miss cycles
1172system.cpu0.icache.demand_miss_latency::cpu0.inst 70930890398 # number of demand (read+write) miss cycles
1173system.cpu0.icache.demand_miss_latency::total 70930890398 # number of demand (read+write) miss cycles
1174system.cpu0.icache.overall_miss_latency::cpu0.inst 70930890398 # number of overall miss cycles
1175system.cpu0.icache.overall_miss_latency::total 70930890398 # number of overall miss cycles
1176system.cpu0.icache.ReadReq_accesses::cpu0.inst 219237685 # number of ReadReq accesses(hits+misses)
1177system.cpu0.icache.ReadReq_accesses::total 219237685 # number of ReadReq accesses(hits+misses)
1178system.cpu0.icache.demand_accesses::cpu0.inst 219237685 # number of demand (read+write) accesses
1179system.cpu0.icache.demand_accesses::total 219237685 # number of demand (read+write) accesses
1180system.cpu0.icache.overall_accesses::cpu0.inst 219237685 # number of overall (read+write) accesses
1181system.cpu0.icache.overall_accesses::total 219237685 # number of overall (read+write) accesses
1182system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028856 # miss rate for ReadReq accesses
1183system.cpu0.icache.ReadReq_miss_rate::total 0.028856 # miss rate for ReadReq accesses
1184system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028856 # miss rate for demand accesses
1185system.cpu0.icache.demand_miss_rate::total 0.028856 # miss rate for demand accesses
1186system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028856 # miss rate for overall accesses
1187system.cpu0.icache.overall_miss_rate::total 0.028856 # miss rate for overall accesses
1188system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11212.191402 # average ReadReq miss latency
1189system.cpu0.icache.ReadReq_avg_miss_latency::total 11212.191402 # average ReadReq miss latency
1190system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11212.191402 # average overall miss latency
1191system.cpu0.icache.demand_avg_miss_latency::total 11212.191402 # average overall miss latency
1192system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11212.191402 # average overall miss latency
1193system.cpu0.icache.overall_avg_miss_latency::total 11212.191402 # average overall miss latency
1194system.cpu0.icache.blocked_cycles::no_mshrs 10513720 # number of cycles access was blocked
1195system.cpu0.icache.blocked_cycles::no_targets 1665 # number of cycles access was blocked
1196system.cpu0.icache.blocked::no_mshrs 740505 # number of cycles access was blocked
1197system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked
1198system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.198041 # average number of cycles each access was blocked
1199system.cpu0.icache.avg_blocked_cycles::no_targets 128.076923 # average number of cycles each access was blocked
1200system.cpu0.icache.writebacks::writebacks 5974428 # number of writebacks
1201system.cpu0.icache.writebacks::total 5974428 # number of writebacks
1202system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 351221 # number of ReadReq MSHR hits
1203system.cpu0.icache.ReadReq_mshr_hits::total 351221 # number of ReadReq MSHR hits
1204system.cpu0.icache.demand_mshr_hits::cpu0.inst 351221 # number of demand (read+write) MSHR hits
1205system.cpu0.icache.demand_mshr_hits::total 351221 # number of demand (read+write) MSHR hits
1206system.cpu0.icache.overall_mshr_hits::cpu0.inst 351221 # number of overall MSHR hits
1207system.cpu0.icache.overall_mshr_hits::total 351221 # number of overall MSHR hits
1208system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5975008 # number of ReadReq MSHR misses
1209system.cpu0.icache.ReadReq_mshr_misses::total 5975008 # number of ReadReq MSHR misses
1210system.cpu0.icache.demand_mshr_misses::cpu0.inst 5975008 # number of demand (read+write) MSHR misses
1211system.cpu0.icache.demand_mshr_misses::total 5975008 # number of demand (read+write) MSHR misses
1212system.cpu0.icache.overall_mshr_misses::cpu0.inst 5975008 # number of overall MSHR misses
1213system.cpu0.icache.overall_mshr_misses::total 5975008 # number of overall MSHR misses
1214system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
1215system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable
1216system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
1217system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses
1218system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 63931230447 # number of ReadReq MSHR miss cycles
1219system.cpu0.icache.ReadReq_mshr_miss_latency::total 63931230447 # number of ReadReq MSHR miss cycles
1220system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 63931230447 # number of demand (read+write) MSHR miss cycles
1221system.cpu0.icache.demand_mshr_miss_latency::total 63931230447 # number of demand (read+write) MSHR miss cycles
1222system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 63931230447 # number of overall MSHR miss cycles
1223system.cpu0.icache.overall_mshr_miss_latency::total 63931230447 # number of overall MSHR miss cycles
1224system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2027158498 # number of ReadReq MSHR uncacheable cycles
1225system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2027158498 # number of ReadReq MSHR uncacheable cycles
1226system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2027158498 # number of overall MSHR uncacheable cycles
1227system.cpu0.icache.overall_mshr_uncacheable_latency::total 2027158498 # number of overall MSHR uncacheable cycles
1228system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027254 # mshr miss rate for ReadReq accesses
1229system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027254 # mshr miss rate for ReadReq accesses
1230system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027254 # mshr miss rate for demand accesses
1231system.cpu0.icache.demand_mshr_miss_rate::total 0.027254 # mshr miss rate for demand accesses
1232system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027254 # mshr miss rate for overall accesses
1233system.cpu0.icache.overall_mshr_miss_rate::total 0.027254 # mshr miss rate for overall accesses
1234system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10699.773196 # average ReadReq mshr miss latency
1235system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10699.773196 # average ReadReq mshr miss latency
1236system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10699.773196 # average overall mshr miss latency
1237system.cpu0.icache.demand_avg_mshr_miss_latency::total 10699.773196 # average overall mshr miss latency
1238system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10699.773196 # average overall mshr miss latency
1239system.cpu0.icache.overall_avg_mshr_miss_latency::total 10699.773196 # average overall mshr miss latency
1240system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856 # average ReadReq mshr uncacheable latency
1241system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95203.047856 # average ReadReq mshr uncacheable latency
1242system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856 # average overall mshr uncacheable latency
1243system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95203.047856 # average overall mshr uncacheable latency
1244system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
1245system.cpu0.l2cache.prefetcher.num_hwpf_issued 8714333 # number of hwpf issued
1246system.cpu0.l2cache.prefetcher.pfIdentified 8724211 # number of prefetch candidates identified
1247system.cpu0.l2cache.prefetcher.pfBufferHit 8793 # number of redundant prefetches already in prefetch queue
1248system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1249system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1250system.cpu0.l2cache.prefetcher.pfSpanPage 1114037 # number of prefetches not generated due to page crossing
1251system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
1252system.cpu0.l2cache.tags.replacements 2711723 # number of replacements
1253system.cpu0.l2cache.tags.tagsinuse 15840.616895 # Cycle average of tags in use
1254system.cpu0.l2cache.tags.total_refs 10811538 # Total number of references to valid blocks.
1255system.cpu0.l2cache.tags.sampled_refs 2727125 # Sample count of references to valid blocks.
1256system.cpu0.l2cache.tags.avg_refs 3.964445 # Average number of references to valid blocks.
1257system.cpu0.l2cache.tags.warmup_cycle 2357982000 # Cycle when the warmup percentage was hit.
1258system.cpu0.l2cache.tags.occ_blocks::writebacks 15519.308256 # Average occupied blocks per requestor
1259system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 33.621063 # Average occupied blocks per requestor
1260system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 19.237059 # Average occupied blocks per requestor
1261system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000001 # Average occupied blocks per requestor
1262system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 268.450517 # Average occupied blocks per requestor
1263system.cpu0.l2cache.tags.occ_percent::writebacks 0.947223 # Average percentage of cache occupancy
1264system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002052 # Average percentage of cache occupancy
1265system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001174 # Average percentage of cache occupancy
1266system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy
1267system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.016385 # Average percentage of cache occupancy
1268system.cpu0.l2cache.tags.occ_percent::total 0.966835 # Average percentage of cache occupancy
1269system.cpu0.l2cache.tags.occ_task_id_blocks::1022 381 # Occupied blocks per task id
1270system.cpu0.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id
1271system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14929 # Occupied blocks per task id
1272system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 75 # Occupied blocks per task id
1273system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 118 # Occupied blocks per task id
1274system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 93 # Occupied blocks per task id
1275system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 95 # Occupied blocks per task id
1276system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id
1277system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 69 # Occupied blocks per task id
1278system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
1279system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id
1280system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 499 # Occupied blocks per task id
1281system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1082 # Occupied blocks per task id
1282system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5719 # Occupied blocks per task id
1283system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5657 # Occupied blocks per task id
1284system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1972 # Occupied blocks per task id
1285system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.023254 # Percentage of cache occupancy per task id
1286system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id
1287system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.911194 # Percentage of cache occupancy per task id
1288system.cpu0.l2cache.tags.tag_accesses 427199165 # Number of tag accesses
1289system.cpu0.l2cache.tags.data_accesses 427199165 # Number of data accesses
1290system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
1291system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 602660 # number of ReadReq hits
1292system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 185799 # number of ReadReq hits
1293system.cpu0.l2cache.ReadReq_hits::total 788459 # number of ReadReq hits
1294system.cpu0.l2cache.WritebackDirty_hits::writebacks 4096903 # number of WritebackDirty hits
1295system.cpu0.l2cache.WritebackDirty_hits::total 4096903 # number of WritebackDirty hits
1296system.cpu0.l2cache.WritebackClean_hits::writebacks 8161916 # number of WritebackClean hits
1297system.cpu0.l2cache.WritebackClean_hits::total 8161916 # number of WritebackClean hits
1298system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 32 # number of UpgradeReq hits
1299system.cpu0.l2cache.UpgradeReq_hits::total 32 # number of UpgradeReq hits
1300system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits
1301system.cpu0.l2cache.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits
1302system.cpu0.l2cache.ReadExReq_hits::cpu0.data 986017 # number of ReadExReq hits
1303system.cpu0.l2cache.ReadExReq_hits::total 986017 # number of ReadExReq hits
1304system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5386829 # number of ReadCleanReq hits
1305system.cpu0.l2cache.ReadCleanReq_hits::total 5386829 # number of ReadCleanReq hits
1306system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3255809 # number of ReadSharedReq hits
1307system.cpu0.l2cache.ReadSharedReq_hits::total 3255809 # number of ReadSharedReq hits
1308system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 183461 # number of InvalidateReq hits
1309system.cpu0.l2cache.InvalidateReq_hits::total 183461 # number of InvalidateReq hits
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1311system.cpu0.l2cache.demand_hits::cpu0.itb.walker 185799 # number of demand (read+write) hits
1312system.cpu0.l2cache.demand_hits::cpu0.inst 5386829 # number of demand (read+write) hits
1313system.cpu0.l2cache.demand_hits::cpu0.data 4241826 # number of demand (read+write) hits
1314system.cpu0.l2cache.demand_hits::total 10417114 # number of demand (read+write) hits
1315system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 602660 # number of overall hits
1316system.cpu0.l2cache.overall_hits::cpu0.itb.walker 185799 # number of overall hits
1317system.cpu0.l2cache.overall_hits::cpu0.inst 5386829 # number of overall hits
1318system.cpu0.l2cache.overall_hits::cpu0.data 4241826 # number of overall hits
1319system.cpu0.l2cache.overall_hits::total 10417114 # number of overall hits
1320system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 25200 # number of ReadReq misses
1321system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 12620 # number of ReadReq misses
1322system.cpu0.l2cache.ReadReq_misses::total 37820 # number of ReadReq misses
1323system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 257381 # number of UpgradeReq misses
1324system.cpu0.l2cache.UpgradeReq_misses::total 257381 # number of UpgradeReq misses
1325system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 186815 # number of SCUpgradeReq misses
1326system.cpu0.l2cache.SCUpgradeReq_misses::total 186815 # number of SCUpgradeReq misses
1327system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses
1328system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses
1329system.cpu0.l2cache.ReadExReq_misses::cpu0.data 295278 # number of ReadExReq misses
1330system.cpu0.l2cache.ReadExReq_misses::total 295278 # number of ReadExReq misses
1331system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 588130 # number of ReadCleanReq misses
1332system.cpu0.l2cache.ReadCleanReq_misses::total 588130 # number of ReadCleanReq misses
1333system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1045192 # number of ReadSharedReq misses
1334system.cpu0.l2cache.ReadSharedReq_misses::total 1045192 # number of ReadSharedReq misses
1335system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 617837 # number of InvalidateReq misses
1336system.cpu0.l2cache.InvalidateReq_misses::total 617837 # number of InvalidateReq misses
1337system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 25200 # number of demand (read+write) misses
1338system.cpu0.l2cache.demand_misses::cpu0.itb.walker 12620 # number of demand (read+write) misses
1339system.cpu0.l2cache.demand_misses::cpu0.inst 588130 # number of demand (read+write) misses
1340system.cpu0.l2cache.demand_misses::cpu0.data 1340470 # number of demand (read+write) misses
1341system.cpu0.l2cache.demand_misses::total 1966420 # number of demand (read+write) misses
1342system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 25200 # number of overall misses
1343system.cpu0.l2cache.overall_misses::cpu0.itb.walker 12620 # number of overall misses
1344system.cpu0.l2cache.overall_misses::cpu0.inst 588130 # number of overall misses
1345system.cpu0.l2cache.overall_misses::cpu0.data 1340470 # number of overall misses
1346system.cpu0.l2cache.overall_misses::total 1966420 # number of overall misses
1347system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 896455000 # number of ReadReq miss cycles
1348system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 597646500 # number of ReadReq miss cycles
1349system.cpu0.l2cache.ReadReq_miss_latency::total 1494101500 # number of ReadReq miss cycles
1350system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 982091000 # number of UpgradeReq miss cycles
1351system.cpu0.l2cache.UpgradeReq_miss_latency::total 982091000 # number of UpgradeReq miss cycles
1352system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 295025000 # number of SCUpgradeReq miss cycles
1353system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 295025000 # number of SCUpgradeReq miss cycles
1354system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2003000 # number of SCUpgradeFailReq miss cycles
1355system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2003000 # number of SCUpgradeFailReq miss cycles
1356system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 18413910498 # number of ReadExReq miss cycles
1357system.cpu0.l2cache.ReadExReq_miss_latency::total 18413910498 # number of ReadExReq miss cycles
1358system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 22335302000 # number of ReadCleanReq miss cycles
1359system.cpu0.l2cache.ReadCleanReq_miss_latency::total 22335302000 # number of ReadCleanReq miss cycles
1360system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 43094995483 # number of ReadSharedReq miss cycles
1361system.cpu0.l2cache.ReadSharedReq_miss_latency::total 43094995483 # number of ReadSharedReq miss cycles
1362system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 882000 # number of InvalidateReq miss cycles
1363system.cpu0.l2cache.InvalidateReq_miss_latency::total 882000 # number of InvalidateReq miss cycles
1364system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 896455000 # number of demand (read+write) miss cycles
1365system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 597646500 # number of demand (read+write) miss cycles
1366system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22335302000 # number of demand (read+write) miss cycles
1367system.cpu0.l2cache.demand_miss_latency::cpu0.data 61508905981 # number of demand (read+write) miss cycles
1368system.cpu0.l2cache.demand_miss_latency::total 85338309481 # number of demand (read+write) miss cycles
1369system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 896455000 # number of overall miss cycles
1370system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 597646500 # number of overall miss cycles
1371system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22335302000 # number of overall miss cycles
1372system.cpu0.l2cache.overall_miss_latency::cpu0.data 61508905981 # number of overall miss cycles
1373system.cpu0.l2cache.overall_miss_latency::total 85338309481 # number of overall miss cycles
1374system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 627860 # number of ReadReq accesses(hits+misses)
1375system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 198419 # number of ReadReq accesses(hits+misses)
1376system.cpu0.l2cache.ReadReq_accesses::total 826279 # number of ReadReq accesses(hits+misses)
1377system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4096903 # number of WritebackDirty accesses(hits+misses)
1378system.cpu0.l2cache.WritebackDirty_accesses::total 4096903 # number of WritebackDirty accesses(hits+misses)
1379system.cpu0.l2cache.WritebackClean_accesses::writebacks 8161916 # number of WritebackClean accesses(hits+misses)
1380system.cpu0.l2cache.WritebackClean_accesses::total 8161916 # number of WritebackClean accesses(hits+misses)
1381system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 257413 # number of UpgradeReq accesses(hits+misses)
1382system.cpu0.l2cache.UpgradeReq_accesses::total 257413 # number of UpgradeReq accesses(hits+misses)
1383system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 186820 # number of SCUpgradeReq accesses(hits+misses)
1384system.cpu0.l2cache.SCUpgradeReq_accesses::total 186820 # number of SCUpgradeReq accesses(hits+misses)
1385system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses)
1386system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses)
1387system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1281295 # number of ReadExReq accesses(hits+misses)
1388system.cpu0.l2cache.ReadExReq_accesses::total 1281295 # number of ReadExReq accesses(hits+misses)
1389system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5974959 # number of ReadCleanReq accesses(hits+misses)
1390system.cpu0.l2cache.ReadCleanReq_accesses::total 5974959 # number of ReadCleanReq accesses(hits+misses)
1391system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4301001 # number of ReadSharedReq accesses(hits+misses)
1392system.cpu0.l2cache.ReadSharedReq_accesses::total 4301001 # number of ReadSharedReq accesses(hits+misses)
1393system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 801298 # number of InvalidateReq accesses(hits+misses)
1394system.cpu0.l2cache.InvalidateReq_accesses::total 801298 # number of InvalidateReq accesses(hits+misses)
1395system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 627860 # number of demand (read+write) accesses
1396system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 198419 # number of demand (read+write) accesses
1397system.cpu0.l2cache.demand_accesses::cpu0.inst 5974959 # number of demand (read+write) accesses
1398system.cpu0.l2cache.demand_accesses::cpu0.data 5582296 # number of demand (read+write) accesses
1399system.cpu0.l2cache.demand_accesses::total 12383534 # number of demand (read+write) accesses
1400system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 627860 # number of overall (read+write) accesses
1401system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 198419 # number of overall (read+write) accesses
1402system.cpu0.l2cache.overall_accesses::cpu0.inst 5974959 # number of overall (read+write) accesses
1403system.cpu0.l2cache.overall_accesses::cpu0.data 5582296 # number of overall (read+write) accesses
1404system.cpu0.l2cache.overall_accesses::total 12383534 # number of overall (read+write) accesses
1405system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.040136 # miss rate for ReadReq accesses
1406system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.063603 # miss rate for ReadReq accesses
1407system.cpu0.l2cache.ReadReq_miss_rate::total 0.045771 # miss rate for ReadReq accesses
1408system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999876 # miss rate for UpgradeReq accesses
1409system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999876 # miss rate for UpgradeReq accesses
1410system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999973 # miss rate for SCUpgradeReq accesses
1411system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999973 # miss rate for SCUpgradeReq accesses
1412system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1413system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1414system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.230453 # miss rate for ReadExReq accesses
1415system.cpu0.l2cache.ReadExReq_miss_rate::total 0.230453 # miss rate for ReadExReq accesses
1416system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.098432 # miss rate for ReadCleanReq accesses
1417system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.098432 # miss rate for ReadCleanReq accesses
1418system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.243011 # miss rate for ReadSharedReq accesses
1419system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.243011 # miss rate for ReadSharedReq accesses
1420system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.771045 # miss rate for InvalidateReq accesses
1421system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.771045 # miss rate for InvalidateReq accesses
1422system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.040136 # miss rate for demand accesses
1423system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.063603 # miss rate for demand accesses
1424system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.098432 # miss rate for demand accesses
1425system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.240129 # miss rate for demand accesses
1426system.cpu0.l2cache.demand_miss_rate::total 0.158793 # miss rate for demand accesses
1427system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.040136 # miss rate for overall accesses
1428system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.063603 # miss rate for overall accesses
1429system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.098432 # miss rate for overall accesses
1430system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.240129 # miss rate for overall accesses
1431system.cpu0.l2cache.overall_miss_rate::total 0.158793 # miss rate for overall accesses
1432system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35573.611111 # average ReadReq miss latency
1433system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 47357.091918 # average ReadReq miss latency
1434system.cpu0.l2cache.ReadReq_avg_miss_latency::total 39505.592279 # average ReadReq miss latency
1435system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3815.709007 # average UpgradeReq miss latency
1436system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3815.709007 # average UpgradeReq miss latency
1437system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1579.236143 # average SCUpgradeReq miss latency
1438system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1579.236143 # average SCUpgradeReq miss latency
1439system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 400600 # average SCUpgradeFailReq miss latency
1440system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 400600 # average SCUpgradeFailReq miss latency
1441system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 62361.268019 # average ReadExReq miss latency
1442system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 62361.268019 # average ReadExReq miss latency
1443system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37976.811249 # average ReadCleanReq miss latency
1444system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37976.811249 # average ReadCleanReq miss latency
1445system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41231.654551 # average ReadSharedReq miss latency
1446system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41231.654551 # average ReadSharedReq miss latency
1447system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 1.427561 # average InvalidateReq miss latency
1448system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 1.427561 # average InvalidateReq miss latency
1449system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35573.611111 # average overall miss latency
1450system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 47357.091918 # average overall miss latency
1451system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37976.811249 # average overall miss latency
1452system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45886.074273 # average overall miss latency
1453system.cpu0.l2cache.demand_avg_miss_latency::total 43397.803867 # average overall miss latency
1454system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35573.611111 # average overall miss latency
1455system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 47357.091918 # average overall miss latency
1456system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37976.811249 # average overall miss latency
1457system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45886.074273 # average overall miss latency
1458system.cpu0.l2cache.overall_avg_miss_latency::total 43397.803867 # average overall miss latency
1459system.cpu0.l2cache.blocked_cycles::no_mshrs 1100 # number of cycles access was blocked
1460system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1461system.cpu0.l2cache.blocked::no_mshrs 24 # number of cycles access was blocked
1462system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1463system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 45.833333 # average number of cycles each access was blocked
1464system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1465system.cpu0.l2cache.unused_prefetches 49027 # number of HardPF blocks evicted w/o reference
1466system.cpu0.l2cache.writebacks::writebacks 1747264 # number of writebacks
1467system.cpu0.l2cache.writebacks::total 1747264 # number of writebacks
1468system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 192 # number of ReadReq MSHR hits
1469system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 348 # number of ReadReq MSHR hits
1470system.cpu0.l2cache.ReadReq_mshr_hits::total 540 # number of ReadReq MSHR hits
1471system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 21118 # number of ReadExReq MSHR hits
1472system.cpu0.l2cache.ReadExReq_mshr_hits::total 21118 # number of ReadExReq MSHR hits
1473system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 4 # number of ReadCleanReq MSHR hits
1474system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits
1475system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 5796 # number of ReadSharedReq MSHR hits
1476system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 5796 # number of ReadSharedReq MSHR hits
1477system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 13 # number of InvalidateReq MSHR hits
1478system.cpu0.l2cache.InvalidateReq_mshr_hits::total 13 # number of InvalidateReq MSHR hits
1479system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 192 # number of demand (read+write) MSHR hits
1480system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 348 # number of demand (read+write) MSHR hits
1481system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits
1482system.cpu0.l2cache.demand_mshr_hits::cpu0.data 26914 # number of demand (read+write) MSHR hits
1483system.cpu0.l2cache.demand_mshr_hits::total 27458 # number of demand (read+write) MSHR hits
1484system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 192 # number of overall MSHR hits
1485system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 348 # number of overall MSHR hits
1486system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits
1487system.cpu0.l2cache.overall_mshr_hits::cpu0.data 26914 # number of overall MSHR hits
1488system.cpu0.l2cache.overall_mshr_hits::total 27458 # number of overall MSHR hits
1489system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 25008 # number of ReadReq MSHR misses
1490system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 12272 # number of ReadReq MSHR misses
1491system.cpu0.l2cache.ReadReq_mshr_misses::total 37280 # number of ReadReq MSHR misses
1492system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 914694 # number of HardPFReq MSHR misses
1493system.cpu0.l2cache.HardPFReq_mshr_misses::total 914694 # number of HardPFReq MSHR misses
1494system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 257381 # number of UpgradeReq MSHR misses
1495system.cpu0.l2cache.UpgradeReq_mshr_misses::total 257381 # number of UpgradeReq MSHR misses
1496system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 186815 # number of SCUpgradeReq MSHR misses
1497system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 186815 # number of SCUpgradeReq MSHR misses
1498system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses
1499system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses
1500system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 274160 # number of ReadExReq MSHR misses
1501system.cpu0.l2cache.ReadExReq_mshr_misses::total 274160 # number of ReadExReq MSHR misses
1502system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 588126 # number of ReadCleanReq MSHR misses
1503system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 588126 # number of ReadCleanReq MSHR misses
1504system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1039396 # number of ReadSharedReq MSHR misses
1505system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1039396 # number of ReadSharedReq MSHR misses
1506system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 617824 # number of InvalidateReq MSHR misses
1507system.cpu0.l2cache.InvalidateReq_mshr_misses::total 617824 # number of InvalidateReq MSHR misses
1508system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 25008 # number of demand (read+write) MSHR misses
1509system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 12272 # number of demand (read+write) MSHR misses
1510system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 588126 # number of demand (read+write) MSHR misses
1511system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1313556 # number of demand (read+write) MSHR misses
1512system.cpu0.l2cache.demand_mshr_misses::total 1938962 # number of demand (read+write) MSHR misses
1513system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 25008 # number of overall MSHR misses
1514system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 12272 # number of overall MSHR misses
1515system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 588126 # number of overall MSHR misses
1516system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1313556 # number of overall MSHR misses
1517system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 914694 # number of overall MSHR misses
1518system.cpu0.l2cache.overall_mshr_misses::total 2853656 # number of overall MSHR misses
1519system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
1520system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29615 # number of ReadReq MSHR uncacheable
1521system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 50908 # number of ReadReq MSHR uncacheable
1522system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 29691 # number of WriteReq MSHR uncacheable
1523system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 29691 # number of WriteReq MSHR uncacheable
1524system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
1525system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 59306 # number of overall MSHR uncacheable misses
1526system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 80599 # number of overall MSHR uncacheable misses
1527system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 742635500 # number of ReadReq MSHR miss cycles
1528system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 518427500 # number of ReadReq MSHR miss cycles
1529system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1261063000 # number of ReadReq MSHR miss cycles
1530system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 57180143123 # number of HardPFReq MSHR miss cycles
1531system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 57180143123 # number of HardPFReq MSHR miss cycles
1532system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4798228494 # number of UpgradeReq MSHR miss cycles
1533system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4798228494 # number of UpgradeReq MSHR miss cycles
1534system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2893409994 # number of SCUpgradeReq MSHR miss cycles
1535system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2893409994 # number of SCUpgradeReq MSHR miss cycles
1536system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1691000 # number of SCUpgradeFailReq MSHR miss cycles
1537system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1691000 # number of SCUpgradeFailReq MSHR miss cycles
1538system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 13686705498 # number of ReadExReq MSHR miss cycles
1539system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 13686705498 # number of ReadExReq MSHR miss cycles
1540system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 18806492000 # number of ReadCleanReq MSHR miss cycles
1541system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 18806492000 # number of ReadCleanReq MSHR miss cycles
1542system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 36387650483 # number of ReadSharedReq MSHR miss cycles
1543system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 36387650483 # number of ReadSharedReq MSHR miss cycles
1544system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 21673087497 # number of InvalidateReq MSHR miss cycles
1545system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 21673087497 # number of InvalidateReq MSHR miss cycles
1546system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 742635500 # number of demand (read+write) MSHR miss cycles
1547system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 518427500 # number of demand (read+write) MSHR miss cycles
1548system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 18806492000 # number of demand (read+write) MSHR miss cycles
1549system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 50074355981 # number of demand (read+write) MSHR miss cycles
1550system.cpu0.l2cache.demand_mshr_miss_latency::total 70141910981 # number of demand (read+write) MSHR miss cycles
1551system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 742635500 # number of overall MSHR miss cycles
1552system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 518427500 # number of overall MSHR miss cycles
1553system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 18806492000 # number of overall MSHR miss cycles
1554system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 50074355981 # number of overall MSHR miss cycles
1555system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 57180143123 # number of overall MSHR miss cycles
1556system.cpu0.l2cache.overall_mshr_miss_latency::total 127322054104 # number of overall MSHR miss cycles
1557system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1867460000 # number of ReadReq MSHR uncacheable cycles
1558system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5357476000 # number of ReadReq MSHR uncacheable cycles
1559system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7224936000 # number of ReadReq MSHR uncacheable cycles
1560system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1867460000 # number of overall MSHR uncacheable cycles
1561system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5357476000 # number of overall MSHR uncacheable cycles
1562system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7224936000 # number of overall MSHR uncacheable cycles
1563system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.039831 # mshr miss rate for ReadReq accesses
1564system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.061849 # mshr miss rate for ReadReq accesses
1565system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.045118 # mshr miss rate for ReadReq accesses
1566system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1567system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1568system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999876 # mshr miss rate for UpgradeReq accesses
1569system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999876 # mshr miss rate for UpgradeReq accesses
1570system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999973 # mshr miss rate for SCUpgradeReq accesses
1571system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999973 # mshr miss rate for SCUpgradeReq accesses
1572system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1573system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1574system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.213971 # mshr miss rate for ReadExReq accesses
1575system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.213971 # mshr miss rate for ReadExReq accesses
1576system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.098432 # mshr miss rate for ReadCleanReq accesses
1577system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098432 # mshr miss rate for ReadCleanReq accesses
1578system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.241664 # mshr miss rate for ReadSharedReq accesses
1579system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.241664 # mshr miss rate for ReadSharedReq accesses
1580system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.771029 # mshr miss rate for InvalidateReq accesses
1581system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.771029 # mshr miss rate for InvalidateReq accesses
1582system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.039831 # mshr miss rate for demand accesses
1583system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.061849 # mshr miss rate for demand accesses
1584system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.098432 # mshr miss rate for demand accesses
1585system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.235307 # mshr miss rate for demand accesses
1586system.cpu0.l2cache.demand_mshr_miss_rate::total 0.156576 # mshr miss rate for demand accesses
1587system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.039831 # mshr miss rate for overall accesses
1588system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.061849 # mshr miss rate for overall accesses
1589system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.098432 # mshr miss rate for overall accesses
1590system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.235307 # mshr miss rate for overall accesses
1591system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1592system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230440 # mshr miss rate for overall accesses
1593system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29695.917306 # average ReadReq mshr miss latency
1594system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 42244.744133 # average ReadReq mshr miss latency
1595system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33826.797210 # average ReadReq mshr miss latency
1596system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62512.865639 # average HardPFReq mshr miss latency
1597system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 62512.865639 # average HardPFReq mshr miss latency
1598system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18642.512439 # average UpgradeReq mshr miss latency
1599system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18642.512439 # average UpgradeReq mshr miss latency
1600system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15488.103172 # average SCUpgradeReq mshr miss latency
1601system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15488.103172 # average SCUpgradeReq mshr miss latency
1602system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 338200 # average SCUpgradeFailReq mshr miss latency
1603system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 338200 # average SCUpgradeFailReq mshr miss latency
1604system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 49922.328195 # average ReadExReq mshr miss latency
1605system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 49922.328195 # average ReadExReq mshr miss latency
1606system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31976.977722 # average ReadCleanReq mshr miss latency
1607system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31976.977722 # average ReadCleanReq mshr miss latency
1608system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35008.457299 # average ReadSharedReq mshr miss latency
1609system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35008.457299 # average ReadSharedReq mshr miss latency
1610system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 35079.711207 # average InvalidateReq mshr miss latency
1611system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 35079.711207 # average InvalidateReq mshr miss latency
1612system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29695.917306 # average overall mshr miss latency
1613system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 42244.744133 # average overall mshr miss latency
1614system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31976.977722 # average overall mshr miss latency
1615system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38121.219028 # average overall mshr miss latency
1616system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36174.979696 # average overall mshr miss latency
1617system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29695.917306 # average overall mshr miss latency
1618system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 42244.744133 # average overall mshr miss latency
1619system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31976.977722 # average overall mshr miss latency
1620system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38121.219028 # average overall mshr miss latency
1621system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62512.865639 # average overall mshr miss latency
1622system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44617.169730 # average overall mshr miss latency
1623system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986 # average ReadReq mshr uncacheable latency
1624system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180904.136417 # average ReadReq mshr uncacheable latency
1625system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 141921.426888 # average ReadReq mshr uncacheable latency
1626system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986 # average overall mshr uncacheable latency
1627system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 90336.154858 # average overall mshr uncacheable latency
1628system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89640.516632 # average overall mshr uncacheable latency
1629system.cpu0.toL2Bus.snoop_filter.tot_requests 25418604 # Total number of requests made to the snoop filter.
1630system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13061865 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1631system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1632system.cpu0.toL2Bus.snoop_filter.tot_snoops 690419 # Total number of snoops made to the snoop filter.
1633system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 690321 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1634system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 98 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1635system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
1636system.cpu0.toL2Bus.trans_dist::ReadReq 966476 # Transaction distribution
1637system.cpu0.toL2Bus.trans_dist::ReadResp 11336947 # Transaction distribution
1638system.cpu0.toL2Bus.trans_dist::WriteReq 29691 # Transaction distribution
1639system.cpu0.toL2Bus.trans_dist::WriteResp 29691 # Transaction distribution
1640system.cpu0.toL2Bus.trans_dist::WritebackDirty 5857040 # Transaction distribution
1641system.cpu0.toL2Bus.trans_dist::WritebackClean 8164049 # Transaction distribution
1642system.cpu0.toL2Bus.trans_dist::CleanEvict 1344034 # Transaction distribution
1643system.cpu0.toL2Bus.trans_dist::HardPFReq 1151380 # Transaction distribution
1644system.cpu0.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution
1645system.cpu0.toL2Bus.trans_dist::UpgradeReq 469212 # Transaction distribution
1646system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 335795 # Transaction distribution
1647system.cpu0.toL2Bus.trans_dist::UpgradeResp 509398 # Transaction distribution
1648system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 66 # Transaction distribution
1649system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 113 # Transaction distribution
1650system.cpu0.toL2Bus.trans_dist::ReadExReq 1315239 # Transaction distribution
1651system.cpu0.toL2Bus.trans_dist::ReadExResp 1289150 # Transaction distribution
1652system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5975008 # Transaction distribution
1653system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5298799 # Transaction distribution
1654system.cpu0.toL2Bus.trans_dist::InvalidateReq 872203 # Transaction distribution
1655system.cpu0.toL2Bus.trans_dist::InvalidateResp 802449 # Transaction distribution
1656system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17966980 # Packet count per connected master and slave (bytes)
1657system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20229549 # Packet count per connected master and slave (bytes)
1658system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 416579 # Packet count per connected master and slave (bytes)
1659system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1325266 # Packet count per connected master and slave (bytes)
1660system.cpu0.toL2Bus.pkt_count::total 39938374 # Packet count per connected master and slave (bytes)
1661system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 765101392 # Cumulative packet size per connected master and slave (bytes)
1662system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 766341777 # Cumulative packet size per connected master and slave (bytes)
1663system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1587352 # Cumulative packet size per connected master and slave (bytes)
1664system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5022880 # Cumulative packet size per connected master and slave (bytes)
1665system.cpu0.toL2Bus.pkt_size::total 1538053401 # Cumulative packet size per connected master and slave (bytes)
1666system.cpu0.toL2Bus.snoops 5977120 # Total snoops (count)
1667system.cpu0.toL2Bus.snoopTraffic 119917960 # Total snoop traffic (bytes)
1668system.cpu0.toL2Bus.snoop_fanout::samples 19518051 # Request fanout histogram
1669system.cpu0.toL2Bus.snoop_fanout::mean 0.053731 # Request fanout histogram
1670system.cpu0.toL2Bus.snoop_fanout::stdev 0.225509 # Request fanout histogram
1671system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1672system.cpu0.toL2Bus.snoop_fanout::0 18469421 94.63% 94.63% # Request fanout histogram
1673system.cpu0.toL2Bus.snoop_fanout::1 1048532 5.37% 100.00% # Request fanout histogram
1674system.cpu0.toL2Bus.snoop_fanout::2 98 0.00% 100.00% # Request fanout histogram
1675system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1676system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1677system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1678system.cpu0.toL2Bus.snoop_fanout::total 19518051 # Request fanout histogram
1679system.cpu0.toL2Bus.reqLayer0.occupancy 25305808947 # Layer occupancy (ticks)
1680system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1681system.cpu0.toL2Bus.snoopLayer0.occupancy 186983903 # Layer occupancy (ticks)
1682system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1683system.cpu0.toL2Bus.respLayer0.occupancy 8989974042 # Layer occupancy (ticks)
1684system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1685system.cpu0.toL2Bus.respLayer1.occupancy 9049403091 # Layer occupancy (ticks)
1686system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1687system.cpu0.toL2Bus.respLayer2.occupancy 218640527 # Layer occupancy (ticks)
1688system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1689system.cpu0.toL2Bus.respLayer3.occupancy 698295209 # Layer occupancy (ticks)
1690system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1691system.cpu1.branchPred.lookups 130931248 # Number of BP lookups
1692system.cpu1.branchPred.condPredicted 87112041 # Number of conditional branches predicted
1693system.cpu1.branchPred.condIncorrect 6567659 # Number of conditional branches incorrect
1694system.cpu1.branchPred.BTBLookups 91792654 # Number of BTB lookups
1695system.cpu1.branchPred.BTBHits 56129151 # Number of BTB hits
1696system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1697system.cpu1.branchPred.BTBHitPct 61.147759 # BTB Hit Percentage
1698system.cpu1.branchPred.usedRAS 17311793 # Number of times the RAS was used to get a target.
1699system.cpu1.branchPred.RASInCorrect 174850 # Number of incorrect RAS predictions.
1700system.cpu1.branchPred.indirectLookups 4346649 # Number of indirect predictor lookups.
1701system.cpu1.branchPred.indirectHits 2655837 # Number of indirect target hits.
1702system.cpu1.branchPred.indirectMisses 1690812 # Number of indirect misses.
1703system.cpu1.branchPredindirectMispredicted 417178 # Number of mispredicted indirect branches.
1704system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
1705system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1706system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1707system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1708system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1709system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1710system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1711system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1712system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

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1726system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1727system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1728system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1729system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1730system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1731system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1732system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1733system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1734system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
1735system.cpu1.dtb.walker.walks 551219 # Table walker walks requested
1736system.cpu1.dtb.walker.walksLong 551219 # Table walker walks initiated with long descriptors
1737system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11436 # Level at which table walker walks with long descriptors terminate
1738system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86181 # Level at which table walker walks with long descriptors terminate
1739system.cpu1.dtb.walker.walksSquashedBefore 255688 # Table walks squashed before starting
1740system.cpu1.dtb.walker.walkWaitTime::samples 295531 # Table walker wait (enqueue to first request) latency
1741system.cpu1.dtb.walker.walkWaitTime::mean 2259.422869 # Table walker wait (enqueue to first request) latency
1742system.cpu1.dtb.walker.walkWaitTime::stdev 13315.556253 # Table walker wait (enqueue to first request) latency
1743system.cpu1.dtb.walker.walkWaitTime::0-65535 293454 99.30% 99.30% # Table walker wait (enqueue to first request) latency
1744system.cpu1.dtb.walker.walkWaitTime::65536-131071 1395 0.47% 99.77% # Table walker wait (enqueue to first request) latency
1745system.cpu1.dtb.walker.walkWaitTime::131072-196607 424 0.14% 99.91% # Table walker wait (enqueue to first request) latency
1746system.cpu1.dtb.walker.walkWaitTime::196608-262143 158 0.05% 99.97% # Table walker wait (enqueue to first request) latency
1747system.cpu1.dtb.walker.walkWaitTime::262144-327679 50 0.02% 99.98% # Table walker wait (enqueue to first request) latency
1748system.cpu1.dtb.walker.walkWaitTime::327680-393215 38 0.01% 100.00% # Table walker wait (enqueue to first request) latency
1749system.cpu1.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1750system.cpu1.dtb.walker.walkWaitTime::458752-524287 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1751system.cpu1.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1752system.cpu1.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1753system.cpu1.dtb.walker.walkWaitTime::total 295531 # Table walker wait (enqueue to first request) latency
1754system.cpu1.dtb.walker.walkCompletionTime::samples 283173 # Table walker service (enqueue to completion) latency
1755system.cpu1.dtb.walker.walkCompletionTime::mean 21265.600887 # Table walker service (enqueue to completion) latency
1756system.cpu1.dtb.walker.walkCompletionTime::gmean 18470.492322 # Table walker service (enqueue to completion) latency
1757system.cpu1.dtb.walker.walkCompletionTime::stdev 14814.339876 # Table walker service (enqueue to completion) latency
1758system.cpu1.dtb.walker.walkCompletionTime::0-65535 281324 99.35% 99.35% # Table walker service (enqueue to completion) latency
1759system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1404 0.50% 99.84% # Table walker service (enqueue to completion) latency
1760system.cpu1.dtb.walker.walkCompletionTime::131072-196607 195 0.07% 99.91% # Table walker service (enqueue to completion) latency
1761system.cpu1.dtb.walker.walkCompletionTime::196608-262143 146 0.05% 99.96% # Table walker service (enqueue to completion) latency
1762system.cpu1.dtb.walker.walkCompletionTime::262144-327679 42 0.01% 99.98% # Table walker service (enqueue to completion) latency
1763system.cpu1.dtb.walker.walkCompletionTime::327680-393215 27 0.01% 99.99% # Table walker service (enqueue to completion) latency
1764system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.00% 99.99% # Table walker service (enqueue to completion) latency
1765system.cpu1.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
1766system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
1767system.cpu1.dtb.walker.walkCompletionTime::589824-655359 13 0.00% 100.00% # Table walker service (enqueue to completion) latency
1768system.cpu1.dtb.walker.walkCompletionTime::655360-720895 9 0.00% 100.00% # Table walker service (enqueue to completion) latency
1769system.cpu1.dtb.walker.walkCompletionTime::total 283173 # Table walker service (enqueue to completion) latency
1770system.cpu1.dtb.walker.walksPending::samples 475307081088 # Table walker pending requests distribution
1771system.cpu1.dtb.walker.walksPending::mean 0.614132 # Table walker pending requests distribution
1772system.cpu1.dtb.walker.walksPending::stdev 0.549956 # Table walker pending requests distribution
1773system.cpu1.dtb.walker.walksPending::0-1 474122952588 99.75% 99.75% # Table walker pending requests distribution
1774system.cpu1.dtb.walker.walksPending::2-3 603814500 0.13% 99.88% # Table walker pending requests distribution
1775system.cpu1.dtb.walker.walksPending::4-5 247441500 0.05% 99.93% # Table walker pending requests distribution
1776system.cpu1.dtb.walker.walksPending::6-7 130616500 0.03% 99.96% # Table walker pending requests distribution
1777system.cpu1.dtb.walker.walksPending::8-9 93327500 0.02% 99.98% # Table walker pending requests distribution
1778system.cpu1.dtb.walker.walksPending::10-11 62495500 0.01% 99.99% # Table walker pending requests distribution
1779system.cpu1.dtb.walker.walksPending::12-13 19627500 0.00% 99.99% # Table walker pending requests distribution
1780system.cpu1.dtb.walker.walksPending::14-15 26354000 0.01% 100.00% # Table walker pending requests distribution
1781system.cpu1.dtb.walker.walksPending::16-17 445000 0.00% 100.00% # Table walker pending requests distribution
1782system.cpu1.dtb.walker.walksPending::18-19 6500 0.00% 100.00% # Table walker pending requests distribution
1783system.cpu1.dtb.walker.walksPending::total 475307081088 # Table walker pending requests distribution
1784system.cpu1.dtb.walker.walkPageSizes::4K 86181 88.28% 88.28% # Table walker page sizes translated
1785system.cpu1.dtb.walker.walkPageSizes::2M 11436 11.72% 100.00% # Table walker page sizes translated
1786system.cpu1.dtb.walker.walkPageSizes::total 97617 # Table walker page sizes translated
1787system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 551219 # Table walker requests started/completed, data/inst
1788system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1789system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 551219 # Table walker requests started/completed, data/inst
1790system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97617 # Table walker requests started/completed, data/inst
1791system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1792system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97617 # Table walker requests started/completed, data/inst
1793system.cpu1.dtb.walker.walkRequestOrigin::total 648836 # Table walker requests started/completed, data/inst
1794system.cpu1.dtb.inst_hits 0 # ITB inst hits
1795system.cpu1.dtb.inst_misses 0 # ITB inst misses
1796system.cpu1.dtb.read_hits 95947338 # DTB read hits
1797system.cpu1.dtb.read_misses 376138 # DTB read misses
1798system.cpu1.dtb.write_hits 79464123 # DTB write hits
1799system.cpu1.dtb.write_misses 175081 # DTB write misses
1800system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1801system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1802system.cpu1.dtb.flush_tlb_mva_asid 44658 # Number of times TLB was flushed by MVA & ASID
1803system.cpu1.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
1804system.cpu1.dtb.flush_entries 35142 # Number of entries that have been flushed from TLB
1805system.cpu1.dtb.align_faults 372 # Number of TLB faults due to alignment restrictions
1806system.cpu1.dtb.prefetch_faults 6075 # Number of TLB faults due to prefetch
1807system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1808system.cpu1.dtb.perms_faults 39563 # Number of TLB faults due to permissions restrictions
1809system.cpu1.dtb.read_accesses 96323476 # DTB read accesses
1810system.cpu1.dtb.write_accesses 79639204 # DTB write accesses
1811system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1812system.cpu1.dtb.hits 175411461 # DTB hits
1813system.cpu1.dtb.misses 551219 # DTB misses
1814system.cpu1.dtb.accesses 175962680 # DTB accesses
1815system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
1816system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1817system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1818system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1819system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1820system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1821system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1822system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1823system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1837system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1838system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1839system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1840system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1841system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1842system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1843system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1844system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1845system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
1846system.cpu1.itb.walker.walks 82567 # Table walker walks requested
1847system.cpu1.itb.walker.walksLong 82567 # Table walker walks initiated with long descriptors
1848system.cpu1.itb.walker.walksLongTerminationLevel::Level2 985 # Level at which table walker walks with long descriptors terminate
1849system.cpu1.itb.walker.walksLongTerminationLevel::Level3 60088 # Level at which table walker walks with long descriptors terminate
1850system.cpu1.itb.walker.walksSquashedBefore 9957 # Table walks squashed before starting
1851system.cpu1.itb.walker.walkWaitTime::samples 72610 # Table walker wait (enqueue to first request) latency
1852system.cpu1.itb.walker.walkWaitTime::mean 937.467291 # Table walker wait (enqueue to first request) latency
1853system.cpu1.itb.walker.walkWaitTime::stdev 7808.036609 # Table walker wait (enqueue to first request) latency
1854system.cpu1.itb.walker.walkWaitTime::0-65535 72461 99.79% 99.79% # Table walker wait (enqueue to first request) latency
1855system.cpu1.itb.walker.walkWaitTime::65536-131071 121 0.17% 99.96% # Table walker wait (enqueue to first request) latency
1856system.cpu1.itb.walker.walkWaitTime::131072-196607 15 0.02% 99.98% # Table walker wait (enqueue to first request) latency
1857system.cpu1.itb.walker.walkWaitTime::196608-262143 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency
1858system.cpu1.itb.walker.walkWaitTime::262144-327679 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency
1859system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1860system.cpu1.itb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1861system.cpu1.itb.walker.walkWaitTime::total 72610 # Table walker wait (enqueue to first request) latency
1862system.cpu1.itb.walker.walkCompletionTime::samples 71030 # Table walker service (enqueue to completion) latency
1863system.cpu1.itb.walker.walkCompletionTime::mean 24890.468816 # Table walker service (enqueue to completion) latency
1864system.cpu1.itb.walker.walkCompletionTime::gmean 22675.930059 # Table walker service (enqueue to completion) latency
1865system.cpu1.itb.walker.walkCompletionTime::stdev 19295.215598 # Table walker service (enqueue to completion) latency
1866system.cpu1.itb.walker.walkCompletionTime::0-65535 70173 98.79% 98.79% # Table walker service (enqueue to completion) latency
1867system.cpu1.itb.walker.walkCompletionTime::65536-131071 554 0.78% 99.57% # Table walker service (enqueue to completion) latency
1868system.cpu1.itb.walker.walkCompletionTime::131072-196607 204 0.29% 99.86% # Table walker service (enqueue to completion) latency
1869system.cpu1.itb.walker.walkCompletionTime::196608-262143 35 0.05% 99.91% # Table walker service (enqueue to completion) latency
1870system.cpu1.itb.walker.walkCompletionTime::262144-327679 20 0.03% 99.94% # Table walker service (enqueue to completion) latency
1871system.cpu1.itb.walker.walkCompletionTime::327680-393215 8 0.01% 99.95% # Table walker service (enqueue to completion) latency
1872system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 99.96% # Table walker service (enqueue to completion) latency
1873system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.96% # Table walker service (enqueue to completion) latency
1874system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.96% # Table walker service (enqueue to completion) latency
1875system.cpu1.itb.walker.walkCompletionTime::589824-655359 25 0.04% 100.00% # Table walker service (enqueue to completion) latency
1876system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1877system.cpu1.itb.walker.walkCompletionTime::total 71030 # Table walker service (enqueue to completion) latency
1878system.cpu1.itb.walker.walksPending::samples 397994478260 # Table walker pending requests distribution
1879system.cpu1.itb.walker.walksPending::mean 0.871343 # Table walker pending requests distribution
1880system.cpu1.itb.walker.walksPending::stdev 0.334985 # Table walker pending requests distribution
1881system.cpu1.itb.walker.walksPending::0 51225264788 12.87% 12.87% # Table walker pending requests distribution
1882system.cpu1.itb.walker.walksPending::1 346750110472 87.12% 100.00% # Table walker pending requests distribution
1883system.cpu1.itb.walker.walksPending::2 17741500 0.00% 100.00% # Table walker pending requests distribution
1884system.cpu1.itb.walker.walksPending::3 1276000 0.00% 100.00% # Table walker pending requests distribution
1885system.cpu1.itb.walker.walksPending::4 85500 0.00% 100.00% # Table walker pending requests distribution
1886system.cpu1.itb.walker.walksPending::total 397994478260 # Table walker pending requests distribution
1887system.cpu1.itb.walker.walkPageSizes::4K 60088 98.39% 98.39% # Table walker page sizes translated
1888system.cpu1.itb.walker.walkPageSizes::2M 985 1.61% 100.00% # Table walker page sizes translated
1889system.cpu1.itb.walker.walkPageSizes::total 61073 # Table walker page sizes translated
1890system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1891system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 82567 # Table walker requests started/completed, data/inst
1892system.cpu1.itb.walker.walkRequestOrigin_Requested::total 82567 # Table walker requests started/completed, data/inst
1893system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1894system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61073 # Table walker requests started/completed, data/inst
1895system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61073 # Table walker requests started/completed, data/inst
1896system.cpu1.itb.walker.walkRequestOrigin::total 143640 # Table walker requests started/completed, data/inst
1897system.cpu1.itb.inst_hits 204871540 # ITB inst hits
1898system.cpu1.itb.inst_misses 82567 # ITB inst misses
1899system.cpu1.itb.read_hits 0 # DTB read hits
1900system.cpu1.itb.read_misses 0 # DTB read misses
1901system.cpu1.itb.write_hits 0 # DTB write hits
1902system.cpu1.itb.write_misses 0 # DTB write misses
1903system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1904system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1905system.cpu1.itb.flush_tlb_mva_asid 44658 # Number of times TLB was flushed by MVA & ASID
1906system.cpu1.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID
1907system.cpu1.itb.flush_entries 24862 # Number of entries that have been flushed from TLB
1908system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1909system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1910system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1911system.cpu1.itb.perms_faults 205327 # Number of TLB faults due to permissions restrictions
1912system.cpu1.itb.read_accesses 0 # DTB read accesses
1913system.cpu1.itb.write_accesses 0 # DTB write accesses
1914system.cpu1.itb.inst_accesses 204954107 # ITB inst accesses
1915system.cpu1.itb.hits 204871540 # DTB hits
1916system.cpu1.itb.misses 82567 # DTB misses
1917system.cpu1.itb.accesses 204954107 # DTB accesses
1918system.cpu1.numPwrStateTransitions 10338 # Number of power state transitions
1919system.cpu1.pwrStateClkGateDist::samples 5169 # Distribution of time spent in the clock gated state
1920system.cpu1.pwrStateClkGateDist::mean 9100042413.076223 # Distribution of time spent in the clock gated state
1921system.cpu1.pwrStateClkGateDist::stdev 142913287882.442078 # Distribution of time spent in the clock gated state
1922system.cpu1.pwrStateClkGateDist::underflows 3563 68.93% 68.93% # Distribution of time spent in the clock gated state
1923system.cpu1.pwrStateClkGateDist::1000-5e+10 1580 30.57% 99.50% # Distribution of time spent in the clock gated state
1924system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.04% 99.54% # Distribution of time spent in the clock gated state
1925system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 5 0.10% 99.63% # Distribution of time spent in the clock gated state
1926system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.04% 99.67% # Distribution of time spent in the clock gated state
1927system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.69% # Distribution of time spent in the clock gated state
1928system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state
1929system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state
1930system.cpu1.pwrStateClkGateDist::overflows 14 0.27% 100.00% # Distribution of time spent in the clock gated state
1931system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
1932system.cpu1.pwrStateClkGateDist::max_value 7390880676264 # Distribution of time spent in the clock gated state
1933system.cpu1.pwrStateClkGateDist::total 5169 # Distribution of time spent in the clock gated state
1934system.cpu1.pwrStateResidencyTicks::ON 346821221809 # Cumulative time (in ticks) in various power states
1935system.cpu1.pwrStateResidencyTicks::CLK_GATED 47038119233191 # Cumulative time (in ticks) in various power states
1936system.cpu1.numCycles 693644050 # number of cpu cycles simulated
1937system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1938system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1939system.cpu1.fetch.icacheStallCycles 87527745 # Number of cycles fetch is stalled on an Icache miss
1940system.cpu1.fetch.Insts 578391241 # Number of instructions fetch has processed
1941system.cpu1.fetch.Branches 130931248 # Number of branches that fetch encountered
1942system.cpu1.fetch.predictedBranches 76096781 # Number of branches that fetch has predicted taken
1943system.cpu1.fetch.Cycles 569305331 # Number of cycles fetch has run and was not squashing or blocked
1944system.cpu1.fetch.SquashCycles 14062296 # Number of cycles fetch has spent squashing
1945system.cpu1.fetch.TlbCycles 1768387 # Number of cycles fetch has spent waiting for tlb
1946system.cpu1.fetch.MiscStallCycles 291884 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1947system.cpu1.fetch.PendingTrapStallCycles 5735168 # Number of stall cycles due to pending traps
1948system.cpu1.fetch.PendingQuiesceStallCycles 727906 # Number of stall cycles due to pending quiesce instructions
1949system.cpu1.fetch.IcacheWaitRetryStallCycles 800824 # Number of stall cycles due to full MSHR
1950system.cpu1.fetch.CacheLines 204645173 # Number of cache lines fetched
1951system.cpu1.fetch.IcacheSquashes 1664411 # Number of outstanding Icache misses that were squashed
1952system.cpu1.fetch.ItlbSquashes 27214 # Number of outstanding ITLB misses that were squashed
1953system.cpu1.fetch.rateDist::samples 673188393 # Number of instructions fetched each cycle (Total)
1954system.cpu1.fetch.rateDist::mean 1.008077 # Number of instructions fetched each cycle (Total)
1955system.cpu1.fetch.rateDist::stdev 1.227099 # Number of instructions fetched each cycle (Total)
1956system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1957system.cpu1.fetch.rateDist::0 348457754 51.76% 51.76% # Number of instructions fetched each cycle (Total)
1958system.cpu1.fetch.rateDist::1 126514971 18.79% 70.56% # Number of instructions fetched each cycle (Total)
1959system.cpu1.fetch.rateDist::2 42536092 6.32% 76.87% # Number of instructions fetched each cycle (Total)
1960system.cpu1.fetch.rateDist::3 155679576 23.13% 100.00% # Number of instructions fetched each cycle (Total)
1961system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1962system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1963system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
1964system.cpu1.fetch.rateDist::total 673188393 # Number of instructions fetched each cycle (Total)
1965system.cpu1.fetch.branchRate 0.188759 # Number of branch fetches per cycle
1966system.cpu1.fetch.rate 0.833844 # Number of inst fetches per cycle
1967system.cpu1.decode.IdleCycles 102787429 # Number of cycles decode is idle
1968system.cpu1.decode.BlockedCycles 312284706 # Number of cycles decode is blocked
1969system.cpu1.decode.RunCycles 218180532 # Number of cycles decode is running
1970system.cpu1.decode.UnblockCycles 34930241 # Number of cycles decode is unblocking
1971system.cpu1.decode.SquashCycles 5005485 # Number of cycles decode is squashing
1972system.cpu1.decode.BranchResolved 18306368 # Number of times decode resolved a branch
1973system.cpu1.decode.BranchMispred 2064498 # Number of times decode detected a branch misprediction
1974system.cpu1.decode.DecodedInsts 600925596 # Number of instructions handled by decode
1975system.cpu1.decode.SquashedInsts 22793962 # Number of squashed instructions handled by decode
1976system.cpu1.rename.SquashCycles 5005485 # Number of cycles rename is squashing
1977system.cpu1.rename.IdleCycles 136395689 # Number of cycles rename is idle
1978system.cpu1.rename.BlockCycles 44912882 # Number of cycles rename is blocking
1979system.cpu1.rename.serializeStallCycles 210797905 # count of cycles rename stalled for serializing inst
1980system.cpu1.rename.RunCycles 219085305 # Number of cycles rename is running
1981system.cpu1.rename.UnblockCycles 56991127 # Number of cycles rename is unblocking
1982system.cpu1.rename.RenamedInsts 584399745 # Number of instructions processed by rename
1983system.cpu1.rename.SquashedInsts 6001663 # Number of squashed instructions processed by rename
1984system.cpu1.rename.ROBFullEvents 9489847 # Number of times rename has blocked due to ROB full
1985system.cpu1.rename.IQFullEvents 242679 # Number of times rename has blocked due to IQ full
1986system.cpu1.rename.LQFullEvents 273258 # Number of times rename has blocked due to LQ full
1987system.cpu1.rename.SQFullEvents 24369803 # Number of times rename has blocked due to SQ full
1988system.cpu1.rename.FullRegisterEvents 10662 # Number of times there has been no free registers
1989system.cpu1.rename.RenamedOperands 555653486 # Number of destination operands rename has renamed
1990system.cpu1.rename.RenameLookups 898470064 # Number of register rename lookups that rename has made
1991system.cpu1.rename.int_rename_lookups 689649249 # Number of integer rename lookups
1992system.cpu1.rename.fp_rename_lookups 841085 # Number of floating rename lookups
1993system.cpu1.rename.CommittedMaps 500004101 # Number of HB maps that are committed
1994system.cpu1.rename.UndoneMaps 55649379 # Number of HB maps that are undone due to squashing
1995system.cpu1.rename.serializingInsts 14907079 # count of serializing insts renamed
1996system.cpu1.rename.tempSerializingInsts 13060204 # count of temporary serializing insts renamed
1997system.cpu1.rename.skidInsts 70305418 # count of insts added to the skid buffer
1998system.cpu1.memDep0.insertedLoads 96437745 # Number of loads inserted to the mem dependence unit.
1999system.cpu1.memDep0.insertedStores 82644936 # Number of stores inserted to the mem dependence unit.
2000system.cpu1.memDep0.conflictingLoads 8695524 # Number of conflicting loads.
2001system.cpu1.memDep0.conflictingStores 7557089 # Number of conflicting stores.
2002system.cpu1.iq.iqInstsAdded 562795340 # Number of instructions added to the IQ (excludes non-spec)
2003system.cpu1.iq.iqNonSpecInstsAdded 15022202 # Number of non-speculative instructions added to the IQ
2004system.cpu1.iq.iqInstsIssued 566786483 # Number of instructions issued
2005system.cpu1.iq.iqSquashedInstsIssued 2618124 # Number of squashed instructions issued
2006system.cpu1.iq.iqSquashedInstsExamined 52408988 # Number of squashed instructions iterated over during squash; mainly for profiling
2007system.cpu1.iq.iqSquashedOperandsExamined 33720273 # Number of squashed operands that are examined and possibly removed from graph
2008system.cpu1.iq.iqSquashedNonSpecRemoved 259964 # Number of squashed non-spec instructions that were removed
2009system.cpu1.iq.issued_per_cycle::samples 673188393 # Number of insts issued each cycle
2010system.cpu1.iq.issued_per_cycle::mean 0.841943 # Number of insts issued each cycle
2011system.cpu1.iq.issued_per_cycle::stdev 1.073212 # Number of insts issued each cycle
2012system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
2013system.cpu1.iq.issued_per_cycle::0 363862102 54.05% 54.05% # Number of insts issued each cycle
2014system.cpu1.iq.issued_per_cycle::1 129787759 19.28% 73.33% # Number of insts issued each cycle
2015system.cpu1.iq.issued_per_cycle::2 109122281 16.21% 89.54% # Number of insts issued each cycle
2016system.cpu1.iq.issued_per_cycle::3 62914886 9.35% 98.89% # Number of insts issued each cycle
2017system.cpu1.iq.issued_per_cycle::4 7497321 1.11% 100.00% # Number of insts issued each cycle
2018system.cpu1.iq.issued_per_cycle::5 4044 0.00% 100.00% # Number of insts issued each cycle
2019system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
2020system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
2021system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
2022system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
2023system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
2024system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
2025system.cpu1.iq.issued_per_cycle::total 673188393 # Number of insts issued each cycle
2026system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
2027system.cpu1.iq.fu_full::IntAlu 57388953 44.23% 44.23% # attempts to use FU when none available
2028system.cpu1.iq.fu_full::IntMult 51651 0.04% 44.27% # attempts to use FU when none available
2029system.cpu1.iq.fu_full::IntDiv 16856 0.01% 44.29% # attempts to use FU when none available
2030system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.29% # attempts to use FU when none available
2031system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.29% # attempts to use FU when none available
2032system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.29% # attempts to use FU when none available
2033system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.29% # attempts to use FU when none available
2034system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 44.29% # attempts to use FU when none available
2035system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.29% # attempts to use FU when none available
2036system.cpu1.iq.fu_full::FloatMisc 103 0.00% 44.29% # attempts to use FU when none available
2037system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.29% # attempts to use FU when none available
2038system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.29% # attempts to use FU when none available
2039system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.29% # attempts to use FU when none available
2040system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.29% # attempts to use FU when none available
2041system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.29% # attempts to use FU when none available
2042system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.29% # attempts to use FU when none available
2043system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.29% # attempts to use FU when none available
2044system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.29% # attempts to use FU when none available
2045system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.29% # attempts to use FU when none available
2046system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.29% # attempts to use FU when none available
2047system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.29% # attempts to use FU when none available
2048system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.29% # attempts to use FU when none available
2049system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.29% # attempts to use FU when none available
2050system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.29% # attempts to use FU when none available
2051system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.29% # attempts to use FU when none available
2052system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.29% # attempts to use FU when none available
2053system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.29% # attempts to use FU when none available
2054system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.29% # attempts to use FU when none available
2055system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.29% # attempts to use FU when none available
2056system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.29% # attempts to use FU when none available
2057system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.29% # attempts to use FU when none available
2058system.cpu1.iq.fu_full::MemRead 34250281 26.40% 70.69% # attempts to use FU when none available
2059system.cpu1.iq.fu_full::MemWrite 37595364 28.98% 99.66% # attempts to use FU when none available
2060system.cpu1.iq.fu_full::FloatMemRead 47943 0.04% 99.70% # attempts to use FU when none available
2061system.cpu1.iq.fu_full::FloatMemWrite 388183 0.30% 100.00% # attempts to use FU when none available
2062system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
2063system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2064system.cpu1.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued
2065system.cpu1.iq.FU_type_0::IntAlu 385773007 68.06% 68.06% # Type of FU issued
2066system.cpu1.iq.FU_type_0::IntMult 1187343 0.21% 68.27% # Type of FU issued
2067system.cpu1.iq.FU_type_0::IntDiv 69773 0.01% 68.28% # Type of FU issued
2068system.cpu1.iq.FU_type_0::FloatAdd 8 0.00% 68.28% # Type of FU issued
2069system.cpu1.iq.FU_type_0::FloatCmp 13 0.00% 68.29% # Type of FU issued
2070system.cpu1.iq.FU_type_0::FloatCvt 27 0.00% 68.29% # Type of FU issued
2071system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.29% # Type of FU issued
2072system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 68.29% # Type of FU issued
2073system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.29% # Type of FU issued
2074system.cpu1.iq.FU_type_0::FloatMisc 84205 0.01% 68.30% # Type of FU issued
2075system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.30% # Type of FU issued
2076system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.30% # Type of FU issued
2077system.cpu1.iq.FU_type_0::SimdAddAcc 2 0.00% 68.30% # Type of FU issued
2078system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.30% # Type of FU issued
2079system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.30% # Type of FU issued
2080system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.30% # Type of FU issued
2081system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.30% # Type of FU issued
2082system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.30% # Type of FU issued
2083system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.30% # Type of FU issued
2084system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.30% # Type of FU issued
2085system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.30% # Type of FU issued
2086system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.30% # Type of FU issued
2087system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.30% # Type of FU issued
2088system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.30% # Type of FU issued
2089system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.30% # Type of FU issued
2090system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.30% # Type of FU issued
2091system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.30% # Type of FU issued
2092system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.30% # Type of FU issued
2093system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.30% # Type of FU issued
2094system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.30% # Type of FU issued
2095system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.30% # Type of FU issued
2096system.cpu1.iq.FU_type_0::MemRead 98926523 17.45% 85.75% # Type of FU issued
2097system.cpu1.iq.FU_type_0::MemWrite 80304665 14.17% 99.92% # Type of FU issued
2098system.cpu1.iq.FU_type_0::FloatMemRead 64060 0.01% 99.93% # Type of FU issued
2099system.cpu1.iq.FU_type_0::FloatMemWrite 376846 0.07% 100.00% # Type of FU issued
2100system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
2101system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2102system.cpu1.iq.FU_type_0::total 566786483 # Type of FU issued
2103system.cpu1.iq.rate 0.817114 # Inst issue rate
2104system.cpu1.iq.fu_busy_cnt 129739334 # FU busy when requested
2105system.cpu1.iq.fu_busy_rate 0.228903 # FU busy rate (busy events/executed inst)
2106system.cpu1.iq.int_inst_queue_reads 1937625833 # Number of integer instruction queue reads
2107system.cpu1.iq.int_inst_queue_writes 629808815 # Number of integer instruction queue writes
2108system.cpu1.iq.int_inst_queue_wakeup_accesses 550243700 # Number of integer instruction queue wakeup accesses
2109system.cpu1.iq.fp_inst_queue_reads 1492982 # Number of floating instruction queue reads
2110system.cpu1.iq.fp_inst_queue_writes 556682 # Number of floating instruction queue writes
2111system.cpu1.iq.fp_inst_queue_wakeup_accesses 518492 # Number of floating instruction queue wakeup accesses
2112system.cpu1.iq.int_alu_accesses 695564416 # Number of integer alu accesses
2113system.cpu1.iq.fp_alu_accesses 961390 # Number of floating point alu accesses
2114system.cpu1.iew.lsq.thread0.forwLoads 2525668 # Number of loads that had data forwarded from stores
2115system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2116system.cpu1.iew.lsq.thread0.squashedLoads 12072145 # Number of loads squashed
2117system.cpu1.iew.lsq.thread0.ignoredResponses 16264 # Number of memory responses ignored because the instruction is squashed
2118system.cpu1.iew.lsq.thread0.memOrderViolation 139965 # Number of memory ordering violations
2119system.cpu1.iew.lsq.thread0.squashedStores 5400546 # Number of stores squashed
2120system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2121system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2122system.cpu1.iew.lsq.thread0.rescheduledLoads 2506634 # Number of loads that were rescheduled
2123system.cpu1.iew.lsq.thread0.cacheBlocked 3911021 # Number of times an access to memory failed due to the cache being blocked
2124system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2125system.cpu1.iew.iewSquashCycles 5005485 # Number of cycles IEW is squashing
2126system.cpu1.iew.iewBlockCycles 6180671 # Number of cycles IEW is blocking
2127system.cpu1.iew.iewUnblockCycles 1541266 # Number of cycles IEW is unblocking
2128system.cpu1.iew.iewDispatchedInsts 577948873 # Number of instructions dispatched to IQ
2129system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2130system.cpu1.iew.iewDispLoadInsts 96437745 # Number of dispatched load instructions
2131system.cpu1.iew.iewDispStoreInsts 82644936 # Number of dispatched store instructions
2132system.cpu1.iew.iewDispNonSpecInsts 12856669 # Number of dispatched non-speculative instructions
2133system.cpu1.iew.iewIQFullEvents 62955 # Number of times the IQ has become full, causing a stall
2134system.cpu1.iew.iewLSQFullEvents 1418771 # Number of times the LSQ has become full, causing a stall
2135system.cpu1.iew.memOrderViolationEvents 139965 # Number of memory order violations
2136system.cpu1.iew.predictedTakenIncorrect 1860771 # Number of branches that were predicted taken incorrectly
2137system.cpu1.iew.predictedNotTakenIncorrect 3017279 # Number of branches that were predicted not taken incorrectly
2138system.cpu1.iew.branchMispredicts 4878050 # Number of branch mispredicts detected at execute
2139system.cpu1.iew.iewExecutedInsts 559031023 # Number of executed instructions
2140system.cpu1.iew.iewExecLoadInsts 95939165 # Number of load instructions executed
2141system.cpu1.iew.iewExecSquashedInsts 7216233 # Number of squashed instructions skipped in execute
2142system.cpu1.iew.exec_swp 0 # number of swp insts executed
2143system.cpu1.iew.exec_nop 131331 # number of nop insts executed
2144system.cpu1.iew.exec_refs 175402489 # number of memory reference insts executed
2145system.cpu1.iew.exec_branches 104887487 # Number of branches executed
2146system.cpu1.iew.exec_stores 79463324 # Number of stores executed
2147system.cpu1.iew.exec_rate 0.805934 # Inst execution rate
2148system.cpu1.iew.wb_sent 551451357 # cumulative count of insts sent to commit
2149system.cpu1.iew.wb_count 550762192 # cumulative count of insts written-back
2150system.cpu1.iew.wb_producers 266030186 # num instructions producing a value
2151system.cpu1.iew.wb_consumers 436524752 # num instructions consuming a value
2152system.cpu1.iew.wb_rate 0.794013 # insts written-back per cycle
2153system.cpu1.iew.wb_fanout 0.609427 # average fanout of values written-back
2154system.cpu1.commit.commitSquashedInsts 45696838 # The number of squashed insts skipped by commit
2155system.cpu1.commit.commitNonSpecStalls 14762238 # The number of times commit has been forced to stall to communicate backwards
2156system.cpu1.commit.branchMispredicts 4541996 # The number of times a branch was mispredicted
2157system.cpu1.commit.committed_per_cycle::samples 664504904 # Number of insts commited each cycle
2158system.cpu1.commit.committed_per_cycle::mean 0.790677 # Number of insts commited each cycle
2159system.cpu1.commit.committed_per_cycle::stdev 1.583374 # Number of insts commited each cycle
2160system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2161system.cpu1.commit.committed_per_cycle::0 434201366 65.34% 65.34% # Number of insts commited each cycle
2162system.cpu1.commit.committed_per_cycle::1 119136384 17.93% 83.27% # Number of insts commited each cycle
2163system.cpu1.commit.committed_per_cycle::2 51278197 7.72% 90.99% # Number of insts commited each cycle
2164system.cpu1.commit.committed_per_cycle::3 17339439 2.61% 93.60% # Number of insts commited each cycle
2165system.cpu1.commit.committed_per_cycle::4 12299899 1.85% 95.45% # Number of insts commited each cycle
2166system.cpu1.commit.committed_per_cycle::5 8244778 1.24% 96.69% # Number of insts commited each cycle
2167system.cpu1.commit.committed_per_cycle::6 5665589 0.85% 97.54% # Number of insts commited each cycle
2168system.cpu1.commit.committed_per_cycle::7 3433584 0.52% 98.06% # Number of insts commited each cycle
2169system.cpu1.commit.committed_per_cycle::8 12905668 1.94% 100.00% # Number of insts commited each cycle
2170system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2171system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2172system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2173system.cpu1.commit.committed_per_cycle::total 664504904 # Number of insts commited each cycle
2174system.cpu1.commit.committedInsts 446004136 # Number of instructions committed
2175system.cpu1.commit.committedOps 525408547 # Number of ops (including micro ops) committed
2176system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2177system.cpu1.commit.refs 161609989 # Number of memory references committed
2178system.cpu1.commit.loads 84365599 # Number of loads committed
2179system.cpu1.commit.membars 3561329 # Number of memory barriers committed
2180system.cpu1.commit.branches 99629625 # Number of branches committed
2181system.cpu1.commit.fp_insts 509948 # Number of committed floating point instructions.
2182system.cpu1.commit.int_insts 482210935 # Number of committed integer instructions.
2183system.cpu1.commit.function_calls 12864051 # Number of function calls committed.
2184system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2185system.cpu1.commit.op_class_0::IntAlu 362699186 69.03% 69.03% # Class of committed instruction
2186system.cpu1.commit.op_class_0::IntMult 966499 0.18% 69.22% # Class of committed instruction
2187system.cpu1.commit.op_class_0::IntDiv 55760 0.01% 69.23% # Class of committed instruction
2188system.cpu1.commit.op_class_0::FloatAdd 8 0.00% 69.23% # Class of committed instruction
2189system.cpu1.commit.op_class_0::FloatCmp 13 0.00% 69.23% # Class of committed instruction
2190system.cpu1.commit.op_class_0::FloatCvt 21 0.00% 69.23% # Class of committed instruction
2191system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.23% # Class of committed instruction
2192system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 69.23% # Class of committed instruction
2193system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.23% # Class of committed instruction
2194system.cpu1.commit.op_class_0::FloatMisc 77071 0.01% 69.24% # Class of committed instruction
2195system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.24% # Class of committed instruction
2196system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.24% # Class of committed instruction
2197system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.24% # Class of committed instruction
2198system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.24% # Class of committed instruction
2199system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.24% # Class of committed instruction
2200system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.24% # Class of committed instruction
2201system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.24% # Class of committed instruction
2202system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.24% # Class of committed instruction
2203system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.24% # Class of committed instruction
2204system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.24% # Class of committed instruction
2205system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.24% # Class of committed instruction
2206system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.24% # Class of committed instruction
2207system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.24% # Class of committed instruction
2208system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.24% # Class of committed instruction
2209system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.24% # Class of committed instruction
2210system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.24% # Class of committed instruction
2211system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.24% # Class of committed instruction
2212system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 69.24% # Class of committed instruction
2213system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.24% # Class of committed instruction
2214system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.24% # Class of committed instruction
2215system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.24% # Class of committed instruction
2216system.cpu1.commit.op_class_0::MemRead 84306280 16.05% 85.29% # Class of committed instruction
2217system.cpu1.commit.op_class_0::MemWrite 76870874 14.63% 99.92% # Class of committed instruction
2218system.cpu1.commit.op_class_0::FloatMemRead 59319 0.01% 99.93% # Class of committed instruction
2219system.cpu1.commit.op_class_0::FloatMemWrite 373516 0.07% 100.00% # Class of committed instruction
2220system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2221system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2222system.cpu1.commit.op_class_0::total 525408547 # Class of committed instruction
2223system.cpu1.commit.bw_lim_events 12905668 # number cycles where commit BW limit reached
2224system.cpu1.rob.rob_reads 1219098786 # The number of ROB reads
2225system.cpu1.rob.rob_writes 1150856845 # The number of ROB writes
2226system.cpu1.timesIdled 925679 # Number of times that the entire CPU went into an idle state and unscheduled itself
2227system.cpu1.idleCycles 20455657 # Total number of cycles that the CPU has spent unscheduled due to idling
2228system.cpu1.quiesceCycles 94076236903 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2229system.cpu1.committedInsts 446004136 # Number of Instructions Simulated
2230system.cpu1.committedOps 525408547 # Number of Ops (including micro ops) Simulated
2231system.cpu1.cpi 1.555241 # CPI: Cycles Per Instruction
2232system.cpu1.cpi_total 1.555241 # CPI: Total CPI of All Threads
2233system.cpu1.ipc 0.642987 # IPC: Instructions Per Cycle
2234system.cpu1.ipc_total 0.642987 # IPC: Total IPC of All Threads
2235system.cpu1.int_regfile_reads 659945611 # number of integer regfile reads
2236system.cpu1.int_regfile_writes 391450025 # number of integer regfile writes
2237system.cpu1.fp_regfile_reads 826837 # number of floating regfile reads
2238system.cpu1.fp_regfile_writes 461620 # number of floating regfile writes
2239system.cpu1.cc_regfile_reads 120567774 # number of cc regfile reads
2240system.cpu1.cc_regfile_writes 121287073 # number of cc regfile writes
2241system.cpu1.misc_regfile_reads 1215585693 # number of misc regfile reads
2242system.cpu1.misc_regfile_writes 14957440 # number of misc regfile writes
2243system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
2244system.cpu1.dcache.tags.replacements 5242137 # number of replacements
2245system.cpu1.dcache.tags.tagsinuse 459.717362 # Cycle average of tags in use
2246system.cpu1.dcache.tags.total_refs 151071021 # Total number of references to valid blocks.
2247system.cpu1.dcache.tags.sampled_refs 5242649 # Sample count of references to valid blocks.
2248system.cpu1.dcache.tags.avg_refs 28.815780 # Average number of references to valid blocks.
2249system.cpu1.dcache.tags.warmup_cycle 8517875621500 # Cycle when the warmup percentage was hit.
2250system.cpu1.dcache.tags.occ_blocks::cpu1.data 459.717362 # Average occupied blocks per requestor
2251system.cpu1.dcache.tags.occ_percent::cpu1.data 0.897885 # Average percentage of cache occupancy
2252system.cpu1.dcache.tags.occ_percent::total 0.897885 # Average percentage of cache occupancy
2253system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2254system.cpu1.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id
2255system.cpu1.dcache.tags.age_task_id_blocks_1024::1 393 # Occupied blocks per task id
2256system.cpu1.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
2257system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2258system.cpu1.dcache.tags.tag_accesses 335085452 # Number of tag accesses
2259system.cpu1.dcache.tags.data_accesses 335085452 # Number of data accesses
2260system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
2261system.cpu1.dcache.ReadReq_hits::cpu1.data 78683388 # number of ReadReq hits
2262system.cpu1.dcache.ReadReq_hits::total 78683388 # number of ReadReq hits
2263system.cpu1.dcache.WriteReq_hits::cpu1.data 67788952 # number of WriteReq hits
2264system.cpu1.dcache.WriteReq_hits::total 67788952 # number of WriteReq hits
2265system.cpu1.dcache.SoftPFReq_hits::cpu1.data 181257 # number of SoftPFReq hits
2266system.cpu1.dcache.SoftPFReq_hits::total 181257 # number of SoftPFReq hits
2267system.cpu1.dcache.WriteLineReq_hits::cpu1.data 140156 # number of WriteLineReq hits
2268system.cpu1.dcache.WriteLineReq_hits::total 140156 # number of WriteLineReq hits
2269system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1756750 # number of LoadLockedReq hits
2270system.cpu1.dcache.LoadLockedReq_hits::total 1756750 # number of LoadLockedReq hits
2271system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1770273 # number of StoreCondReq hits
2272system.cpu1.dcache.StoreCondReq_hits::total 1770273 # number of StoreCondReq hits
2273system.cpu1.dcache.demand_hits::cpu1.data 146612496 # number of demand (read+write) hits
2274system.cpu1.dcache.demand_hits::total 146612496 # number of demand (read+write) hits
2275system.cpu1.dcache.overall_hits::cpu1.data 146793753 # number of overall hits
2276system.cpu1.dcache.overall_hits::total 146793753 # number of overall hits
2277system.cpu1.dcache.ReadReq_misses::cpu1.data 6126313 # number of ReadReq misses
2278system.cpu1.dcache.ReadReq_misses::total 6126313 # number of ReadReq misses
2279system.cpu1.dcache.WriteReq_misses::cpu1.data 6911292 # number of WriteReq misses
2280system.cpu1.dcache.WriteReq_misses::total 6911292 # number of WriteReq misses
2281system.cpu1.dcache.SoftPFReq_misses::cpu1.data 643081 # number of SoftPFReq misses
2282system.cpu1.dcache.SoftPFReq_misses::total 643081 # number of SoftPFReq misses
2283system.cpu1.dcache.WriteLineReq_misses::cpu1.data 451908 # number of WriteLineReq misses
2284system.cpu1.dcache.WriteLineReq_misses::total 451908 # number of WriteLineReq misses
2285system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 241040 # number of LoadLockedReq misses
2286system.cpu1.dcache.LoadLockedReq_misses::total 241040 # number of LoadLockedReq misses
2287system.cpu1.dcache.StoreCondReq_misses::cpu1.data 183733 # number of StoreCondReq misses
2288system.cpu1.dcache.StoreCondReq_misses::total 183733 # number of StoreCondReq misses
2289system.cpu1.dcache.demand_misses::cpu1.data 13489513 # number of demand (read+write) misses
2290system.cpu1.dcache.demand_misses::total 13489513 # number of demand (read+write) misses
2291system.cpu1.dcache.overall_misses::cpu1.data 14132594 # number of overall misses
2292system.cpu1.dcache.overall_misses::total 14132594 # number of overall misses
2293system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 94548549000 # number of ReadReq miss cycles
2294system.cpu1.dcache.ReadReq_miss_latency::total 94548549000 # number of ReadReq miss cycles
2295system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 128933568944 # number of WriteReq miss cycles
2296system.cpu1.dcache.WriteReq_miss_latency::total 128933568944 # number of WriteReq miss cycles
2297system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10455217570 # number of WriteLineReq miss cycles
2298system.cpu1.dcache.WriteLineReq_miss_latency::total 10455217570 # number of WriteLineReq miss cycles
2299system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3390405500 # number of LoadLockedReq miss cycles
2300system.cpu1.dcache.LoadLockedReq_miss_latency::total 3390405500 # number of LoadLockedReq miss cycles
2301system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4379858500 # number of StoreCondReq miss cycles
2302system.cpu1.dcache.StoreCondReq_miss_latency::total 4379858500 # number of StoreCondReq miss cycles
2303system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2605000 # number of StoreCondFailReq miss cycles
2304system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2605000 # number of StoreCondFailReq miss cycles
2305system.cpu1.dcache.demand_miss_latency::cpu1.data 233937335514 # number of demand (read+write) miss cycles
2306system.cpu1.dcache.demand_miss_latency::total 233937335514 # number of demand (read+write) miss cycles
2307system.cpu1.dcache.overall_miss_latency::cpu1.data 233937335514 # number of overall miss cycles
2308system.cpu1.dcache.overall_miss_latency::total 233937335514 # number of overall miss cycles
2309system.cpu1.dcache.ReadReq_accesses::cpu1.data 84809701 # number of ReadReq accesses(hits+misses)
2310system.cpu1.dcache.ReadReq_accesses::total 84809701 # number of ReadReq accesses(hits+misses)
2311system.cpu1.dcache.WriteReq_accesses::cpu1.data 74700244 # number of WriteReq accesses(hits+misses)
2312system.cpu1.dcache.WriteReq_accesses::total 74700244 # number of WriteReq accesses(hits+misses)
2313system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 824338 # number of SoftPFReq accesses(hits+misses)
2314system.cpu1.dcache.SoftPFReq_accesses::total 824338 # number of SoftPFReq accesses(hits+misses)
2315system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 592064 # number of WriteLineReq accesses(hits+misses)
2316system.cpu1.dcache.WriteLineReq_accesses::total 592064 # number of WriteLineReq accesses(hits+misses)
2317system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1997790 # number of LoadLockedReq accesses(hits+misses)
2318system.cpu1.dcache.LoadLockedReq_accesses::total 1997790 # number of LoadLockedReq accesses(hits+misses)
2319system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1954006 # number of StoreCondReq accesses(hits+misses)
2320system.cpu1.dcache.StoreCondReq_accesses::total 1954006 # number of StoreCondReq accesses(hits+misses)
2321system.cpu1.dcache.demand_accesses::cpu1.data 160102009 # number of demand (read+write) accesses
2322system.cpu1.dcache.demand_accesses::total 160102009 # number of demand (read+write) accesses
2323system.cpu1.dcache.overall_accesses::cpu1.data 160926347 # number of overall (read+write) accesses
2324system.cpu1.dcache.overall_accesses::total 160926347 # number of overall (read+write) accesses
2325system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.072236 # miss rate for ReadReq accesses
2326system.cpu1.dcache.ReadReq_miss_rate::total 0.072236 # miss rate for ReadReq accesses
2327system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.092520 # miss rate for WriteReq accesses
2328system.cpu1.dcache.WriteReq_miss_rate::total 0.092520 # miss rate for WriteReq accesses
2329system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.780118 # miss rate for SoftPFReq accesses
2330system.cpu1.dcache.SoftPFReq_miss_rate::total 0.780118 # miss rate for SoftPFReq accesses
2331system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.763276 # miss rate for WriteLineReq accesses
2332system.cpu1.dcache.WriteLineReq_miss_rate::total 0.763276 # miss rate for WriteLineReq accesses
2333system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120653 # miss rate for LoadLockedReq accesses
2334system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120653 # miss rate for LoadLockedReq accesses
2335system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094029 # miss rate for StoreCondReq accesses
2336system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094029 # miss rate for StoreCondReq accesses
2337system.cpu1.dcache.demand_miss_rate::cpu1.data 0.084256 # miss rate for demand accesses
2338system.cpu1.dcache.demand_miss_rate::total 0.084256 # miss rate for demand accesses
2339system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087820 # miss rate for overall accesses
2340system.cpu1.dcache.overall_miss_rate::total 0.087820 # miss rate for overall accesses
2341system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15433.189424 # average ReadReq miss latency
2342system.cpu1.dcache.ReadReq_avg_miss_latency::total 15433.189424 # average ReadReq miss latency
2343system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18655.494363 # average WriteReq miss latency
2344system.cpu1.dcache.WriteReq_avg_miss_latency::total 18655.494363 # average WriteReq miss latency
2345system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23135.721364 # average WriteLineReq miss latency
2346system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23135.721364 # average WriteLineReq miss latency
2347system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14065.738052 # average LoadLockedReq miss latency
2348system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14065.738052 # average LoadLockedReq miss latency
2349system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23838.170062 # average StoreCondReq miss latency
2350system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23838.170062 # average StoreCondReq miss latency
2351system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
2352system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2353system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17342.163169 # average overall miss latency
2354system.cpu1.dcache.demand_avg_miss_latency::total 17342.163169 # average overall miss latency
2355system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16553.035877 # average overall miss latency
2356system.cpu1.dcache.overall_avg_miss_latency::total 16553.035877 # average overall miss latency
2357system.cpu1.dcache.blocked_cycles::no_mshrs 2644851 # number of cycles access was blocked
2358system.cpu1.dcache.blocked_cycles::no_targets 20463296 # number of cycles access was blocked
2359system.cpu1.dcache.blocked::no_mshrs 369952 # number of cycles access was blocked
2360system.cpu1.dcache.blocked::no_targets 688434 # number of cycles access was blocked
2361system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.149173 # average number of cycles each access was blocked
2362system.cpu1.dcache.avg_blocked_cycles::no_targets 29.724412 # average number of cycles each access was blocked
2363system.cpu1.dcache.writebacks::writebacks 5242162 # number of writebacks
2364system.cpu1.dcache.writebacks::total 5242162 # number of writebacks
2365system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3113636 # number of ReadReq MSHR hits
2366system.cpu1.dcache.ReadReq_mshr_hits::total 3113636 # number of ReadReq MSHR hits
2367system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5578267 # number of WriteReq MSHR hits
2368system.cpu1.dcache.WriteReq_mshr_hits::total 5578267 # number of WriteReq MSHR hits
2369system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3659 # number of WriteLineReq MSHR hits
2370system.cpu1.dcache.WriteLineReq_mshr_hits::total 3659 # number of WriteLineReq MSHR hits
2371system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 125068 # number of LoadLockedReq MSHR hits
2372system.cpu1.dcache.LoadLockedReq_mshr_hits::total 125068 # number of LoadLockedReq MSHR hits
2373system.cpu1.dcache.demand_mshr_hits::cpu1.data 8695562 # number of demand (read+write) MSHR hits
2374system.cpu1.dcache.demand_mshr_hits::total 8695562 # number of demand (read+write) MSHR hits
2375system.cpu1.dcache.overall_mshr_hits::cpu1.data 8695562 # number of overall MSHR hits
2376system.cpu1.dcache.overall_mshr_hits::total 8695562 # number of overall MSHR hits
2377system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3012677 # number of ReadReq MSHR misses
2378system.cpu1.dcache.ReadReq_mshr_misses::total 3012677 # number of ReadReq MSHR misses
2379system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1333025 # number of WriteReq MSHR misses
2380system.cpu1.dcache.WriteReq_mshr_misses::total 1333025 # number of WriteReq MSHR misses
2381system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 643006 # number of SoftPFReq MSHR misses
2382system.cpu1.dcache.SoftPFReq_mshr_misses::total 643006 # number of SoftPFReq MSHR misses
2383system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 448249 # number of WriteLineReq MSHR misses
2384system.cpu1.dcache.WriteLineReq_mshr_misses::total 448249 # number of WriteLineReq MSHR misses
2385system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 115972 # number of LoadLockedReq MSHR misses
2386system.cpu1.dcache.LoadLockedReq_mshr_misses::total 115972 # number of LoadLockedReq MSHR misses
2387system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 183726 # number of StoreCondReq MSHR misses
2388system.cpu1.dcache.StoreCondReq_mshr_misses::total 183726 # number of StoreCondReq MSHR misses
2389system.cpu1.dcache.demand_mshr_misses::cpu1.data 4793951 # number of demand (read+write) MSHR misses
2390system.cpu1.dcache.demand_mshr_misses::total 4793951 # number of demand (read+write) MSHR misses
2391system.cpu1.dcache.overall_mshr_misses::cpu1.data 5436957 # number of overall MSHR misses
2392system.cpu1.dcache.overall_mshr_misses::total 5436957 # number of overall MSHR misses
2393system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 8871 # number of ReadReq MSHR uncacheable
2394system.cpu1.dcache.ReadReq_mshr_uncacheable::total 8871 # number of ReadReq MSHR uncacheable
2395system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 8695 # number of WriteReq MSHR uncacheable
2396system.cpu1.dcache.WriteReq_mshr_uncacheable::total 8695 # number of WriteReq MSHR uncacheable
2397system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 17566 # number of overall MSHR uncacheable misses
2398system.cpu1.dcache.overall_mshr_uncacheable_misses::total 17566 # number of overall MSHR uncacheable misses
2399system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42819104500 # number of ReadReq MSHR miss cycles
2400system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42819104500 # number of ReadReq MSHR miss cycles
2401system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26001782801 # number of WriteReq MSHR miss cycles
2402system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26001782801 # number of WriteReq MSHR miss cycles
2403system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14897861000 # number of SoftPFReq MSHR miss cycles
2404system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14897861000 # number of SoftPFReq MSHR miss cycles
2405system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9889085570 # number of WriteLineReq MSHR miss cycles
2406system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9889085570 # number of WriteLineReq MSHR miss cycles
2407system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1553813500 # number of LoadLockedReq MSHR miss cycles
2408system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1553813500 # number of LoadLockedReq MSHR miss cycles
2409system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4196193500 # number of StoreCondReq MSHR miss cycles
2410system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4196193500 # number of StoreCondReq MSHR miss cycles
2411system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2544000 # number of StoreCondFailReq MSHR miss cycles
2412system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2544000 # number of StoreCondFailReq MSHR miss cycles
2413system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 78709972871 # number of demand (read+write) MSHR miss cycles
2414system.cpu1.dcache.demand_mshr_miss_latency::total 78709972871 # number of demand (read+write) MSHR miss cycles
2415system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 93607833871 # number of overall MSHR miss cycles
2416system.cpu1.dcache.overall_mshr_miss_latency::total 93607833871 # number of overall MSHR miss cycles
2417system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1354957000 # number of ReadReq MSHR uncacheable cycles
2418system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1354957000 # number of ReadReq MSHR uncacheable cycles
2419system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1354957000 # number of overall MSHR uncacheable cycles
2420system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1354957000 # number of overall MSHR uncacheable cycles
2421system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035523 # mshr miss rate for ReadReq accesses
2422system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035523 # mshr miss rate for ReadReq accesses
2423system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017845 # mshr miss rate for WriteReq accesses
2424system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017845 # mshr miss rate for WriteReq accesses
2425system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.780027 # mshr miss rate for SoftPFReq accesses
2426system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.780027 # mshr miss rate for SoftPFReq accesses
2427system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.757096 # mshr miss rate for WriteLineReq accesses
2428system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.757096 # mshr miss rate for WriteLineReq accesses
2429system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058050 # mshr miss rate for LoadLockedReq accesses
2430system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058050 # mshr miss rate for LoadLockedReq accesses
2431system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094025 # mshr miss rate for StoreCondReq accesses
2432system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094025 # mshr miss rate for StoreCondReq accesses
2433system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029943 # mshr miss rate for demand accesses
2434system.cpu1.dcache.demand_mshr_miss_rate::total 0.029943 # mshr miss rate for demand accesses
2435system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033785 # mshr miss rate for overall accesses
2436system.cpu1.dcache.overall_mshr_miss_rate::total 0.033785 # mshr miss rate for overall accesses
2437system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14212.975536 # average ReadReq mshr miss latency
2438system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14212.975536 # average ReadReq mshr miss latency
2439system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19505.847828 # average WriteReq mshr miss latency
2440system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19505.847828 # average WriteReq mshr miss latency
2441system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23169.085514 # average SoftPFReq mshr miss latency
2442system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23169.085514 # average SoftPFReq mshr miss latency
2443system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22061.589808 # average WriteLineReq mshr miss latency
2444system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22061.589808 # average WriteLineReq mshr miss latency
2445system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13398.178008 # average LoadLockedReq mshr miss latency
2446system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13398.178008 # average LoadLockedReq mshr miss latency
2447system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22839.410318 # average StoreCondReq mshr miss latency
2448system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22839.410318 # average StoreCondReq mshr miss latency
2449system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
2450system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2451system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16418.601874 # average overall mshr miss latency
2452system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16418.601874 # average overall mshr miss latency
2453system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17216.953136 # average overall mshr miss latency
2454system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17216.953136 # average overall mshr miss latency
2455system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152740.051854 # average ReadReq mshr uncacheable latency
2456system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 152740.051854 # average ReadReq mshr uncacheable latency
2457system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 77135.204372 # average overall mshr uncacheable latency
2458system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 77135.204372 # average overall mshr uncacheable latency
2459system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
2460system.cpu1.icache.tags.replacements 5955489 # number of replacements
2461system.cpu1.icache.tags.tagsinuse 501.186843 # Cycle average of tags in use
2462system.cpu1.icache.tags.total_refs 198342876 # Total number of references to valid blocks.
2463system.cpu1.icache.tags.sampled_refs 5956001 # Sample count of references to valid blocks.
2464system.cpu1.icache.tags.avg_refs 33.301350 # Average number of references to valid blocks.
2465system.cpu1.icache.tags.warmup_cycle 8518419495000 # Cycle when the warmup percentage was hit.
2466system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.186843 # Average occupied blocks per requestor
2467system.cpu1.icache.tags.occ_percent::cpu1.inst 0.978881 # Average percentage of cache occupancy
2468system.cpu1.icache.tags.occ_percent::total 0.978881 # Average percentage of cache occupancy
2469system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2470system.cpu1.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
2471system.cpu1.icache.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id
2472system.cpu1.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id
2473system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2474system.cpu1.icache.tags.tag_accesses 415232377 # Number of tag accesses
2475system.cpu1.icache.tags.data_accesses 415232377 # Number of data accesses
2476system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
2477system.cpu1.icache.ReadReq_hits::cpu1.inst 198342876 # number of ReadReq hits
2478system.cpu1.icache.ReadReq_hits::total 198342876 # number of ReadReq hits
2479system.cpu1.icache.demand_hits::cpu1.inst 198342876 # number of demand (read+write) hits
2480system.cpu1.icache.demand_hits::total 198342876 # number of demand (read+write) hits
2481system.cpu1.icache.overall_hits::cpu1.inst 198342876 # number of overall hits
2482system.cpu1.icache.overall_hits::total 198342876 # number of overall hits
2483system.cpu1.icache.ReadReq_misses::cpu1.inst 6295293 # number of ReadReq misses
2484system.cpu1.icache.ReadReq_misses::total 6295293 # number of ReadReq misses
2485system.cpu1.icache.demand_misses::cpu1.inst 6295293 # number of demand (read+write) misses
2486system.cpu1.icache.demand_misses::total 6295293 # number of demand (read+write) misses
2487system.cpu1.icache.overall_misses::cpu1.inst 6295293 # number of overall misses
2488system.cpu1.icache.overall_misses::total 6295293 # number of overall misses
2489system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 67919445914 # number of ReadReq miss cycles
2490system.cpu1.icache.ReadReq_miss_latency::total 67919445914 # number of ReadReq miss cycles
2491system.cpu1.icache.demand_miss_latency::cpu1.inst 67919445914 # number of demand (read+write) miss cycles
2492system.cpu1.icache.demand_miss_latency::total 67919445914 # number of demand (read+write) miss cycles
2493system.cpu1.icache.overall_miss_latency::cpu1.inst 67919445914 # number of overall miss cycles
2494system.cpu1.icache.overall_miss_latency::total 67919445914 # number of overall miss cycles
2495system.cpu1.icache.ReadReq_accesses::cpu1.inst 204638169 # number of ReadReq accesses(hits+misses)
2496system.cpu1.icache.ReadReq_accesses::total 204638169 # number of ReadReq accesses(hits+misses)
2497system.cpu1.icache.demand_accesses::cpu1.inst 204638169 # number of demand (read+write) accesses
2498system.cpu1.icache.demand_accesses::total 204638169 # number of demand (read+write) accesses
2499system.cpu1.icache.overall_accesses::cpu1.inst 204638169 # number of overall (read+write) accesses
2500system.cpu1.icache.overall_accesses::total 204638169 # number of overall (read+write) accesses
2501system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030763 # miss rate for ReadReq accesses
2502system.cpu1.icache.ReadReq_miss_rate::total 0.030763 # miss rate for ReadReq accesses
2503system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030763 # miss rate for demand accesses
2504system.cpu1.icache.demand_miss_rate::total 0.030763 # miss rate for demand accesses
2505system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030763 # miss rate for overall accesses
2506system.cpu1.icache.overall_miss_rate::total 0.030763 # miss rate for overall accesses
2507system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10788.925299 # average ReadReq miss latency
2508system.cpu1.icache.ReadReq_avg_miss_latency::total 10788.925299 # average ReadReq miss latency
2509system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10788.925299 # average overall miss latency
2510system.cpu1.icache.demand_avg_miss_latency::total 10788.925299 # average overall miss latency
2511system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10788.925299 # average overall miss latency
2512system.cpu1.icache.overall_avg_miss_latency::total 10788.925299 # average overall miss latency
2513system.cpu1.icache.blocked_cycles::no_mshrs 9829448 # number of cycles access was blocked
2514system.cpu1.icache.blocked_cycles::no_targets 701 # number of cycles access was blocked
2515system.cpu1.icache.blocked::no_mshrs 729519 # number of cycles access was blocked
2516system.cpu1.icache.blocked::no_targets 3 # number of cycles access was blocked
2517system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.473875 # average number of cycles each access was blocked
2518system.cpu1.icache.avg_blocked_cycles::no_targets 233.666667 # average number of cycles each access was blocked
2519system.cpu1.icache.writebacks::writebacks 5955489 # number of writebacks
2520system.cpu1.icache.writebacks::total 5955489 # number of writebacks
2521system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 339254 # number of ReadReq MSHR hits
2522system.cpu1.icache.ReadReq_mshr_hits::total 339254 # number of ReadReq MSHR hits
2523system.cpu1.icache.demand_mshr_hits::cpu1.inst 339254 # number of demand (read+write) MSHR hits
2524system.cpu1.icache.demand_mshr_hits::total 339254 # number of demand (read+write) MSHR hits
2525system.cpu1.icache.overall_mshr_hits::cpu1.inst 339254 # number of overall MSHR hits
2526system.cpu1.icache.overall_mshr_hits::total 339254 # number of overall MSHR hits
2527system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5956039 # number of ReadReq MSHR misses
2528system.cpu1.icache.ReadReq_mshr_misses::total 5956039 # number of ReadReq MSHR misses
2529system.cpu1.icache.demand_mshr_misses::cpu1.inst 5956039 # number of demand (read+write) MSHR misses
2530system.cpu1.icache.demand_mshr_misses::total 5956039 # number of demand (read+write) MSHR misses
2531system.cpu1.icache.overall_mshr_misses::cpu1.inst 5956039 # number of overall MSHR misses
2532system.cpu1.icache.overall_mshr_misses::total 5956039 # number of overall MSHR misses
2533system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
2534system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable
2535system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
2536system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses
2537system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 61337721519 # number of ReadReq MSHR miss cycles
2538system.cpu1.icache.ReadReq_mshr_miss_latency::total 61337721519 # number of ReadReq MSHR miss cycles
2539system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 61337721519 # number of demand (read+write) MSHR miss cycles
2540system.cpu1.icache.demand_mshr_miss_latency::total 61337721519 # number of demand (read+write) MSHR miss cycles
2541system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 61337721519 # number of overall MSHR miss cycles
2542system.cpu1.icache.overall_mshr_miss_latency::total 61337721519 # number of overall MSHR miss cycles
2543system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6801498 # number of ReadReq MSHR uncacheable cycles
2544system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6801498 # number of ReadReq MSHR uncacheable cycles
2545system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6801498 # number of overall MSHR uncacheable cycles
2546system.cpu1.icache.overall_mshr_uncacheable_latency::total 6801498 # number of overall MSHR uncacheable cycles
2547system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.029105 # mshr miss rate for ReadReq accesses
2548system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.029105 # mshr miss rate for ReadReq accesses
2549system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.029105 # mshr miss rate for demand accesses
2550system.cpu1.icache.demand_mshr_miss_rate::total 0.029105 # mshr miss rate for demand accesses
2551system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.029105 # mshr miss rate for overall accesses
2552system.cpu1.icache.overall_mshr_miss_rate::total 0.029105 # mshr miss rate for overall accesses
2553system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10298.408308 # average ReadReq mshr miss latency
2554system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10298.408308 # average ReadReq mshr miss latency
2555system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10298.408308 # average overall mshr miss latency
2556system.cpu1.icache.demand_avg_mshr_miss_latency::total 10298.408308 # average overall mshr miss latency
2557system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10298.408308 # average overall mshr miss latency
2558system.cpu1.icache.overall_avg_mshr_miss_latency::total 10298.408308 # average overall mshr miss latency
2559system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 101514.895522 # average ReadReq mshr uncacheable latency
2560system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 101514.895522 # average ReadReq mshr uncacheable latency
2561system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 101514.895522 # average overall mshr uncacheable latency
2562system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 101514.895522 # average overall mshr uncacheable latency
2563system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
2564system.cpu1.l2cache.prefetcher.num_hwpf_issued 7017688 # number of hwpf issued
2565system.cpu1.l2cache.prefetcher.pfIdentified 7023313 # number of prefetch candidates identified
2566system.cpu1.l2cache.prefetcher.pfBufferHit 5116 # number of redundant prefetches already in prefetch queue
2567system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
2568system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2569system.cpu1.l2cache.prefetcher.pfSpanPage 831383 # number of prefetches not generated due to page crossing
2570system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
2571system.cpu1.l2cache.tags.replacements 2042934 # number of replacements
2572system.cpu1.l2cache.tags.tagsinuse 12933.505047 # Cycle average of tags in use
2573system.cpu1.l2cache.tags.total_refs 10254699 # Total number of references to valid blocks.
2574system.cpu1.l2cache.tags.sampled_refs 2058843 # Sample count of references to valid blocks.
2575system.cpu1.l2cache.tags.avg_refs 4.980807 # Average number of references to valid blocks.
2576system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
2577system.cpu1.l2cache.tags.occ_blocks::writebacks 12624.033726 # Average occupied blocks per requestor
2578system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 36.418354 # Average occupied blocks per requestor
2579system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 27.691890 # Average occupied blocks per requestor
2580system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 245.361077 # Average occupied blocks per requestor
2581system.cpu1.l2cache.tags.occ_percent::writebacks 0.770510 # Average percentage of cache occupancy
2582system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002223 # Average percentage of cache occupancy
2583system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001690 # Average percentage of cache occupancy
2584system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014976 # Average percentage of cache occupancy
2585system.cpu1.l2cache.tags.occ_percent::total 0.789399 # Average percentage of cache occupancy
2586system.cpu1.l2cache.tags.occ_task_id_blocks::1022 293 # Occupied blocks per task id
2587system.cpu1.l2cache.tags.occ_task_id_blocks::1023 63 # Occupied blocks per task id
2588system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15553 # Occupied blocks per task id
2589system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id
2590system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 116 # Occupied blocks per task id
2591system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 99 # Occupied blocks per task id
2592system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 69 # Occupied blocks per task id
2593system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id
2594system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id
2595system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id
2596system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id
2597system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1807 # Occupied blocks per task id
2598system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7301 # Occupied blocks per task id
2599system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4524 # Occupied blocks per task id
2600system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1724 # Occupied blocks per task id
2601system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.017883 # Percentage of cache occupancy per task id
2602system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id
2603system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.949280 # Percentage of cache occupancy per task id
2604system.cpu1.l2cache.tags.tag_accesses 390440087 # Number of tag accesses
2605system.cpu1.l2cache.tags.data_accesses 390440087 # Number of data accesses
2606system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
2607system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 557579 # number of ReadReq hits
2608system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 186161 # number of ReadReq hits
2609system.cpu1.l2cache.ReadReq_hits::total 743740 # number of ReadReq hits
2610system.cpu1.l2cache.WritebackDirty_hits::writebacks 3343376 # number of WritebackDirty hits
2611system.cpu1.l2cache.WritebackDirty_hits::total 3343376 # number of WritebackDirty hits
2612system.cpu1.l2cache.WritebackClean_hits::writebacks 7851276 # number of WritebackClean hits
2613system.cpu1.l2cache.WritebackClean_hits::total 7851276 # number of WritebackClean hits
2614system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits
2615system.cpu1.l2cache.UpgradeReq_hits::total 37 # number of UpgradeReq hits
2616system.cpu1.l2cache.ReadExReq_hits::cpu1.data 859794 # number of ReadExReq hits
2617system.cpu1.l2cache.ReadExReq_hits::total 859794 # number of ReadExReq hits
2618system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5412981 # number of ReadCleanReq hits
2619system.cpu1.l2cache.ReadCleanReq_hits::total 5412981 # number of ReadCleanReq hits
2620system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2828036 # number of ReadSharedReq hits
2621system.cpu1.l2cache.ReadSharedReq_hits::total 2828036 # number of ReadSharedReq hits
2622system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 191737 # number of InvalidateReq hits
2623system.cpu1.l2cache.InvalidateReq_hits::total 191737 # number of InvalidateReq hits
2624system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 557579 # number of demand (read+write) hits
2625system.cpu1.l2cache.demand_hits::cpu1.itb.walker 186161 # number of demand (read+write) hits
2626system.cpu1.l2cache.demand_hits::cpu1.inst 5412981 # number of demand (read+write) hits
2627system.cpu1.l2cache.demand_hits::cpu1.data 3687830 # number of demand (read+write) hits
2628system.cpu1.l2cache.demand_hits::total 9844551 # number of demand (read+write) hits
2629system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 557579 # number of overall hits
2630system.cpu1.l2cache.overall_hits::cpu1.itb.walker 186161 # number of overall hits
2631system.cpu1.l2cache.overall_hits::cpu1.inst 5412981 # number of overall hits
2632system.cpu1.l2cache.overall_hits::cpu1.data 3687830 # number of overall hits
2633system.cpu1.l2cache.overall_hits::total 9844551 # number of overall hits
2634system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 21615 # number of ReadReq misses
2635system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9433 # number of ReadReq misses
2636system.cpu1.l2cache.ReadReq_misses::total 31048 # number of ReadReq misses
2637system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses
2638system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses
2639system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 224939 # number of UpgradeReq misses
2640system.cpu1.l2cache.UpgradeReq_misses::total 224939 # number of UpgradeReq misses
2641system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 183720 # number of SCUpgradeReq misses
2642system.cpu1.l2cache.SCUpgradeReq_misses::total 183720 # number of SCUpgradeReq misses
2643system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses
2644system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
2645system.cpu1.l2cache.ReadExReq_misses::cpu1.data 255308 # number of ReadExReq misses
2646system.cpu1.l2cache.ReadExReq_misses::total 255308 # number of ReadExReq misses
2647system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 543023 # number of ReadCleanReq misses
2648system.cpu1.l2cache.ReadCleanReq_misses::total 543023 # number of ReadCleanReq misses
2649system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 939708 # number of ReadSharedReq misses
2650system.cpu1.l2cache.ReadSharedReq_misses::total 939708 # number of ReadSharedReq misses
2651system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 256512 # number of InvalidateReq misses
2652system.cpu1.l2cache.InvalidateReq_misses::total 256512 # number of InvalidateReq misses
2653system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 21615 # number of demand (read+write) misses
2654system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9433 # number of demand (read+write) misses
2655system.cpu1.l2cache.demand_misses::cpu1.inst 543023 # number of demand (read+write) misses
2656system.cpu1.l2cache.demand_misses::cpu1.data 1195016 # number of demand (read+write) misses
2657system.cpu1.l2cache.demand_misses::total 1769087 # number of demand (read+write) misses
2658system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 21615 # number of overall misses
2659system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9433 # number of overall misses
2660system.cpu1.l2cache.overall_misses::cpu1.inst 543023 # number of overall misses
2661system.cpu1.l2cache.overall_misses::cpu1.data 1195016 # number of overall misses
2662system.cpu1.l2cache.overall_misses::total 1769087 # number of overall misses
2663system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 686942500 # number of ReadReq miss cycles
2664system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 338389000 # number of ReadReq miss cycles
2665system.cpu1.l2cache.ReadReq_miss_latency::total 1025331500 # number of ReadReq miss cycles
2666system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 939480500 # number of UpgradeReq miss cycles
2667system.cpu1.l2cache.UpgradeReq_miss_latency::total 939480500 # number of UpgradeReq miss cycles
2668system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 264112000 # number of SCUpgradeReq miss cycles
2669system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 264112000 # number of SCUpgradeReq miss cycles
2670system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2448496 # number of SCUpgradeFailReq miss cycles
2671system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2448496 # number of SCUpgradeFailReq miss cycles
2672system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12203061000 # number of ReadExReq miss cycles
2673system.cpu1.l2cache.ReadExReq_miss_latency::total 12203061000 # number of ReadExReq miss cycles
2674system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 19608835500 # number of ReadCleanReq miss cycles
2675system.cpu1.l2cache.ReadCleanReq_miss_latency::total 19608835500 # number of ReadCleanReq miss cycles
2676system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 34743736987 # number of ReadSharedReq miss cycles
2677system.cpu1.l2cache.ReadSharedReq_miss_latency::total 34743736987 # number of ReadSharedReq miss cycles
2678system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 165000 # number of InvalidateReq miss cycles
2679system.cpu1.l2cache.InvalidateReq_miss_latency::total 165000 # number of InvalidateReq miss cycles
2680system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 686942500 # number of demand (read+write) miss cycles
2681system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 338389000 # number of demand (read+write) miss cycles
2682system.cpu1.l2cache.demand_miss_latency::cpu1.inst 19608835500 # number of demand (read+write) miss cycles
2683system.cpu1.l2cache.demand_miss_latency::cpu1.data 46946797987 # number of demand (read+write) miss cycles
2684system.cpu1.l2cache.demand_miss_latency::total 67580964987 # number of demand (read+write) miss cycles
2685system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 686942500 # number of overall miss cycles
2686system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 338389000 # number of overall miss cycles
2687system.cpu1.l2cache.overall_miss_latency::cpu1.inst 19608835500 # number of overall miss cycles
2688system.cpu1.l2cache.overall_miss_latency::cpu1.data 46946797987 # number of overall miss cycles
2689system.cpu1.l2cache.overall_miss_latency::total 67580964987 # number of overall miss cycles
2690system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 579194 # number of ReadReq accesses(hits+misses)
2691system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 195594 # number of ReadReq accesses(hits+misses)
2692system.cpu1.l2cache.ReadReq_accesses::total 774788 # number of ReadReq accesses(hits+misses)
2693system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3343377 # number of WritebackDirty accesses(hits+misses)
2694system.cpu1.l2cache.WritebackDirty_accesses::total 3343377 # number of WritebackDirty accesses(hits+misses)
2695system.cpu1.l2cache.WritebackClean_accesses::writebacks 7851276 # number of WritebackClean accesses(hits+misses)
2696system.cpu1.l2cache.WritebackClean_accesses::total 7851276 # number of WritebackClean accesses(hits+misses)
2697system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 224976 # number of UpgradeReq accesses(hits+misses)
2698system.cpu1.l2cache.UpgradeReq_accesses::total 224976 # number of UpgradeReq accesses(hits+misses)
2699system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 183720 # number of SCUpgradeReq accesses(hits+misses)
2700system.cpu1.l2cache.SCUpgradeReq_accesses::total 183720 # number of SCUpgradeReq accesses(hits+misses)
2701system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses)
2702system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
2703system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1115102 # number of ReadExReq accesses(hits+misses)
2704system.cpu1.l2cache.ReadExReq_accesses::total 1115102 # number of ReadExReq accesses(hits+misses)
2705system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5956004 # number of ReadCleanReq accesses(hits+misses)
2706system.cpu1.l2cache.ReadCleanReq_accesses::total 5956004 # number of ReadCleanReq accesses(hits+misses)
2707system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3767744 # number of ReadSharedReq accesses(hits+misses)
2708system.cpu1.l2cache.ReadSharedReq_accesses::total 3767744 # number of ReadSharedReq accesses(hits+misses)
2709system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 448249 # number of InvalidateReq accesses(hits+misses)
2710system.cpu1.l2cache.InvalidateReq_accesses::total 448249 # number of InvalidateReq accesses(hits+misses)
2711system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 579194 # number of demand (read+write) accesses
2712system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 195594 # number of demand (read+write) accesses
2713system.cpu1.l2cache.demand_accesses::cpu1.inst 5956004 # number of demand (read+write) accesses
2714system.cpu1.l2cache.demand_accesses::cpu1.data 4882846 # number of demand (read+write) accesses
2715system.cpu1.l2cache.demand_accesses::total 11613638 # number of demand (read+write) accesses
2716system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 579194 # number of overall (read+write) accesses
2717system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 195594 # number of overall (read+write) accesses
2718system.cpu1.l2cache.overall_accesses::cpu1.inst 5956004 # number of overall (read+write) accesses
2719system.cpu1.l2cache.overall_accesses::cpu1.data 4882846 # number of overall (read+write) accesses
2720system.cpu1.l2cache.overall_accesses::total 11613638 # number of overall (read+write) accesses
2721system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.037319 # miss rate for ReadReq accesses
2722system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048227 # miss rate for ReadReq accesses
2723system.cpu1.l2cache.ReadReq_miss_rate::total 0.040073 # miss rate for ReadReq accesses
2724system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses
2725system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses
2726system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999836 # miss rate for UpgradeReq accesses
2727system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999836 # miss rate for UpgradeReq accesses
2728system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
2729system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
2730system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2731system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2732system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.228955 # miss rate for ReadExReq accesses
2733system.cpu1.l2cache.ReadExReq_miss_rate::total 0.228955 # miss rate for ReadExReq accesses
2734system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.091172 # miss rate for ReadCleanReq accesses
2735system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.091172 # miss rate for ReadCleanReq accesses
2736system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.249409 # miss rate for ReadSharedReq accesses
2737system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.249409 # miss rate for ReadSharedReq accesses
2738system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.572253 # miss rate for InvalidateReq accesses
2739system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.572253 # miss rate for InvalidateReq accesses
2740system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.037319 # miss rate for demand accesses
2741system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048227 # miss rate for demand accesses
2742system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.091172 # miss rate for demand accesses
2743system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.244738 # miss rate for demand accesses
2744system.cpu1.l2cache.demand_miss_rate::total 0.152328 # miss rate for demand accesses
2745system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.037319 # miss rate for overall accesses
2746system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048227 # miss rate for overall accesses
2747system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.091172 # miss rate for overall accesses
2748system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.244738 # miss rate for overall accesses
2749system.cpu1.l2cache.overall_miss_rate::total 0.152328 # miss rate for overall accesses
2750system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 31780.823502 # average ReadReq miss latency
2751system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 35872.893035 # average ReadReq miss latency
2752system.cpu1.l2cache.ReadReq_avg_miss_latency::total 33024.075625 # average ReadReq miss latency
2753system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4176.601212 # average UpgradeReq miss latency
2754system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4176.601212 # average UpgradeReq miss latency
2755system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1437.578924 # average SCUpgradeReq miss latency
2756system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1437.578924 # average SCUpgradeReq miss latency
2757system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 408082.666667 # average SCUpgradeFailReq miss latency
2758system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 408082.666667 # average SCUpgradeFailReq miss latency
2759system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 47797.409404 # average ReadExReq miss latency
2760system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 47797.409404 # average ReadExReq miss latency
2761system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36110.506369 # average ReadCleanReq miss latency
2762system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36110.506369 # average ReadCleanReq miss latency
2763system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 36972.907528 # average ReadSharedReq miss latency
2764system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 36972.907528 # average ReadSharedReq miss latency
2765system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 0.643245 # average InvalidateReq miss latency
2766system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 0.643245 # average InvalidateReq miss latency
2767system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 31780.823502 # average overall miss latency
2768system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 35872.893035 # average overall miss latency
2769system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36110.506369 # average overall miss latency
2770system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 39285.497422 # average overall miss latency
2771system.cpu1.l2cache.demand_avg_miss_latency::total 38201.040982 # average overall miss latency
2772system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 31780.823502 # average overall miss latency
2773system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 35872.893035 # average overall miss latency
2774system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36110.506369 # average overall miss latency
2775system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 39285.497422 # average overall miss latency
2776system.cpu1.l2cache.overall_avg_miss_latency::total 38201.040982 # average overall miss latency
2777system.cpu1.l2cache.blocked_cycles::no_mshrs 345 # number of cycles access was blocked
2778system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2779system.cpu1.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked
2780system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2781system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 43.125000 # average number of cycles each access was blocked
2782system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2783system.cpu1.l2cache.unused_prefetches 42412 # number of HardPF blocks evicted w/o reference
2784system.cpu1.l2cache.writebacks::writebacks 1137390 # number of writebacks
2785system.cpu1.l2cache.writebacks::total 1137390 # number of writebacks
2786system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 59 # number of ReadReq MSHR hits
2787system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 256 # number of ReadReq MSHR hits
2788system.cpu1.l2cache.ReadReq_mshr_hits::total 315 # number of ReadReq MSHR hits
2789system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 10963 # number of ReadExReq MSHR hits
2790system.cpu1.l2cache.ReadExReq_mshr_hits::total 10963 # number of ReadExReq MSHR hits
2791system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits
2792system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
2793system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 3995 # number of ReadSharedReq MSHR hits
2794system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 3995 # number of ReadSharedReq MSHR hits
2795system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 3 # number of InvalidateReq MSHR hits
2796system.cpu1.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits
2797system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 59 # number of demand (read+write) MSHR hits
2798system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 256 # number of demand (read+write) MSHR hits
2799system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
2800system.cpu1.l2cache.demand_mshr_hits::cpu1.data 14958 # number of demand (read+write) MSHR hits
2801system.cpu1.l2cache.demand_mshr_hits::total 15274 # number of demand (read+write) MSHR hits
2802system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 59 # number of overall MSHR hits
2803system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 256 # number of overall MSHR hits
2804system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
2805system.cpu1.l2cache.overall_mshr_hits::cpu1.data 14958 # number of overall MSHR hits
2806system.cpu1.l2cache.overall_mshr_hits::total 15274 # number of overall MSHR hits
2807system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 21556 # number of ReadReq MSHR misses
2808system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9177 # number of ReadReq MSHR misses
2809system.cpu1.l2cache.ReadReq_mshr_misses::total 30733 # number of ReadReq MSHR misses
2810system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses
2811system.cpu1.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses
2812system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 745312 # number of HardPFReq MSHR misses
2813system.cpu1.l2cache.HardPFReq_mshr_misses::total 745312 # number of HardPFReq MSHR misses
2814system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 224939 # number of UpgradeReq MSHR misses
2815system.cpu1.l2cache.UpgradeReq_mshr_misses::total 224939 # number of UpgradeReq MSHR misses
2816system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 183720 # number of SCUpgradeReq MSHR misses
2817system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 183720 # number of SCUpgradeReq MSHR misses
2818system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses
2819system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses
2820system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 244345 # number of ReadExReq MSHR misses
2821system.cpu1.l2cache.ReadExReq_mshr_misses::total 244345 # number of ReadExReq MSHR misses
2822system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 543022 # number of ReadCleanReq MSHR misses
2823system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 543022 # number of ReadCleanReq MSHR misses
2824system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 935713 # number of ReadSharedReq MSHR misses
2825system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 935713 # number of ReadSharedReq MSHR misses
2826system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 256509 # number of InvalidateReq MSHR misses
2827system.cpu1.l2cache.InvalidateReq_mshr_misses::total 256509 # number of InvalidateReq MSHR misses
2828system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 21556 # number of demand (read+write) MSHR misses
2829system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9177 # number of demand (read+write) MSHR misses
2830system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 543022 # number of demand (read+write) MSHR misses
2831system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1180058 # number of demand (read+write) MSHR misses
2832system.cpu1.l2cache.demand_mshr_misses::total 1753813 # number of demand (read+write) MSHR misses
2833system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 21556 # number of overall MSHR misses
2834system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9177 # number of overall MSHR misses
2835system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 543022 # number of overall MSHR misses
2836system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1180058 # number of overall MSHR misses
2837system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 745312 # number of overall MSHR misses
2838system.cpu1.l2cache.overall_mshr_misses::total 2499125 # number of overall MSHR misses
2839system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
2840system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 8871 # number of ReadReq MSHR uncacheable
2841system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 8938 # number of ReadReq MSHR uncacheable
2842system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 8695 # number of WriteReq MSHR uncacheable
2843system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 8695 # number of WriteReq MSHR uncacheable
2844system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
2845system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 17566 # number of overall MSHR uncacheable misses
2846system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 17633 # number of overall MSHR uncacheable misses
2847system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 556465500 # number of ReadReq MSHR miss cycles
2848system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 279014500 # number of ReadReq MSHR miss cycles
2849system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 835480000 # number of ReadReq MSHR miss cycles
2850system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 36237678760 # number of HardPFReq MSHR miss cycles
2851system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 36237678760 # number of HardPFReq MSHR miss cycles
2852system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4227924487 # number of UpgradeReq MSHR miss cycles
2853system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4227924487 # number of UpgradeReq MSHR miss cycles
2854system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2815609497 # number of SCUpgradeReq MSHR miss cycles
2855system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2815609497 # number of SCUpgradeReq MSHR miss cycles
2856system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2082496 # number of SCUpgradeFailReq MSHR miss cycles
2857system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2082496 # number of SCUpgradeFailReq MSHR miss cycles
2858system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9065423000 # number of ReadExReq MSHR miss cycles
2859system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9065423000 # number of ReadExReq MSHR miss cycles
2860system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 16350690000 # number of ReadCleanReq MSHR miss cycles
2861system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 16350690000 # number of ReadCleanReq MSHR miss cycles
2862system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 28869020987 # number of ReadSharedReq MSHR miss cycles
2863system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 28869020987 # number of ReadSharedReq MSHR miss cycles
2864system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 5973751999 # number of InvalidateReq MSHR miss cycles
2865system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 5973751999 # number of InvalidateReq MSHR miss cycles
2866system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 556465500 # number of demand (read+write) MSHR miss cycles
2867system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 279014500 # number of demand (read+write) MSHR miss cycles
2868system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 16350690000 # number of demand (read+write) MSHR miss cycles
2869system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 37934443987 # number of demand (read+write) MSHR miss cycles
2870system.cpu1.l2cache.demand_mshr_miss_latency::total 55120613987 # number of demand (read+write) MSHR miss cycles
2871system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 556465500 # number of overall MSHR miss cycles
2872system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 279014500 # number of overall MSHR miss cycles
2873system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16350690000 # number of overall MSHR miss cycles
2874system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 37934443987 # number of overall MSHR miss cycles
2875system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 36237678760 # number of overall MSHR miss cycles
2876system.cpu1.l2cache.overall_mshr_miss_latency::total 91358292747 # number of overall MSHR miss cycles
2877system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6298000 # number of ReadReq MSHR uncacheable cycles
2878system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1283792500 # number of ReadReq MSHR uncacheable cycles
2879system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1290090500 # number of ReadReq MSHR uncacheable cycles
2880system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6298000 # number of overall MSHR uncacheable cycles
2881system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1283792500 # number of overall MSHR uncacheable cycles
2882system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1290090500 # number of overall MSHR uncacheable cycles
2883system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.037217 # mshr miss rate for ReadReq accesses
2884system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046919 # mshr miss rate for ReadReq accesses
2885system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.039666 # mshr miss rate for ReadReq accesses
2886system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses
2887system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses
2888system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2889system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2890system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999836 # mshr miss rate for UpgradeReq accesses
2891system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999836 # mshr miss rate for UpgradeReq accesses
2892system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
2893system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
2894system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2895system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2896system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.219123 # mshr miss rate for ReadExReq accesses
2897system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.219123 # mshr miss rate for ReadExReq accesses
2898system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.091172 # mshr miss rate for ReadCleanReq accesses
2899system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.091172 # mshr miss rate for ReadCleanReq accesses
2900system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.248348 # mshr miss rate for ReadSharedReq accesses
2901system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248348 # mshr miss rate for ReadSharedReq accesses
2902system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.572247 # mshr miss rate for InvalidateReq accesses
2903system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.572247 # mshr miss rate for InvalidateReq accesses
2904system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.037217 # mshr miss rate for demand accesses
2905system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046919 # mshr miss rate for demand accesses
2906system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.091172 # mshr miss rate for demand accesses
2907system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.241674 # mshr miss rate for demand accesses
2908system.cpu1.l2cache.demand_mshr_miss_rate::total 0.151013 # mshr miss rate for demand accesses
2909system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.037217 # mshr miss rate for overall accesses
2910system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046919 # mshr miss rate for overall accesses
2911system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.091172 # mshr miss rate for overall accesses
2912system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.241674 # mshr miss rate for overall accesses
2913system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2914system.cpu1.l2cache.overall_mshr_miss_rate::total 0.215189 # mshr miss rate for overall accesses
2915system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 25814.877528 # average ReadReq mshr miss latency
2916system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 30403.672224 # average ReadReq mshr miss latency
2917system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 27185.110468 # average ReadReq mshr miss latency
2918system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48620.817537 # average HardPFReq mshr miss latency
2919system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48620.817537 # average HardPFReq mshr miss latency
2920system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18795.871267 # average UpgradeReq mshr miss latency
2921system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18795.871267 # average UpgradeReq mshr miss latency
2922system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15325.547012 # average SCUpgradeReq mshr miss latency
2923system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15325.547012 # average SCUpgradeReq mshr miss latency
2924system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 347082.666667 # average SCUpgradeFailReq mshr miss latency
2925system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 347082.666667 # average SCUpgradeFailReq mshr miss latency
2926system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37100.914690 # average ReadExReq mshr miss latency
2927system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37100.914690 # average ReadExReq mshr miss latency
2928system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30110.548007 # average ReadCleanReq mshr miss latency
2929system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30110.548007 # average ReadCleanReq mshr miss latency
2930system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 30852.431234 # average ReadSharedReq mshr miss latency
2931system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30852.431234 # average ReadSharedReq mshr miss latency
2932system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23288.664331 # average InvalidateReq mshr miss latency
2933system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23288.664331 # average InvalidateReq mshr miss latency
2934system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 25814.877528 # average overall mshr miss latency
2935system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 30403.672224 # average overall mshr miss latency
2936system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30110.548007 # average overall mshr miss latency
2937system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32146.253817 # average overall mshr miss latency
2938system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31429.014374 # average overall mshr miss latency
2939system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 25814.877528 # average overall mshr miss latency
2940system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 30403.672224 # average overall mshr miss latency
2941system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30110.548007 # average overall mshr miss latency
2942system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32146.253817 # average overall mshr miss latency
2943system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48620.817537 # average overall mshr miss latency
2944system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36556.111738 # average overall mshr miss latency
2945system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94000 # average ReadReq mshr uncacheable latency
2946system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 144717.901026 # average ReadReq mshr uncacheable latency
2947system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 144337.715373 # average ReadReq mshr uncacheable latency
2948system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94000 # average overall mshr uncacheable latency
2949system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 73083.940567 # average overall mshr uncacheable latency
2950system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 73163.415187 # average overall mshr uncacheable latency
2951system.cpu1.toL2Bus.snoop_filter.tot_requests 23228623 # Total number of requests made to the snoop filter.
2952system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11943528 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2953system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 5072 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2954system.cpu1.toL2Bus.snoop_filter.tot_snoops 598776 # Total number of snoops made to the snoop filter.
2955system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 598706 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2956system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 70 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2957system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
2958system.cpu1.toL2Bus.trans_dist::ReadReq 867379 # Transaction distribution
2959system.cpu1.toL2Bus.trans_dist::ReadResp 10679013 # Transaction distribution
2960system.cpu1.toL2Bus.trans_dist::WriteReq 8695 # Transaction distribution
2961system.cpu1.toL2Bus.trans_dist::WriteResp 8695 # Transaction distribution
2962system.cpu1.toL2Bus.trans_dist::WritebackDirty 4499349 # Transaction distribution
2963system.cpu1.toL2Bus.trans_dist::WritebackClean 7854270 # Transaction distribution
2964system.cpu1.toL2Bus.trans_dist::CleanEvict 1254191 # Transaction distribution
2965system.cpu1.toL2Bus.trans_dist::HardPFReq 938082 # Transaction distribution
2966system.cpu1.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution
2967system.cpu1.toL2Bus.trans_dist::UpgradeReq 428069 # Transaction distribution
2968system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 332128 # Transaction distribution
2969system.cpu1.toL2Bus.trans_dist::UpgradeResp 468300 # Transaction distribution
2970system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution
2971system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 113 # Transaction distribution
2972system.cpu1.toL2Bus.trans_dist::ReadExReq 1145370 # Transaction distribution
2973system.cpu1.toL2Bus.trans_dist::ReadExResp 1120388 # Transaction distribution
2974system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5956039 # Transaction distribution
2975system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4785637 # Transaction distribution
2976system.cpu1.toL2Bus.trans_dist::InvalidateReq 521245 # Transaction distribution
2977system.cpu1.toL2Bus.trans_dist::InvalidateResp 449809 # Transaction distribution
2978system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17867666 # Packet count per connected master and slave (bytes)
2979system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16911297 # Packet count per connected master and slave (bytes)
2980system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 409122 # Packet count per connected master and slave (bytes)
2981system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1224107 # Packet count per connected master and slave (bytes)
2982system.cpu1.toL2Bus.pkt_count::total 36412192 # Packet count per connected master and slave (bytes)
2983system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 762336624 # Cumulative packet size per connected master and slave (bytes)
2984system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 654015560 # Cumulative packet size per connected master and slave (bytes)
2985system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1564752 # Cumulative packet size per connected master and slave (bytes)
2986system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4633552 # Cumulative packet size per connected master and slave (bytes)
2987system.cpu1.toL2Bus.pkt_size::total 1422550488 # Cumulative packet size per connected master and slave (bytes)
2988system.cpu1.toL2Bus.snoops 5059056 # Total snoops (count)
2989system.cpu1.toL2Bus.snoopTraffic 80617704 # Total snoop traffic (bytes)
2990system.cpu1.toL2Bus.snoop_fanout::samples 17392868 # Request fanout histogram
2991system.cpu1.toL2Bus.snoop_fanout::mean 0.053991 # Request fanout histogram
2992system.cpu1.toL2Bus.snoop_fanout::stdev 0.226018 # Request fanout histogram
2993system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2994system.cpu1.toL2Bus.snoop_fanout::0 16453876 94.60% 94.60% # Request fanout histogram
2995system.cpu1.toL2Bus.snoop_fanout::1 938922 5.40% 100.00% # Request fanout histogram
2996system.cpu1.toL2Bus.snoop_fanout::2 70 0.00% 100.00% # Request fanout histogram
2997system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2998system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2999system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3000system.cpu1.toL2Bus.snoop_fanout::total 17392868 # Request fanout histogram
3001system.cpu1.toL2Bus.reqLayer0.occupancy 23086793966 # Layer occupancy (ticks)
3002system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3003system.cpu1.toL2Bus.snoopLayer0.occupancy 170580468 # Layer occupancy (ticks)
3004system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3005system.cpu1.toL2Bus.respLayer0.occupancy 8939751182 # Layer occupancy (ticks)
3006system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3007system.cpu1.toL2Bus.respLayer1.occupancy 7774836803 # Layer occupancy (ticks)
3008system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3009system.cpu1.toL2Bus.respLayer2.occupancy 213941664 # Layer occupancy (ticks)
3010system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
3011system.cpu1.toL2Bus.respLayer3.occupancy 645834647 # Layer occupancy (ticks)
3012system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
3013system.iobus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3014system.iobus.trans_dist::ReadReq 40408 # Transaction distribution
3015system.iobus.trans_dist::ReadResp 40408 # Transaction distribution
3016system.iobus.trans_dist::WriteReq 136658 # Transaction distribution
3017system.iobus.trans_dist::WriteResp 136658 # Transaction distribution
3018system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47776 # Packet count per connected master and slave (bytes)
3019system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
3020system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
3021system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
3022system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
3023system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
3024system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
3025system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
3026system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
3027system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
3028system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
3029system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
3030system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
3031system.iobus.pkt_count_system.bridge.master::total 122710 # Packet count per connected master and slave (bytes)
3032system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231342 # Packet count per connected master and slave (bytes)
3033system.iobus.pkt_count_system.realview.ide.dma::total 231342 # Packet count per connected master and slave (bytes)
3034system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
3035system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
3036system.iobus.pkt_count::total 354132 # Packet count per connected master and slave (bytes)
3037system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47796 # Cumulative packet size per connected master and slave (bytes)
3038system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
3039system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
3040system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
3041system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
3042system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
3043system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
3044system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
3045system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
3046system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
3047system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
3048system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
3049system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
3050system.iobus.pkt_size_system.bridge.master::total 155817 # Cumulative packet size per connected master and slave (bytes)
3051system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339384 # Cumulative packet size per connected master and slave (bytes)
3052system.iobus.pkt_size_system.realview.ide.dma::total 7339384 # Cumulative packet size per connected master and slave (bytes)
3053system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
3054system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
3055system.iobus.pkt_size::total 7497287 # Cumulative packet size per connected master and slave (bytes)
3056system.iobus.reqLayer0.occupancy 37041003 # Layer occupancy (ticks)
3057system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
3058system.iobus.reqLayer1.occupancy 9500 # Layer occupancy (ticks)
3059system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
3060system.iobus.reqLayer2.occupancy 331500 # Layer occupancy (ticks)
3061system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
3062system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks)
3063system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
3064system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks)
3065system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
3066system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks)
3067system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
3068system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
3069system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
3070system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks)
3071system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
3072system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks)
3073system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
3074system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks)
3075system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
3076system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
3077system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
3078system.iobus.reqLayer23.occupancy 24305002 # Layer occupancy (ticks)
3079system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
3080system.iobus.reqLayer24.occupancy 36394500 # Layer occupancy (ticks)
3081system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
3082system.iobus.reqLayer25.occupancy 570335330 # Layer occupancy (ticks)
3083system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
3084system.iobus.respLayer0.occupancy 92783000 # Layer occupancy (ticks)
3085system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
3086system.iobus.respLayer3.occupancy 148038000 # Layer occupancy (ticks)
3087system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
3088system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
3089system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
3090system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3091system.iocache.tags.replacements 115667 # number of replacements
3092system.iocache.tags.tagsinuse 11.289924 # Cycle average of tags in use
3093system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
3094system.iocache.tags.sampled_refs 115683 # Sample count of references to valid blocks.
3095system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
3096system.iocache.tags.warmup_cycle 9156457442000 # Cycle when the warmup percentage was hit.
3097system.iocache.tags.occ_blocks::realview.ethernet 7.417343 # Average occupied blocks per requestor
3098system.iocache.tags.occ_blocks::realview.ide 3.872581 # Average occupied blocks per requestor
3099system.iocache.tags.occ_percent::realview.ethernet 0.463584 # Average percentage of cache occupancy
3100system.iocache.tags.occ_percent::realview.ide 0.242036 # Average percentage of cache occupancy
3101system.iocache.tags.occ_percent::total 0.705620 # Average percentage of cache occupancy
3102system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
3103system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
3104system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
3105system.iocache.tags.tag_accesses 1041396 # Number of tag accesses
3106system.iocache.tags.data_accesses 1041396 # Number of data accesses
3107system.iocache.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3108system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
3109system.iocache.ReadReq_misses::realview.ide 8943 # number of ReadReq misses
3110system.iocache.ReadReq_misses::total 8980 # number of ReadReq misses
3111system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
3112system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
3113system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
3114system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
3115system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
3116system.iocache.demand_misses::realview.ide 115671 # number of demand (read+write) misses
3117system.iocache.demand_misses::total 115711 # number of demand (read+write) misses
3118system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
3119system.iocache.overall_misses::realview.ide 115671 # number of overall misses
3120system.iocache.overall_misses::total 115711 # number of overall misses
3121system.iocache.ReadReq_miss_latency::realview.ethernet 5200000 # number of ReadReq miss cycles
3122system.iocache.ReadReq_miss_latency::realview.ide 1878808543 # number of ReadReq miss cycles
3123system.iocache.ReadReq_miss_latency::total 1884008543 # number of ReadReq miss cycles
3124system.iocache.WriteReq_miss_latency::realview.ethernet 370000 # number of WriteReq miss cycles
3125system.iocache.WriteReq_miss_latency::total 370000 # number of WriteReq miss cycles
3126system.iocache.WriteLineReq_miss_latency::realview.ide 13080956787 # number of WriteLineReq miss cycles
3127system.iocache.WriteLineReq_miss_latency::total 13080956787 # number of WriteLineReq miss cycles
3128system.iocache.demand_miss_latency::realview.ethernet 5570000 # number of demand (read+write) miss cycles
3129system.iocache.demand_miss_latency::realview.ide 14959765330 # number of demand (read+write) miss cycles
3130system.iocache.demand_miss_latency::total 14965335330 # number of demand (read+write) miss cycles
3131system.iocache.overall_miss_latency::realview.ethernet 5570000 # number of overall miss cycles
3132system.iocache.overall_miss_latency::realview.ide 14959765330 # number of overall miss cycles
3133system.iocache.overall_miss_latency::total 14965335330 # number of overall miss cycles
3134system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
3135system.iocache.ReadReq_accesses::realview.ide 8943 # number of ReadReq accesses(hits+misses)
3136system.iocache.ReadReq_accesses::total 8980 # number of ReadReq accesses(hits+misses)
3137system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
3138system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
3139system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
3140system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
3141system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
3142system.iocache.demand_accesses::realview.ide 115671 # number of demand (read+write) accesses
3143system.iocache.demand_accesses::total 115711 # number of demand (read+write) accesses
3144system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
3145system.iocache.overall_accesses::realview.ide 115671 # number of overall (read+write) accesses
3146system.iocache.overall_accesses::total 115711 # number of overall (read+write) accesses
3147system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
3148system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
3149system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
3150system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
3151system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
3152system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
3153system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
3154system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
3155system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
3156system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
3157system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
3158system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
3159system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
3160system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541 # average ReadReq miss latency
3161system.iocache.ReadReq_avg_miss_latency::realview.ide 210087.056133 # average ReadReq miss latency
3162system.iocache.ReadReq_avg_miss_latency::total 209800.505902 # average ReadReq miss latency
3163system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123333.333333 # average WriteReq miss latency
3164system.iocache.WriteReq_avg_miss_latency::total 123333.333333 # average WriteReq miss latency
3165system.iocache.WriteLineReq_avg_miss_latency::realview.ide 122563.495868 # average WriteLineReq miss latency
3166system.iocache.WriteLineReq_avg_miss_latency::total 122563.495868 # average WriteLineReq miss latency
3167system.iocache.demand_avg_miss_latency::realview.ethernet 139250 # average overall miss latency
3168system.iocache.demand_avg_miss_latency::realview.ide 129330.301718 # average overall miss latency
3169system.iocache.demand_avg_miss_latency::total 129333.730847 # average overall miss latency
3170system.iocache.overall_avg_miss_latency::realview.ethernet 139250 # average overall miss latency
3171system.iocache.overall_avg_miss_latency::realview.ide 129330.301718 # average overall miss latency
3172system.iocache.overall_avg_miss_latency::total 129333.730847 # average overall miss latency
3173system.iocache.blocked_cycles::no_mshrs 43850 # number of cycles access was blocked
3174system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
3175system.iocache.blocked::no_mshrs 3467 # number of cycles access was blocked
3176system.iocache.blocked::no_targets 0 # number of cycles access was blocked
3177system.iocache.avg_blocked_cycles::no_mshrs 12.647822 # average number of cycles each access was blocked
3178system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3179system.iocache.writebacks::writebacks 106694 # number of writebacks
3180system.iocache.writebacks::total 106694 # number of writebacks
3181system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
3182system.iocache.ReadReq_mshr_misses::realview.ide 8943 # number of ReadReq MSHR misses
3183system.iocache.ReadReq_mshr_misses::total 8980 # number of ReadReq MSHR misses
3184system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
3185system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
3186system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
3187system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
3188system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
3189system.iocache.demand_mshr_misses::realview.ide 115671 # number of demand (read+write) MSHR misses
3190system.iocache.demand_mshr_misses::total 115711 # number of demand (read+write) MSHR misses
3191system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
3192system.iocache.overall_mshr_misses::realview.ide 115671 # number of overall MSHR misses
3193system.iocache.overall_mshr_misses::total 115711 # number of overall MSHR misses
3194system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3350000 # number of ReadReq MSHR miss cycles
3195system.iocache.ReadReq_mshr_miss_latency::realview.ide 1431658543 # number of ReadReq MSHR miss cycles
3196system.iocache.ReadReq_mshr_miss_latency::total 1435008543 # number of ReadReq MSHR miss cycles
3197system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 220000 # number of WriteReq MSHR miss cycles
3198system.iocache.WriteReq_mshr_miss_latency::total 220000 # number of WriteReq MSHR miss cycles
3199system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7738901569 # number of WriteLineReq MSHR miss cycles
3200system.iocache.WriteLineReq_mshr_miss_latency::total 7738901569 # number of WriteLineReq MSHR miss cycles
3201system.iocache.demand_mshr_miss_latency::realview.ethernet 3570000 # number of demand (read+write) MSHR miss cycles
3202system.iocache.demand_mshr_miss_latency::realview.ide 9170560112 # number of demand (read+write) MSHR miss cycles
3203system.iocache.demand_mshr_miss_latency::total 9174130112 # number of demand (read+write) MSHR miss cycles
3204system.iocache.overall_mshr_miss_latency::realview.ethernet 3570000 # number of overall MSHR miss cycles
3205system.iocache.overall_mshr_miss_latency::realview.ide 9170560112 # number of overall MSHR miss cycles
3206system.iocache.overall_mshr_miss_latency::total 9174130112 # number of overall MSHR miss cycles
3207system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
3208system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
3209system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
3210system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
3211system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
3212system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
3213system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
3214system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
3215system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
3216system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
3217system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
3218system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
3219system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
3220system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541 # average ReadReq mshr miss latency
3221system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 160087.056133 # average ReadReq mshr miss latency
3222system.iocache.ReadReq_avg_mshr_miss_latency::total 159800.505902 # average ReadReq mshr miss latency
3223system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73333.333333 # average WriteReq mshr miss latency
3224system.iocache.WriteReq_avg_mshr_miss_latency::total 73333.333333 # average WriteReq mshr miss latency
3225system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 72510.508667 # average WriteLineReq mshr miss latency
3226system.iocache.WriteLineReq_avg_mshr_miss_latency::total 72510.508667 # average WriteLineReq mshr miss latency
3227system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89250 # average overall mshr miss latency
3228system.iocache.demand_avg_mshr_miss_latency::realview.ide 79281.411175 # average overall mshr miss latency
3229system.iocache.demand_avg_mshr_miss_latency::total 79284.857205 # average overall mshr miss latency
3230system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89250 # average overall mshr miss latency
3231system.iocache.overall_avg_mshr_miss_latency::realview.ide 79281.411175 # average overall mshr miss latency
3232system.iocache.overall_avg_mshr_miss_latency::total 79284.857205 # average overall mshr miss latency
3233system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3234system.l2c.tags.replacements 1625787 # number of replacements
3235system.l2c.tags.tagsinuse 65181.204595 # Cycle average of tags in use
3236system.l2c.tags.total_refs 6817657 # Total number of references to valid blocks.
3237system.l2c.tags.sampled_refs 1687923 # Sample count of references to valid blocks.
3238system.l2c.tags.avg_refs 4.039081 # Average number of references to valid blocks.
3239system.l2c.tags.warmup_cycle 3083223500 # Cycle when the warmup percentage was hit.
3240system.l2c.tags.occ_blocks::writebacks 9617.868100 # Average occupied blocks per requestor
3241system.l2c.tags.occ_blocks::cpu0.dtb.walker 445.484302 # Average occupied blocks per requestor
3242system.l2c.tags.occ_blocks::cpu0.itb.walker 525.919749 # Average occupied blocks per requestor
3243system.l2c.tags.occ_blocks::cpu0.inst 4087.647415 # Average occupied blocks per requestor
3244system.l2c.tags.occ_blocks::cpu0.data 22210.879235 # Average occupied blocks per requestor
3245system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 20823.279726 # Average occupied blocks per requestor
3246system.l2c.tags.occ_blocks::cpu1.dtb.walker 29.752566 # Average occupied blocks per requestor
3247system.l2c.tags.occ_blocks::cpu1.itb.walker 32.095436 # Average occupied blocks per requestor
3248system.l2c.tags.occ_blocks::cpu1.inst 2691.005366 # Average occupied blocks per requestor
3249system.l2c.tags.occ_blocks::cpu1.data 3224.848807 # Average occupied blocks per requestor
3250system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1492.423894 # Average occupied blocks per requestor
3251system.l2c.tags.occ_percent::writebacks 0.146757 # Average percentage of cache occupancy
3252system.l2c.tags.occ_percent::cpu0.dtb.walker 0.006798 # Average percentage of cache occupancy
3253system.l2c.tags.occ_percent::cpu0.itb.walker 0.008025 # Average percentage of cache occupancy
3254system.l2c.tags.occ_percent::cpu0.inst 0.062373 # Average percentage of cache occupancy
3255system.l2c.tags.occ_percent::cpu0.data 0.338911 # Average percentage of cache occupancy
3256system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.317738 # Average percentage of cache occupancy
3257system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000454 # Average percentage of cache occupancy
3258system.l2c.tags.occ_percent::cpu1.itb.walker 0.000490 # Average percentage of cache occupancy
3259system.l2c.tags.occ_percent::cpu1.inst 0.041061 # Average percentage of cache occupancy
3260system.l2c.tags.occ_percent::cpu1.data 0.049207 # Average percentage of cache occupancy
3261system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022773 # Average percentage of cache occupancy
3262system.l2c.tags.occ_percent::total 0.994586 # Average percentage of cache occupancy
3263system.l2c.tags.occ_task_id_blocks::1022 12119 # Occupied blocks per task id
3264system.l2c.tags.occ_task_id_blocks::1023 287 # Occupied blocks per task id
3265system.l2c.tags.occ_task_id_blocks::1024 49730 # Occupied blocks per task id
3266system.l2c.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id
3267system.l2c.tags.age_task_id_blocks_1022::2 1349 # Occupied blocks per task id
3268system.l2c.tags.age_task_id_blocks_1022::3 918 # Occupied blocks per task id
3269system.l2c.tags.age_task_id_blocks_1022::4 9840 # Occupied blocks per task id
3270system.l2c.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
3271system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
3272system.l2c.tags.age_task_id_blocks_1023::4 283 # Occupied blocks per task id
3273system.l2c.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
3274system.l2c.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id
3275system.l2c.tags.age_task_id_blocks_1024::2 2201 # Occupied blocks per task id
3276system.l2c.tags.age_task_id_blocks_1024::3 4435 # Occupied blocks per task id
3277system.l2c.tags.age_task_id_blocks_1024::4 42789 # Occupied blocks per task id
3278system.l2c.tags.occ_task_id_percent::1022 0.184921 # Percentage of cache occupancy per task id
3279system.l2c.tags.occ_task_id_percent::1023 0.004379 # Percentage of cache occupancy per task id
3280system.l2c.tags.occ_task_id_percent::1024 0.758820 # Percentage of cache occupancy per task id
3281system.l2c.tags.tag_accesses 77430161 # Number of tag accesses
3282system.l2c.tags.data_accesses 77430161 # Number of data accesses
3283system.l2c.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3284system.l2c.WritebackDirty_hits::writebacks 2884653 # number of WritebackDirty hits
3285system.l2c.WritebackDirty_hits::total 2884653 # number of WritebackDirty hits
3286system.l2c.UpgradeReq_hits::cpu0.data 199415 # number of UpgradeReq hits
3287system.l2c.UpgradeReq_hits::cpu1.data 166641 # number of UpgradeReq hits
3288system.l2c.UpgradeReq_hits::total 366056 # number of UpgradeReq hits
3289system.l2c.SCUpgradeReq_hits::cpu0.data 54285 # number of SCUpgradeReq hits
3290system.l2c.SCUpgradeReq_hits::cpu1.data 48308 # number of SCUpgradeReq hits
3291system.l2c.SCUpgradeReq_hits::total 102593 # number of SCUpgradeReq hits
3292system.l2c.ReadExReq_hits::cpu0.data 52113 # number of ReadExReq hits
3293system.l2c.ReadExReq_hits::cpu1.data 55927 # number of ReadExReq hits
3294system.l2c.ReadExReq_hits::total 108040 # number of ReadExReq hits
3295system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 12524 # number of ReadSharedReq hits
3296system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4903 # number of ReadSharedReq hits
3297system.l2c.ReadSharedReq_hits::cpu0.inst 523305 # number of ReadSharedReq hits
3298system.l2c.ReadSharedReq_hits::cpu0.data 612159 # number of ReadSharedReq hits
3299system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 287889 # number of ReadSharedReq hits
3300system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 14056 # number of ReadSharedReq hits
3301system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5296 # number of ReadSharedReq hits
3302system.l2c.ReadSharedReq_hits::cpu1.inst 496370 # number of ReadSharedReq hits
3303system.l2c.ReadSharedReq_hits::cpu1.data 569933 # number of ReadSharedReq hits
3304system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 304905 # number of ReadSharedReq hits
3305system.l2c.ReadSharedReq_hits::total 2831340 # number of ReadSharedReq hits
3306system.l2c.InvalidateReq_hits::cpu0.data 116676 # number of InvalidateReq hits
3307system.l2c.InvalidateReq_hits::cpu1.data 127973 # number of InvalidateReq hits
3308system.l2c.InvalidateReq_hits::total 244649 # number of InvalidateReq hits
3309system.l2c.demand_hits::cpu0.dtb.walker 12524 # number of demand (read+write) hits
3310system.l2c.demand_hits::cpu0.itb.walker 4903 # number of demand (read+write) hits
3311system.l2c.demand_hits::cpu0.inst 523305 # number of demand (read+write) hits
3312system.l2c.demand_hits::cpu0.data 664272 # number of demand (read+write) hits
3313system.l2c.demand_hits::cpu0.l2cache.prefetcher 287889 # number of demand (read+write) hits
3314system.l2c.demand_hits::cpu1.dtb.walker 14056 # number of demand (read+write) hits
3315system.l2c.demand_hits::cpu1.itb.walker 5296 # number of demand (read+write) hits
3316system.l2c.demand_hits::cpu1.inst 496370 # number of demand (read+write) hits
3317system.l2c.demand_hits::cpu1.data 625860 # number of demand (read+write) hits
3318system.l2c.demand_hits::cpu1.l2cache.prefetcher 304905 # number of demand (read+write) hits
3319system.l2c.demand_hits::total 2939380 # number of demand (read+write) hits
3320system.l2c.overall_hits::cpu0.dtb.walker 12524 # number of overall hits
3321system.l2c.overall_hits::cpu0.itb.walker 4903 # number of overall hits
3322system.l2c.overall_hits::cpu0.inst 523305 # number of overall hits
3323system.l2c.overall_hits::cpu0.data 664272 # number of overall hits
3324system.l2c.overall_hits::cpu0.l2cache.prefetcher 287889 # number of overall hits
3325system.l2c.overall_hits::cpu1.dtb.walker 14056 # number of overall hits
3326system.l2c.overall_hits::cpu1.itb.walker 5296 # number of overall hits
3327system.l2c.overall_hits::cpu1.inst 496370 # number of overall hits
3328system.l2c.overall_hits::cpu1.data 625860 # number of overall hits
3329system.l2c.overall_hits::cpu1.l2cache.prefetcher 304905 # number of overall hits
3330system.l2c.overall_hits::total 2939380 # number of overall hits
3331system.l2c.UpgradeReq_misses::cpu0.data 23367 # number of UpgradeReq misses
3332system.l2c.UpgradeReq_misses::cpu1.data 23265 # number of UpgradeReq misses
3333system.l2c.UpgradeReq_misses::total 46632 # number of UpgradeReq misses
3334system.l2c.SCUpgradeReq_misses::cpu0.data 687 # number of SCUpgradeReq misses
3335system.l2c.SCUpgradeReq_misses::cpu1.data 824 # number of SCUpgradeReq misses
3336system.l2c.SCUpgradeReq_misses::total 1511 # number of SCUpgradeReq misses
3337system.l2c.ReadExReq_misses::cpu0.data 90180 # number of ReadExReq misses
3338system.l2c.ReadExReq_misses::cpu1.data 49097 # number of ReadExReq misses
3339system.l2c.ReadExReq_misses::total 139277 # number of ReadExReq misses
3340system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3479 # number of ReadSharedReq misses
3341system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3368 # number of ReadSharedReq misses
3342system.l2c.ReadSharedReq_misses::cpu0.inst 64819 # number of ReadSharedReq misses
3343system.l2c.ReadSharedReq_misses::cpu0.data 175048 # number of ReadSharedReq misses
3344system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 338569 # number of ReadSharedReq misses
3345system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1814 # number of ReadSharedReq misses
3346system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1250 # number of ReadSharedReq misses
3347system.l2c.ReadSharedReq_misses::cpu1.inst 46649 # number of ReadSharedReq misses
3348system.l2c.ReadSharedReq_misses::cpu1.data 114016 # number of ReadSharedReq misses
3349system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 201392 # number of ReadSharedReq misses
3350system.l2c.ReadSharedReq_misses::total 950404 # number of ReadSharedReq misses
3351system.l2c.InvalidateReq_misses::cpu0.data 450671 # number of InvalidateReq misses
3352system.l2c.InvalidateReq_misses::cpu1.data 82488 # number of InvalidateReq misses
3353system.l2c.InvalidateReq_misses::total 533159 # number of InvalidateReq misses
3354system.l2c.demand_misses::cpu0.dtb.walker 3479 # number of demand (read+write) misses
3355system.l2c.demand_misses::cpu0.itb.walker 3368 # number of demand (read+write) misses
3356system.l2c.demand_misses::cpu0.inst 64819 # number of demand (read+write) misses
3357system.l2c.demand_misses::cpu0.data 265228 # number of demand (read+write) misses
3358system.l2c.demand_misses::cpu0.l2cache.prefetcher 338569 # number of demand (read+write) misses
3359system.l2c.demand_misses::cpu1.dtb.walker 1814 # number of demand (read+write) misses
3360system.l2c.demand_misses::cpu1.itb.walker 1250 # number of demand (read+write) misses
3361system.l2c.demand_misses::cpu1.inst 46649 # number of demand (read+write) misses
3362system.l2c.demand_misses::cpu1.data 163113 # number of demand (read+write) misses
3363system.l2c.demand_misses::cpu1.l2cache.prefetcher 201392 # number of demand (read+write) misses
3364system.l2c.demand_misses::total 1089681 # number of demand (read+write) misses
3365system.l2c.overall_misses::cpu0.dtb.walker 3479 # number of overall misses
3366system.l2c.overall_misses::cpu0.itb.walker 3368 # number of overall misses
3367system.l2c.overall_misses::cpu0.inst 64819 # number of overall misses
3368system.l2c.overall_misses::cpu0.data 265228 # number of overall misses
3369system.l2c.overall_misses::cpu0.l2cache.prefetcher 338569 # number of overall misses
3370system.l2c.overall_misses::cpu1.dtb.walker 1814 # number of overall misses
3371system.l2c.overall_misses::cpu1.itb.walker 1250 # number of overall misses
3372system.l2c.overall_misses::cpu1.inst 46649 # number of overall misses
3373system.l2c.overall_misses::cpu1.data 163113 # number of overall misses
3374system.l2c.overall_misses::cpu1.l2cache.prefetcher 201392 # number of overall misses
3375system.l2c.overall_misses::total 1089681 # number of overall misses
3376system.l2c.UpgradeReq_miss_latency::cpu0.data 136803000 # number of UpgradeReq miss cycles
3377system.l2c.UpgradeReq_miss_latency::cpu1.data 150683000 # number of UpgradeReq miss cycles
3378system.l2c.UpgradeReq_miss_latency::total 287486000 # number of UpgradeReq miss cycles
3379system.l2c.SCUpgradeReq_miss_latency::cpu0.data 9622000 # number of SCUpgradeReq miss cycles
3380system.l2c.SCUpgradeReq_miss_latency::cpu1.data 7084500 # number of SCUpgradeReq miss cycles
3381system.l2c.SCUpgradeReq_miss_latency::total 16706500 # number of SCUpgradeReq miss cycles
3382system.l2c.ReadExReq_miss_latency::cpu0.data 9842771994 # number of ReadExReq miss cycles
3383system.l2c.ReadExReq_miss_latency::cpu1.data 5304657999 # number of ReadExReq miss cycles
3384system.l2c.ReadExReq_miss_latency::total 15147429993 # number of ReadExReq miss cycles
3385system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 352314500 # number of ReadSharedReq miss cycles
3386system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 351549500 # number of ReadSharedReq miss cycles
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3389system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 51686460606 # number of ReadSharedReq miss cycles
3390system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 196164500 # number of ReadSharedReq miss cycles
3391system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 138775500 # number of ReadSharedReq miss cycles
3392system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5424777500 # number of ReadSharedReq miss cycles
3393system.l2c.ReadSharedReq_miss_latency::cpu1.data 13175715998 # number of ReadSharedReq miss cycles
3394system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 30642096870 # number of ReadSharedReq miss cycles
3395system.l2c.ReadSharedReq_miss_latency::total 128734883472 # number of ReadSharedReq miss cycles
3396system.l2c.demand_miss_latency::cpu0.dtb.walker 352314500 # number of demand (read+write) miss cycles
3397system.l2c.demand_miss_latency::cpu0.itb.walker 351549500 # number of demand (read+write) miss cycles
3398system.l2c.demand_miss_latency::cpu0.inst 7169242500 # number of demand (read+write) miss cycles
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3400system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 51686460606 # number of demand (read+write) miss cycles
3401system.l2c.demand_miss_latency::cpu1.dtb.walker 196164500 # number of demand (read+write) miss cycles
3402system.l2c.demand_miss_latency::cpu1.itb.walker 138775500 # number of demand (read+write) miss cycles
3403system.l2c.demand_miss_latency::cpu1.inst 5424777500 # number of demand (read+write) miss cycles
3404system.l2c.demand_miss_latency::cpu1.data 18480373997 # number of demand (read+write) miss cycles
3405system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 30642096870 # number of demand (read+write) miss cycles
3406system.l2c.demand_miss_latency::total 143882313465 # number of demand (read+write) miss cycles
3407system.l2c.overall_miss_latency::cpu0.dtb.walker 352314500 # number of overall miss cycles
3408system.l2c.overall_miss_latency::cpu0.itb.walker 351549500 # number of overall miss cycles
3409system.l2c.overall_miss_latency::cpu0.inst 7169242500 # number of overall miss cycles
3410system.l2c.overall_miss_latency::cpu0.data 29440557992 # number of overall miss cycles
3411system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 51686460606 # number of overall miss cycles
3412system.l2c.overall_miss_latency::cpu1.dtb.walker 196164500 # number of overall miss cycles
3413system.l2c.overall_miss_latency::cpu1.itb.walker 138775500 # number of overall miss cycles
3414system.l2c.overall_miss_latency::cpu1.inst 5424777500 # number of overall miss cycles
3415system.l2c.overall_miss_latency::cpu1.data 18480373997 # number of overall miss cycles
3416system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 30642096870 # number of overall miss cycles
3417system.l2c.overall_miss_latency::total 143882313465 # number of overall miss cycles
3418system.l2c.WritebackDirty_accesses::writebacks 2884653 # number of WritebackDirty accesses(hits+misses)
3419system.l2c.WritebackDirty_accesses::total 2884653 # number of WritebackDirty accesses(hits+misses)
3420system.l2c.UpgradeReq_accesses::cpu0.data 222782 # number of UpgradeReq accesses(hits+misses)
3421system.l2c.UpgradeReq_accesses::cpu1.data 189906 # number of UpgradeReq accesses(hits+misses)
3422system.l2c.UpgradeReq_accesses::total 412688 # number of UpgradeReq accesses(hits+misses)
3423system.l2c.SCUpgradeReq_accesses::cpu0.data 54972 # number of SCUpgradeReq accesses(hits+misses)
3424system.l2c.SCUpgradeReq_accesses::cpu1.data 49132 # number of SCUpgradeReq accesses(hits+misses)
3425system.l2c.SCUpgradeReq_accesses::total 104104 # number of SCUpgradeReq accesses(hits+misses)
3426system.l2c.ReadExReq_accesses::cpu0.data 142293 # number of ReadExReq accesses(hits+misses)
3427system.l2c.ReadExReq_accesses::cpu1.data 105024 # number of ReadExReq accesses(hits+misses)
3428system.l2c.ReadExReq_accesses::total 247317 # number of ReadExReq accesses(hits+misses)
3429system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 16003 # number of ReadSharedReq accesses(hits+misses)
3430system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 8271 # number of ReadSharedReq accesses(hits+misses)
3431system.l2c.ReadSharedReq_accesses::cpu0.inst 588124 # number of ReadSharedReq accesses(hits+misses)
3432system.l2c.ReadSharedReq_accesses::cpu0.data 787207 # number of ReadSharedReq accesses(hits+misses)
3433system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 626458 # number of ReadSharedReq accesses(hits+misses)
3434system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 15870 # number of ReadSharedReq accesses(hits+misses)
3435system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6546 # number of ReadSharedReq accesses(hits+misses)
3436system.l2c.ReadSharedReq_accesses::cpu1.inst 543019 # number of ReadSharedReq accesses(hits+misses)
3437system.l2c.ReadSharedReq_accesses::cpu1.data 683949 # number of ReadSharedReq accesses(hits+misses)
3438system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 506297 # number of ReadSharedReq accesses(hits+misses)
3439system.l2c.ReadSharedReq_accesses::total 3781744 # number of ReadSharedReq accesses(hits+misses)
3440system.l2c.InvalidateReq_accesses::cpu0.data 567347 # number of InvalidateReq accesses(hits+misses)
3441system.l2c.InvalidateReq_accesses::cpu1.data 210461 # number of InvalidateReq accesses(hits+misses)
3442system.l2c.InvalidateReq_accesses::total 777808 # number of InvalidateReq accesses(hits+misses)
3443system.l2c.demand_accesses::cpu0.dtb.walker 16003 # number of demand (read+write) accesses
3444system.l2c.demand_accesses::cpu0.itb.walker 8271 # number of demand (read+write) accesses
3445system.l2c.demand_accesses::cpu0.inst 588124 # number of demand (read+write) accesses
3446system.l2c.demand_accesses::cpu0.data 929500 # number of demand (read+write) accesses
3447system.l2c.demand_accesses::cpu0.l2cache.prefetcher 626458 # number of demand (read+write) accesses
3448system.l2c.demand_accesses::cpu1.dtb.walker 15870 # number of demand (read+write) accesses
3449system.l2c.demand_accesses::cpu1.itb.walker 6546 # number of demand (read+write) accesses
3450system.l2c.demand_accesses::cpu1.inst 543019 # number of demand (read+write) accesses
3451system.l2c.demand_accesses::cpu1.data 788973 # number of demand (read+write) accesses
3452system.l2c.demand_accesses::cpu1.l2cache.prefetcher 506297 # number of demand (read+write) accesses
3453system.l2c.demand_accesses::total 4029061 # number of demand (read+write) accesses
3454system.l2c.overall_accesses::cpu0.dtb.walker 16003 # number of overall (read+write) accesses
3455system.l2c.overall_accesses::cpu0.itb.walker 8271 # number of overall (read+write) accesses
3456system.l2c.overall_accesses::cpu0.inst 588124 # number of overall (read+write) accesses
3457system.l2c.overall_accesses::cpu0.data 929500 # number of overall (read+write) accesses
3458system.l2c.overall_accesses::cpu0.l2cache.prefetcher 626458 # number of overall (read+write) accesses
3459system.l2c.overall_accesses::cpu1.dtb.walker 15870 # number of overall (read+write) accesses
3460system.l2c.overall_accesses::cpu1.itb.walker 6546 # number of overall (read+write) accesses
3461system.l2c.overall_accesses::cpu1.inst 543019 # number of overall (read+write) accesses
3462system.l2c.overall_accesses::cpu1.data 788973 # number of overall (read+write) accesses
3463system.l2c.overall_accesses::cpu1.l2cache.prefetcher 506297 # number of overall (read+write) accesses
3464system.l2c.overall_accesses::total 4029061 # number of overall (read+write) accesses
3465system.l2c.UpgradeReq_miss_rate::cpu0.data 0.104887 # miss rate for UpgradeReq accesses
3466system.l2c.UpgradeReq_miss_rate::cpu1.data 0.122508 # miss rate for UpgradeReq accesses
3467system.l2c.UpgradeReq_miss_rate::total 0.112996 # miss rate for UpgradeReq accesses
3468system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.012497 # miss rate for SCUpgradeReq accesses
3469system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.016771 # miss rate for SCUpgradeReq accesses
3470system.l2c.SCUpgradeReq_miss_rate::total 0.014514 # miss rate for SCUpgradeReq accesses
3471system.l2c.ReadExReq_miss_rate::cpu0.data 0.633763 # miss rate for ReadExReq accesses
3472system.l2c.ReadExReq_miss_rate::cpu1.data 0.467484 # miss rate for ReadExReq accesses
3473system.l2c.ReadExReq_miss_rate::total 0.563152 # miss rate for ReadExReq accesses
3474system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.217397 # miss rate for ReadSharedReq accesses
3475system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.407206 # miss rate for ReadSharedReq accesses
3476system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.110213 # miss rate for ReadSharedReq accesses
3477system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.222366 # miss rate for ReadSharedReq accesses
3478system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.540450 # miss rate for ReadSharedReq accesses
3479system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.114304 # miss rate for ReadSharedReq accesses
3480system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.190956 # miss rate for ReadSharedReq accesses
3481system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.085907 # miss rate for ReadSharedReq accesses
3482system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.166702 # miss rate for ReadSharedReq accesses
3483system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.397774 # miss rate for ReadSharedReq accesses
3484system.l2c.ReadSharedReq_miss_rate::total 0.251314 # miss rate for ReadSharedReq accesses
3485system.l2c.InvalidateReq_miss_rate::cpu0.data 0.794348 # miss rate for InvalidateReq accesses
3486system.l2c.InvalidateReq_miss_rate::cpu1.data 0.391940 # miss rate for InvalidateReq accesses
3487system.l2c.InvalidateReq_miss_rate::total 0.685464 # miss rate for InvalidateReq accesses
3488system.l2c.demand_miss_rate::cpu0.dtb.walker 0.217397 # miss rate for demand accesses
3489system.l2c.demand_miss_rate::cpu0.itb.walker 0.407206 # miss rate for demand accesses
3490system.l2c.demand_miss_rate::cpu0.inst 0.110213 # miss rate for demand accesses
3491system.l2c.demand_miss_rate::cpu0.data 0.285345 # miss rate for demand accesses
3492system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.540450 # miss rate for demand accesses
3493system.l2c.demand_miss_rate::cpu1.dtb.walker 0.114304 # miss rate for demand accesses
3494system.l2c.demand_miss_rate::cpu1.itb.walker 0.190956 # miss rate for demand accesses
3495system.l2c.demand_miss_rate::cpu1.inst 0.085907 # miss rate for demand accesses
3496system.l2c.demand_miss_rate::cpu1.data 0.206741 # miss rate for demand accesses
3497system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.397774 # miss rate for demand accesses
3498system.l2c.demand_miss_rate::total 0.270455 # miss rate for demand accesses
3499system.l2c.overall_miss_rate::cpu0.dtb.walker 0.217397 # miss rate for overall accesses
3500system.l2c.overall_miss_rate::cpu0.itb.walker 0.407206 # miss rate for overall accesses
3501system.l2c.overall_miss_rate::cpu0.inst 0.110213 # miss rate for overall accesses
3502system.l2c.overall_miss_rate::cpu0.data 0.285345 # miss rate for overall accesses
3503system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.540450 # miss rate for overall accesses
3504system.l2c.overall_miss_rate::cpu1.dtb.walker 0.114304 # miss rate for overall accesses
3505system.l2c.overall_miss_rate::cpu1.itb.walker 0.190956 # miss rate for overall accesses
3506system.l2c.overall_miss_rate::cpu1.inst 0.085907 # miss rate for overall accesses
3507system.l2c.overall_miss_rate::cpu1.data 0.206741 # miss rate for overall accesses
3508system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.397774 # miss rate for overall accesses
3509system.l2c.overall_miss_rate::total 0.270455 # miss rate for overall accesses
3510system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5854.538452 # average UpgradeReq miss latency
3511system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6476.810660 # average UpgradeReq miss latency
3512system.l2c.UpgradeReq_avg_miss_latency::total 6164.993996 # average UpgradeReq miss latency
3513system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14005.822416 # average SCUpgradeReq miss latency
3514system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 8597.694175 # average SCUpgradeReq miss latency
3515system.l2c.SCUpgradeReq_avg_miss_latency::total 11056.585043 # average SCUpgradeReq miss latency
3516system.l2c.ReadExReq_avg_miss_latency::cpu0.data 109145.841583 # average ReadExReq miss latency
3517system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108044.442614 # average ReadExReq miss latency
3518system.l2c.ReadExReq_avg_miss_latency::total 108757.583758 # average ReadExReq miss latency
3519system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 101268.899109 # average ReadSharedReq miss latency
3520system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 104379.305226 # average ReadSharedReq miss latency
3521system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 110604.028140 # average ReadSharedReq miss latency
3522system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 111956.640453 # average ReadSharedReq miss latency
3523system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 152661.527210 # average ReadSharedReq miss latency
3524system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 108139.195149 # average ReadSharedReq miss latency
3525system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 111020.400000 # average ReadSharedReq miss latency
3526system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 116289.255933 # average ReadSharedReq miss latency
3527system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 115560.237142 # average ReadSharedReq miss latency
3528system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 152151.509842 # average ReadSharedReq miss latency
3529system.l2c.ReadSharedReq_avg_miss_latency::total 135452.800569 # average ReadSharedReq miss latency
3530system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 101268.899109 # average overall miss latency
3531system.l2c.demand_avg_miss_latency::cpu0.itb.walker 104379.305226 # average overall miss latency
3532system.l2c.demand_avg_miss_latency::cpu0.inst 110604.028140 # average overall miss latency
3533system.l2c.demand_avg_miss_latency::cpu0.data 111000.942555 # average overall miss latency
3534system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 152661.527210 # average overall miss latency
3535system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 108139.195149 # average overall miss latency
3536system.l2c.demand_avg_miss_latency::cpu1.itb.walker 111020.400000 # average overall miss latency
3537system.l2c.demand_avg_miss_latency::cpu1.inst 116289.255933 # average overall miss latency
3538system.l2c.demand_avg_miss_latency::cpu1.data 113297.983588 # average overall miss latency
3539system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 152151.509842 # average overall miss latency
3540system.l2c.demand_avg_miss_latency::total 132040.765568 # average overall miss latency
3541system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 101268.899109 # average overall miss latency
3542system.l2c.overall_avg_miss_latency::cpu0.itb.walker 104379.305226 # average overall miss latency
3543system.l2c.overall_avg_miss_latency::cpu0.inst 110604.028140 # average overall miss latency
3544system.l2c.overall_avg_miss_latency::cpu0.data 111000.942555 # average overall miss latency
3545system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 152661.527210 # average overall miss latency
3546system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 108139.195149 # average overall miss latency
3547system.l2c.overall_avg_miss_latency::cpu1.itb.walker 111020.400000 # average overall miss latency
3548system.l2c.overall_avg_miss_latency::cpu1.inst 116289.255933 # average overall miss latency
3549system.l2c.overall_avg_miss_latency::cpu1.data 113297.983588 # average overall miss latency
3550system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 152151.509842 # average overall miss latency
3551system.l2c.overall_avg_miss_latency::total 132040.765568 # average overall miss latency
3552system.l2c.blocked_cycles::no_mshrs 7046 # number of cycles access was blocked
3553system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
3554system.l2c.blocked::no_mshrs 62 # number of cycles access was blocked
3555system.l2c.blocked::no_targets 0 # number of cycles access was blocked
3556system.l2c.avg_blocked_cycles::no_mshrs 113.645161 # average number of cycles each access was blocked
3557system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3558system.l2c.writebacks::writebacks 1244548 # number of writebacks
3559system.l2c.writebacks::total 1244548 # number of writebacks
3560system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 102 # number of ReadSharedReq MSHR hits
3561system.l2c.ReadSharedReq_mshr_hits::cpu0.data 15 # number of ReadSharedReq MSHR hits
3562system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 118 # number of ReadSharedReq MSHR hits
3563system.l2c.ReadSharedReq_mshr_hits::cpu1.data 19 # number of ReadSharedReq MSHR hits
3564system.l2c.ReadSharedReq_mshr_hits::total 254 # number of ReadSharedReq MSHR hits
3565system.l2c.demand_mshr_hits::cpu0.inst 102 # number of demand (read+write) MSHR hits
3566system.l2c.demand_mshr_hits::cpu0.data 15 # number of demand (read+write) MSHR hits
3567system.l2c.demand_mshr_hits::cpu1.inst 118 # number of demand (read+write) MSHR hits
3568system.l2c.demand_mshr_hits::cpu1.data 19 # number of demand (read+write) MSHR hits
3569system.l2c.demand_mshr_hits::total 254 # number of demand (read+write) MSHR hits
3570system.l2c.overall_mshr_hits::cpu0.inst 102 # number of overall MSHR hits
3571system.l2c.overall_mshr_hits::cpu0.data 15 # number of overall MSHR hits
3572system.l2c.overall_mshr_hits::cpu1.inst 118 # number of overall MSHR hits
3573system.l2c.overall_mshr_hits::cpu1.data 19 # number of overall MSHR hits
3574system.l2c.overall_mshr_hits::total 254 # number of overall MSHR hits
3575system.l2c.CleanEvict_mshr_misses::writebacks 67228 # number of CleanEvict MSHR misses
3576system.l2c.CleanEvict_mshr_misses::total 67228 # number of CleanEvict MSHR misses
3577system.l2c.UpgradeReq_mshr_misses::cpu0.data 23367 # number of UpgradeReq MSHR misses
3578system.l2c.UpgradeReq_mshr_misses::cpu1.data 23265 # number of UpgradeReq MSHR misses
3579system.l2c.UpgradeReq_mshr_misses::total 46632 # number of UpgradeReq MSHR misses
3580system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 687 # number of SCUpgradeReq MSHR misses
3581system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 824 # number of SCUpgradeReq MSHR misses
3582system.l2c.SCUpgradeReq_mshr_misses::total 1511 # number of SCUpgradeReq MSHR misses
3583system.l2c.ReadExReq_mshr_misses::cpu0.data 90180 # number of ReadExReq MSHR misses
3584system.l2c.ReadExReq_mshr_misses::cpu1.data 49097 # number of ReadExReq MSHR misses
3585system.l2c.ReadExReq_mshr_misses::total 139277 # number of ReadExReq MSHR misses
3586system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 3479 # number of ReadSharedReq MSHR misses
3587system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3368 # number of ReadSharedReq MSHR misses
3588system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 64717 # number of ReadSharedReq MSHR misses
3589system.l2c.ReadSharedReq_mshr_misses::cpu0.data 175033 # number of ReadSharedReq MSHR misses
3590system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 338569 # number of ReadSharedReq MSHR misses
3591system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1814 # number of ReadSharedReq MSHR misses
3592system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1250 # number of ReadSharedReq MSHR misses
3593system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 46531 # number of ReadSharedReq MSHR misses
3594system.l2c.ReadSharedReq_mshr_misses::cpu1.data 113997 # number of ReadSharedReq MSHR misses
3595system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 201392 # number of ReadSharedReq MSHR misses
3596system.l2c.ReadSharedReq_mshr_misses::total 950150 # number of ReadSharedReq MSHR misses
3597system.l2c.InvalidateReq_mshr_misses::cpu0.data 450671 # number of InvalidateReq MSHR misses
3598system.l2c.InvalidateReq_mshr_misses::cpu1.data 82488 # number of InvalidateReq MSHR misses
3599system.l2c.InvalidateReq_mshr_misses::total 533159 # number of InvalidateReq MSHR misses
3600system.l2c.demand_mshr_misses::cpu0.dtb.walker 3479 # number of demand (read+write) MSHR misses
3601system.l2c.demand_mshr_misses::cpu0.itb.walker 3368 # number of demand (read+write) MSHR misses
3602system.l2c.demand_mshr_misses::cpu0.inst 64717 # number of demand (read+write) MSHR misses
3603system.l2c.demand_mshr_misses::cpu0.data 265213 # number of demand (read+write) MSHR misses
3604system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 338569 # number of demand (read+write) MSHR misses
3605system.l2c.demand_mshr_misses::cpu1.dtb.walker 1814 # number of demand (read+write) MSHR misses
3606system.l2c.demand_mshr_misses::cpu1.itb.walker 1250 # number of demand (read+write) MSHR misses
3607system.l2c.demand_mshr_misses::cpu1.inst 46531 # number of demand (read+write) MSHR misses
3608system.l2c.demand_mshr_misses::cpu1.data 163094 # number of demand (read+write) MSHR misses
3609system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 201392 # number of demand (read+write) MSHR misses
3610system.l2c.demand_mshr_misses::total 1089427 # number of demand (read+write) MSHR misses
3611system.l2c.overall_mshr_misses::cpu0.dtb.walker 3479 # number of overall MSHR misses
3612system.l2c.overall_mshr_misses::cpu0.itb.walker 3368 # number of overall MSHR misses
3613system.l2c.overall_mshr_misses::cpu0.inst 64717 # number of overall MSHR misses
3614system.l2c.overall_mshr_misses::cpu0.data 265213 # number of overall MSHR misses
3615system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 338569 # number of overall MSHR misses
3616system.l2c.overall_mshr_misses::cpu1.dtb.walker 1814 # number of overall MSHR misses
3617system.l2c.overall_mshr_misses::cpu1.itb.walker 1250 # number of overall MSHR misses
3618system.l2c.overall_mshr_misses::cpu1.inst 46531 # number of overall MSHR misses
3619system.l2c.overall_mshr_misses::cpu1.data 163094 # number of overall MSHR misses
3620system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 201392 # number of overall MSHR misses
3621system.l2c.overall_mshr_misses::total 1089427 # number of overall MSHR misses
3622system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
3623system.l2c.ReadReq_mshr_uncacheable::cpu0.data 29615 # number of ReadReq MSHR uncacheable
3624system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
3625system.l2c.ReadReq_mshr_uncacheable::cpu1.data 8869 # number of ReadReq MSHR uncacheable
3626system.l2c.ReadReq_mshr_uncacheable::total 59844 # number of ReadReq MSHR uncacheable
3627system.l2c.WriteReq_mshr_uncacheable::cpu0.data 29691 # number of WriteReq MSHR uncacheable
3628system.l2c.WriteReq_mshr_uncacheable::cpu1.data 8695 # number of WriteReq MSHR uncacheable
3629system.l2c.WriteReq_mshr_uncacheable::total 38386 # number of WriteReq MSHR uncacheable
3630system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
3631system.l2c.overall_mshr_uncacheable_misses::cpu0.data 59306 # number of overall MSHR uncacheable misses
3632system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
3633system.l2c.overall_mshr_uncacheable_misses::cpu1.data 17564 # number of overall MSHR uncacheable misses
3634system.l2c.overall_mshr_uncacheable_misses::total 98230 # number of overall MSHR uncacheable misses
3635system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 466632500 # number of UpgradeReq MSHR miss cycles
3636system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 483108499 # number of UpgradeReq MSHR miss cycles
3637system.l2c.UpgradeReq_mshr_miss_latency::total 949740999 # number of UpgradeReq MSHR miss cycles
3638system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16616499 # number of SCUpgradeReq MSHR miss cycles
3639system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20367500 # number of SCUpgradeReq MSHR miss cycles
3640system.l2c.SCUpgradeReq_mshr_miss_latency::total 36983999 # number of SCUpgradeReq MSHR miss cycles
3641system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8940824795 # number of ReadExReq MSHR miss cycles
3642system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4813505389 # number of ReadExReq MSHR miss cycles
3643system.l2c.ReadExReq_mshr_miss_latency::total 13754330184 # number of ReadExReq MSHR miss cycles
3644system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 317523502 # number of ReadSharedReq MSHR miss cycles
3645system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 317869500 # number of ReadSharedReq MSHR miss cycles
3646system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6512407062 # number of ReadSharedReq MSHR miss cycles
3647system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17845292687 # number of ReadSharedReq MSHR miss cycles
3648system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 48300635417 # number of ReadSharedReq MSHR miss cycles
3649system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 178023502 # number of ReadSharedReq MSHR miss cycles
3650system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 126275001 # number of ReadSharedReq MSHR miss cycles
3651system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4948966536 # number of ReadSharedReq MSHR miss cycles
3652system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 12033347692 # number of ReadSharedReq MSHR miss cycles
3653system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 28627972330 # number of ReadSharedReq MSHR miss cycles
3654system.l2c.ReadSharedReq_mshr_miss_latency::total 119208313229 # number of ReadSharedReq MSHR miss cycles
3655system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 11145696799 # number of InvalidateReq MSHR miss cycles
3656system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1615953000 # number of InvalidateReq MSHR miss cycles
3657system.l2c.InvalidateReq_mshr_miss_latency::total 12761649799 # number of InvalidateReq MSHR miss cycles
3658system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 317523502 # number of demand (read+write) MSHR miss cycles
3659system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 317869500 # number of demand (read+write) MSHR miss cycles
3660system.l2c.demand_mshr_miss_latency::cpu0.inst 6512407062 # number of demand (read+write) MSHR miss cycles
3661system.l2c.demand_mshr_miss_latency::cpu0.data 26786117482 # number of demand (read+write) MSHR miss cycles
3662system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 48300635417 # number of demand (read+write) MSHR miss cycles
3663system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 178023502 # number of demand (read+write) MSHR miss cycles
3664system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 126275001 # number of demand (read+write) MSHR miss cycles
3665system.l2c.demand_mshr_miss_latency::cpu1.inst 4948966536 # number of demand (read+write) MSHR miss cycles
3666system.l2c.demand_mshr_miss_latency::cpu1.data 16846853081 # number of demand (read+write) MSHR miss cycles
3667system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 28627972330 # number of demand (read+write) MSHR miss cycles
3668system.l2c.demand_mshr_miss_latency::total 132962643413 # number of demand (read+write) MSHR miss cycles
3669system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 317523502 # number of overall MSHR miss cycles
3670system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 317869500 # number of overall MSHR miss cycles
3671system.l2c.overall_mshr_miss_latency::cpu0.inst 6512407062 # number of overall MSHR miss cycles
3672system.l2c.overall_mshr_miss_latency::cpu0.data 26786117482 # number of overall MSHR miss cycles
3673system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 48300635417 # number of overall MSHR miss cycles
3674system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 178023502 # number of overall MSHR miss cycles
3675system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 126275001 # number of overall MSHR miss cycles
3676system.l2c.overall_mshr_miss_latency::cpu1.inst 4948966536 # number of overall MSHR miss cycles
3677system.l2c.overall_mshr_miss_latency::cpu1.data 16846853081 # number of overall MSHR miss cycles
3678system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 28627972330 # number of overall MSHR miss cycles
3679system.l2c.overall_mshr_miss_latency::total 132962643413 # number of overall MSHR miss cycles
3680system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1484185500 # number of ReadReq MSHR uncacheable cycles
3681system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4824158502 # number of ReadReq MSHR uncacheable cycles
3682system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5090000 # number of ReadReq MSHR uncacheable cycles
3683system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1123983502 # number of ReadReq MSHR uncacheable cycles
3684system.l2c.ReadReq_mshr_uncacheable_latency::total 7437417504 # number of ReadReq MSHR uncacheable cycles
3685system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1484185500 # number of overall MSHR uncacheable cycles
3686system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4824158502 # number of overall MSHR uncacheable cycles
3687system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5090000 # number of overall MSHR uncacheable cycles
3688system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1123983502 # number of overall MSHR uncacheable cycles
3689system.l2c.overall_mshr_uncacheable_latency::total 7437417504 # number of overall MSHR uncacheable cycles
3690system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3691system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3692system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.104887 # mshr miss rate for UpgradeReq accesses
3693system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.122508 # mshr miss rate for UpgradeReq accesses
3694system.l2c.UpgradeReq_mshr_miss_rate::total 0.112996 # mshr miss rate for UpgradeReq accesses
3695system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.012497 # mshr miss rate for SCUpgradeReq accesses
3696system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016771 # mshr miss rate for SCUpgradeReq accesses
3697system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.014514 # mshr miss rate for SCUpgradeReq accesses
3698system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.633763 # mshr miss rate for ReadExReq accesses
3699system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.467484 # mshr miss rate for ReadExReq accesses
3700system.l2c.ReadExReq_mshr_miss_rate::total 0.563152 # mshr miss rate for ReadExReq accesses
3701system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.217397 # mshr miss rate for ReadSharedReq accesses
3702system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.407206 # mshr miss rate for ReadSharedReq accesses
3703system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.110040 # mshr miss rate for ReadSharedReq accesses
3704system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.222347 # mshr miss rate for ReadSharedReq accesses
3705system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.540450 # mshr miss rate for ReadSharedReq accesses
3706system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.114304 # mshr miss rate for ReadSharedReq accesses
3707system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.190956 # mshr miss rate for ReadSharedReq accesses
3708system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.085689 # mshr miss rate for ReadSharedReq accesses
3709system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.166675 # mshr miss rate for ReadSharedReq accesses
3710system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.397774 # mshr miss rate for ReadSharedReq accesses
3711system.l2c.ReadSharedReq_mshr_miss_rate::total 0.251247 # mshr miss rate for ReadSharedReq accesses
3712system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.794348 # mshr miss rate for InvalidateReq accesses
3713system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.391940 # mshr miss rate for InvalidateReq accesses
3714system.l2c.InvalidateReq_mshr_miss_rate::total 0.685464 # mshr miss rate for InvalidateReq accesses
3715system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.217397 # mshr miss rate for demand accesses
3716system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.407206 # mshr miss rate for demand accesses
3717system.l2c.demand_mshr_miss_rate::cpu0.inst 0.110040 # mshr miss rate for demand accesses
3718system.l2c.demand_mshr_miss_rate::cpu0.data 0.285329 # mshr miss rate for demand accesses
3719system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.540450 # mshr miss rate for demand accesses
3720system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.114304 # mshr miss rate for demand accesses
3721system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.190956 # mshr miss rate for demand accesses
3722system.l2c.demand_mshr_miss_rate::cpu1.inst 0.085689 # mshr miss rate for demand accesses
3723system.l2c.demand_mshr_miss_rate::cpu1.data 0.206717 # mshr miss rate for demand accesses
3724system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.397774 # mshr miss rate for demand accesses
3725system.l2c.demand_mshr_miss_rate::total 0.270392 # mshr miss rate for demand accesses
3726system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.217397 # mshr miss rate for overall accesses
3727system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.407206 # mshr miss rate for overall accesses
3728system.l2c.overall_mshr_miss_rate::cpu0.inst 0.110040 # mshr miss rate for overall accesses
3729system.l2c.overall_mshr_miss_rate::cpu0.data 0.285329 # mshr miss rate for overall accesses
3730system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.540450 # mshr miss rate for overall accesses
3731system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.114304 # mshr miss rate for overall accesses
3732system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.190956 # mshr miss rate for overall accesses
3733system.l2c.overall_mshr_miss_rate::cpu1.inst 0.085689 # mshr miss rate for overall accesses
3734system.l2c.overall_mshr_miss_rate::cpu1.data 0.206717 # mshr miss rate for overall accesses
3735system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.397774 # mshr miss rate for overall accesses
3736system.l2c.overall_mshr_miss_rate::total 0.270392 # mshr miss rate for overall accesses
3737system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19969.722258 # average UpgradeReq mshr miss latency
3738system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20765.463099 # average UpgradeReq mshr miss latency
3739system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20366.722401 # average UpgradeReq mshr miss latency
3740system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24187.043668 # average SCUpgradeReq mshr miss latency
3741system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24717.839806 # average SCUpgradeReq mshr miss latency
3742system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24476.504964 # average SCUpgradeReq mshr miss latency
3743system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 99144.209304 # average ReadExReq mshr miss latency
3744system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98040.723242 # average ReadExReq mshr miss latency
3745system.l2c.ReadExReq_avg_mshr_miss_latency::total 98755.215750 # average ReadExReq mshr miss latency
3746system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 91268.612245 # average ReadSharedReq mshr miss latency
3747system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 94379.305226 # average ReadSharedReq mshr miss latency
3748system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 100629.001066 # average ReadSharedReq mshr miss latency
3749system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101953.875481 # average ReadSharedReq mshr miss latency
3750system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142661.127915 # average ReadSharedReq mshr miss latency
3751system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 98138.644983 # average ReadSharedReq mshr miss latency
3752system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 101020.000800 # average ReadSharedReq mshr miss latency
3753system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 106358.482216 # average ReadSharedReq mshr miss latency
3754system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 105558.459363 # average ReadSharedReq mshr miss latency
3755system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142150.494210 # average ReadSharedReq mshr miss latency
3756system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 125462.625090 # average ReadSharedReq mshr miss latency
3757system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24731.337936 # average InvalidateReq mshr miss latency
3758system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19590.158569 # average InvalidateReq mshr miss latency
3759system.l2c.InvalidateReq_avg_mshr_miss_latency::total 23935.917426 # average InvalidateReq mshr miss latency
3760system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 91268.612245 # average overall mshr miss latency
3761system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 94379.305226 # average overall mshr miss latency
3762system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 100629.001066 # average overall mshr miss latency
3763system.l2c.demand_avg_mshr_miss_latency::cpu0.data 100998.508678 # average overall mshr miss latency
3764system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142661.127915 # average overall mshr miss latency
3765system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 98138.644983 # average overall mshr miss latency
3766system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 101020.000800 # average overall mshr miss latency
3767system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 106358.482216 # average overall mshr miss latency
3768system.l2c.demand_avg_mshr_miss_latency::cpu1.data 103295.357775 # average overall mshr miss latency
3769system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142150.494210 # average overall mshr miss latency
3770system.l2c.demand_avg_mshr_miss_latency::total 122048.235828 # average overall mshr miss latency
3771system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 91268.612245 # average overall mshr miss latency
3772system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 94379.305226 # average overall mshr miss latency
3773system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 100629.001066 # average overall mshr miss latency
3774system.l2c.overall_avg_mshr_miss_latency::cpu0.data 100998.508678 # average overall mshr miss latency
3775system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142661.127915 # average overall mshr miss latency
3776system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 98138.644983 # average overall mshr miss latency
3777system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 101020.000800 # average overall mshr miss latency
3778system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 106358.482216 # average overall mshr miss latency
3779system.l2c.overall_avg_mshr_miss_latency::cpu1.data 103295.357775 # average overall mshr miss latency
3780system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142150.494210 # average overall mshr miss latency
3781system.l2c.overall_avg_mshr_miss_latency::total 122048.235828 # average overall mshr miss latency
3782system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504 # average ReadReq mshr uncacheable latency
3783system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162895.779233 # average ReadReq mshr uncacheable latency
3784system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 75970.149254 # average ReadReq mshr uncacheable latency
3785system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 126731.706168 # average ReadReq mshr uncacheable latency
3786system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 124280.086625 # average ReadReq mshr uncacheable latency
3787system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504 # average overall mshr uncacheable latency
3788system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 81343.515024 # average overall mshr uncacheable latency
3789system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 75970.149254 # average overall mshr uncacheable latency
3790system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 63993.594967 # average overall mshr uncacheable latency
3791system.l2c.overall_avg_mshr_uncacheable_latency::total 75714.318477 # average overall mshr uncacheable latency
3792system.membus.snoop_filter.tot_requests 4039865 # Total number of requests made to the snoop filter.
3793system.membus.snoop_filter.hit_single_requests 2364937 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3794system.membus.snoop_filter.hit_multi_requests 3552 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3795system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
3796system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3797system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3798system.membus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3799system.membus.trans_dist::ReadReq 59844 # Transaction distribution
3800system.membus.trans_dist::ReadResp 1018974 # Transaction distribution
3801system.membus.trans_dist::WriteReq 38386 # Transaction distribution
3802system.membus.trans_dist::WriteResp 38386 # Transaction distribution
3803system.membus.trans_dist::WritebackDirty 1351242 # Transaction distribution
3804system.membus.trans_dist::CleanEvict 267627 # Transaction distribution
3805system.membus.trans_dist::UpgradeReq 336754 # Transaction distribution
3806system.membus.trans_dist::SCUpgradeReq 267840 # Transaction distribution
3807system.membus.trans_dist::UpgradeResp 23 # Transaction distribution
3808system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
3809system.membus.trans_dist::ReadExReq 152823 # Transaction distribution
3810system.membus.trans_dist::ReadExResp 138565 # Transaction distribution
3811system.membus.trans_dist::ReadSharedReq 959130 # Transaction distribution
3812system.membus.trans_dist::InvalidateReq 652932 # Transaction distribution
3813system.membus.trans_dist::InvalidateResp 30629 # Transaction distribution
3814system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122710 # Packet count per connected master and slave (bytes)
3815system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes)
3816system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25810 # Packet count per connected master and slave (bytes)
3817system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4892821 # Packet count per connected master and slave (bytes)
3818system.membus.pkt_count_system.l2c.mem_side::total 5041417 # Packet count per connected master and slave (bytes)
3819system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237968 # Packet count per connected master and slave (bytes)
3820system.membus.pkt_count_system.iocache.mem_side::total 237968 # Packet count per connected master and slave (bytes)
3821system.membus.pkt_count::total 5279385 # Packet count per connected master and slave (bytes)
3822system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155817 # Cumulative packet size per connected master and slave (bytes)
3823system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes)
3824system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51620 # Cumulative packet size per connected master and slave (bytes)
3825system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 149644096 # Cumulative packet size per connected master and slave (bytes)
3826system.membus.pkt_size_system.l2c.mem_side::total 149852089 # Cumulative packet size per connected master and slave (bytes)
3827system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7250176 # Cumulative packet size per connected master and slave (bytes)
3828system.membus.pkt_size_system.iocache.mem_side::total 7250176 # Cumulative packet size per connected master and slave (bytes)
3829system.membus.pkt_size::total 157102265 # Cumulative packet size per connected master and slave (bytes)
3830system.membus.snoops 616817 # Total snoops (count)
3831system.membus.snoopTraffic 199808 # Total snoop traffic (bytes)
3832system.membus.snoop_fanout::samples 2467715 # Request fanout histogram
3833system.membus.snoop_fanout::mean 0.013862 # Request fanout histogram
3834system.membus.snoop_fanout::stdev 0.116919 # Request fanout histogram
3835system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3836system.membus.snoop_fanout::0 2433507 98.61% 98.61% # Request fanout histogram
3837system.membus.snoop_fanout::1 34208 1.39% 100.00% # Request fanout histogram
3838system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3839system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3840system.membus.snoop_fanout::min_value 0 # Request fanout histogram
3841system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3842system.membus.snoop_fanout::total 2467715 # Request fanout histogram
3843system.membus.reqLayer0.occupancy 98169995 # Layer occupancy (ticks)
3844system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3845system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks)
3846system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3847system.membus.reqLayer2.occupancy 21686998 # Layer occupancy (ticks)
3848system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3849system.membus.reqLayer5.occupancy 9247698101 # Layer occupancy (ticks)
3850system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3851system.membus.respLayer2.occupancy 5871093052 # Layer occupancy (ticks)
3852system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3853system.membus.respLayer3.occupancy 81490219 # Layer occupancy (ticks)
3854system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3855system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3856system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3857system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3858system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3859system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3860system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3861system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3862system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3863system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3864system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3865system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3866system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3867system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3868system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3869system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3870system.realview.ethernet.txBytes 966 # Bytes Transmitted
3871system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3872system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3873system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3874system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3875system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3876system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
3877system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA

--- 26 unchanged lines hidden (view full) ---

3904system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
3905system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3906system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3907system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
3908system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3909system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3910system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3911system.realview.ethernet.droppedPackets 0 # number of packets dropped
3912system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3913system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3914system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3915system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3916system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3917system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3918system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3919system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3920system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3921system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3922system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3923system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3924system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3925system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3926system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3927system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3928system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3929system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3930system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3931system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3932system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3933system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3934system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3935system.toL2Bus.snoop_filter.tot_requests 12086303 # Total number of requests made to the snoop filter.
3936system.toL2Bus.snoop_filter.hit_single_requests 6387551 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3937system.toL2Bus.snoop_filter.hit_multi_requests 2235502 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3938system.toL2Bus.snoop_filter.tot_snoops 239971 # Total number of snoops made to the snoop filter.
3939system.toL2Bus.snoop_filter.hit_single_snoops 217052 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3940system.toL2Bus.snoop_filter.hit_multi_snoops 22919 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3941system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384940455000 # Cumulative time (in ticks) in various power states
3942system.toL2Bus.trans_dist::ReadReq 59846 # Transaction distribution
3943system.toL2Bus.trans_dist::ReadResp 4613854 # Transaction distribution
3944system.toL2Bus.trans_dist::WriteReq 38386 # Transaction distribution
3945system.toL2Bus.trans_dist::WriteResp 38386 # Transaction distribution
3946system.toL2Bus.trans_dist::WritebackDirty 4129201 # Transaction distribution
3947system.toL2Bus.trans_dist::CleanEvict 2768870 # Transaction distribution
3948system.toL2Bus.trans_dist::UpgradeReq 702098 # Transaction distribution
3949system.toL2Bus.trans_dist::SCUpgradeReq 370433 # Transaction distribution
3950system.toL2Bus.trans_dist::UpgradeResp 1072531 # Transaction distribution
3951system.toL2Bus.trans_dist::SCUpgradeFailReq 113 # Transaction distribution
3952system.toL2Bus.trans_dist::UpgradeFailResp 113 # Transaction distribution
3953system.toL2Bus.trans_dist::ReadExReq 298786 # Transaction distribution
3954system.toL2Bus.trans_dist::ReadExResp 298786 # Transaction distribution
3955system.toL2Bus.trans_dist::ReadSharedReq 4554900 # Transaction distribution
3956system.toL2Bus.trans_dist::InvalidateReq 905153 # Transaction distribution
3957system.toL2Bus.trans_dist::InvalidateResp 886862 # Transaction distribution
3958system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9925339 # Packet count per connected master and slave (bytes)
3959system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7679367 # Packet count per connected master and slave (bytes)
3960system.toL2Bus.pkt_count::total 17604706 # Packet count per connected master and slave (bytes)
3961system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 251196049 # Cumulative packet size per connected master and slave (bytes)
3962system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 191962664 # Cumulative packet size per connected master and slave (bytes)
3963system.toL2Bus.pkt_size::total 443158713 # Cumulative packet size per connected master and slave (bytes)
3964system.toL2Bus.snoops 3147878 # Total snoops (count)
3965system.toL2Bus.snoopTraffic 132377296 # Total snoop traffic (bytes)
3966system.toL2Bus.snoop_fanout::samples 8556431 # Request fanout histogram
3967system.toL2Bus.snoop_fanout::mean 0.371457 # Request fanout histogram
3968system.toL2Bus.snoop_fanout::stdev 0.488706 # Request fanout histogram
3969system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3970system.toL2Bus.snoop_fanout::0 5401002 63.12% 63.12% # Request fanout histogram
3971system.toL2Bus.snoop_fanout::1 3132510 36.61% 99.73% # Request fanout histogram
3972system.toL2Bus.snoop_fanout::2 22919 0.27% 100.00% # Request fanout histogram
3973system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3974system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3975system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3976system.toL2Bus.snoop_fanout::total 8556431 # Request fanout histogram
3977system.toL2Bus.reqLayer0.occupancy 9443624545 # Layer occupancy (ticks)
3978system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3979system.toL2Bus.snoopLayer0.occupancy 9237873 # Layer occupancy (ticks)
3980system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3981system.toL2Bus.respLayer0.occupancy 4533014073 # Layer occupancy (ticks)
3982system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3983system.toL2Bus.respLayer1.occupancy 3814018472 # Layer occupancy (ticks)
3984system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3985system.cpu0.kern.inst.arm 0 # number of arm instructions executed
3986system.cpu0.kern.inst.quiesce 13606 # number of quiesce instructions executed
3987system.cpu1.kern.inst.arm 0 # number of arm instructions executed
3988system.cpu1.kern.inst.quiesce 5169 # number of quiesce instructions executed
3989
3990---------- End Simulation Statistics ----------