1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.468752 # Number of seconds simulated
4sim_ticks 47468751978000 # Number of ticks simulated
5final_tick 47468751978000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 133266 # Simulator instruction rate (inst/s)
8host_op_rate 156717 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 6699893970 # Simulator tick rate (ticks/s)
10host_mem_usage 769956 # Number of bytes of host memory used
11host_seconds 7085.00 # Real time elapsed on the host
12sim_insts 944191442 # Number of instructions simulated
13sim_ops 1110340105 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 171136 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 120960 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 3861216 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 14070216 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 17654336 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 218240 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 209216 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 3621984 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 13693456 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 20748864 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 405504 # Number of bytes read from this memory
27system.physmem.bytes_read::total 74775128 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 3861216 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 3621984 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 7483200 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 90808384 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
34system.physmem.bytes_written::total 90828968 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 2674 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 1890 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 76284 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 219860 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 275849 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 3410 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.itb.walker 3269 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.inst 56637 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.data 213973 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.l2cache.prefetcher 324201 # Number of read requests responded to by this memory
45system.physmem.num_reads::realview.ide 6336 # Number of read requests responded to by this memory
46system.physmem.num_reads::total 1184383 # Number of read requests responded to by this memory
47system.physmem.num_writes::writebacks 1418881 # Number of write requests responded to by this memory
48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
50system.physmem.num_writes::total 1421455 # Number of write requests responded to by this memory
51system.physmem.bw_read::cpu0.dtb.walker 3605 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.itb.walker 2548 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.inst 81342 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.data 296410 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.l2cache.prefetcher 371915 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.dtb.walker 4598 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.itb.walker 4407 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.inst 76302 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.data 288473 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.l2cache.prefetcher 437106 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::realview.ide 8543 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::total 1575250 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::cpu0.inst 81342 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu1.inst 76302 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::total 157645 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_write::writebacks 1913014 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::total 1913448 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_total::writebacks 1913014 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.dtb.walker 3605 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.itb.walker 2548 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.inst 81342 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.data 296844 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.l2cache.prefetcher 371915 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.dtb.walker 4598 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.itb.walker 4407 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.inst 76302 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.data 288473 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.l2cache.prefetcher 437106 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.ide 8543 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::total 3488697 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.readReqs 1184383 # Number of read requests accepted
84system.physmem.writeReqs 1421455 # Number of write requests accepted
85system.physmem.readBursts 1184383 # Number of DRAM read bursts, including those serviced by the write queue
86system.physmem.writeBursts 1421455 # Number of DRAM write bursts, including those merged in the write queue
87system.physmem.bytesReadDRAM 75776512 # Total number of bytes read from DRAM
88system.physmem.bytesReadWrQ 24000 # Total number of bytes read from write queue
89system.physmem.bytesWritten 90827456 # Total number of bytes written to DRAM
90system.physmem.bytesReadSys 74775128 # Total read bytes from the system interface side
91system.physmem.bytesWrittenSys 90828968 # Total written bytes from the system interface side
92system.physmem.servicedByWrQ 375 # Number of DRAM read bursts serviced by the write queue
93system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
94system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
95system.physmem.perBankRdBursts::0 72103 # Per bank write bursts
96system.physmem.perBankRdBursts::1 78803 # Per bank write bursts
97system.physmem.perBankRdBursts::2 72464 # Per bank write bursts
98system.physmem.perBankRdBursts::3 70552 # Per bank write bursts
99system.physmem.perBankRdBursts::4 69846 # Per bank write bursts
100system.physmem.perBankRdBursts::5 79143 # Per bank write bursts
101system.physmem.perBankRdBursts::6 69266 # Per bank write bursts
102system.physmem.perBankRdBursts::7 70722 # Per bank write bursts
103system.physmem.perBankRdBursts::8 68903 # Per bank write bursts
104system.physmem.perBankRdBursts::9 99020 # Per bank write bursts
105system.physmem.perBankRdBursts::10 71711 # Per bank write bursts
106system.physmem.perBankRdBursts::11 73604 # Per bank write bursts
107system.physmem.perBankRdBursts::12 71852 # Per bank write bursts
108system.physmem.perBankRdBursts::13 74765 # Per bank write bursts
109system.physmem.perBankRdBursts::14 70123 # Per bank write bursts
110system.physmem.perBankRdBursts::15 71131 # Per bank write bursts
111system.physmem.perBankWrBursts::0 89065 # Per bank write bursts
112system.physmem.perBankWrBursts::1 93300 # Per bank write bursts
113system.physmem.perBankWrBursts::2 85781 # Per bank write bursts
114system.physmem.perBankWrBursts::3 86502 # Per bank write bursts
115system.physmem.perBankWrBursts::4 86907 # Per bank write bursts
116system.physmem.perBankWrBursts::5 92159 # Per bank write bursts
117system.physmem.perBankWrBursts::6 86239 # Per bank write bursts
118system.physmem.perBankWrBursts::7 88123 # Per bank write bursts
119system.physmem.perBankWrBursts::8 85047 # Per bank write bursts
120system.physmem.perBankWrBursts::9 93098 # Per bank write bursts
121system.physmem.perBankWrBursts::10 87729 # Per bank write bursts
122system.physmem.perBankWrBursts::11 90867 # Per bank write bursts
123system.physmem.perBankWrBursts::12 86341 # Per bank write bursts
124system.physmem.perBankWrBursts::13 90891 # Per bank write bursts
125system.physmem.perBankWrBursts::14 88902 # Per bank write bursts
126system.physmem.perBankWrBursts::15 88228 # Per bank write bursts
127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
128system.physmem.numWrRetry 43 # Number of times write queue was full causing retry
129system.physmem.totGap 47468750370500 # Total gap between requests
130system.physmem.readPktSize::0 0 # Read request sizes (log2)
131system.physmem.readPktSize::1 0 # Read request sizes (log2)
132system.physmem.readPktSize::2 0 # Read request sizes (log2)
133system.physmem.readPktSize::3 25 # Read request sizes (log2)
134system.physmem.readPktSize::4 21333 # Read request sizes (log2)
135system.physmem.readPktSize::5 0 # Read request sizes (log2)
136system.physmem.readPktSize::6 1163025 # Read request sizes (log2)
137system.physmem.writePktSize::0 0 # Write request sizes (log2)
138system.physmem.writePktSize::1 0 # Write request sizes (log2)
139system.physmem.writePktSize::2 2 # Write request sizes (log2)
140system.physmem.writePktSize::3 2572 # Write request sizes (log2)
141system.physmem.writePktSize::4 0 # Write request sizes (log2)
142system.physmem.writePktSize::5 0 # Write request sizes (log2)
143system.physmem.writePktSize::6 1418881 # Write request sizes (log2)
144system.physmem.rdQLenPdf::0 512770 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::1 308725 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::2 87137 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::3 63943 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::4 45149 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::5 40149 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::6 37001 # What read queue length does an incoming req see
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154system.physmem.rdQLenPdf::10 4718 # What read queue length does an incoming req see
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157system.physmem.rdQLenPdf::13 1609 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::14 1005 # What read queue length does an incoming req see
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183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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191system.physmem.wrQLenPdf::15 26847 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::16 31854 # What write queue length does an incoming req see
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194system.physmem.wrQLenPdf::18 49676 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::19 56919 # What write queue length does an incoming req see
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203system.physmem.wrQLenPdf::27 94983 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::28 99480 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::29 111361 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::30 98562 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::31 89368 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::32 83432 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::33 13050 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::34 9803 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::35 8425 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::36 6741 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::37 5561 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::38 4626 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::39 3942 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::40 3261 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::41 2837 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::42 2381 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::43 2058 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::44 1909 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::45 1685 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::46 1499 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::47 1391 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::48 1145 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::49 1040 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::50 919 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::51 710 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::52 666 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::53 524 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::54 403 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::55 368 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::56 321 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::57 250 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::58 182 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::59 161 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::60 165 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::61 132 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::62 77 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::63 105 # What write queue length does an incoming req see
240system.physmem.bytesPerActivate::samples 1159540 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::mean 143.680535 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::gmean 97.586865 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::stdev 190.741453 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::0-127 783407 67.56% 67.56% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::128-255 222260 19.17% 86.73% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::256-383 55727 4.81% 91.54% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::384-511 24890 2.15% 93.68% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::512-639 21192 1.83% 95.51% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::640-767 11987 1.03% 96.54% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::768-895 8178 0.71% 97.25% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::896-1023 4967 0.43% 97.68% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::1024-1151 26932 2.32% 100.00% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::total 1159540 # Bytes accessed per row activation
254system.physmem.rdPerTurnAround::samples 67946 # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::mean 17.425117 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::stdev 68.584486 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::0-511 67943 100.00% 100.00% # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::512-1023 1 0.00% 100.00% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::total 67946 # Reads before turning the bus around for writes
262system.physmem.wrPerTurnAround::samples 67946 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::mean 20.886866 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::gmean 17.982744 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::stdev 74.693624 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::0-127 67692 99.63% 99.63% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::128-255 167 0.25% 99.87% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::256-383 12 0.02% 99.89% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::384-511 13 0.02% 99.91% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::512-639 10 0.01% 99.92% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::640-767 5 0.01% 99.93% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::768-895 6 0.01% 99.94% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::896-1023 2 0.00% 99.94% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::1024-1151 3 0.00% 99.95% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::1152-1279 3 0.00% 99.95% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::1280-1407 1 0.00% 99.95% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::1408-1535 3 0.00% 99.96% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::1536-1663 1 0.00% 99.96% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::1664-1791 2 0.00% 99.96% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::1792-1919 3 0.00% 99.97% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::1920-2047 1 0.00% 99.97% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::2048-2175 1 0.00% 99.97% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::2176-2303 2 0.00% 99.97% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::2432-2559 1 0.00% 99.97% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::2560-2687 2 0.00% 99.98% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::2688-2815 1 0.00% 99.98% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::2944-3071 1 0.00% 99.98% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::3072-3199 1 0.00% 99.98% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::3200-3327 1 0.00% 99.98% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::3584-3711 1 0.00% 99.98% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::3840-3967 2 0.00% 99.99% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::3968-4095 3 0.00% 99.99% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::4224-4351 3 0.00% 100.00% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::4736-4863 1 0.00% 100.00% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::5760-5887 1 0.00% 100.00% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::6528-6655 1 0.00% 100.00% # Writes before turning the bus around for reads
297system.physmem.wrPerTurnAround::total 67946 # Writes before turning the bus around for reads
298system.physmem.totQLat 53444908202 # Total ticks spent queuing
299system.physmem.totMemAccLat 75645058202 # Total ticks spent from burst creation until serviced by the DRAM
300system.physmem.totBusLat 5920040000 # Total ticks spent in databus transfers
301system.physmem.avgQLat 45138.98 # Average queueing delay per DRAM burst
302system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
303system.physmem.avgMemAccLat 63888.98 # Average memory access latency per DRAM burst
304system.physmem.avgRdBW 1.60 # Average DRAM read bandwidth in MiByte/s
305system.physmem.avgWrBW 1.91 # Average achieved write bandwidth in MiByte/s
306system.physmem.avgRdBWSys 1.58 # Average system read bandwidth in MiByte/s
307system.physmem.avgWrBWSys 1.91 # Average system write bandwidth in MiByte/s
308system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
309system.physmem.busUtil 0.03 # Data bus utilization in percentage
310system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
311system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
312system.physmem.avgRdQLen 2.06 # Average read queue length when enqueuing
313system.physmem.avgWrQLen 23.70 # Average write queue length when enqueuing
314system.physmem.readRowHits 894156 # Number of row buffer hits during reads
315system.physmem.writeRowHits 549489 # Number of row buffer hits during writes
316system.physmem.readRowHitRate 75.52 # Row buffer hit rate for reads
317system.physmem.writeRowHitRate 38.72 # Row buffer hit rate for writes
318system.physmem.avgGap 18216309.06 # Average gap between requests
319system.physmem.pageHitRate 55.46 # Row buffer hit rate, read and write combined
320system.physmem_0.actEnergy 4374828360 # Energy for activate commands per rank (pJ)
321system.physmem_0.preEnergy 2387059125 # Energy for precharge commands per rank (pJ)
322system.physmem_0.readEnergy 4546612200 # Energy for read commands per rank (pJ)
323system.physmem_0.writeEnergy 4588332480 # Energy for write commands per rank (pJ)
324system.physmem_0.refreshEnergy 3100427903040 # Energy for refresh commands per rank (pJ)
325system.physmem_0.actBackEnergy 1181604436515 # Energy for active background per rank (pJ)
326system.physmem_0.preBackEnergy 27444754155000 # Energy for precharge background per rank (pJ)
327system.physmem_0.totalEnergy 31742683326720 # Total energy per rank (pJ)
328system.physmem_0.averagePower 668.706973 # Core power per rank (mW)
329system.physmem_0.memoryStateTime::IDLE 45656629611476 # Time in different power states
330system.physmem_0.memoryStateTime::REF 1585085840000 # Time in different power states
331system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
332system.physmem_0.memoryStateTime::ACT 227033353524 # Time in different power states
333system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
334system.physmem_1.actEnergy 4391294040 # Energy for activate commands per rank (pJ)
335system.physmem_1.preEnergy 2396043375 # Energy for precharge commands per rank (pJ)
336system.physmem_1.readEnergy 4688572200 # Energy for read commands per rank (pJ)
337system.physmem_1.writeEnergy 4607947440 # Energy for write commands per rank (pJ)
338system.physmem_1.refreshEnergy 3100427903040 # Energy for refresh commands per rank (pJ)
339system.physmem_1.actBackEnergy 1183305976290 # Energy for active background per rank (pJ)
340system.physmem_1.preBackEnergy 27443261584500 # Energy for precharge background per rank (pJ)
341system.physmem_1.totalEnergy 31743079320885 # Total energy per rank (pJ)
342system.physmem_1.averagePower 668.715315 # Core power per rank (mW)
343system.physmem_1.memoryStateTime::IDLE 45654123959514 # Time in different power states
344system.physmem_1.memoryStateTime::REF 1585085840000 # Time in different power states
345system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
346system.physmem_1.memoryStateTime::ACT 229539287986 # Time in different power states
347system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
348system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory
349system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
350system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
351system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
352system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory
353system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory
354system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory

--- 17 unchanged lines hidden (view full) ---

372system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
373system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
374system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
375system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
376system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
377system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
378system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
379system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
380system.cpu0.branchPred.lookups 132444225 # Number of BP lookups
381system.cpu0.branchPred.condPredicted 87787955 # Number of conditional branches predicted
382system.cpu0.branchPred.condIncorrect 6400754 # Number of conditional branches incorrect
383system.cpu0.branchPred.BTBLookups 93524644 # Number of BTB lookups
384system.cpu0.branchPred.BTBHits 57612051 # Number of BTB hits
385system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
386system.cpu0.branchPred.BTBHitPct 61.600931 # BTB Hit Percentage
387system.cpu0.branchPred.usedRAS 17778768 # Number of times the RAS was used to get a target.
388system.cpu0.branchPred.RASInCorrect 168825 # Number of incorrect RAS predictions.
389system.cpu0.branchPred.indirectLookups 4144770 # Number of indirect predictor lookups.
390system.cpu0.branchPred.indirectHits 2586947 # Number of indirect target hits.
391system.cpu0.branchPred.indirectMisses 1557823 # Number of indirect misses.
392system.cpu0.branchPredindirectMispredicted 392899 # Number of mispredicted indirect branches.
393system.cpu_clk_domain.clock 500 # Clock period in ticks
394system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

415system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
416system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
417system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
418system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
419system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
420system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
421system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
422system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
423system.cpu0.dtb.walker.walks 539802 # Table walker walks requested
424system.cpu0.dtb.walker.walksLong 539802 # Table walker walks initiated with long descriptors
425system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11294 # Level at which table walker walks with long descriptors terminate
426system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84152 # Level at which table walker walks with long descriptors terminate
427system.cpu0.dtb.walker.walksSquashedBefore 248635 # Table walks squashed before starting
428system.cpu0.dtb.walker.walkWaitTime::samples 291167 # Table walker wait (enqueue to first request) latency
429system.cpu0.dtb.walker.walkWaitTime::mean 2569.659336 # Table walker wait (enqueue to first request) latency
430system.cpu0.dtb.walker.walkWaitTime::stdev 15605.583986 # Table walker wait (enqueue to first request) latency
431system.cpu0.dtb.walker.walkWaitTime::0-65535 288567 99.11% 99.11% # Table walker wait (enqueue to first request) latency
432system.cpu0.dtb.walker.walkWaitTime::65536-131071 1409 0.48% 99.59% # Table walker wait (enqueue to first request) latency
433system.cpu0.dtb.walker.walkWaitTime::131072-196607 865 0.30% 99.89% # Table walker wait (enqueue to first request) latency
434system.cpu0.dtb.walker.walkWaitTime::196608-262143 174 0.06% 99.95% # Table walker wait (enqueue to first request) latency
435system.cpu0.dtb.walker.walkWaitTime::262144-327679 52 0.02% 99.97% # Table walker wait (enqueue to first request) latency
436system.cpu0.dtb.walker.walkWaitTime::327680-393215 75 0.03% 99.99% # Table walker wait (enqueue to first request) latency
437system.cpu0.dtb.walker.walkWaitTime::393216-458751 18 0.01% 100.00% # Table walker wait (enqueue to first request) latency
438system.cpu0.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency
439system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
440system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
441system.cpu0.dtb.walker.walkWaitTime::total 291167 # Table walker wait (enqueue to first request) latency
442system.cpu0.dtb.walker.walkCompletionTime::samples 273980 # Table walker service (enqueue to completion) latency
443system.cpu0.dtb.walker.walkCompletionTime::mean 20501.036572 # Table walker service (enqueue to completion) latency
444system.cpu0.dtb.walker.walkCompletionTime::gmean 17496.757374 # Table walker service (enqueue to completion) latency
445system.cpu0.dtb.walker.walkCompletionTime::stdev 20192.590719 # Table walker service (enqueue to completion) latency
446system.cpu0.dtb.walker.walkCompletionTime::0-65535 271123 98.96% 98.96% # Table walker service (enqueue to completion) latency
447system.cpu0.dtb.walker.walkCompletionTime::65536-131071 705 0.26% 99.21% # Table walker service (enqueue to completion) latency
448system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1540 0.56% 99.78% # Table walker service (enqueue to completion) latency
449system.cpu0.dtb.walker.walkCompletionTime::196608-262143 149 0.05% 99.83% # Table walker service (enqueue to completion) latency
450system.cpu0.dtb.walker.walkCompletionTime::262144-327679 269 0.10% 99.93% # Table walker service (enqueue to completion) latency
451system.cpu0.dtb.walker.walkCompletionTime::327680-393215 86 0.03% 99.96% # Table walker service (enqueue to completion) latency
452system.cpu0.dtb.walker.walkCompletionTime::393216-458751 62 0.02% 99.98% # Table walker service (enqueue to completion) latency
453system.cpu0.dtb.walker.walkCompletionTime::458752-524287 25 0.01% 99.99% # Table walker service (enqueue to completion) latency
454system.cpu0.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 99.99% # Table walker service (enqueue to completion) latency
455system.cpu0.dtb.walker.walkCompletionTime::589824-655359 8 0.00% 100.00% # Table walker service (enqueue to completion) latency
456system.cpu0.dtb.walker.walkCompletionTime::655360-720895 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
457system.cpu0.dtb.walker.walkCompletionTime::total 273980 # Table walker service (enqueue to completion) latency
458system.cpu0.dtb.walker.walksPending::samples 529053057016 # Table walker pending requests distribution
459system.cpu0.dtb.walker.walksPending::mean 0.549473 # Table walker pending requests distribution
460system.cpu0.dtb.walker.walksPending::stdev 0.550536 # Table walker pending requests distribution
461system.cpu0.dtb.walker.walksPending::0-1 527876290016 99.78% 99.78% # Table walker pending requests distribution
462system.cpu0.dtb.walker.walksPending::2-3 603631000 0.11% 99.89% # Table walker pending requests distribution
463system.cpu0.dtb.walker.walksPending::4-5 259797000 0.05% 99.94% # Table walker pending requests distribution
464system.cpu0.dtb.walker.walksPending::6-7 123836500 0.02% 99.96% # Table walker pending requests distribution
465system.cpu0.dtb.walker.walksPending::8-9 92525500 0.02% 99.98% # Table walker pending requests distribution
466system.cpu0.dtb.walker.walksPending::10-11 56948500 0.01% 99.99% # Table walker pending requests distribution
467system.cpu0.dtb.walker.walksPending::12-13 16655000 0.00% 100.00% # Table walker pending requests distribution
468system.cpu0.dtb.walker.walksPending::14-15 23145000 0.00% 100.00% # Table walker pending requests distribution
469system.cpu0.dtb.walker.walksPending::16-17 228500 0.00% 100.00% # Table walker pending requests distribution
470system.cpu0.dtb.walker.walksPending::total 529053057016 # Table walker pending requests distribution
471system.cpu0.dtb.walker.walkPageSizes::4K 84152 88.17% 88.17% # Table walker page sizes translated
472system.cpu0.dtb.walker.walkPageSizes::2M 11294 11.83% 100.00% # Table walker page sizes translated
473system.cpu0.dtb.walker.walkPageSizes::total 95446 # Table walker page sizes translated
474system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 539802 # Table walker requests started/completed, data/inst
475system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
476system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 539802 # Table walker requests started/completed, data/inst
477system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 95446 # Table walker requests started/completed, data/inst
478system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
479system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 95446 # Table walker requests started/completed, data/inst
480system.cpu0.dtb.walker.walkRequestOrigin::total 635248 # Table walker requests started/completed, data/inst
481system.cpu0.dtb.inst_hits 0 # ITB inst hits
482system.cpu0.dtb.inst_misses 0 # ITB inst misses
483system.cpu0.dtb.read_hits 96092667 # DTB read hits
484system.cpu0.dtb.read_misses 371231 # DTB read misses
485system.cpu0.dtb.write_hits 80108557 # DTB write hits
486system.cpu0.dtb.write_misses 168571 # DTB write misses
487system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
488system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
489system.cpu0.dtb.flush_tlb_mva_asid 46091 # Number of times TLB was flushed by MVA & ASID
490system.cpu0.dtb.flush_tlb_asid 1084 # Number of times TLB was flushed by ASID
491system.cpu0.dtb.flush_entries 35125 # Number of entries that have been flushed from TLB
492system.cpu0.dtb.align_faults 346 # Number of TLB faults due to alignment restrictions
493system.cpu0.dtb.prefetch_faults 6813 # Number of TLB faults due to prefetch
494system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
495system.cpu0.dtb.perms_faults 38936 # Number of TLB faults due to permissions restrictions
496system.cpu0.dtb.read_accesses 96463898 # DTB read accesses
497system.cpu0.dtb.write_accesses 80277128 # DTB write accesses
498system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
499system.cpu0.dtb.hits 176201224 # DTB hits
500system.cpu0.dtb.misses 539802 # DTB misses
501system.cpu0.dtb.accesses 176741026 # DTB accesses
502system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
503system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
504system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
505system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
506system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
507system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
508system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
509system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

523system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
524system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
525system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
526system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
527system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
528system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
529system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
530system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
531system.cpu0.itb.walker.walks 79903 # Table walker walks requested
532system.cpu0.itb.walker.walksLong 79903 # Table walker walks initiated with long descriptors
533system.cpu0.itb.walker.walksLongTerminationLevel::Level2 950 # Level at which table walker walks with long descriptors terminate
534system.cpu0.itb.walker.walksLongTerminationLevel::Level3 57315 # Level at which table walker walks with long descriptors terminate
535system.cpu0.itb.walker.walksSquashedBefore 9653 # Table walks squashed before starting
536system.cpu0.itb.walker.walkWaitTime::samples 70250 # Table walker wait (enqueue to first request) latency
537system.cpu0.itb.walker.walkWaitTime::mean 1248.284698 # Table walker wait (enqueue to first request) latency
538system.cpu0.itb.walker.walkWaitTime::stdev 10855.060811 # Table walker wait (enqueue to first request) latency
539system.cpu0.itb.walker.walkWaitTime::0-65535 69985 99.62% 99.62% # Table walker wait (enqueue to first request) latency
540system.cpu0.itb.walker.walkWaitTime::65536-131071 65 0.09% 99.72% # Table walker wait (enqueue to first request) latency
541system.cpu0.itb.walker.walkWaitTime::131072-196607 177 0.25% 99.97% # Table walker wait (enqueue to first request) latency
542system.cpu0.itb.walker.walkWaitTime::196608-262143 11 0.02% 99.98% # Table walker wait (enqueue to first request) latency
543system.cpu0.itb.walker.walkWaitTime::262144-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency
544system.cpu0.itb.walker.walkWaitTime::327680-393215 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
545system.cpu0.itb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
546system.cpu0.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
547system.cpu0.itb.walker.walkWaitTime::total 70250 # Table walker wait (enqueue to first request) latency
548system.cpu0.itb.walker.walkCompletionTime::samples 67918 # Table walker service (enqueue to completion) latency
549system.cpu0.itb.walker.walkCompletionTime::mean 26250.242940 # Table walker service (enqueue to completion) latency
550system.cpu0.itb.walker.walkCompletionTime::gmean 22828.736245 # Table walker service (enqueue to completion) latency
551system.cpu0.itb.walker.walkCompletionTime::stdev 25780.781063 # Table walker service (enqueue to completion) latency
552system.cpu0.itb.walker.walkCompletionTime::0-65535 66522 97.94% 97.94% # Table walker service (enqueue to completion) latency
553system.cpu0.itb.walker.walkCompletionTime::65536-131071 103 0.15% 98.10% # Table walker service (enqueue to completion) latency
554system.cpu0.itb.walker.walkCompletionTime::131072-196607 1066 1.57% 99.67% # Table walker service (enqueue to completion) latency
555system.cpu0.itb.walker.walkCompletionTime::196608-262143 71 0.10% 99.77% # Table walker service (enqueue to completion) latency
556system.cpu0.itb.walker.walkCompletionTime::262144-327679 86 0.13% 99.90% # Table walker service (enqueue to completion) latency
557system.cpu0.itb.walker.walkCompletionTime::327680-393215 28 0.04% 99.94% # Table walker service (enqueue to completion) latency
558system.cpu0.itb.walker.walkCompletionTime::393216-458751 25 0.04% 99.97% # Table walker service (enqueue to completion) latency
559system.cpu0.itb.walker.walkCompletionTime::458752-524287 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
560system.cpu0.itb.walker.walkCompletionTime::524288-589823 8 0.01% 100.00% # Table walker service (enqueue to completion) latency
561system.cpu0.itb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
562system.cpu0.itb.walker.walkCompletionTime::total 67918 # Table walker service (enqueue to completion) latency
563system.cpu0.itb.walker.walksPending::samples 408740768228 # Table walker pending requests distribution
564system.cpu0.itb.walker.walksPending::mean 0.873449 # Table walker pending requests distribution
565system.cpu0.itb.walker.walksPending::stdev 0.332683 # Table walker pending requests distribution
566system.cpu0.itb.walker.walksPending::0 51752271292 12.66% 12.66% # Table walker pending requests distribution
567system.cpu0.itb.walker.walksPending::1 356965086936 87.33% 99.99% # Table walker pending requests distribution
568system.cpu0.itb.walker.walksPending::2 21879500 0.01% 100.00% # Table walker pending requests distribution
569system.cpu0.itb.walker.walksPending::3 1303500 0.00% 100.00% # Table walker pending requests distribution
570system.cpu0.itb.walker.walksPending::4 81500 0.00% 100.00% # Table walker pending requests distribution
571system.cpu0.itb.walker.walksPending::5 52500 0.00% 100.00% # Table walker pending requests distribution
572system.cpu0.itb.walker.walksPending::6 29500 0.00% 100.00% # Table walker pending requests distribution
573system.cpu0.itb.walker.walksPending::7 1000 0.00% 100.00% # Table walker pending requests distribution
574system.cpu0.itb.walker.walksPending::8 62500 0.00% 100.00% # Table walker pending requests distribution
575system.cpu0.itb.walker.walksPending::total 408740768228 # Table walker pending requests distribution
576system.cpu0.itb.walker.walkPageSizes::4K 57315 98.37% 98.37% # Table walker page sizes translated
577system.cpu0.itb.walker.walkPageSizes::2M 950 1.63% 100.00% # Table walker page sizes translated
578system.cpu0.itb.walker.walkPageSizes::total 58265 # Table walker page sizes translated
579system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
580system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 79903 # Table walker requests started/completed, data/inst
581system.cpu0.itb.walker.walkRequestOrigin_Requested::total 79903 # Table walker requests started/completed, data/inst
582system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
583system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 58265 # Table walker requests started/completed, data/inst
584system.cpu0.itb.walker.walkRequestOrigin_Completed::total 58265 # Table walker requests started/completed, data/inst
585system.cpu0.itb.walker.walkRequestOrigin::total 138168 # Table walker requests started/completed, data/inst
586system.cpu0.itb.inst_hits 207793696 # ITB inst hits
587system.cpu0.itb.inst_misses 79903 # ITB inst misses
588system.cpu0.itb.read_hits 0 # DTB read hits
589system.cpu0.itb.read_misses 0 # DTB read misses
590system.cpu0.itb.write_hits 0 # DTB write hits
591system.cpu0.itb.write_misses 0 # DTB write misses
592system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
593system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
594system.cpu0.itb.flush_tlb_mva_asid 46091 # Number of times TLB was flushed by MVA & ASID
595system.cpu0.itb.flush_tlb_asid 1084 # Number of times TLB was flushed by ASID
596system.cpu0.itb.flush_entries 24840 # Number of entries that have been flushed from TLB
597system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
598system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
599system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
600system.cpu0.itb.perms_faults 191050 # Number of TLB faults due to permissions restrictions
601system.cpu0.itb.read_accesses 0 # DTB read accesses
602system.cpu0.itb.write_accesses 0 # DTB write accesses
603system.cpu0.itb.inst_accesses 207873599 # ITB inst accesses
604system.cpu0.itb.hits 207793696 # DTB hits
605system.cpu0.itb.misses 79903 # DTB misses
606system.cpu0.itb.accesses 207873599 # DTB accesses
607system.cpu0.numCycles 761315266 # number of cpu cycles simulated
608system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
609system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
610system.cpu0.fetch.icacheStallCycles 84074114 # Number of cycles fetch is stalled on an Icache miss
611system.cpu0.fetch.Insts 585063894 # Number of instructions fetch has processed
612system.cpu0.fetch.Branches 132444225 # Number of branches that fetch encountered
613system.cpu0.fetch.predictedBranches 77977766 # Number of branches that fetch has predicted taken
614system.cpu0.fetch.Cycles 631770796 # Number of cycles fetch has run and was not squashing or blocked
615system.cpu0.fetch.SquashCycles 13765762 # Number of cycles fetch has spent squashing
616system.cpu0.fetch.TlbCycles 1785587 # Number of cycles fetch has spent waiting for tlb
617system.cpu0.fetch.MiscStallCycles 318737 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
618system.cpu0.fetch.PendingTrapStallCycles 5559321 # Number of stall cycles due to pending traps
619system.cpu0.fetch.PendingQuiesceStallCycles 752999 # Number of stall cycles due to pending quiesce instructions
620system.cpu0.fetch.IcacheWaitRetryStallCycles 796339 # Number of stall cycles due to full MSHR
621system.cpu0.fetch.CacheLines 207603742 # Number of cache lines fetched
622system.cpu0.fetch.IcacheSquashes 1586738 # Number of outstanding Icache misses that were squashed
623system.cpu0.fetch.ItlbSquashes 26136 # Number of outstanding ITLB misses that were squashed
624system.cpu0.fetch.rateDist::samples 731940774 # Number of instructions fetched each cycle (Total)
625system.cpu0.fetch.rateDist::mean 0.936268 # Number of instructions fetched each cycle (Total)
626system.cpu0.fetch.rateDist::stdev 1.209570 # Number of instructions fetched each cycle (Total)
627system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
628system.cpu0.fetch.rateDist::0 403543312 55.13% 55.13% # Number of instructions fetched each cycle (Total)
629system.cpu0.fetch.rateDist::1 128205713 17.52% 72.65% # Number of instructions fetched each cycle (Total)
630system.cpu0.fetch.rateDist::2 43488128 5.94% 78.59% # Number of instructions fetched each cycle (Total)
631system.cpu0.fetch.rateDist::3 156703621 21.41% 100.00% # Number of instructions fetched each cycle (Total)
632system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
633system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
634system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
635system.cpu0.fetch.rateDist::total 731940774 # Number of instructions fetched each cycle (Total)
636system.cpu0.fetch.branchRate 0.173968 # Number of branch fetches per cycle
637system.cpu0.fetch.rate 0.768491 # Number of inst fetches per cycle
638system.cpu0.decode.IdleCycles 100319911 # Number of cycles decode is idle
639system.cpu0.decode.BlockedCycles 372509653 # Number of cycles decode is blocked
640system.cpu0.decode.RunCycles 217857253 # Number of cycles decode is running
641system.cpu0.decode.UnblockCycles 36338079 # Number of cycles decode is unblocking
642system.cpu0.decode.SquashCycles 4915878 # Number of cycles decode is squashing
643system.cpu0.decode.BranchResolved 18873695 # Number of times decode resolved a branch
644system.cpu0.decode.BranchMispred 2004301 # Number of times decode detected a branch misprediction
645system.cpu0.decode.DecodedInsts 606758178 # Number of instructions handled by decode
646system.cpu0.decode.SquashedInsts 22350639 # Number of squashed instructions handled by decode
647system.cpu0.rename.SquashCycles 4915878 # Number of cycles rename is squashing
648system.cpu0.rename.IdleCycles 134368949 # Number of cycles rename is idle
649system.cpu0.rename.BlockCycles 57393762 # Number of cycles rename is blocking
650system.cpu0.rename.serializeStallCycles 239367965 # count of cycles rename stalled for serializing inst
651system.cpu0.rename.RunCycles 219640614 # Number of cycles rename is running
652system.cpu0.rename.UnblockCycles 76253606 # Number of cycles rename is unblocking
653system.cpu0.rename.RenamedInsts 590337881 # Number of instructions processed by rename
654system.cpu0.rename.SquashedInsts 5891778 # Number of squashed instructions processed by rename
655system.cpu0.rename.ROBFullEvents 10879657 # Number of times rename has blocked due to ROB full
656system.cpu0.rename.IQFullEvents 272900 # Number of times rename has blocked due to IQ full
657system.cpu0.rename.LQFullEvents 275104 # Number of times rename has blocked due to LQ full
658system.cpu0.rename.SQFullEvents 42478331 # Number of times rename has blocked due to SQ full
659system.cpu0.rename.FullRegisterEvents 10735 # Number of times there has been no free registers
660system.cpu0.rename.RenamedOperands 562575259 # Number of destination operands rename has renamed
661system.cpu0.rename.RenameLookups 912365987 # Number of register rename lookups that rename has made
662system.cpu0.rename.int_rename_lookups 697390419 # Number of integer rename lookups
663system.cpu0.rename.fp_rename_lookups 694396 # Number of floating rename lookups
664system.cpu0.rename.CommittedMaps 507972674 # Number of HB maps that are committed
665system.cpu0.rename.UndoneMaps 54602579 # Number of HB maps that are undone due to squashing
666system.cpu0.rename.serializingInsts 15164295 # count of serializing insts renamed
667system.cpu0.rename.tempSerializingInsts 13334098 # count of temporary serializing insts renamed
668system.cpu0.rename.skidInsts 72899123 # count of insts added to the skid buffer
669system.cpu0.memDep0.insertedLoads 96066209 # Number of loads inserted to the mem dependence unit.
670system.cpu0.memDep0.insertedStores 83257958 # Number of stores inserted to the mem dependence unit.
671system.cpu0.memDep0.conflictingLoads 8637114 # Number of conflicting loads.
672system.cpu0.memDep0.conflictingStores 7533431 # Number of conflicting stores.
673system.cpu0.iq.iqInstsAdded 568637659 # Number of instructions added to the IQ (excludes non-spec)
674system.cpu0.iq.iqNonSpecInstsAdded 15304177 # Number of non-speculative instructions added to the IQ
675system.cpu0.iq.iqInstsIssued 573527019 # Number of instructions issued
676system.cpu0.iq.iqSquashedInstsIssued 2573483 # Number of squashed instructions issued
677system.cpu0.iq.iqSquashedInstsExamined 51469570 # Number of squashed instructions iterated over during squash; mainly for profiling
678system.cpu0.iq.iqSquashedOperandsExamined 33194366 # Number of squashed operands that are examined and possibly removed from graph
679system.cpu0.iq.iqSquashedNonSpecRemoved 252301 # Number of squashed non-spec instructions that were removed
680system.cpu0.iq.issued_per_cycle::samples 731940774 # Number of insts issued each cycle
681system.cpu0.iq.issued_per_cycle::mean 0.783570 # Number of insts issued each cycle
682system.cpu0.iq.issued_per_cycle::stdev 1.057506 # Number of insts issued each cycle
683system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
684system.cpu0.iq.issued_per_cycle::0 419086912 57.26% 57.26% # Number of insts issued each cycle
685system.cpu0.iq.issued_per_cycle::1 131041268 17.90% 75.16% # Number of insts issued each cycle
686system.cpu0.iq.issued_per_cycle::2 110621862 15.11% 90.27% # Number of insts issued each cycle
687system.cpu0.iq.issued_per_cycle::3 63525040 8.68% 98.95% # Number of insts issued each cycle
688system.cpu0.iq.issued_per_cycle::4 7661553 1.05% 100.00% # Number of insts issued each cycle
689system.cpu0.iq.issued_per_cycle::5 4139 0.00% 100.00% # Number of insts issued each cycle
690system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
691system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
692system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
693system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
694system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
695system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
696system.cpu0.iq.issued_per_cycle::total 731940774 # Number of insts issued each cycle
697system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
698system.cpu0.iq.fu_full::IntAlu 59257381 45.13% 45.13% # attempts to use FU when none available
699system.cpu0.iq.fu_full::IntMult 46667 0.04% 45.16% # attempts to use FU when none available
700system.cpu0.iq.fu_full::IntDiv 17941 0.01% 45.18% # attempts to use FU when none available
701system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.18% # attempts to use FU when none available
702system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.18% # attempts to use FU when none available
703system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.18% # attempts to use FU when none available
704system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.18% # attempts to use FU when none available
705system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.18% # attempts to use FU when none available
706system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.18% # attempts to use FU when none available
707system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.18% # attempts to use FU when none available
708system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.18% # attempts to use FU when none available
709system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.18% # attempts to use FU when none available
710system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.18% # attempts to use FU when none available
711system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.18% # attempts to use FU when none available
712system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.18% # attempts to use FU when none available
713system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.18% # attempts to use FU when none available
714system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.18% # attempts to use FU when none available
715system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.18% # attempts to use FU when none available
716system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.18% # attempts to use FU when none available
717system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.18% # attempts to use FU when none available
718system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.18% # attempts to use FU when none available
719system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.18% # attempts to use FU when none available
720system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.18% # attempts to use FU when none available
721system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.18% # attempts to use FU when none available
722system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.18% # attempts to use FU when none available
723system.cpu0.iq.fu_full::SimdFloatMisc 17 0.00% 45.18% # attempts to use FU when none available
724system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.18% # attempts to use FU when none available
725system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.18% # attempts to use FU when none available
726system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.18% # attempts to use FU when none available
727system.cpu0.iq.fu_full::MemRead 34285997 26.11% 71.29% # attempts to use FU when none available
728system.cpu0.iq.fu_full::MemWrite 37701656 28.71% 100.00% # attempts to use FU when none available
729system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
730system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
731system.cpu0.iq.FU_type_0::No_OpClass 17 0.00% 0.00% # Type of FU issued
732system.cpu0.iq.FU_type_0::IntAlu 391712029 68.30% 68.30% # Type of FU issued
733system.cpu0.iq.FU_type_0::IntMult 1330798 0.23% 68.53% # Type of FU issued
734system.cpu0.iq.FU_type_0::IntDiv 69152 0.01% 68.54% # Type of FU issued
735system.cpu0.iq.FU_type_0::FloatAdd 6 0.00% 68.54% # Type of FU issued
736system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.54% # Type of FU issued
737system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.54% # Type of FU issued
738system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.54% # Type of FU issued
739system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.54% # Type of FU issued
740system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.54% # Type of FU issued
741system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.54% # Type of FU issued
742system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.54% # Type of FU issued
743system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 68.54% # Type of FU issued
744system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.54% # Type of FU issued
745system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.54% # Type of FU issued
746system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.54% # Type of FU issued
747system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.54% # Type of FU issued
748system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.54% # Type of FU issued
749system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.54% # Type of FU issued
750system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.54% # Type of FU issued
751system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.54% # Type of FU issued
752system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.54% # Type of FU issued
753system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.54% # Type of FU issued
754system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.54% # Type of FU issued
755system.cpu0.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.54% # Type of FU issued
756system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.54% # Type of FU issued
757system.cpu0.iq.FU_type_0::SimdFloatMisc 42956 0.01% 68.55% # Type of FU issued
758system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.55% # Type of FU issued
759system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.55% # Type of FU issued
760system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.55% # Type of FU issued
761system.cpu0.iq.FU_type_0::MemRead 99049842 17.27% 85.82% # Type of FU issued
762system.cpu0.iq.FU_type_0::MemWrite 81322170 14.18% 100.00% # Type of FU issued
763system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
764system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
765system.cpu0.iq.FU_type_0::total 573527019 # Type of FU issued
766system.cpu0.iq.rate 0.753337 # Inst issue rate
767system.cpu0.iq.fu_busy_cnt 131309659 # FU busy when requested
768system.cpu0.iq.fu_busy_rate 0.228951 # FU busy rate (busy events/executed inst)
769system.cpu0.iq.int_inst_queue_reads 2011763518 # Number of integer instruction queue reads
770system.cpu0.iq.int_inst_queue_writes 635110276 # Number of integer instruction queue writes
771system.cpu0.iq.int_inst_queue_wakeup_accesses 556950573 # Number of integer instruction queue wakeup accesses
772system.cpu0.iq.fp_inst_queue_reads 1114436 # Number of floating instruction queue reads
773system.cpu0.iq.fp_inst_queue_writes 438215 # Number of floating instruction queue writes
774system.cpu0.iq.fp_inst_queue_wakeup_accesses 411063 # Number of floating instruction queue wakeup accesses
775system.cpu0.iq.int_alu_accesses 704141671 # Number of integer alu accesses
776system.cpu0.iq.fp_alu_accesses 694990 # Number of floating point alu accesses
777system.cpu0.iew.lsq.thread0.forwLoads 2575949 # Number of loads that had data forwarded from stores
778system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
779system.cpu0.iew.lsq.thread0.squashedLoads 11750995 # Number of loads squashed
780system.cpu0.iew.lsq.thread0.ignoredResponses 17228 # Number of memory responses ignored because the instruction is squashed
781system.cpu0.iew.lsq.thread0.memOrderViolation 138196 # Number of memory ordering violations
782system.cpu0.iew.lsq.thread0.squashedStores 5318019 # Number of stores squashed
783system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
784system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
785system.cpu0.iew.lsq.thread0.rescheduledLoads 2553185 # Number of loads that were rescheduled
786system.cpu0.iew.lsq.thread0.cacheBlocked 4584143 # Number of times an access to memory failed due to the cache being blocked
787system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
788system.cpu0.iew.iewSquashCycles 4915878 # Number of cycles IEW is squashing
789system.cpu0.iew.iewBlockCycles 6708218 # Number of cycles IEW is blocking
790system.cpu0.iew.iewUnblockCycles 2698388 # Number of cycles IEW is unblocking
791system.cpu0.iew.iewDispatchedInsts 584066483 # Number of instructions dispatched to IQ
792system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
793system.cpu0.iew.iewDispLoadInsts 96066209 # Number of dispatched load instructions
794system.cpu0.iew.iewDispStoreInsts 83257958 # Number of dispatched store instructions
795system.cpu0.iew.iewDispNonSpecInsts 13102761 # Number of dispatched non-speculative instructions
796system.cpu0.iew.iewIQFullEvents 64235 # Number of times the IQ has become full, causing a stall
797system.cpu0.iew.iewLSQFullEvents 2566402 # Number of times the LSQ has become full, causing a stall
798system.cpu0.iew.memOrderViolationEvents 138196 # Number of memory order violations
799system.cpu0.iew.predictedTakenIncorrect 1807441 # Number of branches that were predicted taken incorrectly
800system.cpu0.iew.predictedNotTakenIncorrect 2958148 # Number of branches that were predicted not taken incorrectly
801system.cpu0.iew.branchMispredicts 4765589 # Number of branch mispredicts detected at execute
802system.cpu0.iew.iewExecutedInsts 565930325 # Number of executed instructions
803system.cpu0.iew.iewExecLoadInsts 96085763 # Number of load instructions executed
804system.cpu0.iew.iewExecSquashedInsts 7069222 # Number of squashed instructions skipped in execute
805system.cpu0.iew.exec_swp 0 # number of swp insts executed
806system.cpu0.iew.exec_nop 124647 # number of nop insts executed
807system.cpu0.iew.exec_refs 176196325 # number of memory reference insts executed
808system.cpu0.iew.exec_branches 106580080 # Number of branches executed
809system.cpu0.iew.exec_stores 80110562 # Number of stores executed
810system.cpu0.iew.exec_rate 0.743359 # Inst execution rate
811system.cpu0.iew.wb_sent 558072531 # cumulative count of insts sent to commit
812system.cpu0.iew.wb_count 557361636 # cumulative count of insts written-back
813system.cpu0.iew.wb_producers 269759058 # num instructions producing a value
814system.cpu0.iew.wb_consumers 442874225 # num instructions consuming a value
815system.cpu0.iew.wb_rate 0.732104 # insts written-back per cycle
816system.cpu0.iew.wb_fanout 0.609110 # average fanout of values written-back
817system.cpu0.commit.commitSquashedInsts 44855365 # The number of squashed insts skipped by commit
818system.cpu0.commit.commitNonSpecStalls 15051876 # The number of times commit has been forced to stall to communicate backwards
819system.cpu0.commit.branchMispredicts 4433751 # The number of times a branch was mispredicted
820system.cpu0.commit.committed_per_cycle::samples 723417587 # Number of insts commited each cycle
821system.cpu0.commit.committed_per_cycle::mean 0.736051 # Number of insts commited each cycle
822system.cpu0.commit.committed_per_cycle::stdev 1.544488 # Number of insts commited each cycle
823system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
824system.cpu0.commit.committed_per_cycle::0 490442876 67.80% 67.80% # Number of insts commited each cycle
825system.cpu0.commit.committed_per_cycle::1 120876307 16.71% 84.50% # Number of insts commited each cycle
826system.cpu0.commit.committed_per_cycle::2 51465837 7.11% 91.62% # Number of insts commited each cycle
827system.cpu0.commit.committed_per_cycle::3 17138323 2.37% 93.99% # Number of insts commited each cycle
828system.cpu0.commit.committed_per_cycle::4 12635808 1.75% 95.73% # Number of insts commited each cycle
829system.cpu0.commit.committed_per_cycle::5 8409902 1.16% 96.90% # Number of insts commited each cycle
830system.cpu0.commit.committed_per_cycle::6 5731195 0.79% 97.69% # Number of insts commited each cycle
831system.cpu0.commit.committed_per_cycle::7 3469312 0.48% 98.17% # Number of insts commited each cycle
832system.cpu0.commit.committed_per_cycle::8 13248027 1.83% 100.00% # Number of insts commited each cycle
833system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
834system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
835system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
836system.cpu0.commit.committed_per_cycle::total 723417587 # Number of insts commited each cycle
837system.cpu0.commit.committedInsts 452974919 # Number of instructions committed
838system.cpu0.commit.committedOps 532472262 # Number of ops (including micro ops) committed
839system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
840system.cpu0.commit.refs 162255152 # Number of memory references committed
841system.cpu0.commit.loads 84315213 # Number of loads committed
842system.cpu0.commit.membars 3606698 # Number of memory barriers committed
843system.cpu0.commit.branches 101352780 # Number of branches committed
844system.cpu0.commit.fp_insts 403239 # Number of committed floating point instructions.
845system.cpu0.commit.int_insts 488332622 # Number of committed integer instructions.
846system.cpu0.commit.function_calls 13274605 # Number of function calls committed.
847system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
848system.cpu0.commit.op_class_0::IntAlu 369012489 69.30% 69.30% # Class of committed instruction
849system.cpu0.commit.op_class_0::IntMult 1112277 0.21% 69.51% # Class of committed instruction
850system.cpu0.commit.op_class_0::IntDiv 54460 0.01% 69.52% # Class of committed instruction
851system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction
852system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction
853system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction
854system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction
855system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction
856system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction
857system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction
858system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction
859system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction
860system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction
861system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction
862system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction
863system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction
864system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction
865system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction
866system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction
867system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction
868system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.52% # Class of committed instruction
869system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction
870system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.52% # Class of committed instruction
871system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.52% # Class of committed instruction
872system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction
873system.cpu0.commit.op_class_0::SimdFloatMisc 37842 0.01% 69.53% # Class of committed instruction
874system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction
875system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction
876system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction
877system.cpu0.commit.op_class_0::MemRead 84315213 15.83% 85.36% # Class of committed instruction
878system.cpu0.commit.op_class_0::MemWrite 77939939 14.64% 100.00% # Class of committed instruction
879system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
880system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
881system.cpu0.commit.op_class_0::total 532472262 # Class of committed instruction
882system.cpu0.commit.bw_lim_events 13248027 # number cycles where commit BW limit reached
883system.cpu0.rob.rob_reads 1283601950 # The number of ROB reads
884system.cpu0.rob.rob_writes 1163144719 # The number of ROB writes
885system.cpu0.timesIdled 940575 # Number of times that the entire CPU went into an idle state and unscheduled itself
886system.cpu0.idleCycles 29374492 # Total number of cycles that the CPU has spent unscheduled due to idling
887system.cpu0.quiesceCycles 94176188727 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
888system.cpu0.committedInsts 452974919 # Number of Instructions Simulated
889system.cpu0.committedOps 532472262 # Number of Ops (including micro ops) Simulated
890system.cpu0.cpi 1.680701 # CPI: Cycles Per Instruction
891system.cpu0.cpi_total 1.680701 # CPI: Total CPI of All Threads
892system.cpu0.ipc 0.594990 # IPC: Instructions Per Cycle
893system.cpu0.ipc_total 0.594990 # IPC: Total IPC of All Threads
894system.cpu0.int_regfile_reads 668586496 # number of integer regfile reads
895system.cpu0.int_regfile_writes 395947855 # number of integer regfile writes
896system.cpu0.fp_regfile_reads 683579 # number of floating regfile reads
897system.cpu0.fp_regfile_writes 295852 # number of floating regfile writes
898system.cpu0.cc_regfile_reads 123538962 # number of cc regfile reads
899system.cpu0.cc_regfile_writes 124272565 # number of cc regfile writes
900system.cpu0.misc_regfile_reads 1278649841 # number of misc regfile reads
901system.cpu0.misc_regfile_writes 15273032 # number of misc regfile writes
902system.cpu0.dcache.tags.replacements 5802522 # number of replacements
903system.cpu0.dcache.tags.tagsinuse 485.093904 # Cycle average of tags in use
904system.cpu0.dcache.tags.total_refs 150368529 # Total number of references to valid blocks.
905system.cpu0.dcache.tags.sampled_refs 5803033 # Sample count of references to valid blocks.
906system.cpu0.dcache.tags.avg_refs 25.912058 # Average number of references to valid blocks.
907system.cpu0.dcache.tags.warmup_cycle 2962390000 # Cycle when the warmup percentage was hit.
908system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.093904 # Average occupied blocks per requestor
909system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947449 # Average percentage of cache occupancy
910system.cpu0.dcache.tags.occ_percent::total 0.947449 # Average percentage of cache occupancy
911system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
912system.cpu0.dcache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
913system.cpu0.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id
914system.cpu0.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
915system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
916system.cpu0.dcache.tags.tag_accesses 336490622 # Number of tag accesses
917system.cpu0.dcache.tags.data_accesses 336490622 # Number of data accesses
918system.cpu0.dcache.ReadReq_hits::cpu0.data 77978502 # number of ReadReq hits
919system.cpu0.dcache.ReadReq_hits::total 77978502 # number of ReadReq hits
920system.cpu0.dcache.WriteReq_hits::cpu0.data 67507915 # number of WriteReq hits
921system.cpu0.dcache.WriteReq_hits::total 67507915 # number of WriteReq hits
922system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199394 # number of SoftPFReq hits
923system.cpu0.dcache.SoftPFReq_hits::total 199394 # number of SoftPFReq hits
924system.cpu0.dcache.WriteLineReq_hits::cpu0.data 171803 # number of WriteLineReq hits
925system.cpu0.dcache.WriteLineReq_hits::total 171803 # number of WriteLineReq hits
926system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1821693 # number of LoadLockedReq hits
927system.cpu0.dcache.LoadLockedReq_hits::total 1821693 # number of LoadLockedReq hits
928system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1835435 # number of StoreCondReq hits
929system.cpu0.dcache.StoreCondReq_hits::total 1835435 # number of StoreCondReq hits
930system.cpu0.dcache.demand_hits::cpu0.data 145658220 # number of demand (read+write) hits
931system.cpu0.dcache.demand_hits::total 145658220 # number of demand (read+write) hits
932system.cpu0.dcache.overall_hits::cpu0.data 145857614 # number of overall hits
933system.cpu0.dcache.overall_hits::total 145857614 # number of overall hits
934system.cpu0.dcache.ReadReq_misses::cpu0.data 6410027 # number of ReadReq misses
935system.cpu0.dcache.ReadReq_misses::total 6410027 # number of ReadReq misses
936system.cpu0.dcache.WriteReq_misses::cpu0.data 7429665 # number of WriteReq misses
937system.cpu0.dcache.WriteReq_misses::total 7429665 # number of WriteReq misses
938system.cpu0.dcache.SoftPFReq_misses::cpu0.data 719434 # number of SoftPFReq misses
939system.cpu0.dcache.SoftPFReq_misses::total 719434 # number of SoftPFReq misses
940system.cpu0.dcache.WriteLineReq_misses::cpu0.data 793389 # number of WriteLineReq misses
941system.cpu0.dcache.WriteLineReq_misses::total 793389 # number of WriteLineReq misses
942system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 238145 # number of LoadLockedReq misses
943system.cpu0.dcache.LoadLockedReq_misses::total 238145 # number of LoadLockedReq misses
944system.cpu0.dcache.StoreCondReq_misses::cpu0.data 190782 # number of StoreCondReq misses
945system.cpu0.dcache.StoreCondReq_misses::total 190782 # number of StoreCondReq misses
946system.cpu0.dcache.demand_misses::cpu0.data 14633081 # number of demand (read+write) misses
947system.cpu0.dcache.demand_misses::total 14633081 # number of demand (read+write) misses
948system.cpu0.dcache.overall_misses::cpu0.data 15352515 # number of overall misses
949system.cpu0.dcache.overall_misses::total 15352515 # number of overall misses
950system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 109062490500 # number of ReadReq miss cycles
951system.cpu0.dcache.ReadReq_miss_latency::total 109062490500 # number of ReadReq miss cycles
952system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 171373805000 # number of WriteReq miss cycles
953system.cpu0.dcache.WriteReq_miss_latency::total 171373805000 # number of WriteReq miss cycles
954system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 50210173040 # number of WriteLineReq miss cycles
955system.cpu0.dcache.WriteLineReq_miss_latency::total 50210173040 # number of WriteLineReq miss cycles
956system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3622154000 # number of LoadLockedReq miss cycles
957system.cpu0.dcache.LoadLockedReq_miss_latency::total 3622154000 # number of LoadLockedReq miss cycles
958system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5311494500 # number of StoreCondReq miss cycles
959system.cpu0.dcache.StoreCondReq_miss_latency::total 5311494500 # number of StoreCondReq miss cycles
960system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5825000 # number of StoreCondFailReq miss cycles
961system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5825000 # number of StoreCondFailReq miss cycles
962system.cpu0.dcache.demand_miss_latency::cpu0.data 330646468540 # number of demand (read+write) miss cycles
963system.cpu0.dcache.demand_miss_latency::total 330646468540 # number of demand (read+write) miss cycles
964system.cpu0.dcache.overall_miss_latency::cpu0.data 330646468540 # number of overall miss cycles
965system.cpu0.dcache.overall_miss_latency::total 330646468540 # number of overall miss cycles
966system.cpu0.dcache.ReadReq_accesses::cpu0.data 84388529 # number of ReadReq accesses(hits+misses)
967system.cpu0.dcache.ReadReq_accesses::total 84388529 # number of ReadReq accesses(hits+misses)
968system.cpu0.dcache.WriteReq_accesses::cpu0.data 74937580 # number of WriteReq accesses(hits+misses)
969system.cpu0.dcache.WriteReq_accesses::total 74937580 # number of WriteReq accesses(hits+misses)
970system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 918828 # number of SoftPFReq accesses(hits+misses)
971system.cpu0.dcache.SoftPFReq_accesses::total 918828 # number of SoftPFReq accesses(hits+misses)
972system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 965192 # number of WriteLineReq accesses(hits+misses)
973system.cpu0.dcache.WriteLineReq_accesses::total 965192 # number of WriteLineReq accesses(hits+misses)
974system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2059838 # number of LoadLockedReq accesses(hits+misses)
975system.cpu0.dcache.LoadLockedReq_accesses::total 2059838 # number of LoadLockedReq accesses(hits+misses)
976system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2026217 # number of StoreCondReq accesses(hits+misses)
977system.cpu0.dcache.StoreCondReq_accesses::total 2026217 # number of StoreCondReq accesses(hits+misses)
978system.cpu0.dcache.demand_accesses::cpu0.data 160291301 # number of demand (read+write) accesses
979system.cpu0.dcache.demand_accesses::total 160291301 # number of demand (read+write) accesses
980system.cpu0.dcache.overall_accesses::cpu0.data 161210129 # number of overall (read+write) accesses
981system.cpu0.dcache.overall_accesses::total 161210129 # number of overall (read+write) accesses
982system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075959 # miss rate for ReadReq accesses
983system.cpu0.dcache.ReadReq_miss_rate::total 0.075959 # miss rate for ReadReq accesses
984system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.099145 # miss rate for WriteReq accesses
985system.cpu0.dcache.WriteReq_miss_rate::total 0.099145 # miss rate for WriteReq accesses
986system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.782991 # miss rate for SoftPFReq accesses
987system.cpu0.dcache.SoftPFReq_miss_rate::total 0.782991 # miss rate for SoftPFReq accesses
988system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.822001 # miss rate for WriteLineReq accesses
989system.cpu0.dcache.WriteLineReq_miss_rate::total 0.822001 # miss rate for WriteLineReq accesses
990system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.115613 # miss rate for LoadLockedReq accesses
991system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.115613 # miss rate for LoadLockedReq accesses
992system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.094157 # miss rate for StoreCondReq accesses
993system.cpu0.dcache.StoreCondReq_miss_rate::total 0.094157 # miss rate for StoreCondReq accesses
994system.cpu0.dcache.demand_miss_rate::cpu0.data 0.091291 # miss rate for demand accesses
995system.cpu0.dcache.demand_miss_rate::total 0.091291 # miss rate for demand accesses
996system.cpu0.dcache.overall_miss_rate::cpu0.data 0.095233 # miss rate for overall accesses
997system.cpu0.dcache.overall_miss_rate::total 0.095233 # miss rate for overall accesses
998system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17014.357428 # average ReadReq miss latency
999system.cpu0.dcache.ReadReq_avg_miss_latency::total 17014.357428 # average ReadReq miss latency
1000system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23066.155069 # average WriteReq miss latency
1001system.cpu0.dcache.WriteReq_avg_miss_latency::total 23066.155069 # average WriteReq miss latency
1002system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 63285.693449 # average WriteLineReq miss latency
1003system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 63285.693449 # average WriteLineReq miss latency
1004system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15209.867938 # average LoadLockedReq miss latency
1005system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15209.867938 # average LoadLockedReq miss latency
1006system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 27840.647965 # average StoreCondReq miss latency
1007system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 27840.647965 # average StoreCondReq miss latency
1008system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
1009system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1010system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22595.820288 # average overall miss latency
1011system.cpu0.dcache.demand_avg_miss_latency::total 22595.820288 # average overall miss latency
1012system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21536.957856 # average overall miss latency
1013system.cpu0.dcache.overall_avg_miss_latency::total 21536.957856 # average overall miss latency
1014system.cpu0.dcache.blocked_cycles::no_mshrs 15517119 # number of cycles access was blocked
1015system.cpu0.dcache.blocked_cycles::no_targets 25638833 # number of cycles access was blocked
1016system.cpu0.dcache.blocked::no_mshrs 732854 # number of cycles access was blocked
1017system.cpu0.dcache.blocked::no_targets 730129 # number of cycles access was blocked
1018system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.173548 # average number of cycles each access was blocked
1019system.cpu0.dcache.avg_blocked_cycles::no_targets 35.115484 # average number of cycles each access was blocked
1020system.cpu0.dcache.writebacks::writebacks 5802538 # number of writebacks
1021system.cpu0.dcache.writebacks::total 5802538 # number of writebacks
1022system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3327729 # number of ReadReq MSHR hits
1023system.cpu0.dcache.ReadReq_mshr_hits::total 3327729 # number of ReadReq MSHR hits
1024system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5970882 # number of WriteReq MSHR hits
1025system.cpu0.dcache.WriteReq_mshr_hits::total 5970882 # number of WriteReq MSHR hits
1026system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4398 # number of WriteLineReq MSHR hits
1027system.cpu0.dcache.WriteLineReq_mshr_hits::total 4398 # number of WriteLineReq MSHR hits
1028system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 123286 # number of LoadLockedReq MSHR hits
1029system.cpu0.dcache.LoadLockedReq_mshr_hits::total 123286 # number of LoadLockedReq MSHR hits
1030system.cpu0.dcache.demand_mshr_hits::cpu0.data 9303009 # number of demand (read+write) MSHR hits
1031system.cpu0.dcache.demand_mshr_hits::total 9303009 # number of demand (read+write) MSHR hits
1032system.cpu0.dcache.overall_mshr_hits::cpu0.data 9303009 # number of overall MSHR hits
1033system.cpu0.dcache.overall_mshr_hits::total 9303009 # number of overall MSHR hits
1034system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3082298 # number of ReadReq MSHR misses
1035system.cpu0.dcache.ReadReq_mshr_misses::total 3082298 # number of ReadReq MSHR misses
1036system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1458783 # number of WriteReq MSHR misses
1037system.cpu0.dcache.WriteReq_mshr_misses::total 1458783 # number of WriteReq MSHR misses
1038system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 712505 # number of SoftPFReq MSHR misses
1039system.cpu0.dcache.SoftPFReq_mshr_misses::total 712505 # number of SoftPFReq MSHR misses
1040system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 788991 # number of WriteLineReq MSHR misses
1041system.cpu0.dcache.WriteLineReq_mshr_misses::total 788991 # number of WriteLineReq MSHR misses
1042system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 114859 # number of LoadLockedReq MSHR misses
1043system.cpu0.dcache.LoadLockedReq_mshr_misses::total 114859 # number of LoadLockedReq MSHR misses
1044system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 190777 # number of StoreCondReq MSHR misses
1045system.cpu0.dcache.StoreCondReq_mshr_misses::total 190777 # number of StoreCondReq MSHR misses
1046system.cpu0.dcache.demand_mshr_misses::cpu0.data 5330072 # number of demand (read+write) MSHR misses
1047system.cpu0.dcache.demand_mshr_misses::total 5330072 # number of demand (read+write) MSHR misses
1048system.cpu0.dcache.overall_mshr_misses::cpu0.data 6042577 # number of overall MSHR misses
1049system.cpu0.dcache.overall_mshr_misses::total 6042577 # number of overall MSHR misses
1050system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 19706 # number of ReadReq MSHR uncacheable
1051system.cpu0.dcache.ReadReq_mshr_uncacheable::total 19706 # number of ReadReq MSHR uncacheable
1052system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 21266 # number of WriteReq MSHR uncacheable
1053system.cpu0.dcache.WriteReq_mshr_uncacheable::total 21266 # number of WriteReq MSHR uncacheable
1054system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 40972 # number of overall MSHR uncacheable misses
1055system.cpu0.dcache.overall_mshr_uncacheable_misses::total 40972 # number of overall MSHR uncacheable misses
1056system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 48302897000 # number of ReadReq MSHR miss cycles
1057system.cpu0.dcache.ReadReq_mshr_miss_latency::total 48302897000 # number of ReadReq MSHR miss cycles
1058system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 39166129612 # number of WriteReq MSHR miss cycles
1059system.cpu0.dcache.WriteReq_mshr_miss_latency::total 39166129612 # number of WriteReq MSHR miss cycles
1060system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 19342072500 # number of SoftPFReq MSHR miss cycles
1061system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 19342072500 # number of SoftPFReq MSHR miss cycles
1062system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 49145395540 # number of WriteLineReq MSHR miss cycles
1063system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 49145395540 # number of WriteLineReq MSHR miss cycles
1064system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1672767500 # number of LoadLockedReq MSHR miss cycles
1065system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1672767500 # number of LoadLockedReq MSHR miss cycles
1066system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5120787500 # number of StoreCondReq MSHR miss cycles
1067system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5120787500 # number of StoreCondReq MSHR miss cycles
1068system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5755000 # number of StoreCondFailReq MSHR miss cycles
1069system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5755000 # number of StoreCondFailReq MSHR miss cycles
1070system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 136614422152 # number of demand (read+write) MSHR miss cycles
1071system.cpu0.dcache.demand_mshr_miss_latency::total 136614422152 # number of demand (read+write) MSHR miss cycles
1072system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 155956494652 # number of overall MSHR miss cycles
1073system.cpu0.dcache.overall_mshr_miss_latency::total 155956494652 # number of overall MSHR miss cycles
1074system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3863694500 # number of ReadReq MSHR uncacheable cycles
1075system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3863694500 # number of ReadReq MSHR uncacheable cycles
1076system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3863694500 # number of overall MSHR uncacheable cycles
1077system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3863694500 # number of overall MSHR uncacheable cycles
1078system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036525 # mshr miss rate for ReadReq accesses
1079system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036525 # mshr miss rate for ReadReq accesses
1080system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019467 # mshr miss rate for WriteReq accesses
1081system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019467 # mshr miss rate for WriteReq accesses
1082system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.775450 # mshr miss rate for SoftPFReq accesses
1083system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.775450 # mshr miss rate for SoftPFReq accesses
1084system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.817445 # mshr miss rate for WriteLineReq accesses
1085system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.817445 # mshr miss rate for WriteLineReq accesses
1086system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055761 # mshr miss rate for LoadLockedReq accesses
1087system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055761 # mshr miss rate for LoadLockedReq accesses
1088system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.094154 # mshr miss rate for StoreCondReq accesses
1089system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.094154 # mshr miss rate for StoreCondReq accesses
1090system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.033252 # mshr miss rate for demand accesses
1091system.cpu0.dcache.demand_mshr_miss_rate::total 0.033252 # mshr miss rate for demand accesses
1092system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.037483 # mshr miss rate for overall accesses
1093system.cpu0.dcache.overall_mshr_miss_rate::total 0.037483 # mshr miss rate for overall accesses
1094system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15671.066522 # average ReadReq mshr miss latency
1095system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15671.066522 # average ReadReq mshr miss latency
1096system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26848.496049 # average WriteReq mshr miss latency
1097system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26848.496049 # average WriteReq mshr miss latency
1098system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 27146.577919 # average SoftPFReq mshr miss latency
1099system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 27146.577919 # average SoftPFReq mshr miss latency
1100system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 62288.917795 # average WriteLineReq mshr miss latency
1101system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 62288.917795 # average WriteLineReq mshr miss latency
1102system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14563.660662 # average LoadLockedReq mshr miss latency
1103system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14563.660662 # average LoadLockedReq mshr miss latency
1104system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 26841.744550 # average StoreCondReq mshr miss latency
1105system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26841.744550 # average StoreCondReq mshr miss latency
1106system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
1107system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1108system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25630.877435 # average overall mshr miss latency
1109system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25630.877435 # average overall mshr miss latency
1110system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25809.599886 # average overall mshr miss latency
1111system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25809.599886 # average overall mshr miss latency
1112system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196066.908556 # average ReadReq mshr uncacheable latency
1113system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196066.908556 # average ReadReq mshr uncacheable latency
1114system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 94300.851801 # average overall mshr uncacheable latency
1115system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 94300.851801 # average overall mshr uncacheable latency
1116system.cpu0.icache.tags.replacements 5681079 # number of replacements
1117system.cpu0.icache.tags.tagsinuse 511.944679 # Cycle average of tags in use
1118system.cpu0.icache.tags.total_refs 201561746 # Total number of references to valid blocks.
1119system.cpu0.icache.tags.sampled_refs 5681591 # Sample count of references to valid blocks.
1120system.cpu0.icache.tags.avg_refs 35.476286 # Average number of references to valid blocks.
1121system.cpu0.icache.tags.warmup_cycle 18014203000 # Cycle when the warmup percentage was hit.
1122system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.944679 # Average occupied blocks per requestor
1123system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999892 # Average percentage of cache occupancy
1124system.cpu0.icache.tags.occ_percent::total 0.999892 # Average percentage of cache occupancy
1125system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1126system.cpu0.icache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id
1127system.cpu0.icache.tags.age_task_id_blocks_1024::1 483 # Occupied blocks per task id
1128system.cpu0.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id
1129system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1130system.cpu0.icache.tags.tag_accesses 420833426 # Number of tag accesses
1131system.cpu0.icache.tags.data_accesses 420833426 # Number of data accesses
1132system.cpu0.icache.ReadReq_hits::cpu0.inst 201561746 # number of ReadReq hits
1133system.cpu0.icache.ReadReq_hits::total 201561746 # number of ReadReq hits
1134system.cpu0.icache.demand_hits::cpu0.inst 201561746 # number of demand (read+write) hits
1135system.cpu0.icache.demand_hits::total 201561746 # number of demand (read+write) hits
1136system.cpu0.icache.overall_hits::cpu0.inst 201561746 # number of overall hits
1137system.cpu0.icache.overall_hits::total 201561746 # number of overall hits
1138system.cpu0.icache.ReadReq_misses::cpu0.inst 6014149 # number of ReadReq misses
1139system.cpu0.icache.ReadReq_misses::total 6014149 # number of ReadReq misses
1140system.cpu0.icache.demand_misses::cpu0.inst 6014149 # number of demand (read+write) misses
1141system.cpu0.icache.demand_misses::total 6014149 # number of demand (read+write) misses
1142system.cpu0.icache.overall_misses::cpu0.inst 6014149 # number of overall misses
1143system.cpu0.icache.overall_misses::total 6014149 # number of overall misses
1144system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 68585469625 # number of ReadReq miss cycles
1145system.cpu0.icache.ReadReq_miss_latency::total 68585469625 # number of ReadReq miss cycles
1146system.cpu0.icache.demand_miss_latency::cpu0.inst 68585469625 # number of demand (read+write) miss cycles
1147system.cpu0.icache.demand_miss_latency::total 68585469625 # number of demand (read+write) miss cycles
1148system.cpu0.icache.overall_miss_latency::cpu0.inst 68585469625 # number of overall miss cycles
1149system.cpu0.icache.overall_miss_latency::total 68585469625 # number of overall miss cycles
1150system.cpu0.icache.ReadReq_accesses::cpu0.inst 207575895 # number of ReadReq accesses(hits+misses)
1151system.cpu0.icache.ReadReq_accesses::total 207575895 # number of ReadReq accesses(hits+misses)
1152system.cpu0.icache.demand_accesses::cpu0.inst 207575895 # number of demand (read+write) accesses
1153system.cpu0.icache.demand_accesses::total 207575895 # number of demand (read+write) accesses
1154system.cpu0.icache.overall_accesses::cpu0.inst 207575895 # number of overall (read+write) accesses
1155system.cpu0.icache.overall_accesses::total 207575895 # number of overall (read+write) accesses
1156system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028973 # miss rate for ReadReq accesses
1157system.cpu0.icache.ReadReq_miss_rate::total 0.028973 # miss rate for ReadReq accesses
1158system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028973 # miss rate for demand accesses
1159system.cpu0.icache.demand_miss_rate::total 0.028973 # miss rate for demand accesses
1160system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028973 # miss rate for overall accesses
1161system.cpu0.icache.overall_miss_rate::total 0.028973 # miss rate for overall accesses
1162system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11404.019027 # average ReadReq miss latency
1163system.cpu0.icache.ReadReq_avg_miss_latency::total 11404.019027 # average ReadReq miss latency
1164system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11404.019027 # average overall miss latency
1165system.cpu0.icache.demand_avg_miss_latency::total 11404.019027 # average overall miss latency
1166system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11404.019027 # average overall miss latency
1167system.cpu0.icache.overall_avg_miss_latency::total 11404.019027 # average overall miss latency
1168system.cpu0.icache.blocked_cycles::no_mshrs 10444384 # number of cycles access was blocked
1169system.cpu0.icache.blocked_cycles::no_targets 1542 # number of cycles access was blocked
1170system.cpu0.icache.blocked::no_mshrs 695799 # number of cycles access was blocked
1171system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked
1172system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.010634 # average number of cycles each access was blocked
1173system.cpu0.icache.avg_blocked_cycles::no_targets 118.615385 # average number of cycles each access was blocked
1174system.cpu0.icache.writebacks::writebacks 5681079 # number of writebacks
1175system.cpu0.icache.writebacks::total 5681079 # number of writebacks
1176system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 332513 # number of ReadReq MSHR hits
1177system.cpu0.icache.ReadReq_mshr_hits::total 332513 # number of ReadReq MSHR hits
1178system.cpu0.icache.demand_mshr_hits::cpu0.inst 332513 # number of demand (read+write) MSHR hits
1179system.cpu0.icache.demand_mshr_hits::total 332513 # number of demand (read+write) MSHR hits
1180system.cpu0.icache.overall_mshr_hits::cpu0.inst 332513 # number of overall MSHR hits
1181system.cpu0.icache.overall_mshr_hits::total 332513 # number of overall MSHR hits
1182system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5681636 # number of ReadReq MSHR misses
1183system.cpu0.icache.ReadReq_mshr_misses::total 5681636 # number of ReadReq MSHR misses
1184system.cpu0.icache.demand_mshr_misses::cpu0.inst 5681636 # number of demand (read+write) MSHR misses
1185system.cpu0.icache.demand_mshr_misses::total 5681636 # number of demand (read+write) MSHR misses
1186system.cpu0.icache.overall_mshr_misses::cpu0.inst 5681636 # number of overall MSHR misses
1187system.cpu0.icache.overall_mshr_misses::total 5681636 # number of overall MSHR misses
1188system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
1189system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable
1190system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
1191system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses
1192system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 61685306454 # number of ReadReq MSHR miss cycles
1193system.cpu0.icache.ReadReq_mshr_miss_latency::total 61685306454 # number of ReadReq MSHR miss cycles
1194system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 61685306454 # number of demand (read+write) MSHR miss cycles
1195system.cpu0.icache.demand_mshr_miss_latency::total 61685306454 # number of demand (read+write) MSHR miss cycles
1196system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 61685306454 # number of overall MSHR miss cycles
1197system.cpu0.icache.overall_mshr_miss_latency::total 61685306454 # number of overall MSHR miss cycles
1198system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939780498 # number of ReadReq MSHR uncacheable cycles
1199system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939780498 # number of ReadReq MSHR uncacheable cycles
1200system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939780498 # number of overall MSHR uncacheable cycles
1201system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939780498 # number of overall MSHR uncacheable cycles
1202system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027371 # mshr miss rate for ReadReq accesses
1203system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027371 # mshr miss rate for ReadReq accesses
1204system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027371 # mshr miss rate for demand accesses
1205system.cpu0.icache.demand_mshr_miss_rate::total 0.027371 # mshr miss rate for demand accesses
1206system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027371 # mshr miss rate for overall accesses
1207system.cpu0.icache.overall_mshr_miss_rate::total 0.027371 # mshr miss rate for overall accesses
1208system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10856.962054 # average ReadReq mshr miss latency
1209system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10856.962054 # average ReadReq mshr miss latency
1210system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10856.962054 # average overall mshr miss latency
1211system.cpu0.icache.demand_avg_mshr_miss_latency::total 10856.962054 # average overall mshr miss latency
1212system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10856.962054 # average overall mshr miss latency
1213system.cpu0.icache.overall_avg_mshr_miss_latency::total 10856.962054 # average overall mshr miss latency
1214system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.236651 # average ReadReq mshr uncacheable latency
1215system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.236651 # average ReadReq mshr uncacheable latency
1216system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.236651 # average overall mshr uncacheable latency
1217system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.236651 # average overall mshr uncacheable latency
1218system.cpu0.l2cache.prefetcher.num_hwpf_issued 7915167 # number of hwpf issued
1219system.cpu0.l2cache.prefetcher.pfIdentified 7926437 # number of prefetch candidates identified
1220system.cpu0.l2cache.prefetcher.pfBufferHit 10130 # number of redundant prefetches already in prefetch queue
1221system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1222system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1223system.cpu0.l2cache.prefetcher.pfSpanPage 1009963 # number of prefetches not generated due to page crossing
1224system.cpu0.l2cache.tags.replacements 2664029 # number of replacements
1225system.cpu0.l2cache.tags.tagsinuse 16072.729216 # Cycle average of tags in use
1226system.cpu0.l2cache.tags.total_refs 16415073 # Total number of references to valid blocks.
1227system.cpu0.l2cache.tags.sampled_refs 2680041 # Sample count of references to valid blocks.
1228system.cpu0.l2cache.tags.avg_refs 6.124934 # Average number of references to valid blocks.
1229system.cpu0.l2cache.tags.warmup_cycle 3423391000 # Cycle when the warmup percentage was hit.
1230system.cpu0.l2cache.tags.occ_blocks::writebacks 14987.796585 # Average occupied blocks per requestor
1231system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 47.087094 # Average occupied blocks per requestor
1232system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 49.541309 # Average occupied blocks per requestor
1233system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 988.304228 # Average occupied blocks per requestor
1234system.cpu0.l2cache.tags.occ_percent::writebacks 0.914783 # Average percentage of cache occupancy
1235system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002874 # Average percentage of cache occupancy
1236system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003024 # Average percentage of cache occupancy
1237system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.060321 # Average percentage of cache occupancy
1238system.cpu0.l2cache.tags.occ_percent::total 0.981002 # Average percentage of cache occupancy
1239system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1464 # Occupied blocks per task id
1240system.cpu0.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id
1241system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14480 # Occupied blocks per task id
1242system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 10 # Occupied blocks per task id
1243system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 48 # Occupied blocks per task id
1244system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 590 # Occupied blocks per task id
1245system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 290 # Occupied blocks per task id
1246system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 526 # Occupied blocks per task id
1247system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
1248system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 35 # Occupied blocks per task id
1249system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 10 # Occupied blocks per task id
1250system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 21 # Occupied blocks per task id
1251system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id
1252system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1208 # Occupied blocks per task id
1253system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5747 # Occupied blocks per task id
1254system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2985 # Occupied blocks per task id
1255system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4461 # Occupied blocks per task id
1256system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.089355 # Percentage of cache occupancy per task id
1257system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id
1258system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.883789 # Percentage of cache occupancy per task id
1259system.cpu0.l2cache.tags.tag_accesses 394147733 # Number of tag accesses
1260system.cpu0.l2cache.tags.data_accesses 394147733 # Number of data accesses
1261system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 551770 # number of ReadReq hits
1262system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 179424 # number of ReadReq hits
1263system.cpu0.l2cache.ReadReq_hits::total 731194 # number of ReadReq hits
1264system.cpu0.l2cache.WritebackDirty_hits::writebacks 3854487 # number of WritebackDirty hits
1265system.cpu0.l2cache.WritebackDirty_hits::total 3854487 # number of WritebackDirty hits
1266system.cpu0.l2cache.WritebackClean_hits::writebacks 7627202 # number of WritebackClean hits
1267system.cpu0.l2cache.WritebackClean_hits::total 7627202 # number of WritebackClean hits
1268system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 654 # number of UpgradeReq hits
1269system.cpu0.l2cache.UpgradeReq_hits::total 654 # number of UpgradeReq hits
1270system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits
1271system.cpu0.l2cache.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits
1272system.cpu0.l2cache.ReadExReq_hits::cpu0.data 878534 # number of ReadExReq hits
1273system.cpu0.l2cache.ReadExReq_hits::total 878534 # number of ReadExReq hits
1274system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5121208 # number of ReadCleanReq hits
1275system.cpu0.l2cache.ReadCleanReq_hits::total 5121208 # number of ReadCleanReq hits
1276system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2880934 # number of ReadSharedReq hits
1277system.cpu0.l2cache.ReadSharedReq_hits::total 2880934 # number of ReadSharedReq hits
1278system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 188453 # number of InvalidateReq hits
1279system.cpu0.l2cache.InvalidateReq_hits::total 188453 # number of InvalidateReq hits
1280system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 551770 # number of demand (read+write) hits
1281system.cpu0.l2cache.demand_hits::cpu0.itb.walker 179424 # number of demand (read+write) hits
1282system.cpu0.l2cache.demand_hits::cpu0.inst 5121208 # number of demand (read+write) hits
1283system.cpu0.l2cache.demand_hits::cpu0.data 3759468 # number of demand (read+write) hits
1284system.cpu0.l2cache.demand_hits::total 9611870 # number of demand (read+write) hits
1285system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 551770 # number of overall hits
1286system.cpu0.l2cache.overall_hits::cpu0.itb.walker 179424 # number of overall hits
1287system.cpu0.l2cache.overall_hits::cpu0.inst 5121208 # number of overall hits
1288system.cpu0.l2cache.overall_hits::cpu0.data 3759468 # number of overall hits
1289system.cpu0.l2cache.overall_hits::total 9611870 # number of overall hits
1290system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12055 # number of ReadReq misses
1291system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8680 # number of ReadReq misses
1292system.cpu0.l2cache.ReadReq_misses::total 20735 # number of ReadReq misses
1293system.cpu0.l2cache.WritebackDirty_misses::writebacks 3 # number of WritebackDirty misses
1294system.cpu0.l2cache.WritebackDirty_misses::total 3 # number of WritebackDirty misses
1295system.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses
1296system.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses
1297system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 264383 # number of UpgradeReq misses
1298system.cpu0.l2cache.UpgradeReq_misses::total 264383 # number of UpgradeReq misses
1299system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 190766 # number of SCUpgradeReq misses
1300system.cpu0.l2cache.SCUpgradeReq_misses::total 190766 # number of SCUpgradeReq misses
1301system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses
1302system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
1303system.cpu0.l2cache.ReadExReq_misses::cpu0.data 327479 # number of ReadExReq misses
1304system.cpu0.l2cache.ReadExReq_misses::total 327479 # number of ReadExReq misses
1305system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 560388 # number of ReadCleanReq misses
1306system.cpu0.l2cache.ReadCleanReq_misses::total 560388 # number of ReadCleanReq misses
1307system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1024494 # number of ReadSharedReq misses
1308system.cpu0.l2cache.ReadSharedReq_misses::total 1024494 # number of ReadSharedReq misses
1309system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 598286 # number of InvalidateReq misses
1310system.cpu0.l2cache.InvalidateReq_misses::total 598286 # number of InvalidateReq misses
1311system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12055 # number of demand (read+write) misses
1312system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8680 # number of demand (read+write) misses
1313system.cpu0.l2cache.demand_misses::cpu0.inst 560388 # number of demand (read+write) misses
1314system.cpu0.l2cache.demand_misses::cpu0.data 1351973 # number of demand (read+write) misses
1315system.cpu0.l2cache.demand_misses::total 1933096 # number of demand (read+write) misses
1316system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12055 # number of overall misses
1317system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8680 # number of overall misses
1318system.cpu0.l2cache.overall_misses::cpu0.inst 560388 # number of overall misses
1319system.cpu0.l2cache.overall_misses::cpu0.data 1351973 # number of overall misses
1320system.cpu0.l2cache.overall_misses::total 1933096 # number of overall misses
1321system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 639534000 # number of ReadReq miss cycles
1322system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 449293500 # number of ReadReq miss cycles
1323system.cpu0.l2cache.ReadReq_miss_latency::total 1088827500 # number of ReadReq miss cycles
1324system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3359987500 # number of UpgradeReq miss cycles
1325system.cpu0.l2cache.UpgradeReq_miss_latency::total 3359987500 # number of UpgradeReq miss cycles
1326system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1839849500 # number of SCUpgradeReq miss cycles
1327system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1839849500 # number of SCUpgradeReq miss cycles
1328system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 5649000 # number of SCUpgradeFailReq miss cycles
1329system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 5649000 # number of SCUpgradeFailReq miss cycles
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1331system.cpu0.l2cache.ReadExReq_miss_latency::total 21332705499 # number of ReadExReq miss cycles
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1333system.cpu0.l2cache.ReadCleanReq_miss_latency::total 22152073000 # number of ReadCleanReq miss cycles
1334system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 44214750984 # number of ReadSharedReq miss cycles
1335system.cpu0.l2cache.ReadSharedReq_miss_latency::total 44214750984 # number of ReadSharedReq miss cycles
1336system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 435322500 # number of InvalidateReq miss cycles
1337system.cpu0.l2cache.InvalidateReq_miss_latency::total 435322500 # number of InvalidateReq miss cycles
1338system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 639534000 # number of demand (read+write) miss cycles
1339system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 449293500 # number of demand (read+write) miss cycles
1340system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22152073000 # number of demand (read+write) miss cycles
1341system.cpu0.l2cache.demand_miss_latency::cpu0.data 65547456483 # number of demand (read+write) miss cycles
1342system.cpu0.l2cache.demand_miss_latency::total 88788356983 # number of demand (read+write) miss cycles
1343system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 639534000 # number of overall miss cycles
1344system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 449293500 # number of overall miss cycles
1345system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22152073000 # number of overall miss cycles
1346system.cpu0.l2cache.overall_miss_latency::cpu0.data 65547456483 # number of overall miss cycles
1347system.cpu0.l2cache.overall_miss_latency::total 88788356983 # number of overall miss cycles
1348system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 563825 # number of ReadReq accesses(hits+misses)
1349system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 188104 # number of ReadReq accesses(hits+misses)
1350system.cpu0.l2cache.ReadReq_accesses::total 751929 # number of ReadReq accesses(hits+misses)
1351system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3854490 # number of WritebackDirty accesses(hits+misses)
1352system.cpu0.l2cache.WritebackDirty_accesses::total 3854490 # number of WritebackDirty accesses(hits+misses)
1353system.cpu0.l2cache.WritebackClean_accesses::writebacks 7627203 # number of WritebackClean accesses(hits+misses)
1354system.cpu0.l2cache.WritebackClean_accesses::total 7627203 # number of WritebackClean accesses(hits+misses)
1355system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 265037 # number of UpgradeReq accesses(hits+misses)
1356system.cpu0.l2cache.UpgradeReq_accesses::total 265037 # number of UpgradeReq accesses(hits+misses)
1357system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 190771 # number of SCUpgradeReq accesses(hits+misses)
1358system.cpu0.l2cache.SCUpgradeReq_accesses::total 190771 # number of SCUpgradeReq accesses(hits+misses)
1359system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 6 # number of SCUpgradeFailReq accesses(hits+misses)
1360system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
1361system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1206013 # number of ReadExReq accesses(hits+misses)
1362system.cpu0.l2cache.ReadExReq_accesses::total 1206013 # number of ReadExReq accesses(hits+misses)
1363system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5681596 # number of ReadCleanReq accesses(hits+misses)
1364system.cpu0.l2cache.ReadCleanReq_accesses::total 5681596 # number of ReadCleanReq accesses(hits+misses)
1365system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3905428 # number of ReadSharedReq accesses(hits+misses)
1366system.cpu0.l2cache.ReadSharedReq_accesses::total 3905428 # number of ReadSharedReq accesses(hits+misses)
1367system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 786739 # number of InvalidateReq accesses(hits+misses)
1368system.cpu0.l2cache.InvalidateReq_accesses::total 786739 # number of InvalidateReq accesses(hits+misses)
1369system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 563825 # number of demand (read+write) accesses
1370system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 188104 # number of demand (read+write) accesses
1371system.cpu0.l2cache.demand_accesses::cpu0.inst 5681596 # number of demand (read+write) accesses
1372system.cpu0.l2cache.demand_accesses::cpu0.data 5111441 # number of demand (read+write) accesses
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1374system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 563825 # number of overall (read+write) accesses
1375system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 188104 # number of overall (read+write) accesses
1376system.cpu0.l2cache.overall_accesses::cpu0.inst 5681596 # number of overall (read+write) accesses
1377system.cpu0.l2cache.overall_accesses::cpu0.data 5111441 # number of overall (read+write) accesses
1378system.cpu0.l2cache.overall_accesses::total 11544966 # number of overall (read+write) accesses
1379system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021381 # miss rate for ReadReq accesses
1380system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.046145 # miss rate for ReadReq accesses
1381system.cpu0.l2cache.ReadReq_miss_rate::total 0.027576 # miss rate for ReadReq accesses
1382system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses
1383system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses
1384system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses
1385system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses
1386system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.997532 # miss rate for UpgradeReq accesses
1387system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.997532 # miss rate for UpgradeReq accesses
1388system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999974 # miss rate for SCUpgradeReq accesses
1389system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999974 # miss rate for SCUpgradeReq accesses
1390system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1391system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1392system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.271539 # miss rate for ReadExReq accesses
1393system.cpu0.l2cache.ReadExReq_miss_rate::total 0.271539 # miss rate for ReadExReq accesses
1394system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.098632 # miss rate for ReadCleanReq accesses
1395system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.098632 # miss rate for ReadCleanReq accesses
1396system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.262326 # miss rate for ReadSharedReq accesses
1397system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.262326 # miss rate for ReadSharedReq accesses
1398system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.760463 # miss rate for InvalidateReq accesses
1399system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.760463 # miss rate for InvalidateReq accesses
1400system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021381 # miss rate for demand accesses
1401system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.046145 # miss rate for demand accesses
1402system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.098632 # miss rate for demand accesses
1403system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.264499 # miss rate for demand accesses
1404system.cpu0.l2cache.demand_miss_rate::total 0.167441 # miss rate for demand accesses
1405system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021381 # miss rate for overall accesses
1406system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.046145 # miss rate for overall accesses
1407system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.098632 # miss rate for overall accesses
1408system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.264499 # miss rate for overall accesses
1409system.cpu0.l2cache.overall_miss_rate::total 0.167441 # miss rate for overall accesses
1410system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 53051.347988 # average ReadReq miss latency
1411system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 51761.923963 # average ReadReq miss latency
1412system.cpu0.l2cache.ReadReq_avg_miss_latency::total 52511.574632 # average ReadReq miss latency
1413system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 12708.788008 # average UpgradeReq miss latency
1414system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 12708.788008 # average UpgradeReq miss latency
1415system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 9644.535714 # average SCUpgradeReq miss latency
1416system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 9644.535714 # average SCUpgradeReq miss latency
1417system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 941500 # average SCUpgradeFailReq miss latency
1418system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 941500 # average SCUpgradeFailReq miss latency
1419system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 65142.209116 # average ReadExReq miss latency
1420system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 65142.209116 # average ReadExReq miss latency
1421system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39529.884651 # average ReadCleanReq miss latency
1422system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39529.884651 # average ReadCleanReq miss latency
1423system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 43157.647565 # average ReadSharedReq miss latency
1424system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 43157.647565 # average ReadSharedReq miss latency
1425system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 727.616057 # average InvalidateReq miss latency
1426system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 727.616057 # average InvalidateReq miss latency
1427system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 53051.347988 # average overall miss latency
1428system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 51761.923963 # average overall miss latency
1429system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39529.884651 # average overall miss latency
1430system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 48482.814733 # average overall miss latency
1431system.cpu0.l2cache.demand_avg_miss_latency::total 45930.650616 # average overall miss latency
1432system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 53051.347988 # average overall miss latency
1433system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 51761.923963 # average overall miss latency
1434system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39529.884651 # average overall miss latency
1435system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 48482.814733 # average overall miss latency
1436system.cpu0.l2cache.overall_avg_miss_latency::total 45930.650616 # average overall miss latency
1437system.cpu0.l2cache.blocked_cycles::no_mshrs 710 # number of cycles access was blocked
1438system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1439system.cpu0.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked
1440system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1441system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 118.333333 # average number of cycles each access was blocked
1442system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1443system.cpu0.l2cache.unused_prefetches 45316 # number of HardPF blocks evicted w/o reference
1444system.cpu0.l2cache.writebacks::writebacks 1671374 # number of writebacks
1445system.cpu0.l2cache.writebacks::total 1671374 # number of writebacks
1446system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 3 # number of ReadReq MSHR hits
1447system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 14 # number of ReadReq MSHR hits
1448system.cpu0.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits
1449system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 47908 # number of ReadExReq MSHR hits
1450system.cpu0.l2cache.ReadExReq_mshr_hits::total 47908 # number of ReadExReq MSHR hits
1451system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 7 # number of ReadCleanReq MSHR hits
1452system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits
1453system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 5947 # number of ReadSharedReq MSHR hits
1454system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 5947 # number of ReadSharedReq MSHR hits
1455system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 12 # number of InvalidateReq MSHR hits
1456system.cpu0.l2cache.InvalidateReq_mshr_hits::total 12 # number of InvalidateReq MSHR hits
1457system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 3 # number of demand (read+write) MSHR hits
1458system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 14 # number of demand (read+write) MSHR hits
1459system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits
1460system.cpu0.l2cache.demand_mshr_hits::cpu0.data 53855 # number of demand (read+write) MSHR hits
1461system.cpu0.l2cache.demand_mshr_hits::total 53879 # number of demand (read+write) MSHR hits
1462system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 3 # number of overall MSHR hits
1463system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 14 # number of overall MSHR hits
1464system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits
1465system.cpu0.l2cache.overall_mshr_hits::cpu0.data 53855 # number of overall MSHR hits
1466system.cpu0.l2cache.overall_mshr_hits::total 53879 # number of overall MSHR hits
1467system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12052 # number of ReadReq MSHR misses
1468system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8666 # number of ReadReq MSHR misses
1469system.cpu0.l2cache.ReadReq_mshr_misses::total 20718 # number of ReadReq MSHR misses
1470system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 3 # number of WritebackDirty MSHR misses
1471system.cpu0.l2cache.WritebackDirty_mshr_misses::total 3 # number of WritebackDirty MSHR misses
1472system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses
1473system.cpu0.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses
1474system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 803197 # number of HardPFReq MSHR misses
1475system.cpu0.l2cache.HardPFReq_mshr_misses::total 803197 # number of HardPFReq MSHR misses
1476system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 264383 # number of UpgradeReq MSHR misses
1477system.cpu0.l2cache.UpgradeReq_mshr_misses::total 264383 # number of UpgradeReq MSHR misses
1478system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 190766 # number of SCUpgradeReq MSHR misses
1479system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 190766 # number of SCUpgradeReq MSHR misses
1480system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses
1481system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses
1482system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 279571 # number of ReadExReq MSHR misses
1483system.cpu0.l2cache.ReadExReq_mshr_misses::total 279571 # number of ReadExReq MSHR misses
1484system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 560381 # number of ReadCleanReq MSHR misses
1485system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 560381 # number of ReadCleanReq MSHR misses
1486system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1018547 # number of ReadSharedReq MSHR misses
1487system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1018547 # number of ReadSharedReq MSHR misses
1488system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 598274 # number of InvalidateReq MSHR misses
1489system.cpu0.l2cache.InvalidateReq_mshr_misses::total 598274 # number of InvalidateReq MSHR misses
1490system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12052 # number of demand (read+write) MSHR misses
1491system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8666 # number of demand (read+write) MSHR misses
1492system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 560381 # number of demand (read+write) MSHR misses
1493system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1298118 # number of demand (read+write) MSHR misses
1494system.cpu0.l2cache.demand_mshr_misses::total 1879217 # number of demand (read+write) MSHR misses
1495system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12052 # number of overall MSHR misses
1496system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8666 # number of overall MSHR misses
1497system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 560381 # number of overall MSHR misses
1498system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1298118 # number of overall MSHR misses
1499system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 803197 # number of overall MSHR misses
1500system.cpu0.l2cache.overall_mshr_misses::total 2682414 # number of overall MSHR misses
1501system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
1502system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 19706 # number of ReadReq MSHR uncacheable
1503system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40999 # number of ReadReq MSHR uncacheable
1504system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 21266 # number of WriteReq MSHR uncacheable
1505system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 21266 # number of WriteReq MSHR uncacheable
1506system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
1507system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 40972 # number of overall MSHR uncacheable misses
1508system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 62265 # number of overall MSHR uncacheable misses
1509system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 567159000 # number of ReadReq MSHR miss cycles
1510system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 396729500 # number of ReadReq MSHR miss cycles
1511system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 963888500 # number of ReadReq MSHR miss cycles
1512system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 57196003159 # number of HardPFReq MSHR miss cycles
1513system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 57196003159 # number of HardPFReq MSHR miss cycles
1514system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7687713495 # number of UpgradeReq MSHR miss cycles
1515system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7687713495 # number of UpgradeReq MSHR miss cycles
1516system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3687086997 # number of SCUpgradeReq MSHR miss cycles
1517system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3687086997 # number of SCUpgradeReq MSHR miss cycles
1518system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 5229000 # number of SCUpgradeFailReq MSHR miss cycles
1519system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 5229000 # number of SCUpgradeFailReq MSHR miss cycles
1520system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 16511973000 # number of ReadExReq MSHR miss cycles
1521system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 16511973000 # number of ReadExReq MSHR miss cycles
1522system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 18789663000 # number of ReadCleanReq MSHR miss cycles
1523system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 18789663000 # number of ReadCleanReq MSHR miss cycles
1524system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 37621826984 # number of ReadSharedReq MSHR miss cycles
1525system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 37621826984 # number of ReadSharedReq MSHR miss cycles
1526system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 42300516999 # number of InvalidateReq MSHR miss cycles
1527system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 42300516999 # number of InvalidateReq MSHR miss cycles
1528system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 567159000 # number of demand (read+write) MSHR miss cycles
1529system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 396729500 # number of demand (read+write) MSHR miss cycles
1530system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 18789663000 # number of demand (read+write) MSHR miss cycles
1531system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 54133799984 # number of demand (read+write) MSHR miss cycles
1532system.cpu0.l2cache.demand_mshr_miss_latency::total 73887351484 # number of demand (read+write) MSHR miss cycles
1533system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 567159000 # number of overall MSHR miss cycles
1534system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 396729500 # number of overall MSHR miss cycles
1535system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 18789663000 # number of overall MSHR miss cycles
1536system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 54133799984 # number of overall MSHR miss cycles
1537system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 57196003159 # number of overall MSHR miss cycles
1538system.cpu0.l2cache.overall_mshr_miss_latency::total 131083354643 # number of overall MSHR miss cycles
1539system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780082000 # number of ReadReq MSHR uncacheable cycles
1540system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3705524000 # number of ReadReq MSHR uncacheable cycles
1541system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6485606000 # number of ReadReq MSHR uncacheable cycles
1542system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 2780082000 # number of overall MSHR uncacheable cycles
1543system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 3705524000 # number of overall MSHR uncacheable cycles
1544system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6485606000 # number of overall MSHR uncacheable cycles
1545system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021375 # mshr miss rate for ReadReq accesses
1546system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.046070 # mshr miss rate for ReadReq accesses
1547system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027553 # mshr miss rate for ReadReq accesses
1548system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses
1549system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses
1550system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
1551system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
1552system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1553system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1554system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997532 # mshr miss rate for UpgradeReq accesses
1555system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997532 # mshr miss rate for UpgradeReq accesses
1556system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999974 # mshr miss rate for SCUpgradeReq accesses
1557system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999974 # mshr miss rate for SCUpgradeReq accesses
1558system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1559system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1560system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.231814 # mshr miss rate for ReadExReq accesses
1561system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231814 # mshr miss rate for ReadExReq accesses
1562system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.098631 # mshr miss rate for ReadCleanReq accesses
1563system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098631 # mshr miss rate for ReadCleanReq accesses
1564system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.260803 # mshr miss rate for ReadSharedReq accesses
1565system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.260803 # mshr miss rate for ReadSharedReq accesses
1566system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.760448 # mshr miss rate for InvalidateReq accesses
1567system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.760448 # mshr miss rate for InvalidateReq accesses
1568system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021375 # mshr miss rate for demand accesses
1569system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046070 # mshr miss rate for demand accesses
1570system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.098631 # mshr miss rate for demand accesses
1571system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.253963 # mshr miss rate for demand accesses
1572system.cpu0.l2cache.demand_mshr_miss_rate::total 0.162774 # mshr miss rate for demand accesses
1573system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021375 # mshr miss rate for overall accesses
1574system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046070 # mshr miss rate for overall accesses
1575system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.098631 # mshr miss rate for overall accesses
1576system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.253963 # mshr miss rate for overall accesses
1577system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1578system.cpu0.l2cache.overall_mshr_miss_rate::total 0.232345 # mshr miss rate for overall accesses
1579system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 47059.326253 # average ReadReq mshr miss latency
1580system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 45780.002308 # average ReadReq mshr miss latency
1581system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 46524.206004 # average ReadReq mshr miss latency
1582system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 71210.429271 # average HardPFReq mshr miss latency
1583system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 71210.429271 # average HardPFReq mshr miss latency
1584system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29077.941831 # average UpgradeReq mshr miss latency
1585system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29077.941831 # average UpgradeReq mshr miss latency
1586system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19327.799487 # average SCUpgradeReq mshr miss latency
1587system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19327.799487 # average SCUpgradeReq mshr miss latency
1588system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 871500 # average SCUpgradeFailReq mshr miss latency
1589system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 871500 # average SCUpgradeFailReq mshr miss latency
1590system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 59061.823294 # average ReadExReq mshr miss latency
1591system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 59061.823294 # average ReadExReq mshr miss latency
1592system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33530.157161 # average ReadCleanReq mshr miss latency
1593system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33530.157161 # average ReadCleanReq mshr miss latency
1594system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 36936.760880 # average ReadSharedReq mshr miss latency
1595system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 36936.760880 # average ReadSharedReq mshr miss latency
1596system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70704.254236 # average InvalidateReq mshr miss latency
1597system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70704.254236 # average InvalidateReq mshr miss latency
1598system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 47059.326253 # average overall mshr miss latency
1599system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 45780.002308 # average overall mshr miss latency
1600system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33530.157161 # average overall mshr miss latency
1601system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 41701.755914 # average overall mshr miss latency
1602system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 39318.158299 # average overall mshr miss latency
1603system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 47059.326253 # average overall mshr miss latency
1604system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 45780.002308 # average overall mshr miss latency
1605system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33530.157161 # average overall mshr miss latency
1606system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 41701.755914 # average overall mshr miss latency
1607system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 71210.429271 # average overall mshr miss latency
1608system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48867.682111 # average overall mshr miss latency
1609system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.189781 # average ReadReq mshr uncacheable latency
1610system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188040.393789 # average ReadReq mshr uncacheable latency
1611system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 158189.370472 # average ReadReq mshr uncacheable latency
1612system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.189781 # average overall mshr uncacheable latency
1613system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 90440.398321 # average overall mshr uncacheable latency
1614system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104161.342648 # average overall mshr uncacheable latency
1615system.cpu0.toL2Bus.snoop_filter.tot_requests 23859843 # Total number of requests made to the snoop filter.
1616system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12280153 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1617system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1945 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1618system.cpu0.toL2Bus.snoop_filter.tot_snoops 2008292 # Total number of snoops made to the snoop filter.
1619system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2007802 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1620system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 490 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1621system.cpu0.toL2Bus.trans_dist::ReadReq 875651 # Transaction distribution
1622system.cpu0.toL2Bus.trans_dist::ReadResp 10557046 # Transaction distribution
1623system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
1624system.cpu0.toL2Bus.trans_dist::WriteReq 21267 # Transaction distribution
1625system.cpu0.toL2Bus.trans_dist::WriteResp 21266 # Transaction distribution
1626system.cpu0.toL2Bus.trans_dist::WritebackDirty 5532941 # Transaction distribution
1627system.cpu0.toL2Bus.trans_dist::WritebackClean 7629125 # Transaction distribution
1628system.cpu0.toL2Bus.trans_dist::CleanEvict 2654810 # Transaction distribution
1629system.cpu0.toL2Bus.trans_dist::HardPFReq 1033772 # Transaction distribution
1630system.cpu0.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution
1631system.cpu0.toL2Bus.trans_dist::UpgradeReq 476440 # Transaction distribution
1632system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 348822 # Transaction distribution
1633system.cpu0.toL2Bus.trans_dist::UpgradeResp 520615 # Transaction distribution
1634system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution
1635system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution
1636system.cpu0.toL2Bus.trans_dist::ReadExReq 1237465 # Transaction distribution
1637system.cpu0.toL2Bus.trans_dist::ReadExResp 1213308 # Transaction distribution
1638system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5681636 # Transaction distribution
1639system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4942147 # Transaction distribution
1640system.cpu0.toL2Bus.trans_dist::InvalidateReq 844889 # Transaction distribution
1641system.cpu0.toL2Bus.trans_dist::InvalidateResp 786739 # Transaction distribution
1642system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17086897 # Packet count per connected master and slave (bytes)
1643system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18759020 # Packet count per connected master and slave (bytes)
1644system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 394013 # Packet count per connected master and slave (bytes)
1645system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1192566 # Packet count per connected master and slave (bytes)
1646system.cpu0.toL2Bus.pkt_count::total 37432496 # Packet count per connected master and slave (bytes)
1647system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 727551888 # Cumulative packet size per connected master and slave (bytes)
1648system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 705113777 # Cumulative packet size per connected master and slave (bytes)
1649system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1504832 # Cumulative packet size per connected master and slave (bytes)
1650system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4510600 # Cumulative packet size per connected master and slave (bytes)
1651system.cpu0.toL2Bus.pkt_size::total 1438681097 # Cumulative packet size per connected master and slave (bytes)
1652system.cpu0.toL2Bus.snoops 7112172 # Total snoops (count)
1653system.cpu0.toL2Bus.snoop_fanout::samples 19795414 # Request fanout histogram
1654system.cpu0.toL2Bus.snoop_fanout::mean 0.118782 # Request fanout histogram
1655system.cpu0.toL2Bus.snoop_fanout::stdev 0.323609 # Request fanout histogram
1656system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1657system.cpu0.toL2Bus.snoop_fanout::0 17444556 88.12% 88.12% # Request fanout histogram
1658system.cpu0.toL2Bus.snoop_fanout::1 2350368 11.87% 100.00% # Request fanout histogram
1659system.cpu0.toL2Bus.snoop_fanout::2 490 0.00% 100.00% # Request fanout histogram
1660system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1661system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1662system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1663system.cpu0.toL2Bus.snoop_fanout::total 19795414 # Request fanout histogram
1664system.cpu0.toL2Bus.reqLayer0.occupancy 23702360441 # Layer occupancy (ticks)
1665system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1666system.cpu0.toL2Bus.snoopLayer0.occupancy 185100538 # Layer occupancy (ticks)
1667system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1668system.cpu0.toL2Bus.respLayer0.occupancy 8549815301 # Layer occupancy (ticks)
1669system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1670system.cpu0.toL2Bus.respLayer1.occupancy 8326796053 # Layer occupancy (ticks)
1671system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1672system.cpu0.toL2Bus.respLayer2.occupancy 206206896 # Layer occupancy (ticks)
1673system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1674system.cpu0.toL2Bus.respLayer3.occupancy 629446573 # Layer occupancy (ticks)
1675system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1676system.cpu1.branchPred.lookups 144214101 # Number of BP lookups
1677system.cpu1.branchPred.condPredicted 95658264 # Number of conditional branches predicted
1678system.cpu1.branchPred.condIncorrect 7037471 # Number of conditional branches incorrect
1679system.cpu1.branchPred.BTBLookups 101536339 # Number of BTB lookups
1680system.cpu1.branchPred.BTBHits 63283833 # Number of BTB hits
1681system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1682system.cpu1.branchPred.BTBHitPct 62.326290 # BTB Hit Percentage
1683system.cpu1.branchPred.usedRAS 19487906 # Number of times the RAS was used to get a target.
1684system.cpu1.branchPred.RASInCorrect 205159 # Number of incorrect RAS predictions.
1685system.cpu1.branchPred.indirectLookups 4571638 # Number of indirect predictor lookups.
1686system.cpu1.branchPred.indirectHits 2870819 # Number of indirect target hits.
1687system.cpu1.branchPred.indirectMisses 1700819 # Number of indirect misses.
1688system.cpu1.branchPredindirectMispredicted 415354 # Number of mispredicted indirect branches.
1689system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1690system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1691system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1692system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1693system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1694system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1695system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1696system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

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1710system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1711system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1712system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1713system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1714system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1715system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1716system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1717system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1718system.cpu1.dtb.walker.walks 655828 # Table walker walks requested
1719system.cpu1.dtb.walker.walksLong 655828 # Table walker walks initiated with long descriptors
1720system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 14723 # Level at which table walker walks with long descriptors terminate
1721system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 107099 # Level at which table walker walks with long descriptors terminate
1722system.cpu1.dtb.walker.walksSquashedBefore 315531 # Table walks squashed before starting
1723system.cpu1.dtb.walker.walkWaitTime::samples 340297 # Table walker wait (enqueue to first request) latency
1724system.cpu1.dtb.walker.walkWaitTime::mean 2456.990511 # Table walker wait (enqueue to first request) latency
1725system.cpu1.dtb.walker.walkWaitTime::stdev 14831.918999 # Table walker wait (enqueue to first request) latency
1726system.cpu1.dtb.walker.walkWaitTime::0-65535 337419 99.15% 99.15% # Table walker wait (enqueue to first request) latency
1727system.cpu1.dtb.walker.walkWaitTime::65536-131071 1530 0.45% 99.60% # Table walker wait (enqueue to first request) latency
1728system.cpu1.dtb.walker.walkWaitTime::131072-196607 1096 0.32% 99.93% # Table walker wait (enqueue to first request) latency
1729system.cpu1.dtb.walker.walkWaitTime::196608-262143 124 0.04% 99.96% # Table walker wait (enqueue to first request) latency
1730system.cpu1.dtb.walker.walkWaitTime::262144-327679 45 0.01% 99.98% # Table walker wait (enqueue to first request) latency
1731system.cpu1.dtb.walker.walkWaitTime::327680-393215 65 0.02% 99.99% # Table walker wait (enqueue to first request) latency
1732system.cpu1.dtb.walker.walkWaitTime::393216-458751 10 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1733system.cpu1.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1734system.cpu1.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1735system.cpu1.dtb.walker.walkWaitTime::786432-851967 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1736system.cpu1.dtb.walker.walkWaitTime::total 340297 # Table walker wait (enqueue to first request) latency
1737system.cpu1.dtb.walker.walkCompletionTime::samples 353965 # Table walker service (enqueue to completion) latency
1738system.cpu1.dtb.walker.walkCompletionTime::mean 21023.430283 # Table walker service (enqueue to completion) latency
1739system.cpu1.dtb.walker.walkCompletionTime::gmean 17819.927272 # Table walker service (enqueue to completion) latency
1740system.cpu1.dtb.walker.walkCompletionTime::stdev 22140.509228 # Table walker service (enqueue to completion) latency
1741system.cpu1.dtb.walker.walkCompletionTime::0-65535 349562 98.76% 98.76% # Table walker service (enqueue to completion) latency
1742system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1039 0.29% 99.05% # Table walker service (enqueue to completion) latency
1743system.cpu1.dtb.walker.walkCompletionTime::131072-196607 2363 0.67% 99.72% # Table walker service (enqueue to completion) latency
1744system.cpu1.dtb.walker.walkCompletionTime::196608-262143 142 0.04% 99.76% # Table walker service (enqueue to completion) latency
1745system.cpu1.dtb.walker.walkCompletionTime::262144-327679 520 0.15% 99.90% # Table walker service (enqueue to completion) latency
1746system.cpu1.dtb.walker.walkCompletionTime::327680-393215 154 0.04% 99.95% # Table walker service (enqueue to completion) latency
1747system.cpu1.dtb.walker.walkCompletionTime::393216-458751 109 0.03% 99.98% # Table walker service (enqueue to completion) latency
1748system.cpu1.dtb.walker.walkCompletionTime::458752-524287 57 0.02% 99.99% # Table walker service (enqueue to completion) latency
1749system.cpu1.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
1750system.cpu1.dtb.walker.walkCompletionTime::589824-655359 8 0.00% 100.00% # Table walker service (enqueue to completion) latency
1751system.cpu1.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
1752system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1753system.cpu1.dtb.walker.walkCompletionTime::total 353965 # Table walker service (enqueue to completion) latency
1754system.cpu1.dtb.walker.walksPending::samples 524755655220 # Table walker pending requests distribution
1755system.cpu1.dtb.walker.walksPending::mean 0.627277 # Table walker pending requests distribution
1756system.cpu1.dtb.walker.walksPending::stdev 0.547876 # Table walker pending requests distribution
1757system.cpu1.dtb.walker.walksPending::0-1 523184603720 99.70% 99.70% # Table walker pending requests distribution
1758system.cpu1.dtb.walker.walksPending::2-3 876126000 0.17% 99.87% # Table walker pending requests distribution
1759system.cpu1.dtb.walker.walksPending::4-5 338256000 0.06% 99.93% # Table walker pending requests distribution
1760system.cpu1.dtb.walker.walksPending::6-7 142712500 0.03% 99.96% # Table walker pending requests distribution
1761system.cpu1.dtb.walker.walksPending::8-9 110713000 0.02% 99.98% # Table walker pending requests distribution
1762system.cpu1.dtb.walker.walksPending::10-11 57399000 0.01% 99.99% # Table walker pending requests distribution
1763system.cpu1.dtb.walker.walksPending::12-13 19068500 0.00% 99.99% # Table walker pending requests distribution
1764system.cpu1.dtb.walker.walksPending::14-15 26227000 0.00% 100.00% # Table walker pending requests distribution
1765system.cpu1.dtb.walker.walksPending::16-17 540000 0.00% 100.00% # Table walker pending requests distribution
1766system.cpu1.dtb.walker.walksPending::18-19 6500 0.00% 100.00% # Table walker pending requests distribution
1767system.cpu1.dtb.walker.walksPending::20-21 1500 0.00% 100.00% # Table walker pending requests distribution
1768system.cpu1.dtb.walker.walksPending::22-23 1500 0.00% 100.00% # Table walker pending requests distribution
1769system.cpu1.dtb.walker.walksPending::total 524755655220 # Table walker pending requests distribution
1770system.cpu1.dtb.walker.walkPageSizes::4K 107100 87.91% 87.91% # Table walker page sizes translated
1771system.cpu1.dtb.walker.walkPageSizes::2M 14723 12.09% 100.00% # Table walker page sizes translated
1772system.cpu1.dtb.walker.walkPageSizes::total 121823 # Table walker page sizes translated
1773system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 655828 # Table walker requests started/completed, data/inst
1774system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1775system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 655828 # Table walker requests started/completed, data/inst
1776system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 121823 # Table walker requests started/completed, data/inst
1777system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1778system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 121823 # Table walker requests started/completed, data/inst
1779system.cpu1.dtb.walker.walkRequestOrigin::total 777651 # Table walker requests started/completed, data/inst
1780system.cpu1.dtb.inst_hits 0 # ITB inst hits
1781system.cpu1.dtb.inst_misses 0 # ITB inst misses
1782system.cpu1.dtb.read_hits 106468062 # DTB read hits
1783system.cpu1.dtb.read_misses 473211 # DTB read misses
1784system.cpu1.dtb.write_hits 85858726 # DTB write hits
1785system.cpu1.dtb.write_misses 182617 # DTB write misses
1786system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
1787system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1788system.cpu1.dtb.flush_tlb_mva_asid 46091 # Number of times TLB was flushed by MVA & ASID
1789system.cpu1.dtb.flush_tlb_asid 1084 # Number of times TLB was flushed by ASID
1790system.cpu1.dtb.flush_entries 44338 # Number of entries that have been flushed from TLB
1791system.cpu1.dtb.align_faults 492 # Number of TLB faults due to alignment restrictions
1792system.cpu1.dtb.prefetch_faults 7273 # Number of TLB faults due to prefetch
1793system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1794system.cpu1.dtb.perms_faults 40937 # Number of TLB faults due to permissions restrictions
1795system.cpu1.dtb.read_accesses 106941273 # DTB read accesses
1796system.cpu1.dtb.write_accesses 86041343 # DTB write accesses
1797system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1798system.cpu1.dtb.hits 192326788 # DTB hits
1799system.cpu1.dtb.misses 655828 # DTB misses
1800system.cpu1.dtb.accesses 192982616 # DTB accesses
1801system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1802system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1803system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1804system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1805system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1806system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1807system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1808system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1822system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1823system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1824system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1825system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1826system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1827system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1828system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1829system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1830system.cpu1.itb.walker.walks 90500 # Table walker walks requested
1831system.cpu1.itb.walker.walksLong 90500 # Table walker walks initiated with long descriptors
1832system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1174 # Level at which table walker walks with long descriptors terminate
1833system.cpu1.itb.walker.walksLongTerminationLevel::Level3 63013 # Level at which table walker walks with long descriptors terminate
1834system.cpu1.itb.walker.walksSquashedBefore 10919 # Table walks squashed before starting
1835system.cpu1.itb.walker.walkWaitTime::samples 79581 # Table walker wait (enqueue to first request) latency
1836system.cpu1.itb.walker.walkWaitTime::mean 1858.653447 # Table walker wait (enqueue to first request) latency
1837system.cpu1.itb.walker.walkWaitTime::stdev 14270.720139 # Table walker wait (enqueue to first request) latency
1838system.cpu1.itb.walker.walkWaitTime::0-65535 78947 99.20% 99.20% # Table walker wait (enqueue to first request) latency
1839system.cpu1.itb.walker.walkWaitTime::65536-131071 217 0.27% 99.48% # Table walker wait (enqueue to first request) latency
1840system.cpu1.itb.walker.walkWaitTime::131072-196607 367 0.46% 99.94% # Table walker wait (enqueue to first request) latency
1841system.cpu1.itb.walker.walkWaitTime::196608-262143 26 0.03% 99.97% # Table walker wait (enqueue to first request) latency
1842system.cpu1.itb.walker.walkWaitTime::262144-327679 15 0.02% 99.99% # Table walker wait (enqueue to first request) latency
1843system.cpu1.itb.walker.walkWaitTime::327680-393215 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
1844system.cpu1.itb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1845system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1846system.cpu1.itb.walker.walkWaitTime::total 79581 # Table walker wait (enqueue to first request) latency
1847system.cpu1.itb.walker.walkCompletionTime::samples 75106 # Table walker service (enqueue to completion) latency
1848system.cpu1.itb.walker.walkCompletionTime::mean 27703.186164 # Table walker service (enqueue to completion) latency
1849system.cpu1.itb.walker.walkCompletionTime::gmean 23129.879308 # Table walker service (enqueue to completion) latency
1850system.cpu1.itb.walker.walkCompletionTime::stdev 30256.665627 # Table walker service (enqueue to completion) latency
1851system.cpu1.itb.walker.walkCompletionTime::0-65535 72610 96.68% 96.68% # Table walker service (enqueue to completion) latency
1852system.cpu1.itb.walker.walkCompletionTime::65536-131071 191 0.25% 96.93% # Table walker service (enqueue to completion) latency
1853system.cpu1.itb.walker.walkCompletionTime::131072-196607 1968 2.62% 99.55% # Table walker service (enqueue to completion) latency
1854system.cpu1.itb.walker.walkCompletionTime::196608-262143 115 0.15% 99.70% # Table walker service (enqueue to completion) latency
1855system.cpu1.itb.walker.walkCompletionTime::262144-327679 133 0.18% 99.88% # Table walker service (enqueue to completion) latency
1856system.cpu1.itb.walker.walkCompletionTime::327680-393215 46 0.06% 99.94% # Table walker service (enqueue to completion) latency
1857system.cpu1.itb.walker.walkCompletionTime::393216-458751 21 0.03% 99.97% # Table walker service (enqueue to completion) latency
1858system.cpu1.itb.walker.walkCompletionTime::458752-524287 16 0.02% 99.99% # Table walker service (enqueue to completion) latency
1859system.cpu1.itb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
1860system.cpu1.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1861system.cpu1.itb.walker.walkCompletionTime::total 75106 # Table walker service (enqueue to completion) latency
1862system.cpu1.itb.walker.walksPending::samples 438856254800 # Table walker pending requests distribution
1863system.cpu1.itb.walker.walksPending::mean 0.887236 # Table walker pending requests distribution
1864system.cpu1.itb.walker.walksPending::stdev 0.316700 # Table walker pending requests distribution
1865system.cpu1.itb.walker.walksPending::0 49536953716 11.29% 11.29% # Table walker pending requests distribution
1866system.cpu1.itb.walker.walksPending::1 389273644084 88.70% 99.99% # Table walker pending requests distribution
1867system.cpu1.itb.walker.walksPending::2 42101500 0.01% 100.00% # Table walker pending requests distribution
1868system.cpu1.itb.walker.walksPending::3 2811500 0.00% 100.00% # Table walker pending requests distribution
1869system.cpu1.itb.walker.walksPending::4 744000 0.00% 100.00% # Table walker pending requests distribution
1870system.cpu1.itb.walker.walksPending::total 438856254800 # Table walker pending requests distribution
1871system.cpu1.itb.walker.walkPageSizes::4K 63013 98.17% 98.17% # Table walker page sizes translated
1872system.cpu1.itb.walker.walkPageSizes::2M 1174 1.83% 100.00% # Table walker page sizes translated
1873system.cpu1.itb.walker.walkPageSizes::total 64187 # Table walker page sizes translated
1874system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1875system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 90500 # Table walker requests started/completed, data/inst
1876system.cpu1.itb.walker.walkRequestOrigin_Requested::total 90500 # Table walker requests started/completed, data/inst
1877system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1878system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 64187 # Table walker requests started/completed, data/inst
1879system.cpu1.itb.walker.walkRequestOrigin_Completed::total 64187 # Table walker requests started/completed, data/inst
1880system.cpu1.itb.walker.walkRequestOrigin::total 154687 # Table walker requests started/completed, data/inst
1881system.cpu1.itb.inst_hits 226870355 # ITB inst hits
1882system.cpu1.itb.inst_misses 90500 # ITB inst misses
1883system.cpu1.itb.read_hits 0 # DTB read hits
1884system.cpu1.itb.read_misses 0 # DTB read misses
1885system.cpu1.itb.write_hits 0 # DTB write hits
1886system.cpu1.itb.write_misses 0 # DTB write misses
1887system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
1888system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1889system.cpu1.itb.flush_tlb_mva_asid 46091 # Number of times TLB was flushed by MVA & ASID
1890system.cpu1.itb.flush_tlb_asid 1084 # Number of times TLB was flushed by ASID
1891system.cpu1.itb.flush_entries 32400 # Number of entries that have been flushed from TLB
1892system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1893system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1894system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1895system.cpu1.itb.perms_faults 223247 # Number of TLB faults due to permissions restrictions
1896system.cpu1.itb.read_accesses 0 # DTB read accesses
1897system.cpu1.itb.write_accesses 0 # DTB write accesses
1898system.cpu1.itb.inst_accesses 226960855 # ITB inst accesses
1899system.cpu1.itb.hits 226870355 # DTB hits
1900system.cpu1.itb.misses 90500 # DTB misses
1901system.cpu1.itb.accesses 226960855 # DTB accesses
1902system.cpu1.numCycles 812532558 # number of cpu cycles simulated
1903system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1904system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1905system.cpu1.fetch.icacheStallCycles 91759705 # Number of cycles fetch is stalled on an Icache miss
1906system.cpu1.fetch.Insts 638580491 # Number of instructions fetch has processed
1907system.cpu1.fetch.Branches 144214101 # Number of branches that fetch encountered
1908system.cpu1.fetch.predictedBranches 85642558 # Number of branches that fetch has predicted taken
1909system.cpu1.fetch.Cycles 676433492 # Number of cycles fetch has run and was not squashing or blocked
1910system.cpu1.fetch.SquashCycles 15215298 # Number of cycles fetch has spent squashing
1911system.cpu1.fetch.TlbCycles 2168545 # Number of cycles fetch has spent waiting for tlb
1912system.cpu1.fetch.MiscStallCycles 336979 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1913system.cpu1.fetch.PendingTrapStallCycles 6484962 # Number of stall cycles due to pending traps
1914system.cpu1.fetch.PendingQuiesceStallCycles 887415 # Number of stall cycles due to pending quiesce instructions
1915system.cpu1.fetch.IcacheWaitRetryStallCycles 890942 # Number of stall cycles due to full MSHR
1916system.cpu1.fetch.CacheLines 226625049 # Number of cache lines fetched
1917system.cpu1.fetch.IcacheSquashes 1736948 # Number of outstanding Icache misses that were squashed
1918system.cpu1.fetch.ItlbSquashes 29701 # Number of outstanding ITLB misses that were squashed
1919system.cpu1.fetch.rateDist::samples 786569689 # Number of instructions fetched each cycle (Total)
1920system.cpu1.fetch.rateDist::mean 0.951781 # Number of instructions fetched each cycle (Total)
1921system.cpu1.fetch.rateDist::stdev 1.213726 # Number of instructions fetched each cycle (Total)
1922system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1923system.cpu1.fetch.rateDist::0 428022323 54.42% 54.42% # Number of instructions fetched each cycle (Total)
1924system.cpu1.fetch.rateDist::1 139668800 17.76% 72.17% # Number of instructions fetched each cycle (Total)
1925system.cpu1.fetch.rateDist::2 47662444 6.06% 78.23% # Number of instructions fetched each cycle (Total)
1926system.cpu1.fetch.rateDist::3 171216122 21.77% 100.00% # Number of instructions fetched each cycle (Total)
1927system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1928system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1929system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
1930system.cpu1.fetch.rateDist::total 786569689 # Number of instructions fetched each cycle (Total)
1931system.cpu1.fetch.branchRate 0.177487 # Number of branch fetches per cycle
1932system.cpu1.fetch.rate 0.785914 # Number of inst fetches per cycle
1933system.cpu1.decode.IdleCycles 110960591 # Number of cycles decode is idle
1934system.cpu1.decode.BlockedCycles 393393476 # Number of cycles decode is blocked
1935system.cpu1.decode.RunCycles 236254465 # Number of cycles decode is running
1936system.cpu1.decode.UnblockCycles 40475350 # Number of cycles decode is unblocking
1937system.cpu1.decode.SquashCycles 5485807 # Number of cycles decode is squashing
1938system.cpu1.decode.BranchResolved 20188292 # Number of times decode resolved a branch
1939system.cpu1.decode.BranchMispred 2163849 # Number of times decode detected a branch misprediction
1940system.cpu1.decode.DecodedInsts 661116472 # Number of instructions handled by decode
1941system.cpu1.decode.SquashedInsts 24295467 # Number of squashed instructions handled by decode
1942system.cpu1.rename.SquashCycles 5485807 # Number of cycles rename is squashing
1943system.cpu1.rename.IdleCycles 148680347 # Number of cycles rename is idle
1944system.cpu1.rename.BlockCycles 59294510 # Number of cycles rename is blocking
1945system.cpu1.rename.serializeStallCycles 260447701 # count of cycles rename stalled for serializing inst
1946system.cpu1.rename.RunCycles 238523513 # Number of cycles rename is running
1947system.cpu1.rename.UnblockCycles 74137811 # Number of cycles rename is unblocking
1948system.cpu1.rename.RenamedInsts 642734014 # Number of instructions processed by rename
1949system.cpu1.rename.SquashedInsts 6463851 # Number of squashed instructions processed by rename
1950system.cpu1.rename.ROBFullEvents 12050420 # Number of times rename has blocked due to ROB full
1951system.cpu1.rename.IQFullEvents 431614 # Number of times rename has blocked due to IQ full
1952system.cpu1.rename.LQFullEvents 1024133 # Number of times rename has blocked due to LQ full
1953system.cpu1.rename.SQFullEvents 35807802 # Number of times rename has blocked due to SQ full
1954system.cpu1.rename.FullRegisterEvents 12087 # Number of times there has been no free registers
1955system.cpu1.rename.RenamedOperands 613144176 # Number of destination operands rename has renamed
1956system.cpu1.rename.RenameLookups 993338486 # Number of register rename lookups that rename has made
1957system.cpu1.rename.int_rename_lookups 758389620 # Number of integer rename lookups
1958system.cpu1.rename.fp_rename_lookups 787806 # Number of floating rename lookups
1959system.cpu1.rename.CommittedMaps 551826661 # Number of HB maps that are committed
1960system.cpu1.rename.UndoneMaps 61317509 # Number of HB maps that are undone due to squashing
1961system.cpu1.rename.serializingInsts 17340731 # count of serializing insts renamed
1962system.cpu1.rename.tempSerializingInsts 15198476 # count of temporary serializing insts renamed
1963system.cpu1.rename.skidInsts 81471302 # count of insts added to the skid buffer
1964system.cpu1.memDep0.insertedLoads 106673767 # Number of loads inserted to the mem dependence unit.
1965system.cpu1.memDep0.insertedStores 89326102 # Number of stores inserted to the mem dependence unit.
1966system.cpu1.memDep0.conflictingLoads 10094322 # Number of conflicting loads.
1967system.cpu1.memDep0.conflictingStores 8631476 # Number of conflicting stores.
1968system.cpu1.iq.iqInstsAdded 618122262 # Number of instructions added to the IQ (excludes non-spec)
1969system.cpu1.iq.iqNonSpecInstsAdded 17529509 # Number of non-speculative instructions added to the IQ
1970system.cpu1.iq.iqInstsIssued 623787865 # Number of instructions issued
1971system.cpu1.iq.iqSquashedInstsIssued 2873824 # Number of squashed instructions issued
1972system.cpu1.iq.iqSquashedInstsExamined 57783921 # Number of squashed instructions iterated over during squash; mainly for profiling
1973system.cpu1.iq.iqSquashedOperandsExamined 37389903 # Number of squashed operands that are examined and possibly removed from graph
1974system.cpu1.iq.iqSquashedNonSpecRemoved 307135 # Number of squashed non-spec instructions that were removed
1975system.cpu1.iq.issued_per_cycle::samples 786569689 # Number of insts issued each cycle
1976system.cpu1.iq.issued_per_cycle::mean 0.793048 # Number of insts issued each cycle
1977system.cpu1.iq.issued_per_cycle::stdev 1.056857 # Number of insts issued each cycle
1978system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1979system.cpu1.iq.issued_per_cycle::0 444068370 56.46% 56.46% # Number of insts issued each cycle
1980system.cpu1.iq.issued_per_cycle::1 146437024 18.62% 75.07% # Number of insts issued each cycle
1981system.cpu1.iq.issued_per_cycle::2 119059525 15.14% 90.21% # Number of insts issued each cycle
1982system.cpu1.iq.issued_per_cycle::3 68792645 8.75% 98.96% # Number of insts issued each cycle
1983system.cpu1.iq.issued_per_cycle::4 8206769 1.04% 100.00% # Number of insts issued each cycle
1984system.cpu1.iq.issued_per_cycle::5 5356 0.00% 100.00% # Number of insts issued each cycle
1985system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
1986system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
1987system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
1988system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1989system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1990system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
1991system.cpu1.iq.issued_per_cycle::total 786569689 # Number of insts issued each cycle
1992system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1993system.cpu1.iq.fu_full::IntAlu 62505184 44.18% 44.18% # attempts to use FU when none available
1994system.cpu1.iq.fu_full::IntMult 68578 0.05% 44.23% # attempts to use FU when none available
1995system.cpu1.iq.fu_full::IntDiv 15954 0.01% 44.24% # attempts to use FU when none available
1996system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.24% # attempts to use FU when none available
1997system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.24% # attempts to use FU when none available
1998system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.24% # attempts to use FU when none available
1999system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.24% # attempts to use FU when none available
2000system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.24% # attempts to use FU when none available
2001system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.24% # attempts to use FU when none available
2002system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.24% # attempts to use FU when none available
2003system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.24% # attempts to use FU when none available
2004system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.24% # attempts to use FU when none available
2005system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.24% # attempts to use FU when none available
2006system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.24% # attempts to use FU when none available
2007system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.24% # attempts to use FU when none available
2008system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.24% # attempts to use FU when none available
2009system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.24% # attempts to use FU when none available
2010system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.24% # attempts to use FU when none available
2011system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.24% # attempts to use FU when none available
2012system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.24% # attempts to use FU when none available
2013system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.24% # attempts to use FU when none available
2014system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.24% # attempts to use FU when none available
2015system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.24% # attempts to use FU when none available
2016system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.24% # attempts to use FU when none available
2017system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.24% # attempts to use FU when none available
2018system.cpu1.iq.fu_full::SimdFloatMisc 29 0.00% 44.24% # attempts to use FU when none available
2019system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.24% # attempts to use FU when none available
2020system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.24% # attempts to use FU when none available
2021system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.24% # attempts to use FU when none available
2022system.cpu1.iq.fu_full::MemRead 38525280 27.23% 71.47% # attempts to use FU when none available
2023system.cpu1.iq.fu_full::MemWrite 40370294 28.53% 100.00% # attempts to use FU when none available
2024system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
2025system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2026system.cpu1.iq.FU_type_0::No_OpClass 56 0.00% 0.00% # Type of FU issued
2027system.cpu1.iq.FU_type_0::IntAlu 425111535 68.15% 68.15% # Type of FU issued
2028system.cpu1.iq.FU_type_0::IntMult 1458161 0.23% 68.38% # Type of FU issued
2029system.cpu1.iq.FU_type_0::IntDiv 82493 0.01% 68.40% # Type of FU issued
2030system.cpu1.iq.FU_type_0::FloatAdd 4 0.00% 68.40% # Type of FU issued
2031system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.40% # Type of FU issued
2032system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.40% # Type of FU issued
2033system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.40% # Type of FU issued
2034system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.40% # Type of FU issued
2035system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued
2036system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued
2037system.cpu1.iq.FU_type_0::SimdAddAcc 1 0.00% 68.40% # Type of FU issued
2038system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.40% # Type of FU issued
2039system.cpu1.iq.FU_type_0::SimdCmp 1 0.00% 68.40% # Type of FU issued
2040system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.40% # Type of FU issued
2041system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.40% # Type of FU issued
2042system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.40% # Type of FU issued
2043system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.40% # Type of FU issued
2044system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.40% # Type of FU issued
2045system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.40% # Type of FU issued
2046system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.40% # Type of FU issued
2047system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.40% # Type of FU issued
2048system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.40% # Type of FU issued
2049system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.40% # Type of FU issued
2050system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.40% # Type of FU issued
2051system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.40% # Type of FU issued
2052system.cpu1.iq.FU_type_0::SimdFloatMisc 80022 0.01% 68.41% # Type of FU issued
2053system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.41% # Type of FU issued
2054system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.41% # Type of FU issued
2055system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.41% # Type of FU issued
2056system.cpu1.iq.FU_type_0::MemRead 109884961 17.62% 86.03% # Type of FU issued
2057system.cpu1.iq.FU_type_0::MemWrite 87170631 13.97% 100.00% # Type of FU issued
2058system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
2059system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2060system.cpu1.iq.FU_type_0::total 623787865 # Type of FU issued
2061system.cpu1.iq.rate 0.767708 # Inst issue rate
2062system.cpu1.iq.fu_busy_cnt 141485319 # FU busy when requested
2063system.cpu1.iq.fu_busy_rate 0.226816 # FU busy rate (busy events/executed inst)
2064system.cpu1.iq.int_inst_queue_reads 2177185436 # Number of integer instruction queue reads
2065system.cpu1.iq.int_inst_queue_writes 693073885 # Number of integer instruction queue writes
2066system.cpu1.iq.int_inst_queue_wakeup_accesses 605244442 # Number of integer instruction queue wakeup accesses
2067system.cpu1.iq.fp_inst_queue_reads 1319124 # Number of floating instruction queue reads
2068system.cpu1.iq.fp_inst_queue_writes 525529 # Number of floating instruction queue writes
2069system.cpu1.iq.fp_inst_queue_wakeup_accesses 491804 # Number of floating instruction queue wakeup accesses
2070system.cpu1.iq.int_alu_accesses 764456486 # Number of integer alu accesses
2071system.cpu1.iq.fp_alu_accesses 816642 # Number of floating point alu accesses
2072system.cpu1.iew.lsq.thread0.forwLoads 2875534 # Number of loads that had data forwarded from stores
2073system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2074system.cpu1.iew.lsq.thread0.squashedLoads 13536096 # Number of loads squashed
2075system.cpu1.iew.lsq.thread0.ignoredResponses 19732 # Number of memory responses ignored because the instruction is squashed
2076system.cpu1.iew.lsq.thread0.memOrderViolation 165171 # Number of memory ordering violations
2077system.cpu1.iew.lsq.thread0.squashedStores 5907805 # Number of stores squashed
2078system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2079system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2080system.cpu1.iew.lsq.thread0.rescheduledLoads 2920913 # Number of loads that were rescheduled
2081system.cpu1.iew.lsq.thread0.cacheBlocked 4601873 # Number of times an access to memory failed due to the cache being blocked
2082system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2083system.cpu1.iew.iewSquashCycles 5485807 # Number of cycles IEW is squashing
2084system.cpu1.iew.iewBlockCycles 8833718 # Number of cycles IEW is blocking
2085system.cpu1.iew.iewUnblockCycles 2787810 # Number of cycles IEW is unblocking
2086system.cpu1.iew.iewDispatchedInsts 635796262 # Number of instructions dispatched to IQ
2087system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2088system.cpu1.iew.iewDispLoadInsts 106673767 # Number of dispatched load instructions
2089system.cpu1.iew.iewDispStoreInsts 89326102 # Number of dispatched store instructions
2090system.cpu1.iew.iewDispNonSpecInsts 14923932 # Number of dispatched non-speculative instructions
2091system.cpu1.iew.iewIQFullEvents 69191 # Number of times the IQ has become full, causing a stall
2092system.cpu1.iew.iewLSQFullEvents 2639688 # Number of times the LSQ has become full, causing a stall
2093system.cpu1.iew.memOrderViolationEvents 165171 # Number of memory order violations
2094system.cpu1.iew.predictedTakenIncorrect 2071854 # Number of branches that were predicted taken incorrectly
2095system.cpu1.iew.predictedNotTakenIncorrect 3210854 # Number of branches that were predicted not taken incorrectly
2096system.cpu1.iew.branchMispredicts 5282708 # Number of branch mispredicts detected at execute
2097system.cpu1.iew.iewExecutedInsts 615332242 # Number of executed instructions
2098system.cpu1.iew.iewExecLoadInsts 106464546 # Number of load instructions executed
2099system.cpu1.iew.iewExecSquashedInsts 7808914 # Number of squashed instructions skipped in execute
2100system.cpu1.iew.exec_swp 0 # number of swp insts executed
2101system.cpu1.iew.exec_nop 144491 # number of nop insts executed
2102system.cpu1.iew.exec_refs 192321367 # number of memory reference insts executed
2103system.cpu1.iew.exec_branches 115394599 # Number of branches executed
2104system.cpu1.iew.exec_stores 85856821 # Number of stores executed
2105system.cpu1.iew.exec_rate 0.757302 # Inst execution rate
2106system.cpu1.iew.wb_sent 606557665 # cumulative count of insts sent to commit
2107system.cpu1.iew.wb_count 605736246 # cumulative count of insts written-back
2108system.cpu1.iew.wb_producers 294174085 # num instructions producing a value
2109system.cpu1.iew.wb_consumers 482464820 # num instructions consuming a value
2110system.cpu1.iew.wb_rate 0.745492 # insts written-back per cycle
2111system.cpu1.iew.wb_fanout 0.609732 # average fanout of values written-back
2112system.cpu1.commit.commitSquashedInsts 50535620 # The number of squashed insts skipped by commit
2113system.cpu1.commit.commitNonSpecStalls 17222374 # The number of times commit has been forced to stall to communicate backwards
2114system.cpu1.commit.branchMispredicts 4915629 # The number of times a branch was mispredicted
2115system.cpu1.commit.committed_per_cycle::samples 776983088 # Number of insts commited each cycle
2116system.cpu1.commit.committed_per_cycle::mean 0.743733 # Number of insts commited each cycle
2117system.cpu1.commit.committed_per_cycle::stdev 1.546908 # Number of insts commited each cycle
2118system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2119system.cpu1.commit.committed_per_cycle::0 522401316 67.23% 67.23% # Number of insts commited each cycle
2120system.cpu1.commit.committed_per_cycle::1 133381083 17.17% 84.40% # Number of insts commited each cycle
2121system.cpu1.commit.committed_per_cycle::2 55837578 7.19% 91.59% # Number of insts commited each cycle
2122system.cpu1.commit.committed_per_cycle::3 18787317 2.42% 94.01% # Number of insts commited each cycle
2123system.cpu1.commit.committed_per_cycle::4 13118953 1.69% 95.69% # Number of insts commited each cycle
2124system.cpu1.commit.committed_per_cycle::5 9117290 1.17% 96.87% # Number of insts commited each cycle
2125system.cpu1.commit.committed_per_cycle::6 6295998 0.81% 97.68% # Number of insts commited each cycle
2126system.cpu1.commit.committed_per_cycle::7 3737021 0.48% 98.16% # Number of insts commited each cycle
2127system.cpu1.commit.committed_per_cycle::8 14306532 1.84% 100.00% # Number of insts commited each cycle
2128system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2129system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2130system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2131system.cpu1.commit.committed_per_cycle::total 776983088 # Number of insts commited each cycle
2132system.cpu1.commit.committedInsts 491216523 # Number of instructions committed
2133system.cpu1.commit.committedOps 577867843 # Number of ops (including micro ops) committed
2134system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2135system.cpu1.commit.refs 176555967 # Number of memory references committed
2136system.cpu1.commit.loads 93137670 # Number of loads committed
2137system.cpu1.commit.membars 4128399 # Number of memory barriers committed
2138system.cpu1.commit.branches 109594417 # Number of branches committed
2139system.cpu1.commit.fp_insts 483207 # Number of committed floating point instructions.
2140system.cpu1.commit.int_insts 530271703 # Number of committed integer instructions.
2141system.cpu1.commit.function_calls 14440728 # Number of function calls committed.
2142system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2143system.cpu1.commit.op_class_0::IntAlu 399975864 69.22% 69.22% # Class of committed instruction
2144system.cpu1.commit.op_class_0::IntMult 1198206 0.21% 69.42% # Class of committed instruction
2145system.cpu1.commit.op_class_0::IntDiv 65313 0.01% 69.43% # Class of committed instruction
2146system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.43% # Class of committed instruction
2147system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.43% # Class of committed instruction
2148system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.43% # Class of committed instruction
2149system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.43% # Class of committed instruction
2150system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.43% # Class of committed instruction
2151system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.43% # Class of committed instruction
2152system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.43% # Class of committed instruction
2153system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.43% # Class of committed instruction
2154system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.43% # Class of committed instruction
2155system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.43% # Class of committed instruction
2156system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.43% # Class of committed instruction
2157system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.43% # Class of committed instruction
2158system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.43% # Class of committed instruction
2159system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.43% # Class of committed instruction
2160system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.43% # Class of committed instruction
2161system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.43% # Class of committed instruction
2162system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.43% # Class of committed instruction
2163system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.43% # Class of committed instruction
2164system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.43% # Class of committed instruction
2165system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.43% # Class of committed instruction
2166system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.43% # Class of committed instruction
2167system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.43% # Class of committed instruction
2168system.cpu1.commit.op_class_0::SimdFloatMisc 72493 0.01% 69.45% # Class of committed instruction
2169system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.45% # Class of committed instruction
2170system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.45% # Class of committed instruction
2171system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.45% # Class of committed instruction
2172system.cpu1.commit.op_class_0::MemRead 93137670 16.12% 85.56% # Class of committed instruction
2173system.cpu1.commit.op_class_0::MemWrite 83418297 14.44% 100.00% # Class of committed instruction
2174system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2175system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2176system.cpu1.commit.op_class_0::total 577867843 # Class of committed instruction
2177system.cpu1.commit.bw_lim_events 14306532 # number cycles where commit BW limit reached
2178system.cpu1.rob.rob_reads 1386603636 # The number of ROB reads
2179system.cpu1.rob.rob_writes 1266352729 # The number of ROB writes
2180system.cpu1.timesIdled 1031751 # Number of times that the entire CPU went into an idle state and unscheduled itself
2181system.cpu1.idleCycles 25962869 # Total number of cycles that the CPU has spent unscheduled due to idling
2182system.cpu1.quiesceCycles 94124971438 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2183system.cpu1.committedInsts 491216523 # Number of Instructions Simulated
2184system.cpu1.committedOps 577867843 # Number of Ops (including micro ops) Simulated
2185system.cpu1.cpi 1.654123 # CPI: Cycles Per Instruction
2186system.cpu1.cpi_total 1.654123 # CPI: Total CPI of All Threads
2187system.cpu1.ipc 0.604550 # IPC: Instructions Per Cycle
2188system.cpu1.ipc_total 0.604550 # IPC: Total IPC of All Threads
2189system.cpu1.int_regfile_reads 726234004 # number of integer regfile reads
2190system.cpu1.int_regfile_writes 431188126 # number of integer regfile writes
2191system.cpu1.fp_regfile_reads 774766 # number of floating regfile reads
2192system.cpu1.fp_regfile_writes 462404 # number of floating regfile writes
2193system.cpu1.cc_regfile_reads 133303662 # number of cc regfile reads
2194system.cpu1.cc_regfile_writes 133988748 # number of cc regfile writes
2195system.cpu1.misc_regfile_reads 1377831690 # number of misc regfile reads
2196system.cpu1.misc_regfile_writes 17262707 # number of misc regfile writes
2197system.cpu1.dcache.tags.replacements 6040824 # number of replacements
2198system.cpu1.dcache.tags.tagsinuse 459.378668 # Cycle average of tags in use
2199system.cpu1.dcache.tags.total_refs 164299100 # Total number of references to valid blocks.
2200system.cpu1.dcache.tags.sampled_refs 6041336 # Sample count of references to valid blocks.
2201system.cpu1.dcache.tags.avg_refs 27.195822 # Average number of references to valid blocks.
2202system.cpu1.dcache.tags.warmup_cycle 8482617709500 # Cycle when the warmup percentage was hit.
2203system.cpu1.dcache.tags.occ_blocks::cpu1.data 459.378668 # Average occupied blocks per requestor
2204system.cpu1.dcache.tags.occ_percent::cpu1.data 0.897224 # Average percentage of cache occupancy
2205system.cpu1.dcache.tags.occ_percent::total 0.897224 # Average percentage of cache occupancy
2206system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2207system.cpu1.dcache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id
2208system.cpu1.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id
2209system.cpu1.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id
2210system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2211system.cpu1.dcache.tags.tag_accesses 366496301 # Number of tag accesses
2212system.cpu1.dcache.tags.data_accesses 366496301 # Number of data accesses
2213system.cpu1.dcache.ReadReq_hits::cpu1.data 86507946 # number of ReadReq hits
2214system.cpu1.dcache.ReadReq_hits::total 86507946 # number of ReadReq hits
2215system.cpu1.dcache.WriteReq_hits::cpu1.data 72726229 # number of WriteReq hits
2216system.cpu1.dcache.WriteReq_hits::total 72726229 # number of WriteReq hits
2217system.cpu1.dcache.SoftPFReq_hits::cpu1.data 199332 # number of SoftPFReq hits
2218system.cpu1.dcache.SoftPFReq_hits::total 199332 # number of SoftPFReq hits
2219system.cpu1.dcache.WriteLineReq_hits::cpu1.data 142639 # number of WriteLineReq hits
2220system.cpu1.dcache.WriteLineReq_hits::total 142639 # number of WriteLineReq hits
2221system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1934214 # number of LoadLockedReq hits
2222system.cpu1.dcache.LoadLockedReq_hits::total 1934214 # number of LoadLockedReq hits
2223system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1984655 # number of StoreCondReq hits
2224system.cpu1.dcache.StoreCondReq_hits::total 1984655 # number of StoreCondReq hits
2225system.cpu1.dcache.demand_hits::cpu1.data 159376814 # number of demand (read+write) hits
2226system.cpu1.dcache.demand_hits::total 159376814 # number of demand (read+write) hits
2227system.cpu1.dcache.overall_hits::cpu1.data 159576146 # number of overall hits
2228system.cpu1.dcache.overall_hits::total 159576146 # number of overall hits
2229system.cpu1.dcache.ReadReq_misses::cpu1.data 7084890 # number of ReadReq misses
2230system.cpu1.dcache.ReadReq_misses::total 7084890 # number of ReadReq misses
2231system.cpu1.dcache.WriteReq_misses::cpu1.data 7887926 # number of WriteReq misses
2232system.cpu1.dcache.WriteReq_misses::total 7887926 # number of WriteReq misses
2233system.cpu1.dcache.SoftPFReq_misses::cpu1.data 742812 # number of SoftPFReq misses
2234system.cpu1.dcache.SoftPFReq_misses::total 742812 # number of SoftPFReq misses
2235system.cpu1.dcache.WriteLineReq_misses::cpu1.data 468512 # number of WriteLineReq misses
2236system.cpu1.dcache.WriteLineReq_misses::total 468512 # number of WriteLineReq misses
2237system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 301623 # number of LoadLockedReq misses
2238system.cpu1.dcache.LoadLockedReq_misses::total 301623 # number of LoadLockedReq misses
2239system.cpu1.dcache.StoreCondReq_misses::cpu1.data 202162 # number of StoreCondReq misses
2240system.cpu1.dcache.StoreCondReq_misses::total 202162 # number of StoreCondReq misses
2241system.cpu1.dcache.demand_misses::cpu1.data 15441328 # number of demand (read+write) misses
2242system.cpu1.dcache.demand_misses::total 15441328 # number of demand (read+write) misses
2243system.cpu1.dcache.overall_misses::cpu1.data 16184140 # number of overall misses
2244system.cpu1.dcache.overall_misses::total 16184140 # number of overall misses
2245system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 122386342500 # number of ReadReq miss cycles
2246system.cpu1.dcache.ReadReq_miss_latency::total 122386342500 # number of ReadReq miss cycles
2247system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 173974758337 # number of WriteReq miss cycles
2248system.cpu1.dcache.WriteReq_miss_latency::total 173974758337 # number of WriteReq miss cycles
2249system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20327422974 # number of WriteLineReq miss cycles
2250system.cpu1.dcache.WriteLineReq_miss_latency::total 20327422974 # number of WriteLineReq miss cycles
2251system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 5004935500 # number of LoadLockedReq miss cycles
2252system.cpu1.dcache.LoadLockedReq_miss_latency::total 5004935500 # number of LoadLockedReq miss cycles
2253system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5709587500 # number of StoreCondReq miss cycles
2254system.cpu1.dcache.StoreCondReq_miss_latency::total 5709587500 # number of StoreCondReq miss cycles
2255system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3496000 # number of StoreCondFailReq miss cycles
2256system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3496000 # number of StoreCondFailReq miss cycles
2257system.cpu1.dcache.demand_miss_latency::cpu1.data 316688523811 # number of demand (read+write) miss cycles
2258system.cpu1.dcache.demand_miss_latency::total 316688523811 # number of demand (read+write) miss cycles
2259system.cpu1.dcache.overall_miss_latency::cpu1.data 316688523811 # number of overall miss cycles
2260system.cpu1.dcache.overall_miss_latency::total 316688523811 # number of overall miss cycles
2261system.cpu1.dcache.ReadReq_accesses::cpu1.data 93592836 # number of ReadReq accesses(hits+misses)
2262system.cpu1.dcache.ReadReq_accesses::total 93592836 # number of ReadReq accesses(hits+misses)
2263system.cpu1.dcache.WriteReq_accesses::cpu1.data 80614155 # number of WriteReq accesses(hits+misses)
2264system.cpu1.dcache.WriteReq_accesses::total 80614155 # number of WriteReq accesses(hits+misses)
2265system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 942144 # number of SoftPFReq accesses(hits+misses)
2266system.cpu1.dcache.SoftPFReq_accesses::total 942144 # number of SoftPFReq accesses(hits+misses)
2267system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 611151 # number of WriteLineReq accesses(hits+misses)
2268system.cpu1.dcache.WriteLineReq_accesses::total 611151 # number of WriteLineReq accesses(hits+misses)
2269system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2235837 # number of LoadLockedReq accesses(hits+misses)
2270system.cpu1.dcache.LoadLockedReq_accesses::total 2235837 # number of LoadLockedReq accesses(hits+misses)
2271system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2186817 # number of StoreCondReq accesses(hits+misses)
2272system.cpu1.dcache.StoreCondReq_accesses::total 2186817 # number of StoreCondReq accesses(hits+misses)
2273system.cpu1.dcache.demand_accesses::cpu1.data 174818142 # number of demand (read+write) accesses
2274system.cpu1.dcache.demand_accesses::total 174818142 # number of demand (read+write) accesses
2275system.cpu1.dcache.overall_accesses::cpu1.data 175760286 # number of overall (read+write) accesses
2276system.cpu1.dcache.overall_accesses::total 175760286 # number of overall (read+write) accesses
2277system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.075699 # miss rate for ReadReq accesses
2278system.cpu1.dcache.ReadReq_miss_rate::total 0.075699 # miss rate for ReadReq accesses
2279system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.097848 # miss rate for WriteReq accesses
2280system.cpu1.dcache.WriteReq_miss_rate::total 0.097848 # miss rate for WriteReq accesses
2281system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.788427 # miss rate for SoftPFReq accesses
2282system.cpu1.dcache.SoftPFReq_miss_rate::total 0.788427 # miss rate for SoftPFReq accesses
2283system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.766606 # miss rate for WriteLineReq accesses
2284system.cpu1.dcache.WriteLineReq_miss_rate::total 0.766606 # miss rate for WriteLineReq accesses
2285system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.134904 # miss rate for LoadLockedReq accesses
2286system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.134904 # miss rate for LoadLockedReq accesses
2287system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.092446 # miss rate for StoreCondReq accesses
2288system.cpu1.dcache.StoreCondReq_miss_rate::total 0.092446 # miss rate for StoreCondReq accesses
2289system.cpu1.dcache.demand_miss_rate::cpu1.data 0.088328 # miss rate for demand accesses
2290system.cpu1.dcache.demand_miss_rate::total 0.088328 # miss rate for demand accesses
2291system.cpu1.dcache.overall_miss_rate::cpu1.data 0.092081 # miss rate for overall accesses
2292system.cpu1.dcache.overall_miss_rate::total 0.092081 # miss rate for overall accesses
2293system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17274.275606 # average ReadReq miss latency
2294system.cpu1.dcache.ReadReq_avg_miss_latency::total 17274.275606 # average ReadReq miss latency
2295system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22055.830435 # average WriteReq miss latency
2296system.cpu1.dcache.WriteReq_avg_miss_latency::total 22055.830435 # average WriteReq miss latency
2297system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 43387.198138 # average WriteLineReq miss latency
2298system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 43387.198138 # average WriteLineReq miss latency
2299system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16593.348319 # average LoadLockedReq miss latency
2300system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16593.348319 # average LoadLockedReq miss latency
2301system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 28242.634620 # average StoreCondReq miss latency
2302system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 28242.634620 # average StoreCondReq miss latency
2303system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
2304system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2305system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20509.150755 # average overall miss latency
2306system.cpu1.dcache.demand_avg_miss_latency::total 20509.150755 # average overall miss latency
2307system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19567.831458 # average overall miss latency
2308system.cpu1.dcache.overall_avg_miss_latency::total 19567.831458 # average overall miss latency
2309system.cpu1.dcache.blocked_cycles::no_mshrs 5568492 # number of cycles access was blocked
2310system.cpu1.dcache.blocked_cycles::no_targets 28779495 # number of cycles access was blocked
2311system.cpu1.dcache.blocked::no_mshrs 387755 # number of cycles access was blocked
2312system.cpu1.dcache.blocked::no_targets 802381 # number of cycles access was blocked
2313system.cpu1.dcache.avg_blocked_cycles::no_mshrs 14.360852 # average number of cycles each access was blocked
2314system.cpu1.dcache.avg_blocked_cycles::no_targets 35.867618 # average number of cycles each access was blocked
2315system.cpu1.dcache.writebacks::writebacks 6040976 # number of writebacks
2316system.cpu1.dcache.writebacks::total 6040976 # number of writebacks
2317system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3573916 # number of ReadReq MSHR hits
2318system.cpu1.dcache.ReadReq_mshr_hits::total 3573916 # number of ReadReq MSHR hits
2319system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6375716 # number of WriteReq MSHR hits
2320system.cpu1.dcache.WriteReq_mshr_hits::total 6375716 # number of WriteReq MSHR hits
2321system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3475 # number of WriteLineReq MSHR hits
2322system.cpu1.dcache.WriteLineReq_mshr_hits::total 3475 # number of WriteLineReq MSHR hits
2323system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 153685 # number of LoadLockedReq MSHR hits
2324system.cpu1.dcache.LoadLockedReq_mshr_hits::total 153685 # number of LoadLockedReq MSHR hits
2325system.cpu1.dcache.demand_mshr_hits::cpu1.data 9953107 # number of demand (read+write) MSHR hits
2326system.cpu1.dcache.demand_mshr_hits::total 9953107 # number of demand (read+write) MSHR hits
2327system.cpu1.dcache.overall_mshr_hits::cpu1.data 9953107 # number of overall MSHR hits
2328system.cpu1.dcache.overall_mshr_hits::total 9953107 # number of overall MSHR hits
2329system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3510974 # number of ReadReq MSHR misses
2330system.cpu1.dcache.ReadReq_mshr_misses::total 3510974 # number of ReadReq MSHR misses
2331system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1512210 # number of WriteReq MSHR misses
2332system.cpu1.dcache.WriteReq_mshr_misses::total 1512210 # number of WriteReq MSHR misses
2333system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 742708 # number of SoftPFReq MSHR misses
2334system.cpu1.dcache.SoftPFReq_mshr_misses::total 742708 # number of SoftPFReq MSHR misses
2335system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 465037 # number of WriteLineReq MSHR misses
2336system.cpu1.dcache.WriteLineReq_mshr_misses::total 465037 # number of WriteLineReq MSHR misses
2337system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 147938 # number of LoadLockedReq MSHR misses
2338system.cpu1.dcache.LoadLockedReq_mshr_misses::total 147938 # number of LoadLockedReq MSHR misses
2339system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202156 # number of StoreCondReq MSHR misses
2340system.cpu1.dcache.StoreCondReq_mshr_misses::total 202156 # number of StoreCondReq MSHR misses
2341system.cpu1.dcache.demand_mshr_misses::cpu1.data 5488221 # number of demand (read+write) MSHR misses
2342system.cpu1.dcache.demand_mshr_misses::total 5488221 # number of demand (read+write) MSHR misses
2343system.cpu1.dcache.overall_mshr_misses::cpu1.data 6230929 # number of overall MSHR misses
2344system.cpu1.dcache.overall_mshr_misses::total 6230929 # number of overall MSHR misses
2345system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 18701 # number of ReadReq MSHR uncacheable
2346system.cpu1.dcache.ReadReq_mshr_uncacheable::total 18701 # number of ReadReq MSHR uncacheable
2347system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 17029 # number of WriteReq MSHR uncacheable
2348system.cpu1.dcache.WriteReq_mshr_uncacheable::total 17029 # number of WriteReq MSHR uncacheable
2349system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 35730 # number of overall MSHR uncacheable misses
2350system.cpu1.dcache.overall_mshr_uncacheable_misses::total 35730 # number of overall MSHR uncacheable misses
2351system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 55262810500 # number of ReadReq MSHR miss cycles
2352system.cpu1.dcache.ReadReq_mshr_miss_latency::total 55262810500 # number of ReadReq MSHR miss cycles
2353system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 37074565990 # number of WriteReq MSHR miss cycles
2354system.cpu1.dcache.WriteReq_mshr_miss_latency::total 37074565990 # number of WriteReq MSHR miss cycles
2355system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 18477747500 # number of SoftPFReq MSHR miss cycles
2356system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 18477747500 # number of SoftPFReq MSHR miss cycles
2357system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 19695654974 # number of WriteLineReq MSHR miss cycles
2358system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 19695654974 # number of WriteLineReq MSHR miss cycles
2359system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 2170800500 # number of LoadLockedReq MSHR miss cycles
2360system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 2170800500 # number of LoadLockedReq MSHR miss cycles
2361system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5507478500 # number of StoreCondReq MSHR miss cycles
2362system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5507478500 # number of StoreCondReq MSHR miss cycles
2363system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3449000 # number of StoreCondFailReq MSHR miss cycles
2364system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3449000 # number of StoreCondFailReq MSHR miss cycles
2365system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 112033031464 # number of demand (read+write) MSHR miss cycles
2366system.cpu1.dcache.demand_mshr_miss_latency::total 112033031464 # number of demand (read+write) MSHR miss cycles
2367system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 130510778964 # number of overall MSHR miss cycles
2368system.cpu1.dcache.overall_mshr_miss_latency::total 130510778964 # number of overall MSHR miss cycles
2369system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3038329000 # number of ReadReq MSHR uncacheable cycles
2370system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3038329000 # number of ReadReq MSHR uncacheable cycles
2371system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3038329000 # number of overall MSHR uncacheable cycles
2372system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3038329000 # number of overall MSHR uncacheable cycles
2373system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037513 # mshr miss rate for ReadReq accesses
2374system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037513 # mshr miss rate for ReadReq accesses
2375system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018759 # mshr miss rate for WriteReq accesses
2376system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018759 # mshr miss rate for WriteReq accesses
2377system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.788317 # mshr miss rate for SoftPFReq accesses
2378system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.788317 # mshr miss rate for SoftPFReq accesses
2379system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.760920 # mshr miss rate for WriteLineReq accesses
2380system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.760920 # mshr miss rate for WriteLineReq accesses
2381system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066167 # mshr miss rate for LoadLockedReq accesses
2382system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066167 # mshr miss rate for LoadLockedReq accesses
2383system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092443 # mshr miss rate for StoreCondReq accesses
2384system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092443 # mshr miss rate for StoreCondReq accesses
2385system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031394 # mshr miss rate for demand accesses
2386system.cpu1.dcache.demand_mshr_miss_rate::total 0.031394 # mshr miss rate for demand accesses
2387system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035451 # mshr miss rate for overall accesses
2388system.cpu1.dcache.overall_mshr_miss_rate::total 0.035451 # mshr miss rate for overall accesses
2389system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15740.022712 # average ReadReq mshr miss latency
2390system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15740.022712 # average ReadReq mshr miss latency
2391system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24516.810489 # average WriteReq mshr miss latency
2392system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24516.810489 # average WriteReq mshr miss latency
2393system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24878.885780 # average SoftPFReq mshr miss latency
2394system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24878.885780 # average SoftPFReq mshr miss latency
2395system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 42352.877242 # average WriteLineReq mshr miss latency
2396system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 42352.877242 # average WriteLineReq mshr miss latency
2397system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14673.718044 # average LoadLockedReq mshr miss latency
2398system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14673.718044 # average LoadLockedReq mshr miss latency
2399system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 27243.705356 # average StoreCondReq mshr miss latency
2400system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 27243.705356 # average StoreCondReq mshr miss latency
2401system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
2402system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2403system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20413.360079 # average overall mshr miss latency
2404system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20413.360079 # average overall mshr miss latency
2405system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20945.637314 # average overall mshr miss latency
2406system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20945.637314 # average overall mshr miss latency
2407system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162468.798460 # average ReadReq mshr uncacheable latency
2408system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162468.798460 # average ReadReq mshr uncacheable latency
2409system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 85035.796250 # average overall mshr uncacheable latency
2410system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 85035.796250 # average overall mshr uncacheable latency
2411system.cpu1.icache.tags.replacements 6229961 # number of replacements
2412system.cpu1.icache.tags.tagsinuse 501.669710 # Cycle average of tags in use
2413system.cpu1.icache.tags.total_refs 220025292 # Total number of references to valid blocks.
2414system.cpu1.icache.tags.sampled_refs 6230473 # Sample count of references to valid blocks.
2415system.cpu1.icache.tags.avg_refs 35.314380 # Average number of references to valid blocks.
2416system.cpu1.icache.tags.warmup_cycle 8522353535000 # Cycle when the warmup percentage was hit.
2417system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.669710 # Average occupied blocks per requestor
2418system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979824 # Average percentage of cache occupancy
2419system.cpu1.icache.tags.occ_percent::total 0.979824 # Average percentage of cache occupancy
2420system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2421system.cpu1.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
2422system.cpu1.icache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id
2423system.cpu1.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id
2424system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2425system.cpu1.icache.tags.tag_accesses 459465626 # Number of tag accesses
2426system.cpu1.icache.tags.data_accesses 459465626 # Number of data accesses
2427system.cpu1.icache.ReadReq_hits::cpu1.inst 220025292 # number of ReadReq hits
2428system.cpu1.icache.ReadReq_hits::total 220025292 # number of ReadReq hits
2429system.cpu1.icache.demand_hits::cpu1.inst 220025292 # number of demand (read+write) hits
2430system.cpu1.icache.demand_hits::total 220025292 # number of demand (read+write) hits
2431system.cpu1.icache.overall_hits::cpu1.inst 220025292 # number of overall hits
2432system.cpu1.icache.overall_hits::total 220025292 # number of overall hits
2433system.cpu1.icache.ReadReq_misses::cpu1.inst 6592262 # number of ReadReq misses
2434system.cpu1.icache.ReadReq_misses::total 6592262 # number of ReadReq misses
2435system.cpu1.icache.demand_misses::cpu1.inst 6592262 # number of demand (read+write) misses
2436system.cpu1.icache.demand_misses::total 6592262 # number of demand (read+write) misses
2437system.cpu1.icache.overall_misses::cpu1.inst 6592262 # number of overall misses
2438system.cpu1.icache.overall_misses::total 6592262 # number of overall misses
2439system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 74756974451 # number of ReadReq miss cycles
2440system.cpu1.icache.ReadReq_miss_latency::total 74756974451 # number of ReadReq miss cycles
2441system.cpu1.icache.demand_miss_latency::cpu1.inst 74756974451 # number of demand (read+write) miss cycles
2442system.cpu1.icache.demand_miss_latency::total 74756974451 # number of demand (read+write) miss cycles
2443system.cpu1.icache.overall_miss_latency::cpu1.inst 74756974451 # number of overall miss cycles
2444system.cpu1.icache.overall_miss_latency::total 74756974451 # number of overall miss cycles
2445system.cpu1.icache.ReadReq_accesses::cpu1.inst 226617554 # number of ReadReq accesses(hits+misses)
2446system.cpu1.icache.ReadReq_accesses::total 226617554 # number of ReadReq accesses(hits+misses)
2447system.cpu1.icache.demand_accesses::cpu1.inst 226617554 # number of demand (read+write) accesses
2448system.cpu1.icache.demand_accesses::total 226617554 # number of demand (read+write) accesses
2449system.cpu1.icache.overall_accesses::cpu1.inst 226617554 # number of overall (read+write) accesses
2450system.cpu1.icache.overall_accesses::total 226617554 # number of overall (read+write) accesses
2451system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029090 # miss rate for ReadReq accesses
2452system.cpu1.icache.ReadReq_miss_rate::total 0.029090 # miss rate for ReadReq accesses
2453system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029090 # miss rate for demand accesses
2454system.cpu1.icache.demand_miss_rate::total 0.029090 # miss rate for demand accesses
2455system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029090 # miss rate for overall accesses
2456system.cpu1.icache.overall_miss_rate::total 0.029090 # miss rate for overall accesses
2457system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11340.109730 # average ReadReq miss latency
2458system.cpu1.icache.ReadReq_avg_miss_latency::total 11340.109730 # average ReadReq miss latency
2459system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11340.109730 # average overall miss latency
2460system.cpu1.icache.demand_avg_miss_latency::total 11340.109730 # average overall miss latency
2461system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11340.109730 # average overall miss latency
2462system.cpu1.icache.overall_avg_miss_latency::total 11340.109730 # average overall miss latency
2463system.cpu1.icache.blocked_cycles::no_mshrs 11528745 # number of cycles access was blocked
2464system.cpu1.icache.blocked_cycles::no_targets 835 # number of cycles access was blocked
2465system.cpu1.icache.blocked::no_mshrs 773545 # number of cycles access was blocked
2466system.cpu1.icache.blocked::no_targets 6 # number of cycles access was blocked
2467system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.903781 # average number of cycles each access was blocked
2468system.cpu1.icache.avg_blocked_cycles::no_targets 139.166667 # average number of cycles each access was blocked
2469system.cpu1.icache.writebacks::writebacks 6229961 # number of writebacks
2470system.cpu1.icache.writebacks::total 6229961 # number of writebacks
2471system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 361744 # number of ReadReq MSHR hits
2472system.cpu1.icache.ReadReq_mshr_hits::total 361744 # number of ReadReq MSHR hits
2473system.cpu1.icache.demand_mshr_hits::cpu1.inst 361744 # number of demand (read+write) MSHR hits
2474system.cpu1.icache.demand_mshr_hits::total 361744 # number of demand (read+write) MSHR hits
2475system.cpu1.icache.overall_mshr_hits::cpu1.inst 361744 # number of overall MSHR hits
2476system.cpu1.icache.overall_mshr_hits::total 361744 # number of overall MSHR hits
2477system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 6230518 # number of ReadReq MSHR misses
2478system.cpu1.icache.ReadReq_mshr_misses::total 6230518 # number of ReadReq MSHR misses
2479system.cpu1.icache.demand_mshr_misses::cpu1.inst 6230518 # number of demand (read+write) MSHR misses
2480system.cpu1.icache.demand_mshr_misses::total 6230518 # number of demand (read+write) MSHR misses
2481system.cpu1.icache.overall_mshr_misses::cpu1.inst 6230518 # number of overall MSHR misses
2482system.cpu1.icache.overall_mshr_misses::total 6230518 # number of overall MSHR misses
2483system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
2484system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable
2485system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
2486system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses
2487system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 67349232950 # number of ReadReq MSHR miss cycles
2488system.cpu1.icache.ReadReq_mshr_miss_latency::total 67349232950 # number of ReadReq MSHR miss cycles
2489system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 67349232950 # number of demand (read+write) MSHR miss cycles
2490system.cpu1.icache.demand_mshr_miss_latency::total 67349232950 # number of demand (read+write) MSHR miss cycles
2491system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 67349232950 # number of overall MSHR miss cycles
2492system.cpu1.icache.overall_mshr_miss_latency::total 67349232950 # number of overall MSHR miss cycles
2493system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8957498 # number of ReadReq MSHR uncacheable cycles
2494system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8957498 # number of ReadReq MSHR uncacheable cycles
2495system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8957498 # number of overall MSHR uncacheable cycles
2496system.cpu1.icache.overall_mshr_uncacheable_latency::total 8957498 # number of overall MSHR uncacheable cycles
2497system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027494 # mshr miss rate for ReadReq accesses
2498system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027494 # mshr miss rate for ReadReq accesses
2499system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027494 # mshr miss rate for demand accesses
2500system.cpu1.icache.demand_mshr_miss_rate::total 0.027494 # mshr miss rate for demand accesses
2501system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027494 # mshr miss rate for overall accesses
2502system.cpu1.icache.overall_mshr_miss_rate::total 0.027494 # mshr miss rate for overall accesses
2503system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10809.572005 # average ReadReq mshr miss latency
2504system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10809.572005 # average ReadReq mshr miss latency
2505system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10809.572005 # average overall mshr miss latency
2506system.cpu1.icache.demand_avg_mshr_miss_latency::total 10809.572005 # average overall mshr miss latency
2507system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10809.572005 # average overall mshr miss latency
2508system.cpu1.icache.overall_avg_mshr_miss_latency::total 10809.572005 # average overall mshr miss latency
2509system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133694 # average ReadReq mshr uncacheable latency
2510system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133694 # average ReadReq mshr uncacheable latency
2511system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133694 # average overall mshr uncacheable latency
2512system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133694 # average overall mshr uncacheable latency
2513system.cpu1.l2cache.prefetcher.num_hwpf_issued 8304723 # number of hwpf issued
2514system.cpu1.l2cache.prefetcher.pfIdentified 8311187 # number of prefetch candidates identified
2515system.cpu1.l2cache.prefetcher.pfBufferHit 5839 # number of redundant prefetches already in prefetch queue
2516system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
2517system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2518system.cpu1.l2cache.prefetcher.pfSpanPage 1024317 # number of prefetches not generated due to page crossing
2519system.cpu1.l2cache.tags.replacements 2528309 # number of replacements
2520system.cpu1.l2cache.tags.tagsinuse 13413.609149 # Cycle average of tags in use
2521system.cpu1.l2cache.tags.total_refs 18251408 # Total number of references to valid blocks.
2522system.cpu1.l2cache.tags.sampled_refs 2544361 # Sample count of references to valid blocks.
2523system.cpu1.l2cache.tags.avg_refs 7.173278 # Average number of references to valid blocks.
2524system.cpu1.l2cache.tags.warmup_cycle 9891515003500 # Cycle when the warmup percentage was hit.
2525system.cpu1.l2cache.tags.occ_blocks::writebacks 12660.361458 # Average occupied blocks per requestor
2526system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 61.649049 # Average occupied blocks per requestor
2527system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 73.939309 # Average occupied blocks per requestor
2528system.cpu1.l2cache.tags.occ_blocks::cpu1.data 0.000012 # Average occupied blocks per requestor
2529system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 617.659322 # Average occupied blocks per requestor
2530system.cpu1.l2cache.tags.occ_percent::writebacks 0.772727 # Average percentage of cache occupancy
2531system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003763 # Average percentage of cache occupancy
2532system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004513 # Average percentage of cache occupancy
2533system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.000000 # Average percentage of cache occupancy
2534system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.037699 # Average percentage of cache occupancy
2535system.cpu1.l2cache.tags.occ_percent::total 0.818702 # Average percentage of cache occupancy
2536system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1288 # Occupied blocks per task id
2537system.cpu1.l2cache.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id
2538system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14705 # Occupied blocks per task id
2539system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id
2540system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 259 # Occupied blocks per task id
2541system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 581 # Occupied blocks per task id
2542system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 431 # Occupied blocks per task id
2543system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 38 # Occupied blocks per task id
2544system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id
2545system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id
2546system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
2547system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1409 # Occupied blocks per task id
2548system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5268 # Occupied blocks per task id
2549system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4214 # Occupied blocks per task id
2550system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3711 # Occupied blocks per task id
2551system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078613 # Percentage of cache occupancy per task id
2552system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id
2553system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.897522 # Percentage of cache occupancy per task id
2554system.cpu1.l2cache.tags.tag_accesses 421641447 # Number of tag accesses
2555system.cpu1.l2cache.tags.data_accesses 421641447 # Number of data accesses
2556system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 670573 # number of ReadReq hits
2557system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 201040 # number of ReadReq hits
2558system.cpu1.l2cache.ReadReq_hits::total 871613 # number of ReadReq hits
2559system.cpu1.l2cache.WritebackDirty_hits::writebacks 3790012 # number of WritebackDirty hits
2560system.cpu1.l2cache.WritebackDirty_hits::total 3790012 # number of WritebackDirty hits
2561system.cpu1.l2cache.WritebackClean_hits::writebacks 8479233 # number of WritebackClean hits
2562system.cpu1.l2cache.WritebackClean_hits::total 8479233 # number of WritebackClean hits
2563system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 992 # number of UpgradeReq hits
2564system.cpu1.l2cache.UpgradeReq_hits::total 992 # number of UpgradeReq hits
2565system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 7 # number of SCUpgradeReq hits
2566system.cpu1.l2cache.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits
2567system.cpu1.l2cache.ReadExReq_hits::cpu1.data 953658 # number of ReadExReq hits
2568system.cpu1.l2cache.ReadExReq_hits::total 953658 # number of ReadExReq hits
2569system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5605859 # number of ReadCleanReq hits
2570system.cpu1.l2cache.ReadCleanReq_hits::total 5605859 # number of ReadCleanReq hits
2571system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3317239 # number of ReadSharedReq hits
2572system.cpu1.l2cache.ReadSharedReq_hits::total 3317239 # number of ReadSharedReq hits
2573system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 173754 # number of InvalidateReq hits
2574system.cpu1.l2cache.InvalidateReq_hits::total 173754 # number of InvalidateReq hits
2575system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 670573 # number of demand (read+write) hits
2576system.cpu1.l2cache.demand_hits::cpu1.itb.walker 201040 # number of demand (read+write) hits
2577system.cpu1.l2cache.demand_hits::cpu1.inst 5605859 # number of demand (read+write) hits
2578system.cpu1.l2cache.demand_hits::cpu1.data 4270897 # number of demand (read+write) hits
2579system.cpu1.l2cache.demand_hits::total 10748369 # number of demand (read+write) hits
2580system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 670573 # number of overall hits
2581system.cpu1.l2cache.overall_hits::cpu1.itb.walker 201040 # number of overall hits
2582system.cpu1.l2cache.overall_hits::cpu1.inst 5605859 # number of overall hits
2583system.cpu1.l2cache.overall_hits::cpu1.data 4270897 # number of overall hits
2584system.cpu1.l2cache.overall_hits::total 10748369 # number of overall hits
2585system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 13735 # number of ReadReq misses
2586system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10344 # number of ReadReq misses
2587system.cpu1.l2cache.ReadReq_misses::total 24079 # number of ReadReq misses
2588system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses
2589system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses
2590system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses
2591system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses
2592system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 250358 # number of UpgradeReq misses
2593system.cpu1.l2cache.UpgradeReq_misses::total 250358 # number of UpgradeReq misses
2594system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 202146 # number of SCUpgradeReq misses
2595system.cpu1.l2cache.SCUpgradeReq_misses::total 202146 # number of SCUpgradeReq misses
2596system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses
2597system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
2598system.cpu1.l2cache.ReadExReq_misses::cpu1.data 315483 # number of ReadExReq misses
2599system.cpu1.l2cache.ReadExReq_misses::total 315483 # number of ReadExReq misses
2600system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 624615 # number of ReadCleanReq misses
2601system.cpu1.l2cache.ReadCleanReq_misses::total 624615 # number of ReadCleanReq misses
2602system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1080990 # number of ReadSharedReq misses
2603system.cpu1.l2cache.ReadSharedReq_misses::total 1080990 # number of ReadSharedReq misses
2604system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 289367 # number of InvalidateReq misses
2605system.cpu1.l2cache.InvalidateReq_misses::total 289367 # number of InvalidateReq misses
2606system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 13735 # number of demand (read+write) misses
2607system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10344 # number of demand (read+write) misses
2608system.cpu1.l2cache.demand_misses::cpu1.inst 624615 # number of demand (read+write) misses
2609system.cpu1.l2cache.demand_misses::cpu1.data 1396473 # number of demand (read+write) misses
2610system.cpu1.l2cache.demand_misses::total 2045167 # number of demand (read+write) misses
2611system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 13735 # number of overall misses
2612system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10344 # number of overall misses
2613system.cpu1.l2cache.overall_misses::cpu1.inst 624615 # number of overall misses
2614system.cpu1.l2cache.overall_misses::cpu1.data 1396473 # number of overall misses
2615system.cpu1.l2cache.overall_misses::total 2045167 # number of overall misses
2616system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 769352500 # number of ReadReq miss cycles
2617system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 652492500 # number of ReadReq miss cycles
2618system.cpu1.l2cache.ReadReq_miss_latency::total 1421845000 # number of ReadReq miss cycles
2619system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3726618500 # number of UpgradeReq miss cycles
2620system.cpu1.l2cache.UpgradeReq_miss_latency::total 3726618500 # number of UpgradeReq miss cycles
2621system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 2054743500 # number of SCUpgradeReq miss cycles
2622system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 2054743500 # number of SCUpgradeReq miss cycles
2623system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3377498 # number of SCUpgradeFailReq miss cycles
2624system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3377498 # number of SCUpgradeFailReq miss cycles
2625system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 18580326500 # number of ReadExReq miss cycles
2626system.cpu1.l2cache.ReadExReq_miss_latency::total 18580326500 # number of ReadExReq miss cycles
2627system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24049432000 # number of ReadCleanReq miss cycles
2628system.cpu1.l2cache.ReadCleanReq_miss_latency::total 24049432000 # number of ReadCleanReq miss cycles
2629system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 47157033477 # number of ReadSharedReq miss cycles
2630system.cpu1.l2cache.ReadSharedReq_miss_latency::total 47157033477 # number of ReadSharedReq miss cycles
2631system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 475628500 # number of InvalidateReq miss cycles
2632system.cpu1.l2cache.InvalidateReq_miss_latency::total 475628500 # number of InvalidateReq miss cycles
2633system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 769352500 # number of demand (read+write) miss cycles
2634system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 652492500 # number of demand (read+write) miss cycles
2635system.cpu1.l2cache.demand_miss_latency::cpu1.inst 24049432000 # number of demand (read+write) miss cycles
2636system.cpu1.l2cache.demand_miss_latency::cpu1.data 65737359977 # number of demand (read+write) miss cycles
2637system.cpu1.l2cache.demand_miss_latency::total 91208636977 # number of demand (read+write) miss cycles
2638system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 769352500 # number of overall miss cycles
2639system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 652492500 # number of overall miss cycles
2640system.cpu1.l2cache.overall_miss_latency::cpu1.inst 24049432000 # number of overall miss cycles
2641system.cpu1.l2cache.overall_miss_latency::cpu1.data 65737359977 # number of overall miss cycles
2642system.cpu1.l2cache.overall_miss_latency::total 91208636977 # number of overall miss cycles
2643system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 684308 # number of ReadReq accesses(hits+misses)
2644system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 211384 # number of ReadReq accesses(hits+misses)
2645system.cpu1.l2cache.ReadReq_accesses::total 895692 # number of ReadReq accesses(hits+misses)
2646system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3790013 # number of WritebackDirty accesses(hits+misses)
2647system.cpu1.l2cache.WritebackDirty_accesses::total 3790013 # number of WritebackDirty accesses(hits+misses)
2648system.cpu1.l2cache.WritebackClean_accesses::writebacks 8479234 # number of WritebackClean accesses(hits+misses)
2649system.cpu1.l2cache.WritebackClean_accesses::total 8479234 # number of WritebackClean accesses(hits+misses)
2650system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 251350 # number of UpgradeReq accesses(hits+misses)
2651system.cpu1.l2cache.UpgradeReq_accesses::total 251350 # number of UpgradeReq accesses(hits+misses)
2652system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 202153 # number of SCUpgradeReq accesses(hits+misses)
2653system.cpu1.l2cache.SCUpgradeReq_accesses::total 202153 # number of SCUpgradeReq accesses(hits+misses)
2654system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses)
2655system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses)
2656system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1269141 # number of ReadExReq accesses(hits+misses)
2657system.cpu1.l2cache.ReadExReq_accesses::total 1269141 # number of ReadExReq accesses(hits+misses)
2658system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 6230474 # number of ReadCleanReq accesses(hits+misses)
2659system.cpu1.l2cache.ReadCleanReq_accesses::total 6230474 # number of ReadCleanReq accesses(hits+misses)
2660system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4398229 # number of ReadSharedReq accesses(hits+misses)
2661system.cpu1.l2cache.ReadSharedReq_accesses::total 4398229 # number of ReadSharedReq accesses(hits+misses)
2662system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 463121 # number of InvalidateReq accesses(hits+misses)
2663system.cpu1.l2cache.InvalidateReq_accesses::total 463121 # number of InvalidateReq accesses(hits+misses)
2664system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 684308 # number of demand (read+write) accesses
2665system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 211384 # number of demand (read+write) accesses
2666system.cpu1.l2cache.demand_accesses::cpu1.inst 6230474 # number of demand (read+write) accesses
2667system.cpu1.l2cache.demand_accesses::cpu1.data 5667370 # number of demand (read+write) accesses
2668system.cpu1.l2cache.demand_accesses::total 12793536 # number of demand (read+write) accesses
2669system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 684308 # number of overall (read+write) accesses
2670system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 211384 # number of overall (read+write) accesses
2671system.cpu1.l2cache.overall_accesses::cpu1.inst 6230474 # number of overall (read+write) accesses
2672system.cpu1.l2cache.overall_accesses::cpu1.data 5667370 # number of overall (read+write) accesses
2673system.cpu1.l2cache.overall_accesses::total 12793536 # number of overall (read+write) accesses
2674system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020071 # miss rate for ReadReq accesses
2675system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048935 # miss rate for ReadReq accesses
2676system.cpu1.l2cache.ReadReq_miss_rate::total 0.026883 # miss rate for ReadReq accesses
2677system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses
2678system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses
2679system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses
2680system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses
2681system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.996053 # miss rate for UpgradeReq accesses
2682system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.996053 # miss rate for UpgradeReq accesses
2683system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999965 # miss rate for SCUpgradeReq accesses
2684system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999965 # miss rate for SCUpgradeReq accesses
2685system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2686system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2687system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.248580 # miss rate for ReadExReq accesses
2688system.cpu1.l2cache.ReadExReq_miss_rate::total 0.248580 # miss rate for ReadExReq accesses
2689system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.100252 # miss rate for ReadCleanReq accesses
2690system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.100252 # miss rate for ReadCleanReq accesses
2691system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.245778 # miss rate for ReadSharedReq accesses
2692system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.245778 # miss rate for ReadSharedReq accesses
2693system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.624819 # miss rate for InvalidateReq accesses
2694system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.624819 # miss rate for InvalidateReq accesses
2695system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020071 # miss rate for demand accesses
2696system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048935 # miss rate for demand accesses
2697system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.100252 # miss rate for demand accesses
2698system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.246406 # miss rate for demand accesses
2699system.cpu1.l2cache.demand_miss_rate::total 0.159859 # miss rate for demand accesses
2700system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020071 # miss rate for overall accesses
2701system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048935 # miss rate for overall accesses
2702system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.100252 # miss rate for overall accesses
2703system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.246406 # miss rate for overall accesses
2704system.cpu1.l2cache.overall_miss_rate::total 0.159859 # miss rate for overall accesses
2705system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 56014.015289 # average ReadReq miss latency
2706system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 63079.321346 # average ReadReq miss latency
2707system.cpu1.l2cache.ReadReq_avg_miss_latency::total 59049.171477 # average ReadReq miss latency
2708system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14885.158453 # average UpgradeReq miss latency
2709system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14885.158453 # average UpgradeReq miss latency
2710system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 10164.650797 # average SCUpgradeReq miss latency
2711system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 10164.650797 # average SCUpgradeReq miss latency
2712system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1125832.666667 # average SCUpgradeFailReq miss latency
2713system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1125832.666667 # average SCUpgradeFailReq miss latency
2714system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 58894.858043 # average ReadExReq miss latency
2715system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 58894.858043 # average ReadExReq miss latency
2716system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38502.808930 # average ReadCleanReq miss latency
2717system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38502.808930 # average ReadCleanReq miss latency
2718system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 43623.931282 # average ReadSharedReq miss latency
2719system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 43623.931282 # average ReadSharedReq miss latency
2720system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1643.686046 # average InvalidateReq miss latency
2721system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1643.686046 # average InvalidateReq miss latency
2722system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 56014.015289 # average overall miss latency
2723system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 63079.321346 # average overall miss latency
2724system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38502.808930 # average overall miss latency
2725system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 47073.849603 # average overall miss latency
2726system.cpu1.l2cache.demand_avg_miss_latency::total 44597.158558 # average overall miss latency
2727system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 56014.015289 # average overall miss latency
2728system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 63079.321346 # average overall miss latency
2729system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38502.808930 # average overall miss latency
2730system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 47073.849603 # average overall miss latency
2731system.cpu1.l2cache.overall_avg_miss_latency::total 44597.158558 # average overall miss latency
2732system.cpu1.l2cache.blocked_cycles::no_mshrs 1476 # number of cycles access was blocked
2733system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2734system.cpu1.l2cache.blocked::no_mshrs 14 # number of cycles access was blocked
2735system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2736system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 105.428571 # average number of cycles each access was blocked
2737system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2738system.cpu1.l2cache.unused_prefetches 50570 # number of HardPF blocks evicted w/o reference
2739system.cpu1.l2cache.writebacks::writebacks 1373649 # number of writebacks
2740system.cpu1.l2cache.writebacks::total 1373649 # number of writebacks
2741system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 2 # number of ReadReq MSHR hits
2742system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 9 # number of ReadReq MSHR hits
2743system.cpu1.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
2744system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 59817 # number of ReadExReq MSHR hits
2745system.cpu1.l2cache.ReadExReq_mshr_hits::total 59817 # number of ReadExReq MSHR hits
2746system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 6475 # number of ReadSharedReq MSHR hits
2747system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 6475 # number of ReadSharedReq MSHR hits
2748system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 7 # number of InvalidateReq MSHR hits
2749system.cpu1.l2cache.InvalidateReq_mshr_hits::total 7 # number of InvalidateReq MSHR hits
2750system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 2 # number of demand (read+write) MSHR hits
2751system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 9 # number of demand (read+write) MSHR hits
2752system.cpu1.l2cache.demand_mshr_hits::cpu1.data 66292 # number of demand (read+write) MSHR hits
2753system.cpu1.l2cache.demand_mshr_hits::total 66303 # number of demand (read+write) MSHR hits
2754system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 2 # number of overall MSHR hits
2755system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 9 # number of overall MSHR hits
2756system.cpu1.l2cache.overall_mshr_hits::cpu1.data 66292 # number of overall MSHR hits
2757system.cpu1.l2cache.overall_mshr_hits::total 66303 # number of overall MSHR hits
2758system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 13733 # number of ReadReq MSHR misses
2759system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10335 # number of ReadReq MSHR misses
2760system.cpu1.l2cache.ReadReq_mshr_misses::total 24068 # number of ReadReq MSHR misses
2761system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses
2762system.cpu1.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses
2763system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses
2764system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses
2765system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 868323 # number of HardPFReq MSHR misses
2766system.cpu1.l2cache.HardPFReq_mshr_misses::total 868323 # number of HardPFReq MSHR misses
2767system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 250358 # number of UpgradeReq MSHR misses
2768system.cpu1.l2cache.UpgradeReq_mshr_misses::total 250358 # number of UpgradeReq MSHR misses
2769system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 202146 # number of SCUpgradeReq MSHR misses
2770system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 202146 # number of SCUpgradeReq MSHR misses
2771system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses
2772system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses
2773system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 255666 # number of ReadExReq MSHR misses
2774system.cpu1.l2cache.ReadExReq_mshr_misses::total 255666 # number of ReadExReq MSHR misses
2775system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 624615 # number of ReadCleanReq MSHR misses
2776system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 624615 # number of ReadCleanReq MSHR misses
2777system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 1074515 # number of ReadSharedReq MSHR misses
2778system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 1074515 # number of ReadSharedReq MSHR misses
2779system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 289360 # number of InvalidateReq MSHR misses
2780system.cpu1.l2cache.InvalidateReq_mshr_misses::total 289360 # number of InvalidateReq MSHR misses
2781system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 13733 # number of demand (read+write) MSHR misses
2782system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10335 # number of demand (read+write) MSHR misses
2783system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 624615 # number of demand (read+write) MSHR misses
2784system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1330181 # number of demand (read+write) MSHR misses
2785system.cpu1.l2cache.demand_mshr_misses::total 1978864 # number of demand (read+write) MSHR misses
2786system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 13733 # number of overall MSHR misses
2787system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10335 # number of overall MSHR misses
2788system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 624615 # number of overall MSHR misses
2789system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1330181 # number of overall MSHR misses
2790system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 868323 # number of overall MSHR misses
2791system.cpu1.l2cache.overall_mshr_misses::total 2847187 # number of overall MSHR misses
2792system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
2793system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 18701 # number of ReadReq MSHR uncacheable
2794system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 18768 # number of ReadReq MSHR uncacheable
2795system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 17029 # number of WriteReq MSHR uncacheable
2796system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 17029 # number of WriteReq MSHR uncacheable
2797system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
2798system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 35730 # number of overall MSHR uncacheable misses
2799system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 35797 # number of overall MSHR uncacheable misses
2800system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 686821000 # number of ReadReq MSHR miss cycles
2801system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 590353500 # number of ReadReq MSHR miss cycles
2802system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1277174500 # number of ReadReq MSHR miss cycles
2803system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 65644901114 # number of HardPFReq MSHR miss cycles
2804system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 65644901114 # number of HardPFReq MSHR miss cycles
2805system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7861561998 # number of UpgradeReq MSHR miss cycles
2806system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7861561998 # number of UpgradeReq MSHR miss cycles
2807system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3988088997 # number of SCUpgradeReq MSHR miss cycles
2808system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3988088997 # number of SCUpgradeReq MSHR miss cycles
2809system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3095498 # number of SCUpgradeFailReq MSHR miss cycles
2810system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3095498 # number of SCUpgradeFailReq MSHR miss cycles
2811system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 13308484000 # number of ReadExReq MSHR miss cycles
2812system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 13308484000 # number of ReadExReq MSHR miss cycles
2813system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20301742000 # number of ReadCleanReq MSHR miss cycles
2814system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20301742000 # number of ReadCleanReq MSHR miss cycles
2815system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 40328599477 # number of ReadSharedReq MSHR miss cycles
2816system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 40328599477 # number of ReadSharedReq MSHR miss cycles
2817system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 15597274497 # number of InvalidateReq MSHR miss cycles
2818system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 15597274497 # number of InvalidateReq MSHR miss cycles
2819system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 686821000 # number of demand (read+write) MSHR miss cycles
2820system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 590353500 # number of demand (read+write) MSHR miss cycles
2821system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20301742000 # number of demand (read+write) MSHR miss cycles
2822system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 53637083477 # number of demand (read+write) MSHR miss cycles
2823system.cpu1.l2cache.demand_mshr_miss_latency::total 75215999977 # number of demand (read+write) MSHR miss cycles
2824system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 686821000 # number of overall MSHR miss cycles
2825system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 590353500 # number of overall MSHR miss cycles
2826system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20301742000 # number of overall MSHR miss cycles
2827system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 53637083477 # number of overall MSHR miss cycles
2828system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 65644901114 # number of overall MSHR miss cycles
2829system.cpu1.l2cache.overall_mshr_miss_latency::total 140860901091 # number of overall MSHR miss cycles
2830system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8454000 # number of ReadReq MSHR uncacheable cycles
2831system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2888554500 # number of ReadReq MSHR uncacheable cycles
2832system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2897008500 # number of ReadReq MSHR uncacheable cycles
2833system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8454000 # number of overall MSHR uncacheable cycles
2834system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2888554500 # number of overall MSHR uncacheable cycles
2835system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2897008500 # number of overall MSHR uncacheable cycles
2836system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020068 # mshr miss rate for ReadReq accesses
2837system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048892 # mshr miss rate for ReadReq accesses
2838system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.026871 # mshr miss rate for ReadReq accesses
2839system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses
2840system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses
2841system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
2842system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
2843system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2844system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2845system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996053 # mshr miss rate for UpgradeReq accesses
2846system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996053 # mshr miss rate for UpgradeReq accesses
2847system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999965 # mshr miss rate for SCUpgradeReq accesses
2848system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999965 # mshr miss rate for SCUpgradeReq accesses
2849system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2850system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2851system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.201448 # mshr miss rate for ReadExReq accesses
2852system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.201448 # mshr miss rate for ReadExReq accesses
2853system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.100252 # mshr miss rate for ReadCleanReq accesses
2854system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.100252 # mshr miss rate for ReadCleanReq accesses
2855system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.244306 # mshr miss rate for ReadSharedReq accesses
2856system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.244306 # mshr miss rate for ReadSharedReq accesses
2857system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.624804 # mshr miss rate for InvalidateReq accesses
2858system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.624804 # mshr miss rate for InvalidateReq accesses
2859system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020068 # mshr miss rate for demand accesses
2860system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048892 # mshr miss rate for demand accesses
2861system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.100252 # mshr miss rate for demand accesses
2862system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.234709 # mshr miss rate for demand accesses
2863system.cpu1.l2cache.demand_mshr_miss_rate::total 0.154677 # mshr miss rate for demand accesses
2864system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020068 # mshr miss rate for overall accesses
2865system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048892 # mshr miss rate for overall accesses
2866system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.100252 # mshr miss rate for overall accesses
2867system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.234709 # mshr miss rate for overall accesses
2868system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2869system.cpu1.l2cache.overall_mshr_miss_rate::total 0.222549 # mshr miss rate for overall accesses
2870system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 50012.451759 # average ReadReq mshr miss latency
2871system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 57121.770682 # average ReadReq mshr miss latency
2872system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 53065.252618 # average ReadReq mshr miss latency
2873system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 75599.634138 # average HardPFReq mshr miss latency
2874system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 75599.634138 # average HardPFReq mshr miss latency
2875system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31401.281357 # average UpgradeReq mshr miss latency
2876system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31401.281357 # average UpgradeReq mshr miss latency
2877system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19728.755439 # average SCUpgradeReq mshr miss latency
2878system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19728.755439 # average SCUpgradeReq mshr miss latency
2879system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1031832.666667 # average SCUpgradeFailReq mshr miss latency
2880system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1031832.666667 # average SCUpgradeFailReq mshr miss latency
2881system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 52054.180063 # average ReadExReq mshr miss latency
2882system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 52054.180063 # average ReadExReq mshr miss latency
2883system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32502.808930 # average ReadCleanReq mshr miss latency
2884system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32502.808930 # average ReadCleanReq mshr miss latency
2885system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 37531.909259 # average ReadSharedReq mshr miss latency
2886system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 37531.909259 # average ReadSharedReq mshr miss latency
2887system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 53902.662763 # average InvalidateReq mshr miss latency
2888system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 53902.662763 # average InvalidateReq mshr miss latency
2889system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 50012.451759 # average overall mshr miss latency
2890system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 57121.770682 # average overall mshr miss latency
2891system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32502.808930 # average overall mshr miss latency
2892system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 40323.146607 # average overall mshr miss latency
2893system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 38009.686354 # average overall mshr miss latency
2894system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 50012.451759 # average overall mshr miss latency
2895system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 57121.770682 # average overall mshr miss latency
2896system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32502.808930 # average overall mshr miss latency
2897system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 40323.146607 # average overall mshr miss latency
2898system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 75599.634138 # average overall mshr miss latency
2899system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 49473.708995 # average overall mshr miss latency
2900system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 126179.104478 # average ReadReq mshr uncacheable latency
2901system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154459.895193 # average ReadReq mshr uncacheable latency
2902system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 154358.935422 # average ReadReq mshr uncacheable latency
2903system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 126179.104478 # average overall mshr uncacheable latency
2904system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 80843.954660 # average overall mshr uncacheable latency
2905system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 80928.806883 # average overall mshr uncacheable latency
2906system.cpu1.toL2Bus.snoop_filter.tot_requests 25472686 # Total number of requests made to the snoop filter.
2907system.cpu1.toL2Bus.snoop_filter.hit_single_requests 13111869 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2908system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1712 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2909system.cpu1.toL2Bus.snoop_filter.tot_snoops 2149417 # Total number of snoops made to the snoop filter.
2910system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2149008 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2911system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 409 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2912system.cpu1.toL2Bus.trans_dist::ReadReq 1009964 # Transaction distribution
2913system.cpu1.toL2Bus.trans_dist::ReadResp 11730214 # Transaction distribution
2914system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution
2915system.cpu1.toL2Bus.trans_dist::WriteReq 17029 # Transaction distribution
2916system.cpu1.toL2Bus.trans_dist::WriteResp 17029 # Transaction distribution
2917system.cpu1.toL2Bus.trans_dist::WritebackDirty 5169290 # Transaction distribution
2918system.cpu1.toL2Bus.trans_dist::WritebackClean 8480923 # Transaction distribution
2919system.cpu1.toL2Bus.trans_dist::CleanEvict 2927219 # Transaction distribution
2920system.cpu1.toL2Bus.trans_dist::HardPFReq 1103039 # Transaction distribution
2921system.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution
2922system.cpu1.toL2Bus.trans_dist::UpgradeReq 459055 # Transaction distribution
2923system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 356155 # Transaction distribution
2924system.cpu1.toL2Bus.trans_dist::UpgradeResp 515583 # Transaction distribution
2925system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 73 # Transaction distribution
2926system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution
2927system.cpu1.toL2Bus.trans_dist::ReadExReq 1297103 # Transaction distribution
2928system.cpu1.toL2Bus.trans_dist::ReadExResp 1275135 # Transaction distribution
2929system.cpu1.toL2Bus.trans_dist::ReadCleanReq 6230518 # Transaction distribution
2930system.cpu1.toL2Bus.trans_dist::ReadSharedReq 5372910 # Transaction distribution
2931system.cpu1.toL2Bus.trans_dist::InvalidateReq 516382 # Transaction distribution
2932system.cpu1.toL2Bus.trans_dist::InvalidateResp 463121 # Transaction distribution
2933system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18691087 # Packet count per connected master and slave (bytes)
2934system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 19440124 # Packet count per connected master and slave (bytes)
2935system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 443982 # Packet count per connected master and slave (bytes)
2936system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1442906 # Packet count per connected master and slave (bytes)
2937system.cpu1.toL2Bus.pkt_count::total 40018099 # Packet count per connected master and slave (bytes)
2938system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 797468912 # Cumulative packet size per connected master and slave (bytes)
2939system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 755702222 # Cumulative packet size per connected master and slave (bytes)
2940system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1691072 # Cumulative packet size per connected master and slave (bytes)
2941system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 5474464 # Cumulative packet size per connected master and slave (bytes)
2942system.cpu1.toL2Bus.pkt_size::total 1560336670 # Cumulative packet size per connected master and slave (bytes)
2943system.cpu1.toL2Bus.snoops 7082459 # Total snoops (count)
2944system.cpu1.toL2Bus.snoop_fanout::samples 20668727 # Request fanout histogram
2945system.cpu1.toL2Bus.snoop_fanout::mean 0.122834 # Request fanout histogram
2946system.cpu1.toL2Bus.snoop_fanout::stdev 0.328306 # Request fanout histogram
2947system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2948system.cpu1.toL2Bus.snoop_fanout::0 18130322 87.72% 87.72% # Request fanout histogram
2949system.cpu1.toL2Bus.snoop_fanout::1 2537996 12.28% 100.00% # Request fanout histogram
2950system.cpu1.toL2Bus.snoop_fanout::2 409 0.00% 100.00% # Request fanout histogram
2951system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2952system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2953system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2954system.cpu1.toL2Bus.snoop_fanout::total 20668727 # Request fanout histogram
2955system.cpu1.toL2Bus.reqLayer0.occupancy 25335696459 # Layer occupancy (ticks)
2956system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
2957system.cpu1.toL2Bus.snoopLayer0.occupancy 177629109 # Layer occupancy (ticks)
2958system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2959system.cpu1.toL2Bus.respLayer0.occupancy 9352273561 # Layer occupancy (ticks)
2960system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2961system.cpu1.toL2Bus.respLayer1.occupancy 8995491238 # Layer occupancy (ticks)
2962system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2963system.cpu1.toL2Bus.respLayer2.occupancy 232944299 # Layer occupancy (ticks)
2964system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2965system.cpu1.toL2Bus.respLayer3.occupancy 759270636 # Layer occupancy (ticks)
2966system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2967system.iobus.trans_dist::ReadReq 40305 # Transaction distribution
2968system.iobus.trans_dist::ReadResp 40305 # Transaction distribution
2969system.iobus.trans_dist::WriteReq 136595 # Transaction distribution
2970system.iobus.trans_dist::WriteResp 136595 # Transaction distribution
2971system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47570 # Packet count per connected master and slave (bytes)
2972system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2973system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
2974system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2975system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2976system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2977system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2978system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2979system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2980system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2981system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2982system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
2983system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2984system.iobus.pkt_count_system.bridge.master::total 122504 # Packet count per connected master and slave (bytes)
2985system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231216 # Packet count per connected master and slave (bytes)
2986system.iobus.pkt_count_system.realview.ide.dma::total 231216 # Packet count per connected master and slave (bytes)
2987system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2988system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2989system.iobus.pkt_count::total 353800 # Packet count per connected master and slave (bytes)
2990system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47590 # Cumulative packet size per connected master and slave (bytes)
2991system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2992system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
2993system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2994system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2995system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2996system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2997system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2998system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2999system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
3000system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
3001system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
3002system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
3003system.iobus.pkt_size_system.bridge.master::total 155611 # Cumulative packet size per connected master and slave (bytes)
3004system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338880 # Cumulative packet size per connected master and slave (bytes)
3005system.iobus.pkt_size_system.realview.ide.dma::total 7338880 # Cumulative packet size per connected master and slave (bytes)
3006system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
3007system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
3008system.iobus.pkt_size::total 7496577 # Cumulative packet size per connected master and slave (bytes)
3009system.iobus.reqLayer0.occupancy 36858001 # Layer occupancy (ticks)
3010system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
3011system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
3012system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
3013system.iobus.reqLayer2.occupancy 326000 # Layer occupancy (ticks)
3014system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
3015system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks)
3016system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
3017system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks)
3018system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
3019system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks)
3020system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
3021system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
3022system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
3023system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks)
3024system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
3025system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks)
3026system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
3027system.iobus.reqLayer16.occupancy 13500 # Layer occupancy (ticks)
3028system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
3029system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks)
3030system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
3031system.iobus.reqLayer23.occupancy 24204504 # Layer occupancy (ticks)
3032system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
3033system.iobus.reqLayer24.occupancy 36391000 # Layer occupancy (ticks)
3034system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
3035system.iobus.reqLayer25.occupancy 567248472 # Layer occupancy (ticks)
3036system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
3037system.iobus.respLayer0.occupancy 92640000 # Layer occupancy (ticks)
3038system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
3039system.iobus.respLayer3.occupancy 147912000 # Layer occupancy (ticks)
3040system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
3041system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
3042system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
3043system.iocache.tags.replacements 115604 # number of replacements
3044system.iocache.tags.tagsinuse 11.311799 # Cycle average of tags in use
3045system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
3046system.iocache.tags.sampled_refs 115620 # Sample count of references to valid blocks.
3047system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
3048system.iocache.tags.warmup_cycle 9121271629000 # Cycle when the warmup percentage was hit.
3049system.iocache.tags.occ_blocks::realview.ethernet 7.400215 # Average occupied blocks per requestor
3050system.iocache.tags.occ_blocks::realview.ide 3.911583 # Average occupied blocks per requestor
3051system.iocache.tags.occ_percent::realview.ethernet 0.462513 # Average percentage of cache occupancy
3052system.iocache.tags.occ_percent::realview.ide 0.244474 # Average percentage of cache occupancy
3053system.iocache.tags.occ_percent::total 0.706987 # Average percentage of cache occupancy
3054system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
3055system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
3056system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
3057system.iocache.tags.tag_accesses 1040829 # Number of tag accesses
3058system.iocache.tags.data_accesses 1040829 # Number of data accesses
3059system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
3060system.iocache.ReadReq_misses::realview.ide 8880 # number of ReadReq misses
3061system.iocache.ReadReq_misses::total 8917 # number of ReadReq misses
3062system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
3063system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
3064system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
3065system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
3066system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
3067system.iocache.demand_misses::realview.ide 115608 # number of demand (read+write) misses
3068system.iocache.demand_misses::total 115648 # number of demand (read+write) misses
3069system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
3070system.iocache.overall_misses::realview.ide 115608 # number of overall misses
3071system.iocache.overall_misses::total 115648 # number of overall misses
3072system.iocache.ReadReq_miss_latency::realview.ethernet 5214500 # number of ReadReq miss cycles
3073system.iocache.ReadReq_miss_latency::realview.ide 1674617085 # number of ReadReq miss cycles
3074system.iocache.ReadReq_miss_latency::total 1679831585 # number of ReadReq miss cycles
3075system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
3076system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
3077system.iocache.WriteLineReq_miss_latency::realview.ide 13548349887 # number of WriteLineReq miss cycles
3078system.iocache.WriteLineReq_miss_latency::total 13548349887 # number of WriteLineReq miss cycles
3079system.iocache.demand_miss_latency::realview.ethernet 5583500 # number of demand (read+write) miss cycles
3080system.iocache.demand_miss_latency::realview.ide 15222966972 # number of demand (read+write) miss cycles
3081system.iocache.demand_miss_latency::total 15228550472 # number of demand (read+write) miss cycles
3082system.iocache.overall_miss_latency::realview.ethernet 5583500 # number of overall miss cycles
3083system.iocache.overall_miss_latency::realview.ide 15222966972 # number of overall miss cycles
3084system.iocache.overall_miss_latency::total 15228550472 # number of overall miss cycles
3085system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
3086system.iocache.ReadReq_accesses::realview.ide 8880 # number of ReadReq accesses(hits+misses)
3087system.iocache.ReadReq_accesses::total 8917 # number of ReadReq accesses(hits+misses)
3088system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
3089system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
3090system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
3091system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
3092system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
3093system.iocache.demand_accesses::realview.ide 115608 # number of demand (read+write) accesses
3094system.iocache.demand_accesses::total 115648 # number of demand (read+write) accesses
3095system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
3096system.iocache.overall_accesses::realview.ide 115608 # number of overall (read+write) accesses
3097system.iocache.overall_accesses::total 115648 # number of overall (read+write) accesses
3098system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
3099system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
3100system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
3101system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
3102system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
3103system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
3104system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
3105system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
3106system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
3107system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
3108system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
3109system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
3110system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
3111system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140932.432432 # average ReadReq miss latency
3112system.iocache.ReadReq_avg_miss_latency::realview.ide 188583.005068 # average ReadReq miss latency
3113system.iocache.ReadReq_avg_miss_latency::total 188385.284849 # average ReadReq miss latency
3114system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
3115system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
3116system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126942.788087 # average WriteLineReq miss latency
3117system.iocache.WriteLineReq_avg_miss_latency::total 126942.788087 # average WriteLineReq miss latency
3118system.iocache.demand_avg_miss_latency::realview.ethernet 139587.500000 # average overall miss latency
3119system.iocache.demand_avg_miss_latency::realview.ide 131677.452875 # average overall miss latency
3120system.iocache.demand_avg_miss_latency::total 131680.188780 # average overall miss latency
3121system.iocache.overall_avg_miss_latency::realview.ethernet 139587.500000 # average overall miss latency
3122system.iocache.overall_avg_miss_latency::realview.ide 131677.452875 # average overall miss latency
3123system.iocache.overall_avg_miss_latency::total 131680.188780 # average overall miss latency
3124system.iocache.blocked_cycles::no_mshrs 33801 # number of cycles access was blocked
3125system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
3126system.iocache.blocked::no_mshrs 3396 # number of cycles access was blocked
3127system.iocache.blocked::no_targets 0 # number of cycles access was blocked
3128system.iocache.avg_blocked_cycles::no_mshrs 9.953180 # average number of cycles each access was blocked
3129system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3130system.iocache.writebacks::writebacks 106694 # number of writebacks
3131system.iocache.writebacks::total 106694 # number of writebacks
3132system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
3133system.iocache.ReadReq_mshr_misses::realview.ide 8880 # number of ReadReq MSHR misses
3134system.iocache.ReadReq_mshr_misses::total 8917 # number of ReadReq MSHR misses
3135system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
3136system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
3137system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
3138system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
3139system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
3140system.iocache.demand_mshr_misses::realview.ide 115608 # number of demand (read+write) MSHR misses
3141system.iocache.demand_mshr_misses::total 115648 # number of demand (read+write) MSHR misses
3142system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
3143system.iocache.overall_mshr_misses::realview.ide 115608 # number of overall MSHR misses
3144system.iocache.overall_mshr_misses::total 115648 # number of overall MSHR misses
3145system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3364500 # number of ReadReq MSHR miss cycles
3146system.iocache.ReadReq_mshr_miss_latency::realview.ide 1230617085 # number of ReadReq MSHR miss cycles
3147system.iocache.ReadReq_mshr_miss_latency::total 1233981585 # number of ReadReq MSHR miss cycles
3148system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
3149system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
3150system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8205400767 # number of WriteLineReq MSHR miss cycles
3151system.iocache.WriteLineReq_mshr_miss_latency::total 8205400767 # number of WriteLineReq MSHR miss cycles
3152system.iocache.demand_mshr_miss_latency::realview.ethernet 3583500 # number of demand (read+write) MSHR miss cycles
3153system.iocache.demand_mshr_miss_latency::realview.ide 9436017852 # number of demand (read+write) MSHR miss cycles
3154system.iocache.demand_mshr_miss_latency::total 9439601352 # number of demand (read+write) MSHR miss cycles
3155system.iocache.overall_mshr_miss_latency::realview.ethernet 3583500 # number of overall MSHR miss cycles
3156system.iocache.overall_mshr_miss_latency::realview.ide 9436017852 # number of overall MSHR miss cycles
3157system.iocache.overall_mshr_miss_latency::total 9439601352 # number of overall MSHR miss cycles
3158system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
3159system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
3160system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
3161system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
3162system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
3163system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
3164system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
3165system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
3166system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
3167system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
3168system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
3169system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
3170system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
3171system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90932.432432 # average ReadReq mshr miss latency
3172system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138583.005068 # average ReadReq mshr miss latency
3173system.iocache.ReadReq_avg_mshr_miss_latency::total 138385.284849 # average ReadReq mshr miss latency
3174system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
3175system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
3176system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76881.425371 # average WriteLineReq mshr miss latency
3177system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76881.425371 # average WriteLineReq mshr miss latency
3178system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89587.500000 # average overall mshr miss latency
3179system.iocache.demand_avg_mshr_miss_latency::realview.ide 81620.803508 # average overall mshr miss latency
3180system.iocache.demand_avg_mshr_miss_latency::total 81623.559007 # average overall mshr miss latency
3181system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89587.500000 # average overall mshr miss latency
3182system.iocache.overall_avg_mshr_miss_latency::realview.ide 81620.803508 # average overall mshr miss latency
3183system.iocache.overall_avg_mshr_miss_latency::total 81623.559007 # average overall mshr miss latency
3184system.l2c.tags.replacements 1658646 # number of replacements
3185system.l2c.tags.tagsinuse 63614.355421 # Cycle average of tags in use
3186system.l2c.tags.total_refs 6503693 # Total number of references to valid blocks.
3187system.l2c.tags.sampled_refs 1717473 # Sample count of references to valid blocks.
3188system.l2c.tags.avg_refs 3.786780 # Average number of references to valid blocks.
3189system.l2c.tags.warmup_cycle 4906135000 # Cycle when the warmup percentage was hit.
3190system.l2c.tags.occ_blocks::writebacks 21778.868920 # Average occupied blocks per requestor
3191system.l2c.tags.occ_blocks::cpu0.dtb.walker 77.174149 # Average occupied blocks per requestor
3192system.l2c.tags.occ_blocks::cpu0.itb.walker 104.892582 # Average occupied blocks per requestor
3193system.l2c.tags.occ_blocks::cpu0.inst 3369.245029 # Average occupied blocks per requestor
3194system.l2c.tags.occ_blocks::cpu0.data 4690.877672 # Average occupied blocks per requestor
3195system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 5127.772728 # Average occupied blocks per requestor
3196system.l2c.tags.occ_blocks::cpu1.dtb.walker 275.118534 # Average occupied blocks per requestor
3197system.l2c.tags.occ_blocks::cpu1.itb.walker 421.752346 # Average occupied blocks per requestor
3198system.l2c.tags.occ_blocks::cpu1.inst 3923.044466 # Average occupied blocks per requestor
3199system.l2c.tags.occ_blocks::cpu1.data 10215.764671 # Average occupied blocks per requestor
3200system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13629.844323 # Average occupied blocks per requestor
3201system.l2c.tags.occ_percent::writebacks 0.332319 # Average percentage of cache occupancy
3202system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001178 # Average percentage of cache occupancy
3203system.l2c.tags.occ_percent::cpu0.itb.walker 0.001601 # Average percentage of cache occupancy
3204system.l2c.tags.occ_percent::cpu0.inst 0.051411 # Average percentage of cache occupancy
3205system.l2c.tags.occ_percent::cpu0.data 0.071577 # Average percentage of cache occupancy
3206system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.078244 # Average percentage of cache occupancy
3207system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004198 # Average percentage of cache occupancy
3208system.l2c.tags.occ_percent::cpu1.itb.walker 0.006435 # Average percentage of cache occupancy
3209system.l2c.tags.occ_percent::cpu1.inst 0.059861 # Average percentage of cache occupancy
3210system.l2c.tags.occ_percent::cpu1.data 0.155880 # Average percentage of cache occupancy
3211system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.207975 # Average percentage of cache occupancy
3212system.l2c.tags.occ_percent::total 0.970678 # Average percentage of cache occupancy
3213system.l2c.tags.occ_task_id_blocks::1022 9349 # Occupied blocks per task id
3214system.l2c.tags.occ_task_id_blocks::1023 246 # Occupied blocks per task id
3215system.l2c.tags.occ_task_id_blocks::1024 49232 # Occupied blocks per task id
3216system.l2c.tags.age_task_id_blocks_1022::0 12 # Occupied blocks per task id
3217system.l2c.tags.age_task_id_blocks_1022::1 39 # Occupied blocks per task id
3218system.l2c.tags.age_task_id_blocks_1022::2 275 # Occupied blocks per task id
3219system.l2c.tags.age_task_id_blocks_1022::3 523 # Occupied blocks per task id
3220system.l2c.tags.age_task_id_blocks_1022::4 8500 # Occupied blocks per task id
3221system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
3222system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
3223system.l2c.tags.age_task_id_blocks_1023::4 244 # Occupied blocks per task id
3224system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
3225system.l2c.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id
3226system.l2c.tags.age_task_id_blocks_1024::2 2922 # Occupied blocks per task id
3227system.l2c.tags.age_task_id_blocks_1024::3 4073 # Occupied blocks per task id
3228system.l2c.tags.age_task_id_blocks_1024::4 41884 # Occupied blocks per task id
3229system.l2c.tags.occ_task_id_percent::1022 0.142654 # Percentage of cache occupancy per task id
3230system.l2c.tags.occ_task_id_percent::1023 0.003754 # Percentage of cache occupancy per task id
3231system.l2c.tags.occ_task_id_percent::1024 0.751221 # Percentage of cache occupancy per task id
3232system.l2c.tags.tag_accesses 83070472 # Number of tag accesses
3233system.l2c.tags.data_accesses 83070472 # Number of data accesses
3234system.l2c.WritebackDirty_hits::writebacks 3045027 # number of WritebackDirty hits
3235system.l2c.WritebackDirty_hits::total 3045027 # number of WritebackDirty hits
3236system.l2c.WritebackClean_hits::writebacks 2 # number of WritebackClean hits
3237system.l2c.WritebackClean_hits::total 2 # number of WritebackClean hits
3238system.l2c.UpgradeReq_hits::cpu0.data 177681 # number of UpgradeReq hits
3239system.l2c.UpgradeReq_hits::cpu1.data 151575 # number of UpgradeReq hits
3240system.l2c.UpgradeReq_hits::total 329256 # number of UpgradeReq hits
3241system.l2c.SCUpgradeReq_hits::cpu0.data 38520 # number of SCUpgradeReq hits
3242system.l2c.SCUpgradeReq_hits::cpu1.data 46161 # number of SCUpgradeReq hits
3243system.l2c.SCUpgradeReq_hits::total 84681 # number of SCUpgradeReq hits
3244system.l2c.ReadExReq_hits::cpu0.data 58316 # number of ReadExReq hits
3245system.l2c.ReadExReq_hits::cpu1.data 56868 # number of ReadExReq hits
3246system.l2c.ReadExReq_hits::total 115184 # number of ReadExReq hits
3247system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6506 # number of ReadSharedReq hits
3248system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4755 # number of ReadSharedReq hits
3249system.l2c.ReadSharedReq_hits::cpu0.inst 505198 # number of ReadSharedReq hits
3250system.l2c.ReadSharedReq_hits::cpu0.data 629843 # number of ReadSharedReq hits
3251system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 303617 # number of ReadSharedReq hits
3252system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6637 # number of ReadSharedReq hits
3253system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4374 # number of ReadSharedReq hits
3254system.l2c.ReadSharedReq_hits::cpu1.inst 567907 # number of ReadSharedReq hits
3255system.l2c.ReadSharedReq_hits::cpu1.data 649267 # number of ReadSharedReq hits
3256system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 304398 # number of ReadSharedReq hits
3257system.l2c.ReadSharedReq_hits::total 2982502 # number of ReadSharedReq hits
3258system.l2c.InvalidateReq_hits::cpu0.data 134777 # number of InvalidateReq hits
3259system.l2c.InvalidateReq_hits::cpu1.data 127780 # number of InvalidateReq hits
3260system.l2c.InvalidateReq_hits::total 262557 # number of InvalidateReq hits
3261system.l2c.demand_hits::cpu0.dtb.walker 6506 # number of demand (read+write) hits
3262system.l2c.demand_hits::cpu0.itb.walker 4755 # number of demand (read+write) hits
3263system.l2c.demand_hits::cpu0.inst 505198 # number of demand (read+write) hits
3264system.l2c.demand_hits::cpu0.data 688159 # number of demand (read+write) hits
3265system.l2c.demand_hits::cpu0.l2cache.prefetcher 303617 # number of demand (read+write) hits
3266system.l2c.demand_hits::cpu1.dtb.walker 6637 # number of demand (read+write) hits
3267system.l2c.demand_hits::cpu1.itb.walker 4374 # number of demand (read+write) hits
3268system.l2c.demand_hits::cpu1.inst 567907 # number of demand (read+write) hits
3269system.l2c.demand_hits::cpu1.data 706135 # number of demand (read+write) hits
3270system.l2c.demand_hits::cpu1.l2cache.prefetcher 304398 # number of demand (read+write) hits
3271system.l2c.demand_hits::total 3097686 # number of demand (read+write) hits
3272system.l2c.overall_hits::cpu0.dtb.walker 6506 # number of overall hits
3273system.l2c.overall_hits::cpu0.itb.walker 4755 # number of overall hits
3274system.l2c.overall_hits::cpu0.inst 505198 # number of overall hits
3275system.l2c.overall_hits::cpu0.data 688159 # number of overall hits
3276system.l2c.overall_hits::cpu0.l2cache.prefetcher 303617 # number of overall hits
3277system.l2c.overall_hits::cpu1.dtb.walker 6637 # number of overall hits
3278system.l2c.overall_hits::cpu1.itb.walker 4374 # number of overall hits
3279system.l2c.overall_hits::cpu1.inst 567907 # number of overall hits
3280system.l2c.overall_hits::cpu1.data 706135 # number of overall hits
3281system.l2c.overall_hits::cpu1.l2cache.prefetcher 304398 # number of overall hits
3282system.l2c.overall_hits::total 3097686 # number of overall hits
3283system.l2c.UpgradeReq_misses::cpu0.data 62380 # number of UpgradeReq misses
3284system.l2c.UpgradeReq_misses::cpu1.data 67853 # number of UpgradeReq misses
3285system.l2c.UpgradeReq_misses::total 130233 # number of UpgradeReq misses
3286system.l2c.SCUpgradeReq_misses::cpu0.data 11700 # number of SCUpgradeReq misses
3287system.l2c.SCUpgradeReq_misses::cpu1.data 13195 # number of SCUpgradeReq misses
3288system.l2c.SCUpgradeReq_misses::total 24895 # number of SCUpgradeReq misses
3289system.l2c.ReadExReq_misses::cpu0.data 82725 # number of ReadExReq misses
3290system.l2c.ReadExReq_misses::cpu1.data 61895 # number of ReadExReq misses
3291system.l2c.ReadExReq_misses::total 144620 # number of ReadExReq misses
3292system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2677 # number of ReadSharedReq misses
3293system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1890 # number of ReadSharedReq misses
3294system.l2c.ReadSharedReq_misses::cpu0.inst 55177 # number of ReadSharedReq misses
3295system.l2c.ReadSharedReq_misses::cpu0.data 140078 # number of ReadSharedReq misses
3296system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 275934 # number of ReadSharedReq misses
3297system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3410 # number of ReadSharedReq misses
3298system.l2c.ReadSharedReq_misses::cpu1.itb.walker 3269 # number of ReadSharedReq misses
3299system.l2c.ReadSharedReq_misses::cpu1.inst 56707 # number of ReadSharedReq misses
3300system.l2c.ReadSharedReq_misses::cpu1.data 154817 # number of ReadSharedReq misses
3301system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 324363 # number of ReadSharedReq misses
3302system.l2c.ReadSharedReq_misses::total 1018322 # number of ReadSharedReq misses
3303system.l2c.InvalidateReq_misses::cpu0.data 452102 # number of InvalidateReq misses
3304system.l2c.InvalidateReq_misses::cpu1.data 148246 # number of InvalidateReq misses
3305system.l2c.InvalidateReq_misses::total 600348 # number of InvalidateReq misses
3306system.l2c.demand_misses::cpu0.dtb.walker 2677 # number of demand (read+write) misses
3307system.l2c.demand_misses::cpu0.itb.walker 1890 # number of demand (read+write) misses
3308system.l2c.demand_misses::cpu0.inst 55177 # number of demand (read+write) misses
3309system.l2c.demand_misses::cpu0.data 222803 # number of demand (read+write) misses
3310system.l2c.demand_misses::cpu0.l2cache.prefetcher 275934 # number of demand (read+write) misses
3311system.l2c.demand_misses::cpu1.dtb.walker 3410 # number of demand (read+write) misses
3312system.l2c.demand_misses::cpu1.itb.walker 3269 # number of demand (read+write) misses
3313system.l2c.demand_misses::cpu1.inst 56707 # number of demand (read+write) misses
3314system.l2c.demand_misses::cpu1.data 216712 # number of demand (read+write) misses
3315system.l2c.demand_misses::cpu1.l2cache.prefetcher 324363 # number of demand (read+write) misses
3316system.l2c.demand_misses::total 1162942 # number of demand (read+write) misses
3317system.l2c.overall_misses::cpu0.dtb.walker 2677 # number of overall misses
3318system.l2c.overall_misses::cpu0.itb.walker 1890 # number of overall misses
3319system.l2c.overall_misses::cpu0.inst 55177 # number of overall misses
3320system.l2c.overall_misses::cpu0.data 222803 # number of overall misses
3321system.l2c.overall_misses::cpu0.l2cache.prefetcher 275934 # number of overall misses
3322system.l2c.overall_misses::cpu1.dtb.walker 3410 # number of overall misses
3323system.l2c.overall_misses::cpu1.itb.walker 3269 # number of overall misses
3324system.l2c.overall_misses::cpu1.inst 56707 # number of overall misses
3325system.l2c.overall_misses::cpu1.data 216712 # number of overall misses
3326system.l2c.overall_misses::cpu1.l2cache.prefetcher 324363 # number of overall misses
3327system.l2c.overall_misses::total 1162942 # number of overall misses
3328system.l2c.UpgradeReq_miss_latency::cpu0.data 1034957000 # number of UpgradeReq miss cycles
3329system.l2c.UpgradeReq_miss_latency::cpu1.data 1157063000 # number of UpgradeReq miss cycles
3330system.l2c.UpgradeReq_miss_latency::total 2192020000 # number of UpgradeReq miss cycles
3331system.l2c.SCUpgradeReq_miss_latency::cpu0.data 174365000 # number of SCUpgradeReq miss cycles
3332system.l2c.SCUpgradeReq_miss_latency::cpu1.data 228989500 # number of SCUpgradeReq miss cycles
3333system.l2c.SCUpgradeReq_miss_latency::total 403354500 # number of SCUpgradeReq miss cycles
3334system.l2c.ReadExReq_miss_latency::cpu0.data 11711225489 # number of ReadExReq miss cycles
3335system.l2c.ReadExReq_miss_latency::cpu1.data 8776678992 # number of ReadExReq miss cycles
3336system.l2c.ReadExReq_miss_latency::total 20487904481 # number of ReadExReq miss cycles
3337system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 384848000 # number of ReadSharedReq miss cycles
3338system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 271512500 # number of ReadSharedReq miss cycles
3339system.l2c.ReadSharedReq_miss_latency::cpu0.inst 7616921000 # number of ReadSharedReq miss cycles
3340system.l2c.ReadSharedReq_miss_latency::cpu0.data 20740892494 # number of ReadSharedReq miss cycles
3341system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 51616446987 # number of ReadSharedReq miss cycles
3342system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 485048000 # number of ReadSharedReq miss cycles
3343system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 453166500 # number of ReadSharedReq miss cycles
3344system.l2c.ReadSharedReq_miss_latency::cpu1.inst 7794605500 # number of ReadSharedReq miss cycles
3345system.l2c.ReadSharedReq_miss_latency::cpu1.data 22700743998 # number of ReadSharedReq miss cycles
3346system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 60057715420 # number of ReadSharedReq miss cycles
3347system.l2c.ReadSharedReq_miss_latency::total 172121900399 # number of ReadSharedReq miss cycles
3348system.l2c.InvalidateReq_miss_latency::cpu0.data 148772000 # number of InvalidateReq miss cycles
3349system.l2c.InvalidateReq_miss_latency::cpu1.data 161516500 # number of InvalidateReq miss cycles
3350system.l2c.InvalidateReq_miss_latency::total 310288500 # number of InvalidateReq miss cycles
3351system.l2c.demand_miss_latency::cpu0.dtb.walker 384848000 # number of demand (read+write) miss cycles
3352system.l2c.demand_miss_latency::cpu0.itb.walker 271512500 # number of demand (read+write) miss cycles
3353system.l2c.demand_miss_latency::cpu0.inst 7616921000 # number of demand (read+write) miss cycles
3354system.l2c.demand_miss_latency::cpu0.data 32452117983 # number of demand (read+write) miss cycles
3355system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 51616446987 # number of demand (read+write) miss cycles
3356system.l2c.demand_miss_latency::cpu1.dtb.walker 485048000 # number of demand (read+write) miss cycles
3357system.l2c.demand_miss_latency::cpu1.itb.walker 453166500 # number of demand (read+write) miss cycles
3358system.l2c.demand_miss_latency::cpu1.inst 7794605500 # number of demand (read+write) miss cycles
3359system.l2c.demand_miss_latency::cpu1.data 31477422990 # number of demand (read+write) miss cycles
3360system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 60057715420 # number of demand (read+write) miss cycles
3361system.l2c.demand_miss_latency::total 192609804880 # number of demand (read+write) miss cycles
3362system.l2c.overall_miss_latency::cpu0.dtb.walker 384848000 # number of overall miss cycles
3363system.l2c.overall_miss_latency::cpu0.itb.walker 271512500 # number of overall miss cycles
3364system.l2c.overall_miss_latency::cpu0.inst 7616921000 # number of overall miss cycles
3365system.l2c.overall_miss_latency::cpu0.data 32452117983 # number of overall miss cycles
3366system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 51616446987 # number of overall miss cycles
3367system.l2c.overall_miss_latency::cpu1.dtb.walker 485048000 # number of overall miss cycles
3368system.l2c.overall_miss_latency::cpu1.itb.walker 453166500 # number of overall miss cycles
3369system.l2c.overall_miss_latency::cpu1.inst 7794605500 # number of overall miss cycles
3370system.l2c.overall_miss_latency::cpu1.data 31477422990 # number of overall miss cycles
3371system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 60057715420 # number of overall miss cycles
3372system.l2c.overall_miss_latency::total 192609804880 # number of overall miss cycles
3373system.l2c.WritebackDirty_accesses::writebacks 3045027 # number of WritebackDirty accesses(hits+misses)
3374system.l2c.WritebackDirty_accesses::total 3045027 # number of WritebackDirty accesses(hits+misses)
3375system.l2c.WritebackClean_accesses::writebacks 2 # number of WritebackClean accesses(hits+misses)
3376system.l2c.WritebackClean_accesses::total 2 # number of WritebackClean accesses(hits+misses)
3377system.l2c.UpgradeReq_accesses::cpu0.data 240061 # number of UpgradeReq accesses(hits+misses)
3378system.l2c.UpgradeReq_accesses::cpu1.data 219428 # number of UpgradeReq accesses(hits+misses)
3379system.l2c.UpgradeReq_accesses::total 459489 # number of UpgradeReq accesses(hits+misses)
3380system.l2c.SCUpgradeReq_accesses::cpu0.data 50220 # number of SCUpgradeReq accesses(hits+misses)
3381system.l2c.SCUpgradeReq_accesses::cpu1.data 59356 # number of SCUpgradeReq accesses(hits+misses)
3382system.l2c.SCUpgradeReq_accesses::total 109576 # number of SCUpgradeReq accesses(hits+misses)
3383system.l2c.ReadExReq_accesses::cpu0.data 141041 # number of ReadExReq accesses(hits+misses)
3384system.l2c.ReadExReq_accesses::cpu1.data 118763 # number of ReadExReq accesses(hits+misses)
3385system.l2c.ReadExReq_accesses::total 259804 # number of ReadExReq accesses(hits+misses)
3386system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 9183 # number of ReadSharedReq accesses(hits+misses)
3387system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6645 # number of ReadSharedReq accesses(hits+misses)
3388system.l2c.ReadSharedReq_accesses::cpu0.inst 560375 # number of ReadSharedReq accesses(hits+misses)
3389system.l2c.ReadSharedReq_accesses::cpu0.data 769921 # number of ReadSharedReq accesses(hits+misses)
3390system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 579551 # number of ReadSharedReq accesses(hits+misses)
3391system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 10047 # number of ReadSharedReq accesses(hits+misses)
3392system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7643 # number of ReadSharedReq accesses(hits+misses)
3393system.l2c.ReadSharedReq_accesses::cpu1.inst 624614 # number of ReadSharedReq accesses(hits+misses)
3394system.l2c.ReadSharedReq_accesses::cpu1.data 804084 # number of ReadSharedReq accesses(hits+misses)
3395system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 628761 # number of ReadSharedReq accesses(hits+misses)
3396system.l2c.ReadSharedReq_accesses::total 4000824 # number of ReadSharedReq accesses(hits+misses)
3397system.l2c.InvalidateReq_accesses::cpu0.data 586879 # number of InvalidateReq accesses(hits+misses)
3398system.l2c.InvalidateReq_accesses::cpu1.data 276026 # number of InvalidateReq accesses(hits+misses)
3399system.l2c.InvalidateReq_accesses::total 862905 # number of InvalidateReq accesses(hits+misses)
3400system.l2c.demand_accesses::cpu0.dtb.walker 9183 # number of demand (read+write) accesses
3401system.l2c.demand_accesses::cpu0.itb.walker 6645 # number of demand (read+write) accesses
3402system.l2c.demand_accesses::cpu0.inst 560375 # number of demand (read+write) accesses
3403system.l2c.demand_accesses::cpu0.data 910962 # number of demand (read+write) accesses
3404system.l2c.demand_accesses::cpu0.l2cache.prefetcher 579551 # number of demand (read+write) accesses
3405system.l2c.demand_accesses::cpu1.dtb.walker 10047 # number of demand (read+write) accesses
3406system.l2c.demand_accesses::cpu1.itb.walker 7643 # number of demand (read+write) accesses
3407system.l2c.demand_accesses::cpu1.inst 624614 # number of demand (read+write) accesses
3408system.l2c.demand_accesses::cpu1.data 922847 # number of demand (read+write) accesses
3409system.l2c.demand_accesses::cpu1.l2cache.prefetcher 628761 # number of demand (read+write) accesses
3410system.l2c.demand_accesses::total 4260628 # number of demand (read+write) accesses
3411system.l2c.overall_accesses::cpu0.dtb.walker 9183 # number of overall (read+write) accesses
3412system.l2c.overall_accesses::cpu0.itb.walker 6645 # number of overall (read+write) accesses
3413system.l2c.overall_accesses::cpu0.inst 560375 # number of overall (read+write) accesses
3414system.l2c.overall_accesses::cpu0.data 910962 # number of overall (read+write) accesses
3415system.l2c.overall_accesses::cpu0.l2cache.prefetcher 579551 # number of overall (read+write) accesses
3416system.l2c.overall_accesses::cpu1.dtb.walker 10047 # number of overall (read+write) accesses
3417system.l2c.overall_accesses::cpu1.itb.walker 7643 # number of overall (read+write) accesses
3418system.l2c.overall_accesses::cpu1.inst 624614 # number of overall (read+write) accesses
3419system.l2c.overall_accesses::cpu1.data 922847 # number of overall (read+write) accesses
3420system.l2c.overall_accesses::cpu1.l2cache.prefetcher 628761 # number of overall (read+write) accesses
3421system.l2c.overall_accesses::total 4260628 # number of overall (read+write) accesses
3422system.l2c.UpgradeReq_miss_rate::cpu0.data 0.259851 # miss rate for UpgradeReq accesses
3423system.l2c.UpgradeReq_miss_rate::cpu1.data 0.309227 # miss rate for UpgradeReq accesses
3424system.l2c.UpgradeReq_miss_rate::total 0.283430 # miss rate for UpgradeReq accesses
3425system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.232975 # miss rate for SCUpgradeReq accesses
3426system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.222303 # miss rate for SCUpgradeReq accesses
3427system.l2c.SCUpgradeReq_miss_rate::total 0.227194 # miss rate for SCUpgradeReq accesses
3428system.l2c.ReadExReq_miss_rate::cpu0.data 0.586532 # miss rate for ReadExReq accesses
3429system.l2c.ReadExReq_miss_rate::cpu1.data 0.521164 # miss rate for ReadExReq accesses
3430system.l2c.ReadExReq_miss_rate::total 0.556650 # miss rate for ReadExReq accesses
3431system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.291517 # miss rate for ReadSharedReq accesses
3432system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.284424 # miss rate for ReadSharedReq accesses
3433system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.098464 # miss rate for ReadSharedReq accesses
3434system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.181938 # miss rate for ReadSharedReq accesses
3435system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.476117 # miss rate for ReadSharedReq accesses
3436system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.339405 # miss rate for ReadSharedReq accesses
3437system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.427712 # miss rate for ReadSharedReq accesses
3438system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.090787 # miss rate for ReadSharedReq accesses
3439system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.192538 # miss rate for ReadSharedReq accesses
3440system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.515876 # miss rate for ReadSharedReq accesses
3441system.l2c.ReadSharedReq_miss_rate::total 0.254528 # miss rate for ReadSharedReq accesses
3442system.l2c.InvalidateReq_miss_rate::cpu0.data 0.770350 # miss rate for InvalidateReq accesses
3443system.l2c.InvalidateReq_miss_rate::cpu1.data 0.537073 # miss rate for InvalidateReq accesses
3444system.l2c.InvalidateReq_miss_rate::total 0.695729 # miss rate for InvalidateReq accesses
3445system.l2c.demand_miss_rate::cpu0.dtb.walker 0.291517 # miss rate for demand accesses
3446system.l2c.demand_miss_rate::cpu0.itb.walker 0.284424 # miss rate for demand accesses
3447system.l2c.demand_miss_rate::cpu0.inst 0.098464 # miss rate for demand accesses
3448system.l2c.demand_miss_rate::cpu0.data 0.244580 # miss rate for demand accesses
3449system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.476117 # miss rate for demand accesses
3450system.l2c.demand_miss_rate::cpu1.dtb.walker 0.339405 # miss rate for demand accesses
3451system.l2c.demand_miss_rate::cpu1.itb.walker 0.427712 # miss rate for demand accesses
3452system.l2c.demand_miss_rate::cpu1.inst 0.090787 # miss rate for demand accesses
3453system.l2c.demand_miss_rate::cpu1.data 0.234830 # miss rate for demand accesses
3454system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.515876 # miss rate for demand accesses
3455system.l2c.demand_miss_rate::total 0.272951 # miss rate for demand accesses
3456system.l2c.overall_miss_rate::cpu0.dtb.walker 0.291517 # miss rate for overall accesses
3457system.l2c.overall_miss_rate::cpu0.itb.walker 0.284424 # miss rate for overall accesses
3458system.l2c.overall_miss_rate::cpu0.inst 0.098464 # miss rate for overall accesses
3459system.l2c.overall_miss_rate::cpu0.data 0.244580 # miss rate for overall accesses
3460system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.476117 # miss rate for overall accesses
3461system.l2c.overall_miss_rate::cpu1.dtb.walker 0.339405 # miss rate for overall accesses
3462system.l2c.overall_miss_rate::cpu1.itb.walker 0.427712 # miss rate for overall accesses
3463system.l2c.overall_miss_rate::cpu1.inst 0.090787 # miss rate for overall accesses
3464system.l2c.overall_miss_rate::cpu1.data 0.234830 # miss rate for overall accesses
3465system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.515876 # miss rate for overall accesses
3466system.l2c.overall_miss_rate::total 0.272951 # miss rate for overall accesses
3467system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16591.167041 # average UpgradeReq miss latency
3468system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17052.495837 # average UpgradeReq miss latency
3469system.l2c.UpgradeReq_avg_miss_latency::total 16831.525036 # average UpgradeReq miss latency
3470system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14902.991453 # average SCUpgradeReq miss latency
3471system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17354.262978 # average SCUpgradeReq miss latency
3472system.l2c.SCUpgradeReq_avg_miss_latency::total 16202.229363 # average SCUpgradeReq miss latency
3473system.l2c.ReadExReq_avg_miss_latency::cpu0.data 141568.153388 # average ReadExReq miss latency
3474system.l2c.ReadExReq_avg_miss_latency::cpu1.data 141799.482866 # average ReadExReq miss latency
3475system.l2c.ReadExReq_avg_miss_latency::total 141667.158630 # average ReadExReq miss latency
3476system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 143760.926410 # average ReadSharedReq miss latency
3477system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 143657.407407 # average ReadSharedReq miss latency
3478system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 138045.218116 # average ReadSharedReq miss latency
3479system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 148066.737775 # average ReadSharedReq miss latency
3480system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 187060.844213 # average ReadSharedReq miss latency
3481system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 142242.815249 # average ReadSharedReq miss latency
3482system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 138625.420618 # average ReadSharedReq miss latency
3483system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137454.026840 # average ReadSharedReq miss latency
3484system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 146629.530336 # average ReadSharedReq miss latency
3485system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 185155.876040 # average ReadSharedReq miss latency
3486system.l2c.ReadSharedReq_avg_miss_latency::total 169025.023911 # average ReadSharedReq miss latency
3487system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 329.067334 # average InvalidateReq miss latency
3488system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 1089.516749 # average InvalidateReq miss latency
3489system.l2c.InvalidateReq_avg_miss_latency::total 516.847728 # average InvalidateReq miss latency
3490system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 143760.926410 # average overall miss latency
3491system.l2c.demand_avg_miss_latency::cpu0.itb.walker 143657.407407 # average overall miss latency
3492system.l2c.demand_avg_miss_latency::cpu0.inst 138045.218116 # average overall miss latency
3493system.l2c.demand_avg_miss_latency::cpu0.data 145653.864549 # average overall miss latency
3494system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 187060.844213 # average overall miss latency
3495system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 142242.815249 # average overall miss latency
3496system.l2c.demand_avg_miss_latency::cpu1.itb.walker 138625.420618 # average overall miss latency
3497system.l2c.demand_avg_miss_latency::cpu1.inst 137454.026840 # average overall miss latency
3498system.l2c.demand_avg_miss_latency::cpu1.data 145250.023026 # average overall miss latency
3499system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 185155.876040 # average overall miss latency
3500system.l2c.demand_avg_miss_latency::total 165622.881347 # average overall miss latency
3501system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 143760.926410 # average overall miss latency
3502system.l2c.overall_avg_miss_latency::cpu0.itb.walker 143657.407407 # average overall miss latency
3503system.l2c.overall_avg_miss_latency::cpu0.inst 138045.218116 # average overall miss latency
3504system.l2c.overall_avg_miss_latency::cpu0.data 145653.864549 # average overall miss latency
3505system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 187060.844213 # average overall miss latency
3506system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 142242.815249 # average overall miss latency
3507system.l2c.overall_avg_miss_latency::cpu1.itb.walker 138625.420618 # average overall miss latency
3508system.l2c.overall_avg_miss_latency::cpu1.inst 137454.026840 # average overall miss latency
3509system.l2c.overall_avg_miss_latency::cpu1.data 145250.023026 # average overall miss latency
3510system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 185155.876040 # average overall miss latency
3511system.l2c.overall_avg_miss_latency::total 165622.881347 # average overall miss latency
3512system.l2c.blocked_cycles::no_mshrs 15923 # number of cycles access was blocked
3513system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
3514system.l2c.blocked::no_mshrs 177 # number of cycles access was blocked
3515system.l2c.blocked::no_targets 0 # number of cycles access was blocked
3516system.l2c.avg_blocked_cycles::no_mshrs 89.960452 # average number of cycles each access was blocked
3517system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3518system.l2c.writebacks::writebacks 1312187 # number of writebacks
3519system.l2c.writebacks::total 1312187 # number of writebacks
3520system.l2c.ReadSharedReq_mshr_hits::cpu0.dtb.walker 3 # number of ReadSharedReq MSHR hits
3521system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 163 # number of ReadSharedReq MSHR hits
3522system.l2c.ReadSharedReq_mshr_hits::cpu0.data 34 # number of ReadSharedReq MSHR hits
3523system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 114 # number of ReadSharedReq MSHR hits
3524system.l2c.ReadSharedReq_mshr_hits::cpu1.data 21 # number of ReadSharedReq MSHR hits
3525system.l2c.ReadSharedReq_mshr_hits::total 335 # number of ReadSharedReq MSHR hits
3526system.l2c.demand_mshr_hits::cpu0.dtb.walker 3 # number of demand (read+write) MSHR hits
3527system.l2c.demand_mshr_hits::cpu0.inst 163 # number of demand (read+write) MSHR hits
3528system.l2c.demand_mshr_hits::cpu0.data 34 # number of demand (read+write) MSHR hits
3529system.l2c.demand_mshr_hits::cpu1.inst 114 # number of demand (read+write) MSHR hits
3530system.l2c.demand_mshr_hits::cpu1.data 21 # number of demand (read+write) MSHR hits
3531system.l2c.demand_mshr_hits::total 335 # number of demand (read+write) MSHR hits
3532system.l2c.overall_mshr_hits::cpu0.dtb.walker 3 # number of overall MSHR hits
3533system.l2c.overall_mshr_hits::cpu0.inst 163 # number of overall MSHR hits
3534system.l2c.overall_mshr_hits::cpu0.data 34 # number of overall MSHR hits
3535system.l2c.overall_mshr_hits::cpu1.inst 114 # number of overall MSHR hits
3536system.l2c.overall_mshr_hits::cpu1.data 21 # number of overall MSHR hits
3537system.l2c.overall_mshr_hits::total 335 # number of overall MSHR hits
3538system.l2c.CleanEvict_mshr_misses::writebacks 62188 # number of CleanEvict MSHR misses
3539system.l2c.CleanEvict_mshr_misses::total 62188 # number of CleanEvict MSHR misses
3540system.l2c.UpgradeReq_mshr_misses::cpu0.data 62380 # number of UpgradeReq MSHR misses
3541system.l2c.UpgradeReq_mshr_misses::cpu1.data 67853 # number of UpgradeReq MSHR misses
3542system.l2c.UpgradeReq_mshr_misses::total 130233 # number of UpgradeReq MSHR misses
3543system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 11700 # number of SCUpgradeReq MSHR misses
3544system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 13195 # number of SCUpgradeReq MSHR misses
3545system.l2c.SCUpgradeReq_mshr_misses::total 24895 # number of SCUpgradeReq MSHR misses
3546system.l2c.ReadExReq_mshr_misses::cpu0.data 82725 # number of ReadExReq MSHR misses
3547system.l2c.ReadExReq_mshr_misses::cpu1.data 61895 # number of ReadExReq MSHR misses
3548system.l2c.ReadExReq_mshr_misses::total 144620 # number of ReadExReq MSHR misses
3549system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2674 # number of ReadSharedReq MSHR misses
3550system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1890 # number of ReadSharedReq MSHR misses
3551system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 55014 # number of ReadSharedReq MSHR misses
3552system.l2c.ReadSharedReq_mshr_misses::cpu0.data 140044 # number of ReadSharedReq MSHR misses
3553system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 275934 # number of ReadSharedReq MSHR misses
3554system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 3410 # number of ReadSharedReq MSHR misses
3555system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 3269 # number of ReadSharedReq MSHR misses
3556system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 56593 # number of ReadSharedReq MSHR misses
3557system.l2c.ReadSharedReq_mshr_misses::cpu1.data 154796 # number of ReadSharedReq MSHR misses
3558system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 324363 # number of ReadSharedReq MSHR misses
3559system.l2c.ReadSharedReq_mshr_misses::total 1017987 # number of ReadSharedReq MSHR misses
3560system.l2c.InvalidateReq_mshr_misses::cpu0.data 452102 # number of InvalidateReq MSHR misses
3561system.l2c.InvalidateReq_mshr_misses::cpu1.data 148246 # number of InvalidateReq MSHR misses
3562system.l2c.InvalidateReq_mshr_misses::total 600348 # number of InvalidateReq MSHR misses
3563system.l2c.demand_mshr_misses::cpu0.dtb.walker 2674 # number of demand (read+write) MSHR misses
3564system.l2c.demand_mshr_misses::cpu0.itb.walker 1890 # number of demand (read+write) MSHR misses
3565system.l2c.demand_mshr_misses::cpu0.inst 55014 # number of demand (read+write) MSHR misses
3566system.l2c.demand_mshr_misses::cpu0.data 222769 # number of demand (read+write) MSHR misses
3567system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 275934 # number of demand (read+write) MSHR misses
3568system.l2c.demand_mshr_misses::cpu1.dtb.walker 3410 # number of demand (read+write) MSHR misses
3569system.l2c.demand_mshr_misses::cpu1.itb.walker 3269 # number of demand (read+write) MSHR misses
3570system.l2c.demand_mshr_misses::cpu1.inst 56593 # number of demand (read+write) MSHR misses
3571system.l2c.demand_mshr_misses::cpu1.data 216691 # number of demand (read+write) MSHR misses
3572system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 324363 # number of demand (read+write) MSHR misses
3573system.l2c.demand_mshr_misses::total 1162607 # number of demand (read+write) MSHR misses
3574system.l2c.overall_mshr_misses::cpu0.dtb.walker 2674 # number of overall MSHR misses
3575system.l2c.overall_mshr_misses::cpu0.itb.walker 1890 # number of overall MSHR misses
3576system.l2c.overall_mshr_misses::cpu0.inst 55014 # number of overall MSHR misses
3577system.l2c.overall_mshr_misses::cpu0.data 222769 # number of overall MSHR misses
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3579system.l2c.overall_mshr_misses::cpu1.dtb.walker 3410 # number of overall MSHR misses
3580system.l2c.overall_mshr_misses::cpu1.itb.walker 3269 # number of overall MSHR misses
3581system.l2c.overall_mshr_misses::cpu1.inst 56593 # number of overall MSHR misses
3582system.l2c.overall_mshr_misses::cpu1.data 216691 # number of overall MSHR misses
3583system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 324363 # number of overall MSHR misses
3584system.l2c.overall_mshr_misses::total 1162607 # number of overall MSHR misses
3585system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
3586system.l2c.ReadReq_mshr_uncacheable::cpu0.data 19706 # number of ReadReq MSHR uncacheable
3587system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
3588system.l2c.ReadReq_mshr_uncacheable::cpu1.data 18699 # number of ReadReq MSHR uncacheable
3589system.l2c.ReadReq_mshr_uncacheable::total 59765 # number of ReadReq MSHR uncacheable
3590system.l2c.WriteReq_mshr_uncacheable::cpu0.data 21266 # number of WriteReq MSHR uncacheable
3591system.l2c.WriteReq_mshr_uncacheable::cpu1.data 17029 # number of WriteReq MSHR uncacheable
3592system.l2c.WriteReq_mshr_uncacheable::total 38295 # number of WriteReq MSHR uncacheable
3593system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
3594system.l2c.overall_mshr_uncacheable_misses::cpu0.data 40972 # number of overall MSHR uncacheable misses
3595system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
3596system.l2c.overall_mshr_uncacheable_misses::cpu1.data 35728 # number of overall MSHR uncacheable misses
3597system.l2c.overall_mshr_uncacheable_misses::total 98060 # number of overall MSHR uncacheable misses
3598system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4409168995 # number of UpgradeReq MSHR miss cycles
3599system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4786348998 # number of UpgradeReq MSHR miss cycles
3600system.l2c.UpgradeReq_mshr_miss_latency::total 9195517993 # number of UpgradeReq MSHR miss cycles
3601system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 862109992 # number of SCUpgradeReq MSHR miss cycles
3602system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 970555497 # number of SCUpgradeReq MSHR miss cycles
3603system.l2c.SCUpgradeReq_mshr_miss_latency::total 1832665489 # number of SCUpgradeReq MSHR miss cycles
3604system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10883415957 # number of ReadExReq MSHR miss cycles
3605system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 8157375512 # number of ReadExReq MSHR miss cycles
3606system.l2c.ReadExReq_mshr_miss_latency::total 19040791469 # number of ReadExReq MSHR miss cycles
3607system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 357690038 # number of ReadSharedReq MSHR miss cycles
3608system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 252601028 # number of ReadSharedReq MSHR miss cycles
3609system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 7044725224 # number of ReadSharedReq MSHR miss cycles
3610system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 19335135004 # number of ReadSharedReq MSHR miss cycles
3611system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 48855278506 # number of ReadSharedReq MSHR miss cycles
3612system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 450944507 # number of ReadSharedReq MSHR miss cycles
3613system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 420472009 # number of ReadSharedReq MSHR miss cycles
3614system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 7214941938 # number of ReadSharedReq MSHR miss cycles
3615system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 21149813267 # number of ReadSharedReq MSHR miss cycles
3616system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 56812837096 # number of ReadSharedReq MSHR miss cycles
3617system.l2c.ReadSharedReq_mshr_miss_latency::total 161894438617 # number of ReadSharedReq MSHR miss cycles
3618system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 31769945999 # number of InvalidateReq MSHR miss cycles
3619system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 10316729000 # number of InvalidateReq MSHR miss cycles
3620system.l2c.InvalidateReq_mshr_miss_latency::total 42086674999 # number of InvalidateReq MSHR miss cycles
3621system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 357690038 # number of demand (read+write) MSHR miss cycles
3622system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 252601028 # number of demand (read+write) MSHR miss cycles
3623system.l2c.demand_mshr_miss_latency::cpu0.inst 7044725224 # number of demand (read+write) MSHR miss cycles
3624system.l2c.demand_mshr_miss_latency::cpu0.data 30218550961 # number of demand (read+write) MSHR miss cycles
3625system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 48855278506 # number of demand (read+write) MSHR miss cycles
3626system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 450944507 # number of demand (read+write) MSHR miss cycles
3627system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 420472009 # number of demand (read+write) MSHR miss cycles
3628system.l2c.demand_mshr_miss_latency::cpu1.inst 7214941938 # number of demand (read+write) MSHR miss cycles
3629system.l2c.demand_mshr_miss_latency::cpu1.data 29307188779 # number of demand (read+write) MSHR miss cycles
3630system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 56812837096 # number of demand (read+write) MSHR miss cycles
3631system.l2c.demand_mshr_miss_latency::total 180935230086 # number of demand (read+write) MSHR miss cycles
3632system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 357690038 # number of overall MSHR miss cycles
3633system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 252601028 # number of overall MSHR miss cycles
3634system.l2c.overall_mshr_miss_latency::cpu0.inst 7044725224 # number of overall MSHR miss cycles
3635system.l2c.overall_mshr_miss_latency::cpu0.data 30218550961 # number of overall MSHR miss cycles
3636system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 48855278506 # number of overall MSHR miss cycles
3637system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 450944507 # number of overall MSHR miss cycles
3638system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 420472009 # number of overall MSHR miss cycles
3639system.l2c.overall_mshr_miss_latency::cpu1.inst 7214941938 # number of overall MSHR miss cycles
3640system.l2c.overall_mshr_miss_latency::cpu1.data 29307188779 # number of overall MSHR miss cycles
3641system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 56812837096 # number of overall MSHR miss cycles
3642system.l2c.overall_mshr_miss_latency::total 180935230086 # number of overall MSHR miss cycles
3643system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2396807500 # number of ReadReq MSHR uncacheable cycles
3644system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3350562534 # number of ReadReq MSHR uncacheable cycles
3645system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7247500 # number of ReadReq MSHR uncacheable cycles
3646system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2551834016 # number of ReadReq MSHR uncacheable cycles
3647system.l2c.ReadReq_mshr_uncacheable_latency::total 8306451550 # number of ReadReq MSHR uncacheable cycles
3648system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2396807500 # number of overall MSHR uncacheable cycles
3649system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3350562534 # number of overall MSHR uncacheable cycles
3650system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7247500 # number of overall MSHR uncacheable cycles
3651system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2551834016 # number of overall MSHR uncacheable cycles
3652system.l2c.overall_mshr_uncacheable_latency::total 8306451550 # number of overall MSHR uncacheable cycles
3653system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3654system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3655system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.259851 # mshr miss rate for UpgradeReq accesses
3656system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.309227 # mshr miss rate for UpgradeReq accesses
3657system.l2c.UpgradeReq_mshr_miss_rate::total 0.283430 # mshr miss rate for UpgradeReq accesses
3658system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.232975 # mshr miss rate for SCUpgradeReq accesses
3659system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.222303 # mshr miss rate for SCUpgradeReq accesses
3660system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.227194 # mshr miss rate for SCUpgradeReq accesses
3661system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.586532 # mshr miss rate for ReadExReq accesses
3662system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.521164 # mshr miss rate for ReadExReq accesses
3663system.l2c.ReadExReq_mshr_miss_rate::total 0.556650 # mshr miss rate for ReadExReq accesses
3664system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.291190 # mshr miss rate for ReadSharedReq accesses
3665system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.284424 # mshr miss rate for ReadSharedReq accesses
3666system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.098174 # mshr miss rate for ReadSharedReq accesses
3667system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.181894 # mshr miss rate for ReadSharedReq accesses
3668system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.476117 # mshr miss rate for ReadSharedReq accesses
3669system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.339405 # mshr miss rate for ReadSharedReq accesses
3670system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.427712 # mshr miss rate for ReadSharedReq accesses
3671system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.090605 # mshr miss rate for ReadSharedReq accesses
3672system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.192512 # mshr miss rate for ReadSharedReq accesses
3673system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.515876 # mshr miss rate for ReadSharedReq accesses
3674system.l2c.ReadSharedReq_mshr_miss_rate::total 0.254444 # mshr miss rate for ReadSharedReq accesses
3675system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.770350 # mshr miss rate for InvalidateReq accesses
3676system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.537073 # mshr miss rate for InvalidateReq accesses
3677system.l2c.InvalidateReq_mshr_miss_rate::total 0.695729 # mshr miss rate for InvalidateReq accesses
3678system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.291190 # mshr miss rate for demand accesses
3679system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.284424 # mshr miss rate for demand accesses
3680system.l2c.demand_mshr_miss_rate::cpu0.inst 0.098174 # mshr miss rate for demand accesses
3681system.l2c.demand_mshr_miss_rate::cpu0.data 0.244543 # mshr miss rate for demand accesses
3682system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.476117 # mshr miss rate for demand accesses
3683system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.339405 # mshr miss rate for demand accesses
3684system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.427712 # mshr miss rate for demand accesses
3685system.l2c.demand_mshr_miss_rate::cpu1.inst 0.090605 # mshr miss rate for demand accesses
3686system.l2c.demand_mshr_miss_rate::cpu1.data 0.234807 # mshr miss rate for demand accesses
3687system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.515876 # mshr miss rate for demand accesses
3688system.l2c.demand_mshr_miss_rate::total 0.272872 # mshr miss rate for demand accesses
3689system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.291190 # mshr miss rate for overall accesses
3690system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.284424 # mshr miss rate for overall accesses
3691system.l2c.overall_mshr_miss_rate::cpu0.inst 0.098174 # mshr miss rate for overall accesses
3692system.l2c.overall_mshr_miss_rate::cpu0.data 0.244543 # mshr miss rate for overall accesses
3693system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.476117 # mshr miss rate for overall accesses
3694system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.339405 # mshr miss rate for overall accesses
3695system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.427712 # mshr miss rate for overall accesses
3696system.l2c.overall_mshr_miss_rate::cpu1.inst 0.090605 # mshr miss rate for overall accesses
3697system.l2c.overall_mshr_miss_rate::cpu1.data 0.234807 # mshr miss rate for overall accesses
3698system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.515876 # mshr miss rate for overall accesses
3699system.l2c.overall_mshr_miss_rate::total 0.272872 # mshr miss rate for overall accesses
3700system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70682.414155 # average UpgradeReq mshr miss latency
3701system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70539.976095 # average UpgradeReq mshr miss latency
3702system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70608.202168 # average UpgradeReq mshr miss latency
3703system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73684.614701 # average SCUpgradeReq mshr miss latency
3704system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73554.793255 # average SCUpgradeReq mshr miss latency
3705system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73615.805945 # average SCUpgradeReq mshr miss latency
3706system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 131561.389628 # average ReadExReq mshr miss latency
3707system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 131793.771904 # average ReadExReq mshr miss latency
3708system.l2c.ReadExReq_avg_mshr_miss_latency::total 131660.845450 # average ReadExReq mshr miss latency
3709system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 133765.908003 # average ReadSharedReq mshr miss latency
3710system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 133651.337566 # average ReadSharedReq mshr miss latency
3711system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 128053.317774 # average ReadSharedReq mshr miss latency
3712system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 138064.715404 # average ReadSharedReq mshr miss latency
3713system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177054.217697 # average ReadSharedReq mshr miss latency
3714system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 132241.790909 # average ReadSharedReq mshr miss latency
3715system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 128624.046803 # average ReadSharedReq mshr miss latency
3716system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127488.239500 # average ReadSharedReq mshr miss latency
3717system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 136630.231188 # average ReadSharedReq mshr miss latency
3718system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175152.027500 # average ReadSharedReq mshr miss latency
3719system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 159033.895931 # average ReadSharedReq mshr miss latency
3720system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70271.633390 # average InvalidateReq mshr miss latency
3721system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69591.955264 # average InvalidateReq mshr miss latency
3722system.l2c.InvalidateReq_avg_mshr_miss_latency::total 70103.798129 # average InvalidateReq mshr miss latency
3723system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 133765.908003 # average overall mshr miss latency
3724system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 133651.337566 # average overall mshr miss latency
3725system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 128053.317774 # average overall mshr miss latency
3726system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135649.713205 # average overall mshr miss latency
3727system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177054.217697 # average overall mshr miss latency
3728system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 132241.790909 # average overall mshr miss latency
3729system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 128624.046803 # average overall mshr miss latency
3730system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127488.239500 # average overall mshr miss latency
3731system.l2c.demand_avg_mshr_miss_latency::cpu1.data 135248.758735 # average overall mshr miss latency
3732system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175152.027500 # average overall mshr miss latency
3733system.l2c.demand_avg_mshr_miss_latency::total 155628.884125 # average overall mshr miss latency
3734system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 133765.908003 # average overall mshr miss latency
3735system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 133651.337566 # average overall mshr miss latency
3736system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 128053.317774 # average overall mshr miss latency
3737system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135649.713205 # average overall mshr miss latency
3738system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177054.217697 # average overall mshr miss latency
3739system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 132241.790909 # average overall mshr miss latency
3740system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 128624.046803 # average overall mshr miss latency
3741system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127488.239500 # average overall mshr miss latency
3742system.l2c.overall_avg_mshr_miss_latency::cpu1.data 135248.758735 # average overall mshr miss latency
3743system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 175152.027500 # average overall mshr miss latency
3744system.l2c.overall_avg_mshr_miss_latency::total 155628.884125 # average overall mshr miss latency
3745system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.166299 # average ReadReq mshr uncacheable latency
3746system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170027.531412 # average ReadReq mshr uncacheable latency
3747system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108171.641791 # average ReadReq mshr uncacheable latency
3748system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136469.009894 # average ReadReq mshr uncacheable latency
3749system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138985.217937 # average ReadReq mshr uncacheable latency
3750system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.166299 # average overall mshr uncacheable latency
3751system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 81776.885043 # average overall mshr uncacheable latency
3752system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108171.641791 # average overall mshr uncacheable latency
3753system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 71423.925661 # average overall mshr uncacheable latency
3754system.l2c.overall_avg_mshr_uncacheable_latency::total 84707.847746 # average overall mshr uncacheable latency
3755system.membus.trans_dist::ReadReq 59765 # Transaction distribution
3756system.membus.trans_dist::ReadResp 1086669 # Transaction distribution
3757system.membus.trans_dist::WriteReq 38295 # Transaction distribution
3758system.membus.trans_dist::WriteResp 38295 # Transaction distribution
3759system.membus.trans_dist::WritebackDirty 1418881 # Transaction distribution
3760system.membus.trans_dist::CleanEvict 277094 # Transaction distribution
3761system.membus.trans_dist::UpgradeReq 441724 # Transaction distribution
3762system.membus.trans_dist::SCUpgradeReq 308123 # Transaction distribution
3763system.membus.trans_dist::UpgradeResp 23 # Transaction distribution
3764system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
3765system.membus.trans_dist::ReadExReq 153866 # Transaction distribution
3766system.membus.trans_dist::ReadExResp 139435 # Transaction distribution
3767system.membus.trans_dist::ReadSharedReq 1026904 # Transaction distribution
3768system.membus.trans_dist::InvalidateReq 703178 # Transaction distribution
3769system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122504 # Packet count per connected master and slave (bytes)
3770system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes)
3771system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25676 # Packet count per connected master and slave (bytes)
3772system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5303073 # Packet count per connected master and slave (bytes)
3773system.membus.pkt_count_system.l2c.mem_side::total 5451329 # Packet count per connected master and slave (bytes)
3774system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237588 # Packet count per connected master and slave (bytes)
3775system.membus.pkt_count_system.iocache.mem_side::total 237588 # Packet count per connected master and slave (bytes)
3776system.membus.pkt_count::total 5688917 # Packet count per connected master and slave (bytes)
3777system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155611 # Cumulative packet size per connected master and slave (bytes)
3778system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes)
3779system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51352 # Cumulative packet size per connected master and slave (bytes)
3780system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 158370176 # Cumulative packet size per connected master and slave (bytes)
3781system.membus.pkt_size_system.l2c.mem_side::total 158577695 # Cumulative packet size per connected master and slave (bytes)
3782system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7233920 # Cumulative packet size per connected master and slave (bytes)
3783system.membus.pkt_size_system.iocache.mem_side::total 7233920 # Cumulative packet size per connected master and slave (bytes)
3784system.membus.pkt_size::total 165811615 # Cumulative packet size per connected master and slave (bytes)
3785system.membus.snoops 603403 # Total snoops (count)
3786system.membus.snoop_fanout::samples 4427877 # Request fanout histogram
3787system.membus.snoop_fanout::mean 1 # Request fanout histogram
3788system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3789system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3790system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3791system.membus.snoop_fanout::1 4427877 100.00% 100.00% # Request fanout histogram
3792system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3793system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3794system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3795system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3796system.membus.snoop_fanout::total 4427877 # Request fanout histogram
3797system.membus.reqLayer0.occupancy 97877995 # Layer occupancy (ticks)
3798system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3799system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks)
3800system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3801system.membus.reqLayer2.occupancy 21789496 # Layer occupancy (ticks)
3802system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3803system.membus.reqLayer5.occupancy 9855054431 # Layer occupancy (ticks)
3804system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3805system.membus.respLayer2.occupancy 6236968511 # Layer occupancy (ticks)
3806system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3807system.membus.respLayer3.occupancy 45519188 # Layer occupancy (ticks)
3808system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3809system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
3810system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
3811system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
3812system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
3813system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
3814system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
3815system.realview.ethernet.txBytes 966 # Bytes Transmitted

--- 37 unchanged lines hidden (view full) ---

3853system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3854system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3855system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3856system.realview.ethernet.droppedPackets 0 # number of packets dropped
3857system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
3858system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
3859system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
3860system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
3861system.toL2Bus.snoop_filter.tot_requests 12681630 # Total number of requests made to the snoop filter.
3862system.toL2Bus.snoop_filter.hit_single_requests 6883923 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3863system.toL2Bus.snoop_filter.hit_multi_requests 2005926 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3864system.toL2Bus.snoop_filter.tot_snoops 170885 # Total number of snoops made to the snoop filter.
3865system.toL2Bus.snoop_filter.hit_single_snoops 155146 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3866system.toL2Bus.snoop_filter.hit_multi_snoops 15739 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3867system.toL2Bus.trans_dist::ReadReq 59767 # Transaction distribution
3868system.toL2Bus.trans_dist::ReadResp 4843433 # Transaction distribution
3869system.toL2Bus.trans_dist::WriteReq 38295 # Transaction distribution
3870system.toL2Bus.trans_dist::WriteResp 38295 # Transaction distribution
3871system.toL2Bus.trans_dist::WritebackDirty 4463947 # Transaction distribution
3872system.toL2Bus.trans_dist::WritebackClean 2 # Transaction distribution
3873system.toL2Bus.trans_dist::CleanEvict 2878269 # Transaction distribution
3874system.toL2Bus.trans_dist::UpgradeReq 761897 # Transaction distribution
3875system.toL2Bus.trans_dist::SCUpgradeReq 392804 # Transaction distribution
3876system.toL2Bus.trans_dist::UpgradeResp 1154700 # Transaction distribution
3877system.toL2Bus.trans_dist::SCUpgradeFailReq 117 # Transaction distribution
3878system.toL2Bus.trans_dist::UpgradeFailResp 117 # Transaction distribution
3879system.toL2Bus.trans_dist::ReadExReq 312867 # Transaction distribution
3880system.toL2Bus.trans_dist::ReadExResp 312867 # Transaction distribution
3881system.toL2Bus.trans_dist::ReadSharedReq 4790902 # Transaction distribution
3882system.toL2Bus.trans_dist::InvalidateReq 969633 # Transaction distribution
3883system.toL2Bus.trans_dist::InvalidateResp 862905 # Transaction distribution
3884system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9568329 # Packet count per connected master and slave (bytes)
3885system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9002574 # Packet count per connected master and slave (bytes)
3886system.toL2Bus.pkt_count::total 18570903 # Packet count per connected master and slave (bytes)
3887system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 239712817 # Cumulative packet size per connected master and slave (bytes)
3888system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 228526446 # Cumulative packet size per connected master and slave (bytes)
3889system.toL2Bus.pkt_size::total 468239263 # Cumulative packet size per connected master and slave (bytes)
3890system.toL2Bus.snoops 3311598 # Total snoops (count)
3891system.toL2Bus.snoop_fanout::samples 9100879 # Request fanout histogram
3892system.toL2Bus.snoop_fanout::mean 0.338787 # Request fanout histogram
3893system.toL2Bus.snoop_fanout::stdev 0.476937 # Request fanout histogram
3894system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3895system.toL2Bus.snoop_fanout::0 6033358 66.29% 66.29% # Request fanout histogram
3896system.toL2Bus.snoop_fanout::1 3051782 33.53% 99.83% # Request fanout histogram
3897system.toL2Bus.snoop_fanout::2 15739 0.17% 100.00% # Request fanout histogram
3898system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3899system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3900system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3901system.toL2Bus.snoop_fanout::total 9100879 # Request fanout histogram
3902system.toL2Bus.reqLayer0.occupancy 9916846796 # Layer occupancy (ticks)
3903system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3904system.toL2Bus.snoopLayer0.occupancy 2612852 # Layer occupancy (ticks)
3905system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3906system.toL2Bus.respLayer0.occupancy 4354241663 # Layer occupancy (ticks)
3907system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3908system.toL2Bus.respLayer1.occupancy 4394264623 # Layer occupancy (ticks)
3909system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3910system.cpu0.kern.inst.arm 0 # number of arm instructions executed
3911system.cpu0.kern.inst.quiesce 4933 # number of quiesce instructions executed
3912system.cpu1.kern.inst.arm 0 # number of arm instructions executed
3913system.cpu1.kern.inst.quiesce 14218 # number of quiesce instructions executed
3914
3915---------- End Simulation Statistics ----------