1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.434893 # Number of seconds simulated
4sim_ticks 47434893411000 # Number of ticks simulated
5final_tick 47434893411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 99639 # Simulator instruction rate (inst/s)
8host_op_rate 117176 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 5152463712 # Simulator tick rate (ticks/s)
10host_mem_usage 784704 # Number of bytes of host memory used
11host_seconds 9206.25 # Real time elapsed on the host
12sim_insts 917301737 # Number of instructions simulated
13sim_ops 1078753903 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 208192 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 203648 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 4658336 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 45847432 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 22095168 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 91328 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 66368 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 2323808 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 12264528 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 10934912 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 422080 # Number of bytes read from this memory
27system.physmem.bytes_read::total 99115800 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 4658336 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 2323808 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 6982144 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 83002560 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
34system.physmem.bytes_written::total 83023144 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 3253 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 3182 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 88739 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 716379 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 345237 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 1427 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.itb.walker 1037 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.inst 36353 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.data 191646 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.l2cache.prefetcher 170858 # Number of read requests responded to by this memory
45system.physmem.num_reads::realview.ide 6595 # Number of read requests responded to by this memory
46system.physmem.num_reads::total 1564706 # Number of read requests responded to by this memory
47system.physmem.num_writes::writebacks 1296915 # Number of write requests responded to by this memory
48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
50system.physmem.num_writes::total 1299489 # Number of write requests responded to by this memory
51system.physmem.bw_read::cpu0.dtb.walker 4389 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.itb.walker 4293 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.inst 98205 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.data 966534 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.l2cache.prefetcher 465800 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.dtb.walker 1925 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.itb.walker 1399 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.inst 48989 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.data 258555 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.l2cache.prefetcher 230525 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::realview.ide 8898 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::total 2089512 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::cpu0.inst 98205 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu1.inst 48989 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::total 147194 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_write::writebacks 1749821 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::total 1750255 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_total::writebacks 1749821 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.dtb.walker 4389 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.itb.walker 4293 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.inst 98205 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.data 966968 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.l2cache.prefetcher 465800 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.dtb.walker 1925 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.itb.walker 1399 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.inst 48989 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.data 258555 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.l2cache.prefetcher 230525 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.ide 8898 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::total 3839767 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.readReqs 1564706 # Number of read requests accepted
84system.physmem.writeReqs 1299489 # Number of write requests accepted
85system.physmem.readBursts 1564706 # Number of DRAM read bursts, including those serviced by the write queue
86system.physmem.writeBursts 1299489 # Number of DRAM write bursts, including those merged in the write queue
87system.physmem.bytesReadDRAM 100111296 # Total number of bytes read from DRAM
88system.physmem.bytesReadWrQ 29888 # Total number of bytes read from write queue
89system.physmem.bytesWritten 83021568 # Total number of bytes written to DRAM
90system.physmem.bytesReadSys 99115800 # Total read bytes from the system interface side
91system.physmem.bytesWrittenSys 83023144 # Total written bytes from the system interface side
92system.physmem.servicedByWrQ 467 # Number of DRAM read bursts serviced by the write queue
93system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
94system.physmem.neitherReadNorWriteReqs 228681 # Number of requests that are neither read nor write
95system.physmem.perBankRdBursts::0 96105 # Per bank write bursts
96system.physmem.perBankRdBursts::1 104079 # Per bank write bursts
97system.physmem.perBankRdBursts::2 99076 # Per bank write bursts
98system.physmem.perBankRdBursts::3 102555 # Per bank write bursts
99system.physmem.perBankRdBursts::4 95026 # Per bank write bursts
100system.physmem.perBankRdBursts::5 98411 # Per bank write bursts
101system.physmem.perBankRdBursts::6 98571 # Per bank write bursts
102system.physmem.perBankRdBursts::7 95349 # Per bank write bursts
103system.physmem.perBankRdBursts::8 90083 # Per bank write bursts
104system.physmem.perBankRdBursts::9 124090 # Per bank write bursts
105system.physmem.perBankRdBursts::10 93867 # Per bank write bursts
106system.physmem.perBankRdBursts::11 97434 # Per bank write bursts
107system.physmem.perBankRdBursts::12 91060 # Per bank write bursts
108system.physmem.perBankRdBursts::13 95554 # Per bank write bursts
109system.physmem.perBankRdBursts::14 90000 # Per bank write bursts
110system.physmem.perBankRdBursts::15 92979 # Per bank write bursts
111system.physmem.perBankWrBursts::0 80467 # Per bank write bursts
112system.physmem.perBankWrBursts::1 87240 # Per bank write bursts
113system.physmem.perBankWrBursts::2 82424 # Per bank write bursts
114system.physmem.perBankWrBursts::3 84720 # Per bank write bursts
115system.physmem.perBankWrBursts::4 78521 # Per bank write bursts
116system.physmem.perBankWrBursts::5 82917 # Per bank write bursts
117system.physmem.perBankWrBursts::6 81751 # Per bank write bursts
118system.physmem.perBankWrBursts::7 80612 # Per bank write bursts
119system.physmem.perBankWrBursts::8 77294 # Per bank write bursts
120system.physmem.perBankWrBursts::9 85251 # Per bank write bursts
121system.physmem.perBankWrBursts::10 78271 # Per bank write bursts
122system.physmem.perBankWrBursts::11 81127 # Per bank write bursts
123system.physmem.perBankWrBursts::12 78007 # Per bank write bursts
124system.physmem.perBankWrBursts::13 81137 # Per bank write bursts
125system.physmem.perBankWrBursts::14 77706 # Per bank write bursts
126system.physmem.perBankWrBursts::15 79767 # Per bank write bursts
127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
128system.physmem.numWrRetry 33 # Number of times write queue was full causing retry
129system.physmem.totGap 47434891912500 # Total gap between requests
130system.physmem.readPktSize::0 0 # Read request sizes (log2)
131system.physmem.readPktSize::1 0 # Read request sizes (log2)
132system.physmem.readPktSize::2 0 # Read request sizes (log2)
133system.physmem.readPktSize::3 25 # Read request sizes (log2)
134system.physmem.readPktSize::4 21333 # Read request sizes (log2)
135system.physmem.readPktSize::5 0 # Read request sizes (log2)
136system.physmem.readPktSize::6 1543348 # Read request sizes (log2)
137system.physmem.writePktSize::0 0 # Write request sizes (log2)
138system.physmem.writePktSize::1 0 # Write request sizes (log2)
139system.physmem.writePktSize::2 2 # Write request sizes (log2)
140system.physmem.writePktSize::3 2572 # Write request sizes (log2)
141system.physmem.writePktSize::4 0 # Write request sizes (log2)
142system.physmem.writePktSize::5 0 # Write request sizes (log2)
143system.physmem.writePktSize::6 1296915 # Write request sizes (log2)
144system.physmem.rdQLenPdf::0 588411 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::1 392193 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::2 156445 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::3 159831 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::4 99518 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::5 60251 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::6 31814 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::7 29617 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::8 26249 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::9 7312 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::10 4196 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::11 2603 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::12 1676 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::13 1352 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::14 882 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::15 666 # What read queue length does an incoming req see
160system.physmem.rdQLenPdf::16 550 # What read queue length does an incoming req see
161system.physmem.rdQLenPdf::17 422 # What read queue length does an incoming req see
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163system.physmem.rdQLenPdf::19 91 # What read queue length does an incoming req see
164system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see
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183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::15 18951 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::16 21518 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::17 33036 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::18 40734 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::19 49908 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::20 58222 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::21 67476 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::22 73957 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::23 80711 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::24 84361 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::25 87259 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::26 93166 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::27 91933 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::28 94699 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::29 106371 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::30 99156 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::31 93223 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::32 82575 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::33 5494 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::34 3221 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::35 1939 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::36 1368 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::37 895 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::38 681 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::39 468 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::40 468 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::41 374 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::42 431 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::43 286 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::44 340 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::45 277 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::46 294 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::47 350 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::48 319 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::49 389 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::50 266 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::51 263 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::52 246 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::53 271 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::54 255 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::55 225 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::56 177 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::57 138 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::58 101 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::59 113 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::60 78 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::61 101 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::62 75 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::63 69 # What write queue length does an incoming req see
240system.physmem.bytesPerActivate::samples 977888 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::mean 187.273406 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::gmean 115.248079 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::stdev 243.900483 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::0-127 583799 59.70% 59.70% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::128-255 193375 19.77% 79.47% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::256-383 62560 6.40% 85.87% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::384-511 34177 3.49% 89.37% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::512-639 24599 2.52% 91.88% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::640-767 13672 1.40% 93.28% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::768-895 13781 1.41% 94.69% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::896-1023 7457 0.76% 95.45% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::1024-1151 44468 4.55% 100.00% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::total 977888 # Bytes accessed per row activation
254system.physmem.rdPerTurnAround::samples 73621 # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::mean 21.246927 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::stdev 254.221432 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::0-4095 73618 100.00% 100.00% # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::65536-69631 1 0.00% 100.00% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::total 73621 # Reads before turning the bus around for writes
262system.physmem.wrPerTurnAround::samples 73621 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::mean 17.620136 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::gmean 17.126079 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::stdev 6.628572 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::16-19 68415 92.93% 92.93% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::20-23 2834 3.85% 96.78% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::24-27 416 0.57% 97.34% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::28-31 328 0.45% 97.79% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::32-35 84 0.11% 97.90% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::36-39 303 0.41% 98.31% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::40-43 179 0.24% 98.56% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::44-47 107 0.15% 98.70% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::48-51 91 0.12% 98.83% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::52-55 122 0.17% 98.99% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::56-59 36 0.05% 99.04% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::60-63 46 0.06% 99.10% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::64-67 419 0.57% 99.67% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::68-71 29 0.04% 99.71% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::72-75 25 0.03% 99.75% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::76-79 117 0.16% 99.90% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::80-83 10 0.01% 99.92% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::96-99 2 0.00% 99.93% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::104-107 4 0.01% 99.93% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::112-115 5 0.01% 99.94% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::116-119 3 0.00% 99.94% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::120-123 2 0.00% 99.94% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::128-131 27 0.04% 99.98% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::140-143 3 0.00% 99.99% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::156-159 3 0.00% 99.99% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::164-167 3 0.00% 100.00% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads
297system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads
298system.physmem.wrPerTurnAround::total 73621 # Writes before turning the bus around for reads
299system.physmem.totQLat 78457411069 # Total ticks spent queuing
300system.physmem.totMemAccLat 107786892319 # Total ticks spent from burst creation until serviced by the DRAM
301system.physmem.totBusLat 7821195000 # Total ticks spent in databus transfers
302system.physmem.avgQLat 50156.92 # Average queueing delay per DRAM burst
303system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
304system.physmem.avgMemAccLat 68906.92 # Average memory access latency per DRAM burst
305system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s
306system.physmem.avgWrBW 1.75 # Average achieved write bandwidth in MiByte/s
307system.physmem.avgRdBWSys 2.09 # Average system read bandwidth in MiByte/s
308system.physmem.avgWrBWSys 1.75 # Average system write bandwidth in MiByte/s
309system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
310system.physmem.busUtil 0.03 # Data bus utilization in percentage
311system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
312system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
313system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing
314system.physmem.avgWrQLen 26.14 # Average write queue length when enqueuing
315system.physmem.readRowHits 1261076 # Number of row buffer hits during reads
316system.physmem.writeRowHits 622485 # Number of row buffer hits during writes
317system.physmem.readRowHitRate 80.62 # Row buffer hit rate for reads
318system.physmem.writeRowHitRate 47.99 # Row buffer hit rate for writes
319system.physmem.avgGap 16561334.66 # Average gap between requests
320system.physmem.pageHitRate 65.82 # Row buffer hit rate, read and write combined
321system.physmem_0.actEnergy 3784611600 # Energy for activate commands per rank (pJ)
322system.physmem_0.preEnergy 2065016250 # Energy for precharge commands per rank (pJ)
323system.physmem_0.readEnergy 6155541600 # Energy for read commands per rank (pJ)
324system.physmem_0.writeEnergy 4268064960 # Energy for write commands per rank (pJ)
325system.physmem_0.refreshEnergy 3098216175600 # Energy for refresh commands per rank (pJ)
326system.physmem_0.actBackEnergy 1175166619965 # Energy for active background per rank (pJ)
327system.physmem_0.preBackEnergy 27430083930000 # Energy for precharge background per rank (pJ)
328system.physmem_0.totalEnergy 31719739959975 # Total energy per rank (pJ)
329system.physmem_0.averagePower 668.700662 # Core power per rank (mW)
330system.physmem_0.memoryStateTime::IDLE 45632003284876 # Time in different power states
331system.physmem_0.memoryStateTime::REF 1583955100000 # Time in different power states
332system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
333system.physmem_0.memoryStateTime::ACT 218928032624 # Time in different power states
334system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
335system.physmem_1.actEnergy 3608221680 # Energy for activate commands per rank (pJ)
336system.physmem_1.preEnergy 1968771750 # Energy for precharge commands per rank (pJ)
337system.physmem_1.readEnergy 6045468000 # Energy for read commands per rank (pJ)
338system.physmem_1.writeEnergy 4137868800 # Energy for write commands per rank (pJ)
339system.physmem_1.refreshEnergy 3098216175600 # Energy for refresh commands per rank (pJ)
340system.physmem_1.actBackEnergy 1172302278480 # Energy for active background per rank (pJ)
341system.physmem_1.preBackEnergy 27432596510250 # Energy for precharge background per rank (pJ)
342system.physmem_1.totalEnergy 31718875294560 # Total energy per rank (pJ)
343system.physmem_1.averagePower 668.682434 # Core power per rank (mW)
344system.physmem_1.memoryStateTime::IDLE 45636187348814 # Time in different power states
345system.physmem_1.memoryStateTime::REF 1583955100000 # Time in different power states
346system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
347system.physmem_1.memoryStateTime::ACT 214746668686 # Time in different power states
348system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
349system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory
350system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
351system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
352system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
353system.realview.nvmem.bytes_read::total 572 # Number of bytes read from this memory
354system.realview.nvmem.bytes_inst_read::cpu0.inst 384 # Number of instructions bytes read from this memory
355system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory

--- 17 unchanged lines hidden (view full) ---

373system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
374system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
375system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
376system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
377system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
378system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
379system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
380system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
381system.cpu0.branchPred.lookups 146144434 # Number of BP lookups
382system.cpu0.branchPred.condPredicted 97047776 # Number of conditional branches predicted
383system.cpu0.branchPred.condIncorrect 7141884 # Number of conditional branches incorrect
384system.cpu0.branchPred.BTBLookups 102585049 # Number of BTB lookups
385system.cpu0.branchPred.BTBHits 68142392 # Number of BTB hits
386system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
387system.cpu0.branchPred.BTBHitPct 66.425266 # BTB Hit Percentage
388system.cpu0.branchPred.usedRAS 20061645 # Number of times the RAS was used to get a target.
389system.cpu0.branchPred.RASInCorrect 208019 # Number of incorrect RAS predictions.
390system.cpu_clk_domain.clock 500 # Clock period in ticks
391system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

412system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
413system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
414system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
415system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
416system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
417system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
418system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
419system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
420system.cpu0.dtb.walker.walks 627056 # Table walker walks requested
421system.cpu0.dtb.walker.walksLong 627056 # Table walker walks initiated with long descriptors
422system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13350 # Level at which table walker walks with long descriptors terminate
423system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 99805 # Level at which table walker walks with long descriptors terminate
424system.cpu0.dtb.walker.walksSquashedBefore 293358 # Table walks squashed before starting
425system.cpu0.dtb.walker.walkWaitTime::samples 333698 # Table walker wait (enqueue to first request) latency
426system.cpu0.dtb.walker.walkWaitTime::mean 2422.801455 # Table walker wait (enqueue to first request) latency
427system.cpu0.dtb.walker.walkWaitTime::stdev 15109.123610 # Table walker wait (enqueue to first request) latency
428system.cpu0.dtb.walker.walkWaitTime::0-65535 330908 99.16% 99.16% # Table walker wait (enqueue to first request) latency
429system.cpu0.dtb.walker.walkWaitTime::65536-131071 1425 0.43% 99.59% # Table walker wait (enqueue to first request) latency
430system.cpu0.dtb.walker.walkWaitTime::131072-196607 1094 0.33% 99.92% # Table walker wait (enqueue to first request) latency
431system.cpu0.dtb.walker.walkWaitTime::196608-262143 126 0.04% 99.96% # Table walker wait (enqueue to first request) latency
432system.cpu0.dtb.walker.walkWaitTime::262144-327679 36 0.01% 99.97% # Table walker wait (enqueue to first request) latency
433system.cpu0.dtb.walker.walkWaitTime::327680-393215 71 0.02% 99.99% # Table walker wait (enqueue to first request) latency
434system.cpu0.dtb.walker.walkWaitTime::393216-458751 25 0.01% 100.00% # Table walker wait (enqueue to first request) latency
435system.cpu0.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency
436system.cpu0.dtb.walker.walkWaitTime::524288-589823 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency
437system.cpu0.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
438system.cpu0.dtb.walker.walkWaitTime::total 333698 # Table walker wait (enqueue to first request) latency
439system.cpu0.dtb.walker.walkCompletionTime::samples 325671 # Table walker service (enqueue to completion) latency
440system.cpu0.dtb.walker.walkCompletionTime::mean 20358.917435 # Table walker service (enqueue to completion) latency
441system.cpu0.dtb.walker.walkCompletionTime::gmean 16786.442146 # Table walker service (enqueue to completion) latency
442system.cpu0.dtb.walker.walkCompletionTime::stdev 23186.053079 # Table walker service (enqueue to completion) latency
443system.cpu0.dtb.walker.walkCompletionTime::0-65535 321319 98.66% 98.66% # Table walker service (enqueue to completion) latency
444system.cpu0.dtb.walker.walkCompletionTime::65536-131071 949 0.29% 98.96% # Table walker service (enqueue to completion) latency
445system.cpu0.dtb.walker.walkCompletionTime::131072-196607 2404 0.74% 99.69% # Table walker service (enqueue to completion) latency
446system.cpu0.dtb.walker.walkCompletionTime::196608-262143 140 0.04% 99.74% # Table walker service (enqueue to completion) latency
447system.cpu0.dtb.walker.walkCompletionTime::262144-327679 546 0.17% 99.90% # Table walker service (enqueue to completion) latency
448system.cpu0.dtb.walker.walkCompletionTime::327680-393215 110 0.03% 99.94% # Table walker service (enqueue to completion) latency
449system.cpu0.dtb.walker.walkCompletionTime::393216-458751 121 0.04% 99.97% # Table walker service (enqueue to completion) latency
450system.cpu0.dtb.walker.walkCompletionTime::458752-524287 45 0.01% 99.99% # Table walker service (enqueue to completion) latency
451system.cpu0.dtb.walker.walkCompletionTime::524288-589823 26 0.01% 100.00% # Table walker service (enqueue to completion) latency
452system.cpu0.dtb.walker.walkCompletionTime::589824-655359 11 0.00% 100.00% # Table walker service (enqueue to completion) latency
453system.cpu0.dtb.walker.walkCompletionTime::total 325671 # Table walker service (enqueue to completion) latency
454system.cpu0.dtb.walker.walksPending::samples 568195090048 # Table walker pending requests distribution
455system.cpu0.dtb.walker.walksPending::mean 0.606171 # Table walker pending requests distribution
456system.cpu0.dtb.walker.walksPending::stdev 0.541778 # Table walker pending requests distribution
457system.cpu0.dtb.walker.walksPending::0-1 566772056048 99.75% 99.75% # Table walker pending requests distribution
458system.cpu0.dtb.walker.walksPending::2-3 811255500 0.14% 99.89% # Table walker pending requests distribution
459system.cpu0.dtb.walker.walksPending::4-5 288193500 0.05% 99.94% # Table walker pending requests distribution
460system.cpu0.dtb.walker.walksPending::6-7 133409000 0.02% 99.97% # Table walker pending requests distribution
461system.cpu0.dtb.walker.walksPending::8-9 101036500 0.02% 99.98% # Table walker pending requests distribution
462system.cpu0.dtb.walker.walksPending::10-11 47966000 0.01% 99.99% # Table walker pending requests distribution
463system.cpu0.dtb.walker.walksPending::12-13 17568000 0.00% 100.00% # Table walker pending requests distribution
464system.cpu0.dtb.walker.walksPending::14-15 22933000 0.00% 100.00% # Table walker pending requests distribution
465system.cpu0.dtb.walker.walksPending::16-17 641000 0.00% 100.00% # Table walker pending requests distribution
466system.cpu0.dtb.walker.walksPending::18-19 31500 0.00% 100.00% # Table walker pending requests distribution
467system.cpu0.dtb.walker.walksPending::total 568195090048 # Table walker pending requests distribution
468system.cpu0.dtb.walker.walkPageSizes::4K 99806 88.20% 88.20% # Table walker page sizes translated
469system.cpu0.dtb.walker.walkPageSizes::2M 13350 11.80% 100.00% # Table walker page sizes translated
470system.cpu0.dtb.walker.walkPageSizes::total 113156 # Table walker page sizes translated
471system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 627056 # Table walker requests started/completed, data/inst
472system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
473system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 627056 # Table walker requests started/completed, data/inst
474system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 113156 # Table walker requests started/completed, data/inst
475system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
476system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 113156 # Table walker requests started/completed, data/inst
477system.cpu0.dtb.walker.walkRequestOrigin::total 740212 # Table walker requests started/completed, data/inst
478system.cpu0.dtb.inst_hits 0 # ITB inst hits
479system.cpu0.dtb.inst_misses 0 # ITB inst misses
480system.cpu0.dtb.read_hits 106442927 # DTB read hits
481system.cpu0.dtb.read_misses 452572 # DTB read misses
482system.cpu0.dtb.write_hits 87367482 # DTB write hits
483system.cpu0.dtb.write_misses 174484 # DTB write misses
484system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
485system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
486system.cpu0.dtb.flush_tlb_mva_asid 44087 # Number of times TLB was flushed by MVA & ASID
487system.cpu0.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
488system.cpu0.dtb.flush_entries 43076 # Number of entries that have been flushed from TLB
489system.cpu0.dtb.align_faults 336 # Number of TLB faults due to alignment restrictions
490system.cpu0.dtb.prefetch_faults 7862 # Number of TLB faults due to prefetch
491system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
492system.cpu0.dtb.perms_faults 41749 # Number of TLB faults due to permissions restrictions
493system.cpu0.dtb.read_accesses 106895499 # DTB read accesses
494system.cpu0.dtb.write_accesses 87541966 # DTB write accesses
495system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
496system.cpu0.dtb.hits 193810409 # DTB hits
497system.cpu0.dtb.misses 627056 # DTB misses
498system.cpu0.dtb.accesses 194437465 # DTB accesses
499system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
500system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
501system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
502system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
503system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
504system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
505system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
506system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

520system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
521system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
522system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
523system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
524system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
525system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
526system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
527system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
528system.cpu0.itb.walker.walks 89572 # Table walker walks requested
529system.cpu0.itb.walker.walksLong 89572 # Table walker walks initiated with long descriptors
530system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1024 # Level at which table walker walks with long descriptors terminate
531system.cpu0.itb.walker.walksLongTerminationLevel::Level3 63745 # Level at which table walker walks with long descriptors terminate
532system.cpu0.itb.walker.walksSquashedBefore 10456 # Table walks squashed before starting
533system.cpu0.itb.walker.walkWaitTime::samples 79116 # Table walker wait (enqueue to first request) latency
534system.cpu0.itb.walker.walkWaitTime::mean 1699.586683 # Table walker wait (enqueue to first request) latency
535system.cpu0.itb.walker.walkWaitTime::stdev 13044.450560 # Table walker wait (enqueue to first request) latency
536system.cpu0.itb.walker.walkWaitTime::0-32767 78197 98.84% 98.84% # Table walker wait (enqueue to first request) latency
537system.cpu0.itb.walker.walkWaitTime::32768-65535 434 0.55% 99.39% # Table walker wait (enqueue to first request) latency
538system.cpu0.itb.walker.walkWaitTime::65536-98303 37 0.05% 99.43% # Table walker wait (enqueue to first request) latency
539system.cpu0.itb.walker.walkWaitTime::98304-131071 79 0.10% 99.53% # Table walker wait (enqueue to first request) latency
540system.cpu0.itb.walker.walkWaitTime::131072-163839 275 0.35% 99.88% # Table walker wait (enqueue to first request) latency
541system.cpu0.itb.walker.walkWaitTime::163840-196607 59 0.07% 99.96% # Table walker wait (enqueue to first request) latency
542system.cpu0.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.97% # Table walker wait (enqueue to first request) latency
543system.cpu0.itb.walker.walkWaitTime::229376-262143 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency
544system.cpu0.itb.walker.walkWaitTime::262144-294911 7 0.01% 99.98% # Table walker wait (enqueue to first request) latency
545system.cpu0.itb.walker.walkWaitTime::294912-327679 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency
546system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
547system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
548system.cpu0.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
549system.cpu0.itb.walker.walkWaitTime::total 79116 # Table walker wait (enqueue to first request) latency
550system.cpu0.itb.walker.walkCompletionTime::samples 75225 # Table walker service (enqueue to completion) latency
551system.cpu0.itb.walker.walkCompletionTime::mean 26620.711200 # Table walker service (enqueue to completion) latency
552system.cpu0.itb.walker.walkCompletionTime::gmean 21926.293248 # Table walker service (enqueue to completion) latency
553system.cpu0.itb.walker.walkCompletionTime::stdev 30000.304563 # Table walker service (enqueue to completion) latency
554system.cpu0.itb.walker.walkCompletionTime::0-65535 72890 96.90% 96.90% # Table walker service (enqueue to completion) latency
555system.cpu0.itb.walker.walkCompletionTime::65536-131071 127 0.17% 97.06% # Table walker service (enqueue to completion) latency
556system.cpu0.itb.walker.walkCompletionTime::131072-196607 1867 2.48% 99.55% # Table walker service (enqueue to completion) latency
557system.cpu0.itb.walker.walkCompletionTime::196608-262143 130 0.17% 99.72% # Table walker service (enqueue to completion) latency
558system.cpu0.itb.walker.walkCompletionTime::262144-327679 117 0.16% 99.88% # Table walker service (enqueue to completion) latency
559system.cpu0.itb.walker.walkCompletionTime::327680-393215 47 0.06% 99.94% # Table walker service (enqueue to completion) latency
560system.cpu0.itb.walker.walkCompletionTime::393216-458751 31 0.04% 99.98% # Table walker service (enqueue to completion) latency
561system.cpu0.itb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
562system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
563system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
564system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
565system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
566system.cpu0.itb.walker.walkCompletionTime::total 75225 # Table walker service (enqueue to completion) latency
567system.cpu0.itb.walker.walksPending::samples 417841685688 # Table walker pending requests distribution
568system.cpu0.itb.walker.walksPending::mean 0.859653 # Table walker pending requests distribution
569system.cpu0.itb.walker.walksPending::stdev 0.347613 # Table walker pending requests distribution
570system.cpu0.itb.walker.walksPending::0 58676119976 14.04% 14.04% # Table walker pending requests distribution
571system.cpu0.itb.walker.walksPending::1 359136359212 85.95% 99.99% # Table walker pending requests distribution
572system.cpu0.itb.walker.walksPending::2 25573000 0.01% 100.00% # Table walker pending requests distribution
573system.cpu0.itb.walker.walksPending::3 3283500 0.00% 100.00% # Table walker pending requests distribution
574system.cpu0.itb.walker.walksPending::4 186000 0.00% 100.00% # Table walker pending requests distribution
575system.cpu0.itb.walker.walksPending::5 60000 0.00% 100.00% # Table walker pending requests distribution
576system.cpu0.itb.walker.walksPending::6 104000 0.00% 100.00% # Table walker pending requests distribution
577system.cpu0.itb.walker.walksPending::total 417841685688 # Table walker pending requests distribution
578system.cpu0.itb.walker.walkPageSizes::4K 63745 98.42% 98.42% # Table walker page sizes translated
579system.cpu0.itb.walker.walkPageSizes::2M 1024 1.58% 100.00% # Table walker page sizes translated
580system.cpu0.itb.walker.walkPageSizes::total 64769 # Table walker page sizes translated
581system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
582system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 89572 # Table walker requests started/completed, data/inst
583system.cpu0.itb.walker.walkRequestOrigin_Requested::total 89572 # Table walker requests started/completed, data/inst
584system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
585system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64769 # Table walker requests started/completed, data/inst
586system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64769 # Table walker requests started/completed, data/inst
587system.cpu0.itb.walker.walkRequestOrigin::total 154341 # Table walker requests started/completed, data/inst
588system.cpu0.itb.inst_hits 230754760 # ITB inst hits
589system.cpu0.itb.inst_misses 89572 # ITB inst misses
590system.cpu0.itb.read_hits 0 # DTB read hits
591system.cpu0.itb.read_misses 0 # DTB read misses
592system.cpu0.itb.write_hits 0 # DTB write hits
593system.cpu0.itb.write_misses 0 # DTB write misses
594system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
595system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
596system.cpu0.itb.flush_tlb_mva_asid 44087 # Number of times TLB was flushed by MVA & ASID
597system.cpu0.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
598system.cpu0.itb.flush_entries 31365 # Number of entries that have been flushed from TLB
599system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
600system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
601system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
602system.cpu0.itb.perms_faults 227814 # Number of TLB faults due to permissions restrictions
603system.cpu0.itb.read_accesses 0 # DTB read accesses
604system.cpu0.itb.write_accesses 0 # DTB write accesses
605system.cpu0.itb.inst_accesses 230844332 # ITB inst accesses
606system.cpu0.itb.hits 230754760 # DTB hits
607system.cpu0.itb.misses 89572 # DTB misses
608system.cpu0.itb.accesses 230844332 # DTB accesses
609system.cpu0.numCycles 860058385 # number of cpu cycles simulated
610system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
611system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
612system.cpu0.fetch.icacheStallCycles 93823767 # Number of cycles fetch is stalled on an Icache miss
613system.cpu0.fetch.Insts 647034006 # Number of instructions fetch has processed
614system.cpu0.fetch.Branches 146144434 # Number of branches that fetch encountered
615system.cpu0.fetch.predictedBranches 88204037 # Number of branches that fetch has predicted taken
616system.cpu0.fetch.Cycles 713428063 # Number of cycles fetch has run and was not squashing or blocked
617system.cpu0.fetch.SquashCycles 15421284 # Number of cycles fetch has spent squashing
618system.cpu0.fetch.TlbCycles 2142608 # Number of cycles fetch has spent waiting for tlb
619system.cpu0.fetch.MiscStallCycles 370377 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
620system.cpu0.fetch.PendingTrapStallCycles 6662477 # Number of stall cycles due to pending traps
621system.cpu0.fetch.PendingQuiesceStallCycles 811703 # Number of stall cycles due to pending quiesce instructions
622system.cpu0.fetch.IcacheWaitRetryStallCycles 935488 # Number of stall cycles due to full MSHR
623system.cpu0.fetch.CacheLines 230526197 # Number of cache lines fetched
624system.cpu0.fetch.IcacheSquashes 1802314 # Number of outstanding Icache misses that were squashed
625system.cpu0.fetch.ItlbSquashes 29828 # Number of outstanding ITLB misses that were squashed
626system.cpu0.fetch.rateDist::samples 825885125 # Number of instructions fetched each cycle (Total)
627system.cpu0.fetch.rateDist::mean 0.917836 # Number of instructions fetched each cycle (Total)
628system.cpu0.fetch.rateDist::stdev 1.204243 # Number of instructions fetched each cycle (Total)
629system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
630system.cpu0.fetch.rateDist::0 462725297 56.03% 56.03% # Number of instructions fetched each cycle (Total)
631system.cpu0.fetch.rateDist::1 141134334 17.09% 73.12% # Number of instructions fetched each cycle (Total)
632system.cpu0.fetch.rateDist::2 49183945 5.96% 79.07% # Number of instructions fetched each cycle (Total)
633system.cpu0.fetch.rateDist::3 172841549 20.93% 100.00% # Number of instructions fetched each cycle (Total)
634system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
635system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
636system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
637system.cpu0.fetch.rateDist::total 825885125 # Number of instructions fetched each cycle (Total)
638system.cpu0.fetch.branchRate 0.169924 # Number of branch fetches per cycle
639system.cpu0.fetch.rate 0.752314 # Number of inst fetches per cycle
640system.cpu0.decode.IdleCycles 112769742 # Number of cycles decode is idle
641system.cpu0.decode.BlockedCycles 426082666 # Number of cycles decode is blocked
642system.cpu0.decode.RunCycles 241448796 # Number of cycles decode is running
643system.cpu0.decode.UnblockCycles 40086734 # Number of cycles decode is unblocking
644system.cpu0.decode.SquashCycles 5497187 # Number of cycles decode is squashing
645system.cpu0.decode.BranchResolved 21049410 # Number of times decode resolved a branch
646system.cpu0.decode.BranchMispred 2256773 # Number of times decode detected a branch misprediction
647system.cpu0.decode.DecodedInsts 670218998 # Number of instructions handled by decode
648system.cpu0.decode.SquashedInsts 24585217 # Number of squashed instructions handled by decode
649system.cpu0.rename.SquashCycles 5497187 # Number of cycles rename is squashing
650system.cpu0.rename.IdleCycles 150343342 # Number of cycles rename is idle
651system.cpu0.rename.BlockCycles 70257974 # Number of cycles rename is blocking
652system.cpu0.rename.serializeStallCycles 265091659 # count of cycles rename stalled for serializing inst
653system.cpu0.rename.RunCycles 243360217 # Number of cycles rename is running
654system.cpu0.rename.UnblockCycles 91334746 # Number of cycles rename is unblocking
655system.cpu0.rename.RenamedInsts 651968055 # Number of instructions processed by rename
656system.cpu0.rename.SquashedInsts 6322268 # Number of squashed instructions processed by rename
657system.cpu0.rename.ROBFullEvents 11333163 # Number of times rename has blocked due to ROB full
658system.cpu0.rename.IQFullEvents 398238 # Number of times rename has blocked due to IQ full
659system.cpu0.rename.LQFullEvents 892987 # Number of times rename has blocked due to LQ full
660system.cpu0.rename.SQFullEvents 53687870 # Number of times rename has blocked due to SQ full
661system.cpu0.rename.FullRegisterEvents 12055 # Number of times there has been no free registers
662system.cpu0.rename.RenamedOperands 623161441 # Number of destination operands rename has renamed
663system.cpu0.rename.RenameLookups 1008090615 # Number of register rename lookups that rename has made
664system.cpu0.rename.int_rename_lookups 769730678 # Number of integer rename lookups
665system.cpu0.rename.fp_rename_lookups 803084 # Number of floating rename lookups
666system.cpu0.rename.CommittedMaps 561865875 # Number of HB maps that are committed
667system.cpu0.rename.UndoneMaps 61295566 # Number of HB maps that are undone due to squashing
668system.cpu0.rename.serializingInsts 16618595 # count of serializing insts renamed
669system.cpu0.rename.tempSerializingInsts 14448752 # count of temporary serializing insts renamed
670system.cpu0.rename.skidInsts 81009207 # count of insts added to the skid buffer
671system.cpu0.memDep0.insertedLoads 106588320 # Number of loads inserted to the mem dependence unit.
672system.cpu0.memDep0.insertedStores 90921259 # Number of stores inserted to the mem dependence unit.
673system.cpu0.memDep0.conflictingLoads 9791542 # Number of conflicting loads.
674system.cpu0.memDep0.conflictingStores 8386441 # Number of conflicting stores.
675system.cpu0.iq.iqInstsAdded 628410475 # Number of instructions added to the IQ (excludes non-spec)
676system.cpu0.iq.iqNonSpecInstsAdded 16690332 # Number of non-speculative instructions added to the IQ
677system.cpu0.iq.iqInstsIssued 633219394 # Number of instructions issued
678system.cpu0.iq.iqSquashedInstsIssued 2873840 # Number of squashed instructions issued
679system.cpu0.iq.iqSquashedInstsExamined 57472988 # Number of squashed instructions iterated over during squash; mainly for profiling
680system.cpu0.iq.iqSquashedOperandsExamined 37517559 # Number of squashed operands that are examined and possibly removed from graph
681system.cpu0.iq.iqSquashedNonSpecRemoved 288712 # Number of squashed non-spec instructions that were removed
682system.cpu0.iq.issued_per_cycle::samples 825885125 # Number of insts issued each cycle
683system.cpu0.iq.issued_per_cycle::mean 0.766716 # Number of insts issued each cycle
684system.cpu0.iq.issued_per_cycle::stdev 1.051496 # Number of insts issued each cycle
685system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
686system.cpu0.iq.issued_per_cycle::0 480372364 58.16% 58.16% # Number of insts issued each cycle
687system.cpu0.iq.issued_per_cycle::1 144500445 17.50% 75.66% # Number of insts issued each cycle
688system.cpu0.iq.issued_per_cycle::2 122618774 14.85% 90.51% # Number of insts issued each cycle
689system.cpu0.iq.issued_per_cycle::3 70098834 8.49% 99.00% # Number of insts issued each cycle
690system.cpu0.iq.issued_per_cycle::4 8288641 1.00% 100.00% # Number of insts issued each cycle
691system.cpu0.iq.issued_per_cycle::5 6067 0.00% 100.00% # Number of insts issued each cycle
692system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
693system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
694system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
695system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
696system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
697system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
698system.cpu0.iq.issued_per_cycle::total 825885125 # Number of insts issued each cycle
699system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
700system.cpu0.iq.fu_full::IntAlu 65372240 45.40% 45.40% # attempts to use FU when none available
701system.cpu0.iq.fu_full::IntMult 70238 0.05% 45.45% # attempts to use FU when none available
702system.cpu0.iq.fu_full::IntDiv 24747 0.02% 45.46% # attempts to use FU when none available
703system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.46% # attempts to use FU when none available
704system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.46% # attempts to use FU when none available
705system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.46% # attempts to use FU when none available
706system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.46% # attempts to use FU when none available
707system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.46% # attempts to use FU when none available
708system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.46% # attempts to use FU when none available
709system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.46% # attempts to use FU when none available
710system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.46% # attempts to use FU when none available
711system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.46% # attempts to use FU when none available
712system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.46% # attempts to use FU when none available
713system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.46% # attempts to use FU when none available
714system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.46% # attempts to use FU when none available
715system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.46% # attempts to use FU when none available
716system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.46% # attempts to use FU when none available
717system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.46% # attempts to use FU when none available
718system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.46% # attempts to use FU when none available
719system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.46% # attempts to use FU when none available
720system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.46% # attempts to use FU when none available
721system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.46% # attempts to use FU when none available
722system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.46% # attempts to use FU when none available
723system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.46% # attempts to use FU when none available
724system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.46% # attempts to use FU when none available
725system.cpu0.iq.fu_full::SimdFloatMisc 29 0.00% 45.46% # attempts to use FU when none available
726system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.46% # attempts to use FU when none available
727system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.46% # attempts to use FU when none available
728system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.46% # attempts to use FU when none available
729system.cpu0.iq.fu_full::MemRead 37918627 26.33% 71.79% # attempts to use FU when none available
730system.cpu0.iq.fu_full::MemWrite 40615883 28.21% 100.00% # attempts to use FU when none available
731system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
732system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
733system.cpu0.iq.FU_type_0::No_OpClass 10 0.00% 0.00% # Type of FU issued
734system.cpu0.iq.FU_type_0::IntAlu 433018605 68.38% 68.38% # Type of FU issued
735system.cpu0.iq.FU_type_0::IntMult 1583156 0.25% 68.63% # Type of FU issued
736system.cpu0.iq.FU_type_0::IntDiv 81666 0.01% 68.65% # Type of FU issued
737system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.65% # Type of FU issued
738system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.65% # Type of FU issued
739system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.65% # Type of FU issued
740system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.65% # Type of FU issued
741system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.65% # Type of FU issued
742system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.65% # Type of FU issued
743system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.65% # Type of FU issued
744system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.65% # Type of FU issued
745system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.65% # Type of FU issued
746system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.65% # Type of FU issued
747system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.65% # Type of FU issued
748system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.65% # Type of FU issued
749system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.65% # Type of FU issued
750system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.65% # Type of FU issued
751system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.65% # Type of FU issued
752system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.65% # Type of FU issued
753system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.65% # Type of FU issued
754system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.65% # Type of FU issued
755system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.65% # Type of FU issued
756system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.65% # Type of FU issued
757system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.65% # Type of FU issued
758system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.65% # Type of FU issued
759system.cpu0.iq.FU_type_0::SimdFloatMisc 80947 0.01% 68.66% # Type of FU issued
760system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.66% # Type of FU issued
761system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.66% # Type of FU issued
762system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.66% # Type of FU issued
763system.cpu0.iq.FU_type_0::MemRead 109728452 17.33% 85.99% # Type of FU issued
764system.cpu0.iq.FU_type_0::MemWrite 88726558 14.01% 100.00% # Type of FU issued
765system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
766system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
767system.cpu0.iq.FU_type_0::total 633219394 # Type of FU issued
768system.cpu0.iq.rate 0.736252 # Inst issue rate
769system.cpu0.iq.fu_busy_cnt 144001764 # FU busy when requested
770system.cpu0.iq.fu_busy_rate 0.227412 # FU busy rate (busy events/executed inst)
771system.cpu0.iq.int_inst_queue_reads 2237858803 # Number of integer instruction queue reads
772system.cpu0.iq.int_inst_queue_writes 702176142 # Number of integer instruction queue writes
773system.cpu0.iq.int_inst_queue_wakeup_accesses 615023589 # Number of integer instruction queue wakeup accesses
774system.cpu0.iq.fp_inst_queue_reads 1340714 # Number of floating instruction queue reads
775system.cpu0.iq.fp_inst_queue_writes 546565 # Number of floating instruction queue writes
776system.cpu0.iq.fp_inst_queue_wakeup_accesses 499647 # Number of floating instruction queue wakeup accesses
777system.cpu0.iq.int_alu_accesses 776393889 # Number of integer alu accesses
778system.cpu0.iq.fp_alu_accesses 827259 # Number of floating point alu accesses
779system.cpu0.iew.lsq.thread0.forwLoads 2940154 # Number of loads that had data forwarded from stores
780system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
781system.cpu0.iew.lsq.thread0.squashedLoads 13228982 # Number of loads squashed
782system.cpu0.iew.lsq.thread0.ignoredResponses 17998 # Number of memory responses ignored because the instruction is squashed
783system.cpu0.iew.lsq.thread0.memOrderViolation 150420 # Number of memory ordering violations
784system.cpu0.iew.lsq.thread0.squashedStores 6097724 # Number of stores squashed
785system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
786system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
787system.cpu0.iew.lsq.thread0.rescheduledLoads 2855732 # Number of loads that were rescheduled
788system.cpu0.iew.lsq.thread0.cacheBlocked 4944067 # Number of times an access to memory failed due to the cache being blocked
789system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
790system.cpu0.iew.iewSquashCycles 5497187 # Number of cycles IEW is squashing
791system.cpu0.iew.iewBlockCycles 8555370 # Number of cycles IEW is blocking
792system.cpu0.iew.iewUnblockCycles 7804154 # Number of cycles IEW is unblocking
793system.cpu0.iew.iewDispatchedInsts 645228891 # Number of instructions dispatched to IQ
794system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
795system.cpu0.iew.iewDispLoadInsts 106588320 # Number of dispatched load instructions
796system.cpu0.iew.iewDispStoreInsts 90921259 # Number of dispatched store instructions
797system.cpu0.iew.iewDispNonSpecInsts 14154267 # Number of dispatched non-speculative instructions
798system.cpu0.iew.iewIQFullEvents 60797 # Number of times the IQ has become full, causing a stall
799system.cpu0.iew.iewLSQFullEvents 7667643 # Number of times the LSQ has become full, causing a stall
800system.cpu0.iew.memOrderViolationEvents 150420 # Number of memory order violations
801system.cpu0.iew.predictedTakenIncorrect 2190803 # Number of branches that were predicted taken incorrectly
802system.cpu0.iew.predictedNotTakenIncorrect 3056972 # Number of branches that were predicted not taken incorrectly
803system.cpu0.iew.branchMispredicts 5247775 # Number of branch mispredicts detected at execute
804system.cpu0.iew.iewExecutedInsts 624930976 # Number of executed instructions
805system.cpu0.iew.iewExecLoadInsts 106438227 # Number of load instructions executed
806system.cpu0.iew.iewExecSquashedInsts 7669606 # Number of squashed instructions skipped in execute
807system.cpu0.iew.exec_swp 0 # number of swp insts executed
808system.cpu0.iew.exec_nop 128084 # number of nop insts executed
809system.cpu0.iew.exec_refs 193805308 # number of memory reference insts executed
810system.cpu0.iew.exec_branches 117788400 # Number of branches executed
811system.cpu0.iew.exec_stores 87367081 # Number of stores executed
812system.cpu0.iew.exec_rate 0.726615 # Inst execution rate
813system.cpu0.iew.wb_sent 616360773 # cumulative count of insts sent to commit
814system.cpu0.iew.wb_count 615523236 # cumulative count of insts written-back
815system.cpu0.iew.wb_producers 299533919 # num instructions producing a value
816system.cpu0.iew.wb_consumers 491459888 # num instructions consuming a value
817system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
818system.cpu0.iew.wb_rate 0.715676 # insts written-back per cycle
819system.cpu0.iew.wb_fanout 0.609478 # average fanout of values written-back
820system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
821system.cpu0.commit.commitSquashedInsts 50152735 # The number of squashed insts skipped by commit
822system.cpu0.commit.commitNonSpecStalls 16401620 # The number of times commit has been forced to stall to communicate backwards
823system.cpu0.commit.branchMispredicts 4928429 # The number of times a branch was mispredicted
824system.cpu0.commit.committed_per_cycle::samples 816336878 # Number of insts commited each cycle
825system.cpu0.commit.committed_per_cycle::mean 0.719835 # Number of insts commited each cycle
826system.cpu0.commit.committed_per_cycle::stdev 1.528210 # Number of insts commited each cycle
827system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
828system.cpu0.commit.committed_per_cycle::0 559210939 68.50% 68.50% # Number of insts commited each cycle
829system.cpu0.commit.committed_per_cycle::1 132620550 16.25% 84.75% # Number of insts commited each cycle
830system.cpu0.commit.committed_per_cycle::2 57447612 7.04% 91.79% # Number of insts commited each cycle
831system.cpu0.commit.committed_per_cycle::3 19359516 2.37% 94.16% # Number of insts commited each cycle
832system.cpu0.commit.committed_per_cycle::4 13667086 1.67% 95.83% # Number of insts commited each cycle
833system.cpu0.commit.committed_per_cycle::5 9472900 1.16% 96.99% # Number of insts commited each cycle
834system.cpu0.commit.committed_per_cycle::6 6300261 0.77% 97.76% # Number of insts commited each cycle
835system.cpu0.commit.committed_per_cycle::7 3865026 0.47% 98.24% # Number of insts commited each cycle
836system.cpu0.commit.committed_per_cycle::8 14392988 1.76% 100.00% # Number of insts commited each cycle
837system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
838system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
839system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
840system.cpu0.commit.committed_per_cycle::total 816336878 # Number of insts commited each cycle
841system.cpu0.commit.committedInsts 500561663 # Number of instructions committed
842system.cpu0.commit.committedOps 587627818 # Number of ops (including micro ops) committed
843system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
844system.cpu0.commit.refs 178182873 # Number of memory references committed
845system.cpu0.commit.loads 93359338 # Number of loads committed
846system.cpu0.commit.membars 3999106 # Number of memory barriers committed
847system.cpu0.commit.branches 111869987 # Number of branches committed
848system.cpu0.commit.fp_insts 487433 # Number of committed floating point instructions.
849system.cpu0.commit.int_insts 538915028 # Number of committed integer instructions.
850system.cpu0.commit.function_calls 14906557 # Number of function calls committed.
851system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
852system.cpu0.commit.op_class_0::IntAlu 407981366 69.43% 69.43% # Class of committed instruction
853system.cpu0.commit.op_class_0::IntMult 1327807 0.23% 69.65% # Class of committed instruction
854system.cpu0.commit.op_class_0::IntDiv 64470 0.01% 69.67% # Class of committed instruction
855system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.67% # Class of committed instruction
856system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.67% # Class of committed instruction
857system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.67% # Class of committed instruction
858system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.67% # Class of committed instruction
859system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.67% # Class of committed instruction
860system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.67% # Class of committed instruction
861system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.67% # Class of committed instruction
862system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.67% # Class of committed instruction
863system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.67% # Class of committed instruction
864system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.67% # Class of committed instruction
865system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.67% # Class of committed instruction
866system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.67% # Class of committed instruction
867system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.67% # Class of committed instruction
868system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.67% # Class of committed instruction
869system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.67% # Class of committed instruction
870system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.67% # Class of committed instruction
871system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.67% # Class of committed instruction
872system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.67% # Class of committed instruction
873system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.67% # Class of committed instruction
874system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.67% # Class of committed instruction
875system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.67% # Class of committed instruction
876system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.67% # Class of committed instruction
877system.cpu0.commit.op_class_0::SimdFloatMisc 71302 0.01% 69.68% # Class of committed instruction
878system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.68% # Class of committed instruction
879system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.68% # Class of committed instruction
880system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.68% # Class of committed instruction
881system.cpu0.commit.op_class_0::MemRead 93359338 15.89% 85.57% # Class of committed instruction
882system.cpu0.commit.op_class_0::MemWrite 84823535 14.43% 100.00% # Class of committed instruction
883system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
884system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
885system.cpu0.commit.op_class_0::total 587627818 # Class of committed instruction
886system.cpu0.commit.bw_lim_events 14392988 # number cycles where commit BW limit reached
887system.cpu0.rob.rob_reads 1435053387 # The number of ROB reads
888system.cpu0.rob.rob_writes 1285071513 # The number of ROB writes
889system.cpu0.timesIdled 1102508 # Number of times that the entire CPU went into an idle state and unscheduled itself
890system.cpu0.idleCycles 34173260 # Total number of cycles that the CPU has spent unscheduled due to idling
891system.cpu0.quiesceCycles 94009700955 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
892system.cpu0.committedInsts 500561663 # Number of Instructions Simulated
893system.cpu0.committedOps 587627818 # Number of Ops (including micro ops) Simulated
894system.cpu0.cpi 1.718187 # CPI: Cycles Per Instruction
895system.cpu0.cpi_total 1.718187 # CPI: Total CPI of All Threads
896system.cpu0.ipc 0.582009 # IPC: Instructions Per Cycle
897system.cpu0.ipc_total 0.582009 # IPC: Total IPC of All Threads
898system.cpu0.int_regfile_reads 737541509 # number of integer regfile reads
899system.cpu0.int_regfile_writes 438217894 # number of integer regfile writes
900system.cpu0.fp_regfile_reads 788412 # number of floating regfile reads
901system.cpu0.fp_regfile_writes 466436 # number of floating regfile writes
902system.cpu0.cc_regfile_reads 137084844 # number of cc regfile reads
903system.cpu0.cc_regfile_writes 137795028 # number of cc regfile writes
904system.cpu0.misc_regfile_reads 1439828550 # number of misc regfile reads
905system.cpu0.misc_regfile_writes 16463907 # number of misc regfile writes
906system.cpu0.dcache.tags.replacements 6421526 # number of replacements
907system.cpu0.dcache.tags.tagsinuse 508.135251 # Cycle average of tags in use
908system.cpu0.dcache.tags.total_refs 165251545 # Total number of references to valid blocks.
909system.cpu0.dcache.tags.sampled_refs 6422031 # Sample count of references to valid blocks.
910system.cpu0.dcache.tags.avg_refs 25.731976 # Average number of references to valid blocks.
911system.cpu0.dcache.tags.warmup_cycle 2962355000 # Cycle when the warmup percentage was hit.
912system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.135251 # Average occupied blocks per requestor
913system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992452 # Average percentage of cache occupancy
914system.cpu0.dcache.tags.occ_percent::total 0.992452 # Average percentage of cache occupancy
915system.cpu0.dcache.tags.occ_task_id_blocks::1024 505 # Occupied blocks per task id
916system.cpu0.dcache.tags.age_task_id_blocks_1024::1 452 # Occupied blocks per task id
917system.cpu0.dcache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id
918system.cpu0.dcache.tags.occ_task_id_percent::1024 0.986328 # Percentage of cache occupancy per task id
919system.cpu0.dcache.tags.tag_accesses 369713036 # Number of tag accesses
920system.cpu0.dcache.tags.data_accesses 369713036 # Number of data accesses
921system.cpu0.dcache.ReadReq_hits::cpu0.data 86498014 # number of ReadReq hits
922system.cpu0.dcache.ReadReq_hits::total 86498014 # number of ReadReq hits
923system.cpu0.dcache.WriteReq_hits::cpu0.data 73594824 # number of WriteReq hits
924system.cpu0.dcache.WriteReq_hits::total 73594824 # number of WriteReq hits
925system.cpu0.dcache.SoftPFReq_hits::cpu0.data 223952 # number of SoftPFReq hits
926system.cpu0.dcache.SoftPFReq_hits::total 223952 # number of SoftPFReq hits
927system.cpu0.dcache.WriteLineReq_hits::cpu0.data 261481 # number of WriteLineReq hits
928system.cpu0.dcache.WriteLineReq_hits::total 261481 # number of WriteLineReq hits
929system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1906554 # number of LoadLockedReq hits
930system.cpu0.dcache.LoadLockedReq_hits::total 1906554 # number of LoadLockedReq hits
931system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1959919 # number of StoreCondReq hits
932system.cpu0.dcache.StoreCondReq_hits::total 1959919 # number of StoreCondReq hits
933system.cpu0.dcache.demand_hits::cpu0.data 160092838 # number of demand (read+write) hits
934system.cpu0.dcache.demand_hits::total 160092838 # number of demand (read+write) hits
935system.cpu0.dcache.overall_hits::cpu0.data 160316790 # number of overall hits
936system.cpu0.dcache.overall_hits::total 160316790 # number of overall hits
937system.cpu0.dcache.ReadReq_misses::cpu0.data 7115044 # number of ReadReq misses
938system.cpu0.dcache.ReadReq_misses::total 7115044 # number of ReadReq misses
939system.cpu0.dcache.WriteReq_misses::cpu0.data 7950326 # number of WriteReq misses
940system.cpu0.dcache.WriteReq_misses::total 7950326 # number of WriteReq misses
941system.cpu0.dcache.SoftPFReq_misses::cpu0.data 760555 # number of SoftPFReq misses
942system.cpu0.dcache.SoftPFReq_misses::total 760555 # number of SoftPFReq misses
943system.cpu0.dcache.WriteLineReq_misses::cpu0.data 841390 # number of WriteLineReq misses
944system.cpu0.dcache.WriteLineReq_misses::total 841390 # number of WriteLineReq misses
945system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 287295 # number of LoadLockedReq misses
946system.cpu0.dcache.LoadLockedReq_misses::total 287295 # number of LoadLockedReq misses
947system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195310 # number of StoreCondReq misses
948system.cpu0.dcache.StoreCondReq_misses::total 195310 # number of StoreCondReq misses
949system.cpu0.dcache.demand_misses::cpu0.data 15065370 # number of demand (read+write) misses
950system.cpu0.dcache.demand_misses::total 15065370 # number of demand (read+write) misses
951system.cpu0.dcache.overall_misses::cpu0.data 15825925 # number of overall misses
952system.cpu0.dcache.overall_misses::total 15825925 # number of overall misses
953system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 123619441500 # number of ReadReq miss cycles
954system.cpu0.dcache.ReadReq_miss_latency::total 123619441500 # number of ReadReq miss cycles
955system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 174765170319 # number of WriteReq miss cycles
956system.cpu0.dcache.WriteReq_miss_latency::total 174765170319 # number of WriteReq miss cycles
957system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 99329075406 # number of WriteLineReq miss cycles
958system.cpu0.dcache.WriteLineReq_miss_latency::total 99329075406 # number of WriteLineReq miss cycles
959system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4513560000 # number of LoadLockedReq miss cycles
960system.cpu0.dcache.LoadLockedReq_miss_latency::total 4513560000 # number of LoadLockedReq miss cycles
961system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4763112500 # number of StoreCondReq miss cycles
962system.cpu0.dcache.StoreCondReq_miss_latency::total 4763112500 # number of StoreCondReq miss cycles
963system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4991000 # number of StoreCondFailReq miss cycles
964system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4991000 # number of StoreCondFailReq miss cycles
965system.cpu0.dcache.demand_miss_latency::cpu0.data 298384611819 # number of demand (read+write) miss cycles
966system.cpu0.dcache.demand_miss_latency::total 298384611819 # number of demand (read+write) miss cycles
967system.cpu0.dcache.overall_miss_latency::cpu0.data 298384611819 # number of overall miss cycles
968system.cpu0.dcache.overall_miss_latency::total 298384611819 # number of overall miss cycles
969system.cpu0.dcache.ReadReq_accesses::cpu0.data 93613058 # number of ReadReq accesses(hits+misses)
970system.cpu0.dcache.ReadReq_accesses::total 93613058 # number of ReadReq accesses(hits+misses)
971system.cpu0.dcache.WriteReq_accesses::cpu0.data 81545150 # number of WriteReq accesses(hits+misses)
972system.cpu0.dcache.WriteReq_accesses::total 81545150 # number of WriteReq accesses(hits+misses)
973system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 984507 # number of SoftPFReq accesses(hits+misses)
974system.cpu0.dcache.SoftPFReq_accesses::total 984507 # number of SoftPFReq accesses(hits+misses)
975system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1102871 # number of WriteLineReq accesses(hits+misses)
976system.cpu0.dcache.WriteLineReq_accesses::total 1102871 # number of WriteLineReq accesses(hits+misses)
977system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2193849 # number of LoadLockedReq accesses(hits+misses)
978system.cpu0.dcache.LoadLockedReq_accesses::total 2193849 # number of LoadLockedReq accesses(hits+misses)
979system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2155229 # number of StoreCondReq accesses(hits+misses)
980system.cpu0.dcache.StoreCondReq_accesses::total 2155229 # number of StoreCondReq accesses(hits+misses)
981system.cpu0.dcache.demand_accesses::cpu0.data 175158208 # number of demand (read+write) accesses
982system.cpu0.dcache.demand_accesses::total 175158208 # number of demand (read+write) accesses
983system.cpu0.dcache.overall_accesses::cpu0.data 176142715 # number of overall (read+write) accesses
984system.cpu0.dcache.overall_accesses::total 176142715 # number of overall (read+write) accesses
985system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.076005 # miss rate for ReadReq accesses
986system.cpu0.dcache.ReadReq_miss_rate::total 0.076005 # miss rate for ReadReq accesses
987system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.097496 # miss rate for WriteReq accesses
988system.cpu0.dcache.WriteReq_miss_rate::total 0.097496 # miss rate for WriteReq accesses
989system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.772524 # miss rate for SoftPFReq accesses
990system.cpu0.dcache.SoftPFReq_miss_rate::total 0.772524 # miss rate for SoftPFReq accesses
991system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.762909 # miss rate for WriteLineReq accesses
992system.cpu0.dcache.WriteLineReq_miss_rate::total 0.762909 # miss rate for WriteLineReq accesses
993system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.130955 # miss rate for LoadLockedReq accesses
994system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.130955 # miss rate for LoadLockedReq accesses
995system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.090621 # miss rate for StoreCondReq accesses
996system.cpu0.dcache.StoreCondReq_miss_rate::total 0.090621 # miss rate for StoreCondReq accesses
997system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086010 # miss rate for demand accesses
998system.cpu0.dcache.demand_miss_rate::total 0.086010 # miss rate for demand accesses
999system.cpu0.dcache.overall_miss_rate::cpu0.data 0.089847 # miss rate for overall accesses
1000system.cpu0.dcache.overall_miss_rate::total 0.089847 # miss rate for overall accesses
1001system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17374.374846 # average ReadReq miss latency
1002system.cpu0.dcache.ReadReq_avg_miss_latency::total 17374.374846 # average ReadReq miss latency
1003system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21982.138886 # average WriteReq miss latency
1004system.cpu0.dcache.WriteReq_avg_miss_latency::total 21982.138886 # average WriteReq miss latency
1005system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 118053.548778 # average WriteLineReq miss latency
1006system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 118053.548778 # average WriteLineReq miss latency
1007system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15710.541430 # average LoadLockedReq miss latency
1008system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15710.541430 # average LoadLockedReq miss latency
1009system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24387.448159 # average StoreCondReq miss latency
1010system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24387.448159 # average StoreCondReq miss latency
1011system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
1012system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1013system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19805.992937 # average overall miss latency
1014system.cpu0.dcache.demand_avg_miss_latency::total 19805.992937 # average overall miss latency
1015system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18854.165669 # average overall miss latency
1016system.cpu0.dcache.overall_avg_miss_latency::total 18854.165669 # average overall miss latency
1017system.cpu0.dcache.blocked_cycles::no_mshrs 31101776 # number of cycles access was blocked
1018system.cpu0.dcache.blocked_cycles::no_targets 27008277 # number of cycles access was blocked
1019system.cpu0.dcache.blocked::no_mshrs 772694 # number of cycles access was blocked
1020system.cpu0.dcache.blocked::no_targets 787427 # number of cycles access was blocked
1021system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.251090 # average number of cycles each access was blocked
1022system.cpu0.dcache.avg_blocked_cycles::no_targets 34.299404 # average number of cycles each access was blocked
1023system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1024system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1025system.cpu0.dcache.writebacks::writebacks 4324525 # number of writebacks
1026system.cpu0.dcache.writebacks::total 4324525 # number of writebacks
1027system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3632070 # number of ReadReq MSHR hits
1028system.cpu0.dcache.ReadReq_mshr_hits::total 3632070 # number of ReadReq MSHR hits
1029system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6394266 # number of WriteReq MSHR hits
1030system.cpu0.dcache.WriteReq_mshr_hits::total 6394266 # number of WriteReq MSHR hits
1031system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4384 # number of WriteLineReq MSHR hits
1032system.cpu0.dcache.WriteLineReq_mshr_hits::total 4384 # number of WriteLineReq MSHR hits
1033system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 147311 # number of LoadLockedReq MSHR hits
1034system.cpu0.dcache.LoadLockedReq_mshr_hits::total 147311 # number of LoadLockedReq MSHR hits
1035system.cpu0.dcache.demand_mshr_hits::cpu0.data 10026336 # number of demand (read+write) MSHR hits
1036system.cpu0.dcache.demand_mshr_hits::total 10026336 # number of demand (read+write) MSHR hits
1037system.cpu0.dcache.overall_mshr_hits::cpu0.data 10026336 # number of overall MSHR hits
1038system.cpu0.dcache.overall_mshr_hits::total 10026336 # number of overall MSHR hits
1039system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3482974 # number of ReadReq MSHR misses
1040system.cpu0.dcache.ReadReq_mshr_misses::total 3482974 # number of ReadReq MSHR misses
1041system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1556060 # number of WriteReq MSHR misses
1042system.cpu0.dcache.WriteReq_mshr_misses::total 1556060 # number of WriteReq MSHR misses
1043system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 753575 # number of SoftPFReq MSHR misses
1044system.cpu0.dcache.SoftPFReq_mshr_misses::total 753575 # number of SoftPFReq MSHR misses
1045system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 837006 # number of WriteLineReq MSHR misses
1046system.cpu0.dcache.WriteLineReq_mshr_misses::total 837006 # number of WriteLineReq MSHR misses
1047system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 139984 # number of LoadLockedReq MSHR misses
1048system.cpu0.dcache.LoadLockedReq_mshr_misses::total 139984 # number of LoadLockedReq MSHR misses
1049system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195309 # number of StoreCondReq MSHR misses
1050system.cpu0.dcache.StoreCondReq_mshr_misses::total 195309 # number of StoreCondReq MSHR misses
1051system.cpu0.dcache.demand_mshr_misses::cpu0.data 5039034 # number of demand (read+write) MSHR misses
1052system.cpu0.dcache.demand_mshr_misses::total 5039034 # number of demand (read+write) MSHR misses
1053system.cpu0.dcache.overall_mshr_misses::cpu0.data 5792609 # number of overall MSHR misses
1054system.cpu0.dcache.overall_mshr_misses::total 5792609 # number of overall MSHR misses
1055system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31951 # number of ReadReq MSHR uncacheable
1056system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31951 # number of ReadReq MSHR uncacheable
1057system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31485 # number of WriteReq MSHR uncacheable
1058system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31485 # number of WriteReq MSHR uncacheable
1059system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 63436 # number of overall MSHR uncacheable misses
1060system.cpu0.dcache.overall_mshr_uncacheable_misses::total 63436 # number of overall MSHR uncacheable misses
1061system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 56753773500 # number of ReadReq MSHR miss cycles
1062system.cpu0.dcache.ReadReq_mshr_miss_latency::total 56753773500 # number of ReadReq MSHR miss cycles
1063system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 38838935578 # number of WriteReq MSHR miss cycles
1064system.cpu0.dcache.WriteReq_mshr_miss_latency::total 38838935578 # number of WriteReq MSHR miss cycles
1065system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 19682576500 # number of SoftPFReq MSHR miss cycles
1066system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 19682576500 # number of SoftPFReq MSHR miss cycles
1067system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 98248508406 # number of WriteLineReq MSHR miss cycles
1068system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 98248508406 # number of WriteLineReq MSHR miss cycles
1069system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1973900000 # number of LoadLockedReq MSHR miss cycles
1070system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1973900000 # number of LoadLockedReq MSHR miss cycles
1071system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4567861500 # number of StoreCondReq MSHR miss cycles
1072system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4567861500 # number of StoreCondReq MSHR miss cycles
1073system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4933000 # number of StoreCondFailReq MSHR miss cycles
1074system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4933000 # number of StoreCondFailReq MSHR miss cycles
1075system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95592709078 # number of demand (read+write) MSHR miss cycles
1076system.cpu0.dcache.demand_mshr_miss_latency::total 95592709078 # number of demand (read+write) MSHR miss cycles
1077system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115275285578 # number of overall MSHR miss cycles
1078system.cpu0.dcache.overall_mshr_miss_latency::total 115275285578 # number of overall MSHR miss cycles
1079system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5771319500 # number of ReadReq MSHR uncacheable cycles
1080system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5771319500 # number of ReadReq MSHR uncacheable cycles
1081system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5597630000 # number of WriteReq MSHR uncacheable cycles
1082system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5597630000 # number of WriteReq MSHR uncacheable cycles
1083system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11368949500 # number of overall MSHR uncacheable cycles
1084system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11368949500 # number of overall MSHR uncacheable cycles
1085system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037206 # mshr miss rate for ReadReq accesses
1086system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037206 # mshr miss rate for ReadReq accesses
1087system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019082 # mshr miss rate for WriteReq accesses
1088system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019082 # mshr miss rate for WriteReq accesses
1089system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.765434 # mshr miss rate for SoftPFReq accesses
1090system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.765434 # mshr miss rate for SoftPFReq accesses
1091system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.758934 # mshr miss rate for WriteLineReq accesses
1092system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.758934 # mshr miss rate for WriteLineReq accesses
1093system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063807 # mshr miss rate for LoadLockedReq accesses
1094system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063807 # mshr miss rate for LoadLockedReq accesses
1095system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.090621 # mshr miss rate for StoreCondReq accesses
1096system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.090621 # mshr miss rate for StoreCondReq accesses
1097system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028768 # mshr miss rate for demand accesses
1098system.cpu0.dcache.demand_mshr_miss_rate::total 0.028768 # mshr miss rate for demand accesses
1099system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032886 # mshr miss rate for overall accesses
1100system.cpu0.dcache.overall_mshr_miss_rate::total 0.032886 # mshr miss rate for overall accesses
1101system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16294.630250 # average ReadReq mshr miss latency
1102system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16294.630250 # average ReadReq mshr miss latency
1103system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24959.793053 # average WriteReq mshr miss latency
1104system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24959.793053 # average WriteReq mshr miss latency
1105system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26118.935076 # average SoftPFReq mshr miss latency
1106system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26118.935076 # average SoftPFReq mshr miss latency
1107system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 117380.889033 # average WriteLineReq mshr miss latency
1108system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 117380.889033 # average WriteLineReq mshr miss latency
1109system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14100.897245 # average LoadLockedReq mshr miss latency
1110system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14100.897245 # average LoadLockedReq mshr miss latency
1111system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23387.869991 # average StoreCondReq mshr miss latency
1112system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23387.869991 # average StoreCondReq mshr miss latency
1113system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
1114system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1115system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18970.443358 # average overall mshr miss latency
1116system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18970.443358 # average overall mshr miss latency
1117system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19900.408534 # average overall mshr miss latency
1118system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19900.408534 # average overall mshr miss latency
1119system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180630.324559 # average ReadReq mshr uncacheable latency
1120system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180630.324559 # average ReadReq mshr uncacheable latency
1121system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 177787.200254 # average WriteReq mshr uncacheable latency
1122system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 177787.200254 # average WriteReq mshr uncacheable latency
1123system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179219.205183 # average overall mshr uncacheable latency
1124system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179219.205183 # average overall mshr uncacheable latency
1125system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1126system.cpu0.icache.tags.replacements 6358728 # number of replacements
1127system.cpu0.icache.tags.tagsinuse 511.935177 # Cycle average of tags in use
1128system.cpu0.icache.tags.total_refs 223756411 # Total number of references to valid blocks.
1129system.cpu0.icache.tags.sampled_refs 6359240 # Sample count of references to valid blocks.
1130system.cpu0.icache.tags.avg_refs 35.186030 # Average number of references to valid blocks.
1131system.cpu0.icache.tags.warmup_cycle 22852216000 # Cycle when the warmup percentage was hit.
1132system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.935177 # Average occupied blocks per requestor
1133system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999873 # Average percentage of cache occupancy
1134system.cpu0.icache.tags.occ_percent::total 0.999873 # Average percentage of cache occupancy
1135system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1136system.cpu0.icache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id
1137system.cpu0.icache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id
1138system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1139system.cpu0.icache.tags.tag_accesses 467353436 # Number of tag accesses
1140system.cpu0.icache.tags.data_accesses 467353436 # Number of data accesses
1141system.cpu0.icache.ReadReq_hits::cpu0.inst 223756411 # number of ReadReq hits
1142system.cpu0.icache.ReadReq_hits::total 223756411 # number of ReadReq hits
1143system.cpu0.icache.demand_hits::cpu0.inst 223756411 # number of demand (read+write) hits
1144system.cpu0.icache.demand_hits::total 223756411 # number of demand (read+write) hits
1145system.cpu0.icache.overall_hits::cpu0.inst 223756411 # number of overall hits
1146system.cpu0.icache.overall_hits::total 223756411 # number of overall hits
1147system.cpu0.icache.ReadReq_misses::cpu0.inst 6740667 # number of ReadReq misses
1148system.cpu0.icache.ReadReq_misses::total 6740667 # number of ReadReq misses
1149system.cpu0.icache.demand_misses::cpu0.inst 6740667 # number of demand (read+write) misses
1150system.cpu0.icache.demand_misses::total 6740667 # number of demand (read+write) misses
1151system.cpu0.icache.overall_misses::cpu0.inst 6740667 # number of overall misses
1152system.cpu0.icache.overall_misses::total 6740667 # number of overall misses
1153system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 78361220616 # number of ReadReq miss cycles
1154system.cpu0.icache.ReadReq_miss_latency::total 78361220616 # number of ReadReq miss cycles
1155system.cpu0.icache.demand_miss_latency::cpu0.inst 78361220616 # number of demand (read+write) miss cycles
1156system.cpu0.icache.demand_miss_latency::total 78361220616 # number of demand (read+write) miss cycles
1157system.cpu0.icache.overall_miss_latency::cpu0.inst 78361220616 # number of overall miss cycles
1158system.cpu0.icache.overall_miss_latency::total 78361220616 # number of overall miss cycles
1159system.cpu0.icache.ReadReq_accesses::cpu0.inst 230497078 # number of ReadReq accesses(hits+misses)
1160system.cpu0.icache.ReadReq_accesses::total 230497078 # number of ReadReq accesses(hits+misses)
1161system.cpu0.icache.demand_accesses::cpu0.inst 230497078 # number of demand (read+write) accesses
1162system.cpu0.icache.demand_accesses::total 230497078 # number of demand (read+write) accesses
1163system.cpu0.icache.overall_accesses::cpu0.inst 230497078 # number of overall (read+write) accesses
1164system.cpu0.icache.overall_accesses::total 230497078 # number of overall (read+write) accesses
1165system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029244 # miss rate for ReadReq accesses
1166system.cpu0.icache.ReadReq_miss_rate::total 0.029244 # miss rate for ReadReq accesses
1167system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029244 # miss rate for demand accesses
1168system.cpu0.icache.demand_miss_rate::total 0.029244 # miss rate for demand accesses
1169system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029244 # miss rate for overall accesses
1170system.cpu0.icache.overall_miss_rate::total 0.029244 # miss rate for overall accesses
1171system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11625.143419 # average ReadReq miss latency
1172system.cpu0.icache.ReadReq_avg_miss_latency::total 11625.143419 # average ReadReq miss latency
1173system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11625.143419 # average overall miss latency
1174system.cpu0.icache.demand_avg_miss_latency::total 11625.143419 # average overall miss latency
1175system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11625.143419 # average overall miss latency
1176system.cpu0.icache.overall_avg_miss_latency::total 11625.143419 # average overall miss latency
1177system.cpu0.icache.blocked_cycles::no_mshrs 12527067 # number of cycles access was blocked
1178system.cpu0.icache.blocked_cycles::no_targets 1547 # number of cycles access was blocked
1179system.cpu0.icache.blocked::no_mshrs 814769 # number of cycles access was blocked
1180system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked
1181system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.374992 # average number of cycles each access was blocked
1182system.cpu0.icache.avg_blocked_cycles::no_targets 119 # average number of cycles each access was blocked
1183system.cpu0.icache.fast_writes 0 # number of fast writes performed
1184system.cpu0.icache.cache_copies 0 # number of cache copies performed
1185system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 381387 # number of ReadReq MSHR hits
1186system.cpu0.icache.ReadReq_mshr_hits::total 381387 # number of ReadReq MSHR hits
1187system.cpu0.icache.demand_mshr_hits::cpu0.inst 381387 # number of demand (read+write) MSHR hits
1188system.cpu0.icache.demand_mshr_hits::total 381387 # number of demand (read+write) MSHR hits
1189system.cpu0.icache.overall_mshr_hits::cpu0.inst 381387 # number of overall MSHR hits
1190system.cpu0.icache.overall_mshr_hits::total 381387 # number of overall MSHR hits
1191system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6359280 # number of ReadReq MSHR misses
1192system.cpu0.icache.ReadReq_mshr_misses::total 6359280 # number of ReadReq MSHR misses
1193system.cpu0.icache.demand_mshr_misses::cpu0.inst 6359280 # number of demand (read+write) MSHR misses
1194system.cpu0.icache.demand_mshr_misses::total 6359280 # number of demand (read+write) MSHR misses
1195system.cpu0.icache.overall_mshr_misses::cpu0.inst 6359280 # number of overall MSHR misses
1196system.cpu0.icache.overall_mshr_misses::total 6359280 # number of overall MSHR misses
1197system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable
1198system.cpu0.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable
1199system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses
1200system.cpu0.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses
1201system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 70398317173 # number of ReadReq MSHR miss cycles
1202system.cpu0.icache.ReadReq_mshr_miss_latency::total 70398317173 # number of ReadReq MSHR miss cycles
1203system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 70398317173 # number of demand (read+write) MSHR miss cycles
1204system.cpu0.icache.demand_mshr_miss_latency::total 70398317173 # number of demand (read+write) MSHR miss cycles
1205system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 70398317173 # number of overall MSHR miss cycles
1206system.cpu0.icache.overall_mshr_miss_latency::total 70398317173 # number of overall MSHR miss cycles
1207system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939725498 # number of ReadReq MSHR uncacheable cycles
1208system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939725498 # number of ReadReq MSHR uncacheable cycles
1209system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939725498 # number of overall MSHR uncacheable cycles
1210system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939725498 # number of overall MSHR uncacheable cycles
1211system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027589 # mshr miss rate for ReadReq accesses
1212system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027589 # mshr miss rate for ReadReq accesses
1213system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027589 # mshr miss rate for demand accesses
1214system.cpu0.icache.demand_mshr_miss_rate::total 0.027589 # mshr miss rate for demand accesses
1215system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027589 # mshr miss rate for overall accesses
1216system.cpu0.icache.overall_mshr_miss_rate::total 0.027589 # mshr miss rate for overall accesses
1217system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11070.171021 # average ReadReq mshr miss latency
1218system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11070.171021 # average ReadReq mshr miss latency
1219system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11070.171021 # average overall mshr miss latency
1220system.cpu0.icache.demand_avg_mshr_miss_latency::total 11070.171021 # average overall mshr miss latency
1221system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11070.171021 # average overall mshr miss latency
1222system.cpu0.icache.overall_avg_mshr_miss_latency::total 11070.171021 # average overall mshr miss latency
1223system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138054.170095 # average ReadReq mshr uncacheable latency
1224system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138054.170095 # average ReadReq mshr uncacheable latency
1225system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138054.170095 # average overall mshr uncacheable latency
1226system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138054.170095 # average overall mshr uncacheable latency
1227system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1228system.cpu0.l2cache.prefetcher.num_hwpf_issued 8863203 # number of hwpf issued
1229system.cpu0.l2cache.prefetcher.pfIdentified 8872058 # number of prefetch candidates identified
1230system.cpu0.l2cache.prefetcher.pfBufferHit 7949 # number of redundant prefetches already in prefetch queue
1231system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1232system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1233system.cpu0.l2cache.prefetcher.pfSpanPage 1112734 # number of prefetches not generated due to page crossing
1234system.cpu0.l2cache.tags.replacements 2914685 # number of replacements
1235system.cpu0.l2cache.tags.tagsinuse 16233.717637 # Cycle average of tags in use
1236system.cpu0.l2cache.tags.total_refs 21584031 # Total number of references to valid blocks.
1237system.cpu0.l2cache.tags.sampled_refs 2930348 # Sample count of references to valid blocks.
1238system.cpu0.l2cache.tags.avg_refs 7.365689 # Average number of references to valid blocks.
1239system.cpu0.l2cache.tags.warmup_cycle 21271828500 # Cycle when the warmup percentage was hit.
1240system.cpu0.l2cache.tags.occ_blocks::writebacks 7511.186177 # Average occupied blocks per requestor
1241system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 88.364339 # Average occupied blocks per requestor
1242system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 96.668630 # Average occupied blocks per requestor
1243system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4222.815045 # Average occupied blocks per requestor
1244system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3387.843530 # Average occupied blocks per requestor
1245system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 926.839916 # Average occupied blocks per requestor
1246system.cpu0.l2cache.tags.occ_percent::writebacks 0.458446 # Average percentage of cache occupancy
1247system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.005393 # Average percentage of cache occupancy
1248system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005900 # Average percentage of cache occupancy
1249system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.257740 # Average percentage of cache occupancy
1250system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.206778 # Average percentage of cache occupancy
1251system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056570 # Average percentage of cache occupancy
1252system.cpu0.l2cache.tags.occ_percent::total 0.990827 # Average percentage of cache occupancy
1253system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1335 # Occupied blocks per task id
1254system.cpu0.l2cache.tags.occ_task_id_blocks::1023 99 # Occupied blocks per task id
1255system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14229 # Occupied blocks per task id
1256system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 95 # Occupied blocks per task id
1257system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 255 # Occupied blocks per task id
1258system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 575 # Occupied blocks per task id
1259system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 410 # Occupied blocks per task id
1260system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 6 # Occupied blocks per task id
1261system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 74 # Occupied blocks per task id
1262system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id
1263system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id
1264system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 796 # Occupied blocks per task id
1265system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4905 # Occupied blocks per task id
1266system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4871 # Occupied blocks per task id
1267system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3657 # Occupied blocks per task id
1268system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.081482 # Percentage of cache occupancy per task id
1269system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006042 # Percentage of cache occupancy per task id
1270system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.868469 # Percentage of cache occupancy per task id
1271system.cpu0.l2cache.tags.tag_accesses 436831326 # Number of tag accesses
1272system.cpu0.l2cache.tags.data_accesses 436831326 # Number of data accesses
1273system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 607592 # number of ReadReq hits
1274system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 191548 # number of ReadReq hits
1275system.cpu0.l2cache.ReadReq_hits::total 799140 # number of ReadReq hits
1276system.cpu0.l2cache.Writeback_hits::writebacks 4324517 # number of Writeback hits
1277system.cpu0.l2cache.Writeback_hits::total 4324517 # number of Writeback hits
1278system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 114203 # number of UpgradeReq hits
1279system.cpu0.l2cache.UpgradeReq_hits::total 114203 # number of UpgradeReq hits
1280system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 36958 # number of SCUpgradeReq hits
1281system.cpu0.l2cache.SCUpgradeReq_hits::total 36958 # number of SCUpgradeReq hits
1282system.cpu0.l2cache.ReadExReq_hits::cpu0.data 970189 # number of ReadExReq hits
1283system.cpu0.l2cache.ReadExReq_hits::total 970189 # number of ReadExReq hits
1284system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5673182 # number of ReadCleanReq hits
1285system.cpu0.l2cache.ReadCleanReq_hits::total 5673182 # number of ReadCleanReq hits
1286system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3273926 # number of ReadSharedReq hits
1287system.cpu0.l2cache.ReadSharedReq_hits::total 3273926 # number of ReadSharedReq hits
1288system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 211331 # number of InvalidateReq hits
1289system.cpu0.l2cache.InvalidateReq_hits::total 211331 # number of InvalidateReq hits
1290system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 607592 # number of demand (read+write) hits
1291system.cpu0.l2cache.demand_hits::cpu0.itb.walker 191548 # number of demand (read+write) hits
1292system.cpu0.l2cache.demand_hits::cpu0.inst 5673182 # number of demand (read+write) hits
1293system.cpu0.l2cache.demand_hits::cpu0.data 4244115 # number of demand (read+write) hits
1294system.cpu0.l2cache.demand_hits::total 10716437 # number of demand (read+write) hits
1295system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 607592 # number of overall hits
1296system.cpu0.l2cache.overall_hits::cpu0.itb.walker 191548 # number of overall hits
1297system.cpu0.l2cache.overall_hits::cpu0.inst 5673182 # number of overall hits
1298system.cpu0.l2cache.overall_hits::cpu0.data 4244115 # number of overall hits
1299system.cpu0.l2cache.overall_hits::total 10716437 # number of overall hits
1300system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13844 # number of ReadReq misses
1301system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10570 # number of ReadReq misses
1302system.cpu0.l2cache.ReadReq_misses::total 24414 # number of ReadReq misses
1303system.cpu0.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses
1304system.cpu0.l2cache.Writeback_misses::total 2 # number of Writeback misses
1305system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 138430 # number of UpgradeReq misses
1306system.cpu0.l2cache.UpgradeReq_misses::total 138430 # number of UpgradeReq misses
1307system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158345 # number of SCUpgradeReq misses
1308system.cpu0.l2cache.SCUpgradeReq_misses::total 158345 # number of SCUpgradeReq misses
1309system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses
1310system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses
1311system.cpu0.l2cache.ReadExReq_misses::cpu0.data 344034 # number of ReadExReq misses
1312system.cpu0.l2cache.ReadExReq_misses::total 344034 # number of ReadExReq misses
1313system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 686063 # number of ReadCleanReq misses
1314system.cpu0.l2cache.ReadCleanReq_misses::total 686063 # number of ReadCleanReq misses
1315system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1100006 # number of ReadSharedReq misses
1316system.cpu0.l2cache.ReadSharedReq_misses::total 1100006 # number of ReadSharedReq misses
1317system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 624163 # number of InvalidateReq misses
1318system.cpu0.l2cache.InvalidateReq_misses::total 624163 # number of InvalidateReq misses
1319system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13844 # number of demand (read+write) misses
1320system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10570 # number of demand (read+write) misses
1321system.cpu0.l2cache.demand_misses::cpu0.inst 686063 # number of demand (read+write) misses
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1333system.cpu0.l2cache.UpgradeReq_miss_latency::total 4320468000 # number of UpgradeReq miss cycles
1334system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3850233000 # number of SCUpgradeReq miss cycles
1335system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3850233000 # number of SCUpgradeReq miss cycles
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1343system.cpu0.l2cache.ReadSharedReq_miss_latency::total 50121323488 # number of ReadSharedReq miss cycles
1344system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 94690450497 # number of InvalidateReq miss cycles
1345system.cpu0.l2cache.InvalidateReq_miss_latency::total 94690450497 # number of InvalidateReq miss cycles
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1358system.cpu0.l2cache.ReadReq_accesses::total 823554 # number of ReadReq accesses(hits+misses)
1359system.cpu0.l2cache.Writeback_accesses::writebacks 4324519 # number of Writeback accesses(hits+misses)
1360system.cpu0.l2cache.Writeback_accesses::total 4324519 # number of Writeback accesses(hits+misses)
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1362system.cpu0.l2cache.UpgradeReq_accesses::total 252633 # number of UpgradeReq accesses(hits+misses)
1363system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 195303 # number of SCUpgradeReq accesses(hits+misses)
1364system.cpu0.l2cache.SCUpgradeReq_accesses::total 195303 # number of SCUpgradeReq accesses(hits+misses)
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1366system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses)
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1370system.cpu0.l2cache.ReadCleanReq_accesses::total 6359245 # number of ReadCleanReq accesses(hits+misses)
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1372system.cpu0.l2cache.ReadSharedReq_accesses::total 4373932 # number of ReadSharedReq accesses(hits+misses)
1373system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 835494 # number of InvalidateReq accesses(hits+misses)
1374system.cpu0.l2cache.InvalidateReq_accesses::total 835494 # number of InvalidateReq accesses(hits+misses)
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1381system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 202118 # number of overall (read+write) accesses
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1386system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052296 # miss rate for ReadReq accesses
1387system.cpu0.l2cache.ReadReq_miss_rate::total 0.029645 # miss rate for ReadReq accesses
1388system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses
1389system.cpu0.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses
1390system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.547949 # miss rate for UpgradeReq accesses
1391system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.547949 # miss rate for UpgradeReq accesses
1392system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.810766 # miss rate for SCUpgradeReq accesses
1393system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.810766 # miss rate for SCUpgradeReq accesses
1394system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1395system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1396system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.261777 # miss rate for ReadExReq accesses
1397system.cpu0.l2cache.ReadExReq_miss_rate::total 0.261777 # miss rate for ReadExReq accesses
1398system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.107884 # miss rate for ReadCleanReq accesses
1399system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.107884 # miss rate for ReadCleanReq accesses
1400system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.251491 # miss rate for ReadSharedReq accesses
1401system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.251491 # miss rate for ReadSharedReq accesses
1402system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.747059 # miss rate for InvalidateReq accesses
1403system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.747059 # miss rate for InvalidateReq accesses
1404system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022277 # miss rate for demand accesses
1405system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052296 # miss rate for demand accesses
1406system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.107884 # miss rate for demand accesses
1407system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.253868 # miss rate for demand accesses
1408system.cpu0.l2cache.demand_miss_rate::total 0.167394 # miss rate for demand accesses
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1410system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052296 # miss rate for overall accesses
1411system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.107884 # miss rate for overall accesses
1412system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.253868 # miss rate for overall accesses
1413system.cpu0.l2cache.overall_miss_rate::total 0.167394 # miss rate for overall accesses
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1415system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 62203.500473 # average ReadReq miss latency
1416system.cpu0.l2cache.ReadReq_avg_miss_latency::total 57533.484886 # average ReadReq miss latency
1417system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 31210.489056 # average UpgradeReq miss latency
1418system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 31210.489056 # average UpgradeReq miss latency
1419system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 24315.469386 # average SCUpgradeReq miss latency
1420system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 24315.469386 # average SCUpgradeReq miss latency
1421system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 807666.666667 # average SCUpgradeFailReq miss latency
1422system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 807666.666667 # average SCUpgradeFailReq miss latency
1423system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 67145.122276 # average ReadExReq miss latency
1424system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 67145.122276 # average ReadExReq miss latency
1425system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39413.242658 # average ReadCleanReq miss latency
1426system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39413.242658 # average ReadCleanReq miss latency
1427system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 45564.591000 # average ReadSharedReq miss latency
1428system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 45564.591000 # average ReadSharedReq miss latency
1429system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 151707.887999 # average InvalidateReq miss latency
1430system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 151707.887999 # average InvalidateReq miss latency
1431system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 53967.892228 # average overall miss latency
1432system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 62203.500473 # average overall miss latency
1433system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39413.242658 # average overall miss latency
1434system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 50706.025100 # average overall miss latency
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1436system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 53967.892228 # average overall miss latency
1437system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 62203.500473 # average overall miss latency
1438system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39413.242658 # average overall miss latency
1439system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 50706.025100 # average overall miss latency
1440system.cpu0.l2cache.overall_avg_miss_latency::total 47187.429240 # average overall miss latency
1441system.cpu0.l2cache.blocked_cycles::no_mshrs 4612 # number of cycles access was blocked
1442system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1443system.cpu0.l2cache.blocked::no_mshrs 22 # number of cycles access was blocked
1444system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1445system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 209.636364 # average number of cycles each access was blocked
1446system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1447system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1448system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1449system.cpu0.l2cache.writebacks::writebacks 1594853 # number of writebacks
1450system.cpu0.l2cache.writebacks::total 1594853 # number of writebacks
1451system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 7 # number of ReadReq MSHR hits
1452system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 173 # number of ReadReq MSHR hits
1453system.cpu0.l2cache.ReadReq_mshr_hits::total 180 # number of ReadReq MSHR hits
1454system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 69770 # number of ReadExReq MSHR hits
1455system.cpu0.l2cache.ReadExReq_mshr_hits::total 69770 # number of ReadExReq MSHR hits
1456system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 3 # number of ReadCleanReq MSHR hits
1457system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits
1458system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 7585 # number of ReadSharedReq MSHR hits
1459system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 7585 # number of ReadSharedReq MSHR hits
1460system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 3 # number of InvalidateReq MSHR hits
1461system.cpu0.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits
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1468system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 173 # number of overall MSHR hits
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1475system.cpu0.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses
1476system.cpu0.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses
1477system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 119189 # number of CleanEvict MSHR misses
1478system.cpu0.l2cache.CleanEvict_mshr_misses::total 119189 # number of CleanEvict MSHR misses
1479system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 853540 # number of HardPFReq MSHR misses
1480system.cpu0.l2cache.HardPFReq_mshr_misses::total 853540 # number of HardPFReq MSHR misses
1481system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 138430 # number of UpgradeReq MSHR misses
1482system.cpu0.l2cache.UpgradeReq_mshr_misses::total 138430 # number of UpgradeReq MSHR misses
1483system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 158345 # number of SCUpgradeReq MSHR misses
1484system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 158345 # number of SCUpgradeReq MSHR misses
1485system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses
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1490system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 686060 # number of ReadCleanReq MSHR misses
1491system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1092421 # number of ReadSharedReq MSHR misses
1492system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1092421 # number of ReadSharedReq MSHR misses
1493system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 624160 # number of InvalidateReq MSHR misses
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1495system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 13837 # number of demand (read+write) MSHR misses
1496system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10397 # number of demand (read+write) MSHR misses
1497system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 686060 # number of demand (read+write) MSHR misses
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1500system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 13837 # number of overall MSHR misses
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1505system.cpu0.l2cache.overall_mshr_misses::total 2930519 # number of overall MSHR misses
1506system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable
1507system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31951 # number of ReadReq MSHR uncacheable
1508system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 53245 # number of ReadReq MSHR uncacheable
1509system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31485 # number of WriteReq MSHR uncacheable
1510system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31485 # number of WriteReq MSHR uncacheable
1511system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses
1512system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 63436 # number of overall MSHR uncacheable misses
1513system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 84730 # number of overall MSHR uncacheable misses
1514system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 663983000 # number of ReadReq MSHR miss cycles
1515system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 585367500 # number of ReadReq MSHR miss cycles
1516system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1249350500 # number of ReadReq MSHR miss cycles
1517system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 68949295019 # number of HardPFReq MSHR miss cycles
1518system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 68949295019 # number of HardPFReq MSHR miss cycles
1519system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4907856994 # number of UpgradeReq MSHR miss cycles
1520system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4907856994 # number of UpgradeReq MSHR miss cycles
1521system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3084199996 # number of SCUpgradeReq MSHR miss cycles
1522system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3084199996 # number of SCUpgradeReq MSHR miss cycles
1523system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4498000 # number of SCUpgradeFailReq MSHR miss cycles
1524system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4498000 # number of SCUpgradeFailReq MSHR miss cycles
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1526system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 17239432497 # number of ReadExReq MSHR miss cycles
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1528system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 22923448498 # number of ReadCleanReq MSHR miss cycles
1529system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 43011997988 # number of ReadSharedReq MSHR miss cycles
1530system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 43011997988 # number of ReadSharedReq MSHR miss cycles
1531system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 90945024497 # number of InvalidateReq MSHR miss cycles
1532system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 90945024497 # number of InvalidateReq MSHR miss cycles
1533system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 663983000 # number of demand (read+write) MSHR miss cycles
1534system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 585367500 # number of demand (read+write) MSHR miss cycles
1535system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 22923448498 # number of demand (read+write) MSHR miss cycles
1536system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 60251430485 # number of demand (read+write) MSHR miss cycles
1537system.cpu0.l2cache.demand_mshr_miss_latency::total 84424229483 # number of demand (read+write) MSHR miss cycles
1538system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 663983000 # number of overall MSHR miss cycles
1539system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 585367500 # number of overall MSHR miss cycles
1540system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 22923448498 # number of overall MSHR miss cycles
1541system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 60251430485 # number of overall MSHR miss cycles
1542system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 68949295019 # number of overall MSHR miss cycles
1543system.cpu0.l2cache.overall_mshr_miss_latency::total 153373524502 # number of overall MSHR miss cycles
1544system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780019500 # number of ReadReq MSHR uncacheable cycles
1545system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5515655500 # number of ReadReq MSHR uncacheable cycles
1546system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8295675000 # number of ReadReq MSHR uncacheable cycles
1547system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5356039467 # number of WriteReq MSHR uncacheable cycles
1548system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5356039467 # number of WriteReq MSHR uncacheable cycles
1549system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 2780019500 # number of overall MSHR uncacheable cycles
1550system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10871694967 # number of overall MSHR uncacheable cycles
1551system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 13651714467 # number of overall MSHR uncacheable cycles
1552system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022266 # mshr miss rate for ReadReq accesses
1553system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.051440 # mshr miss rate for ReadReq accesses
1554system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.029426 # mshr miss rate for ReadReq accesses
1555system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses
1556system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses
1557system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1558system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1559system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1560system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1561system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.547949 # mshr miss rate for UpgradeReq accesses
1562system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.547949 # mshr miss rate for UpgradeReq accesses
1563system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.810766 # mshr miss rate for SCUpgradeReq accesses
1564system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.810766 # mshr miss rate for SCUpgradeReq accesses
1565system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1566system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1567system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.208689 # mshr miss rate for ReadExReq accesses
1568system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.208689 # mshr miss rate for ReadExReq accesses
1569system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.107884 # mshr miss rate for ReadCleanReq accesses
1570system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.107884 # mshr miss rate for ReadCleanReq accesses
1571system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.249757 # mshr miss rate for ReadSharedReq accesses
1572system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249757 # mshr miss rate for ReadSharedReq accesses
1573system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.747055 # mshr miss rate for InvalidateReq accesses
1574system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.747055 # mshr miss rate for InvalidateReq accesses
1575system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022266 # mshr miss rate for demand accesses
1576system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.051440 # mshr miss rate for demand accesses
1577system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.107884 # mshr miss rate for demand accesses
1578system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240269 # mshr miss rate for demand accesses
1579system.cpu0.l2cache.demand_mshr_miss_rate::total 0.161369 # mshr miss rate for demand accesses
1580system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022266 # mshr miss rate for overall accesses
1581system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.051440 # mshr miss rate for overall accesses
1582system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.107884 # mshr miss rate for overall accesses
1583system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240269 # mshr miss rate for overall accesses
1584system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1585system.cpu0.l2cache.overall_mshr_miss_rate::total 0.227685 # mshr miss rate for overall accesses
1586system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 47986.051890 # average ReadReq mshr miss latency
1587system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 56301.577378 # average ReadReq mshr miss latency
1588system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 51553.623009 # average ReadReq mshr miss latency
1589system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80780.391099 # average HardPFReq mshr miss latency
1590system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 80780.391099 # average HardPFReq mshr miss latency
1591system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35453.709413 # average UpgradeReq mshr miss latency
1592system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35453.709413 # average UpgradeReq mshr miss latency
1593system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19477.722669 # average SCUpgradeReq mshr miss latency
1594system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19477.722669 # average SCUpgradeReq mshr miss latency
1595system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 749666.666667 # average SCUpgradeFailReq mshr miss latency
1596system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 749666.666667 # average SCUpgradeFailReq mshr miss latency
1597system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62857.073830 # average ReadExReq mshr miss latency
1598system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62857.073830 # average ReadExReq mshr miss latency
1599system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33413.183246 # average ReadCleanReq mshr miss latency
1600system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33413.183246 # average ReadCleanReq mshr miss latency
1601system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39373.096991 # average ReadSharedReq mshr miss latency
1602system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39373.096991 # average ReadSharedReq mshr miss latency
1603system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145707.870573 # average InvalidateReq mshr miss latency
1604system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145707.870573 # average InvalidateReq mshr miss latency
1605system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 47986.051890 # average overall mshr miss latency
1606system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 56301.577378 # average overall mshr miss latency
1607system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33413.183246 # average overall mshr miss latency
1608system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 44085.821155 # average overall mshr miss latency
1609system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40647.608610 # average overall mshr miss latency
1610system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 47986.051890 # average overall mshr miss latency
1611system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 56301.577378 # average overall mshr miss latency
1612system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33413.183246 # average overall mshr miss latency
1613system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 44085.821155 # average overall mshr miss latency
1614system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80780.391099 # average overall mshr miss latency
1615system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52336.642247 # average overall mshr miss latency
1616system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130554.123227 # average ReadReq mshr uncacheable latency
1617system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172628.571876 # average ReadReq mshr uncacheable latency
1618system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 155801.953235 # average ReadReq mshr uncacheable latency
1619system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170114.005622 # average WriteReq mshr uncacheable latency
1620system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 170114.005622 # average WriteReq mshr uncacheable latency
1621system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130554.123227 # average overall mshr uncacheable latency
1622system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 171380.524734 # average overall mshr uncacheable latency
1623system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 161120.199068 # average overall mshr uncacheable latency
1624system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1625system.cpu0.toL2Bus.snoop_filter.tot_requests 26498119 # Total number of requests made to the snoop filter.
1626system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13615382 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1627system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2337 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1628system.cpu0.toL2Bus.snoop_filter.tot_snoops 550917 # Total number of snoops made to the snoop filter.
1629system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 550892 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1630system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 25 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1631system.cpu0.toL2Bus.trans_dist::ReadReq 1014324 # Transaction distribution
1632system.cpu0.toL2Bus.trans_dist::ReadResp 11851775 # Transaction distribution
1633system.cpu0.toL2Bus.trans_dist::WriteReq 31486 # Transaction distribution
1634system.cpu0.toL2Bus.trans_dist::WriteResp 31485 # Transaction distribution
1635system.cpu0.toL2Bus.trans_dist::Writeback 5956604 # Transaction distribution
1636system.cpu0.toL2Bus.trans_dist::CleanEvict 10410037 # Transaction distribution
1637system.cpu0.toL2Bus.trans_dist::HardPFReq 1088232 # Transaction distribution
1638system.cpu0.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution
1639system.cpu0.toL2Bus.trans_dist::UpgradeReq 474368 # Transaction distribution
1640system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 351600 # Transaction distribution
1641system.cpu0.toL2Bus.trans_dist::UpgradeResp 519661 # Transaction distribution
1642system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution
1643system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution
1644system.cpu0.toL2Bus.trans_dist::ReadExReq 1396851 # Transaction distribution
1645system.cpu0.toL2Bus.trans_dist::ReadExResp 1324661 # Transaction distribution
1646system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6359280 # Transaction distribution
1647system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5366614 # Transaction distribution
1648system.cpu0.toL2Bus.trans_dist::InvalidateReq 842272 # Transaction distribution
1649system.cpu0.toL2Bus.trans_dist::InvalidateResp 835494 # Transaction distribution
1650system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19118379 # Packet count per connected master and slave (bytes)
1651system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20677259 # Packet count per connected master and slave (bytes)
1652system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 436050 # Packet count per connected master and slave (bytes)
1653system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1348581 # Packet count per connected master and slave (bytes)
1654system.cpu0.toL2Bus.pkt_count::total 41580269 # Packet count per connected master and slave (bytes)
1655system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 407332384 # Cumulative packet size per connected master and slave (bytes)
1656system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 648350241 # Cumulative packet size per connected master and slave (bytes)
1657system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1616944 # Cumulative packet size per connected master and slave (bytes)
1658system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4971488 # Cumulative packet size per connected master and slave (bytes)
1659system.cpu0.toL2Bus.pkt_size::total 1062271057 # Cumulative packet size per connected master and slave (bytes)
1660system.cpu0.toL2Bus.snoops 6461178 # Total snoops (count)
1661system.cpu0.toL2Bus.snoop_fanout::samples 33294085 # Request fanout histogram
1662system.cpu0.toL2Bus.snoop_fanout::mean 0.028312 # Request fanout histogram
1663system.cpu0.toL2Bus.snoop_fanout::stdev 0.165866 # Request fanout histogram
1664system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1665system.cpu0.toL2Bus.snoop_fanout::0 32351497 97.17% 97.17% # Request fanout histogram
1666system.cpu0.toL2Bus.snoop_fanout::1 942563 2.83% 100.00% # Request fanout histogram
1667system.cpu0.toL2Bus.snoop_fanout::2 25 0.00% 100.00% # Request fanout histogram
1668system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1669system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1670system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1671system.cpu0.toL2Bus.snoop_fanout::total 33294085 # Request fanout histogram
1672system.cpu0.toL2Bus.reqLayer0.occupancy 17918792438 # Layer occupancy (ticks)
1673system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1674system.cpu0.toL2Bus.snoopLayer0.occupancy 208202715 # Layer occupancy (ticks)
1675system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1676system.cpu0.toL2Bus.respLayer0.occupancy 9565441520 # Layer occupancy (ticks)
1677system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1678system.cpu0.toL2Bus.respLayer1.occupancy 9227310290 # Layer occupancy (ticks)
1679system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1680system.cpu0.toL2Bus.respLayer2.occupancy 234328206 # Layer occupancy (ticks)
1681system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1682system.cpu0.toL2Bus.respLayer3.occupancy 727701378 # Layer occupancy (ticks)
1683system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1684system.cpu1.branchPred.lookups 122053066 # Number of BP lookups
1685system.cpu1.branchPred.condPredicted 81331643 # Number of conditional branches predicted
1686system.cpu1.branchPred.condIncorrect 6140345 # Number of conditional branches incorrect
1687system.cpu1.branchPred.BTBLookups 85523370 # Number of BTB lookups
1688system.cpu1.branchPred.BTBHits 55672017 # Number of BTB hits
1689system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1690system.cpu1.branchPred.BTBHitPct 65.095677 # BTB Hit Percentage
1691system.cpu1.branchPred.usedRAS 16431061 # Number of times the RAS was used to get a target.
1692system.cpu1.branchPred.RASInCorrect 166790 # Number of incorrect RAS predictions.
1693system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1694system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1695system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1696system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1697system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1698system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1699system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1700system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

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1714system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1715system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1716system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1717system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1718system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1719system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1720system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1721system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1722system.cpu1.dtb.walker.walks 513343 # Table walker walks requested
1723system.cpu1.dtb.walker.walksLong 513343 # Table walker walks initiated with long descriptors
1724system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10145 # Level at which table walker walks with long descriptors terminate
1725system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80504 # Level at which table walker walks with long descriptors terminate
1726system.cpu1.dtb.walker.walksSquashedBefore 231589 # Table walks squashed before starting
1727system.cpu1.dtb.walker.walkWaitTime::samples 281754 # Table walker wait (enqueue to first request) latency
1728system.cpu1.dtb.walker.walkWaitTime::mean 2191.677847 # Table walker wait (enqueue to first request) latency
1729system.cpu1.dtb.walker.walkWaitTime::stdev 13834.020871 # Table walker wait (enqueue to first request) latency
1730system.cpu1.dtb.walker.walkWaitTime::0-65535 279857 99.33% 99.33% # Table walker wait (enqueue to first request) latency
1731system.cpu1.dtb.walker.walkWaitTime::65536-131071 1045 0.37% 99.70% # Table walker wait (enqueue to first request) latency
1732system.cpu1.dtb.walker.walkWaitTime::131072-196607 593 0.21% 99.91% # Table walker wait (enqueue to first request) latency
1733system.cpu1.dtb.walker.walkWaitTime::196608-262143 154 0.05% 99.96% # Table walker wait (enqueue to first request) latency
1734system.cpu1.dtb.walker.walkWaitTime::262144-327679 32 0.01% 99.97% # Table walker wait (enqueue to first request) latency
1735system.cpu1.dtb.walker.walkWaitTime::327680-393215 54 0.02% 99.99% # Table walker wait (enqueue to first request) latency
1736system.cpu1.dtb.walker.walkWaitTime::393216-458751 12 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1737system.cpu1.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1738system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1739system.cpu1.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1740system.cpu1.dtb.walker.walkWaitTime::total 281754 # Table walker wait (enqueue to first request) latency
1741system.cpu1.dtb.walker.walkCompletionTime::samples 256242 # Table walker service (enqueue to completion) latency
1742system.cpu1.dtb.walker.walkCompletionTime::mean 18411.043076 # Table walker service (enqueue to completion) latency
1743system.cpu1.dtb.walker.walkCompletionTime::gmean 15820.375131 # Table walker service (enqueue to completion) latency
1744system.cpu1.dtb.walker.walkCompletionTime::stdev 14815.596994 # Table walker service (enqueue to completion) latency
1745system.cpu1.dtb.walker.walkCompletionTime::0-65535 254819 99.44% 99.44% # Table walker service (enqueue to completion) latency
1746system.cpu1.dtb.walker.walkCompletionTime::65536-131071 556 0.22% 99.66% # Table walker service (enqueue to completion) latency
1747system.cpu1.dtb.walker.walkCompletionTime::131072-196607 633 0.25% 99.91% # Table walker service (enqueue to completion) latency
1748system.cpu1.dtb.walker.walkCompletionTime::196608-262143 56 0.02% 99.93% # Table walker service (enqueue to completion) latency
1749system.cpu1.dtb.walker.walkCompletionTime::262144-327679 78 0.03% 99.96% # Table walker service (enqueue to completion) latency
1750system.cpu1.dtb.walker.walkCompletionTime::327680-393215 63 0.02% 99.99% # Table walker service (enqueue to completion) latency
1751system.cpu1.dtb.walker.walkCompletionTime::393216-458751 21 0.01% 99.99% # Table walker service (enqueue to completion) latency
1752system.cpu1.dtb.walker.walkCompletionTime::458752-524287 9 0.00% 100.00% # Table walker service (enqueue to completion) latency
1753system.cpu1.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
1754system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1755system.cpu1.dtb.walker.walkCompletionTime::983040-1.04858e+06 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1756system.cpu1.dtb.walker.walkCompletionTime::total 256242 # Table walker service (enqueue to completion) latency
1757system.cpu1.dtb.walker.walksPending::samples 430767474576 # Table walker pending requests distribution
1758system.cpu1.dtb.walker.walksPending::mean 0.581742 # Table walker pending requests distribution
1759system.cpu1.dtb.walker.walksPending::stdev 0.547950 # Table walker pending requests distribution
1760system.cpu1.dtb.walker.walksPending::0-1 429773436576 99.77% 99.77% # Table walker pending requests distribution
1761system.cpu1.dtb.walker.walksPending::2-3 519356000 0.12% 99.89% # Table walker pending requests distribution
1762system.cpu1.dtb.walker.walksPending::4-5 211618500 0.05% 99.94% # Table walker pending requests distribution
1763system.cpu1.dtb.walker.walksPending::6-7 107822000 0.03% 99.96% # Table walker pending requests distribution
1764system.cpu1.dtb.walker.walksPending::8-9 75775500 0.02% 99.98% # Table walker pending requests distribution
1765system.cpu1.dtb.walker.walksPending::10-11 45293000 0.01% 99.99% # Table walker pending requests distribution
1766system.cpu1.dtb.walker.walksPending::12-13 13801500 0.00% 100.00% # Table walker pending requests distribution
1767system.cpu1.dtb.walker.walksPending::14-15 19976000 0.00% 100.00% # Table walker pending requests distribution
1768system.cpu1.dtb.walker.walksPending::16-17 394000 0.00% 100.00% # Table walker pending requests distribution
1769system.cpu1.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution
1770system.cpu1.dtb.walker.walksPending::total 430767474576 # Table walker pending requests distribution
1771system.cpu1.dtb.walker.walkPageSizes::4K 80504 88.81% 88.81% # Table walker page sizes translated
1772system.cpu1.dtb.walker.walkPageSizes::2M 10145 11.19% 100.00% # Table walker page sizes translated
1773system.cpu1.dtb.walker.walkPageSizes::total 90649 # Table walker page sizes translated
1774system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 513343 # Table walker requests started/completed, data/inst
1775system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1776system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 513343 # Table walker requests started/completed, data/inst
1777system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90649 # Table walker requests started/completed, data/inst
1778system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1779system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90649 # Table walker requests started/completed, data/inst
1780system.cpu1.dtb.walker.walkRequestOrigin::total 603992 # Table walker requests started/completed, data/inst
1781system.cpu1.dtb.inst_hits 0 # ITB inst hits
1782system.cpu1.dtb.inst_misses 0 # ITB inst misses
1783system.cpu1.dtb.read_hits 90392235 # DTB read hits
1784system.cpu1.dtb.read_misses 355030 # DTB read misses
1785system.cpu1.dtb.write_hits 74292452 # DTB write hits
1786system.cpu1.dtb.write_misses 158313 # DTB write misses
1787system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1788system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1789system.cpu1.dtb.flush_tlb_mva_asid 44087 # Number of times TLB was flushed by MVA & ASID
1790system.cpu1.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
1791system.cpu1.dtb.flush_entries 34737 # Number of entries that have been flushed from TLB
1792system.cpu1.dtb.align_faults 572 # Number of TLB faults due to alignment restrictions
1793system.cpu1.dtb.prefetch_faults 5833 # Number of TLB faults due to prefetch
1794system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1795system.cpu1.dtb.perms_faults 38175 # Number of TLB faults due to permissions restrictions
1796system.cpu1.dtb.read_accesses 90747265 # DTB read accesses
1797system.cpu1.dtb.write_accesses 74450765 # DTB write accesses
1798system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1799system.cpu1.dtb.hits 164684687 # DTB hits
1800system.cpu1.dtb.misses 513343 # DTB misses
1801system.cpu1.dtb.accesses 165198030 # DTB accesses
1802system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1803system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1804system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1805system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1806system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1807system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1808system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1809system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1823system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1824system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1825system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1826system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1827system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1828system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1829system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1830system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1831system.cpu1.itb.walker.walks 79836 # Table walker walks requested
1832system.cpu1.itb.walker.walksLong 79836 # Table walker walks initiated with long descriptors
1833system.cpu1.itb.walker.walksLongTerminationLevel::Level2 812 # Level at which table walker walks with long descriptors terminate
1834system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57876 # Level at which table walker walks with long descriptors terminate
1835system.cpu1.itb.walker.walksSquashedBefore 9466 # Table walks squashed before starting
1836system.cpu1.itb.walker.walkWaitTime::samples 70370 # Table walker wait (enqueue to first request) latency
1837system.cpu1.itb.walker.walkWaitTime::mean 1202.877647 # Table walker wait (enqueue to first request) latency
1838system.cpu1.itb.walker.walkWaitTime::stdev 9654.881733 # Table walker wait (enqueue to first request) latency
1839system.cpu1.itb.walker.walkWaitTime::0-65535 70178 99.73% 99.73% # Table walker wait (enqueue to first request) latency
1840system.cpu1.itb.walker.walkWaitTime::65536-131071 41 0.06% 99.79% # Table walker wait (enqueue to first request) latency
1841system.cpu1.itb.walker.walkWaitTime::131072-196607 131 0.19% 99.97% # Table walker wait (enqueue to first request) latency
1842system.cpu1.itb.walker.walkWaitTime::196608-262143 11 0.02% 99.99% # Table walker wait (enqueue to first request) latency
1843system.cpu1.itb.walker.walkWaitTime::262144-327679 7 0.01% 100.00% # Table walker wait (enqueue to first request) latency
1844system.cpu1.itb.walker.walkWaitTime::327680-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1845system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1846system.cpu1.itb.walker.walkWaitTime::total 70370 # Table walker wait (enqueue to first request) latency
1847system.cpu1.itb.walker.walkCompletionTime::samples 68154 # Table walker service (enqueue to completion) latency
1848system.cpu1.itb.walker.walkCompletionTime::mean 22918.860228 # Table walker service (enqueue to completion) latency
1849system.cpu1.itb.walker.walkCompletionTime::gmean 20570.604774 # Table walker service (enqueue to completion) latency
1850system.cpu1.itb.walker.walkCompletionTime::stdev 17513.278330 # Table walker service (enqueue to completion) latency
1851system.cpu1.itb.walker.walkCompletionTime::0-65535 67528 99.08% 99.08% # Table walker service (enqueue to completion) latency
1852system.cpu1.itb.walker.walkCompletionTime::65536-131071 75 0.11% 99.19% # Table walker service (enqueue to completion) latency
1853system.cpu1.itb.walker.walkCompletionTime::131072-196607 455 0.67% 99.86% # Table walker service (enqueue to completion) latency
1854system.cpu1.itb.walker.walkCompletionTime::196608-262143 42 0.06% 99.92% # Table walker service (enqueue to completion) latency
1855system.cpu1.itb.walker.walkCompletionTime::262144-327679 28 0.04% 99.96% # Table walker service (enqueue to completion) latency
1856system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.98% # Table walker service (enqueue to completion) latency
1857system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
1858system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1859system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1860system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1861system.cpu1.itb.walker.walkCompletionTime::total 68154 # Table walker service (enqueue to completion) latency
1862system.cpu1.itb.walker.walksPending::samples 396407660708 # Table walker pending requests distribution
1863system.cpu1.itb.walker.walksPending::mean 0.833666 # Table walker pending requests distribution
1864system.cpu1.itb.walker.walksPending::stdev 0.372525 # Table walker pending requests distribution
1865system.cpu1.itb.walker.walksPending::0 65955607768 16.64% 16.64% # Table walker pending requests distribution
1866system.cpu1.itb.walker.walksPending::1 330434317940 83.36% 100.00% # Table walker pending requests distribution
1867system.cpu1.itb.walker.walksPending::2 16293000 0.00% 100.00% # Table walker pending requests distribution
1868system.cpu1.itb.walker.walksPending::3 1234500 0.00% 100.00% # Table walker pending requests distribution
1869system.cpu1.itb.walker.walksPending::4 163500 0.00% 100.00% # Table walker pending requests distribution
1870system.cpu1.itb.walker.walksPending::5 44000 0.00% 100.00% # Table walker pending requests distribution
1871system.cpu1.itb.walker.walksPending::total 396407660708 # Table walker pending requests distribution
1872system.cpu1.itb.walker.walkPageSizes::4K 57876 98.62% 98.62% # Table walker page sizes translated
1873system.cpu1.itb.walker.walkPageSizes::2M 812 1.38% 100.00% # Table walker page sizes translated
1874system.cpu1.itb.walker.walkPageSizes::total 58688 # Table walker page sizes translated
1875system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1876system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 79836 # Table walker requests started/completed, data/inst
1877system.cpu1.itb.walker.walkRequestOrigin_Requested::total 79836 # Table walker requests started/completed, data/inst
1878system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1879system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58688 # Table walker requests started/completed, data/inst
1880system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58688 # Table walker requests started/completed, data/inst
1881system.cpu1.itb.walker.walkRequestOrigin::total 138524 # Table walker requests started/completed, data/inst
1882system.cpu1.itb.inst_hits 192024896 # ITB inst hits
1883system.cpu1.itb.inst_misses 79836 # ITB inst misses
1884system.cpu1.itb.read_hits 0 # DTB read hits
1885system.cpu1.itb.read_misses 0 # DTB read misses
1886system.cpu1.itb.write_hits 0 # DTB write hits
1887system.cpu1.itb.write_misses 0 # DTB write misses
1888system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1889system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1890system.cpu1.itb.flush_tlb_mva_asid 44087 # Number of times TLB was flushed by MVA & ASID
1891system.cpu1.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
1892system.cpu1.itb.flush_entries 24498 # Number of entries that have been flushed from TLB
1893system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1894system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1895system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1896system.cpu1.itb.perms_faults 203556 # Number of TLB faults due to permissions restrictions
1897system.cpu1.itb.read_accesses 0 # DTB read accesses
1898system.cpu1.itb.write_accesses 0 # DTB write accesses
1899system.cpu1.itb.inst_accesses 192104732 # ITB inst accesses
1900system.cpu1.itb.hits 192024896 # DTB hits
1901system.cpu1.itb.misses 79836 # DTB misses
1902system.cpu1.itb.accesses 192104732 # DTB accesses
1903system.cpu1.numCycles 663967264 # number of cpu cycles simulated
1904system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1905system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1906system.cpu1.fetch.icacheStallCycles 80600357 # Number of cycles fetch is stalled on an Icache miss
1907system.cpu1.fetch.Insts 540678400 # Number of instructions fetch has processed
1908system.cpu1.fetch.Branches 122053066 # Number of branches that fetch encountered
1909system.cpu1.fetch.predictedBranches 72103078 # Number of branches that fetch has predicted taken
1910system.cpu1.fetch.Cycles 547218750 # Number of cycles fetch has run and was not squashing or blocked
1911system.cpu1.fetch.SquashCycles 13194102 # Number of cycles fetch has spent squashing
1912system.cpu1.fetch.TlbCycles 1722175 # Number of cycles fetch has spent waiting for tlb
1913system.cpu1.fetch.MiscStallCycles 292741 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1914system.cpu1.fetch.PendingTrapStallCycles 5852987 # Number of stall cycles due to pending traps
1915system.cpu1.fetch.PendingQuiesceStallCycles 747163 # Number of stall cycles due to pending quiesce instructions
1916system.cpu1.fetch.IcacheWaitRetryStallCycles 786410 # Number of stall cycles due to full MSHR
1917system.cpu1.fetch.CacheLines 191800841 # Number of cache lines fetched
1918system.cpu1.fetch.IcacheSquashes 1580435 # Number of outstanding Icache misses that were squashed
1919system.cpu1.fetch.ItlbSquashes 27130 # Number of outstanding ITLB misses that were squashed
1920system.cpu1.fetch.rateDist::samples 643817634 # Number of instructions fetched each cycle (Total)
1921system.cpu1.fetch.rateDist::mean 0.987423 # Number of instructions fetched each cycle (Total)
1922system.cpu1.fetch.rateDist::stdev 1.222838 # Number of instructions fetched each cycle (Total)
1923system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1924system.cpu1.fetch.rateDist::0 339738489 52.77% 52.77% # Number of instructions fetched each cycle (Total)
1925system.cpu1.fetch.rateDist::1 118160249 18.35% 71.12% # Number of instructions fetched each cycle (Total)
1926system.cpu1.fetch.rateDist::2 40196713 6.24% 77.37% # Number of instructions fetched each cycle (Total)
1927system.cpu1.fetch.rateDist::3 145722183 22.63% 100.00% # Number of instructions fetched each cycle (Total)
1928system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1929system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1930system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
1931system.cpu1.fetch.rateDist::total 643817634 # Number of instructions fetched each cycle (Total)
1932system.cpu1.fetch.branchRate 0.183824 # Number of branch fetches per cycle
1933system.cpu1.fetch.rate 0.814315 # Number of inst fetches per cycle
1934system.cpu1.decode.IdleCycles 95925032 # Number of cycles decode is idle
1935system.cpu1.decode.BlockedCycles 307565159 # Number of cycles decode is blocked
1936system.cpu1.decode.RunCycles 202328162 # Number of cycles decode is running
1937system.cpu1.decode.UnblockCycles 33349835 # Number of cycles decode is unblocking
1938system.cpu1.decode.SquashCycles 4649446 # Number of cycles decode is squashing
1939system.cpu1.decode.BranchResolved 17381659 # Number of times decode resolved a branch
1940system.cpu1.decode.BranchMispred 1984856 # Number of times decode detected a branch misprediction
1941system.cpu1.decode.DecodedInsts 561624259 # Number of instructions handled by decode
1942system.cpu1.decode.SquashedInsts 21210320 # Number of squashed instructions handled by decode
1943system.cpu1.rename.SquashCycles 4649446 # Number of cycles rename is squashing
1944system.cpu1.rename.IdleCycles 127605464 # Number of cycles rename is idle
1945system.cpu1.rename.BlockCycles 43917048 # Number of cycles rename is blocking
1946system.cpu1.rename.serializeStallCycles 205458777 # count of cycles rename stalled for serializing inst
1947system.cpu1.rename.RunCycles 203595973 # Number of cycles rename is running
1948system.cpu1.rename.UnblockCycles 58590926 # Number of cycles rename is unblocking
1949system.cpu1.rename.RenamedInsts 546425758 # Number of instructions processed by rename
1950system.cpu1.rename.SquashedInsts 5335623 # Number of squashed instructions processed by rename
1951system.cpu1.rename.ROBFullEvents 9251054 # Number of times rename has blocked due to ROB full
1952system.cpu1.rename.IQFullEvents 227617 # Number of times rename has blocked due to IQ full
1953system.cpu1.rename.LQFullEvents 291872 # Number of times rename has blocked due to LQ full
1954system.cpu1.rename.SQFullEvents 27374536 # Number of times rename has blocked due to SQ full
1955system.cpu1.rename.FullRegisterEvents 10500 # Number of times there has been no free registers
1956system.cpu1.rename.RenamedOperands 518347442 # Number of destination operands rename has renamed
1957system.cpu1.rename.RenameLookups 840457464 # Number of register rename lookups that rename has made
1958system.cpu1.rename.int_rename_lookups 646223551 # Number of integer rename lookups
1959system.cpu1.rename.fp_rename_lookups 691924 # Number of floating rename lookups
1960system.cpu1.rename.CommittedMaps 466279930 # Number of HB maps that are committed
1961system.cpu1.rename.UndoneMaps 52067506 # Number of HB maps that are undone due to squashing
1962system.cpu1.rename.serializingInsts 14268129 # count of serializing insts renamed
1963system.cpu1.rename.tempSerializingInsts 12524757 # count of temporary serializing insts renamed
1964system.cpu1.rename.skidInsts 67234415 # count of insts added to the skid buffer
1965system.cpu1.memDep0.insertedLoads 90658674 # Number of loads inserted to the mem dependence unit.
1966system.cpu1.memDep0.insertedStores 77385188 # Number of stores inserted to the mem dependence unit.
1967system.cpu1.memDep0.conflictingLoads 8528695 # Number of conflicting loads.
1968system.cpu1.memDep0.conflictingStores 7392702 # Number of conflicting stores.
1969system.cpu1.iq.iqInstsAdded 526120257 # Number of instructions added to the IQ (excludes non-spec)
1970system.cpu1.iq.iqNonSpecInstsAdded 14498185 # Number of non-speculative instructions added to the IQ
1971system.cpu1.iq.iqInstsIssued 530312729 # Number of instructions issued
1972system.cpu1.iq.iqSquashedInstsIssued 2450487 # Number of squashed instructions issued
1973system.cpu1.iq.iqSquashedInstsExamined 49492350 # Number of squashed instructions iterated over during squash; mainly for profiling
1974system.cpu1.iq.iqSquashedOperandsExamined 31830796 # Number of squashed operands that are examined and possibly removed from graph
1975system.cpu1.iq.iqSquashedNonSpecRemoved 264307 # Number of squashed non-spec instructions that were removed
1976system.cpu1.iq.issued_per_cycle::samples 643817634 # Number of insts issued each cycle
1977system.cpu1.iq.issued_per_cycle::mean 0.823700 # Number of insts issued each cycle
1978system.cpu1.iq.issued_per_cycle::stdev 1.068099 # Number of insts issued each cycle
1979system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1980system.cpu1.iq.issued_per_cycle::0 353942401 54.98% 54.98% # Number of insts issued each cycle
1981system.cpu1.iq.issued_per_cycle::1 122398683 19.01% 73.99% # Number of insts issued each cycle
1982system.cpu1.iq.issued_per_cycle::2 101611501 15.78% 89.77% # Number of insts issued each cycle
1983system.cpu1.iq.issued_per_cycle::3 58772797 9.13% 98.90% # Number of insts issued each cycle
1984system.cpu1.iq.issued_per_cycle::4 7088607 1.10% 100.00% # Number of insts issued each cycle
1985system.cpu1.iq.issued_per_cycle::5 3645 0.00% 100.00% # Number of insts issued each cycle
1986system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
1987system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
1988system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
1989system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1990system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1991system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
1992system.cpu1.iq.issued_per_cycle::total 643817634 # Number of insts issued each cycle
1993system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1994system.cpu1.iq.fu_full::IntAlu 53425749 43.94% 43.94% # attempts to use FU when none available
1995system.cpu1.iq.fu_full::IntMult 46790 0.04% 43.97% # attempts to use FU when none available
1996system.cpu1.iq.fu_full::IntDiv 9685 0.01% 43.98% # attempts to use FU when none available
1997system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.98% # attempts to use FU when none available
1998system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.98% # attempts to use FU when none available
1999system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.98% # attempts to use FU when none available
2000system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.98% # attempts to use FU when none available
2001system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.98% # attempts to use FU when none available
2002system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.98% # attempts to use FU when none available
2003system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.98% # attempts to use FU when none available
2004system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.98% # attempts to use FU when none available
2005system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.98% # attempts to use FU when none available
2006system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.98% # attempts to use FU when none available
2007system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.98% # attempts to use FU when none available
2008system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.98% # attempts to use FU when none available
2009system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.98% # attempts to use FU when none available
2010system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.98% # attempts to use FU when none available
2011system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.98% # attempts to use FU when none available
2012system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.98% # attempts to use FU when none available
2013system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.98% # attempts to use FU when none available
2014system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.98% # attempts to use FU when none available
2015system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.98% # attempts to use FU when none available
2016system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.98% # attempts to use FU when none available
2017system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.98% # attempts to use FU when none available
2018system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.98% # attempts to use FU when none available
2019system.cpu1.iq.fu_full::SimdFloatMisc 19 0.00% 43.98% # attempts to use FU when none available
2020system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.98% # attempts to use FU when none available
2021system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.98% # attempts to use FU when none available
2022system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.98% # attempts to use FU when none available
2023system.cpu1.iq.fu_full::MemRead 32795787 26.97% 70.95% # attempts to use FU when none available
2024system.cpu1.iq.fu_full::MemWrite 35319606 29.05% 100.00% # attempts to use FU when none available
2025system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
2026system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2027system.cpu1.iq.FU_type_0::No_OpClass 84 0.00% 0.00% # Type of FU issued
2028system.cpu1.iq.FU_type_0::IntAlu 360430820 67.97% 67.97% # Type of FU issued
2029system.cpu1.iq.FU_type_0::IntMult 1171247 0.22% 68.19% # Type of FU issued
2030system.cpu1.iq.FU_type_0::IntDiv 68672 0.01% 68.20% # Type of FU issued
2031system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.20% # Type of FU issued
2032system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.20% # Type of FU issued
2033system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.20% # Type of FU issued
2034system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.20% # Type of FU issued
2035system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.20% # Type of FU issued
2036system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.20% # Type of FU issued
2037system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.20% # Type of FU issued
2038system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.20% # Type of FU issued
2039system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.20% # Type of FU issued
2040system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.20% # Type of FU issued
2041system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.20% # Type of FU issued
2042system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.20% # Type of FU issued
2043system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.20% # Type of FU issued
2044system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.20% # Type of FU issued
2045system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.20% # Type of FU issued
2046system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.20% # Type of FU issued
2047system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.20% # Type of FU issued
2048system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.20% # Type of FU issued
2049system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.20% # Type of FU issued
2050system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.20% # Type of FU issued
2051system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.20% # Type of FU issued
2052system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.20% # Type of FU issued
2053system.cpu1.iq.FU_type_0::SimdFloatMisc 45220 0.01% 68.21% # Type of FU issued
2054system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.21% # Type of FU issued
2055system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.21% # Type of FU issued
2056system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.21% # Type of FU issued
2057system.cpu1.iq.FU_type_0::MemRead 93137728 17.56% 85.77% # Type of FU issued
2058system.cpu1.iq.FU_type_0::MemWrite 75458910 14.23% 100.00% # Type of FU issued
2059system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
2060system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2061system.cpu1.iq.FU_type_0::total 530312729 # Type of FU issued
2062system.cpu1.iq.rate 0.798703 # Inst issue rate
2063system.cpu1.iq.fu_busy_cnt 121597636 # FU busy when requested
2064system.cpu1.iq.fu_busy_rate 0.229294 # FU busy rate (busy events/executed inst)
2065system.cpu1.iq.int_inst_queue_reads 1827371450 # Number of integer instruction queue reads
2066system.cpu1.iq.int_inst_queue_writes 589808611 # Number of integer instruction queue writes
2067system.cpu1.iq.int_inst_queue_wakeup_accesses 515064806 # Number of integer instruction queue wakeup accesses
2068system.cpu1.iq.fp_inst_queue_reads 1119763 # Number of floating instruction queue reads
2069system.cpu1.iq.fp_inst_queue_writes 442884 # Number of floating instruction queue writes
2070system.cpu1.iq.fp_inst_queue_wakeup_accesses 412109 # Number of floating instruction queue wakeup accesses
2071system.cpu1.iq.int_alu_accesses 651211996 # Number of integer alu accesses
2072system.cpu1.iq.fp_alu_accesses 698285 # Number of floating point alu accesses
2073system.cpu1.iew.lsq.thread0.forwLoads 2417067 # Number of loads that had data forwarded from stores
2074system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2075system.cpu1.iew.lsq.thread0.squashedLoads 11379314 # Number of loads squashed
2076system.cpu1.iew.lsq.thread0.ignoredResponses 14413 # Number of memory responses ignored because the instruction is squashed
2077system.cpu1.iew.lsq.thread0.memOrderViolation 141714 # Number of memory ordering violations
2078system.cpu1.iew.lsq.thread0.squashedStores 5438356 # Number of stores squashed
2079system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2080system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2081system.cpu1.iew.lsq.thread0.rescheduledLoads 2432171 # Number of loads that were rescheduled
2082system.cpu1.iew.lsq.thread0.cacheBlocked 3747564 # Number of times an access to memory failed due to the cache being blocked
2083system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2084system.cpu1.iew.iewSquashCycles 4649446 # Number of cycles IEW is squashing
2085system.cpu1.iew.iewBlockCycles 5786949 # Number of cycles IEW is blocking
2086system.cpu1.iew.iewUnblockCycles 2152685 # Number of cycles IEW is unblocking
2087system.cpu1.iew.iewDispatchedInsts 540731877 # Number of instructions dispatched to IQ
2088system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2089system.cpu1.iew.iewDispLoadInsts 90658674 # Number of dispatched load instructions
2090system.cpu1.iew.iewDispStoreInsts 77385188 # Number of dispatched store instructions
2091system.cpu1.iew.iewDispNonSpecInsts 12325629 # Number of dispatched non-speculative instructions
2092system.cpu1.iew.iewIQFullEvents 58000 # Number of times the IQ has become full, causing a stall
2093system.cpu1.iew.iewLSQFullEvents 2039251 # Number of times the LSQ has become full, causing a stall
2094system.cpu1.iew.memOrderViolationEvents 141714 # Number of memory order violations
2095system.cpu1.iew.predictedTakenIncorrect 1867697 # Number of branches that were predicted taken incorrectly
2096system.cpu1.iew.predictedNotTakenIncorrect 2587615 # Number of branches that were predicted not taken incorrectly
2097system.cpu1.iew.branchMispredicts 4455312 # Number of branch mispredicts detected at execute
2098system.cpu1.iew.iewExecutedInsts 523333067 # Number of executed instructions
2099system.cpu1.iew.iewExecLoadInsts 90385914 # Number of load instructions executed
2100system.cpu1.iew.iewExecSquashedInsts 6476972 # Number of squashed instructions skipped in execute
2101system.cpu1.iew.exec_swp 0 # number of swp insts executed
2102system.cpu1.iew.exec_nop 113435 # number of nop insts executed
2103system.cpu1.iew.exec_refs 164677509 # number of memory reference insts executed
2104system.cpu1.iew.exec_branches 98047931 # Number of branches executed
2105system.cpu1.iew.exec_stores 74291595 # Number of stores executed
2106system.cpu1.iew.exec_rate 0.788191 # Inst execution rate
2107system.cpu1.iew.wb_sent 516143321 # cumulative count of insts sent to commit
2108system.cpu1.iew.wb_count 515476915 # cumulative count of insts written-back
2109system.cpu1.iew.wb_producers 249234254 # num instructions producing a value
2110system.cpu1.iew.wb_consumers 407965513 # num instructions consuming a value
2111system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
2112system.cpu1.iew.wb_rate 0.776359 # insts written-back per cycle
2113system.cpu1.iew.wb_fanout 0.610920 # average fanout of values written-back
2114system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
2115system.cpu1.commit.commitSquashedInsts 43327267 # The number of squashed insts skipped by commit
2116system.cpu1.commit.commitNonSpecStalls 14233878 # The number of times commit has been forced to stall to communicate backwards
2117system.cpu1.commit.branchMispredicts 4192740 # The number of times a branch was mispredicted
2118system.cpu1.commit.committed_per_cycle::samples 635627275 # Number of insts commited each cycle
2119system.cpu1.commit.committed_per_cycle::mean 0.772664 # Number of insts commited each cycle
2120system.cpu1.commit.committed_per_cycle::stdev 1.570415 # Number of insts commited each cycle
2121system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2122system.cpu1.commit.committed_per_cycle::0 419865335 66.06% 66.06% # Number of insts commited each cycle
2123system.cpu1.commit.committed_per_cycle::1 112371204 17.68% 83.73% # Number of insts commited each cycle
2124system.cpu1.commit.committed_per_cycle::2 47717309 7.51% 91.24% # Number of insts commited each cycle
2125system.cpu1.commit.committed_per_cycle::3 15913228 2.50% 93.74% # Number of insts commited each cycle
2126system.cpu1.commit.committed_per_cycle::4 11392527 1.79% 95.54% # Number of insts commited each cycle
2127system.cpu1.commit.committed_per_cycle::5 7668933 1.21% 96.74% # Number of insts commited each cycle
2128system.cpu1.commit.committed_per_cycle::6 5369975 0.84% 97.59% # Number of insts commited each cycle
2129system.cpu1.commit.committed_per_cycle::7 3184156 0.50% 98.09% # Number of insts commited each cycle
2130system.cpu1.commit.committed_per_cycle::8 12144608 1.91% 100.00% # Number of insts commited each cycle
2131system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2132system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2133system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2134system.cpu1.commit.committed_per_cycle::total 635627275 # Number of insts commited each cycle
2135system.cpu1.commit.committedInsts 416740074 # Number of instructions committed
2136system.cpu1.commit.committedOps 491126085 # Number of ops (including micro ops) committed
2137system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2138system.cpu1.commit.refs 151226191 # Number of memory references committed
2139system.cpu1.commit.loads 79279359 # Number of loads committed
2140system.cpu1.commit.membars 3502305 # Number of memory barriers committed
2141system.cpu1.commit.branches 92953281 # Number of branches committed
2142system.cpu1.commit.fp_insts 403468 # Number of committed floating point instructions.
2143system.cpu1.commit.int_insts 451237639 # Number of committed integer instructions.
2144system.cpu1.commit.function_calls 12195676 # Number of function calls committed.
2145system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2146system.cpu1.commit.op_class_0::IntAlu 338863536 69.00% 69.00% # Class of committed instruction
2147system.cpu1.commit.op_class_0::IntMult 941904 0.19% 69.19% # Class of committed instruction
2148system.cpu1.commit.op_class_0::IntDiv 54586 0.01% 69.20% # Class of committed instruction
2149system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.20% # Class of committed instruction
2150system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.20% # Class of committed instruction
2151system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.20% # Class of committed instruction
2152system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.20% # Class of committed instruction
2153system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.20% # Class of committed instruction
2154system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.20% # Class of committed instruction
2155system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.20% # Class of committed instruction
2156system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.20% # Class of committed instruction
2157system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.20% # Class of committed instruction
2158system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.20% # Class of committed instruction
2159system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.20% # Class of committed instruction
2160system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.20% # Class of committed instruction
2161system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.20% # Class of committed instruction
2162system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.20% # Class of committed instruction
2163system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.20% # Class of committed instruction
2164system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.20% # Class of committed instruction
2165system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.20% # Class of committed instruction
2166system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.20% # Class of committed instruction
2167system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.20% # Class of committed instruction
2168system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.20% # Class of committed instruction
2169system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.20% # Class of committed instruction
2170system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.20% # Class of committed instruction
2171system.cpu1.commit.op_class_0::SimdFloatMisc 39826 0.01% 69.21% # Class of committed instruction
2172system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.21% # Class of committed instruction
2173system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.21% # Class of committed instruction
2174system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.21% # Class of committed instruction
2175system.cpu1.commit.op_class_0::MemRead 79279359 16.14% 85.35% # Class of committed instruction
2176system.cpu1.commit.op_class_0::MemWrite 71946832 14.65% 100.00% # Class of committed instruction
2177system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2178system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2179system.cpu1.commit.op_class_0::total 491126085 # Class of committed instruction
2180system.cpu1.commit.bw_lim_events 12144608 # number cycles where commit BW limit reached
2181system.cpu1.rob.rob_reads 1154417922 # The number of ROB reads
2182system.cpu1.rob.rob_writes 1077060232 # The number of ROB writes
2183system.cpu1.timesIdled 910594 # Number of times that the entire CPU went into an idle state and unscheduled itself
2184system.cpu1.idleCycles 20149630 # Total number of cycles that the CPU has spent unscheduled due to idling
2185system.cpu1.quiesceCycles 94205821171 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2186system.cpu1.committedInsts 416740074 # Number of Instructions Simulated
2187system.cpu1.committedOps 491126085 # Number of Ops (including micro ops) Simulated
2188system.cpu1.cpi 1.593241 # CPI: Cycles Per Instruction
2189system.cpu1.cpi_total 1.593241 # CPI: Total CPI of All Threads
2190system.cpu1.ipc 0.627652 # IPC: Instructions Per Cycle
2191system.cpu1.ipc_total 0.627652 # IPC: Total IPC of All Threads
2192system.cpu1.int_regfile_reads 618723699 # number of integer regfile reads
2193system.cpu1.int_regfile_writes 366638237 # number of integer regfile writes
2194system.cpu1.fp_regfile_reads 681038 # number of floating regfile reads
2195system.cpu1.fp_regfile_writes 305796 # number of floating regfile writes
2196system.cpu1.cc_regfile_reads 111144597 # number of cc regfile reads
2197system.cpu1.cc_regfile_writes 111901561 # number of cc regfile writes
2198system.cpu1.misc_regfile_reads 1146158029 # number of misc regfile reads
2199system.cpu1.misc_regfile_writes 14345264 # number of misc regfile writes
2200system.cpu1.dcache.tags.replacements 5008277 # number of replacements
2201system.cpu1.dcache.tags.tagsinuse 444.234833 # Cycle average of tags in use
2202system.cpu1.dcache.tags.total_refs 141116395 # Total number of references to valid blocks.
2203system.cpu1.dcache.tags.sampled_refs 5008789 # Sample count of references to valid blocks.
2204system.cpu1.dcache.tags.avg_refs 28.173755 # Average number of references to valid blocks.
2205system.cpu1.dcache.tags.warmup_cycle 8487531137500 # Cycle when the warmup percentage was hit.
2206system.cpu1.dcache.tags.occ_blocks::cpu1.data 444.234833 # Average occupied blocks per requestor
2207system.cpu1.dcache.tags.occ_percent::cpu1.data 0.867646 # Average percentage of cache occupancy
2208system.cpu1.dcache.tags.occ_percent::total 0.867646 # Average percentage of cache occupancy
2209system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2210system.cpu1.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
2211system.cpu1.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id
2212system.cpu1.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
2213system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2214system.cpu1.dcache.tags.tag_accesses 313835409 # Number of tag accesses
2215system.cpu1.dcache.tags.data_accesses 313835409 # Number of data accesses
2216system.cpu1.dcache.ReadReq_hits::cpu1.data 73808968 # number of ReadReq hits
2217system.cpu1.dcache.ReadReq_hits::total 73808968 # number of ReadReq hits
2218system.cpu1.dcache.WriteReq_hits::cpu1.data 63012404 # number of WriteReq hits
2219system.cpu1.dcache.WriteReq_hits::total 63012404 # number of WriteReq hits
2220system.cpu1.dcache.SoftPFReq_hits::cpu1.data 166300 # number of SoftPFReq hits
2221system.cpu1.dcache.SoftPFReq_hits::total 166300 # number of SoftPFReq hits
2222system.cpu1.dcache.WriteLineReq_hits::cpu1.data 49799 # number of WriteLineReq hits
2223system.cpu1.dcache.WriteLineReq_hits::total 49799 # number of WriteLineReq hits
2224system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1689842 # number of LoadLockedReq hits
2225system.cpu1.dcache.LoadLockedReq_hits::total 1689842 # number of LoadLockedReq hits
2226system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1700596 # number of StoreCondReq hits
2227system.cpu1.dcache.StoreCondReq_hits::total 1700596 # number of StoreCondReq hits
2228system.cpu1.dcache.demand_hits::cpu1.data 136821372 # number of demand (read+write) hits
2229system.cpu1.dcache.demand_hits::total 136821372 # number of demand (read+write) hits
2230system.cpu1.dcache.overall_hits::cpu1.data 136987672 # number of overall hits
2231system.cpu1.dcache.overall_hits::total 136987672 # number of overall hits
2232system.cpu1.dcache.ReadReq_misses::cpu1.data 5891473 # number of ReadReq misses
2233system.cpu1.dcache.ReadReq_misses::total 5891473 # number of ReadReq misses
2234system.cpu1.dcache.WriteReq_misses::cpu1.data 6580040 # number of WriteReq misses
2235system.cpu1.dcache.WriteReq_misses::total 6580040 # number of WriteReq misses
2236system.cpu1.dcache.SoftPFReq_misses::cpu1.data 617645 # number of SoftPFReq misses
2237system.cpu1.dcache.SoftPFReq_misses::total 617645 # number of SoftPFReq misses
2238system.cpu1.dcache.WriteLineReq_misses::cpu1.data 417038 # number of WriteLineReq misses
2239system.cpu1.dcache.WriteLineReq_misses::total 417038 # number of WriteLineReq misses
2240system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 243108 # number of LoadLockedReq misses
2241system.cpu1.dcache.LoadLockedReq_misses::total 243108 # number of LoadLockedReq misses
2242system.cpu1.dcache.StoreCondReq_misses::cpu1.data 189778 # number of StoreCondReq misses
2243system.cpu1.dcache.StoreCondReq_misses::total 189778 # number of StoreCondReq misses
2244system.cpu1.dcache.demand_misses::cpu1.data 12471513 # number of demand (read+write) misses
2245system.cpu1.dcache.demand_misses::total 12471513 # number of demand (read+write) misses
2246system.cpu1.dcache.overall_misses::cpu1.data 13089158 # number of overall misses
2247system.cpu1.dcache.overall_misses::total 13089158 # number of overall misses
2248system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 92058874500 # number of ReadReq miss cycles
2249system.cpu1.dcache.ReadReq_miss_latency::total 92058874500 # number of ReadReq miss cycles
2250system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 133118807489 # number of WriteReq miss cycles
2251system.cpu1.dcache.WriteReq_miss_latency::total 133118807489 # number of WriteReq miss cycles
2252system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16001999882 # number of WriteLineReq miss cycles
2253system.cpu1.dcache.WriteLineReq_miss_latency::total 16001999882 # number of WriteLineReq miss cycles
2254system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3690480000 # number of LoadLockedReq miss cycles
2255system.cpu1.dcache.LoadLockedReq_miss_latency::total 3690480000 # number of LoadLockedReq miss cycles
2256system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4542175000 # number of StoreCondReq miss cycles
2257system.cpu1.dcache.StoreCondReq_miss_latency::total 4542175000 # number of StoreCondReq miss cycles
2258system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4462000 # number of StoreCondFailReq miss cycles
2259system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4462000 # number of StoreCondFailReq miss cycles
2260system.cpu1.dcache.demand_miss_latency::cpu1.data 225177681989 # number of demand (read+write) miss cycles
2261system.cpu1.dcache.demand_miss_latency::total 225177681989 # number of demand (read+write) miss cycles
2262system.cpu1.dcache.overall_miss_latency::cpu1.data 225177681989 # number of overall miss cycles
2263system.cpu1.dcache.overall_miss_latency::total 225177681989 # number of overall miss cycles
2264system.cpu1.dcache.ReadReq_accesses::cpu1.data 79700441 # number of ReadReq accesses(hits+misses)
2265system.cpu1.dcache.ReadReq_accesses::total 79700441 # number of ReadReq accesses(hits+misses)
2266system.cpu1.dcache.WriteReq_accesses::cpu1.data 69592444 # number of WriteReq accesses(hits+misses)
2267system.cpu1.dcache.WriteReq_accesses::total 69592444 # number of WriteReq accesses(hits+misses)
2268system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 783945 # number of SoftPFReq accesses(hits+misses)
2269system.cpu1.dcache.SoftPFReq_accesses::total 783945 # number of SoftPFReq accesses(hits+misses)
2270system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 466837 # number of WriteLineReq accesses(hits+misses)
2271system.cpu1.dcache.WriteLineReq_accesses::total 466837 # number of WriteLineReq accesses(hits+misses)
2272system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1932950 # number of LoadLockedReq accesses(hits+misses)
2273system.cpu1.dcache.LoadLockedReq_accesses::total 1932950 # number of LoadLockedReq accesses(hits+misses)
2274system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1890374 # number of StoreCondReq accesses(hits+misses)
2275system.cpu1.dcache.StoreCondReq_accesses::total 1890374 # number of StoreCondReq accesses(hits+misses)
2276system.cpu1.dcache.demand_accesses::cpu1.data 149292885 # number of demand (read+write) accesses
2277system.cpu1.dcache.demand_accesses::total 149292885 # number of demand (read+write) accesses
2278system.cpu1.dcache.overall_accesses::cpu1.data 150076830 # number of overall (read+write) accesses
2279system.cpu1.dcache.overall_accesses::total 150076830 # number of overall (read+write) accesses
2280system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.073920 # miss rate for ReadReq accesses
2281system.cpu1.dcache.ReadReq_miss_rate::total 0.073920 # miss rate for ReadReq accesses
2282system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.094551 # miss rate for WriteReq accesses
2283system.cpu1.dcache.WriteReq_miss_rate::total 0.094551 # miss rate for WriteReq accesses
2284system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.787868 # miss rate for SoftPFReq accesses
2285system.cpu1.dcache.SoftPFReq_miss_rate::total 0.787868 # miss rate for SoftPFReq accesses
2286system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.893327 # miss rate for WriteLineReq accesses
2287system.cpu1.dcache.WriteLineReq_miss_rate::total 0.893327 # miss rate for WriteLineReq accesses
2288system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125770 # miss rate for LoadLockedReq accesses
2289system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125770 # miss rate for LoadLockedReq accesses
2290system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100392 # miss rate for StoreCondReq accesses
2291system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100392 # miss rate for StoreCondReq accesses
2292system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083537 # miss rate for demand accesses
2293system.cpu1.dcache.demand_miss_rate::total 0.083537 # miss rate for demand accesses
2294system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087216 # miss rate for overall accesses
2295system.cpu1.dcache.overall_miss_rate::total 0.087216 # miss rate for overall accesses
2296system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15625.782296 # average ReadReq miss latency
2297system.cpu1.dcache.ReadReq_avg_miss_latency::total 15625.782296 # average ReadReq miss latency
2298system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20230.698824 # average WriteReq miss latency
2299system.cpu1.dcache.WriteReq_avg_miss_latency::total 20230.698824 # average WriteReq miss latency
2300system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 38370.603835 # average WriteLineReq miss latency
2301system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 38370.603835 # average WriteLineReq miss latency
2302system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15180.413643 # average LoadLockedReq miss latency
2303system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15180.413643 # average LoadLockedReq miss latency
2304system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23934.149375 # average StoreCondReq miss latency
2305system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23934.149375 # average StoreCondReq miss latency
2306system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
2307system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2308system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18055.362007 # average overall miss latency
2309system.cpu1.dcache.demand_avg_miss_latency::total 18055.362007 # average overall miss latency
2310system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17203.374120 # average overall miss latency
2311system.cpu1.dcache.overall_avg_miss_latency::total 17203.374120 # average overall miss latency
2312system.cpu1.dcache.blocked_cycles::no_mshrs 4151520 # number of cycles access was blocked
2313system.cpu1.dcache.blocked_cycles::no_targets 21118604 # number of cycles access was blocked
2314system.cpu1.dcache.blocked::no_mshrs 339495 # number of cycles access was blocked
2315system.cpu1.dcache.blocked::no_targets 658226 # number of cycles access was blocked
2316system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.228516 # average number of cycles each access was blocked
2317system.cpu1.dcache.avg_blocked_cycles::no_targets 32.084123 # average number of cycles each access was blocked
2318system.cpu1.dcache.fast_writes 0 # number of fast writes performed
2319system.cpu1.dcache.cache_copies 0 # number of cache copies performed
2320system.cpu1.dcache.writebacks::writebacks 3259663 # number of writebacks
2321system.cpu1.dcache.writebacks::total 3259663 # number of writebacks
2322system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 2995366 # number of ReadReq MSHR hits
2323system.cpu1.dcache.ReadReq_mshr_hits::total 2995366 # number of ReadReq MSHR hits
2324system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5317058 # number of WriteReq MSHR hits
2325system.cpu1.dcache.WriteReq_mshr_hits::total 5317058 # number of WriteReq MSHR hits
2326system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3866 # number of WriteLineReq MSHR hits
2327system.cpu1.dcache.WriteLineReq_mshr_hits::total 3866 # number of WriteLineReq MSHR hits
2328system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 125871 # number of LoadLockedReq MSHR hits
2329system.cpu1.dcache.LoadLockedReq_mshr_hits::total 125871 # number of LoadLockedReq MSHR hits
2330system.cpu1.dcache.demand_mshr_hits::cpu1.data 8312424 # number of demand (read+write) MSHR hits
2331system.cpu1.dcache.demand_mshr_hits::total 8312424 # number of demand (read+write) MSHR hits
2332system.cpu1.dcache.overall_mshr_hits::cpu1.data 8312424 # number of overall MSHR hits
2333system.cpu1.dcache.overall_mshr_hits::total 8312424 # number of overall MSHR hits
2334system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2896107 # number of ReadReq MSHR misses
2335system.cpu1.dcache.ReadReq_mshr_misses::total 2896107 # number of ReadReq MSHR misses
2336system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1262982 # number of WriteReq MSHR misses
2337system.cpu1.dcache.WriteReq_mshr_misses::total 1262982 # number of WriteReq MSHR misses
2338system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 617580 # number of SoftPFReq MSHR misses
2339system.cpu1.dcache.SoftPFReq_mshr_misses::total 617580 # number of SoftPFReq MSHR misses
2340system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 413172 # number of WriteLineReq MSHR misses
2341system.cpu1.dcache.WriteLineReq_mshr_misses::total 413172 # number of WriteLineReq MSHR misses
2342system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 117237 # number of LoadLockedReq MSHR misses
2343system.cpu1.dcache.LoadLockedReq_mshr_misses::total 117237 # number of LoadLockedReq MSHR misses
2344system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 189777 # number of StoreCondReq MSHR misses
2345system.cpu1.dcache.StoreCondReq_mshr_misses::total 189777 # number of StoreCondReq MSHR misses
2346system.cpu1.dcache.demand_mshr_misses::cpu1.data 4159089 # number of demand (read+write) MSHR misses
2347system.cpu1.dcache.demand_mshr_misses::total 4159089 # number of demand (read+write) MSHR misses
2348system.cpu1.dcache.overall_mshr_misses::cpu1.data 4776669 # number of overall MSHR misses
2349system.cpu1.dcache.overall_mshr_misses::total 4776669 # number of overall MSHR misses
2350system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6826 # number of ReadReq MSHR uncacheable
2351system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6826 # number of ReadReq MSHR uncacheable
2352system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7171 # number of WriteReq MSHR uncacheable
2353system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7171 # number of WriteReq MSHR uncacheable
2354system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 13997 # number of overall MSHR uncacheable misses
2355system.cpu1.dcache.overall_mshr_uncacheable_misses::total 13997 # number of overall MSHR uncacheable misses
2356system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41972381500 # number of ReadReq MSHR miss cycles
2357system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41972381500 # number of ReadReq MSHR miss cycles
2358system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 27436414661 # number of WriteReq MSHR miss cycles
2359system.cpu1.dcache.WriteReq_mshr_miss_latency::total 27436414661 # number of WriteReq MSHR miss cycles
2360system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14179581000 # number of SoftPFReq MSHR miss cycles
2361system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14179581000 # number of SoftPFReq MSHR miss cycles
2362system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 15426665382 # number of WriteLineReq MSHR miss cycles
2363system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 15426665382 # number of WriteLineReq MSHR miss cycles
2364system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1682703500 # number of LoadLockedReq MSHR miss cycles
2365system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1682703500 # number of LoadLockedReq MSHR miss cycles
2366system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4352455000 # number of StoreCondReq MSHR miss cycles
2367system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4352455000 # number of StoreCondReq MSHR miss cycles
2368system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4405000 # number of StoreCondFailReq MSHR miss cycles
2369system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4405000 # number of StoreCondFailReq MSHR miss cycles
2370system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69408796161 # number of demand (read+write) MSHR miss cycles
2371system.cpu1.dcache.demand_mshr_miss_latency::total 69408796161 # number of demand (read+write) MSHR miss cycles
2372system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83588377161 # number of overall MSHR miss cycles
2373system.cpu1.dcache.overall_mshr_miss_latency::total 83588377161 # number of overall MSHR miss cycles
2374system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 764918000 # number of ReadReq MSHR uncacheable cycles
2375system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 764918000 # number of ReadReq MSHR uncacheable cycles
2376system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 914224500 # number of WriteReq MSHR uncacheable cycles
2377system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 914224500 # number of WriteReq MSHR uncacheable cycles
2378system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1679142500 # number of overall MSHR uncacheable cycles
2379system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1679142500 # number of overall MSHR uncacheable cycles
2380system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036337 # mshr miss rate for ReadReq accesses
2381system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036337 # mshr miss rate for ReadReq accesses
2382system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018148 # mshr miss rate for WriteReq accesses
2383system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018148 # mshr miss rate for WriteReq accesses
2384system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.787785 # mshr miss rate for SoftPFReq accesses
2385system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.787785 # mshr miss rate for SoftPFReq accesses
2386system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.885046 # mshr miss rate for WriteLineReq accesses
2387system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.885046 # mshr miss rate for WriteLineReq accesses
2388system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060652 # mshr miss rate for LoadLockedReq accesses
2389system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060652 # mshr miss rate for LoadLockedReq accesses
2390system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100391 # mshr miss rate for StoreCondReq accesses
2391system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100391 # mshr miss rate for StoreCondReq accesses
2392system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027859 # mshr miss rate for demand accesses
2393system.cpu1.dcache.demand_mshr_miss_rate::total 0.027859 # mshr miss rate for demand accesses
2394system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031828 # mshr miss rate for overall accesses
2395system.cpu1.dcache.overall_mshr_miss_rate::total 0.031828 # mshr miss rate for overall accesses
2396system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14492.690187 # average ReadReq mshr miss latency
2397system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14492.690187 # average ReadReq mshr miss latency
2398system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 21723.519940 # average WriteReq mshr miss latency
2399system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21723.519940 # average WriteReq mshr miss latency
2400system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22959.909647 # average SoftPFReq mshr miss latency
2401system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22959.909647 # average SoftPFReq mshr miss latency
2402system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 37337.151070 # average WriteLineReq mshr miss latency
2403system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 37337.151070 # average WriteLineReq mshr miss latency
2404system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14353.007156 # average LoadLockedReq mshr miss latency
2405system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14353.007156 # average LoadLockedReq mshr miss latency
2406system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22934.575844 # average StoreCondReq mshr miss latency
2407system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22934.575844 # average StoreCondReq mshr miss latency
2408system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
2409system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2410system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16688.461382 # average overall mshr miss latency
2411system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16688.461382 # average overall mshr miss latency
2412system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17499.302791 # average overall mshr miss latency
2413system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17499.302791 # average overall mshr miss latency
2414system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112059.478465 # average ReadReq mshr uncacheable latency
2415system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 112059.478465 # average ReadReq mshr uncacheable latency
2416system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 127489.122856 # average WriteReq mshr uncacheable latency
2417system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 127489.122856 # average WriteReq mshr uncacheable latency
2418system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 119964.456669 # average overall mshr uncacheable latency
2419system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 119964.456669 # average overall mshr uncacheable latency
2420system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2421system.cpu1.icache.tags.replacements 5544230 # number of replacements
2422system.cpu1.icache.tags.tagsinuse 501.780204 # Cycle average of tags in use
2423system.cpu1.icache.tags.total_refs 185921865 # Total number of references to valid blocks.
2424system.cpu1.icache.tags.sampled_refs 5544742 # Sample count of references to valid blocks.
2425system.cpu1.icache.tags.avg_refs 33.531202 # Average number of references to valid blocks.
2426system.cpu1.icache.tags.warmup_cycle 8527218243000 # Cycle when the warmup percentage was hit.
2427system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.780204 # Average occupied blocks per requestor
2428system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980039 # Average percentage of cache occupancy
2429system.cpu1.icache.tags.occ_percent::total 0.980039 # Average percentage of cache occupancy
2430system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2431system.cpu1.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
2432system.cpu1.icache.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id
2433system.cpu1.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id
2434system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2435system.cpu1.icache.tags.tag_accesses 389132386 # Number of tag accesses
2436system.cpu1.icache.tags.data_accesses 389132386 # Number of data accesses
2437system.cpu1.icache.ReadReq_hits::cpu1.inst 185921865 # number of ReadReq hits
2438system.cpu1.icache.ReadReq_hits::total 185921865 # number of ReadReq hits
2439system.cpu1.icache.demand_hits::cpu1.inst 185921865 # number of demand (read+write) hits
2440system.cpu1.icache.demand_hits::total 185921865 # number of demand (read+write) hits
2441system.cpu1.icache.overall_hits::cpu1.inst 185921865 # number of overall hits
2442system.cpu1.icache.overall_hits::total 185921865 # number of overall hits
2443system.cpu1.icache.ReadReq_misses::cpu1.inst 5871956 # number of ReadReq misses
2444system.cpu1.icache.ReadReq_misses::total 5871956 # number of ReadReq misses
2445system.cpu1.icache.demand_misses::cpu1.inst 5871956 # number of demand (read+write) misses
2446system.cpu1.icache.demand_misses::total 5871956 # number of demand (read+write) misses
2447system.cpu1.icache.overall_misses::cpu1.inst 5871956 # number of overall misses
2448system.cpu1.icache.overall_misses::total 5871956 # number of overall misses
2449system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 64156067699 # number of ReadReq miss cycles
2450system.cpu1.icache.ReadReq_miss_latency::total 64156067699 # number of ReadReq miss cycles
2451system.cpu1.icache.demand_miss_latency::cpu1.inst 64156067699 # number of demand (read+write) miss cycles
2452system.cpu1.icache.demand_miss_latency::total 64156067699 # number of demand (read+write) miss cycles
2453system.cpu1.icache.overall_miss_latency::cpu1.inst 64156067699 # number of overall miss cycles
2454system.cpu1.icache.overall_miss_latency::total 64156067699 # number of overall miss cycles
2455system.cpu1.icache.ReadReq_accesses::cpu1.inst 191793821 # number of ReadReq accesses(hits+misses)
2456system.cpu1.icache.ReadReq_accesses::total 191793821 # number of ReadReq accesses(hits+misses)
2457system.cpu1.icache.demand_accesses::cpu1.inst 191793821 # number of demand (read+write) accesses
2458system.cpu1.icache.demand_accesses::total 191793821 # number of demand (read+write) accesses
2459system.cpu1.icache.overall_accesses::cpu1.inst 191793821 # number of overall (read+write) accesses
2460system.cpu1.icache.overall_accesses::total 191793821 # number of overall (read+write) accesses
2461system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030616 # miss rate for ReadReq accesses
2462system.cpu1.icache.ReadReq_miss_rate::total 0.030616 # miss rate for ReadReq accesses
2463system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030616 # miss rate for demand accesses
2464system.cpu1.icache.demand_miss_rate::total 0.030616 # miss rate for demand accesses
2465system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030616 # miss rate for overall accesses
2466system.cpu1.icache.overall_miss_rate::total 0.030616 # miss rate for overall accesses
2467system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10925.842717 # average ReadReq miss latency
2468system.cpu1.icache.ReadReq_avg_miss_latency::total 10925.842717 # average ReadReq miss latency
2469system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10925.842717 # average overall miss latency
2470system.cpu1.icache.demand_avg_miss_latency::total 10925.842717 # average overall miss latency
2471system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10925.842717 # average overall miss latency
2472system.cpu1.icache.overall_avg_miss_latency::total 10925.842717 # average overall miss latency
2473system.cpu1.icache.blocked_cycles::no_mshrs 9696468 # number of cycles access was blocked
2474system.cpu1.icache.blocked_cycles::no_targets 348 # number of cycles access was blocked
2475system.cpu1.icache.blocked::no_mshrs 701587 # number of cycles access was blocked
2476system.cpu1.icache.blocked::no_targets 5 # number of cycles access was blocked
2477system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.820763 # average number of cycles each access was blocked
2478system.cpu1.icache.avg_blocked_cycles::no_targets 69.600000 # average number of cycles each access was blocked
2479system.cpu1.icache.fast_writes 0 # number of fast writes performed
2480system.cpu1.icache.cache_copies 0 # number of cache copies performed
2481system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 327212 # number of ReadReq MSHR hits
2482system.cpu1.icache.ReadReq_mshr_hits::total 327212 # number of ReadReq MSHR hits
2483system.cpu1.icache.demand_mshr_hits::cpu1.inst 327212 # number of demand (read+write) MSHR hits
2484system.cpu1.icache.demand_mshr_hits::total 327212 # number of demand (read+write) MSHR hits
2485system.cpu1.icache.overall_mshr_hits::cpu1.inst 327212 # number of overall MSHR hits
2486system.cpu1.icache.overall_mshr_hits::total 327212 # number of overall MSHR hits
2487system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5544744 # number of ReadReq MSHR misses
2488system.cpu1.icache.ReadReq_mshr_misses::total 5544744 # number of ReadReq MSHR misses
2489system.cpu1.icache.demand_mshr_misses::cpu1.inst 5544744 # number of demand (read+write) MSHR misses
2490system.cpu1.icache.demand_mshr_misses::total 5544744 # number of demand (read+write) MSHR misses
2491system.cpu1.icache.overall_mshr_misses::cpu1.inst 5544744 # number of overall MSHR misses
2492system.cpu1.icache.overall_mshr_misses::total 5544744 # number of overall MSHR misses
2493system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
2494system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable
2495system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
2496system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses
2497system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 57863828928 # number of ReadReq MSHR miss cycles
2498system.cpu1.icache.ReadReq_mshr_miss_latency::total 57863828928 # number of ReadReq MSHR miss cycles
2499system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 57863828928 # number of demand (read+write) MSHR miss cycles
2500system.cpu1.icache.demand_mshr_miss_latency::total 57863828928 # number of demand (read+write) MSHR miss cycles
2501system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 57863828928 # number of overall MSHR miss cycles
2502system.cpu1.icache.overall_mshr_miss_latency::total 57863828928 # number of overall MSHR miss cycles
2503system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8907998 # number of ReadReq MSHR uncacheable cycles
2504system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8907998 # number of ReadReq MSHR uncacheable cycles
2505system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8907998 # number of overall MSHR uncacheable cycles
2506system.cpu1.icache.overall_mshr_uncacheable_latency::total 8907998 # number of overall MSHR uncacheable cycles
2507system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028910 # mshr miss rate for ReadReq accesses
2508system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028910 # mshr miss rate for ReadReq accesses
2509system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028910 # mshr miss rate for demand accesses
2510system.cpu1.icache.demand_mshr_miss_rate::total 0.028910 # mshr miss rate for demand accesses
2511system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028910 # mshr miss rate for overall accesses
2512system.cpu1.icache.overall_mshr_miss_rate::total 0.028910 # mshr miss rate for overall accesses
2513system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10435.798105 # average ReadReq mshr miss latency
2514system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10435.798105 # average ReadReq mshr miss latency
2515system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10435.798105 # average overall mshr miss latency
2516system.cpu1.icache.demand_avg_mshr_miss_latency::total 10435.798105 # average overall mshr miss latency
2517system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10435.798105 # average overall mshr miss latency
2518system.cpu1.icache.overall_avg_mshr_miss_latency::total 10435.798105 # average overall mshr miss latency
2519system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132955.194030 # average ReadReq mshr uncacheable latency
2520system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132955.194030 # average ReadReq mshr uncacheable latency
2521system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132955.194030 # average overall mshr uncacheable latency
2522system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132955.194030 # average overall mshr uncacheable latency
2523system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2524system.cpu1.l2cache.prefetcher.num_hwpf_issued 6820164 # number of hwpf issued
2525system.cpu1.l2cache.prefetcher.pfIdentified 6823757 # number of prefetch candidates identified
2526system.cpu1.l2cache.prefetcher.pfBufferHit 3326 # number of redundant prefetches already in prefetch queue
2527system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
2528system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2529system.cpu1.l2cache.prefetcher.pfSpanPage 803331 # number of prefetches not generated due to page crossing
2530system.cpu1.l2cache.tags.replacements 1997658 # number of replacements
2531system.cpu1.l2cache.tags.tagsinuse 13422.615868 # Cycle average of tags in use
2532system.cpu1.l2cache.tags.total_refs 18456162 # Total number of references to valid blocks.
2533system.cpu1.l2cache.tags.sampled_refs 2013697 # Sample count of references to valid blocks.
2534system.cpu1.l2cache.tags.avg_refs 9.165312 # Average number of references to valid blocks.
2535system.cpu1.l2cache.tags.warmup_cycle 9617415490500 # Cycle when the warmup percentage was hit.
2536system.cpu1.l2cache.tags.occ_blocks::writebacks 3897.343042 # Average occupied blocks per requestor
2537system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 66.015363 # Average occupied blocks per requestor
2538system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 51.895680 # Average occupied blocks per requestor
2539system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3723.378261 # Average occupied blocks per requestor
2540system.cpu1.l2cache.tags.occ_blocks::cpu1.data 4768.192327 # Average occupied blocks per requestor
2541system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 915.791195 # Average occupied blocks per requestor
2542system.cpu1.l2cache.tags.occ_percent::writebacks 0.237875 # Average percentage of cache occupancy
2543system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004029 # Average percentage of cache occupancy
2544system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003167 # Average percentage of cache occupancy
2545system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.227257 # Average percentage of cache occupancy
2546system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.291027 # Average percentage of cache occupancy
2547system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055895 # Average percentage of cache occupancy
2548system.cpu1.l2cache.tags.occ_percent::total 0.819251 # Average percentage of cache occupancy
2549system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1310 # Occupied blocks per task id
2550system.cpu1.l2cache.tags.occ_task_id_blocks::1023 85 # Occupied blocks per task id
2551system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14644 # Occupied blocks per task id
2552system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
2553system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 29 # Occupied blocks per task id
2554system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 243 # Occupied blocks per task id
2555system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 653 # Occupied blocks per task id
2556system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 377 # Occupied blocks per task id
2557system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
2558system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 38 # Occupied blocks per task id
2559system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 23 # Occupied blocks per task id
2560system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id
2561system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
2562system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1361 # Occupied blocks per task id
2563system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5328 # Occupied blocks per task id
2564system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4585 # Occupied blocks per task id
2565system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3240 # Occupied blocks per task id
2566system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.079956 # Percentage of cache occupancy per task id
2567system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id
2568system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.893799 # Percentage of cache occupancy per task id
2569system.cpu1.l2cache.tags.tag_accesses 360770404 # Number of tag accesses
2570system.cpu1.l2cache.tags.data_accesses 360770404 # Number of data accesses
2571system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 497732 # number of ReadReq hits
2572system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 168884 # number of ReadReq hits
2573system.cpu1.l2cache.ReadReq_hits::total 666616 # number of ReadReq hits
2574system.cpu1.l2cache.Writeback_hits::writebacks 3259650 # number of Writeback hits
2575system.cpu1.l2cache.Writeback_hits::total 3259650 # number of Writeback hits
2576system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 66819 # number of UpgradeReq hits
2577system.cpu1.l2cache.UpgradeReq_hits::total 66819 # number of UpgradeReq hits
2578system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 31621 # number of SCUpgradeReq hits
2579system.cpu1.l2cache.SCUpgradeReq_hits::total 31621 # number of SCUpgradeReq hits
2580system.cpu1.l2cache.ReadExReq_hits::cpu1.data 793791 # number of ReadExReq hits
2581system.cpu1.l2cache.ReadExReq_hits::total 793791 # number of ReadExReq hits
2582system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4983800 # number of ReadCleanReq hits
2583system.cpu1.l2cache.ReadCleanReq_hits::total 4983800 # number of ReadCleanReq hits
2584system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2698278 # number of ReadSharedReq hits
2585system.cpu1.l2cache.ReadSharedReq_hits::total 2698278 # number of ReadSharedReq hits
2586system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 190326 # number of InvalidateReq hits
2587system.cpu1.l2cache.InvalidateReq_hits::total 190326 # number of InvalidateReq hits
2588system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 497732 # number of demand (read+write) hits
2589system.cpu1.l2cache.demand_hits::cpu1.itb.walker 168884 # number of demand (read+write) hits
2590system.cpu1.l2cache.demand_hits::cpu1.inst 4983800 # number of demand (read+write) hits
2591system.cpu1.l2cache.demand_hits::cpu1.data 3492069 # number of demand (read+write) hits
2592system.cpu1.l2cache.demand_hits::total 9142485 # number of demand (read+write) hits
2593system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 497732 # number of overall hits
2594system.cpu1.l2cache.overall_hits::cpu1.itb.walker 168884 # number of overall hits
2595system.cpu1.l2cache.overall_hits::cpu1.inst 4983800 # number of overall hits
2596system.cpu1.l2cache.overall_hits::cpu1.data 3492069 # number of overall hits
2597system.cpu1.l2cache.overall_hits::total 9142485 # number of overall hits
2598system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 10518 # number of ReadReq misses
2599system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7585 # number of ReadReq misses
2600system.cpu1.l2cache.ReadReq_misses::total 18103 # number of ReadReq misses
2601system.cpu1.l2cache.Writeback_misses::writebacks 13 # number of Writeback misses
2602system.cpu1.l2cache.Writeback_misses::total 13 # number of Writeback misses
2603system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 142287 # number of UpgradeReq misses
2604system.cpu1.l2cache.UpgradeReq_misses::total 142287 # number of UpgradeReq misses
2605system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158148 # number of SCUpgradeReq misses
2606system.cpu1.l2cache.SCUpgradeReq_misses::total 158148 # number of SCUpgradeReq misses
2607system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 8 # number of SCUpgradeFailReq misses
2608system.cpu1.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses
2609system.cpu1.l2cache.ReadExReq_misses::cpu1.data 268312 # number of ReadExReq misses
2610system.cpu1.l2cache.ReadExReq_misses::total 268312 # number of ReadExReq misses
2611system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 560943 # number of ReadCleanReq misses
2612system.cpu1.l2cache.ReadCleanReq_misses::total 560943 # number of ReadCleanReq misses
2613system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 929119 # number of ReadSharedReq misses
2614system.cpu1.l2cache.ReadSharedReq_misses::total 929119 # number of ReadSharedReq misses
2615system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 221533 # number of InvalidateReq misses
2616system.cpu1.l2cache.InvalidateReq_misses::total 221533 # number of InvalidateReq misses
2617system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 10518 # number of demand (read+write) misses
2618system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7585 # number of demand (read+write) misses
2619system.cpu1.l2cache.demand_misses::cpu1.inst 560943 # number of demand (read+write) misses
2620system.cpu1.l2cache.demand_misses::cpu1.data 1197431 # number of demand (read+write) misses
2621system.cpu1.l2cache.demand_misses::total 1776477 # number of demand (read+write) misses
2622system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 10518 # number of overall misses
2623system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7585 # number of overall misses
2624system.cpu1.l2cache.overall_misses::cpu1.inst 560943 # number of overall misses
2625system.cpu1.l2cache.overall_misses::cpu1.data 1197431 # number of overall misses
2626system.cpu1.l2cache.overall_misses::total 1776477 # number of overall misses
2627system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 440507000 # number of ReadReq miss cycles
2628system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 317156000 # number of ReadReq miss cycles
2629system.cpu1.l2cache.ReadReq_miss_latency::total 757663000 # number of ReadReq miss cycles
2630system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 4278657000 # number of UpgradeReq miss cycles
2631system.cpu1.l2cache.UpgradeReq_miss_latency::total 4278657000 # number of UpgradeReq miss cycles
2632system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3704095999 # number of SCUpgradeReq miss cycles
2633system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3704095999 # number of SCUpgradeReq miss cycles
2634system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4317497 # number of SCUpgradeFailReq miss cycles
2635system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4317497 # number of SCUpgradeFailReq miss cycles
2636system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 13921759999 # number of ReadExReq miss cycles
2637system.cpu1.l2cache.ReadExReq_miss_latency::total 13921759999 # number of ReadExReq miss cycles
2638system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 19818008500 # number of ReadCleanReq miss cycles
2639system.cpu1.l2cache.ReadCleanReq_miss_latency::total 19818008500 # number of ReadCleanReq miss cycles
2640system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 34488387987 # number of ReadSharedReq miss cycles
2641system.cpu1.l2cache.ReadSharedReq_miss_latency::total 34488387987 # number of ReadSharedReq miss cycles
2642system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 13205591500 # number of InvalidateReq miss cycles
2643system.cpu1.l2cache.InvalidateReq_miss_latency::total 13205591500 # number of InvalidateReq miss cycles
2644system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 440507000 # number of demand (read+write) miss cycles
2645system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 317156000 # number of demand (read+write) miss cycles
2646system.cpu1.l2cache.demand_miss_latency::cpu1.inst 19818008500 # number of demand (read+write) miss cycles
2647system.cpu1.l2cache.demand_miss_latency::cpu1.data 48410147986 # number of demand (read+write) miss cycles
2648system.cpu1.l2cache.demand_miss_latency::total 68985819486 # number of demand (read+write) miss cycles
2649system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 440507000 # number of overall miss cycles
2650system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 317156000 # number of overall miss cycles
2651system.cpu1.l2cache.overall_miss_latency::cpu1.inst 19818008500 # number of overall miss cycles
2652system.cpu1.l2cache.overall_miss_latency::cpu1.data 48410147986 # number of overall miss cycles
2653system.cpu1.l2cache.overall_miss_latency::total 68985819486 # number of overall miss cycles
2654system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 508250 # number of ReadReq accesses(hits+misses)
2655system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 176469 # number of ReadReq accesses(hits+misses)
2656system.cpu1.l2cache.ReadReq_accesses::total 684719 # number of ReadReq accesses(hits+misses)
2657system.cpu1.l2cache.Writeback_accesses::writebacks 3259663 # number of Writeback accesses(hits+misses)
2658system.cpu1.l2cache.Writeback_accesses::total 3259663 # number of Writeback accesses(hits+misses)
2659system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 209106 # number of UpgradeReq accesses(hits+misses)
2660system.cpu1.l2cache.UpgradeReq_accesses::total 209106 # number of UpgradeReq accesses(hits+misses)
2661system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 189769 # number of SCUpgradeReq accesses(hits+misses)
2662system.cpu1.l2cache.SCUpgradeReq_accesses::total 189769 # number of SCUpgradeReq accesses(hits+misses)
2663system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 8 # number of SCUpgradeFailReq accesses(hits+misses)
2664system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses)
2665system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1062103 # number of ReadExReq accesses(hits+misses)
2666system.cpu1.l2cache.ReadExReq_accesses::total 1062103 # number of ReadExReq accesses(hits+misses)
2667system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5544743 # number of ReadCleanReq accesses(hits+misses)
2668system.cpu1.l2cache.ReadCleanReq_accesses::total 5544743 # number of ReadCleanReq accesses(hits+misses)
2669system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3627397 # number of ReadSharedReq accesses(hits+misses)
2670system.cpu1.l2cache.ReadSharedReq_accesses::total 3627397 # number of ReadSharedReq accesses(hits+misses)
2671system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 411859 # number of InvalidateReq accesses(hits+misses)
2672system.cpu1.l2cache.InvalidateReq_accesses::total 411859 # number of InvalidateReq accesses(hits+misses)
2673system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 508250 # number of demand (read+write) accesses
2674system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 176469 # number of demand (read+write) accesses
2675system.cpu1.l2cache.demand_accesses::cpu1.inst 5544743 # number of demand (read+write) accesses
2676system.cpu1.l2cache.demand_accesses::cpu1.data 4689500 # number of demand (read+write) accesses
2677system.cpu1.l2cache.demand_accesses::total 10918962 # number of demand (read+write) accesses
2678system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 508250 # number of overall (read+write) accesses
2679system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 176469 # number of overall (read+write) accesses
2680system.cpu1.l2cache.overall_accesses::cpu1.inst 5544743 # number of overall (read+write) accesses
2681system.cpu1.l2cache.overall_accesses::cpu1.data 4689500 # number of overall (read+write) accesses
2682system.cpu1.l2cache.overall_accesses::total 10918962 # number of overall (read+write) accesses
2683system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020695 # miss rate for ReadReq accesses
2684system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.042982 # miss rate for ReadReq accesses
2685system.cpu1.l2cache.ReadReq_miss_rate::total 0.026439 # miss rate for ReadReq accesses
2686system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000004 # miss rate for Writeback accesses
2687system.cpu1.l2cache.Writeback_miss_rate::total 0.000004 # miss rate for Writeback accesses
2688system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.680454 # miss rate for UpgradeReq accesses
2689system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.680454 # miss rate for UpgradeReq accesses
2690system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.833371 # miss rate for SCUpgradeReq accesses
2691system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.833371 # miss rate for SCUpgradeReq accesses
2692system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2693system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2694system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.252623 # miss rate for ReadExReq accesses
2695system.cpu1.l2cache.ReadExReq_miss_rate::total 0.252623 # miss rate for ReadExReq accesses
2696system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.101167 # miss rate for ReadCleanReq accesses
2697system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.101167 # miss rate for ReadCleanReq accesses
2698system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.256139 # miss rate for ReadSharedReq accesses
2699system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.256139 # miss rate for ReadSharedReq accesses
2700system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.537886 # miss rate for InvalidateReq accesses
2701system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.537886 # miss rate for InvalidateReq accesses
2702system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020695 # miss rate for demand accesses
2703system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.042982 # miss rate for demand accesses
2704system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.101167 # miss rate for demand accesses
2705system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.255343 # miss rate for demand accesses
2706system.cpu1.l2cache.demand_miss_rate::total 0.162697 # miss rate for demand accesses
2707system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020695 # miss rate for overall accesses
2708system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.042982 # miss rate for overall accesses
2709system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.101167 # miss rate for overall accesses
2710system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.255343 # miss rate for overall accesses
2711system.cpu1.l2cache.overall_miss_rate::total 0.162697 # miss rate for overall accesses
2712system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 41881.251188 # average ReadReq miss latency
2713system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 41813.579433 # average ReadReq miss latency
2714system.cpu1.l2cache.ReadReq_avg_miss_latency::total 41852.897310 # average ReadReq miss latency
2715system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 30070.610808 # average UpgradeReq miss latency
2716system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 30070.610808 # average UpgradeReq miss latency
2717system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 23421.706244 # average SCUpgradeReq miss latency
2718system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 23421.706244 # average SCUpgradeReq miss latency
2719system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 539687.125000 # average SCUpgradeFailReq miss latency
2720system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 539687.125000 # average SCUpgradeFailReq miss latency
2721system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51886.460535 # average ReadExReq miss latency
2722system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51886.460535 # average ReadExReq miss latency
2723system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35329.808020 # average ReadCleanReq miss latency
2724system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35329.808020 # average ReadCleanReq miss latency
2725system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 37119.451854 # average ReadSharedReq miss latency
2726system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 37119.451854 # average ReadSharedReq miss latency
2727system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 59610.042296 # average InvalidateReq miss latency
2728system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 59610.042296 # average InvalidateReq miss latency
2729system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 41881.251188 # average overall miss latency
2730system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 41813.579433 # average overall miss latency
2731system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35329.808020 # average overall miss latency
2732system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 40428.340327 # average overall miss latency
2733system.cpu1.l2cache.demand_avg_miss_latency::total 38832.937035 # average overall miss latency
2734system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 41881.251188 # average overall miss latency
2735system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 41813.579433 # average overall miss latency
2736system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35329.808020 # average overall miss latency
2737system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40428.340327 # average overall miss latency
2738system.cpu1.l2cache.overall_avg_miss_latency::total 38832.937035 # average overall miss latency
2739system.cpu1.l2cache.blocked_cycles::no_mshrs 1044 # number of cycles access was blocked
2740system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2741system.cpu1.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked
2742system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2743system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 348 # average number of cycles each access was blocked
2744system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2745system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2746system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2747system.cpu1.l2cache.writebacks::writebacks 898326 # number of writebacks
2748system.cpu1.l2cache.writebacks::total 898326 # number of writebacks
2749system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 8 # number of ReadReq MSHR hits
2750system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 163 # number of ReadReq MSHR hits
2751system.cpu1.l2cache.ReadReq_mshr_hits::total 171 # number of ReadReq MSHR hits
2752system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 35372 # number of ReadExReq MSHR hits
2753system.cpu1.l2cache.ReadExReq_mshr_hits::total 35372 # number of ReadExReq MSHR hits
2754system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4249 # number of ReadSharedReq MSHR hits
2755system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4249 # number of ReadSharedReq MSHR hits
2756system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 14 # number of InvalidateReq MSHR hits
2757system.cpu1.l2cache.InvalidateReq_mshr_hits::total 14 # number of InvalidateReq MSHR hits
2758system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 8 # number of demand (read+write) MSHR hits
2759system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 163 # number of demand (read+write) MSHR hits
2760system.cpu1.l2cache.demand_mshr_hits::cpu1.data 39621 # number of demand (read+write) MSHR hits
2761system.cpu1.l2cache.demand_mshr_hits::total 39792 # number of demand (read+write) MSHR hits
2762system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 8 # number of overall MSHR hits
2763system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 163 # number of overall MSHR hits
2764system.cpu1.l2cache.overall_mshr_hits::cpu1.data 39621 # number of overall MSHR hits
2765system.cpu1.l2cache.overall_mshr_hits::total 39792 # number of overall MSHR hits
2766system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 10510 # number of ReadReq MSHR misses
2767system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7422 # number of ReadReq MSHR misses
2768system.cpu1.l2cache.ReadReq_mshr_misses::total 17932 # number of ReadReq MSHR misses
2769system.cpu1.l2cache.Writeback_mshr_misses::writebacks 13 # number of Writeback MSHR misses
2770system.cpu1.l2cache.Writeback_mshr_misses::total 13 # number of Writeback MSHR misses
2771system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 94515 # number of CleanEvict MSHR misses
2772system.cpu1.l2cache.CleanEvict_mshr_misses::total 94515 # number of CleanEvict MSHR misses
2773system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 663376 # number of HardPFReq MSHR misses
2774system.cpu1.l2cache.HardPFReq_mshr_misses::total 663376 # number of HardPFReq MSHR misses
2775system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 142287 # number of UpgradeReq MSHR misses
2776system.cpu1.l2cache.UpgradeReq_mshr_misses::total 142287 # number of UpgradeReq MSHR misses
2777system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 158148 # number of SCUpgradeReq MSHR misses
2778system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 158148 # number of SCUpgradeReq MSHR misses
2779system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 8 # number of SCUpgradeFailReq MSHR misses
2780system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses
2781system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 232940 # number of ReadExReq MSHR misses
2782system.cpu1.l2cache.ReadExReq_mshr_misses::total 232940 # number of ReadExReq MSHR misses
2783system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 560943 # number of ReadCleanReq MSHR misses
2784system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 560943 # number of ReadCleanReq MSHR misses
2785system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 924870 # number of ReadSharedReq MSHR misses
2786system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 924870 # number of ReadSharedReq MSHR misses
2787system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 221519 # number of InvalidateReq MSHR misses
2788system.cpu1.l2cache.InvalidateReq_mshr_misses::total 221519 # number of InvalidateReq MSHR misses
2789system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 10510 # number of demand (read+write) MSHR misses
2790system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7422 # number of demand (read+write) MSHR misses
2791system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 560943 # number of demand (read+write) MSHR misses
2792system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1157810 # number of demand (read+write) MSHR misses
2793system.cpu1.l2cache.demand_mshr_misses::total 1736685 # number of demand (read+write) MSHR misses
2794system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 10510 # number of overall MSHR misses
2795system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7422 # number of overall MSHR misses
2796system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 560943 # number of overall MSHR misses
2797system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1157810 # number of overall MSHR misses
2798system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 663376 # number of overall MSHR misses
2799system.cpu1.l2cache.overall_mshr_misses::total 2400061 # number of overall MSHR misses
2800system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
2801system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6826 # number of ReadReq MSHR uncacheable
2802system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 6893 # number of ReadReq MSHR uncacheable
2803system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7171 # number of WriteReq MSHR uncacheable
2804system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7171 # number of WriteReq MSHR uncacheable
2805system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
2806system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 13997 # number of overall MSHR uncacheable misses
2807system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14064 # number of overall MSHR uncacheable misses
2808system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 377290500 # number of ReadReq MSHR miss cycles
2809system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 262748000 # number of ReadReq MSHR miss cycles
2810system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 640038500 # number of ReadReq MSHR miss cycles
2811system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 36936048403 # number of HardPFReq MSHR miss cycles
2812system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 36936048403 # number of HardPFReq MSHR miss cycles
2813system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4692578493 # number of UpgradeReq MSHR miss cycles
2814system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4692578493 # number of UpgradeReq MSHR miss cycles
2815system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2913063996 # number of SCUpgradeReq MSHR miss cycles
2816system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2913063996 # number of SCUpgradeReq MSHR miss cycles
2817system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3975497 # number of SCUpgradeFailReq MSHR miss cycles
2818system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3975497 # number of SCUpgradeFailReq MSHR miss cycles
2819system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 10641963999 # number of ReadExReq MSHR miss cycles
2820system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 10641963999 # number of ReadExReq MSHR miss cycles
2821system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 16452350500 # number of ReadCleanReq MSHR miss cycles
2822system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 16452350500 # number of ReadCleanReq MSHR miss cycles
2823system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 28730541987 # number of ReadSharedReq MSHR miss cycles
2824system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 28730541987 # number of ReadSharedReq MSHR miss cycles
2825system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 11875773000 # number of InvalidateReq MSHR miss cycles
2826system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 11875773000 # number of InvalidateReq MSHR miss cycles
2827system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 377290500 # number of demand (read+write) MSHR miss cycles
2828system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 262748000 # number of demand (read+write) MSHR miss cycles
2829system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 16452350500 # number of demand (read+write) MSHR miss cycles
2830system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 39372505986 # number of demand (read+write) MSHR miss cycles
2831system.cpu1.l2cache.demand_mshr_miss_latency::total 56464894986 # number of demand (read+write) MSHR miss cycles
2832system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 377290500 # number of overall MSHR miss cycles
2833system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 262748000 # number of overall MSHR miss cycles
2834system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16452350500 # number of overall MSHR miss cycles
2835system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 39372505986 # number of overall MSHR miss cycles
2836system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 36936048403 # number of overall MSHR miss cycles
2837system.cpu1.l2cache.overall_mshr_miss_latency::total 93400943389 # number of overall MSHR miss cycles
2838system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8404500 # number of ReadReq MSHR uncacheable cycles
2839system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 710244000 # number of ReadReq MSHR uncacheable cycles
2840system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 718648500 # number of ReadReq MSHR uncacheable cycles
2841system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 860387000 # number of WriteReq MSHR uncacheable cycles
2842system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 860387000 # number of WriteReq MSHR uncacheable cycles
2843system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8404500 # number of overall MSHR uncacheable cycles
2844system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1570631000 # number of overall MSHR uncacheable cycles
2845system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1579035500 # number of overall MSHR uncacheable cycles
2846system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020679 # mshr miss rate for ReadReq accesses
2847system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.042058 # mshr miss rate for ReadReq accesses
2848system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.026189 # mshr miss rate for ReadReq accesses
2849system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000004 # mshr miss rate for Writeback accesses
2850system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000004 # mshr miss rate for Writeback accesses
2851system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2852system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2853system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2854system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2855system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.680454 # mshr miss rate for UpgradeReq accesses
2856system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.680454 # mshr miss rate for UpgradeReq accesses
2857system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.833371 # mshr miss rate for SCUpgradeReq accesses
2858system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.833371 # mshr miss rate for SCUpgradeReq accesses
2859system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2860system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2861system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.219320 # mshr miss rate for ReadExReq accesses
2862system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.219320 # mshr miss rate for ReadExReq accesses
2863system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.101167 # mshr miss rate for ReadCleanReq accesses
2864system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.101167 # mshr miss rate for ReadCleanReq accesses
2865system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.254968 # mshr miss rate for ReadSharedReq accesses
2866system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254968 # mshr miss rate for ReadSharedReq accesses
2867system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.537852 # mshr miss rate for InvalidateReq accesses
2868system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.537852 # mshr miss rate for InvalidateReq accesses
2869system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020679 # mshr miss rate for demand accesses
2870system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.042058 # mshr miss rate for demand accesses
2871system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.101167 # mshr miss rate for demand accesses
2872system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.246894 # mshr miss rate for demand accesses
2873system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159052 # mshr miss rate for demand accesses
2874system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020679 # mshr miss rate for overall accesses
2875system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.042058 # mshr miss rate for overall accesses
2876system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.101167 # mshr miss rate for overall accesses
2877system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.246894 # mshr miss rate for overall accesses
2878system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2879system.cpu1.l2cache.overall_mshr_miss_rate::total 0.219807 # mshr miss rate for overall accesses
2880system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 35898.239772 # average ReadReq mshr miss latency
2881system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35401.239558 # average ReadReq mshr miss latency
2882system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 35692.532902 # average ReadReq mshr miss latency
2883system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55678.903673 # average HardPFReq mshr miss latency
2884system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55678.903673 # average HardPFReq mshr miss latency
2885system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32979.671319 # average UpgradeReq mshr miss latency
2886system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32979.671319 # average UpgradeReq mshr miss latency
2887system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18419.859853 # average SCUpgradeReq mshr miss latency
2888system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18419.859853 # average SCUpgradeReq mshr miss latency
2889system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 496937.125000 # average SCUpgradeFailReq mshr miss latency
2890system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 496937.125000 # average SCUpgradeFailReq mshr miss latency
2891system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45685.429720 # average ReadExReq mshr miss latency
2892system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45685.429720 # average ReadExReq mshr miss latency
2893system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29329.808020 # average ReadCleanReq mshr miss latency
2894system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29329.808020 # average ReadCleanReq mshr miss latency
2895system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31064.411200 # average ReadSharedReq mshr miss latency
2896system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31064.411200 # average ReadSharedReq mshr miss latency
2897system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 53610.629337 # average InvalidateReq mshr miss latency
2898system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 53610.629337 # average InvalidateReq mshr miss latency
2899system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 35898.239772 # average overall mshr miss latency
2900system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35401.239558 # average overall mshr miss latency
2901system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29329.808020 # average overall mshr miss latency
2902system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34006.016519 # average overall mshr miss latency
2903system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32513.032004 # average overall mshr miss latency
2904system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 35898.239772 # average overall mshr miss latency
2905system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35401.239558 # average overall mshr miss latency
2906system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29329.808020 # average overall mshr miss latency
2907system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34006.016519 # average overall mshr miss latency
2908system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55678.903673 # average overall mshr miss latency
2909system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 38916.070629 # average overall mshr miss latency
2910system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125440.298507 # average ReadReq mshr uncacheable latency
2911system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 104049.809552 # average ReadReq mshr uncacheable latency
2912system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 104257.725228 # average ReadReq mshr uncacheable latency
2913system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 119981.453075 # average WriteReq mshr uncacheable latency
2914system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 119981.453075 # average WriteReq mshr uncacheable latency
2915system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125440.298507 # average overall mshr uncacheable latency
2916system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 112211.973994 # average overall mshr uncacheable latency
2917system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 112274.992890 # average overall mshr uncacheable latency
2918system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2919system.cpu1.toL2Bus.snoop_filter.tot_requests 21930537 # Total number of requests made to the snoop filter.
2920system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11284587 # Number of requests hitting in the snoop filter with a single holder of the requested data.
2921system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1296 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
2922system.cpu1.toL2Bus.snoop_filter.tot_snoops 520648 # Total number of snoops made to the snoop filter.
2923system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 520636 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
2924system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 12 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
2925system.cpu1.toL2Bus.trans_dist::ReadReq 828450 # Transaction distribution
2926system.cpu1.toL2Bus.trans_dist::ReadResp 10092423 # Transaction distribution
2927system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
2928system.cpu1.toL2Bus.trans_dist::WriteReq 7171 # Transaction distribution
2929system.cpu1.toL2Bus.trans_dist::WriteResp 7171 # Transaction distribution
2930system.cpu1.toL2Bus.trans_dist::Writeback 4200793 # Transaction distribution
2931system.cpu1.toL2Bus.trans_dist::CleanEvict 9135588 # Transaction distribution
2932system.cpu1.toL2Bus.trans_dist::HardPFReq 838070 # Transaction distribution
2933system.cpu1.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution
2934system.cpu1.toL2Bus.trans_dist::UpgradeReq 423377 # Transaction distribution
2935system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 345989 # Transaction distribution
2936system.cpu1.toL2Bus.trans_dist::UpgradeResp 462829 # Transaction distribution
2937system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 66 # Transaction distribution
2938system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution
2939system.cpu1.toL2Bus.trans_dist::ReadExReq 1138657 # Transaction distribution
2940system.cpu1.toL2Bus.trans_dist::ReadExResp 1069017 # Transaction distribution
2941system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5544744 # Transaction distribution
2942system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4688366 # Transaction distribution
2943system.cpu1.toL2Bus.trans_dist::InvalidateReq 419379 # Transaction distribution
2944system.cpu1.toL2Bus.trans_dist::InvalidateResp 411859 # Transaction distribution
2945system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16633313 # Packet count per connected master and slave (bytes)
2946system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16198816 # Packet count per connected master and slave (bytes)
2947system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 385145 # Packet count per connected master and slave (bytes)
2948system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1121131 # Packet count per connected master and slave (bytes)
2949system.cpu1.toL2Bus.pkt_count::total 34338405 # Packet count per connected master and slave (bytes)
2950system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 354864624 # Cumulative packet size per connected master and slave (bytes)
2951system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 515112392 # Cumulative packet size per connected master and slave (bytes)
2952system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1411752 # Cumulative packet size per connected master and slave (bytes)
2953system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4066000 # Cumulative packet size per connected master and slave (bytes)
2954system.cpu1.toL2Bus.pkt_size::total 875454768 # Cumulative packet size per connected master and slave (bytes)
2955system.cpu1.toL2Bus.snoops 5438478 # Total snoops (count)
2956system.cpu1.toL2Bus.snoop_fanout::samples 27571945 # Request fanout histogram
2957system.cpu1.toL2Bus.snoop_fanout::mean 0.031057 # Request fanout histogram
2958system.cpu1.toL2Bus.snoop_fanout::stdev 0.173474 # Request fanout histogram
2959system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2960system.cpu1.toL2Bus.snoop_fanout::0 26715663 96.89% 96.89% # Request fanout histogram
2961system.cpu1.toL2Bus.snoop_fanout::1 856270 3.11% 100.00% # Request fanout histogram
2962system.cpu1.toL2Bus.snoop_fanout::2 12 0.00% 100.00% # Request fanout histogram
2963system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2964system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
2965system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2966system.cpu1.toL2Bus.snoop_fanout::total 27571945 # Request fanout histogram
2967system.cpu1.toL2Bus.reqLayer0.occupancy 14479823475 # Layer occupancy (ticks)
2968system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2969system.cpu1.toL2Bus.snoopLayer0.occupancy 180399406 # Layer occupancy (ticks)
2970system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2971system.cpu1.toL2Bus.respLayer0.occupancy 8321735869 # Layer occupancy (ticks)
2972system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2973system.cpu1.toL2Bus.respLayer1.occupancy 7455510168 # Layer occupancy (ticks)
2974system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2975system.cpu1.toL2Bus.respLayer2.occupancy 208987874 # Layer occupancy (ticks)
2976system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2977system.cpu1.toL2Bus.respLayer3.occupancy 613445865 # Layer occupancy (ticks)
2978system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2979system.iobus.trans_dist::ReadReq 40368 # Transaction distribution
2980system.iobus.trans_dist::ReadResp 40368 # Transaction distribution
2981system.iobus.trans_dist::WriteReq 136681 # Transaction distribution
2982system.iobus.trans_dist::WriteResp 136681 # Transaction distribution
2983system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47892 # Packet count per connected master and slave (bytes)
2984system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2985system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2986system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2987system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2988system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2989system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2990system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2991system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2992system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2993system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
2994system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
2995system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2996system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
2997system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
2998system.iobus.pkt_count_system.bridge.master::total 122826 # Packet count per connected master and slave (bytes)
2999system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231192 # Packet count per connected master and slave (bytes)
3000system.iobus.pkt_count_system.realview.ide.dma::total 231192 # Packet count per connected master and slave (bytes)
3001system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
3002system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
3003system.iobus.pkt_count::total 354098 # Packet count per connected master and slave (bytes)
3004system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47912 # Cumulative packet size per connected master and slave (bytes)
3005system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
3006system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
3007system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
3008system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
3009system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
3010system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
3011system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
3012system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
3013system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
3014system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
3015system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
3016system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
3017system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
3018system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
3019system.iobus.pkt_size_system.bridge.master::total 155933 # Cumulative packet size per connected master and slave (bytes)
3020system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338784 # Cumulative packet size per connected master and slave (bytes)
3021system.iobus.pkt_size_system.realview.ide.dma::total 7338784 # Cumulative packet size per connected master and slave (bytes)
3022system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
3023system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
3024system.iobus.pkt_size::total 7496803 # Cumulative packet size per connected master and slave (bytes)
3025system.iobus.reqLayer0.occupancy 36369000 # Layer occupancy (ticks)
3026system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
3027system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
3028system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
3029system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
3030system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
3031system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
3032system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
3033system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
3034system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
3035system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
3036system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
3037system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
3038system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
3039system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
3040system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
3041system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
3042system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
3043system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
3044system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
3045system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks)
3046system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
3047system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
3048system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
3049system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
3050system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
3051system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
3052system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
3053system.iobus.reqLayer27.occupancy 565777885 # Layer occupancy (ticks)
3054system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
3055system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
3056system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
3057system.iobus.respLayer0.occupancy 92876000 # Layer occupancy (ticks)
3058system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
3059system.iobus.respLayer3.occupancy 147888000 # Layer occupancy (ticks)
3060system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
3061system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
3062system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
3063system.iocache.tags.replacements 115577 # number of replacements
3064system.iocache.tags.tagsinuse 11.305567 # Cycle average of tags in use
3065system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
3066system.iocache.tags.sampled_refs 115593 # Sample count of references to valid blocks.
3067system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
3068system.iocache.tags.warmup_cycle 9126912991000 # Cycle when the warmup percentage was hit.
3069system.iocache.tags.occ_blocks::realview.ethernet 3.834509 # Average occupied blocks per requestor
3070system.iocache.tags.occ_blocks::realview.ide 7.471058 # Average occupied blocks per requestor
3071system.iocache.tags.occ_percent::realview.ethernet 0.239657 # Average percentage of cache occupancy
3072system.iocache.tags.occ_percent::realview.ide 0.466941 # Average percentage of cache occupancy
3073system.iocache.tags.occ_percent::total 0.706598 # Average percentage of cache occupancy
3074system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
3075system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
3076system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
3077system.iocache.tags.tag_accesses 1040721 # Number of tag accesses
3078system.iocache.tags.data_accesses 1040721 # Number of data accesses
3079system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
3080system.iocache.ReadReq_misses::realview.ide 8868 # number of ReadReq misses
3081system.iocache.ReadReq_misses::total 8905 # number of ReadReq misses
3082system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
3083system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
3084system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
3085system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
3086system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
3087system.iocache.demand_misses::realview.ide 8868 # number of demand (read+write) misses
3088system.iocache.demand_misses::total 8908 # number of demand (read+write) misses
3089system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
3090system.iocache.overall_misses::realview.ide 8868 # number of overall misses
3091system.iocache.overall_misses::total 8908 # number of overall misses
3092system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles
3093system.iocache.ReadReq_miss_latency::realview.ide 1707562057 # number of ReadReq miss cycles
3094system.iocache.ReadReq_miss_latency::total 1712757057 # number of ReadReq miss cycles
3095system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
3096system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
3097system.iocache.WriteLineReq_miss_latency::realview.ide 13922427828 # number of WriteLineReq miss cycles
3098system.iocache.WriteLineReq_miss_latency::total 13922427828 # number of WriteLineReq miss cycles
3099system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles
3100system.iocache.demand_miss_latency::realview.ide 1707562057 # number of demand (read+write) miss cycles
3101system.iocache.demand_miss_latency::total 1713126057 # number of demand (read+write) miss cycles
3102system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles
3103system.iocache.overall_miss_latency::realview.ide 1707562057 # number of overall miss cycles
3104system.iocache.overall_miss_latency::total 1713126057 # number of overall miss cycles
3105system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
3106system.iocache.ReadReq_accesses::realview.ide 8868 # number of ReadReq accesses(hits+misses)
3107system.iocache.ReadReq_accesses::total 8905 # number of ReadReq accesses(hits+misses)
3108system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
3109system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
3110system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
3111system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
3112system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
3113system.iocache.demand_accesses::realview.ide 8868 # number of demand (read+write) accesses
3114system.iocache.demand_accesses::total 8908 # number of demand (read+write) accesses
3115system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
3116system.iocache.overall_accesses::realview.ide 8868 # number of overall (read+write) accesses
3117system.iocache.overall_accesses::total 8908 # number of overall (read+write) accesses
3118system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
3119system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
3120system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
3121system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
3122system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
3123system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
3124system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
3125system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
3126system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
3127system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
3128system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
3129system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
3130system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
3131system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency
3132system.iocache.ReadReq_avg_miss_latency::realview.ide 192553.231507 # average ReadReq miss latency
3133system.iocache.ReadReq_avg_miss_latency::total 192336.558899 # average ReadReq miss latency
3134system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
3135system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
3136system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130447.753429 # average WriteLineReq miss latency
3137system.iocache.WriteLineReq_avg_miss_latency::total 130447.753429 # average WriteLineReq miss latency
3138system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency
3139system.iocache.demand_avg_miss_latency::realview.ide 192553.231507 # average overall miss latency
3140system.iocache.demand_avg_miss_latency::total 192313.208015 # average overall miss latency
3141system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency
3142system.iocache.overall_avg_miss_latency::realview.ide 192553.231507 # average overall miss latency
3143system.iocache.overall_avg_miss_latency::total 192313.208015 # average overall miss latency
3144system.iocache.blocked_cycles::no_mshrs 35527 # number of cycles access was blocked
3145system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
3146system.iocache.blocked::no_mshrs 3511 # number of cycles access was blocked
3147system.iocache.blocked::no_targets 0 # number of cycles access was blocked
3148system.iocache.avg_blocked_cycles::no_mshrs 10.118770 # average number of cycles each access was blocked
3149system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3150system.iocache.fast_writes 0 # number of fast writes performed
3151system.iocache.cache_copies 0 # number of cache copies performed
3152system.iocache.writebacks::writebacks 106694 # number of writebacks
3153system.iocache.writebacks::total 106694 # number of writebacks
3154system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
3155system.iocache.ReadReq_mshr_misses::realview.ide 8868 # number of ReadReq MSHR misses
3156system.iocache.ReadReq_mshr_misses::total 8905 # number of ReadReq MSHR misses
3157system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
3158system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
3159system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
3160system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
3161system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
3162system.iocache.demand_mshr_misses::realview.ide 8868 # number of demand (read+write) MSHR misses
3163system.iocache.demand_mshr_misses::total 8908 # number of demand (read+write) MSHR misses
3164system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
3165system.iocache.overall_mshr_misses::realview.ide 8868 # number of overall MSHR misses
3166system.iocache.overall_mshr_misses::total 8908 # number of overall MSHR misses
3167system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles
3168system.iocache.ReadReq_mshr_miss_latency::realview.ide 1264162057 # number of ReadReq MSHR miss cycles
3169system.iocache.ReadReq_mshr_miss_latency::total 1267507057 # number of ReadReq MSHR miss cycles
3170system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
3171system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
3172system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8586027828 # number of WriteLineReq MSHR miss cycles
3173system.iocache.WriteLineReq_mshr_miss_latency::total 8586027828 # number of WriteLineReq MSHR miss cycles
3174system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles
3175system.iocache.demand_mshr_miss_latency::realview.ide 1264162057 # number of demand (read+write) MSHR miss cycles
3176system.iocache.demand_mshr_miss_latency::total 1267726057 # number of demand (read+write) MSHR miss cycles
3177system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles
3178system.iocache.overall_mshr_miss_latency::realview.ide 1264162057 # number of overall MSHR miss cycles
3179system.iocache.overall_mshr_miss_latency::total 1267726057 # number of overall MSHR miss cycles
3180system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
3181system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
3182system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
3183system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
3184system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
3185system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
3186system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
3187system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
3188system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
3189system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
3190system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
3191system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
3192system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
3193system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency
3194system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142553.231507 # average ReadReq mshr miss latency
3195system.iocache.ReadReq_avg_mshr_miss_latency::total 142336.558899 # average ReadReq mshr miss latency
3196system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
3197system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
3198system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80447.753429 # average WriteLineReq mshr miss latency
3199system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80447.753429 # average WriteLineReq mshr miss latency
3200system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency
3201system.iocache.demand_avg_mshr_miss_latency::realview.ide 142553.231507 # average overall mshr miss latency
3202system.iocache.demand_avg_mshr_miss_latency::total 142313.208015 # average overall mshr miss latency
3203system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency
3204system.iocache.overall_avg_mshr_miss_latency::realview.ide 142553.231507 # average overall mshr miss latency
3205system.iocache.overall_avg_mshr_miss_latency::total 142313.208015 # average overall mshr miss latency
3206system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
3207system.l2c.tags.replacements 1523284 # number of replacements
3208system.l2c.tags.tagsinuse 63784.617798 # Cycle average of tags in use
3209system.l2c.tags.total_refs 5785768 # Total number of references to valid blocks.
3210system.l2c.tags.sampled_refs 1584080 # Sample count of references to valid blocks.
3211system.l2c.tags.avg_refs 3.652447 # Average number of references to valid blocks.
3212system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
3213system.l2c.tags.occ_blocks::writebacks 17262.204967 # Average occupied blocks per requestor
3214system.l2c.tags.occ_blocks::cpu0.dtb.walker 288.051541 # Average occupied blocks per requestor
3215system.l2c.tags.occ_blocks::cpu0.itb.walker 383.464514 # Average occupied blocks per requestor
3216system.l2c.tags.occ_blocks::cpu0.inst 4972.263689 # Average occupied blocks per requestor
3217system.l2c.tags.occ_blocks::cpu0.data 12806.585942 # Average occupied blocks per requestor
3218system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 17387.012671 # Average occupied blocks per requestor
3219system.l2c.tags.occ_blocks::cpu1.dtb.walker 85.287470 # Average occupied blocks per requestor
3220system.l2c.tags.occ_blocks::cpu1.itb.walker 93.857044 # Average occupied blocks per requestor
3221system.l2c.tags.occ_blocks::cpu1.inst 2455.379438 # Average occupied blocks per requestor
3222system.l2c.tags.occ_blocks::cpu1.data 4782.512624 # Average occupied blocks per requestor
3223system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3267.997898 # Average occupied blocks per requestor
3224system.l2c.tags.occ_percent::writebacks 0.263400 # Average percentage of cache occupancy
3225system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004395 # Average percentage of cache occupancy
3226system.l2c.tags.occ_percent::cpu0.itb.walker 0.005851 # Average percentage of cache occupancy
3227system.l2c.tags.occ_percent::cpu0.inst 0.075871 # Average percentage of cache occupancy
3228system.l2c.tags.occ_percent::cpu0.data 0.195413 # Average percentage of cache occupancy
3229system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.265305 # Average percentage of cache occupancy
3230system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001301 # Average percentage of cache occupancy
3231system.l2c.tags.occ_percent::cpu1.itb.walker 0.001432 # Average percentage of cache occupancy
3232system.l2c.tags.occ_percent::cpu1.inst 0.037466 # Average percentage of cache occupancy
3233system.l2c.tags.occ_percent::cpu1.data 0.072975 # Average percentage of cache occupancy
3234system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.049866 # Average percentage of cache occupancy
3235system.l2c.tags.occ_percent::total 0.973276 # Average percentage of cache occupancy
3236system.l2c.tags.occ_task_id_blocks::1022 10918 # Occupied blocks per task id
3237system.l2c.tags.occ_task_id_blocks::1023 244 # Occupied blocks per task id
3238system.l2c.tags.occ_task_id_blocks::1024 49634 # Occupied blocks per task id
3239system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
3240system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id
3241system.l2c.tags.age_task_id_blocks_1022::2 1058 # Occupied blocks per task id
3242system.l2c.tags.age_task_id_blocks_1022::3 384 # Occupied blocks per task id
3243system.l2c.tags.age_task_id_blocks_1022::4 9467 # Occupied blocks per task id
3244system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id
3245system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
3246system.l2c.tags.age_task_id_blocks_1023::4 241 # Occupied blocks per task id
3247system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
3248system.l2c.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id
3249system.l2c.tags.age_task_id_blocks_1024::2 2538 # Occupied blocks per task id
3250system.l2c.tags.age_task_id_blocks_1024::3 5035 # Occupied blocks per task id
3251system.l2c.tags.age_task_id_blocks_1024::4 41740 # Occupied blocks per task id
3252system.l2c.tags.occ_task_id_percent::1022 0.166595 # Percentage of cache occupancy per task id
3253system.l2c.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id
3254system.l2c.tags.occ_task_id_percent::1024 0.757355 # Percentage of cache occupancy per task id
3255system.l2c.tags.tag_accesses 71725289 # Number of tag accesses
3256system.l2c.tags.data_accesses 71725289 # Number of data accesses
3257system.l2c.Writeback_hits::writebacks 2493194 # number of Writeback hits
3258system.l2c.Writeback_hits::total 2493194 # number of Writeback hits
3259system.l2c.UpgradeReq_hits::cpu0.data 29135 # number of UpgradeReq hits
3260system.l2c.UpgradeReq_hits::cpu1.data 32441 # number of UpgradeReq hits
3261system.l2c.UpgradeReq_hits::total 61576 # number of UpgradeReq hits
3262system.l2c.SCUpgradeReq_hits::cpu0.data 6380 # number of SCUpgradeReq hits
3263system.l2c.SCUpgradeReq_hits::cpu1.data 5628 # number of SCUpgradeReq hits
3264system.l2c.SCUpgradeReq_hits::total 12008 # number of SCUpgradeReq hits
3265system.l2c.ReadExReq_hits::cpu0.data 165668 # number of ReadExReq hits
3266system.l2c.ReadExReq_hits::cpu1.data 160581 # number of ReadExReq hits
3267system.l2c.ReadExReq_hits::total 326249 # number of ReadExReq hits
3268system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6589 # number of ReadSharedReq hits
3269system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4357 # number of ReadSharedReq hits
3270system.l2c.ReadSharedReq_hits::cpu0.inst 618480 # number of ReadSharedReq hits
3271system.l2c.ReadSharedReq_hits::cpu0.data 631164 # number of ReadSharedReq hits
3272system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 297252 # number of ReadSharedReq hits
3273system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 5967 # number of ReadSharedReq hits
3274system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4162 # number of ReadSharedReq hits
3275system.l2c.ReadSharedReq_hits::cpu1.inst 524459 # number of ReadSharedReq hits
3276system.l2c.ReadSharedReq_hits::cpu1.data 533369 # number of ReadSharedReq hits
3277system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 294077 # number of ReadSharedReq hits
3278system.l2c.ReadSharedReq_hits::total 2919876 # number of ReadSharedReq hits
3279system.l2c.demand_hits::cpu0.dtb.walker 6589 # number of demand (read+write) hits
3280system.l2c.demand_hits::cpu0.itb.walker 4357 # number of demand (read+write) hits
3281system.l2c.demand_hits::cpu0.inst 618480 # number of demand (read+write) hits
3282system.l2c.demand_hits::cpu0.data 796832 # number of demand (read+write) hits
3283system.l2c.demand_hits::cpu0.l2cache.prefetcher 297252 # number of demand (read+write) hits
3284system.l2c.demand_hits::cpu1.dtb.walker 5967 # number of demand (read+write) hits
3285system.l2c.demand_hits::cpu1.itb.walker 4162 # number of demand (read+write) hits
3286system.l2c.demand_hits::cpu1.inst 524459 # number of demand (read+write) hits
3287system.l2c.demand_hits::cpu1.data 693950 # number of demand (read+write) hits
3288system.l2c.demand_hits::cpu1.l2cache.prefetcher 294077 # number of demand (read+write) hits
3289system.l2c.demand_hits::total 3246125 # number of demand (read+write) hits
3290system.l2c.overall_hits::cpu0.dtb.walker 6589 # number of overall hits
3291system.l2c.overall_hits::cpu0.itb.walker 4357 # number of overall hits
3292system.l2c.overall_hits::cpu0.inst 618480 # number of overall hits
3293system.l2c.overall_hits::cpu0.data 796832 # number of overall hits
3294system.l2c.overall_hits::cpu0.l2cache.prefetcher 297252 # number of overall hits
3295system.l2c.overall_hits::cpu1.dtb.walker 5967 # number of overall hits
3296system.l2c.overall_hits::cpu1.itb.walker 4162 # number of overall hits
3297system.l2c.overall_hits::cpu1.inst 524459 # number of overall hits
3298system.l2c.overall_hits::cpu1.data 693950 # number of overall hits
3299system.l2c.overall_hits::cpu1.l2cache.prefetcher 294077 # number of overall hits
3300system.l2c.overall_hits::total 3246125 # number of overall hits
3301system.l2c.UpgradeReq_misses::cpu0.data 49689 # number of UpgradeReq misses
3302system.l2c.UpgradeReq_misses::cpu1.data 45204 # number of UpgradeReq misses
3303system.l2c.UpgradeReq_misses::total 94893 # number of UpgradeReq misses
3304system.l2c.SCUpgradeReq_misses::cpu0.data 10659 # number of SCUpgradeReq misses
3305system.l2c.SCUpgradeReq_misses::cpu1.data 8662 # number of SCUpgradeReq misses
3306system.l2c.SCUpgradeReq_misses::total 19321 # number of SCUpgradeReq misses
3307system.l2c.ReadExReq_misses::cpu0.data 547046 # number of ReadExReq misses
3308system.l2c.ReadExReq_misses::cpu1.data 101994 # number of ReadExReq misses
3309system.l2c.ReadExReq_misses::total 649040 # number of ReadExReq misses
3310system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3253 # number of ReadSharedReq misses
3311system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3182 # number of ReadSharedReq misses
3312system.l2c.ReadSharedReq_misses::cpu0.inst 67580 # number of ReadSharedReq misses
3313system.l2c.ReadSharedReq_misses::cpu0.data 173763 # number of ReadSharedReq misses
3314system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 345323 # number of ReadSharedReq misses
3315system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1427 # number of ReadSharedReq misses
3316system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1037 # number of ReadSharedReq misses
3317system.l2c.ReadSharedReq_misses::cpu1.inst 36484 # number of ReadSharedReq misses
3318system.l2c.ReadSharedReq_misses::cpu1.data 93466 # number of ReadSharedReq misses
3319system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 171017 # number of ReadSharedReq misses
3320system.l2c.ReadSharedReq_misses::total 896532 # number of ReadSharedReq misses
3321system.l2c.demand_misses::cpu0.dtb.walker 3253 # number of demand (read+write) misses
3322system.l2c.demand_misses::cpu0.itb.walker 3182 # number of demand (read+write) misses
3323system.l2c.demand_misses::cpu0.inst 67580 # number of demand (read+write) misses
3324system.l2c.demand_misses::cpu0.data 720809 # number of demand (read+write) misses
3325system.l2c.demand_misses::cpu0.l2cache.prefetcher 345323 # number of demand (read+write) misses
3326system.l2c.demand_misses::cpu1.dtb.walker 1427 # number of demand (read+write) misses
3327system.l2c.demand_misses::cpu1.itb.walker 1037 # number of demand (read+write) misses
3328system.l2c.demand_misses::cpu1.inst 36484 # number of demand (read+write) misses
3329system.l2c.demand_misses::cpu1.data 195460 # number of demand (read+write) misses
3330system.l2c.demand_misses::cpu1.l2cache.prefetcher 171017 # number of demand (read+write) misses
3331system.l2c.demand_misses::total 1545572 # number of demand (read+write) misses
3332system.l2c.overall_misses::cpu0.dtb.walker 3253 # number of overall misses
3333system.l2c.overall_misses::cpu0.itb.walker 3182 # number of overall misses
3334system.l2c.overall_misses::cpu0.inst 67580 # number of overall misses
3335system.l2c.overall_misses::cpu0.data 720809 # number of overall misses
3336system.l2c.overall_misses::cpu0.l2cache.prefetcher 345323 # number of overall misses
3337system.l2c.overall_misses::cpu1.dtb.walker 1427 # number of overall misses
3338system.l2c.overall_misses::cpu1.itb.walker 1037 # number of overall misses
3339system.l2c.overall_misses::cpu1.inst 36484 # number of overall misses
3340system.l2c.overall_misses::cpu1.data 195460 # number of overall misses
3341system.l2c.overall_misses::cpu1.l2cache.prefetcher 171017 # number of overall misses
3342system.l2c.overall_misses::total 1545572 # number of overall misses
3343system.l2c.UpgradeReq_miss_latency::cpu0.data 823665000 # number of UpgradeReq miss cycles
3344system.l2c.UpgradeReq_miss_latency::cpu1.data 712158000 # number of UpgradeReq miss cycles
3345system.l2c.UpgradeReq_miss_latency::total 1535823000 # number of UpgradeReq miss cycles
3346system.l2c.SCUpgradeReq_miss_latency::cpu0.data 169857000 # number of SCUpgradeReq miss cycles
3347system.l2c.SCUpgradeReq_miss_latency::cpu1.data 128692500 # number of SCUpgradeReq miss cycles
3348system.l2c.SCUpgradeReq_miss_latency::total 298549500 # number of SCUpgradeReq miss cycles
3349system.l2c.ReadExReq_miss_latency::cpu0.data 97772317996 # number of ReadExReq miss cycles
3350system.l2c.ReadExReq_miss_latency::cpu1.data 15251359498 # number of ReadExReq miss cycles
3351system.l2c.ReadExReq_miss_latency::total 113023677494 # number of ReadExReq miss cycles
3352system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 459886500 # number of ReadSharedReq miss cycles
3353system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 447245500 # number of ReadSharedReq miss cycles
3354system.l2c.ReadSharedReq_miss_latency::cpu0.inst 9268037502 # number of ReadSharedReq miss cycles
3355system.l2c.ReadSharedReq_miss_latency::cpu0.data 25632017498 # number of ReadSharedReq miss cycles
3356system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 63422033653 # number of ReadSharedReq miss cycles
3357system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 210125000 # number of ReadSharedReq miss cycles
3358system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 151697000 # number of ReadSharedReq miss cycles
3359system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5011265500 # number of ReadSharedReq miss cycles
3360system.l2c.ReadSharedReq_miss_latency::cpu1.data 13524553500 # number of ReadSharedReq miss cycles
3361system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 31614845146 # number of ReadSharedReq miss cycles
3362system.l2c.ReadSharedReq_miss_latency::total 149741706799 # number of ReadSharedReq miss cycles
3363system.l2c.demand_miss_latency::cpu0.dtb.walker 459886500 # number of demand (read+write) miss cycles
3364system.l2c.demand_miss_latency::cpu0.itb.walker 447245500 # number of demand (read+write) miss cycles
3365system.l2c.demand_miss_latency::cpu0.inst 9268037502 # number of demand (read+write) miss cycles
3366system.l2c.demand_miss_latency::cpu0.data 123404335494 # number of demand (read+write) miss cycles
3367system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 63422033653 # number of demand (read+write) miss cycles
3368system.l2c.demand_miss_latency::cpu1.dtb.walker 210125000 # number of demand (read+write) miss cycles
3369system.l2c.demand_miss_latency::cpu1.itb.walker 151697000 # number of demand (read+write) miss cycles
3370system.l2c.demand_miss_latency::cpu1.inst 5011265500 # number of demand (read+write) miss cycles
3371system.l2c.demand_miss_latency::cpu1.data 28775912998 # number of demand (read+write) miss cycles
3372system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 31614845146 # number of demand (read+write) miss cycles
3373system.l2c.demand_miss_latency::total 262765384293 # number of demand (read+write) miss cycles
3374system.l2c.overall_miss_latency::cpu0.dtb.walker 459886500 # number of overall miss cycles
3375system.l2c.overall_miss_latency::cpu0.itb.walker 447245500 # number of overall miss cycles
3376system.l2c.overall_miss_latency::cpu0.inst 9268037502 # number of overall miss cycles
3377system.l2c.overall_miss_latency::cpu0.data 123404335494 # number of overall miss cycles
3378system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 63422033653 # number of overall miss cycles
3379system.l2c.overall_miss_latency::cpu1.dtb.walker 210125000 # number of overall miss cycles
3380system.l2c.overall_miss_latency::cpu1.itb.walker 151697000 # number of overall miss cycles
3381system.l2c.overall_miss_latency::cpu1.inst 5011265500 # number of overall miss cycles
3382system.l2c.overall_miss_latency::cpu1.data 28775912998 # number of overall miss cycles
3383system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 31614845146 # number of overall miss cycles
3384system.l2c.overall_miss_latency::total 262765384293 # number of overall miss cycles
3385system.l2c.Writeback_accesses::writebacks 2493194 # number of Writeback accesses(hits+misses)
3386system.l2c.Writeback_accesses::total 2493194 # number of Writeback accesses(hits+misses)
3387system.l2c.UpgradeReq_accesses::cpu0.data 78824 # number of UpgradeReq accesses(hits+misses)
3388system.l2c.UpgradeReq_accesses::cpu1.data 77645 # number of UpgradeReq accesses(hits+misses)
3389system.l2c.UpgradeReq_accesses::total 156469 # number of UpgradeReq accesses(hits+misses)
3390system.l2c.SCUpgradeReq_accesses::cpu0.data 17039 # number of SCUpgradeReq accesses(hits+misses)
3391system.l2c.SCUpgradeReq_accesses::cpu1.data 14290 # number of SCUpgradeReq accesses(hits+misses)
3392system.l2c.SCUpgradeReq_accesses::total 31329 # number of SCUpgradeReq accesses(hits+misses)
3393system.l2c.ReadExReq_accesses::cpu0.data 712714 # number of ReadExReq accesses(hits+misses)
3394system.l2c.ReadExReq_accesses::cpu1.data 262575 # number of ReadExReq accesses(hits+misses)
3395system.l2c.ReadExReq_accesses::total 975289 # number of ReadExReq accesses(hits+misses)
3396system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 9842 # number of ReadSharedReq accesses(hits+misses)
3397system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7539 # number of ReadSharedReq accesses(hits+misses)
3398system.l2c.ReadSharedReq_accesses::cpu0.inst 686060 # number of ReadSharedReq accesses(hits+misses)
3399system.l2c.ReadSharedReq_accesses::cpu0.data 804927 # number of ReadSharedReq accesses(hits+misses)
3400system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 642575 # number of ReadSharedReq accesses(hits+misses)
3401system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 7394 # number of ReadSharedReq accesses(hits+misses)
3402system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 5199 # number of ReadSharedReq accesses(hits+misses)
3403system.l2c.ReadSharedReq_accesses::cpu1.inst 560943 # number of ReadSharedReq accesses(hits+misses)
3404system.l2c.ReadSharedReq_accesses::cpu1.data 626835 # number of ReadSharedReq accesses(hits+misses)
3405system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 465094 # number of ReadSharedReq accesses(hits+misses)
3406system.l2c.ReadSharedReq_accesses::total 3816408 # number of ReadSharedReq accesses(hits+misses)
3407system.l2c.demand_accesses::cpu0.dtb.walker 9842 # number of demand (read+write) accesses
3408system.l2c.demand_accesses::cpu0.itb.walker 7539 # number of demand (read+write) accesses
3409system.l2c.demand_accesses::cpu0.inst 686060 # number of demand (read+write) accesses
3410system.l2c.demand_accesses::cpu0.data 1517641 # number of demand (read+write) accesses
3411system.l2c.demand_accesses::cpu0.l2cache.prefetcher 642575 # number of demand (read+write) accesses
3412system.l2c.demand_accesses::cpu1.dtb.walker 7394 # number of demand (read+write) accesses
3413system.l2c.demand_accesses::cpu1.itb.walker 5199 # number of demand (read+write) accesses
3414system.l2c.demand_accesses::cpu1.inst 560943 # number of demand (read+write) accesses
3415system.l2c.demand_accesses::cpu1.data 889410 # number of demand (read+write) accesses
3416system.l2c.demand_accesses::cpu1.l2cache.prefetcher 465094 # number of demand (read+write) accesses
3417system.l2c.demand_accesses::total 4791697 # number of demand (read+write) accesses
3418system.l2c.overall_accesses::cpu0.dtb.walker 9842 # number of overall (read+write) accesses
3419system.l2c.overall_accesses::cpu0.itb.walker 7539 # number of overall (read+write) accesses
3420system.l2c.overall_accesses::cpu0.inst 686060 # number of overall (read+write) accesses
3421system.l2c.overall_accesses::cpu0.data 1517641 # number of overall (read+write) accesses
3422system.l2c.overall_accesses::cpu0.l2cache.prefetcher 642575 # number of overall (read+write) accesses
3423system.l2c.overall_accesses::cpu1.dtb.walker 7394 # number of overall (read+write) accesses
3424system.l2c.overall_accesses::cpu1.itb.walker 5199 # number of overall (read+write) accesses
3425system.l2c.overall_accesses::cpu1.inst 560943 # number of overall (read+write) accesses
3426system.l2c.overall_accesses::cpu1.data 889410 # number of overall (read+write) accesses
3427system.l2c.overall_accesses::cpu1.l2cache.prefetcher 465094 # number of overall (read+write) accesses
3428system.l2c.overall_accesses::total 4791697 # number of overall (read+write) accesses
3429system.l2c.UpgradeReq_miss_rate::cpu0.data 0.630379 # miss rate for UpgradeReq accesses
3430system.l2c.UpgradeReq_miss_rate::cpu1.data 0.582188 # miss rate for UpgradeReq accesses
3431system.l2c.UpgradeReq_miss_rate::total 0.606465 # miss rate for UpgradeReq accesses
3432system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.625565 # miss rate for SCUpgradeReq accesses
3433system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.606158 # miss rate for SCUpgradeReq accesses
3434system.l2c.SCUpgradeReq_miss_rate::total 0.616713 # miss rate for SCUpgradeReq accesses
3435system.l2c.ReadExReq_miss_rate::cpu0.data 0.767553 # miss rate for ReadExReq accesses
3436system.l2c.ReadExReq_miss_rate::cpu1.data 0.388438 # miss rate for ReadExReq accesses
3437system.l2c.ReadExReq_miss_rate::total 0.665485 # miss rate for ReadExReq accesses
3438system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.330522 # miss rate for ReadSharedReq accesses
3439system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.422072 # miss rate for ReadSharedReq accesses
3440system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.098505 # miss rate for ReadSharedReq accesses
3441system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.215874 # miss rate for ReadSharedReq accesses
3442system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.537405 # miss rate for ReadSharedReq accesses
3443system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.192994 # miss rate for ReadSharedReq accesses
3444system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.199461 # miss rate for ReadSharedReq accesses
3445system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.065040 # miss rate for ReadSharedReq accesses
3446system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.149108 # miss rate for ReadSharedReq accesses
3447system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.367704 # miss rate for ReadSharedReq accesses
3448system.l2c.ReadSharedReq_miss_rate::total 0.234915 # miss rate for ReadSharedReq accesses
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3450system.l2c.demand_miss_rate::cpu0.itb.walker 0.422072 # miss rate for demand accesses
3451system.l2c.demand_miss_rate::cpu0.inst 0.098505 # miss rate for demand accesses
3452system.l2c.demand_miss_rate::cpu0.data 0.474954 # miss rate for demand accesses
3453system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.537405 # miss rate for demand accesses
3454system.l2c.demand_miss_rate::cpu1.dtb.walker 0.192994 # miss rate for demand accesses
3455system.l2c.demand_miss_rate::cpu1.itb.walker 0.199461 # miss rate for demand accesses
3456system.l2c.demand_miss_rate::cpu1.inst 0.065040 # miss rate for demand accesses
3457system.l2c.demand_miss_rate::cpu1.data 0.219764 # miss rate for demand accesses
3458system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.367704 # miss rate for demand accesses
3459system.l2c.demand_miss_rate::total 0.322552 # miss rate for demand accesses
3460system.l2c.overall_miss_rate::cpu0.dtb.walker 0.330522 # miss rate for overall accesses
3461system.l2c.overall_miss_rate::cpu0.itb.walker 0.422072 # miss rate for overall accesses
3462system.l2c.overall_miss_rate::cpu0.inst 0.098505 # miss rate for overall accesses
3463system.l2c.overall_miss_rate::cpu0.data 0.474954 # miss rate for overall accesses
3464system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.537405 # miss rate for overall accesses
3465system.l2c.overall_miss_rate::cpu1.dtb.walker 0.192994 # miss rate for overall accesses
3466system.l2c.overall_miss_rate::cpu1.itb.walker 0.199461 # miss rate for overall accesses
3467system.l2c.overall_miss_rate::cpu1.inst 0.065040 # miss rate for overall accesses
3468system.l2c.overall_miss_rate::cpu1.data 0.219764 # miss rate for overall accesses
3469system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.367704 # miss rate for overall accesses
3470system.l2c.overall_miss_rate::total 0.322552 # miss rate for overall accesses
3471system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16576.405241 # average UpgradeReq miss latency
3472system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15754.313778 # average UpgradeReq miss latency
3473system.l2c.UpgradeReq_avg_miss_latency::total 16184.787076 # average UpgradeReq miss latency
3474system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15935.547425 # average SCUpgradeReq miss latency
3475system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 14857.134611 # average SCUpgradeReq miss latency
3476system.l2c.SCUpgradeReq_avg_miss_latency::total 15452.072874 # average SCUpgradeReq miss latency
3477system.l2c.ReadExReq_avg_miss_latency::cpu0.data 178727.781569 # average ReadExReq miss latency
3478system.l2c.ReadExReq_avg_miss_latency::cpu1.data 149531.928329 # average ReadExReq miss latency
3479system.l2c.ReadExReq_avg_miss_latency::total 174139.771808 # average ReadExReq miss latency
3480system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 141373.040271 # average ReadSharedReq miss latency
3481system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 140554.839723 # average ReadSharedReq miss latency
3482system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 137141.720953 # average ReadSharedReq miss latency
3483system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 147511.366045 # average ReadSharedReq miss latency
3484system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 183660.033224 # average ReadSharedReq miss latency
3485system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 147249.474422 # average ReadSharedReq miss latency
3486system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 146284.474446 # average ReadSharedReq miss latency
3487system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137355.155685 # average ReadSharedReq miss latency
3488system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 144700.249289 # average ReadSharedReq miss latency
3489system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 184863.757088 # average ReadSharedReq miss latency
3490system.l2c.ReadSharedReq_avg_miss_latency::total 167023.270557 # average ReadSharedReq miss latency
3491system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 141373.040271 # average overall miss latency
3492system.l2c.demand_avg_miss_latency::cpu0.itb.walker 140554.839723 # average overall miss latency
3493system.l2c.demand_avg_miss_latency::cpu0.inst 137141.720953 # average overall miss latency
3494system.l2c.demand_avg_miss_latency::cpu0.data 171202.545326 # average overall miss latency
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3496system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 147249.474422 # average overall miss latency
3497system.l2c.demand_avg_miss_latency::cpu1.itb.walker 146284.474446 # average overall miss latency
3498system.l2c.demand_avg_miss_latency::cpu1.inst 137355.155685 # average overall miss latency
3499system.l2c.demand_avg_miss_latency::cpu1.data 147221.492878 # average overall miss latency
3500system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 184863.757088 # average overall miss latency
3501system.l2c.demand_avg_miss_latency::total 170011.739533 # average overall miss latency
3502system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 141373.040271 # average overall miss latency
3503system.l2c.overall_avg_miss_latency::cpu0.itb.walker 140554.839723 # average overall miss latency
3504system.l2c.overall_avg_miss_latency::cpu0.inst 137141.720953 # average overall miss latency
3505system.l2c.overall_avg_miss_latency::cpu0.data 171202.545326 # average overall miss latency
3506system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 183660.033224 # average overall miss latency
3507system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 147249.474422 # average overall miss latency
3508system.l2c.overall_avg_miss_latency::cpu1.itb.walker 146284.474446 # average overall miss latency
3509system.l2c.overall_avg_miss_latency::cpu1.inst 137355.155685 # average overall miss latency
3510system.l2c.overall_avg_miss_latency::cpu1.data 147221.492878 # average overall miss latency
3511system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 184863.757088 # average overall miss latency
3512system.l2c.overall_avg_miss_latency::total 170011.739533 # average overall miss latency
3513system.l2c.blocked_cycles::no_mshrs 10627 # number of cycles access was blocked
3514system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
3515system.l2c.blocked::no_mshrs 95 # number of cycles access was blocked
3516system.l2c.blocked::no_targets 0 # number of cycles access was blocked
3517system.l2c.avg_blocked_cycles::no_mshrs 111.863158 # average number of cycles each access was blocked
3518system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3519system.l2c.fast_writes 0 # number of fast writes performed
3520system.l2c.cache_copies 0 # number of cache copies performed
3521system.l2c.writebacks::writebacks 1190221 # number of writebacks
3522system.l2c.writebacks::total 1190221 # number of writebacks
3523system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 97 # number of ReadSharedReq MSHR hits
3524system.l2c.ReadSharedReq_mshr_hits::cpu0.data 21 # number of ReadSharedReq MSHR hits
3525system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 189 # number of ReadSharedReq MSHR hits
3526system.l2c.ReadSharedReq_mshr_hits::cpu1.data 20 # number of ReadSharedReq MSHR hits
3527system.l2c.ReadSharedReq_mshr_hits::total 327 # number of ReadSharedReq MSHR hits
3528system.l2c.demand_mshr_hits::cpu0.inst 97 # number of demand (read+write) MSHR hits
3529system.l2c.demand_mshr_hits::cpu0.data 21 # number of demand (read+write) MSHR hits
3530system.l2c.demand_mshr_hits::cpu1.inst 189 # number of demand (read+write) MSHR hits
3531system.l2c.demand_mshr_hits::cpu1.data 20 # number of demand (read+write) MSHR hits
3532system.l2c.demand_mshr_hits::total 327 # number of demand (read+write) MSHR hits
3533system.l2c.overall_mshr_hits::cpu0.inst 97 # number of overall MSHR hits
3534system.l2c.overall_mshr_hits::cpu0.data 21 # number of overall MSHR hits
3535system.l2c.overall_mshr_hits::cpu1.inst 189 # number of overall MSHR hits
3536system.l2c.overall_mshr_hits::cpu1.data 20 # number of overall MSHR hits
3537system.l2c.overall_mshr_hits::total 327 # number of overall MSHR hits
3538system.l2c.CleanEvict_mshr_misses::writebacks 49518 # number of CleanEvict MSHR misses
3539system.l2c.CleanEvict_mshr_misses::total 49518 # number of CleanEvict MSHR misses
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3556system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 36295 # number of ReadSharedReq MSHR misses
3557system.l2c.ReadSharedReq_mshr_misses::cpu1.data 93446 # number of ReadSharedReq MSHR misses
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3559system.l2c.ReadSharedReq_mshr_misses::total 896205 # number of ReadSharedReq MSHR misses
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3562system.l2c.demand_mshr_misses::cpu0.inst 67483 # number of demand (read+write) MSHR misses
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3565system.l2c.demand_mshr_misses::cpu1.dtb.walker 1427 # number of demand (read+write) MSHR misses
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3567system.l2c.demand_mshr_misses::cpu1.inst 36295 # number of demand (read+write) MSHR misses
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3581system.l2c.overall_mshr_misses::total 1545245 # number of overall MSHR misses
3582system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable
3583system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31951 # number of ReadReq MSHR uncacheable
3584system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
3585system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6824 # number of ReadReq MSHR uncacheable
3586system.l2c.ReadReq_mshr_uncacheable::total 60136 # number of ReadReq MSHR uncacheable
3587system.l2c.WriteReq_mshr_uncacheable::cpu0.data 31485 # number of WriteReq MSHR uncacheable
3588system.l2c.WriteReq_mshr_uncacheable::cpu1.data 7171 # number of WriteReq MSHR uncacheable
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3591system.l2c.overall_mshr_uncacheable_misses::cpu0.data 63436 # number of overall MSHR uncacheable misses
3592system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
3593system.l2c.overall_mshr_uncacheable_misses::cpu1.data 13995 # number of overall MSHR uncacheable misses
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3595system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 3656557006 # number of UpgradeReq MSHR miss cycles
3596system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3330209007 # number of UpgradeReq MSHR miss cycles
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3598system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 815429503 # number of SCUpgradeReq MSHR miss cycles
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3615system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 427356500 # number of demand (read+write) MSHR miss cycles
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3619system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 59968803653 # number of demand (read+write) MSHR miss cycles
3620system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 195855000 # number of demand (read+write) MSHR miss cycles
3621system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 141327000 # number of demand (read+write) MSHR miss cycles
3622system.l2c.demand_mshr_miss_latency::cpu1.inst 4625471500 # number of demand (read+write) MSHR miss cycles
3623system.l2c.demand_mshr_miss_latency::cpu1.data 26819057998 # number of demand (read+write) MSHR miss cycles
3624system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 29904675146 # number of demand (read+write) MSHR miss cycles
3625system.l2c.demand_mshr_miss_latency::total 247272059793 # number of demand (read+write) MSHR miss cycles
3626system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 427356500 # number of overall MSHR miss cycles
3627system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 415425500 # number of overall MSHR miss cycles
3628system.l2c.overall_mshr_miss_latency::cpu0.inst 8580768502 # number of overall MSHR miss cycles
3629system.l2c.overall_mshr_miss_latency::cpu0.data 116193318994 # number of overall MSHR miss cycles
3630system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 59968803653 # number of overall MSHR miss cycles
3631system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 195855000 # number of overall MSHR miss cycles
3632system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 141327000 # number of overall MSHR miss cycles
3633system.l2c.overall_mshr_miss_latency::cpu1.inst 4625471500 # number of overall MSHR miss cycles
3634system.l2c.overall_mshr_miss_latency::cpu1.data 26819057998 # number of overall MSHR miss cycles
3635system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 29904675146 # number of overall MSHR miss cycles
3636system.l2c.overall_mshr_miss_latency::total 247272059793 # number of overall MSHR miss cycles
3637system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2396727000 # number of ReadReq MSHR uncacheable cycles
3638system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4940514000 # number of ReadReq MSHR uncacheable cycles
3639system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7197500 # number of ReadReq MSHR uncacheable cycles
3640system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 587373500 # number of ReadReq MSHR uncacheable cycles
3641system.l2c.ReadReq_mshr_uncacheable_latency::total 7931812000 # number of ReadReq MSHR uncacheable cycles
3642system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4820729533 # number of WriteReq MSHR uncacheable cycles
3643system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 738465000 # number of WriteReq MSHR uncacheable cycles
3644system.l2c.WriteReq_mshr_uncacheable_latency::total 5559194533 # number of WriteReq MSHR uncacheable cycles
3645system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2396727000 # number of overall MSHR uncacheable cycles
3646system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9761243533 # number of overall MSHR uncacheable cycles
3647system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7197500 # number of overall MSHR uncacheable cycles
3648system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1325838500 # number of overall MSHR uncacheable cycles
3649system.l2c.overall_mshr_uncacheable_latency::total 13491006533 # number of overall MSHR uncacheable cycles
3650system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3651system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3652system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.630379 # mshr miss rate for UpgradeReq accesses
3653system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.582188 # mshr miss rate for UpgradeReq accesses
3654system.l2c.UpgradeReq_mshr_miss_rate::total 0.606465 # mshr miss rate for UpgradeReq accesses
3655system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.625565 # mshr miss rate for SCUpgradeReq accesses
3656system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.606158 # mshr miss rate for SCUpgradeReq accesses
3657system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.616713 # mshr miss rate for SCUpgradeReq accesses
3658system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.767553 # mshr miss rate for ReadExReq accesses
3659system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.388438 # mshr miss rate for ReadExReq accesses
3660system.l2c.ReadExReq_mshr_miss_rate::total 0.665485 # mshr miss rate for ReadExReq accesses
3661system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.330522 # mshr miss rate for ReadSharedReq accesses
3662system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.422072 # mshr miss rate for ReadSharedReq accesses
3663system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.098363 # mshr miss rate for ReadSharedReq accesses
3664system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.215848 # mshr miss rate for ReadSharedReq accesses
3665system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.537405 # mshr miss rate for ReadSharedReq accesses
3666system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.192994 # mshr miss rate for ReadSharedReq accesses
3667system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.199461 # mshr miss rate for ReadSharedReq accesses
3668system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.064704 # mshr miss rate for ReadSharedReq accesses
3669system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.149076 # mshr miss rate for ReadSharedReq accesses
3670system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.367704 # mshr miss rate for ReadSharedReq accesses
3671system.l2c.ReadSharedReq_mshr_miss_rate::total 0.234829 # mshr miss rate for ReadSharedReq accesses
3672system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.330522 # mshr miss rate for demand accesses
3673system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.422072 # mshr miss rate for demand accesses
3674system.l2c.demand_mshr_miss_rate::cpu0.inst 0.098363 # mshr miss rate for demand accesses
3675system.l2c.demand_mshr_miss_rate::cpu0.data 0.474940 # mshr miss rate for demand accesses
3676system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.537405 # mshr miss rate for demand accesses
3677system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.192994 # mshr miss rate for demand accesses
3678system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.199461 # mshr miss rate for demand accesses
3679system.l2c.demand_mshr_miss_rate::cpu1.inst 0.064704 # mshr miss rate for demand accesses
3680system.l2c.demand_mshr_miss_rate::cpu1.data 0.219741 # mshr miss rate for demand accesses
3681system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.367704 # mshr miss rate for demand accesses
3682system.l2c.demand_mshr_miss_rate::total 0.322484 # mshr miss rate for demand accesses
3683system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.330522 # mshr miss rate for overall accesses
3684system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.422072 # mshr miss rate for overall accesses
3685system.l2c.overall_mshr_miss_rate::cpu0.inst 0.098363 # mshr miss rate for overall accesses
3686system.l2c.overall_mshr_miss_rate::cpu0.data 0.474940 # mshr miss rate for overall accesses
3687system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.537405 # mshr miss rate for overall accesses
3688system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.192994 # mshr miss rate for overall accesses
3689system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.199461 # mshr miss rate for overall accesses
3690system.l2c.overall_mshr_miss_rate::cpu1.inst 0.064704 # mshr miss rate for overall accesses
3691system.l2c.overall_mshr_miss_rate::cpu1.data 0.219741 # mshr miss rate for overall accesses
3692system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.367704 # mshr miss rate for overall accesses
3693system.l2c.overall_mshr_miss_rate::total 0.322484 # mshr miss rate for overall accesses
3694system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73588.862847 # average UpgradeReq mshr miss latency
3695system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73670.670892 # average UpgradeReq mshr miss latency
3696system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73627.833592 # average UpgradeReq mshr miss latency
3697system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76501.501360 # average SCUpgradeReq mshr miss latency
3698system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76430.731355 # average SCUpgradeReq mshr miss latency
3699system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76469.773718 # average SCUpgradeReq mshr miss latency
3700system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 168727.781569 # average ReadExReq mshr miss latency
3701system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139531.928329 # average ReadExReq mshr miss latency
3702system.l2c.ReadExReq_avg_mshr_miss_latency::total 164139.771808 # average ReadExReq mshr miss latency
3703system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 131373.040271 # average ReadSharedReq mshr miss latency
3704system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 130554.839723 # average ReadSharedReq mshr miss latency
3705system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127154.520427 # average ReadSharedReq mshr miss latency
3706system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 137511.142948 # average ReadSharedReq mshr miss latency
3707system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173660.033224 # average ReadSharedReq mshr miss latency
3708system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 137249.474422 # average ReadSharedReq mshr miss latency
3709system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 136284.474446 # average ReadSharedReq mshr miss latency
3710system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127441.011159 # average ReadSharedReq mshr miss latency
3711system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 134704.947242 # average ReadSharedReq mshr miss latency
3712system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174863.757088 # average ReadSharedReq mshr miss latency
3713system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 157038.604224 # average ReadSharedReq mshr miss latency
3714system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 131373.040271 # average overall mshr miss latency
3715system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 130554.839723 # average overall mshr miss latency
3716system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127154.520427 # average overall mshr miss latency
3717system.l2c.demand_avg_mshr_miss_latency::cpu0.data 161203.181787 # average overall mshr miss latency
3718system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173660.033224 # average overall mshr miss latency
3719system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 137249.474422 # average overall mshr miss latency
3720system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 136284.474446 # average overall mshr miss latency
3721system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127441.011159 # average overall mshr miss latency
3722system.l2c.demand_avg_mshr_miss_latency::cpu1.data 137223.997124 # average overall mshr miss latency
3723system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174863.757088 # average overall mshr miss latency
3724system.l2c.demand_avg_mshr_miss_latency::total 160021.265102 # average overall mshr miss latency
3725system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131373.040271 # average overall mshr miss latency
3726system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130554.839723 # average overall mshr miss latency
3727system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127154.520427 # average overall mshr miss latency
3728system.l2c.overall_avg_mshr_miss_latency::cpu0.data 161203.181787 # average overall mshr miss latency
3729system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173660.033224 # average overall mshr miss latency
3730system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 137249.474422 # average overall mshr miss latency
3731system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 136284.474446 # average overall mshr miss latency
3732system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127441.011159 # average overall mshr miss latency
3733system.l2c.overall_avg_mshr_miss_latency::cpu1.data 137223.997124 # average overall mshr miss latency
3734system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174863.757088 # average overall mshr miss latency
3735system.l2c.overall_avg_mshr_miss_latency::total 160021.265102 # average overall mshr miss latency
3736system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112554.099746 # average ReadReq mshr uncacheable latency
3737system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154627.836374 # average ReadReq mshr uncacheable latency
3738system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107425.373134 # average ReadReq mshr uncacheable latency
3739system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 86074.662954 # average ReadReq mshr uncacheable latency
3740system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131897.898098 # average ReadReq mshr uncacheable latency
3741system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153111.943243 # average WriteReq mshr uncacheable latency
3742system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 102979.361316 # average WriteReq mshr uncacheable latency
3743system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 143811.944666 # average WriteReq mshr uncacheable latency
3744system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112554.099746 # average overall mshr uncacheable latency
3745system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 153875.457674 # average overall mshr uncacheable latency
3746system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107425.373134 # average overall mshr uncacheable latency
3747system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 94736.584494 # average overall mshr uncacheable latency
3748system.l2c.overall_avg_mshr_uncacheable_latency::total 136559.706586 # average overall mshr uncacheable latency
3749system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
3750system.membus.trans_dist::ReadReq 60136 # Transaction distribution
3751system.membus.trans_dist::ReadResp 965246 # Transaction distribution
3752system.membus.trans_dist::WriteReq 38656 # Transaction distribution
3753system.membus.trans_dist::WriteResp 38656 # Transaction distribution
3754system.membus.trans_dist::Writeback 1296915 # Transaction distribution
3755system.membus.trans_dist::CleanEvict 243951 # Transaction distribution
3756system.membus.trans_dist::UpgradeReq 452760 # Transaction distribution
3757system.membus.trans_dist::SCUpgradeReq 304384 # Transaction distribution
3758system.membus.trans_dist::UpgradeResp 121976 # Transaction distribution
3759system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
3760system.membus.trans_dist::ReadExReq 662340 # Transaction distribution
3761system.membus.trans_dist::ReadExResp 641281 # Transaction distribution
3762system.membus.trans_dist::ReadSharedReq 905110 # Transaction distribution
3763system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution
3764system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution
3765system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122826 # Packet count per connected master and slave (bytes)
3766system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes)
3767system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26816 # Packet count per connected master and slave (bytes)
3768system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5450054 # Packet count per connected master and slave (bytes)
3769system.membus.pkt_count_system.l2c.mem_side::total 5599774 # Packet count per connected master and slave (bytes)
3770system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342030 # Packet count per connected master and slave (bytes)
3771system.membus.pkt_count_system.iocache.mem_side::total 342030 # Packet count per connected master and slave (bytes)
3772system.membus.pkt_count::total 5941804 # Packet count per connected master and slave (bytes)
3773system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155933 # Cumulative packet size per connected master and slave (bytes)
3774system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes)
3775system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 53632 # Cumulative packet size per connected master and slave (bytes)
3776system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174888448 # Cumulative packet size per connected master and slave (bytes)
3777system.membus.pkt_size_system.l2c.mem_side::total 175098585 # Cumulative packet size per connected master and slave (bytes)
3778system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7250496 # Cumulative packet size per connected master and slave (bytes)
3779system.membus.pkt_size_system.iocache.mem_side::total 7250496 # Cumulative packet size per connected master and slave (bytes)
3780system.membus.pkt_size::total 182349081 # Cumulative packet size per connected master and slave (bytes)
3781system.membus.snoops 659296 # Total snoops (count)
3782system.membus.snoop_fanout::samples 4073524 # Request fanout histogram
3783system.membus.snoop_fanout::mean 1 # Request fanout histogram
3784system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3785system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3786system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3787system.membus.snoop_fanout::1 4073524 100.00% 100.00% # Request fanout histogram
3788system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3789system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3790system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3791system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3792system.membus.snoop_fanout::total 4073524 # Request fanout histogram
3793system.membus.reqLayer0.occupancy 98143499 # Layer occupancy (ticks)
3794system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3795system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks)
3796system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3797system.membus.reqLayer2.occupancy 22747469 # Layer occupancy (ticks)
3798system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3799system.membus.reqLayer5.occupancy 9016528809 # Layer occupancy (ticks)
3800system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3801system.membus.respLayer2.occupancy 8432717951 # Layer occupancy (ticks)
3802system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3803system.membus.respLayer3.occupancy 230475062 # Layer occupancy (ticks)
3804system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3805system.realview.ethernet.txBytes 966 # Bytes Transmitted
3806system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3807system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3808system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3809system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3810system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3811system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA

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3849system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks
3850system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks
3851system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks
3852system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks
3853system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks
3854system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
3855system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
3856system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
3857system.toL2Bus.snoop_filter.tot_requests 11519638 # Total number of requests made to the snoop filter.
3858system.toL2Bus.snoop_filter.hit_single_requests 5862055 # Number of requests hitting in the snoop filter with a single holder of the requested data.
3859system.toL2Bus.snoop_filter.hit_multi_requests 2048796 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
3860system.toL2Bus.snoop_filter.tot_snoops 167370 # Total number of snoops made to the snoop filter.
3861system.toL2Bus.snoop_filter.hit_single_snoops 156134 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
3862system.toL2Bus.snoop_filter.hit_multi_snoops 11236 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
3863system.toL2Bus.trans_dist::ReadReq 60138 # Transaction distribution
3864system.toL2Bus.trans_dist::ReadResp 4755206 # Transaction distribution
3865system.toL2Bus.trans_dist::WriteReq 38656 # Transaction distribution
3866system.toL2Bus.trans_dist::WriteResp 38656 # Transaction distribution
3867system.toL2Bus.trans_dist::Writeback 3790142 # Transaction distribution
3868system.toL2Bus.trans_dist::CleanEvict 1500041 # Transaction distribution
3869system.toL2Bus.trans_dist::UpgradeReq 506577 # Transaction distribution
3870system.toL2Bus.trans_dist::SCUpgradeReq 316392 # Transaction distribution
3871system.toL2Bus.trans_dist::UpgradeResp 822969 # Transaction distribution
3872system.toL2Bus.trans_dist::SCUpgradeFailReq 115 # Transaction distribution
3873system.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution
3874system.toL2Bus.trans_dist::ReadExReq 1127077 # Transaction distribution
3875system.toL2Bus.trans_dist::ReadExResp 1127077 # Transaction distribution
3876system.toL2Bus.trans_dist::ReadSharedReq 4702306 # Transaction distribution
3877system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution
3878system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9146865 # Packet count per connected master and slave (bytes)
3879system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6326733 # Packet count per connected master and slave (bytes)
3880system.toL2Bus.pkt_count::total 15473598 # Packet count per connected master and slave (bytes)
3881system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 285949105 # Cumulative packet size per connected master and slave (bytes)
3882system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 180962856 # Cumulative packet size per connected master and slave (bytes)
3883system.toL2Bus.pkt_size::total 466911961 # Cumulative packet size per connected master and slave (bytes)
3884system.toL2Bus.snoops 3420267 # Total snoops (count)
3885system.toL2Bus.snoop_fanout::samples 13372960 # Request fanout histogram
3886system.toL2Bus.snoop_fanout::mean 0.331842 # Request fanout histogram
3887system.toL2Bus.snoop_fanout::stdev 0.472656 # Request fanout histogram
3888system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3889system.toL2Bus.snoop_fanout::0 8946480 66.90% 66.90% # Request fanout histogram
3890system.toL2Bus.snoop_fanout::1 4415244 33.02% 99.92% # Request fanout histogram
3891system.toL2Bus.snoop_fanout::2 11236 0.08% 100.00% # Request fanout histogram
3892system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3893system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
3894system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3895system.toL2Bus.snoop_fanout::total 13372960 # Request fanout histogram
3896system.toL2Bus.reqLayer0.occupancy 8776402150 # Layer occupancy (ticks)
3897system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3898system.toL2Bus.snoopLayer0.occupancy 2601544 # Layer occupancy (ticks)
3899system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3900system.toL2Bus.respLayer0.occupancy 5338662327 # Layer occupancy (ticks)
3901system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3902system.toL2Bus.respLayer1.occupancy 3896618177 # Layer occupancy (ticks)
3903system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3904system.cpu0.kern.inst.arm 0 # number of arm instructions executed
3905system.cpu0.kern.inst.quiesce 14407 # number of quiesce instructions executed
3906system.cpu1.kern.inst.arm 0 # number of arm instructions executed
3907system.cpu1.kern.inst.quiesce 7094 # number of quiesce instructions executed
3908
3909---------- End Simulation Statistics ----------