1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.309827 # Number of seconds simulated
4sim_ticks 47309826639000 # Number of ticks simulated
5final_tick 47309826639000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 99581 # Simulator instruction rate (inst/s)
8host_op_rate 117105 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 4980017521 # Simulator tick rate (ticks/s)
10host_mem_usage 777716 # Number of bytes of host memory used
11host_seconds 9499.93 # Real time elapsed on the host
12sim_insts 946011818 # Number of instructions simulated
13sim_ops 1112485532 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 184448 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 167936 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 5084832 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 44767048 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 19339456 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 176320 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 161792 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 2535456 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 18891728 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 20722048 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 420544 # Number of bytes read from this memory
27system.physmem.bytes_read::total 112451608 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 5084832 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 2535456 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 7620288 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 93755328 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
34system.physmem.bytes_written::total 93775912 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 2882 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 2624 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 95403 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 699498 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 302179 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 2755 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.itb.walker 2528 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.inst 39660 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.data 295196 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.l2cache.prefetcher 323782 # Number of read requests responded to by this memory
45system.physmem.num_reads::realview.ide 6571 # Number of read requests responded to by this memory
46system.physmem.num_reads::total 1773078 # Number of read requests responded to by this memory
47system.physmem.num_writes::writebacks 1464927 # Number of write requests responded to by this memory
48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
50system.physmem.num_writes::total 1467501 # Number of write requests responded to by this memory
51system.physmem.bw_read::cpu0.dtb.walker 3899 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.itb.walker 3550 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.inst 107479 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.data 946253 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.l2cache.prefetcher 408783 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.dtb.walker 3727 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.itb.walker 3420 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.inst 53593 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.data 399319 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.l2cache.prefetcher 438007 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::realview.ide 8889 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::total 2376919 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::cpu0.inst 107479 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu1.inst 53593 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::total 161072 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_write::writebacks 1981731 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::total 1982166 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_total::writebacks 1981731 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.dtb.walker 3899 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.itb.walker 3550 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.inst 107479 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.data 946688 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.l2cache.prefetcher 408783 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.dtb.walker 3727 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.itb.walker 3420 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.inst 53593 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.data 399319 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.l2cache.prefetcher 438007 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.ide 8889 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::total 4359084 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.readReqs 1773078 # Number of read requests accepted
84system.physmem.writeReqs 1467501 # Number of write requests accepted
85system.physmem.readBursts 1773078 # Number of DRAM read bursts, including those serviced by the write queue
86system.physmem.writeBursts 1467501 # Number of DRAM write bursts, including those merged in the write queue
87system.physmem.bytesReadDRAM 113443520 # Total number of bytes read from DRAM
88system.physmem.bytesReadWrQ 33472 # Total number of bytes read from write queue
89system.physmem.bytesWritten 93774528 # Total number of bytes written to DRAM
90system.physmem.bytesReadSys 112451608 # Total read bytes from the system interface side
91system.physmem.bytesWrittenSys 93775912 # Total written bytes from the system interface side
92system.physmem.servicedByWrQ 523 # Number of DRAM read bursts serviced by the write queue
93system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
94system.physmem.neitherReadNorWriteReqs 224875 # Number of requests that are neither read nor write
95system.physmem.perBankRdBursts::0 113386 # Per bank write bursts
96system.physmem.perBankRdBursts::1 120644 # Per bank write bursts
97system.physmem.perBankRdBursts::2 108661 # Per bank write bursts
98system.physmem.perBankRdBursts::3 115173 # Per bank write bursts
99system.physmem.perBankRdBursts::4 103078 # Per bank write bursts
100system.physmem.perBankRdBursts::5 114921 # Per bank write bursts
101system.physmem.perBankRdBursts::6 108340 # Per bank write bursts
102system.physmem.perBankRdBursts::7 105879 # Per bank write bursts
103system.physmem.perBankRdBursts::8 98747 # Per bank write bursts
104system.physmem.perBankRdBursts::9 127278 # Per bank write bursts
105system.physmem.perBankRdBursts::10 99197 # Per bank write bursts
106system.physmem.perBankRdBursts::11 111650 # Per bank write bursts
107system.physmem.perBankRdBursts::12 107228 # Per bank write bursts
108system.physmem.perBankRdBursts::13 113583 # Per bank write bursts
109system.physmem.perBankRdBursts::14 112177 # Per bank write bursts
110system.physmem.perBankRdBursts::15 112613 # Per bank write bursts
111system.physmem.perBankWrBursts::0 94420 # Per bank write bursts
112system.physmem.perBankWrBursts::1 97266 # Per bank write bursts
113system.physmem.perBankWrBursts::2 90974 # Per bank write bursts
114system.physmem.perBankWrBursts::3 94616 # Per bank write bursts
115system.physmem.perBankWrBursts::4 87287 # Per bank write bursts
116system.physmem.perBankWrBursts::5 94599 # Per bank write bursts
117system.physmem.perBankWrBursts::6 89304 # Per bank write bursts
118system.physmem.perBankWrBursts::7 90590 # Per bank write bursts
119system.physmem.perBankWrBursts::8 84448 # Per bank write bursts
120system.physmem.perBankWrBursts::9 90113 # Per bank write bursts
121system.physmem.perBankWrBursts::10 85465 # Per bank write bursts
122system.physmem.perBankWrBursts::11 93225 # Per bank write bursts
123system.physmem.perBankWrBursts::12 88655 # Per bank write bursts
124system.physmem.perBankWrBursts::13 95246 # Per bank write bursts
125system.physmem.perBankWrBursts::14 93025 # Per bank write bursts
126system.physmem.perBankWrBursts::15 95994 # Per bank write bursts
127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
128system.physmem.numWrRetry 83 # Number of times write queue was full causing retry
129system.physmem.totGap 47309825190500 # Total gap between requests
130system.physmem.readPktSize::0 0 # Read request sizes (log2)
131system.physmem.readPktSize::1 0 # Read request sizes (log2)
132system.physmem.readPktSize::2 0 # Read request sizes (log2)
133system.physmem.readPktSize::3 25 # Read request sizes (log2)
134system.physmem.readPktSize::4 21333 # Read request sizes (log2)
135system.physmem.readPktSize::5 0 # Read request sizes (log2)
136system.physmem.readPktSize::6 1751720 # Read request sizes (log2)
137system.physmem.writePktSize::0 0 # Write request sizes (log2)
138system.physmem.writePktSize::1 0 # Write request sizes (log2)
139system.physmem.writePktSize::2 2 # Write request sizes (log2)
140system.physmem.writePktSize::3 2572 # Write request sizes (log2)
141system.physmem.writePktSize::4 0 # Write request sizes (log2)
142system.physmem.writePktSize::5 0 # Write request sizes (log2)
143system.physmem.writePktSize::6 1464927 # Write request sizes (log2)
144system.physmem.rdQLenPdf::0 608524 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::1 449703 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::2 194607 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::3 195607 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::4 116312 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::5 71048 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::6 40112 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::7 36551 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::8 32712 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::9 10303 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::10 5634 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::11 3467 # What read queue length does an incoming req see
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157system.physmem.rdQLenPdf::13 1844 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::14 1284 # What read queue length does an incoming req see
159system.physmem.rdQLenPdf::15 910 # What read queue length does an incoming req see
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164system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see
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191system.physmem.wrQLenPdf::15 20153 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::16 23447 # What write queue length does an incoming req see
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194system.physmem.wrQLenPdf::18 44303 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::19 53186 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::20 62828 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::21 72210 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::22 82749 # What write queue length does an incoming req see
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201system.physmem.wrQLenPdf::25 97547 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::26 101638 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::27 103246 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::28 108748 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::29 123417 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::30 115282 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::31 109625 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::32 98032 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::33 7953 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::34 4632 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::35 2879 # What write queue length does an incoming req see
212system.physmem.wrQLenPdf::36 1860 # What write queue length does an incoming req see
213system.physmem.wrQLenPdf::37 1227 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::38 995 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::39 815 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::40 720 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::41 612 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::42 525 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::43 410 # What write queue length does an incoming req see
220system.physmem.wrQLenPdf::44 440 # What write queue length does an incoming req see
221system.physmem.wrQLenPdf::45 406 # What write queue length does an incoming req see
222system.physmem.wrQLenPdf::46 425 # What write queue length does an incoming req see
223system.physmem.wrQLenPdf::47 375 # What write queue length does an incoming req see
224system.physmem.wrQLenPdf::48 314 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::49 311 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::50 242 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::51 316 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::52 313 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::53 264 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::54 268 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::55 296 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::56 228 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::57 169 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::58 150 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::59 140 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::60 118 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::61 81 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::62 119 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::63 281 # What write queue length does an incoming req see
240system.physmem.bytesPerActivate::samples 1119709 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::mean 185.063798 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::gmean 114.156365 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::stdev 241.940793 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::0-127 674939 60.28% 60.28% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::128-255 219039 19.56% 79.84% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::256-383 70659 6.31% 86.15% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::384-511 37987 3.39% 89.54% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::512-639 28223 2.52% 92.06% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::640-767 14545 1.30% 93.36% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::768-895 15798 1.41% 94.77% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::896-1023 9595 0.86% 95.63% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::1024-1151 48924 4.37% 100.00% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::total 1119709 # Bytes accessed per row activation
254system.physmem.rdPerTurnAround::samples 84177 # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::mean 21.057367 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::stdev 250.150754 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::0-4095 84175 100.00% 100.00% # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::69632-73727 1 0.00% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::total 84177 # Reads before turning the bus around for writes
261system.physmem.wrPerTurnAround::samples 84177 # Writes before turning the bus around for reads
262system.physmem.wrPerTurnAround::mean 17.406501 # Writes before turning the bus around for reads
263system.physmem.wrPerTurnAround::gmean 16.998569 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::stdev 6.063432 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::16-19 78913 93.75% 93.75% # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::20-23 2654 3.15% 96.90% # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::24-27 594 0.71% 97.61% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::28-31 256 0.30% 97.91% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::32-35 356 0.42% 98.33% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::36-39 499 0.59% 98.92% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::40-43 111 0.13% 99.06% # Writes before turning the bus around for reads
272system.physmem.wrPerTurnAround::44-47 36 0.04% 99.10% # Writes before turning the bus around for reads
273system.physmem.wrPerTurnAround::48-51 47 0.06% 99.16% # Writes before turning the bus around for reads
274system.physmem.wrPerTurnAround::52-55 28 0.03% 99.19% # Writes before turning the bus around for reads
275system.physmem.wrPerTurnAround::56-59 36 0.04% 99.23% # Writes before turning the bus around for reads
276system.physmem.wrPerTurnAround::60-63 26 0.03% 99.26% # Writes before turning the bus around for reads
277system.physmem.wrPerTurnAround::64-67 418 0.50% 99.76% # Writes before turning the bus around for reads
278system.physmem.wrPerTurnAround::68-71 37 0.04% 99.80% # Writes before turning the bus around for reads
279system.physmem.wrPerTurnAround::72-75 46 0.05% 99.86% # Writes before turning the bus around for reads
280system.physmem.wrPerTurnAround::76-79 46 0.05% 99.91% # Writes before turning the bus around for reads
281system.physmem.wrPerTurnAround::80-83 12 0.01% 99.93% # Writes before turning the bus around for reads
282system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads
283system.physmem.wrPerTurnAround::88-91 2 0.00% 99.93% # Writes before turning the bus around for reads
284system.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads
285system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads
286system.physmem.wrPerTurnAround::100-103 4 0.00% 99.94% # Writes before turning the bus around for reads
287system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads
288system.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads
289system.physmem.wrPerTurnAround::120-123 1 0.00% 99.94% # Writes before turning the bus around for reads
290system.physmem.wrPerTurnAround::124-127 1 0.00% 99.95% # Writes before turning the bus around for reads
291system.physmem.wrPerTurnAround::128-131 25 0.03% 99.98% # Writes before turning the bus around for reads
292system.physmem.wrPerTurnAround::132-135 2 0.00% 99.98% # Writes before turning the bus around for reads
293system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads
294system.physmem.wrPerTurnAround::140-143 2 0.00% 99.98% # Writes before turning the bus around for reads
295system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads
296system.physmem.wrPerTurnAround::148-151 2 0.00% 99.99% # Writes before turning the bus around for reads
297system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads
298system.physmem.wrPerTurnAround::160-163 1 0.00% 99.99% # Writes before turning the bus around for reads
299system.physmem.wrPerTurnAround::164-167 4 0.00% 99.99% # Writes before turning the bus around for reads
300system.physmem.wrPerTurnAround::176-179 2 0.00% 100.00% # Writes before turning the bus around for reads
301system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads
302system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads
303system.physmem.wrPerTurnAround::224-227 1 0.00% 100.00% # Writes before turning the bus around for reads
304system.physmem.wrPerTurnAround::232-235 1 0.00% 100.00% # Writes before turning the bus around for reads
305system.physmem.wrPerTurnAround::total 84177 # Writes before turning the bus around for reads
306system.physmem.totQLat 95142418476 # Total ticks spent queuing
307system.physmem.totMemAccLat 128377824726 # Total ticks spent from burst creation until serviced by the DRAM
308system.physmem.totBusLat 8862775000 # Total ticks spent in databus transfers
309system.physmem.avgQLat 53675.30 # Average queueing delay per DRAM burst
310system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
311system.physmem.avgMemAccLat 72425.30 # Average memory access latency per DRAM burst
312system.physmem.avgRdBW 2.40 # Average DRAM read bandwidth in MiByte/s
313system.physmem.avgWrBW 1.98 # Average achieved write bandwidth in MiByte/s
314system.physmem.avgRdBWSys 2.38 # Average system read bandwidth in MiByte/s
315system.physmem.avgWrBWSys 1.98 # Average system write bandwidth in MiByte/s
316system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
317system.physmem.busUtil 0.03 # Data bus utilization in percentage
318system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
319system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
320system.physmem.avgRdQLen 1.17 # Average read queue length when enqueuing
321system.physmem.avgWrQLen 25.45 # Average write queue length when enqueuing
322system.physmem.readRowHits 1427545 # Number of row buffer hits during reads
323system.physmem.writeRowHits 690525 # Number of row buffer hits during writes
324system.physmem.readRowHitRate 80.54 # Row buffer hit rate for reads
325system.physmem.writeRowHitRate 47.13 # Row buffer hit rate for writes
326system.physmem.avgGap 14599188.97 # Average gap between requests
327system.physmem.pageHitRate 65.42 # Row buffer hit rate, read and write combined
328system.physmem_0.actEnergy 4299372000 # Energy for activate commands per rank (pJ)
329system.physmem_0.preEnergy 2345887500 # Energy for precharge commands per rank (pJ)
330system.physmem_0.readEnergy 6942631800 # Energy for read commands per rank (pJ)
331system.physmem_0.writeEnergy 4789082880 # Energy for write commands per rank (pJ)
332system.physmem_0.refreshEnergy 3090047684880 # Energy for refresh commands per rank (pJ)
333system.physmem_0.actBackEnergy 1174100419575 # Energy for active background per rank (pJ)
334system.physmem_0.preBackEnergy 27355981545000 # Energy for precharge background per rank (pJ)
335system.physmem_0.totalEnergy 31638506623635 # Total energy per rank (pJ)
336system.physmem_0.averagePower 668.751312 # Core power per rank (mW)
337system.physmem_0.memoryStateTime::IDLE 45508743621503 # Time in different power states
338system.physmem_0.memoryStateTime::REF 1579778980000 # Time in different power states
339system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
340system.physmem_0.memoryStateTime::ACT 221302763997 # Time in different power states
341system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
342system.physmem_1.actEnergy 4165628040 # Energy for activate commands per rank (pJ)
343system.physmem_1.preEnergy 2272912125 # Energy for precharge commands per rank (pJ)
344system.physmem_1.readEnergy 6883242600 # Energy for read commands per rank (pJ)
345system.physmem_1.writeEnergy 4705588080 # Energy for write commands per rank (pJ)
346system.physmem_1.refreshEnergy 3090047684880 # Energy for refresh commands per rank (pJ)
347system.physmem_1.actBackEnergy 1168667714520 # Energy for active background per rank (pJ)
348system.physmem_1.preBackEnergy 27360747075750 # Energy for precharge background per rank (pJ)
349system.physmem_1.totalEnergy 31637489845995 # Total energy per rank (pJ)
350system.physmem_1.averagePower 668.729820 # Core power per rank (mW)
351system.physmem_1.memoryStateTime::IDLE 45516677078545 # Time in different power states
352system.physmem_1.memoryStateTime::REF 1579778980000 # Time in different power states
353system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
354system.physmem_1.memoryStateTime::ACT 213370138955 # Time in different power states
355system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
356system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory
357system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
358system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
359system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
360system.realview.nvmem.bytes_read::total 572 # Number of bytes read from this memory
361system.realview.nvmem.bytes_inst_read::cpu0.inst 384 # Number of instructions bytes read from this memory
362system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory

--- 17 unchanged lines hidden (view full) ---

380system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
381system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
382system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
383system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
384system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
385system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
386system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
387system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
388system.cpu0.branchPred.lookups 147637418 # Number of BP lookups
389system.cpu0.branchPred.condPredicted 98315773 # Number of conditional branches predicted
390system.cpu0.branchPred.condIncorrect 7247820 # Number of conditional branches incorrect
391system.cpu0.branchPred.BTBLookups 103619610 # Number of BTB lookups
392system.cpu0.branchPred.BTBHits 67413734 # Number of BTB hits
393system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
394system.cpu0.branchPred.BTBHitPct 65.058857 # BTB Hit Percentage
395system.cpu0.branchPred.usedRAS 20080737 # Number of times the RAS was used to get a target.
396system.cpu0.branchPred.RASInCorrect 195189 # Number of incorrect RAS predictions.
397system.cpu_clk_domain.clock 500 # Clock period in ticks
398system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
401system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
402system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
403system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
404system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

419system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
420system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
421system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
422system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
423system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
424system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
425system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
426system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
427system.cpu0.dtb.walker.walks 596316 # Table walker walks requested
428system.cpu0.dtb.walker.walksLong 596316 # Table walker walks initiated with long descriptors
429system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13005 # Level at which table walker walks with long descriptors terminate
430system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90766 # Level at which table walker walks with long descriptors terminate
431system.cpu0.dtb.walker.walksSquashedBefore 267964 # Table walks squashed before starting
432system.cpu0.dtb.walker.walkWaitTime::samples 328352 # Table walker wait (enqueue to first request) latency
433system.cpu0.dtb.walker.walkWaitTime::mean 1967.306427 # Table walker wait (enqueue to first request) latency
434system.cpu0.dtb.walker.walkWaitTime::stdev 12140.663837 # Table walker wait (enqueue to first request) latency
435system.cpu0.dtb.walker.walkWaitTime::0-65535 326191 99.34% 99.34% # Table walker wait (enqueue to first request) latency
436system.cpu0.dtb.walker.walkWaitTime::65536-131071 1511 0.46% 99.80% # Table walker wait (enqueue to first request) latency
437system.cpu0.dtb.walker.walkWaitTime::131072-196607 485 0.15% 99.95% # Table walker wait (enqueue to first request) latency
438system.cpu0.dtb.walker.walkWaitTime::196608-262143 70 0.02% 99.97% # Table walker wait (enqueue to first request) latency
439system.cpu0.dtb.walker.walkWaitTime::262144-327679 71 0.02% 99.99% # Table walker wait (enqueue to first request) latency
440system.cpu0.dtb.walker.walkWaitTime::327680-393215 17 0.01% 100.00% # Table walker wait (enqueue to first request) latency
441system.cpu0.dtb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
442system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
443system.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
444system.cpu0.dtb.walker.walkWaitTime::total 328352 # Table walker wait (enqueue to first request) latency
445system.cpu0.dtb.walker.walkCompletionTime::samples 293288 # Table walker service (enqueue to completion) latency
446system.cpu0.dtb.walker.walkCompletionTime::mean 18414.921511 # Table walker service (enqueue to completion) latency
447system.cpu0.dtb.walker.walkCompletionTime::gmean 15494.626324 # Table walker service (enqueue to completion) latency
448system.cpu0.dtb.walker.walkCompletionTime::stdev 16461.439983 # Table walker service (enqueue to completion) latency
449system.cpu0.dtb.walker.walkCompletionTime::0-65535 290000 98.88% 98.88% # Table walker service (enqueue to completion) latency
450system.cpu0.dtb.walker.walkCompletionTime::65536-131071 2364 0.81% 99.68% # Table walker service (enqueue to completion) latency
451system.cpu0.dtb.walker.walkCompletionTime::131072-196607 368 0.13% 99.81% # Table walker service (enqueue to completion) latency
452system.cpu0.dtb.walker.walkCompletionTime::196608-262143 346 0.12% 99.93% # Table walker service (enqueue to completion) latency
453system.cpu0.dtb.walker.walkCompletionTime::262144-327679 119 0.04% 99.97% # Table walker service (enqueue to completion) latency
454system.cpu0.dtb.walker.walkCompletionTime::327680-393215 72 0.02% 99.99% # Table walker service (enqueue to completion) latency
455system.cpu0.dtb.walker.walkCompletionTime::393216-458751 12 0.00% 100.00% # Table walker service (enqueue to completion) latency
456system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
457system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
458system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
459system.cpu0.dtb.walker.walkCompletionTime::total 293288 # Table walker service (enqueue to completion) latency
460system.cpu0.dtb.walker.walksPending::samples 554812439744 # Table walker pending requests distribution
461system.cpu0.dtb.walker.walksPending::mean 0.594659 # Table walker pending requests distribution
462system.cpu0.dtb.walker.walksPending::stdev 0.537153 # Table walker pending requests distribution
463system.cpu0.dtb.walker.walksPending::0-1 553701545244 99.80% 99.80% # Table walker pending requests distribution
464system.cpu0.dtb.walker.walksPending::2-3 589103000 0.11% 99.91% # Table walker pending requests distribution
465system.cpu0.dtb.walker.walksPending::4-5 238633000 0.04% 99.95% # Table walker pending requests distribution
466system.cpu0.dtb.walker.walksPending::6-7 116174000 0.02% 99.97% # Table walker pending requests distribution
467system.cpu0.dtb.walker.walksPending::8-9 85227000 0.02% 99.99% # Table walker pending requests distribution
468system.cpu0.dtb.walker.walksPending::10-11 46829500 0.01% 99.99% # Table walker pending requests distribution
469system.cpu0.dtb.walker.walksPending::12-13 15433000 0.00% 100.00% # Table walker pending requests distribution
470system.cpu0.dtb.walker.walksPending::14-15 19112000 0.00% 100.00% # Table walker pending requests distribution
471system.cpu0.dtb.walker.walksPending::16-17 363500 0.00% 100.00% # Table walker pending requests distribution
472system.cpu0.dtb.walker.walksPending::18-19 19500 0.00% 100.00% # Table walker pending requests distribution
473system.cpu0.dtb.walker.walksPending::total 554812439744 # Table walker pending requests distribution
474system.cpu0.dtb.walker.walkPageSizes::4K 90767 87.47% 87.47% # Table walker page sizes translated
475system.cpu0.dtb.walker.walkPageSizes::2M 13005 12.53% 100.00% # Table walker page sizes translated
476system.cpu0.dtb.walker.walkPageSizes::total 103772 # Table walker page sizes translated
477system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 596316 # Table walker requests started/completed, data/inst
478system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
479system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 596316 # Table walker requests started/completed, data/inst
480system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 103772 # Table walker requests started/completed, data/inst
481system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
482system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 103772 # Table walker requests started/completed, data/inst
483system.cpu0.dtb.walker.walkRequestOrigin::total 700088 # Table walker requests started/completed, data/inst
484system.cpu0.dtb.inst_hits 0 # ITB inst hits
485system.cpu0.dtb.inst_misses 0 # ITB inst misses
486system.cpu0.dtb.read_hits 107674804 # DTB read hits
487system.cpu0.dtb.read_misses 416109 # DTB read misses
488system.cpu0.dtb.write_hits 89240851 # DTB write hits
489system.cpu0.dtb.write_misses 180207 # DTB write misses
490system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed
491system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
492system.cpu0.dtb.flush_tlb_mva_asid 46383 # Number of times TLB was flushed by MVA & ASID
493system.cpu0.dtb.flush_tlb_asid 1087 # Number of times TLB was flushed by ASID
494system.cpu0.dtb.flush_entries 37572 # Number of entries that have been flushed from TLB
495system.cpu0.dtb.align_faults 168 # Number of TLB faults due to alignment restrictions
496system.cpu0.dtb.prefetch_faults 7516 # Number of TLB faults due to prefetch
497system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
498system.cpu0.dtb.perms_faults 38101 # Number of TLB faults due to permissions restrictions
499system.cpu0.dtb.read_accesses 108090913 # DTB read accesses
500system.cpu0.dtb.write_accesses 89421058 # DTB write accesses
501system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
502system.cpu0.dtb.hits 196915655 # DTB hits
503system.cpu0.dtb.misses 596316 # DTB misses
504system.cpu0.dtb.accesses 197511971 # DTB accesses
505system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
506system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
507system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
508system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
509system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
510system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
511system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
512system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

526system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
527system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
528system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
529system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
530system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
531system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
532system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
533system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
534system.cpu0.itb.walker.walks 85428 # Table walker walks requested
535system.cpu0.itb.walker.walksLong 85428 # Table walker walks initiated with long descriptors
536system.cpu0.itb.walker.walksLongTerminationLevel::Level2 771 # Level at which table walker walks with long descriptors terminate
537system.cpu0.itb.walker.walksLongTerminationLevel::Level3 61190 # Level at which table walker walks with long descriptors terminate
538system.cpu0.itb.walker.walksSquashedBefore 10178 # Table walks squashed before starting
539system.cpu0.itb.walker.walkWaitTime::samples 75250 # Table walker wait (enqueue to first request) latency
540system.cpu0.itb.walker.walkWaitTime::mean 1283.993355 # Table walker wait (enqueue to first request) latency
541system.cpu0.itb.walker.walkWaitTime::stdev 9203.446829 # Table walker wait (enqueue to first request) latency
542system.cpu0.itb.walker.walkWaitTime::0-32767 74460 98.95% 98.95% # Table walker wait (enqueue to first request) latency
543system.cpu0.itb.walker.walkWaitTime::32768-65535 428 0.57% 99.52% # Table walker wait (enqueue to first request) latency
544system.cpu0.itb.walker.walkWaitTime::65536-98303 166 0.22% 99.74% # Table walker wait (enqueue to first request) latency
545system.cpu0.itb.walker.walkWaitTime::98304-131071 158 0.21% 99.95% # Table walker wait (enqueue to first request) latency
546system.cpu0.itb.walker.walkWaitTime::131072-163839 10 0.01% 99.96% # Table walker wait (enqueue to first request) latency
547system.cpu0.itb.walker.walkWaitTime::163840-196607 5 0.01% 99.97% # Table walker wait (enqueue to first request) latency
548system.cpu0.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency
549system.cpu0.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
550system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
551system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency
552system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
553system.cpu0.itb.walker.walkWaitTime::total 75250 # Table walker wait (enqueue to first request) latency
554system.cpu0.itb.walker.walkCompletionTime::samples 72139 # Table walker service (enqueue to completion) latency
555system.cpu0.itb.walker.walkCompletionTime::mean 23671.051720 # Table walker service (enqueue to completion) latency
556system.cpu0.itb.walker.walkCompletionTime::gmean 20466.529400 # Table walker service (enqueue to completion) latency
557system.cpu0.itb.walker.walkCompletionTime::stdev 20605.197168 # Table walker service (enqueue to completion) latency
558system.cpu0.itb.walker.walkCompletionTime::0-65535 70248 97.38% 97.38% # Table walker service (enqueue to completion) latency
559system.cpu0.itb.walker.walkCompletionTime::65536-131071 1514 2.10% 99.48% # Table walker service (enqueue to completion) latency
560system.cpu0.itb.walker.walkCompletionTime::131072-196607 196 0.27% 99.75% # Table walker service (enqueue to completion) latency
561system.cpu0.itb.walker.walkCompletionTime::196608-262143 111 0.15% 99.90% # Table walker service (enqueue to completion) latency
562system.cpu0.itb.walker.walkCompletionTime::262144-327679 47 0.07% 99.97% # Table walker service (enqueue to completion) latency
563system.cpu0.itb.walker.walkCompletionTime::327680-393215 15 0.02% 99.99% # Table walker service (enqueue to completion) latency
564system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
565system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
566system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
567system.cpu0.itb.walker.walkCompletionTime::total 72139 # Table walker service (enqueue to completion) latency
568system.cpu0.itb.walker.walksPending::samples 421639244068 # Table walker pending requests distribution
569system.cpu0.itb.walker.walksPending::mean 0.834946 # Table walker pending requests distribution
570system.cpu0.itb.walker.walksPending::stdev 0.371382 # Table walker pending requests distribution
571system.cpu0.itb.walker.walksPending::0 69614918048 16.51% 16.51% # Table walker pending requests distribution
572system.cpu0.itb.walker.walksPending::1 352004823020 83.48% 100.00% # Table walker pending requests distribution
573system.cpu0.itb.walker.walksPending::2 17379000 0.00% 100.00% # Table walker pending requests distribution
574system.cpu0.itb.walker.walksPending::3 2056500 0.00% 100.00% # Table walker pending requests distribution
575system.cpu0.itb.walker.walksPending::4 67500 0.00% 100.00% # Table walker pending requests distribution
576system.cpu0.itb.walker.walksPending::total 421639244068 # Table walker pending requests distribution
577system.cpu0.itb.walker.walkPageSizes::4K 61190 98.76% 98.76% # Table walker page sizes translated
578system.cpu0.itb.walker.walkPageSizes::2M 771 1.24% 100.00% # Table walker page sizes translated
579system.cpu0.itb.walker.walkPageSizes::total 61961 # Table walker page sizes translated
580system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
581system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85428 # Table walker requests started/completed, data/inst
582system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85428 # Table walker requests started/completed, data/inst
583system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
584system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61961 # Table walker requests started/completed, data/inst
585system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61961 # Table walker requests started/completed, data/inst
586system.cpu0.itb.walker.walkRequestOrigin::total 147389 # Table walker requests started/completed, data/inst
587system.cpu0.itb.inst_hits 231535487 # ITB inst hits
588system.cpu0.itb.inst_misses 85428 # ITB inst misses
589system.cpu0.itb.read_hits 0 # DTB read hits
590system.cpu0.itb.read_misses 0 # DTB read misses
591system.cpu0.itb.write_hits 0 # DTB write hits
592system.cpu0.itb.write_misses 0 # DTB write misses
593system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed
594system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
595system.cpu0.itb.flush_tlb_mva_asid 46383 # Number of times TLB was flushed by MVA & ASID
596system.cpu0.itb.flush_tlb_asid 1087 # Number of times TLB was flushed by ASID
597system.cpu0.itb.flush_entries 26943 # Number of entries that have been flushed from TLB
598system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
599system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
600system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
601system.cpu0.itb.perms_faults 216195 # Number of TLB faults due to permissions restrictions
602system.cpu0.itb.read_accesses 0 # DTB read accesses
603system.cpu0.itb.write_accesses 0 # DTB write accesses
604system.cpu0.itb.inst_accesses 231620915 # ITB inst accesses
605system.cpu0.itb.hits 231535487 # DTB hits
606system.cpu0.itb.misses 85428 # DTB misses
607system.cpu0.itb.accesses 231620915 # DTB accesses
608system.cpu0.numCycles 805724204 # number of cpu cycles simulated
609system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
610system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
611system.cpu0.fetch.icacheStallCycles 95731684 # Number of cycles fetch is stalled on an Icache miss
612system.cpu0.fetch.Insts 652075833 # Number of instructions fetch has processed
613system.cpu0.fetch.Branches 147637418 # Number of branches that fetch encountered
614system.cpu0.fetch.predictedBranches 87494471 # Number of branches that fetch has predicted taken
615system.cpu0.fetch.Cycles 667504198 # Number of cycles fetch has run and was not squashing or blocked
616system.cpu0.fetch.SquashCycles 15546378 # Number of cycles fetch has spent squashing
617system.cpu0.fetch.TlbCycles 1866411 # Number of cycles fetch has spent waiting for tlb
618system.cpu0.fetch.MiscStallCycles 305738 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
619system.cpu0.fetch.PendingTrapStallCycles 6228904 # Number of stall cycles due to pending traps
620system.cpu0.fetch.PendingQuiesceStallCycles 744813 # Number of stall cycles due to pending quiesce instructions
621system.cpu0.fetch.IcacheWaitRetryStallCycles 860245 # Number of stall cycles due to full MSHR
622system.cpu0.fetch.CacheLines 231319013 # Number of cache lines fetched
623system.cpu0.fetch.IcacheSquashes 1833472 # Number of outstanding Icache misses that were squashed
624system.cpu0.fetch.ItlbSquashes 28917 # Number of outstanding ITLB misses that were squashed
625system.cpu0.fetch.rateDist::samples 781015182 # Number of instructions fetched each cycle (Total)
626system.cpu0.fetch.rateDist::mean 0.979576 # Number of instructions fetched each cycle (Total)
627system.cpu0.fetch.rateDist::stdev 1.220669 # Number of instructions fetched each cycle (Total)
628system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
629system.cpu0.fetch.rateDist::0 414945915 53.13% 53.13% # Number of instructions fetched each cycle (Total)
630system.cpu0.fetch.rateDist::1 142136658 18.20% 71.33% # Number of instructions fetched each cycle (Total)
631system.cpu0.fetch.rateDist::2 48870776 6.26% 77.59% # Number of instructions fetched each cycle (Total)
632system.cpu0.fetch.rateDist::3 175061833 22.41% 100.00% # Number of instructions fetched each cycle (Total)
633system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
634system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
635system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
636system.cpu0.fetch.rateDist::total 781015182 # Number of instructions fetched each cycle (Total)
637system.cpu0.fetch.branchRate 0.183236 # Number of branch fetches per cycle
638system.cpu0.fetch.rate 0.809304 # Number of inst fetches per cycle
639system.cpu0.decode.IdleCycles 113248081 # Number of cycles decode is idle
640system.cpu0.decode.BlockedCycles 377378437 # Number of cycles decode is blocked
641system.cpu0.decode.RunCycles 245811555 # Number of cycles decode is running
642system.cpu0.decode.UnblockCycles 39067395 # Number of cycles decode is unblocking
643system.cpu0.decode.SquashCycles 5509714 # Number of cycles decode is squashing
644system.cpu0.decode.BranchResolved 21219272 # Number of times decode resolved a branch
645system.cpu0.decode.BranchMispred 2308032 # Number of times decode detected a branch misprediction
646system.cpu0.decode.DecodedInsts 677494422 # Number of instructions handled by decode
647system.cpu0.decode.SquashedInsts 25172258 # Number of squashed instructions handled by decode
648system.cpu0.rename.SquashCycles 5509714 # Number of cycles rename is squashing
649system.cpu0.rename.IdleCycles 150635102 # Number of cycles rename is idle
650system.cpu0.rename.BlockCycles 57564950 # Number of cycles rename is blocking
651system.cpu0.rename.serializeStallCycles 243777898 # count of cycles rename stalled for serializing inst
652system.cpu0.rename.RunCycles 246916319 # Number of cycles rename is running
653system.cpu0.rename.UnblockCycles 76611199 # Number of cycles rename is unblocking
654system.cpu0.rename.RenamedInsts 659282826 # Number of instructions processed by rename
655system.cpu0.rename.SquashedInsts 6463914 # Number of squashed instructions processed by rename
656system.cpu0.rename.ROBFullEvents 10193503 # Number of times rename has blocked due to ROB full
657system.cpu0.rename.IQFullEvents 302591 # Number of times rename has blocked due to IQ full
658system.cpu0.rename.LQFullEvents 345572 # Number of times rename has blocked due to LQ full
659system.cpu0.rename.SQFullEvents 40114273 # Number of times rename has blocked due to SQ full
660system.cpu0.rename.FullRegisterEvents 11761 # Number of times there has been no free registers
661system.cpu0.rename.RenamedOperands 627680154 # Number of destination operands rename has renamed
662system.cpu0.rename.RenameLookups 1013922393 # Number of register rename lookups that rename has made
663system.cpu0.rename.int_rename_lookups 779757811 # Number of integer rename lookups
664system.cpu0.rename.fp_rename_lookups 794183 # Number of floating rename lookups
665system.cpu0.rename.CommittedMaps 565536193 # Number of HB maps that are committed
666system.cpu0.rename.UndoneMaps 62143943 # Number of HB maps that are undone due to squashing
667system.cpu0.rename.serializingInsts 16063927 # count of serializing insts renamed
668system.cpu0.rename.tempSerializingInsts 14023847 # count of temporary serializing insts renamed
669system.cpu0.rename.skidInsts 79290060 # count of insts added to the skid buffer
670system.cpu0.memDep0.insertedLoads 107984972 # Number of loads inserted to the mem dependence unit.
671system.cpu0.memDep0.insertedStores 92881396 # Number of stores inserted to the mem dependence unit.
672system.cpu0.memDep0.conflictingLoads 9789553 # Number of conflicting loads.
673system.cpu0.memDep0.conflictingStores 8248701 # Number of conflicting stores.
674system.cpu0.iq.iqInstsAdded 636103677 # Number of instructions added to the IQ (excludes non-spec)
675system.cpu0.iq.iqNonSpecInstsAdded 16216212 # Number of non-speculative instructions added to the IQ
676system.cpu0.iq.iqInstsIssued 639991449 # Number of instructions issued
677system.cpu0.iq.iqSquashedInstsIssued 2906968 # Number of squashed instructions issued
678system.cpu0.iq.iqSquashedInstsExamined 58559234 # Number of squashed instructions iterated over during squash; mainly for profiling
679system.cpu0.iq.iqSquashedOperandsExamined 38038909 # Number of squashed operands that are examined and possibly removed from graph
680system.cpu0.iq.iqSquashedNonSpecRemoved 288402 # Number of squashed non-spec instructions that were removed
681system.cpu0.iq.issued_per_cycle::samples 781015182 # Number of insts issued each cycle
682system.cpu0.iq.issued_per_cycle::mean 0.819435 # Number of insts issued each cycle
683system.cpu0.iq.issued_per_cycle::stdev 1.071222 # Number of insts issued each cycle
684system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
685system.cpu0.iq.issued_per_cycle::0 434056489 55.58% 55.58% # Number of insts issued each cycle
686system.cpu0.iq.issued_per_cycle::1 142602713 18.26% 73.83% # Number of insts issued each cycle
687system.cpu0.iq.issued_per_cycle::2 124298977 15.92% 89.75% # Number of insts issued each cycle
688system.cpu0.iq.issued_per_cycle::3 71442121 9.15% 98.90% # Number of insts issued each cycle
689system.cpu0.iq.issued_per_cycle::4 8609991 1.10% 100.00% # Number of insts issued each cycle
690system.cpu0.iq.issued_per_cycle::5 4891 0.00% 100.00% # Number of insts issued each cycle
691system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
692system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
693system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
694system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
695system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
696system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
697system.cpu0.iq.issued_per_cycle::total 781015182 # Number of insts issued each cycle
698system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
699system.cpu0.iq.fu_full::IntAlu 67040735 45.54% 45.54% # attempts to use FU when none available
700system.cpu0.iq.fu_full::IntMult 53703 0.04% 45.58% # attempts to use FU when none available
701system.cpu0.iq.fu_full::IntDiv 26002 0.02% 45.60% # attempts to use FU when none available
702system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.60% # attempts to use FU when none available
703system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.60% # attempts to use FU when none available
704system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.60% # attempts to use FU when none available
705system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.60% # attempts to use FU when none available
706system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.60% # attempts to use FU when none available
707system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.60% # attempts to use FU when none available
708system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.60% # attempts to use FU when none available
709system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.60% # attempts to use FU when none available
710system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.60% # attempts to use FU when none available
711system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.60% # attempts to use FU when none available
712system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.60% # attempts to use FU when none available
713system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.60% # attempts to use FU when none available
714system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.60% # attempts to use FU when none available
715system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.60% # attempts to use FU when none available
716system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.60% # attempts to use FU when none available
717system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.60% # attempts to use FU when none available
718system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.60% # attempts to use FU when none available
719system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.60% # attempts to use FU when none available
720system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.60% # attempts to use FU when none available
721system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.60% # attempts to use FU when none available
722system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.60% # attempts to use FU when none available
723system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.60% # attempts to use FU when none available
724system.cpu0.iq.fu_full::SimdFloatMisc 14 0.00% 45.60% # attempts to use FU when none available
725system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.60% # attempts to use FU when none available
726system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.60% # attempts to use FU when none available
727system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.60% # attempts to use FU when none available
728system.cpu0.iq.fu_full::MemRead 38206404 25.96% 71.55% # attempts to use FU when none available
729system.cpu0.iq.fu_full::MemWrite 41875543 28.45% 100.00% # attempts to use FU when none available
730system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
731system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
732system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
733system.cpu0.iq.FU_type_0::IntAlu 436779538 68.25% 68.25% # Type of FU issued
734system.cpu0.iq.FU_type_0::IntMult 1517289 0.24% 68.48% # Type of FU issued
735system.cpu0.iq.FU_type_0::IntDiv 81855 0.01% 68.50% # Type of FU issued
736system.cpu0.iq.FU_type_0::FloatAdd 5 0.00% 68.50% # Type of FU issued
737system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.50% # Type of FU issued
738system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.50% # Type of FU issued
739system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.50% # Type of FU issued
740system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.50% # Type of FU issued
741system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.50% # Type of FU issued
742system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.50% # Type of FU issued
743system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.50% # Type of FU issued
744system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.50% # Type of FU issued
745system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.50% # Type of FU issued
746system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.50% # Type of FU issued
747system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.50% # Type of FU issued
748system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.50% # Type of FU issued
749system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.50% # Type of FU issued
750system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.50% # Type of FU issued
751system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.50% # Type of FU issued
752system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.50% # Type of FU issued
753system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.50% # Type of FU issued
754system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.50% # Type of FU issued
755system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.50% # Type of FU issued
756system.cpu0.iq.FU_type_0::SimdFloatCvt 23 0.00% 68.50% # Type of FU issued
757system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.50% # Type of FU issued
758system.cpu0.iq.FU_type_0::SimdFloatMisc 47604 0.01% 68.51% # Type of FU issued
759system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.51% # Type of FU issued
760system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.51% # Type of FU issued
761system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.51% # Type of FU issued
762system.cpu0.iq.FU_type_0::MemRead 110932479 17.33% 85.84% # Type of FU issued
763system.cpu0.iq.FU_type_0::MemWrite 90632632 14.16% 100.00% # Type of FU issued
764system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
765system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
766system.cpu0.iq.FU_type_0::total 639991449 # Type of FU issued
767system.cpu0.iq.rate 0.794306 # Inst issue rate
768system.cpu0.iq.fu_busy_cnt 147202401 # FU busy when requested
769system.cpu0.iq.fu_busy_rate 0.230007 # FU busy rate (busy events/executed inst)
770system.cpu0.iq.int_inst_queue_reads 2209837146 # Number of integer instruction queue reads
771system.cpu0.iq.int_inst_queue_writes 710527601 # Number of integer instruction queue writes
772system.cpu0.iq.int_inst_queue_wakeup_accesses 621905864 # Number of integer instruction queue wakeup accesses
773system.cpu0.iq.fp_inst_queue_reads 1270303 # Number of floating instruction queue reads
774system.cpu0.iq.fp_inst_queue_writes 504170 # Number of floating instruction queue writes
775system.cpu0.iq.fp_inst_queue_wakeup_accesses 467307 # Number of floating instruction queue wakeup accesses
776system.cpu0.iq.int_alu_accesses 786402566 # Number of integer alu accesses
777system.cpu0.iq.fp_alu_accesses 791283 # Number of floating point alu accesses
778system.cpu0.iew.lsq.thread0.forwLoads 2962367 # Number of loads that had data forwarded from stores
779system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
780system.cpu0.iew.lsq.thread0.squashedLoads 13371443 # Number of loads squashed
781system.cpu0.iew.lsq.thread0.ignoredResponses 16751 # Number of memory responses ignored because the instruction is squashed
782system.cpu0.iew.lsq.thread0.memOrderViolation 153989 # Number of memory ordering violations
783system.cpu0.iew.lsq.thread0.squashedStores 6295959 # Number of stores squashed
784system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
785system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
786system.cpu0.iew.lsq.thread0.rescheduledLoads 2934112 # Number of loads that were rescheduled
787system.cpu0.iew.lsq.thread0.cacheBlocked 4671160 # Number of times an access to memory failed due to the cache being blocked
788system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
789system.cpu0.iew.iewSquashCycles 5509714 # Number of cycles IEW is squashing
790system.cpu0.iew.iewBlockCycles 7058035 # Number of cycles IEW is blocking
791system.cpu0.iew.iewUnblockCycles 5778589 # Number of cycles IEW is unblocking
792system.cpu0.iew.iewDispatchedInsts 652441938 # Number of instructions dispatched to IQ
793system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
794system.cpu0.iew.iewDispLoadInsts 107984972 # Number of dispatched load instructions
795system.cpu0.iew.iewDispStoreInsts 92881396 # Number of dispatched store instructions
796system.cpu0.iew.iewDispNonSpecInsts 13772451 # Number of dispatched non-speculative instructions
797system.cpu0.iew.iewIQFullEvents 68630 # Number of times the IQ has become full, causing a stall
798system.cpu0.iew.iewLSQFullEvents 5639093 # Number of times the LSQ has become full, causing a stall
799system.cpu0.iew.memOrderViolationEvents 153989 # Number of memory order violations
800system.cpu0.iew.predictedTakenIncorrect 2201982 # Number of branches that were predicted taken incorrectly
801system.cpu0.iew.predictedNotTakenIncorrect 3098287 # Number of branches that were predicted not taken incorrectly
802system.cpu0.iew.branchMispredicts 5300269 # Number of branch mispredicts detected at execute
803system.cpu0.iew.iewExecutedInsts 631633854 # Number of executed instructions
804system.cpu0.iew.iewExecLoadInsts 107665614 # Number of load instructions executed
805system.cpu0.iew.iewExecSquashedInsts 7773689 # Number of squashed instructions skipped in execute
806system.cpu0.iew.exec_swp 0 # number of swp insts executed
807system.cpu0.iew.exec_nop 122049 # number of nop insts executed
808system.cpu0.iew.exec_refs 196907522 # number of memory reference insts executed
809system.cpu0.iew.exec_branches 119104624 # Number of branches executed
810system.cpu0.iew.exec_stores 89241908 # Number of stores executed
811system.cpu0.iew.exec_rate 0.783933 # Inst execution rate
812system.cpu0.iew.wb_sent 623170550 # cumulative count of insts sent to commit
813system.cpu0.iew.wb_count 622373171 # cumulative count of insts written-back
814system.cpu0.iew.wb_producers 301982038 # num instructions producing a value
815system.cpu0.iew.wb_consumers 495557723 # num instructions consuming a value
816system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
817system.cpu0.iew.wb_rate 0.772439 # insts written-back per cycle
818system.cpu0.iew.wb_fanout 0.609378 # average fanout of values written-back
819system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
820system.cpu0.commit.commitSquashedInsts 51133197 # The number of squashed insts skipped by commit
821system.cpu0.commit.commitNonSpecStalls 15927810 # The number of times commit has been forced to stall to communicate backwards
822system.cpu0.commit.branchMispredicts 4984345 # The number of times a branch was mispredicted
823system.cpu0.commit.committed_per_cycle::samples 771348242 # Number of insts commited each cycle
824system.cpu0.commit.committed_per_cycle::mean 0.769770 # Number of insts commited each cycle
825system.cpu0.commit.committed_per_cycle::stdev 1.572751 # Number of insts commited each cycle
826system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
827system.cpu0.commit.committed_per_cycle::0 513096769 66.52% 66.52% # Number of insts commited each cycle
828system.cpu0.commit.committed_per_cycle::1 132148168 17.13% 83.65% # Number of insts commited each cycle
829system.cpu0.commit.committed_per_cycle::2 58179832 7.54% 91.19% # Number of insts commited each cycle
830system.cpu0.commit.committed_per_cycle::3 19360594 2.51% 93.70% # Number of insts commited each cycle
831system.cpu0.commit.committed_per_cycle::4 14004722 1.82% 95.52% # Number of insts commited each cycle
832system.cpu0.commit.committed_per_cycle::5 9477117 1.23% 96.75% # Number of insts commited each cycle
833system.cpu0.commit.committed_per_cycle::6 6473381 0.84% 97.59% # Number of insts commited each cycle
834system.cpu0.commit.committed_per_cycle::7 3935015 0.51% 98.10% # Number of insts commited each cycle
835system.cpu0.commit.committed_per_cycle::8 14672644 1.90% 100.00% # Number of insts commited each cycle
836system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
837system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
838system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
839system.cpu0.commit.committed_per_cycle::total 771348242 # Number of insts commited each cycle
840system.cpu0.commit.committedInsts 504955538 # Number of instructions committed
841system.cpu0.commit.committedOps 593760630 # Number of ops (including micro ops) committed
842system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
843system.cpu0.commit.refs 181198957 # Number of memory references committed
844system.cpu0.commit.loads 94613526 # Number of loads committed
845system.cpu0.commit.membars 4060839 # Number of memory barriers committed
846system.cpu0.commit.branches 113014510 # Number of branches committed
847system.cpu0.commit.fp_insts 458000 # Number of committed floating point instructions.
848system.cpu0.commit.int_insts 545152087 # Number of committed integer instructions.
849system.cpu0.commit.function_calls 14971844 # Number of function calls committed.
850system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
851system.cpu0.commit.op_class_0::IntAlu 411193864 69.25% 69.25% # Class of committed instruction
852system.cpu0.commit.op_class_0::IntMult 1260833 0.21% 69.46% # Class of committed instruction
853system.cpu0.commit.op_class_0::IntDiv 65173 0.01% 69.48% # Class of committed instruction
854system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.48% # Class of committed instruction
855system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.48% # Class of committed instruction
856system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.48% # Class of committed instruction
857system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.48% # Class of committed instruction
858system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.48% # Class of committed instruction
859system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.48% # Class of committed instruction
860system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.48% # Class of committed instruction
861system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.48% # Class of committed instruction
862system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.48% # Class of committed instruction
863system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.48% # Class of committed instruction
864system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.48% # Class of committed instruction
865system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.48% # Class of committed instruction
866system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.48% # Class of committed instruction
867system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.48% # Class of committed instruction
868system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.48% # Class of committed instruction
869system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.48% # Class of committed instruction
870system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.48% # Class of committed instruction
871system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.48% # Class of committed instruction
872system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.48% # Class of committed instruction
873system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.48% # Class of committed instruction
874system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.48% # Class of committed instruction
875system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.48% # Class of committed instruction
876system.cpu0.commit.op_class_0::SimdFloatMisc 41761 0.01% 69.48% # Class of committed instruction
877system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.48% # Class of committed instruction
878system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.48% # Class of committed instruction
879system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.48% # Class of committed instruction
880system.cpu0.commit.op_class_0::MemRead 94613526 15.93% 85.42% # Class of committed instruction
881system.cpu0.commit.op_class_0::MemWrite 86585431 14.58% 100.00% # Class of committed instruction
882system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
883system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
884system.cpu0.commit.op_class_0::total 593760630 # Class of committed instruction
885system.cpu0.commit.bw_lim_events 14672644 # number cycles where commit BW limit reached
886system.cpu0.rob.rob_reads 1397369391 # The number of ROB reads
887system.cpu0.rob.rob_writes 1299419087 # The number of ROB writes
888system.cpu0.timesIdled 1071653 # Number of times that the entire CPU went into an idle state and unscheduled itself
889system.cpu0.idleCycles 24709022 # Total number of cycles that the CPU has spent unscheduled due to idling
890system.cpu0.quiesceCycles 93813929115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
891system.cpu0.committedInsts 504955538 # Number of Instructions Simulated
892system.cpu0.committedOps 593760630 # Number of Ops (including micro ops) Simulated
893system.cpu0.cpi 1.595634 # CPI: Cycles Per Instruction
894system.cpu0.cpi_total 1.595634 # CPI: Total CPI of All Threads
895system.cpu0.ipc 0.626710 # IPC: Instructions Per Cycle
896system.cpu0.ipc_total 0.626710 # IPC: Total IPC of All Threads
897system.cpu0.int_regfile_reads 746722296 # number of integer regfile reads
898system.cpu0.int_regfile_writes 443322911 # number of integer regfile writes
899system.cpu0.fp_regfile_reads 778801 # number of floating regfile reads
900system.cpu0.fp_regfile_writes 335108 # number of floating regfile writes
901system.cpu0.cc_regfile_reads 136612374 # number of cc regfile reads
902system.cpu0.cc_regfile_writes 137527114 # number of cc regfile writes
903system.cpu0.misc_regfile_reads 1389482326 # number of misc regfile reads
904system.cpu0.misc_regfile_writes 16167899 # number of misc regfile writes
905system.cpu0.dcache.tags.replacements 6374252 # number of replacements
906system.cpu0.dcache.tags.tagsinuse 504.525126 # Cycle average of tags in use
907system.cpu0.dcache.tags.total_refs 168612051 # Total number of references to valid blocks.
908system.cpu0.dcache.tags.sampled_refs 6374762 # Sample count of references to valid blocks.
909system.cpu0.dcache.tags.avg_refs 26.449937 # Average number of references to valid blocks.
910system.cpu0.dcache.tags.warmup_cycle 1887138000 # Cycle when the warmup percentage was hit.
911system.cpu0.dcache.tags.occ_blocks::cpu0.data 504.525126 # Average occupied blocks per requestor
912system.cpu0.dcache.tags.occ_percent::cpu0.data 0.985401 # Average percentage of cache occupancy
913system.cpu0.dcache.tags.occ_percent::total 0.985401 # Average percentage of cache occupancy
914system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
915system.cpu0.dcache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id
916system.cpu0.dcache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id
917system.cpu0.dcache.tags.age_task_id_blocks_1024::2 61 # Occupied blocks per task id
918system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
919system.cpu0.dcache.tags.tag_accesses 375986188 # Number of tag accesses
920system.cpu0.dcache.tags.data_accesses 375986188 # Number of data accesses
921system.cpu0.dcache.ReadReq_hits::cpu0.data 87724319 # number of ReadReq hits
922system.cpu0.dcache.ReadReq_hits::total 87724319 # number of ReadReq hits
923system.cpu0.dcache.WriteReq_hits::cpu0.data 75477797 # number of WriteReq hits
924system.cpu0.dcache.WriteReq_hits::total 75477797 # number of WriteReq hits
925system.cpu0.dcache.SoftPFReq_hits::cpu0.data 231729 # number of SoftPFReq hits
926system.cpu0.dcache.SoftPFReq_hits::total 231729 # number of SoftPFReq hits
927system.cpu0.dcache.WriteLineReq_hits::cpu0.data 266468 # number of WriteLineReq hits
928system.cpu0.dcache.WriteLineReq_hits::total 266468 # number of WriteLineReq hits
929system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2022541 # number of LoadLockedReq hits
930system.cpu0.dcache.LoadLockedReq_hits::total 2022541 # number of LoadLockedReq hits
931system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2052696 # number of StoreCondReq hits
932system.cpu0.dcache.StoreCondReq_hits::total 2052696 # number of StoreCondReq hits
933system.cpu0.dcache.demand_hits::cpu0.data 163202116 # number of demand (read+write) hits
934system.cpu0.dcache.demand_hits::total 163202116 # number of demand (read+write) hits
935system.cpu0.dcache.overall_hits::cpu0.data 163433845 # number of overall hits
936system.cpu0.dcache.overall_hits::total 163433845 # number of overall hits
937system.cpu0.dcache.ReadReq_misses::cpu0.data 7197565 # number of ReadReq misses
938system.cpu0.dcache.ReadReq_misses::total 7197565 # number of ReadReq misses
939system.cpu0.dcache.WriteReq_misses::cpu0.data 7724152 # number of WriteReq misses
940system.cpu0.dcache.WriteReq_misses::total 7724152 # number of WriteReq misses
941system.cpu0.dcache.SoftPFReq_misses::cpu0.data 724383 # number of SoftPFReq misses
942system.cpu0.dcache.SoftPFReq_misses::total 724383 # number of SoftPFReq misses
943system.cpu0.dcache.WriteLineReq_misses::cpu0.data 844788 # number of WriteLineReq misses
944system.cpu0.dcache.WriteLineReq_misses::total 844788 # number of WriteLineReq misses
945system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 278463 # number of LoadLockedReq misses
946system.cpu0.dcache.LoadLockedReq_misses::total 278463 # number of LoadLockedReq misses
947system.cpu0.dcache.StoreCondReq_misses::cpu0.data 208196 # number of StoreCondReq misses
948system.cpu0.dcache.StoreCondReq_misses::total 208196 # number of StoreCondReq misses
949system.cpu0.dcache.demand_misses::cpu0.data 14921717 # number of demand (read+write) misses
950system.cpu0.dcache.demand_misses::total 14921717 # number of demand (read+write) misses
951system.cpu0.dcache.overall_misses::cpu0.data 15646100 # number of overall misses
952system.cpu0.dcache.overall_misses::total 15646100 # number of overall misses
953system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 108620779500 # number of ReadReq miss cycles
954system.cpu0.dcache.ReadReq_miss_latency::total 108620779500 # number of ReadReq miss cycles
955system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 138974834179 # number of WriteReq miss cycles
956system.cpu0.dcache.WriteReq_miss_latency::total 138974834179 # number of WriteReq miss cycles
957system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 74732911806 # number of WriteLineReq miss cycles
958system.cpu0.dcache.WriteLineReq_miss_latency::total 74732911806 # number of WriteLineReq miss cycles
959system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4099802000 # number of LoadLockedReq miss cycles
960system.cpu0.dcache.LoadLockedReq_miss_latency::total 4099802000 # number of LoadLockedReq miss cycles
961system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4408839000 # number of StoreCondReq miss cycles
962system.cpu0.dcache.StoreCondReq_miss_latency::total 4408839000 # number of StoreCondReq miss cycles
963system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3050500 # number of StoreCondFailReq miss cycles
964system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3050500 # number of StoreCondFailReq miss cycles
965system.cpu0.dcache.demand_miss_latency::cpu0.data 247595613679 # number of demand (read+write) miss cycles
966system.cpu0.dcache.demand_miss_latency::total 247595613679 # number of demand (read+write) miss cycles
967system.cpu0.dcache.overall_miss_latency::cpu0.data 247595613679 # number of overall miss cycles
968system.cpu0.dcache.overall_miss_latency::total 247595613679 # number of overall miss cycles
969system.cpu0.dcache.ReadReq_accesses::cpu0.data 94921884 # number of ReadReq accesses(hits+misses)
970system.cpu0.dcache.ReadReq_accesses::total 94921884 # number of ReadReq accesses(hits+misses)
971system.cpu0.dcache.WriteReq_accesses::cpu0.data 83201949 # number of WriteReq accesses(hits+misses)
972system.cpu0.dcache.WriteReq_accesses::total 83201949 # number of WriteReq accesses(hits+misses)
973system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 956112 # number of SoftPFReq accesses(hits+misses)
974system.cpu0.dcache.SoftPFReq_accesses::total 956112 # number of SoftPFReq accesses(hits+misses)
975system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1111256 # number of WriteLineReq accesses(hits+misses)
976system.cpu0.dcache.WriteLineReq_accesses::total 1111256 # number of WriteLineReq accesses(hits+misses)
977system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2301004 # number of LoadLockedReq accesses(hits+misses)
978system.cpu0.dcache.LoadLockedReq_accesses::total 2301004 # number of LoadLockedReq accesses(hits+misses)
979system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2260892 # number of StoreCondReq accesses(hits+misses)
980system.cpu0.dcache.StoreCondReq_accesses::total 2260892 # number of StoreCondReq accesses(hits+misses)
981system.cpu0.dcache.demand_accesses::cpu0.data 178123833 # number of demand (read+write) accesses
982system.cpu0.dcache.demand_accesses::total 178123833 # number of demand (read+write) accesses
983system.cpu0.dcache.overall_accesses::cpu0.data 179079945 # number of overall (read+write) accesses
984system.cpu0.dcache.overall_accesses::total 179079945 # number of overall (read+write) accesses
985system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075826 # miss rate for ReadReq accesses
986system.cpu0.dcache.ReadReq_miss_rate::total 0.075826 # miss rate for ReadReq accesses
987system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.092836 # miss rate for WriteReq accesses
988system.cpu0.dcache.WriteReq_miss_rate::total 0.092836 # miss rate for WriteReq accesses
989system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.757634 # miss rate for SoftPFReq accesses
990system.cpu0.dcache.SoftPFReq_miss_rate::total 0.757634 # miss rate for SoftPFReq accesses
991system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760210 # miss rate for WriteLineReq accesses
992system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760210 # miss rate for WriteLineReq accesses
993system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.121018 # miss rate for LoadLockedReq accesses
994system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.121018 # miss rate for LoadLockedReq accesses
995system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.092086 # miss rate for StoreCondReq accesses
996system.cpu0.dcache.StoreCondReq_miss_rate::total 0.092086 # miss rate for StoreCondReq accesses
997system.cpu0.dcache.demand_miss_rate::cpu0.data 0.083772 # miss rate for demand accesses
998system.cpu0.dcache.demand_miss_rate::total 0.083772 # miss rate for demand accesses
999system.cpu0.dcache.overall_miss_rate::cpu0.data 0.087369 # miss rate for overall accesses
1000system.cpu0.dcache.overall_miss_rate::total 0.087369 # miss rate for overall accesses
1001system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15091.323177 # average ReadReq miss latency
1002system.cpu0.dcache.ReadReq_avg_miss_latency::total 15091.323177 # average ReadReq miss latency
1003system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17992.244868 # average WriteReq miss latency
1004system.cpu0.dcache.WriteReq_avg_miss_latency::total 17992.244868 # average WriteReq miss latency
1005system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 88463.510142 # average WriteLineReq miss latency
1006system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 88463.510142 # average WriteLineReq miss latency
1007system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14722.968581 # average LoadLockedReq miss latency
1008system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14722.968581 # average LoadLockedReq miss latency
1009system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21176.386674 # average StoreCondReq miss latency
1010system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21176.386674 # average StoreCondReq miss latency
1011system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
1012system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
1013system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16592.970747 # average overall miss latency
1014system.cpu0.dcache.demand_avg_miss_latency::total 16592.970747 # average overall miss latency
1015system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15824.749534 # average overall miss latency
1016system.cpu0.dcache.overall_avg_miss_latency::total 15824.749534 # average overall miss latency
1017system.cpu0.dcache.blocked_cycles::no_mshrs 23148520 # number of cycles access was blocked
1018system.cpu0.dcache.blocked_cycles::no_targets 20510394 # number of cycles access was blocked
1019system.cpu0.dcache.blocked::no_mshrs 766944 # number of cycles access was blocked
1020system.cpu0.dcache.blocked::no_targets 746852 # number of cycles access was blocked
1021system.cpu0.dcache.avg_blocked_cycles::no_mshrs 30.182803 # average number of cycles each access was blocked
1022system.cpu0.dcache.avg_blocked_cycles::no_targets 27.462461 # average number of cycles each access was blocked
1023system.cpu0.dcache.fast_writes 0 # number of fast writes performed
1024system.cpu0.dcache.cache_copies 0 # number of cache copies performed
1025system.cpu0.dcache.writebacks::writebacks 4317679 # number of writebacks
1026system.cpu0.dcache.writebacks::total 4317679 # number of writebacks
1027system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3700903 # number of ReadReq MSHR hits
1028system.cpu0.dcache.ReadReq_mshr_hits::total 3700903 # number of ReadReq MSHR hits
1029system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6185217 # number of WriteReq MSHR hits
1030system.cpu0.dcache.WriteReq_mshr_hits::total 6185217 # number of WriteReq MSHR hits
1031system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 5102 # number of WriteLineReq MSHR hits
1032system.cpu0.dcache.WriteLineReq_mshr_hits::total 5102 # number of WriteLineReq MSHR hits
1033system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 141775 # number of LoadLockedReq MSHR hits
1034system.cpu0.dcache.LoadLockedReq_mshr_hits::total 141775 # number of LoadLockedReq MSHR hits
1035system.cpu0.dcache.demand_mshr_hits::cpu0.data 9886120 # number of demand (read+write) MSHR hits
1036system.cpu0.dcache.demand_mshr_hits::total 9886120 # number of demand (read+write) MSHR hits
1037system.cpu0.dcache.overall_mshr_hits::cpu0.data 9886120 # number of overall MSHR hits
1038system.cpu0.dcache.overall_mshr_hits::total 9886120 # number of overall MSHR hits
1039system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3496662 # number of ReadReq MSHR misses
1040system.cpu0.dcache.ReadReq_mshr_misses::total 3496662 # number of ReadReq MSHR misses
1041system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1538935 # number of WriteReq MSHR misses
1042system.cpu0.dcache.WriteReq_mshr_misses::total 1538935 # number of WriteReq MSHR misses
1043system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 717217 # number of SoftPFReq MSHR misses
1044system.cpu0.dcache.SoftPFReq_mshr_misses::total 717217 # number of SoftPFReq MSHR misses
1045system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 839686 # number of WriteLineReq MSHR misses
1046system.cpu0.dcache.WriteLineReq_mshr_misses::total 839686 # number of WriteLineReq MSHR misses
1047system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 136688 # number of LoadLockedReq MSHR misses
1048system.cpu0.dcache.LoadLockedReq_mshr_misses::total 136688 # number of LoadLockedReq MSHR misses
1049system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 208181 # number of StoreCondReq MSHR misses
1050system.cpu0.dcache.StoreCondReq_mshr_misses::total 208181 # number of StoreCondReq MSHR misses
1051system.cpu0.dcache.demand_mshr_misses::cpu0.data 5035597 # number of demand (read+write) MSHR misses
1052system.cpu0.dcache.demand_mshr_misses::total 5035597 # number of demand (read+write) MSHR misses
1053system.cpu0.dcache.overall_mshr_misses::cpu0.data 5752814 # number of overall MSHR misses
1054system.cpu0.dcache.overall_mshr_misses::total 5752814 # number of overall MSHR misses
1055system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 21352 # number of ReadReq MSHR uncacheable
1056system.cpu0.dcache.ReadReq_mshr_uncacheable::total 21352 # number of ReadReq MSHR uncacheable
1057system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 23308 # number of WriteReq MSHR uncacheable
1058system.cpu0.dcache.WriteReq_mshr_uncacheable::total 23308 # number of WriteReq MSHR uncacheable
1059system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 44660 # number of overall MSHR uncacheable misses
1060system.cpu0.dcache.overall_mshr_uncacheable_misses::total 44660 # number of overall MSHR uncacheable misses
1061system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50025996500 # number of ReadReq MSHR miss cycles
1062system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50025996500 # number of ReadReq MSHR miss cycles
1063system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29968345030 # number of WriteReq MSHR miss cycles
1064system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29968345030 # number of WriteReq MSHR miss cycles
1065system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17752964500 # number of SoftPFReq MSHR miss cycles
1066system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17752964500 # number of SoftPFReq MSHR miss cycles
1067system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 73677446306 # number of WriteLineReq MSHR miss cycles
1068system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 73677446306 # number of WriteLineReq MSHR miss cycles
1069system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1889285500 # number of LoadLockedReq MSHR miss cycles
1070system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1889285500 # number of LoadLockedReq MSHR miss cycles
1071system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4200723000 # number of StoreCondReq MSHR miss cycles
1072system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4200723000 # number of StoreCondReq MSHR miss cycles
1073system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2985500 # number of StoreCondFailReq MSHR miss cycles
1074system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2985500 # number of StoreCondFailReq MSHR miss cycles
1075system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 79994341530 # number of demand (read+write) MSHR miss cycles
1076system.cpu0.dcache.demand_mshr_miss_latency::total 79994341530 # number of demand (read+write) MSHR miss cycles
1077system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 97747306030 # number of overall MSHR miss cycles
1078system.cpu0.dcache.overall_mshr_miss_latency::total 97747306030 # number of overall MSHR miss cycles
1079system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3896297500 # number of ReadReq MSHR uncacheable cycles
1080system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3896297500 # number of ReadReq MSHR uncacheable cycles
1081system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4053651000 # number of WriteReq MSHR uncacheable cycles
1082system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4053651000 # number of WriteReq MSHR uncacheable cycles
1083system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7949948500 # number of overall MSHR uncacheable cycles
1084system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7949948500 # number of overall MSHR uncacheable cycles
1085system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036837 # mshr miss rate for ReadReq accesses
1086system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036837 # mshr miss rate for ReadReq accesses
1087system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018496 # mshr miss rate for WriteReq accesses
1088system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018496 # mshr miss rate for WriteReq accesses
1089system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.750139 # mshr miss rate for SoftPFReq accesses
1090system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.750139 # mshr miss rate for SoftPFReq accesses
1091system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.755619 # mshr miss rate for WriteLineReq accesses
1092system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.755619 # mshr miss rate for WriteLineReq accesses
1093system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059404 # mshr miss rate for LoadLockedReq accesses
1094system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059404 # mshr miss rate for LoadLockedReq accesses
1095system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092079 # mshr miss rate for StoreCondReq accesses
1096system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092079 # mshr miss rate for StoreCondReq accesses
1097system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028270 # mshr miss rate for demand accesses
1098system.cpu0.dcache.demand_mshr_miss_rate::total 0.028270 # mshr miss rate for demand accesses
1099system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032124 # mshr miss rate for overall accesses
1100system.cpu0.dcache.overall_mshr_miss_rate::total 0.032124 # mshr miss rate for overall accesses
1101system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14306.786444 # average ReadReq mshr miss latency
1102system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14306.786444 # average ReadReq mshr miss latency
1103system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19473.431321 # average WriteReq mshr miss latency
1104system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19473.431321 # average WriteReq mshr miss latency
1105system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24752.570700 # average SoftPFReq mshr miss latency
1106system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24752.570700 # average SoftPFReq mshr miss latency
1107system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 87744.045162 # average WriteLineReq mshr miss latency
1108system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 87744.045162 # average WriteLineReq mshr miss latency
1109system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13821.882682 # average LoadLockedReq mshr miss latency
1110system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13821.882682 # average LoadLockedReq mshr miss latency
1111system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20178.224718 # average StoreCondReq mshr miss latency
1112system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20178.224718 # average StoreCondReq mshr miss latency
1113system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
1114system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1115system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15885.771147 # average overall mshr miss latency
1116system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15885.771147 # average overall mshr miss latency
1117system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16991.216130 # average overall mshr miss latency
1118system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16991.216130 # average overall mshr miss latency
1119system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182479.275946 # average ReadReq mshr uncacheable latency
1120system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182479.275946 # average ReadReq mshr uncacheable latency
1121system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 173916.723872 # average WriteReq mshr uncacheable latency
1122system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 173916.723872 # average WriteReq mshr uncacheable latency
1123system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 178010.490372 # average overall mshr uncacheable latency
1124system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 178010.490372 # average overall mshr uncacheable latency
1125system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1126system.cpu0.icache.tags.replacements 6538162 # number of replacements
1127system.cpu0.icache.tags.tagsinuse 511.955601 # Cycle average of tags in use
1128system.cpu0.icache.tags.total_refs 224372588 # Total number of references to valid blocks.
1129system.cpu0.icache.tags.sampled_refs 6538674 # Sample count of references to valid blocks.
1130system.cpu0.icache.tags.avg_refs 34.314693 # Average number of references to valid blocks.
1131system.cpu0.icache.tags.warmup_cycle 17322639000 # Cycle when the warmup percentage was hit.
1132system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.955601 # Average occupied blocks per requestor
1133system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999913 # Average percentage of cache occupancy
1134system.cpu0.icache.tags.occ_percent::total 0.999913 # Average percentage of cache occupancy
1135system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1136system.cpu0.icache.tags.age_task_id_blocks_1024::0 309 # Occupied blocks per task id
1137system.cpu0.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id
1138system.cpu0.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id
1139system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1140system.cpu0.icache.tags.tag_accesses 469120906 # Number of tag accesses
1141system.cpu0.icache.tags.data_accesses 469120906 # Number of data accesses
1142system.cpu0.icache.ReadReq_hits::cpu0.inst 224372588 # number of ReadReq hits
1143system.cpu0.icache.ReadReq_hits::total 224372588 # number of ReadReq hits
1144system.cpu0.icache.demand_hits::cpu0.inst 224372588 # number of demand (read+write) hits
1145system.cpu0.icache.demand_hits::total 224372588 # number of demand (read+write) hits
1146system.cpu0.icache.overall_hits::cpu0.inst 224372588 # number of overall hits
1147system.cpu0.icache.overall_hits::total 224372588 # number of overall hits
1148system.cpu0.icache.ReadReq_misses::cpu0.inst 6918516 # number of ReadReq misses
1149system.cpu0.icache.ReadReq_misses::total 6918516 # number of ReadReq misses
1150system.cpu0.icache.demand_misses::cpu0.inst 6918516 # number of demand (read+write) misses
1151system.cpu0.icache.demand_misses::total 6918516 # number of demand (read+write) misses
1152system.cpu0.icache.overall_misses::cpu0.inst 6918516 # number of overall misses
1153system.cpu0.icache.overall_misses::total 6918516 # number of overall misses
1154system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 73530599413 # number of ReadReq miss cycles
1155system.cpu0.icache.ReadReq_miss_latency::total 73530599413 # number of ReadReq miss cycles
1156system.cpu0.icache.demand_miss_latency::cpu0.inst 73530599413 # number of demand (read+write) miss cycles
1157system.cpu0.icache.demand_miss_latency::total 73530599413 # number of demand (read+write) miss cycles
1158system.cpu0.icache.overall_miss_latency::cpu0.inst 73530599413 # number of overall miss cycles
1159system.cpu0.icache.overall_miss_latency::total 73530599413 # number of overall miss cycles
1160system.cpu0.icache.ReadReq_accesses::cpu0.inst 231291104 # number of ReadReq accesses(hits+misses)
1161system.cpu0.icache.ReadReq_accesses::total 231291104 # number of ReadReq accesses(hits+misses)
1162system.cpu0.icache.demand_accesses::cpu0.inst 231291104 # number of demand (read+write) accesses
1163system.cpu0.icache.demand_accesses::total 231291104 # number of demand (read+write) accesses
1164system.cpu0.icache.overall_accesses::cpu0.inst 231291104 # number of overall (read+write) accesses
1165system.cpu0.icache.overall_accesses::total 231291104 # number of overall (read+write) accesses
1166system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029913 # miss rate for ReadReq accesses
1167system.cpu0.icache.ReadReq_miss_rate::total 0.029913 # miss rate for ReadReq accesses
1168system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029913 # miss rate for demand accesses
1169system.cpu0.icache.demand_miss_rate::total 0.029913 # miss rate for demand accesses
1170system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029913 # miss rate for overall accesses
1171system.cpu0.icache.overall_miss_rate::total 0.029913 # miss rate for overall accesses
1172system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10628.088366 # average ReadReq miss latency
1173system.cpu0.icache.ReadReq_avg_miss_latency::total 10628.088366 # average ReadReq miss latency
1174system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10628.088366 # average overall miss latency
1175system.cpu0.icache.demand_avg_miss_latency::total 10628.088366 # average overall miss latency
1176system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10628.088366 # average overall miss latency
1177system.cpu0.icache.overall_avg_miss_latency::total 10628.088366 # average overall miss latency
1178system.cpu0.icache.blocked_cycles::no_mshrs 10842770 # number of cycles access was blocked
1179system.cpu0.icache.blocked_cycles::no_targets 750 # number of cycles access was blocked
1180system.cpu0.icache.blocked::no_mshrs 802318 # number of cycles access was blocked
1181system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked
1182system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.514305 # average number of cycles each access was blocked
1183system.cpu0.icache.avg_blocked_cycles::no_targets 75 # average number of cycles each access was blocked
1184system.cpu0.icache.fast_writes 0 # number of fast writes performed
1185system.cpu0.icache.cache_copies 0 # number of cache copies performed
1186system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 379817 # number of ReadReq MSHR hits
1187system.cpu0.icache.ReadReq_mshr_hits::total 379817 # number of ReadReq MSHR hits
1188system.cpu0.icache.demand_mshr_hits::cpu0.inst 379817 # number of demand (read+write) MSHR hits
1189system.cpu0.icache.demand_mshr_hits::total 379817 # number of demand (read+write) MSHR hits
1190system.cpu0.icache.overall_mshr_hits::cpu0.inst 379817 # number of overall MSHR hits
1191system.cpu0.icache.overall_mshr_hits::total 379817 # number of overall MSHR hits
1192system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6538699 # number of ReadReq MSHR misses
1193system.cpu0.icache.ReadReq_mshr_misses::total 6538699 # number of ReadReq MSHR misses
1194system.cpu0.icache.demand_mshr_misses::cpu0.inst 6538699 # number of demand (read+write) MSHR misses
1195system.cpu0.icache.demand_mshr_misses::total 6538699 # number of demand (read+write) MSHR misses
1196system.cpu0.icache.overall_mshr_misses::cpu0.inst 6538699 # number of overall MSHR misses
1197system.cpu0.icache.overall_mshr_misses::total 6538699 # number of overall MSHR misses
1198system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable
1199system.cpu0.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable
1200system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses
1201system.cpu0.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses
1202system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 66562536735 # number of ReadReq MSHR miss cycles
1203system.cpu0.icache.ReadReq_mshr_miss_latency::total 66562536735 # number of ReadReq MSHR miss cycles
1204system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 66562536735 # number of demand (read+write) MSHR miss cycles
1205system.cpu0.icache.demand_mshr_miss_latency::total 66562536735 # number of demand (read+write) MSHR miss cycles
1206system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 66562536735 # number of overall MSHR miss cycles
1207system.cpu0.icache.overall_mshr_miss_latency::total 66562536735 # number of overall MSHR miss cycles
1208system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1863746498 # number of ReadReq MSHR uncacheable cycles
1209system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1863746498 # number of ReadReq MSHR uncacheable cycles
1210system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1863746498 # number of overall MSHR uncacheable cycles
1211system.cpu0.icache.overall_mshr_uncacheable_latency::total 1863746498 # number of overall MSHR uncacheable cycles
1212system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028270 # mshr miss rate for ReadReq accesses
1213system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028270 # mshr miss rate for ReadReq accesses
1214system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028270 # mshr miss rate for demand accesses
1215system.cpu0.icache.demand_mshr_miss_rate::total 0.028270 # mshr miss rate for demand accesses
1216system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028270 # mshr miss rate for overall accesses
1217system.cpu0.icache.overall_mshr_miss_rate::total 0.028270 # mshr miss rate for overall accesses
1218system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10179.782971 # average ReadReq mshr miss latency
1219system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10179.782971 # average ReadReq mshr miss latency
1220system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10179.782971 # average overall mshr miss latency
1221system.cpu0.icache.demand_avg_mshr_miss_latency::total 10179.782971 # average overall mshr miss latency
1222system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10179.782971 # average overall mshr miss latency
1223system.cpu0.icache.overall_avg_mshr_miss_latency::total 10179.782971 # average overall mshr miss latency
1224system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373 # average ReadReq mshr uncacheable latency
1225system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 87524.490373 # average ReadReq mshr uncacheable latency
1226system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87524.490373 # average overall mshr uncacheable latency
1227system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 87524.490373 # average overall mshr uncacheable latency
1228system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1229system.cpu0.l2cache.prefetcher.num_hwpf_issued 8420678 # number of hwpf issued
1230system.cpu0.l2cache.prefetcher.pfIdentified 8427841 # number of prefetch candidates identified
1231system.cpu0.l2cache.prefetcher.pfBufferHit 6477 # number of redundant prefetches already in prefetch queue
1232system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1233system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1234system.cpu0.l2cache.prefetcher.pfSpanPage 1085415 # number of prefetches not generated due to page crossing
1235system.cpu0.l2cache.tags.replacements 2879166 # number of replacements
1236system.cpu0.l2cache.tags.tagsinuse 16210.435264 # Cycle average of tags in use
1237system.cpu0.l2cache.tags.total_refs 21867253 # Total number of references to valid blocks.
1238system.cpu0.l2cache.tags.sampled_refs 2894850 # Sample count of references to valid blocks.
1239system.cpu0.l2cache.tags.avg_refs 7.553847 # Average number of references to valid blocks.
1240system.cpu0.l2cache.tags.warmup_cycle 16000650500 # Cycle when the warmup percentage was hit.
1241system.cpu0.l2cache.tags.occ_blocks::writebacks 7399.715112 # Average occupied blocks per requestor
1242system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 85.098490 # Average occupied blocks per requestor
1243system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 94.687899 # Average occupied blocks per requestor
1244system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4348.179928 # Average occupied blocks per requestor
1245system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3389.288950 # Average occupied blocks per requestor
1246system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 893.464886 # Average occupied blocks per requestor
1247system.cpu0.l2cache.tags.occ_percent::writebacks 0.451643 # Average percentage of cache occupancy
1248system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.005194 # Average percentage of cache occupancy
1249system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005779 # Average percentage of cache occupancy
1250system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.265392 # Average percentage of cache occupancy
1251system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.206866 # Average percentage of cache occupancy
1252system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.054533 # Average percentage of cache occupancy
1253system.cpu0.l2cache.tags.occ_percent::total 0.989406 # Average percentage of cache occupancy
1254system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1404 # Occupied blocks per task id
1255system.cpu0.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id
1256system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14188 # Occupied blocks per task id
1257system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 100 # Occupied blocks per task id
1258system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 251 # Occupied blocks per task id
1259system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 619 # Occupied blocks per task id
1260system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 434 # Occupied blocks per task id
1261system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id
1262system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 68 # Occupied blocks per task id
1263system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
1264system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id
1265system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 213 # Occupied blocks per task id
1266system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 757 # Occupied blocks per task id
1267system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4744 # Occupied blocks per task id
1268system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4803 # Occupied blocks per task id
1269system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3671 # Occupied blocks per task id
1270system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.085693 # Percentage of cache occupancy per task id
1271system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id
1272system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.865967 # Percentage of cache occupancy per task id
1273system.cpu0.l2cache.tags.tag_accesses 440722520 # Number of tag accesses
1274system.cpu0.l2cache.tags.data_accesses 440722520 # Number of data accesses
1275system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 580486 # number of ReadReq hits
1276system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 180915 # number of ReadReq hits
1277system.cpu0.l2cache.ReadReq_hits::total 761401 # number of ReadReq hits
1278system.cpu0.l2cache.Writeback_hits::writebacks 4317669 # number of Writeback hits
1279system.cpu0.l2cache.Writeback_hits::total 4317669 # number of Writeback hits
1280system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 115526 # number of UpgradeReq hits
1281system.cpu0.l2cache.UpgradeReq_hits::total 115526 # number of UpgradeReq hits
1282system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 36643 # number of SCUpgradeReq hits
1283system.cpu0.l2cache.SCUpgradeReq_hits::total 36643 # number of SCUpgradeReq hits
1284system.cpu0.l2cache.ReadExReq_hits::cpu0.data 998559 # number of ReadExReq hits
1285system.cpu0.l2cache.ReadExReq_hits::total 998559 # number of ReadExReq hits
1286system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5850201 # number of ReadCleanReq hits
1287system.cpu0.l2cache.ReadCleanReq_hits::total 5850201 # number of ReadCleanReq hits
1288system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3218899 # number of ReadSharedReq hits
1289system.cpu0.l2cache.ReadSharedReq_hits::total 3218899 # number of ReadSharedReq hits
1290system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 227084 # number of InvalidateReq hits
1291system.cpu0.l2cache.InvalidateReq_hits::total 227084 # number of InvalidateReq hits
1292system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 580486 # number of demand (read+write) hits
1293system.cpu0.l2cache.demand_hits::cpu0.itb.walker 180915 # number of demand (read+write) hits
1294system.cpu0.l2cache.demand_hits::cpu0.inst 5850201 # number of demand (read+write) hits
1295system.cpu0.l2cache.demand_hits::cpu0.data 4217458 # number of demand (read+write) hits
1296system.cpu0.l2cache.demand_hits::total 10829060 # number of demand (read+write) hits
1297system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 580486 # number of overall hits
1298system.cpu0.l2cache.overall_hits::cpu0.itb.walker 180915 # number of overall hits
1299system.cpu0.l2cache.overall_hits::cpu0.inst 5850201 # number of overall hits
1300system.cpu0.l2cache.overall_hits::cpu0.data 4217458 # number of overall hits
1301system.cpu0.l2cache.overall_hits::total 10829060 # number of overall hits
1302system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13187 # number of ReadReq misses
1303system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9856 # number of ReadReq misses
1304system.cpu0.l2cache.ReadReq_misses::total 23043 # number of ReadReq misses
1305system.cpu0.l2cache.Writeback_misses::writebacks 5 # number of Writeback misses
1306system.cpu0.l2cache.Writeback_misses::total 5 # number of Writeback misses
1307system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 140809 # number of UpgradeReq misses
1308system.cpu0.l2cache.UpgradeReq_misses::total 140809 # number of UpgradeReq misses
1309system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 171530 # number of SCUpgradeReq misses
1310system.cpu0.l2cache.SCUpgradeReq_misses::total 171530 # number of SCUpgradeReq misses
1311system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses
1312system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses
1313system.cpu0.l2cache.ReadExReq_misses::cpu0.data 296756 # number of ReadExReq misses
1314system.cpu0.l2cache.ReadExReq_misses::total 296756 # number of ReadExReq misses
1315system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 688482 # number of ReadCleanReq misses
1316system.cpu0.l2cache.ReadCleanReq_misses::total 688482 # number of ReadCleanReq misses
1317system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1127441 # number of ReadSharedReq misses
1318system.cpu0.l2cache.ReadSharedReq_misses::total 1127441 # number of ReadSharedReq misses
1319system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 611195 # number of InvalidateReq misses
1320system.cpu0.l2cache.InvalidateReq_misses::total 611195 # number of InvalidateReq misses
1321system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13187 # number of demand (read+write) misses
1322system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9856 # number of demand (read+write) misses
1323system.cpu0.l2cache.demand_misses::cpu0.inst 688482 # number of demand (read+write) misses
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1326system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 13187 # number of overall misses
1327system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9856 # number of overall misses
1328system.cpu0.l2cache.overall_misses::cpu0.inst 688482 # number of overall misses
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1330system.cpu0.l2cache.overall_misses::total 2135722 # number of overall misses
1331system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 534558500 # number of ReadReq miss cycles
1332system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 449764500 # number of ReadReq miss cycles
1333system.cpu0.l2cache.ReadReq_miss_latency::total 984323000 # number of ReadReq miss cycles
1334system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3072018500 # number of UpgradeReq miss cycles
1335system.cpu0.l2cache.UpgradeReq_miss_latency::total 3072018500 # number of UpgradeReq miss cycles
1336system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3550746499 # number of SCUpgradeReq miss cycles
1337system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3550746499 # number of SCUpgradeReq miss cycles
1338system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2885498 # number of SCUpgradeFailReq miss cycles
1339system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2885498 # number of SCUpgradeFailReq miss cycles
1340system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16106273500 # number of ReadExReq miss cycles
1341system.cpu0.l2cache.ReadExReq_miss_latency::total 16106273500 # number of ReadExReq miss cycles
1342system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 21873259998 # number of ReadCleanReq miss cycles
1343system.cpu0.l2cache.ReadCleanReq_miss_latency::total 21873259998 # number of ReadCleanReq miss cycles
1344system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 41772472980 # number of ReadSharedReq miss cycles
1345system.cpu0.l2cache.ReadSharedReq_miss_latency::total 41772472980 # number of ReadSharedReq miss cycles
1346system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 70023878999 # number of InvalidateReq miss cycles
1347system.cpu0.l2cache.InvalidateReq_miss_latency::total 70023878999 # number of InvalidateReq miss cycles
1348system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 534558500 # number of demand (read+write) miss cycles
1349system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 449764500 # number of demand (read+write) miss cycles
1350system.cpu0.l2cache.demand_miss_latency::cpu0.inst 21873259998 # number of demand (read+write) miss cycles
1351system.cpu0.l2cache.demand_miss_latency::cpu0.data 57878746480 # number of demand (read+write) miss cycles
1352system.cpu0.l2cache.demand_miss_latency::total 80736329478 # number of demand (read+write) miss cycles
1353system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 534558500 # number of overall miss cycles
1354system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 449764500 # number of overall miss cycles
1355system.cpu0.l2cache.overall_miss_latency::cpu0.inst 21873259998 # number of overall miss cycles
1356system.cpu0.l2cache.overall_miss_latency::cpu0.data 57878746480 # number of overall miss cycles
1357system.cpu0.l2cache.overall_miss_latency::total 80736329478 # number of overall miss cycles
1358system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 593673 # number of ReadReq accesses(hits+misses)
1359system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 190771 # number of ReadReq accesses(hits+misses)
1360system.cpu0.l2cache.ReadReq_accesses::total 784444 # number of ReadReq accesses(hits+misses)
1361system.cpu0.l2cache.Writeback_accesses::writebacks 4317674 # number of Writeback accesses(hits+misses)
1362system.cpu0.l2cache.Writeback_accesses::total 4317674 # number of Writeback accesses(hits+misses)
1363system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 256335 # number of UpgradeReq accesses(hits+misses)
1364system.cpu0.l2cache.UpgradeReq_accesses::total 256335 # number of UpgradeReq accesses(hits+misses)
1365system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 208173 # number of SCUpgradeReq accesses(hits+misses)
1366system.cpu0.l2cache.SCUpgradeReq_accesses::total 208173 # number of SCUpgradeReq accesses(hits+misses)
1367system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses)
1368system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses)
1369system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1295315 # number of ReadExReq accesses(hits+misses)
1370system.cpu0.l2cache.ReadExReq_accesses::total 1295315 # number of ReadExReq accesses(hits+misses)
1371system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6538683 # number of ReadCleanReq accesses(hits+misses)
1372system.cpu0.l2cache.ReadCleanReq_accesses::total 6538683 # number of ReadCleanReq accesses(hits+misses)
1373system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4346340 # number of ReadSharedReq accesses(hits+misses)
1374system.cpu0.l2cache.ReadSharedReq_accesses::total 4346340 # number of ReadSharedReq accesses(hits+misses)
1375system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 838279 # number of InvalidateReq accesses(hits+misses)
1376system.cpu0.l2cache.InvalidateReq_accesses::total 838279 # number of InvalidateReq accesses(hits+misses)
1377system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 593673 # number of demand (read+write) accesses
1378system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 190771 # number of demand (read+write) accesses
1379system.cpu0.l2cache.demand_accesses::cpu0.inst 6538683 # number of demand (read+write) accesses
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1382system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 593673 # number of overall (read+write) accesses
1383system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 190771 # number of overall (read+write) accesses
1384system.cpu0.l2cache.overall_accesses::cpu0.inst 6538683 # number of overall (read+write) accesses
1385system.cpu0.l2cache.overall_accesses::cpu0.data 5641655 # number of overall (read+write) accesses
1386system.cpu0.l2cache.overall_accesses::total 12964782 # number of overall (read+write) accesses
1387system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.022213 # miss rate for ReadReq accesses
1388system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.051664 # miss rate for ReadReq accesses
1389system.cpu0.l2cache.ReadReq_miss_rate::total 0.029375 # miss rate for ReadReq accesses
1390system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000001 # miss rate for Writeback accesses
1391system.cpu0.l2cache.Writeback_miss_rate::total 0.000001 # miss rate for Writeback accesses
1392system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.549316 # miss rate for UpgradeReq accesses
1393system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.549316 # miss rate for UpgradeReq accesses
1394system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.823978 # miss rate for SCUpgradeReq accesses
1395system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.823978 # miss rate for SCUpgradeReq accesses
1396system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1397system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1398system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.229099 # miss rate for ReadExReq accesses
1399system.cpu0.l2cache.ReadExReq_miss_rate::total 0.229099 # miss rate for ReadExReq accesses
1400system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.105294 # miss rate for ReadCleanReq accesses
1401system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.105294 # miss rate for ReadCleanReq accesses
1402system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.259400 # miss rate for ReadSharedReq accesses
1403system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.259400 # miss rate for ReadSharedReq accesses
1404system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.729107 # miss rate for InvalidateReq accesses
1405system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.729107 # miss rate for InvalidateReq accesses
1406system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022213 # miss rate for demand accesses
1407system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.051664 # miss rate for demand accesses
1408system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.105294 # miss rate for demand accesses
1409system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.252443 # miss rate for demand accesses
1410system.cpu0.l2cache.demand_miss_rate::total 0.164733 # miss rate for demand accesses
1411system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022213 # miss rate for overall accesses
1412system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.051664 # miss rate for overall accesses
1413system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.105294 # miss rate for overall accesses
1414system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.252443 # miss rate for overall accesses
1415system.cpu0.l2cache.overall_miss_rate::total 0.164733 # miss rate for overall accesses
1416system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 40536.778646 # average ReadReq miss latency
1417system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 45633.573458 # average ReadReq miss latency
1418system.cpu0.l2cache.ReadReq_avg_miss_latency::total 42716.790348 # average ReadReq miss latency
1419system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21816.918663 # average UpgradeReq miss latency
1420system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21816.918663 # average UpgradeReq miss latency
1421system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20700.440150 # average SCUpgradeReq miss latency
1422system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20700.440150 # average SCUpgradeReq miss latency
1423system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 360687.250000 # average SCUpgradeFailReq miss latency
1424system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 360687.250000 # average SCUpgradeFailReq miss latency
1425system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 54274.466228 # average ReadExReq miss latency
1426system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 54274.466228 # average ReadExReq miss latency
1427system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 31770.271406 # average ReadCleanReq miss latency
1428system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 31770.271406 # average ReadCleanReq miss latency
1429system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37050.695318 # average ReadSharedReq miss latency
1430system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37050.695318 # average ReadSharedReq miss latency
1431system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 114568.802099 # average InvalidateReq miss latency
1432system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 114568.802099 # average InvalidateReq miss latency
1433system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 40536.778646 # average overall miss latency
1434system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 45633.573458 # average overall miss latency
1435system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31770.271406 # average overall miss latency
1436system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 40639.564948 # average overall miss latency
1437system.cpu0.l2cache.demand_avg_miss_latency::total 37802.827090 # average overall miss latency
1438system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 40536.778646 # average overall miss latency
1439system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 45633.573458 # average overall miss latency
1440system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31770.271406 # average overall miss latency
1441system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 40639.564948 # average overall miss latency
1442system.cpu0.l2cache.overall_avg_miss_latency::total 37802.827090 # average overall miss latency
1443system.cpu0.l2cache.blocked_cycles::no_mshrs 1651 # number of cycles access was blocked
1444system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1445system.cpu0.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked
1446system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1447system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 275.166667 # average number of cycles each access was blocked
1448system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1449system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1450system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1451system.cpu0.l2cache.writebacks::writebacks 1533538 # number of writebacks
1452system.cpu0.l2cache.writebacks::total 1533538 # number of writebacks
1453system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 3 # number of ReadReq MSHR hits
1454system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 198 # number of ReadReq MSHR hits
1455system.cpu0.l2cache.ReadReq_mshr_hits::total 201 # number of ReadReq MSHR hits
1456system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 18639 # number of ReadExReq MSHR hits
1457system.cpu0.l2cache.ReadExReq_mshr_hits::total 18639 # number of ReadExReq MSHR hits
1458system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 9 # number of ReadCleanReq MSHR hits
1459system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits
1460system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 6125 # number of ReadSharedReq MSHR hits
1461system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 6125 # number of ReadSharedReq MSHR hits
1462system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 3 # number of demand (read+write) MSHR hits
1463system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 198 # number of demand (read+write) MSHR hits
1464system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits
1465system.cpu0.l2cache.demand_mshr_hits::cpu0.data 24764 # number of demand (read+write) MSHR hits
1466system.cpu0.l2cache.demand_mshr_hits::total 24974 # number of demand (read+write) MSHR hits
1467system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 3 # number of overall MSHR hits
1468system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 198 # number of overall MSHR hits
1469system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits
1470system.cpu0.l2cache.overall_mshr_hits::cpu0.data 24764 # number of overall MSHR hits
1471system.cpu0.l2cache.overall_mshr_hits::total 24974 # number of overall MSHR hits
1472system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 13184 # number of ReadReq MSHR misses
1473system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9658 # number of ReadReq MSHR misses
1474system.cpu0.l2cache.ReadReq_mshr_misses::total 22842 # number of ReadReq MSHR misses
1475system.cpu0.l2cache.Writeback_mshr_misses::writebacks 5 # number of Writeback MSHR misses
1476system.cpu0.l2cache.Writeback_mshr_misses::total 5 # number of Writeback MSHR misses
1477system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 117912 # number of CleanEvict MSHR misses
1478system.cpu0.l2cache.CleanEvict_mshr_misses::total 117912 # number of CleanEvict MSHR misses
1479system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 787872 # number of HardPFReq MSHR misses
1480system.cpu0.l2cache.HardPFReq_mshr_misses::total 787872 # number of HardPFReq MSHR misses
1481system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 140809 # number of UpgradeReq MSHR misses
1482system.cpu0.l2cache.UpgradeReq_mshr_misses::total 140809 # number of UpgradeReq MSHR misses
1483system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 171530 # number of SCUpgradeReq MSHR misses
1484system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 171530 # number of SCUpgradeReq MSHR misses
1485system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses
1486system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses
1487system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 278117 # number of ReadExReq MSHR misses
1488system.cpu0.l2cache.ReadExReq_mshr_misses::total 278117 # number of ReadExReq MSHR misses
1489system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 688473 # number of ReadCleanReq MSHR misses
1490system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 688473 # number of ReadCleanReq MSHR misses
1491system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1121316 # number of ReadSharedReq MSHR misses
1492system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1121316 # number of ReadSharedReq MSHR misses
1493system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 611195 # number of InvalidateReq MSHR misses
1494system.cpu0.l2cache.InvalidateReq_mshr_misses::total 611195 # number of InvalidateReq MSHR misses
1495system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 13184 # number of demand (read+write) MSHR misses
1496system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9658 # number of demand (read+write) MSHR misses
1497system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 688473 # number of demand (read+write) MSHR misses
1498system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1399433 # number of demand (read+write) MSHR misses
1499system.cpu0.l2cache.demand_mshr_misses::total 2110748 # number of demand (read+write) MSHR misses
1500system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 13184 # number of overall MSHR misses
1501system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9658 # number of overall MSHR misses
1502system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 688473 # number of overall MSHR misses
1503system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1399433 # number of overall MSHR misses
1504system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 787872 # number of overall MSHR misses
1505system.cpu0.l2cache.overall_mshr_misses::total 2898620 # number of overall MSHR misses
1506system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable
1507system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 21352 # number of ReadReq MSHR uncacheable
1508system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 42646 # number of ReadReq MSHR uncacheable
1509system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 23308 # number of WriteReq MSHR uncacheable
1510system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 23308 # number of WriteReq MSHR uncacheable
1511system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses
1512system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 44660 # number of overall MSHR uncacheable misses
1513system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 65954 # number of overall MSHR uncacheable misses
1514system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 455402500 # number of ReadReq MSHR miss cycles
1515system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 383158000 # number of ReadReq MSHR miss cycles
1516system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 838560500 # number of ReadReq MSHR miss cycles
1517system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 47401942947 # number of HardPFReq MSHR miss cycles
1518system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 47401942947 # number of HardPFReq MSHR miss cycles
1519system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2887874997 # number of UpgradeReq MSHR miss cycles
1520system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2887874997 # number of UpgradeReq MSHR miss cycles
1521system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2620767495 # number of SCUpgradeReq MSHR miss cycles
1522system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2620767495 # number of SCUpgradeReq MSHR miss cycles
1523system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2495498 # number of SCUpgradeFailReq MSHR miss cycles
1524system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2495498 # number of SCUpgradeFailReq MSHR miss cycles
1525system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11968940000 # number of ReadExReq MSHR miss cycles
1526system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11968940000 # number of ReadExReq MSHR miss cycles
1527system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 17742237498 # number of ReadCleanReq MSHR miss cycles
1528system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 17742237498 # number of ReadCleanReq MSHR miss cycles
1529system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 34600470980 # number of ReadSharedReq MSHR miss cycles
1530system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 34600470980 # number of ReadSharedReq MSHR miss cycles
1531system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 66356708999 # number of InvalidateReq MSHR miss cycles
1532system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 66356708999 # number of InvalidateReq MSHR miss cycles
1533system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 455402500 # number of demand (read+write) MSHR miss cycles
1534system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 383158000 # number of demand (read+write) MSHR miss cycles
1535system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 17742237498 # number of demand (read+write) MSHR miss cycles
1536system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 46569410980 # number of demand (read+write) MSHR miss cycles
1537system.cpu0.l2cache.demand_mshr_miss_latency::total 65150208978 # number of demand (read+write) MSHR miss cycles
1538system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 455402500 # number of overall MSHR miss cycles
1539system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 383158000 # number of overall MSHR miss cycles
1540system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 17742237498 # number of overall MSHR miss cycles
1541system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 46569410980 # number of overall MSHR miss cycles
1542system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 47401942947 # number of overall MSHR miss cycles
1543system.cpu0.l2cache.overall_mshr_miss_latency::total 112552151925 # number of overall MSHR miss cycles
1544system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1704040500 # number of ReadReq MSHR uncacheable cycles
1545system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3725362000 # number of ReadReq MSHR uncacheable cycles
1546system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5429402500 # number of ReadReq MSHR uncacheable cycles
1547system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3873404967 # number of WriteReq MSHR uncacheable cycles
1548system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3873404967 # number of WriteReq MSHR uncacheable cycles
1549system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1704040500 # number of overall MSHR uncacheable cycles
1550system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7598766967 # number of overall MSHR uncacheable cycles
1551system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9302807467 # number of overall MSHR uncacheable cycles
1552system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022208 # mshr miss rate for ReadReq accesses
1553system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.050626 # mshr miss rate for ReadReq accesses
1554system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.029119 # mshr miss rate for ReadReq accesses
1555system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for Writeback accesses
1556system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000001 # mshr miss rate for Writeback accesses
1557system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1558system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1559system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1560system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1561system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.549316 # mshr miss rate for UpgradeReq accesses
1562system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.549316 # mshr miss rate for UpgradeReq accesses
1563system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.823978 # mshr miss rate for SCUpgradeReq accesses
1564system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.823978 # mshr miss rate for SCUpgradeReq accesses
1565system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1566system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1567system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.214710 # mshr miss rate for ReadExReq accesses
1568system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.214710 # mshr miss rate for ReadExReq accesses
1569system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.105292 # mshr miss rate for ReadCleanReq accesses
1570system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.105292 # mshr miss rate for ReadCleanReq accesses
1571system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.257991 # mshr miss rate for ReadSharedReq accesses
1572system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.257991 # mshr miss rate for ReadSharedReq accesses
1573system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.729107 # mshr miss rate for InvalidateReq accesses
1574system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.729107 # mshr miss rate for InvalidateReq accesses
1575system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022208 # mshr miss rate for demand accesses
1576system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.050626 # mshr miss rate for demand accesses
1577system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.105292 # mshr miss rate for demand accesses
1578system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.248054 # mshr miss rate for demand accesses
1579system.cpu0.l2cache.demand_mshr_miss_rate::total 0.162806 # mshr miss rate for demand accesses
1580system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022208 # mshr miss rate for overall accesses
1581system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.050626 # mshr miss rate for overall accesses
1582system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.105292 # mshr miss rate for overall accesses
1583system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.248054 # mshr miss rate for overall accesses
1584system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1585system.cpu0.l2cache.overall_mshr_miss_rate::total 0.223576 # mshr miss rate for overall accesses
1586system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34542.058556 # average ReadReq mshr miss latency
1587system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 39672.603023 # average ReadReq mshr miss latency
1588system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 36711.343140 # average ReadReq mshr miss latency
1589system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60164.522850 # average HardPFReq mshr miss latency
1590system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60164.522850 # average HardPFReq mshr miss latency
1591system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20509.164876 # average UpgradeReq mshr miss latency
1592system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20509.164876 # average UpgradeReq mshr miss latency
1593system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15278.770448 # average SCUpgradeReq mshr miss latency
1594system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15278.770448 # average SCUpgradeReq mshr miss latency
1595system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 311937.250000 # average SCUpgradeFailReq mshr miss latency
1596system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 311937.250000 # average SCUpgradeFailReq mshr miss latency
1597system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 43035.628890 # average ReadExReq mshr miss latency
1598system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 43035.628890 # average ReadExReq mshr miss latency
1599system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 25770.418735 # average ReadCleanReq mshr miss latency
1600system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 25770.418735 # average ReadCleanReq mshr miss latency
1601system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 30857.020661 # average ReadSharedReq mshr miss latency
1602system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30857.020661 # average ReadSharedReq mshr miss latency
1603system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 108568.802099 # average InvalidateReq mshr miss latency
1604system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 108568.802099 # average InvalidateReq mshr miss latency
1605system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34542.058556 # average overall mshr miss latency
1606system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 39672.603023 # average overall mshr miss latency
1607system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25770.418735 # average overall mshr miss latency
1608system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33277.342309 # average overall mshr miss latency
1609system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30865.934246 # average overall mshr miss latency
1610system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34542.058556 # average overall mshr miss latency
1611system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 39672.603023 # average overall mshr miss latency
1612system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25770.418735 # average overall mshr miss latency
1613system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33277.342309 # average overall mshr miss latency
1614system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60164.522850 # average overall mshr miss latency
1615system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38829.564388 # average overall mshr miss latency
1616system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505 # average ReadReq mshr uncacheable latency
1617system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174473.679281 # average ReadReq mshr uncacheable latency
1618system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 127313.288468 # average ReadReq mshr uncacheable latency
1619system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 166183.497812 # average WriteReq mshr uncacheable latency
1620system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166183.497812 # average WriteReq mshr uncacheable latency
1621system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80024.443505 # average overall mshr uncacheable latency
1622system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 170147.043596 # average overall mshr uncacheable latency
1623system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 141049.935819 # average overall mshr uncacheable latency
1624system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1625system.cpu0.toL2Bus.trans_dist::ReadReq 984567 # Transaction distribution
1626system.cpu0.toL2Bus.trans_dist::ReadResp 11961948 # Transaction distribution
1627system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
1628system.cpu0.toL2Bus.trans_dist::WriteReq 38204 # Transaction distribution
1629system.cpu0.toL2Bus.trans_dist::WriteResp 23308 # Transaction distribution
1630system.cpu0.toL2Bus.trans_dist::Writeback 8463420 # Transaction distribution
1631system.cpu0.toL2Bus.trans_dist::CleanEvict 11561533 # Transaction distribution
1632system.cpu0.toL2Bus.trans_dist::HardPFReq 1016095 # Transaction distribution
1633system.cpu0.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution
1634system.cpu0.toL2Bus.trans_dist::UpgradeReq 502894 # Transaction distribution
1635system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 380729 # Transaction distribution
1636system.cpu0.toL2Bus.trans_dist::UpgradeResp 540434 # Transaction distribution
1637system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 79 # Transaction distribution
1638system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 136 # Transaction distribution
1639system.cpu0.toL2Bus.trans_dist::ReadExReq 1691199 # Transaction distribution
1640system.cpu0.toL2Bus.trans_dist::ReadExResp 1306018 # Transaction distribution
1641system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6538699 # Transaction distribution
1642system.cpu0.toL2Bus.trans_dist::ReadSharedReq 6804200 # Transaction distribution
1643system.cpu0.toL2Bus.trans_dist::InvalidateReq 945007 # Transaction distribution
1644system.cpu0.toL2Bus.trans_dist::InvalidateResp 838279 # Transaction distribution
1645system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19656927 # Packet count per connected master and slave (bytes)
1646system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20547872 # Packet count per connected master and slave (bytes)
1647system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 414026 # Packet count per connected master and slave (bytes)
1648system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1295337 # Packet count per connected master and slave (bytes)
1649system.cpu0.toL2Bus.pkt_count::total 41914162 # Packet count per connected master and slave (bytes)
1650system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 418816352 # Cumulative packet size per connected master and slave (bytes)
1651system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 645201790 # Cumulative packet size per connected master and slave (bytes)
1652system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1526168 # Cumulative packet size per connected master and slave (bytes)
1653system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4749384 # Cumulative packet size per connected master and slave (bytes)
1654system.cpu0.toL2Bus.pkt_size::total 1070293694 # Cumulative packet size per connected master and slave (bytes)
1655system.cpu0.toL2Bus.snoops 11878703 # Total snoops (count)
1656system.cpu0.toL2Bus.snoop_fanout::samples 38928585 # Request fanout histogram
1657system.cpu0.toL2Bus.snoop_fanout::mean 1.320254 # Request fanout histogram
1658system.cpu0.toL2Bus.snoop_fanout::stdev 0.466574 # Request fanout histogram
1659system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1660system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1661system.cpu0.toL2Bus.snoop_fanout::1 26461563 67.97% 67.97% # Request fanout histogram
1662system.cpu0.toL2Bus.snoop_fanout::2 12467022 32.03% 100.00% # Request fanout histogram
1663system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1664system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
1665system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1666system.cpu0.toL2Bus.snoop_fanout::total 38928585 # Request fanout histogram
1667system.cpu0.toL2Bus.reqLayer0.occupancy 18022605428 # Layer occupancy (ticks)
1668system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1669system.cpu0.toL2Bus.snoopLayer0.occupancy 218178978 # Layer occupancy (ticks)
1670system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1671system.cpu0.toL2Bus.respLayer0.occupancy 9834328997 # Layer occupancy (ticks)
1672system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1673system.cpu0.toL2Bus.respLayer1.occupancy 9151913574 # Layer occupancy (ticks)
1674system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1675system.cpu0.toL2Bus.respLayer2.occupancy 223594319 # Layer occupancy (ticks)
1676system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1677system.cpu0.toL2Bus.respLayer3.occupancy 702320680 # Layer occupancy (ticks)
1678system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1679system.cpu1.branchPred.lookups 127974219 # Number of BP lookups
1680system.cpu1.branchPred.condPredicted 85721226 # Number of conditional branches predicted
1681system.cpu1.branchPred.condIncorrect 6122377 # Number of conditional branches incorrect
1682system.cpu1.branchPred.BTBLookups 91131353 # Number of BTB lookups
1683system.cpu1.branchPred.BTBHits 60172902 # Number of BTB hits
1684system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1685system.cpu1.branchPred.BTBHitPct 66.028760 # BTB Hit Percentage
1686system.cpu1.branchPred.usedRAS 17085083 # Number of times the RAS was used to get a target.
1687system.cpu1.branchPred.RASInCorrect 181731 # Number of incorrect RAS predictions.
1688system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1689system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1690system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1691system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1692system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1693system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1694system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1695system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

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1709system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1710system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1711system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1712system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1713system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1714system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1715system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1716system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1717system.cpu1.dtb.walker.walks 610901 # Table walker walks requested
1718system.cpu1.dtb.walker.walksLong 610901 # Table walker walks initiated with long descriptors
1719system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 15580 # Level at which table walker walks with long descriptors terminate
1720system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 103695 # Level at which table walker walks with long descriptors terminate
1721system.cpu1.dtb.walker.walksSquashedBefore 293448 # Table walks squashed before starting
1722system.cpu1.dtb.walker.walkWaitTime::samples 317453 # Table walker wait (enqueue to first request) latency
1723system.cpu1.dtb.walker.walkWaitTime::mean 2113.928676 # Table walker wait (enqueue to first request) latency
1724system.cpu1.dtb.walker.walkWaitTime::stdev 12461.929670 # Table walker wait (enqueue to first request) latency
1725system.cpu1.dtb.walker.walkWaitTime::0-32767 312797 98.53% 98.53% # Table walker wait (enqueue to first request) latency
1726system.cpu1.dtb.walker.walkWaitTime::32768-65535 2424 0.76% 99.30% # Table walker wait (enqueue to first request) latency
1727system.cpu1.dtb.walker.walkWaitTime::65536-98303 700 0.22% 99.52% # Table walker wait (enqueue to first request) latency
1728system.cpu1.dtb.walker.walkWaitTime::98304-131071 857 0.27% 99.79% # Table walker wait (enqueue to first request) latency
1729system.cpu1.dtb.walker.walkWaitTime::131072-163839 351 0.11% 99.90% # Table walker wait (enqueue to first request) latency
1730system.cpu1.dtb.walker.walkWaitTime::163840-196607 153 0.05% 99.95% # Table walker wait (enqueue to first request) latency
1731system.cpu1.dtb.walker.walkWaitTime::196608-229375 53 0.02% 99.96% # Table walker wait (enqueue to first request) latency
1732system.cpu1.dtb.walker.walkWaitTime::229376-262143 19 0.01% 99.97% # Table walker wait (enqueue to first request) latency
1733system.cpu1.dtb.walker.walkWaitTime::262144-294911 21 0.01% 99.98% # Table walker wait (enqueue to first request) latency
1734system.cpu1.dtb.walker.walkWaitTime::294912-327679 57 0.02% 99.99% # Table walker wait (enqueue to first request) latency
1735system.cpu1.dtb.walker.walkWaitTime::327680-360447 14 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1736system.cpu1.dtb.walker.walkWaitTime::360448-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1737system.cpu1.dtb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1738system.cpu1.dtb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1739system.cpu1.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1740system.cpu1.dtb.walker.walkWaitTime::total 317453 # Table walker wait (enqueue to first request) latency
1741system.cpu1.dtb.walker.walkCompletionTime::samples 338102 # Table walker service (enqueue to completion) latency
1742system.cpu1.dtb.walker.walkCompletionTime::mean 18568.539967 # Table walker service (enqueue to completion) latency
1743system.cpu1.dtb.walker.walkCompletionTime::gmean 16066.889111 # Table walker service (enqueue to completion) latency
1744system.cpu1.dtb.walker.walkCompletionTime::stdev 14911.003076 # Table walker service (enqueue to completion) latency
1745system.cpu1.dtb.walker.walkCompletionTime::0-65535 335377 99.19% 99.19% # Table walker service (enqueue to completion) latency
1746system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1909 0.56% 99.76% # Table walker service (enqueue to completion) latency
1747system.cpu1.dtb.walker.walkCompletionTime::131072-196607 302 0.09% 99.85% # Table walker service (enqueue to completion) latency
1748system.cpu1.dtb.walker.walkCompletionTime::196608-262143 312 0.09% 99.94% # Table walker service (enqueue to completion) latency
1749system.cpu1.dtb.walker.walkCompletionTime::262144-327679 121 0.04% 99.98% # Table walker service (enqueue to completion) latency
1750system.cpu1.dtb.walker.walkCompletionTime::327680-393215 38 0.01% 99.99% # Table walker service (enqueue to completion) latency
1751system.cpu1.dtb.walker.walkCompletionTime::393216-458751 24 0.01% 99.99% # Table walker service (enqueue to completion) latency
1752system.cpu1.dtb.walker.walkCompletionTime::458752-524287 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
1753system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
1754system.cpu1.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
1755system.cpu1.dtb.walker.walkCompletionTime::total 338102 # Table walker service (enqueue to completion) latency
1756system.cpu1.dtb.walker.walksPending::samples 438848021252 # Table walker pending requests distribution
1757system.cpu1.dtb.walker.walksPending::mean 0.580073 # Table walker pending requests distribution
1758system.cpu1.dtb.walker.walksPending::stdev 0.553130 # Table walker pending requests distribution
1759system.cpu1.dtb.walker.walksPending::0-1 437543459752 99.70% 99.70% # Table walker pending requests distribution
1760system.cpu1.dtb.walker.walksPending::2-3 782991500 0.18% 99.88% # Table walker pending requests distribution
1761system.cpu1.dtb.walker.walksPending::4-5 243923500 0.06% 99.94% # Table walker pending requests distribution
1762system.cpu1.dtb.walker.walksPending::6-7 110155500 0.03% 99.96% # Table walker pending requests distribution
1763system.cpu1.dtb.walker.walksPending::8-9 88476500 0.02% 99.98% # Table walker pending requests distribution
1764system.cpu1.dtb.walker.walksPending::10-11 41634500 0.01% 99.99% # Table walker pending requests distribution
1765system.cpu1.dtb.walker.walksPending::12-13 16681500 0.00% 100.00% # Table walker pending requests distribution
1766system.cpu1.dtb.walker.walksPending::14-15 20049000 0.00% 100.00% # Table walker pending requests distribution
1767system.cpu1.dtb.walker.walksPending::16-17 649500 0.00% 100.00% # Table walker pending requests distribution
1768system.cpu1.dtb.walker.walksPending::total 438848021252 # Table walker pending requests distribution
1769system.cpu1.dtb.walker.walkPageSizes::4K 103695 86.94% 86.94% # Table walker page sizes translated
1770system.cpu1.dtb.walker.walkPageSizes::2M 15580 13.06% 100.00% # Table walker page sizes translated
1771system.cpu1.dtb.walker.walkPageSizes::total 119275 # Table walker page sizes translated
1772system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 610901 # Table walker requests started/completed, data/inst
1773system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1774system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 610901 # Table walker requests started/completed, data/inst
1775system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 119275 # Table walker requests started/completed, data/inst
1776system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1777system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 119275 # Table walker requests started/completed, data/inst
1778system.cpu1.dtb.walker.walkRequestOrigin::total 730176 # Table walker requests started/completed, data/inst
1779system.cpu1.dtb.inst_hits 0 # ITB inst hits
1780system.cpu1.dtb.inst_misses 0 # ITB inst misses
1781system.cpu1.dtb.read_hits 94901630 # DTB read hits
1782system.cpu1.dtb.read_misses 438242 # DTB read misses
1783system.cpu1.dtb.write_hits 77470080 # DTB write hits
1784system.cpu1.dtb.write_misses 172659 # DTB write misses
1785system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed
1786system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1787system.cpu1.dtb.flush_tlb_mva_asid 46383 # Number of times TLB was flushed by MVA & ASID
1788system.cpu1.dtb.flush_tlb_asid 1087 # Number of times TLB was flushed by ASID
1789system.cpu1.dtb.flush_entries 42323 # Number of entries that have been flushed from TLB
1790system.cpu1.dtb.align_faults 163 # Number of TLB faults due to alignment restrictions
1791system.cpu1.dtb.prefetch_faults 7630 # Number of TLB faults due to prefetch
1792system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1793system.cpu1.dtb.perms_faults 42941 # Number of TLB faults due to permissions restrictions
1794system.cpu1.dtb.read_accesses 95339872 # DTB read accesses
1795system.cpu1.dtb.write_accesses 77642739 # DTB write accesses
1796system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1797system.cpu1.dtb.hits 172371710 # DTB hits
1798system.cpu1.dtb.misses 610901 # DTB misses
1799system.cpu1.dtb.accesses 172982611 # DTB accesses
1800system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1801system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1802system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1803system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1804system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1805system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1806system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1807system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1821system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1822system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1823system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1824system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1825system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1826system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1827system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1828system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1829system.cpu1.itb.walker.walks 86285 # Table walker walks requested
1830system.cpu1.itb.walker.walksLong 86285 # Table walker walks initiated with long descriptors
1831system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1166 # Level at which table walker walks with long descriptors terminate
1832system.cpu1.itb.walker.walksLongTerminationLevel::Level3 62692 # Level at which table walker walks with long descriptors terminate
1833system.cpu1.itb.walker.walksSquashedBefore 9855 # Table walks squashed before starting
1834system.cpu1.itb.walker.walkWaitTime::samples 76430 # Table walker wait (enqueue to first request) latency
1835system.cpu1.itb.walker.walkWaitTime::mean 1337.426403 # Table walker wait (enqueue to first request) latency
1836system.cpu1.itb.walker.walkWaitTime::stdev 10105.936208 # Table walker wait (enqueue to first request) latency
1837system.cpu1.itb.walker.walkWaitTime::0-32767 75617 98.94% 98.94% # Table walker wait (enqueue to first request) latency
1838system.cpu1.itb.walker.walkWaitTime::32768-65535 383 0.50% 99.44% # Table walker wait (enqueue to first request) latency
1839system.cpu1.itb.walker.walkWaitTime::65536-98303 204 0.27% 99.70% # Table walker wait (enqueue to first request) latency
1840system.cpu1.itb.walker.walkWaitTime::98304-131071 174 0.23% 99.93% # Table walker wait (enqueue to first request) latency
1841system.cpu1.itb.walker.walkWaitTime::131072-163839 8 0.01% 99.94% # Table walker wait (enqueue to first request) latency
1842system.cpu1.itb.walker.walkWaitTime::163840-196607 13 0.02% 99.96% # Table walker wait (enqueue to first request) latency
1843system.cpu1.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.97% # Table walker wait (enqueue to first request) latency
1844system.cpu1.itb.walker.walkWaitTime::229376-262143 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency
1845system.cpu1.itb.walker.walkWaitTime::262144-294911 1 0.00% 99.98% # Table walker wait (enqueue to first request) latency
1846system.cpu1.itb.walker.walkWaitTime::294912-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
1847system.cpu1.itb.walker.walkWaitTime::327680-360447 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency
1848system.cpu1.itb.walker.walkWaitTime::360448-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1849system.cpu1.itb.walker.walkWaitTime::total 76430 # Table walker wait (enqueue to first request) latency
1850system.cpu1.itb.walker.walkCompletionTime::samples 73713 # Table walker service (enqueue to completion) latency
1851system.cpu1.itb.walker.walkCompletionTime::mean 23336.867310 # Table walker service (enqueue to completion) latency
1852system.cpu1.itb.walker.walkCompletionTime::gmean 20402.005732 # Table walker service (enqueue to completion) latency
1853system.cpu1.itb.walker.walkCompletionTime::stdev 19525.264050 # Table walker service (enqueue to completion) latency
1854system.cpu1.itb.walker.walkCompletionTime::0-65535 72001 97.68% 97.68% # Table walker service (enqueue to completion) latency
1855system.cpu1.itb.walker.walkCompletionTime::65536-131071 1393 1.89% 99.57% # Table walker service (enqueue to completion) latency
1856system.cpu1.itb.walker.walkCompletionTime::131072-196607 144 0.20% 99.76% # Table walker service (enqueue to completion) latency
1857system.cpu1.itb.walker.walkCompletionTime::196608-262143 112 0.15% 99.91% # Table walker service (enqueue to completion) latency
1858system.cpu1.itb.walker.walkCompletionTime::262144-327679 36 0.05% 99.96% # Table walker service (enqueue to completion) latency
1859system.cpu1.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.99% # Table walker service (enqueue to completion) latency
1860system.cpu1.itb.walker.walkCompletionTime::393216-458751 7 0.01% 100.00% # Table walker service (enqueue to completion) latency
1861system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1862system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1863system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
1864system.cpu1.itb.walker.walkCompletionTime::total 73713 # Table walker service (enqueue to completion) latency
1865system.cpu1.itb.walker.walksPending::samples 417370190772 # Table walker pending requests distribution
1866system.cpu1.itb.walker.walksPending::mean 0.853526 # Table walker pending requests distribution
1867system.cpu1.itb.walker.walksPending::stdev 0.353735 # Table walker pending requests distribution
1868system.cpu1.itb.walker.walksPending::0 61155433348 14.65% 14.65% # Table walker pending requests distribution
1869system.cpu1.itb.walker.walksPending::1 356194673424 85.34% 100.00% # Table walker pending requests distribution
1870system.cpu1.itb.walker.walksPending::2 18786000 0.00% 100.00% # Table walker pending requests distribution
1871system.cpu1.itb.walker.walksPending::3 1262500 0.00% 100.00% # Table walker pending requests distribution
1872system.cpu1.itb.walker.walksPending::4 35500 0.00% 100.00% # Table walker pending requests distribution
1873system.cpu1.itb.walker.walksPending::total 417370190772 # Table walker pending requests distribution
1874system.cpu1.itb.walker.walkPageSizes::4K 62692 98.17% 98.17% # Table walker page sizes translated
1875system.cpu1.itb.walker.walkPageSizes::2M 1166 1.83% 100.00% # Table walker page sizes translated
1876system.cpu1.itb.walker.walkPageSizes::total 63858 # Table walker page sizes translated
1877system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1878system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 86285 # Table walker requests started/completed, data/inst
1879system.cpu1.itb.walker.walkRequestOrigin_Requested::total 86285 # Table walker requests started/completed, data/inst
1880system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1881system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63858 # Table walker requests started/completed, data/inst
1882system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63858 # Table walker requests started/completed, data/inst
1883system.cpu1.itb.walker.walkRequestOrigin::total 150143 # Table walker requests started/completed, data/inst
1884system.cpu1.itb.inst_hits 203133106 # ITB inst hits
1885system.cpu1.itb.inst_misses 86285 # ITB inst misses
1886system.cpu1.itb.read_hits 0 # DTB read hits
1887system.cpu1.itb.read_misses 0 # DTB read misses
1888system.cpu1.itb.write_hits 0 # DTB write hits
1889system.cpu1.itb.write_misses 0 # DTB write misses
1890system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed
1891system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1892system.cpu1.itb.flush_tlb_mva_asid 46383 # Number of times TLB was flushed by MVA & ASID
1893system.cpu1.itb.flush_tlb_asid 1087 # Number of times TLB was flushed by ASID
1894system.cpu1.itb.flush_entries 30560 # Number of entries that have been flushed from TLB
1895system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1896system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1897system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1898system.cpu1.itb.perms_faults 224551 # Number of TLB faults due to permissions restrictions
1899system.cpu1.itb.read_accesses 0 # DTB read accesses
1900system.cpu1.itb.write_accesses 0 # DTB write accesses
1901system.cpu1.itb.inst_accesses 203219391 # ITB inst accesses
1902system.cpu1.itb.hits 203133106 # DTB hits
1903system.cpu1.itb.misses 86285 # DTB misses
1904system.cpu1.itb.accesses 203219391 # DTB accesses
1905system.cpu1.numCycles 708901373 # number of cpu cycles simulated
1906system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1907system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1908system.cpu1.fetch.icacheStallCycles 79210227 # Number of cycles fetch is stalled on an Icache miss
1909system.cpu1.fetch.Insts 569056404 # Number of instructions fetch has processed
1910system.cpu1.fetch.Branches 127974219 # Number of branches that fetch encountered
1911system.cpu1.fetch.predictedBranches 77257985 # Number of branches that fetch has predicted taken
1912system.cpu1.fetch.Cycles 596249525 # Number of cycles fetch has run and was not squashing or blocked
1913system.cpu1.fetch.SquashCycles 13297978 # Number of cycles fetch has spent squashing
1914system.cpu1.fetch.TlbCycles 1936888 # Number of cycles fetch has spent waiting for tlb
1915system.cpu1.fetch.MiscStallCycles 233747 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1916system.cpu1.fetch.PendingTrapStallCycles 6483042 # Number of stall cycles due to pending traps
1917system.cpu1.fetch.PendingQuiesceStallCycles 760521 # Number of stall cycles due to pending quiesce instructions
1918system.cpu1.fetch.IcacheWaitRetryStallCycles 721953 # Number of stall cycles due to full MSHR
1919system.cpu1.fetch.CacheLines 202886748 # Number of cache lines fetched
1920system.cpu1.fetch.IcacheSquashes 1527721 # Number of outstanding Icache misses that were squashed
1921system.cpu1.fetch.ItlbSquashes 28660 # Number of outstanding ITLB misses that were squashed
1922system.cpu1.fetch.rateDist::samples 692244892 # Number of instructions fetched each cycle (Total)
1923system.cpu1.fetch.rateDist::mean 0.964370 # Number of instructions fetched each cycle (Total)
1924system.cpu1.fetch.rateDist::stdev 1.215604 # Number of instructions fetched each cycle (Total)
1925system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1926system.cpu1.fetch.rateDist::0 371999522 53.74% 53.74% # Number of instructions fetched each cycle (Total)
1927system.cpu1.fetch.rateDist::1 125145403 18.08% 71.82% # Number of instructions fetched each cycle (Total)
1928system.cpu1.fetch.rateDist::2 42864856 6.19% 78.01% # Number of instructions fetched each cycle (Total)
1929system.cpu1.fetch.rateDist::3 152235111 21.99% 100.00% # Number of instructions fetched each cycle (Total)
1930system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1931system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1932system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
1933system.cpu1.fetch.rateDist::total 692244892 # Number of instructions fetched each cycle (Total)
1934system.cpu1.fetch.branchRate 0.180525 # Number of branch fetches per cycle
1935system.cpu1.fetch.rate 0.802730 # Number of inst fetches per cycle
1936system.cpu1.decode.IdleCycles 98103528 # Number of cycles decode is idle
1937system.cpu1.decode.BlockedCycles 343550458 # Number of cycles decode is blocked
1938system.cpu1.decode.RunCycles 207545620 # Number of cycles decode is running
1939system.cpu1.decode.UnblockCycles 38285921 # Number of cycles decode is unblocking
1940system.cpu1.decode.SquashCycles 4759365 # Number of cycles decode is squashing
1941system.cpu1.decode.BranchResolved 18045337 # Number of times decode resolved a branch
1942system.cpu1.decode.BranchMispred 1925812 # Number of times decode detected a branch misprediction
1943system.cpu1.decode.DecodedInsts 590182189 # Number of instructions handled by decode
1944system.cpu1.decode.SquashedInsts 20993149 # Number of squashed instructions handled by decode
1945system.cpu1.rename.SquashCycles 4759365 # Number of cycles rename is squashing
1946system.cpu1.rename.IdleCycles 132299037 # Number of cycles rename is idle
1947system.cpu1.rename.BlockCycles 44198902 # Number of cycles rename is blocking
1948system.cpu1.rename.serializeStallCycles 235238981 # count of cycles rename stalled for serializing inst
1949system.cpu1.rename.RunCycles 211136719 # Number of cycles rename is running
1950system.cpu1.rename.UnblockCycles 64611888 # Number of cycles rename is unblocking
1951system.cpu1.rename.RenamedInsts 574391592 # Number of instructions processed by rename
1952system.cpu1.rename.SquashedInsts 5359861 # Number of squashed instructions processed by rename
1953system.cpu1.rename.ROBFullEvents 9789729 # Number of times rename has blocked due to ROB full
1954system.cpu1.rename.IQFullEvents 401271 # Number of times rename has blocked due to IQ full
1955system.cpu1.rename.LQFullEvents 868513 # Number of times rename has blocked due to LQ full
1956system.cpu1.rename.SQFullEvents 28581746 # Number of times rename has blocked due to SQ full
1957system.cpu1.rename.FullRegisterEvents 10968 # Number of times there has been no free registers
1958system.cpu1.rename.RenamedOperands 549201958 # Number of destination operands rename has renamed
1959system.cpu1.rename.RenameLookups 896745625 # Number of register rename lookups that rename has made
1960system.cpu1.rename.int_rename_lookups 678703153 # Number of integer rename lookups
1961system.cpu1.rename.fp_rename_lookups 702078 # Number of floating rename lookups
1962system.cpu1.rename.CommittedMaps 496570478 # Number of HB maps that are committed
1963system.cpu1.rename.UndoneMaps 52631474 # Number of HB maps that are undone due to squashing
1964system.cpu1.rename.serializingInsts 16637084 # count of serializing insts renamed
1965system.cpu1.rename.tempSerializingInsts 14688391 # count of temporary serializing insts renamed
1966system.cpu1.rename.skidInsts 76542594 # count of insts added to the skid buffer
1967system.cpu1.memDep0.insertedLoads 94434816 # Number of loads inserted to the mem dependence unit.
1968system.cpu1.memDep0.insertedStores 80595349 # Number of stores inserted to the mem dependence unit.
1969system.cpu1.memDep0.conflictingLoads 8923483 # Number of conflicting loads.
1970system.cpu1.memDep0.conflictingStores 7689116 # Number of conflicting stores.
1971system.cpu1.iq.iqInstsAdded 551758554 # Number of instructions added to the IQ (excludes non-spec)
1972system.cpu1.iq.iqNonSpecInstsAdded 16802636 # Number of non-speculative instructions added to the IQ
1973system.cpu1.iq.iqInstsIssued 558923093 # Number of instructions issued
1974system.cpu1.iq.iqSquashedInstsIssued 2479703 # Number of squashed instructions issued
1975system.cpu1.iq.iqSquashedInstsExamined 49836281 # Number of squashed instructions iterated over during squash; mainly for profiling
1976system.cpu1.iq.iqSquashedOperandsExamined 32327580 # Number of squashed operands that are examined and possibly removed from graph
1977system.cpu1.iq.iqSquashedNonSpecRemoved 272404 # Number of squashed non-spec instructions that were removed
1978system.cpu1.iq.issued_per_cycle::samples 692244892 # Number of insts issued each cycle
1979system.cpu1.iq.issued_per_cycle::mean 0.807407 # Number of insts issued each cycle
1980system.cpu1.iq.issued_per_cycle::stdev 1.056587 # Number of insts issued each cycle
1981system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1982system.cpu1.iq.issued_per_cycle::0 382813800 55.30% 55.30% # Number of insts issued each cycle
1983system.cpu1.iq.issued_per_cycle::1 135617529 19.59% 74.89% # Number of insts issued each cycle
1984system.cpu1.iq.issued_per_cycle::2 105540069 15.25% 90.14% # Number of insts issued each cycle
1985system.cpu1.iq.issued_per_cycle::3 60873310 8.79% 98.93% # Number of insts issued each cycle
1986system.cpu1.iq.issued_per_cycle::4 7395424 1.07% 100.00% # Number of insts issued each cycle
1987system.cpu1.iq.issued_per_cycle::5 4760 0.00% 100.00% # Number of insts issued each cycle
1988system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
1989system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
1990system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
1991system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1992system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1993system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
1994system.cpu1.iq.issued_per_cycle::total 692244892 # Number of insts issued each cycle
1995system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1996system.cpu1.iq.fu_full::IntAlu 54751854 43.35% 43.35% # attempts to use FU when none available
1997system.cpu1.iq.fu_full::IntMult 59874 0.05% 43.40% # attempts to use FU when none available
1998system.cpu1.iq.fu_full::IntDiv 7206 0.01% 43.41% # attempts to use FU when none available
1999system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.41% # attempts to use FU when none available
2000system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.41% # attempts to use FU when none available
2001system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.41% # attempts to use FU when none available
2002system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.41% # attempts to use FU when none available
2003system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.41% # attempts to use FU when none available
2004system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.41% # attempts to use FU when none available
2005system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.41% # attempts to use FU when none available
2006system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.41% # attempts to use FU when none available
2007system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.41% # attempts to use FU when none available
2008system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.41% # attempts to use FU when none available
2009system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.41% # attempts to use FU when none available
2010system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.41% # attempts to use FU when none available
2011system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.41% # attempts to use FU when none available
2012system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.41% # attempts to use FU when none available
2013system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.41% # attempts to use FU when none available
2014system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.41% # attempts to use FU when none available
2015system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.41% # attempts to use FU when none available
2016system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.41% # attempts to use FU when none available
2017system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.41% # attempts to use FU when none available
2018system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.41% # attempts to use FU when none available
2019system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.41% # attempts to use FU when none available
2020system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.41% # attempts to use FU when none available
2021system.cpu1.iq.fu_full::SimdFloatMisc 22 0.00% 43.41% # attempts to use FU when none available
2022system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.41% # attempts to use FU when none available
2023system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.41% # attempts to use FU when none available
2024system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.41% # attempts to use FU when none available
2025system.cpu1.iq.fu_full::MemRead 34635726 27.43% 70.83% # attempts to use FU when none available
2026system.cpu1.iq.fu_full::MemWrite 36835867 29.17% 100.00% # attempts to use FU when none available
2027system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
2028system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
2029system.cpu1.iq.FU_type_0::No_OpClass 22 0.00% 0.00% # Type of FU issued
2030system.cpu1.iq.FU_type_0::IntAlu 381080184 68.18% 68.18% # Type of FU issued
2031system.cpu1.iq.FU_type_0::IntMult 1279374 0.23% 68.41% # Type of FU issued
2032system.cpu1.iq.FU_type_0::IntDiv 67457 0.01% 68.42% # Type of FU issued
2033system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.42% # Type of FU issued
2034system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.42% # Type of FU issued
2035system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.42% # Type of FU issued
2036system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.42% # Type of FU issued
2037system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.42% # Type of FU issued
2038system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.42% # Type of FU issued
2039system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.42% # Type of FU issued
2040system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.42% # Type of FU issued
2041system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.42% # Type of FU issued
2042system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.42% # Type of FU issued
2043system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.42% # Type of FU issued
2044system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.42% # Type of FU issued
2045system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.42% # Type of FU issued
2046system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.42% # Type of FU issued
2047system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.42% # Type of FU issued
2048system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.42% # Type of FU issued
2049system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.42% # Type of FU issued
2050system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.42% # Type of FU issued
2051system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.42% # Type of FU issued
2052system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.42% # Type of FU issued
2053system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.42% # Type of FU issued
2054system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.42% # Type of FU issued
2055system.cpu1.iq.FU_type_0::SimdFloatMisc 77518 0.01% 68.44% # Type of FU issued
2056system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.44% # Type of FU issued
2057system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.44% # Type of FU issued
2058system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.44% # Type of FU issued
2059system.cpu1.iq.FU_type_0::MemRead 97747450 17.49% 85.92% # Type of FU issued
2060system.cpu1.iq.FU_type_0::MemWrite 78671088 14.08% 100.00% # Type of FU issued
2061system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
2062system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2063system.cpu1.iq.FU_type_0::total 558923093 # Type of FU issued
2064system.cpu1.iq.rate 0.788436 # Inst issue rate
2065system.cpu1.iq.fu_busy_cnt 126290549 # FU busy when requested
2066system.cpu1.iq.fu_busy_rate 0.225953 # FU busy rate (busy events/executed inst)
2067system.cpu1.iq.int_inst_queue_reads 1937670345 # Number of integer instruction queue reads
2068system.cpu1.iq.int_inst_queue_writes 618057050 # Number of integer instruction queue writes
2069system.cpu1.iq.int_inst_queue_wakeup_accesses 542680096 # Number of integer instruction queue wakeup accesses
2070system.cpu1.iq.fp_inst_queue_reads 1190983 # Number of floating instruction queue reads
2071system.cpu1.iq.fp_inst_queue_writes 486822 # Number of floating instruction queue writes
2072system.cpu1.iq.fp_inst_queue_wakeup_accesses 443064 # Number of floating instruction queue wakeup accesses
2073system.cpu1.iq.int_alu_accesses 684478646 # Number of integer alu accesses
2074system.cpu1.iq.fp_alu_accesses 734974 # Number of floating point alu accesses
2075system.cpu1.iew.lsq.thread0.forwLoads 2497447 # Number of loads that had data forwarded from stores
2076system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2077system.cpu1.iew.lsq.thread0.squashedLoads 11391566 # Number of loads squashed
2078system.cpu1.iew.lsq.thread0.ignoredResponses 16442 # Number of memory responses ignored because the instruction is squashed
2079system.cpu1.iew.lsq.thread0.memOrderViolation 147287 # Number of memory ordering violations
2080system.cpu1.iew.lsq.thread0.squashedStores 5480411 # Number of stores squashed
2081system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2082system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2083system.cpu1.iew.lsq.thread0.rescheduledLoads 2518337 # Number of loads that were rescheduled
2084system.cpu1.iew.lsq.thread0.cacheBlocked 4561530 # Number of times an access to memory failed due to the cache being blocked
2085system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2086system.cpu1.iew.iewSquashCycles 4759365 # Number of cycles IEW is squashing
2087system.cpu1.iew.iewBlockCycles 7377288 # Number of cycles IEW is blocking
2088system.cpu1.iew.iewUnblockCycles 1779487 # Number of cycles IEW is unblocking
2089system.cpu1.iew.iewDispatchedInsts 568686865 # Number of instructions dispatched to IQ
2090system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2091system.cpu1.iew.iewDispLoadInsts 94434816 # Number of dispatched load instructions
2092system.cpu1.iew.iewDispStoreInsts 80595349 # Number of dispatched store instructions
2093system.cpu1.iew.iewDispNonSpecInsts 14436432 # Number of dispatched non-speculative instructions
2094system.cpu1.iew.iewIQFullEvents 67561 # Number of times the IQ has become full, causing a stall
2095system.cpu1.iew.iewLSQFullEvents 1633321 # Number of times the LSQ has become full, causing a stall
2096system.cpu1.iew.memOrderViolationEvents 147287 # Number of memory order violations
2097system.cpu1.iew.predictedTakenIncorrect 1861843 # Number of branches that were predicted taken incorrectly
2098system.cpu1.iew.predictedNotTakenIncorrect 2641662 # Number of branches that were predicted not taken incorrectly
2099system.cpu1.iew.branchMispredicts 4503505 # Number of branch mispredicts detected at execute
2100system.cpu1.iew.iewExecutedInsts 551808656 # Number of executed instructions
2101system.cpu1.iew.iewExecLoadInsts 94901612 # Number of load instructions executed
2102system.cpu1.iew.iewExecSquashedInsts 6513481 # Number of squashed instructions skipped in execute
2103system.cpu1.iew.exec_swp 0 # number of swp insts executed
2104system.cpu1.iew.exec_nop 125675 # number of nop insts executed
2105system.cpu1.iew.exec_refs 172371354 # number of memory reference insts executed
2106system.cpu1.iew.exec_branches 103407043 # Number of branches executed
2107system.cpu1.iew.exec_stores 77469742 # Number of stores executed
2108system.cpu1.iew.exec_rate 0.778400 # Inst execution rate
2109system.cpu1.iew.wb_sent 543849746 # cumulative count of insts sent to commit
2110system.cpu1.iew.wb_count 543123160 # cumulative count of insts written-back
2111system.cpu1.iew.wb_producers 263131919 # num instructions producing a value
2112system.cpu1.iew.wb_consumers 431737287 # num instructions consuming a value
2113system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
2114system.cpu1.iew.wb_rate 0.766148 # insts written-back per cycle
2115system.cpu1.iew.wb_fanout 0.609472 # average fanout of values written-back
2116system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
2117system.cpu1.commit.commitSquashedInsts 43653536 # The number of squashed insts skipped by commit
2118system.cpu1.commit.commitNonSpecStalls 16530232 # The number of times commit has been forced to stall to communicate backwards
2119system.cpu1.commit.branchMispredicts 4232753 # The number of times a branch was mispredicted
2120system.cpu1.commit.committed_per_cycle::samples 683948716 # Number of insts commited each cycle
2121system.cpu1.commit.committed_per_cycle::mean 0.758427 # Number of insts commited each cycle
2122system.cpu1.commit.committed_per_cycle::stdev 1.554925 # Number of insts commited each cycle
2123system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2124system.cpu1.commit.committed_per_cycle::0 453202569 66.26% 66.26% # Number of insts commited each cycle
2125system.cpu1.commit.committed_per_cycle::1 123078137 18.00% 84.26% # Number of insts commited each cycle
2126system.cpu1.commit.committed_per_cycle::2 49564580 7.25% 91.50% # Number of insts commited each cycle
2127system.cpu1.commit.committed_per_cycle::3 16593049 2.43% 93.93% # Number of insts commited each cycle
2128system.cpu1.commit.committed_per_cycle::4 11718092 1.71% 95.64% # Number of insts commited each cycle
2129system.cpu1.commit.committed_per_cycle::5 8048900 1.18% 96.82% # Number of insts commited each cycle
2130system.cpu1.commit.committed_per_cycle::6 5489767 0.80% 97.62% # Number of insts commited each cycle
2131system.cpu1.commit.committed_per_cycle::7 3345988 0.49% 98.11% # Number of insts commited each cycle
2132system.cpu1.commit.committed_per_cycle::8 12907634 1.89% 100.00% # Number of insts commited each cycle
2133system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2134system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2135system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2136system.cpu1.commit.committed_per_cycle::total 683948716 # Number of insts commited each cycle
2137system.cpu1.commit.committedInsts 441056280 # Number of instructions committed
2138system.cpu1.commit.committedOps 518724902 # Number of ops (including micro ops) committed
2139system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2140system.cpu1.commit.refs 158158187 # Number of memory references committed
2141system.cpu1.commit.loads 83043249 # Number of loads committed
2142system.cpu1.commit.membars 3695786 # Number of memory barriers committed
2143system.cpu1.commit.branches 98284315 # Number of branches committed
2144system.cpu1.commit.fp_insts 431344 # Number of committed floating point instructions.
2145system.cpu1.commit.int_insts 475340146 # Number of committed integer instructions.
2146system.cpu1.commit.function_calls 12767541 # Number of function calls committed.
2147system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2148system.cpu1.commit.op_class_0::IntAlu 359393863 69.28% 69.28% # Class of committed instruction
2149system.cpu1.commit.op_class_0::IntMult 1051243 0.20% 69.49% # Class of committed instruction
2150system.cpu1.commit.op_class_0::IntDiv 53001 0.01% 69.50% # Class of committed instruction
2151system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.50% # Class of committed instruction
2152system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.50% # Class of committed instruction
2153system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.50% # Class of committed instruction
2154system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.50% # Class of committed instruction
2155system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.50% # Class of committed instruction
2156system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.50% # Class of committed instruction
2157system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.50% # Class of committed instruction
2158system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.50% # Class of committed instruction
2159system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.50% # Class of committed instruction
2160system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.50% # Class of committed instruction
2161system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.50% # Class of committed instruction
2162system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.50% # Class of committed instruction
2163system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.50% # Class of committed instruction
2164system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.50% # Class of committed instruction
2165system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.50% # Class of committed instruction
2166system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.50% # Class of committed instruction
2167system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.50% # Class of committed instruction
2168system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.50% # Class of committed instruction
2169system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.50% # Class of committed instruction
2170system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.50% # Class of committed instruction
2171system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.50% # Class of committed instruction
2172system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.50% # Class of committed instruction
2173system.cpu1.commit.op_class_0::SimdFloatMisc 68608 0.01% 69.51% # Class of committed instruction
2174system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.51% # Class of committed instruction
2175system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.51% # Class of committed instruction
2176system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.51% # Class of committed instruction
2177system.cpu1.commit.op_class_0::MemRead 83043249 16.01% 85.52% # Class of committed instruction
2178system.cpu1.commit.op_class_0::MemWrite 75114938 14.48% 100.00% # Class of committed instruction
2179system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2180system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2181system.cpu1.commit.op_class_0::total 518724902 # Class of committed instruction
2182system.cpu1.commit.bw_lim_events 12907634 # number cycles where commit BW limit reached
2183system.cpu1.rob.rob_reads 1229236643 # The number of ROB reads
2184system.cpu1.rob.rob_writes 1133012460 # The number of ROB writes
2185system.cpu1.timesIdled 937113 # Number of times that the entire CPU went into an idle state and unscheduled itself
2186system.cpu1.idleCycles 16656481 # Total number of cycles that the CPU has spent unscheduled due to idling
2187system.cpu1.quiesceCycles 93910751930 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2188system.cpu1.committedInsts 441056280 # Number of Instructions Simulated
2189system.cpu1.committedOps 518724902 # Number of Ops (including micro ops) Simulated
2190system.cpu1.cpi 1.607281 # CPI: Cycles Per Instruction
2191system.cpu1.cpi_total 1.607281 # CPI: Total CPI of All Threads
2192system.cpu1.ipc 0.622169 # IPC: Instructions Per Cycle
2193system.cpu1.ipc_total 0.622169 # IPC: Total IPC of All Threads
2194system.cpu1.int_regfile_reads 651831389 # number of integer regfile reads
2195system.cpu1.int_regfile_writes 384949596 # number of integer regfile writes
2196system.cpu1.fp_regfile_reads 687947 # number of floating regfile reads
2197system.cpu1.fp_regfile_writes 437000 # number of floating regfile writes
2198system.cpu1.cc_regfile_reads 121245693 # number of cc regfile reads
2199system.cpu1.cc_regfile_writes 121813302 # number of cc regfile writes
2200system.cpu1.misc_regfile_reads 1231894475 # number of misc regfile reads
2201system.cpu1.misc_regfile_writes 16565900 # number of misc regfile writes
2202system.cpu1.dcache.tags.replacements 5500590 # number of replacements
2203system.cpu1.dcache.tags.tagsinuse 430.004525 # Cycle average of tags in use
2204system.cpu1.dcache.tags.total_refs 146156295 # Total number of references to valid blocks.
2205system.cpu1.dcache.tags.sampled_refs 5501102 # Sample count of references to valid blocks.
2206system.cpu1.dcache.tags.avg_refs 26.568548 # Average number of references to valid blocks.
2207system.cpu1.dcache.tags.warmup_cycle 8485200468500 # Cycle when the warmup percentage was hit.
2208system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.004525 # Average occupied blocks per requestor
2209system.cpu1.dcache.tags.occ_percent::cpu1.data 0.839853 # Average percentage of cache occupancy
2210system.cpu1.dcache.tags.occ_percent::total 0.839853 # Average percentage of cache occupancy
2211system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2212system.cpu1.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
2213system.cpu1.dcache.tags.age_task_id_blocks_1024::1 388 # Occupied blocks per task id
2214system.cpu1.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
2215system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2216system.cpu1.dcache.tags.tag_accesses 327866519 # Number of tag accesses
2217system.cpu1.dcache.tags.data_accesses 327866519 # Number of data accesses
2218system.cpu1.dcache.ReadReq_hits::cpu1.data 76697860 # number of ReadReq hits
2219system.cpu1.dcache.ReadReq_hits::total 76697860 # number of ReadReq hits
2220system.cpu1.dcache.WriteReq_hits::cpu1.data 64975008 # number of WriteReq hits
2221system.cpu1.dcache.WriteReq_hits::total 64975008 # number of WriteReq hits
2222system.cpu1.dcache.SoftPFReq_hits::cpu1.data 170492 # number of SoftPFReq hits
2223system.cpu1.dcache.SoftPFReq_hits::total 170492 # number of SoftPFReq hits
2224system.cpu1.dcache.WriteLineReq_hits::cpu1.data 54492 # number of WriteLineReq hits
2225system.cpu1.dcache.WriteLineReq_hits::total 54492 # number of WriteLineReq hits
2226system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1753772 # number of LoadLockedReq hits
2227system.cpu1.dcache.LoadLockedReq_hits::total 1753772 # number of LoadLockedReq hits
2228system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1761808 # number of StoreCondReq hits
2229system.cpu1.dcache.StoreCondReq_hits::total 1761808 # number of StoreCondReq hits
2230system.cpu1.dcache.demand_hits::cpu1.data 141672868 # number of demand (read+write) hits
2231system.cpu1.dcache.demand_hits::total 141672868 # number of demand (read+write) hits
2232system.cpu1.dcache.overall_hits::cpu1.data 141843360 # number of overall hits
2233system.cpu1.dcache.overall_hits::total 141843360 # number of overall hits
2234system.cpu1.dcache.ReadReq_misses::cpu1.data 6400758 # number of ReadReq misses
2235system.cpu1.dcache.ReadReq_misses::total 6400758 # number of ReadReq misses
2236system.cpu1.dcache.WriteReq_misses::cpu1.data 7699637 # number of WriteReq misses
2237system.cpu1.dcache.WriteReq_misses::total 7699637 # number of WriteReq misses
2238system.cpu1.dcache.SoftPFReq_misses::cpu1.data 744836 # number of SoftPFReq misses
2239system.cpu1.dcache.SoftPFReq_misses::total 744836 # number of SoftPFReq misses
2240system.cpu1.dcache.WriteLineReq_misses::cpu1.data 409878 # number of WriteLineReq misses
2241system.cpu1.dcache.WriteLineReq_misses::total 409878 # number of WriteLineReq misses
2242system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 258549 # number of LoadLockedReq misses
2243system.cpu1.dcache.LoadLockedReq_misses::total 258549 # number of LoadLockedReq misses
2244system.cpu1.dcache.StoreCondReq_misses::cpu1.data 208576 # number of StoreCondReq misses
2245system.cpu1.dcache.StoreCondReq_misses::total 208576 # number of StoreCondReq misses
2246system.cpu1.dcache.demand_misses::cpu1.data 14100395 # number of demand (read+write) misses
2247system.cpu1.dcache.demand_misses::total 14100395 # number of demand (read+write) misses
2248system.cpu1.dcache.overall_misses::cpu1.data 14845231 # number of overall misses
2249system.cpu1.dcache.overall_misses::total 14845231 # number of overall misses
2250system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 92687894000 # number of ReadReq miss cycles
2251system.cpu1.dcache.ReadReq_miss_latency::total 92687894000 # number of ReadReq miss cycles
2252system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 138325220262 # number of WriteReq miss cycles
2253system.cpu1.dcache.WriteReq_miss_latency::total 138325220262 # number of WriteReq miss cycles
2254system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 20294196326 # number of WriteLineReq miss cycles
2255system.cpu1.dcache.WriteLineReq_miss_latency::total 20294196326 # number of WriteLineReq miss cycles
2256system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4013433500 # number of LoadLockedReq miss cycles
2257system.cpu1.dcache.LoadLockedReq_miss_latency::total 4013433500 # number of LoadLockedReq miss cycles
2258system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4392601500 # number of StoreCondReq miss cycles
2259system.cpu1.dcache.StoreCondReq_miss_latency::total 4392601500 # number of StoreCondReq miss cycles
2260system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3408500 # number of StoreCondFailReq miss cycles
2261system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3408500 # number of StoreCondFailReq miss cycles
2262system.cpu1.dcache.demand_miss_latency::cpu1.data 231013114262 # number of demand (read+write) miss cycles
2263system.cpu1.dcache.demand_miss_latency::total 231013114262 # number of demand (read+write) miss cycles
2264system.cpu1.dcache.overall_miss_latency::cpu1.data 231013114262 # number of overall miss cycles
2265system.cpu1.dcache.overall_miss_latency::total 231013114262 # number of overall miss cycles
2266system.cpu1.dcache.ReadReq_accesses::cpu1.data 83098618 # number of ReadReq accesses(hits+misses)
2267system.cpu1.dcache.ReadReq_accesses::total 83098618 # number of ReadReq accesses(hits+misses)
2268system.cpu1.dcache.WriteReq_accesses::cpu1.data 72674645 # number of WriteReq accesses(hits+misses)
2269system.cpu1.dcache.WriteReq_accesses::total 72674645 # number of WriteReq accesses(hits+misses)
2270system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 915328 # number of SoftPFReq accesses(hits+misses)
2271system.cpu1.dcache.SoftPFReq_accesses::total 915328 # number of SoftPFReq accesses(hits+misses)
2272system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 464370 # number of WriteLineReq accesses(hits+misses)
2273system.cpu1.dcache.WriteLineReq_accesses::total 464370 # number of WriteLineReq accesses(hits+misses)
2274system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2012321 # number of LoadLockedReq accesses(hits+misses)
2275system.cpu1.dcache.LoadLockedReq_accesses::total 2012321 # number of LoadLockedReq accesses(hits+misses)
2276system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1970384 # number of StoreCondReq accesses(hits+misses)
2277system.cpu1.dcache.StoreCondReq_accesses::total 1970384 # number of StoreCondReq accesses(hits+misses)
2278system.cpu1.dcache.demand_accesses::cpu1.data 155773263 # number of demand (read+write) accesses
2279system.cpu1.dcache.demand_accesses::total 155773263 # number of demand (read+write) accesses
2280system.cpu1.dcache.overall_accesses::cpu1.data 156688591 # number of overall (read+write) accesses
2281system.cpu1.dcache.overall_accesses::total 156688591 # number of overall (read+write) accesses
2282system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.077026 # miss rate for ReadReq accesses
2283system.cpu1.dcache.ReadReq_miss_rate::total 0.077026 # miss rate for ReadReq accesses
2284system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.105947 # miss rate for WriteReq accesses
2285system.cpu1.dcache.WriteReq_miss_rate::total 0.105947 # miss rate for WriteReq accesses
2286system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.813737 # miss rate for SoftPFReq accesses
2287system.cpu1.dcache.SoftPFReq_miss_rate::total 0.813737 # miss rate for SoftPFReq accesses
2288system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.882654 # miss rate for WriteLineReq accesses
2289system.cpu1.dcache.WriteLineReq_miss_rate::total 0.882654 # miss rate for WriteLineReq accesses
2290system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.128483 # miss rate for LoadLockedReq accesses
2291system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.128483 # miss rate for LoadLockedReq accesses
2292system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.105856 # miss rate for StoreCondReq accesses
2293system.cpu1.dcache.StoreCondReq_miss_rate::total 0.105856 # miss rate for StoreCondReq accesses
2294system.cpu1.dcache.demand_miss_rate::cpu1.data 0.090519 # miss rate for demand accesses
2295system.cpu1.dcache.demand_miss_rate::total 0.090519 # miss rate for demand accesses
2296system.cpu1.dcache.overall_miss_rate::cpu1.data 0.094744 # miss rate for overall accesses
2297system.cpu1.dcache.overall_miss_rate::total 0.094744 # miss rate for overall accesses
2298system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14480.768371 # average ReadReq miss latency
2299system.cpu1.dcache.ReadReq_avg_miss_latency::total 14480.768371 # average ReadReq miss latency
2300system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17965.161249 # average WriteReq miss latency
2301system.cpu1.dcache.WriteReq_avg_miss_latency::total 17965.161249 # average WriteReq miss latency
2302system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 49512.772889 # average WriteLineReq miss latency
2303system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 49512.772889 # average WriteLineReq miss latency
2304system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15522.912485 # average LoadLockedReq miss latency
2305system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15522.912485 # average LoadLockedReq miss latency
2306system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21059.956563 # average StoreCondReq miss latency
2307system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21059.956563 # average StoreCondReq miss latency
2308system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
2309system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2310system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16383.449844 # average overall miss latency
2311system.cpu1.dcache.demand_avg_miss_latency::total 16383.449844 # average overall miss latency
2312system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15561.436145 # average overall miss latency
2313system.cpu1.dcache.overall_avg_miss_latency::total 15561.436145 # average overall miss latency
2314system.cpu1.dcache.blocked_cycles::no_mshrs 5682783 # number of cycles access was blocked
2315system.cpu1.dcache.blocked_cycles::no_targets 23004045 # number of cycles access was blocked
2316system.cpu1.dcache.blocked::no_mshrs 345925 # number of cycles access was blocked
2317system.cpu1.dcache.blocked::no_targets 792691 # number of cycles access was blocked
2318system.cpu1.dcache.avg_blocked_cycles::no_mshrs 16.427789 # average number of cycles each access was blocked
2319system.cpu1.dcache.avg_blocked_cycles::no_targets 29.020192 # average number of cycles each access was blocked
2320system.cpu1.dcache.fast_writes 0 # number of fast writes performed
2321system.cpu1.dcache.cache_copies 0 # number of cache copies performed
2322system.cpu1.dcache.writebacks::writebacks 3566261 # number of writebacks
2323system.cpu1.dcache.writebacks::total 3566261 # number of writebacks
2324system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3293272 # number of ReadReq MSHR hits
2325system.cpu1.dcache.ReadReq_mshr_hits::total 3293272 # number of ReadReq MSHR hits
2326system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6267237 # number of WriteReq MSHR hits
2327system.cpu1.dcache.WriteReq_mshr_hits::total 6267237 # number of WriteReq MSHR hits
2328system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 2938 # number of WriteLineReq MSHR hits
2329system.cpu1.dcache.WriteLineReq_mshr_hits::total 2938 # number of WriteLineReq MSHR hits
2330system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 130878 # number of LoadLockedReq MSHR hits
2331system.cpu1.dcache.LoadLockedReq_mshr_hits::total 130878 # number of LoadLockedReq MSHR hits
2332system.cpu1.dcache.demand_mshr_hits::cpu1.data 9560509 # number of demand (read+write) MSHR hits
2333system.cpu1.dcache.demand_mshr_hits::total 9560509 # number of demand (read+write) MSHR hits
2334system.cpu1.dcache.overall_mshr_hits::cpu1.data 9560509 # number of overall MSHR hits
2335system.cpu1.dcache.overall_mshr_hits::total 9560509 # number of overall MSHR hits
2336system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3107486 # number of ReadReq MSHR misses
2337system.cpu1.dcache.ReadReq_mshr_misses::total 3107486 # number of ReadReq MSHR misses
2338system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1432400 # number of WriteReq MSHR misses
2339system.cpu1.dcache.WriteReq_mshr_misses::total 1432400 # number of WriteReq MSHR misses
2340system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 744751 # number of SoftPFReq MSHR misses
2341system.cpu1.dcache.SoftPFReq_mshr_misses::total 744751 # number of SoftPFReq MSHR misses
2342system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 406940 # number of WriteLineReq MSHR misses
2343system.cpu1.dcache.WriteLineReq_mshr_misses::total 406940 # number of WriteLineReq MSHR misses
2344system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 127671 # number of LoadLockedReq MSHR misses
2345system.cpu1.dcache.LoadLockedReq_mshr_misses::total 127671 # number of LoadLockedReq MSHR misses
2346system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 208566 # number of StoreCondReq MSHR misses
2347system.cpu1.dcache.StoreCondReq_mshr_misses::total 208566 # number of StoreCondReq MSHR misses
2348system.cpu1.dcache.demand_mshr_misses::cpu1.data 4539886 # number of demand (read+write) MSHR misses
2349system.cpu1.dcache.demand_mshr_misses::total 4539886 # number of demand (read+write) MSHR misses
2350system.cpu1.dcache.overall_mshr_misses::cpu1.data 5284637 # number of overall MSHR misses
2351system.cpu1.dcache.overall_mshr_misses::total 5284637 # number of overall MSHR misses
2352system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 16935 # number of ReadReq MSHR uncacheable
2353system.cpu1.dcache.ReadReq_mshr_uncacheable::total 16935 # number of ReadReq MSHR uncacheable
2354system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14896 # number of WriteReq MSHR uncacheable
2355system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14896 # number of WriteReq MSHR uncacheable
2356system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31831 # number of overall MSHR uncacheable misses
2357system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31831 # number of overall MSHR uncacheable misses
2358system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 43040497000 # number of ReadReq MSHR miss cycles
2359system.cpu1.dcache.ReadReq_mshr_miss_latency::total 43040497000 # number of ReadReq MSHR miss cycles
2360system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26400232128 # number of WriteReq MSHR miss cycles
2361system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26400232128 # number of WriteReq MSHR miss cycles
2362system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15655161500 # number of SoftPFReq MSHR miss cycles
2363system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15655161500 # number of SoftPFReq MSHR miss cycles
2364system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 19798456326 # number of WriteLineReq MSHR miss cycles
2365system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 19798456326 # number of WriteLineReq MSHR miss cycles
2366system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1838541000 # number of LoadLockedReq MSHR miss cycles
2367system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1838541000 # number of LoadLockedReq MSHR miss cycles
2368system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4184106500 # number of StoreCondReq MSHR miss cycles
2369system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4184106500 # number of StoreCondReq MSHR miss cycles
2370system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3337500 # number of StoreCondFailReq MSHR miss cycles
2371system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3337500 # number of StoreCondFailReq MSHR miss cycles
2372system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69440729128 # number of demand (read+write) MSHR miss cycles
2373system.cpu1.dcache.demand_mshr_miss_latency::total 69440729128 # number of demand (read+write) MSHR miss cycles
2374system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 85095890628 # number of overall MSHR miss cycles
2375system.cpu1.dcache.overall_mshr_miss_latency::total 85095890628 # number of overall MSHR miss cycles
2376system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2604403500 # number of ReadReq MSHR uncacheable cycles
2377system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2604403500 # number of ReadReq MSHR uncacheable cycles
2378system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2300537000 # number of WriteReq MSHR uncacheable cycles
2379system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2300537000 # number of WriteReq MSHR uncacheable cycles
2380system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4904940500 # number of overall MSHR uncacheable cycles
2381system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4904940500 # number of overall MSHR uncacheable cycles
2382system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037395 # mshr miss rate for ReadReq accesses
2383system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037395 # mshr miss rate for ReadReq accesses
2384system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019710 # mshr miss rate for WriteReq accesses
2385system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019710 # mshr miss rate for WriteReq accesses
2386system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.813644 # mshr miss rate for SoftPFReq accesses
2387system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.813644 # mshr miss rate for SoftPFReq accesses
2388system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.876327 # mshr miss rate for WriteLineReq accesses
2389system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.876327 # mshr miss rate for WriteLineReq accesses
2390system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063445 # mshr miss rate for LoadLockedReq accesses
2391system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063445 # mshr miss rate for LoadLockedReq accesses
2392system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.105850 # mshr miss rate for StoreCondReq accesses
2393system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.105850 # mshr miss rate for StoreCondReq accesses
2394system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029144 # mshr miss rate for demand accesses
2395system.cpu1.dcache.demand_mshr_miss_rate::total 0.029144 # mshr miss rate for demand accesses
2396system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033727 # mshr miss rate for overall accesses
2397system.cpu1.dcache.overall_mshr_miss_rate::total 0.033727 # mshr miss rate for overall accesses
2398system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13850.584363 # average ReadReq mshr miss latency
2399system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13850.584363 # average ReadReq mshr miss latency
2400system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18430.768031 # average WriteReq mshr miss latency
2401system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18430.768031 # average WriteReq mshr miss latency
2402system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21020.665296 # average SoftPFReq mshr miss latency
2403system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21020.665296 # average SoftPFReq mshr miss latency
2404system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 48652.028127 # average WriteLineReq mshr miss latency
2405system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 48652.028127 # average WriteLineReq mshr miss latency
2406system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14400.615645 # average LoadLockedReq mshr miss latency
2407system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14400.615645 # average LoadLockedReq mshr miss latency
2408system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20061.306733 # average StoreCondReq mshr miss latency
2409system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20061.306733 # average StoreCondReq mshr miss latency
2410system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
2411system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2412system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15295.698863 # average overall mshr miss latency
2413system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15295.698863 # average overall mshr miss latency
2414system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16102.504416 # average overall mshr miss latency
2415system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16102.504416 # average overall mshr miss latency
2416system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 153788.219663 # average ReadReq mshr uncacheable latency
2417system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 153788.219663 # average ReadReq mshr uncacheable latency
2418system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154439.916756 # average WriteReq mshr uncacheable latency
2419system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154439.916756 # average WriteReq mshr uncacheable latency
2420system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 154093.195313 # average overall mshr uncacheable latency
2421system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 154093.195313 # average overall mshr uncacheable latency
2422system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2423system.cpu1.icache.tags.replacements 5403947 # number of replacements
2424system.cpu1.icache.tags.tagsinuse 501.811782 # Cycle average of tags in use
2425system.cpu1.icache.tags.total_refs 197154720 # Total number of references to valid blocks.
2426system.cpu1.icache.tags.sampled_refs 5404459 # Sample count of references to valid blocks.
2427system.cpu1.icache.tags.avg_refs 36.480010 # Average number of references to valid blocks.
2428system.cpu1.icache.tags.warmup_cycle 8495886874000 # Cycle when the warmup percentage was hit.
2429system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.811782 # Average occupied blocks per requestor
2430system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980101 # Average percentage of cache occupancy
2431system.cpu1.icache.tags.occ_percent::total 0.980101 # Average percentage of cache occupancy
2432system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2433system.cpu1.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
2434system.cpu1.icache.tags.age_task_id_blocks_1024::1 334 # Occupied blocks per task id
2435system.cpu1.icache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id
2436system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2437system.cpu1.icache.tags.tag_accesses 411165528 # Number of tag accesses
2438system.cpu1.icache.tags.data_accesses 411165528 # Number of data accesses
2439system.cpu1.icache.ReadReq_hits::cpu1.inst 197154720 # number of ReadReq hits
2440system.cpu1.icache.ReadReq_hits::total 197154720 # number of ReadReq hits
2441system.cpu1.icache.demand_hits::cpu1.inst 197154720 # number of demand (read+write) hits
2442system.cpu1.icache.demand_hits::total 197154720 # number of demand (read+write) hits
2443system.cpu1.icache.overall_hits::cpu1.inst 197154720 # number of overall hits
2444system.cpu1.icache.overall_hits::total 197154720 # number of overall hits
2445system.cpu1.icache.ReadReq_misses::cpu1.inst 5725810 # number of ReadReq misses
2446system.cpu1.icache.ReadReq_misses::total 5725810 # number of ReadReq misses
2447system.cpu1.icache.demand_misses::cpu1.inst 5725810 # number of demand (read+write) misses
2448system.cpu1.icache.demand_misses::total 5725810 # number of demand (read+write) misses
2449system.cpu1.icache.overall_misses::cpu1.inst 5725810 # number of overall misses
2450system.cpu1.icache.overall_misses::total 5725810 # number of overall misses
2451system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 59819230732 # number of ReadReq miss cycles
2452system.cpu1.icache.ReadReq_miss_latency::total 59819230732 # number of ReadReq miss cycles
2453system.cpu1.icache.demand_miss_latency::cpu1.inst 59819230732 # number of demand (read+write) miss cycles
2454system.cpu1.icache.demand_miss_latency::total 59819230732 # number of demand (read+write) miss cycles
2455system.cpu1.icache.overall_miss_latency::cpu1.inst 59819230732 # number of overall miss cycles
2456system.cpu1.icache.overall_miss_latency::total 59819230732 # number of overall miss cycles
2457system.cpu1.icache.ReadReq_accesses::cpu1.inst 202880530 # number of ReadReq accesses(hits+misses)
2458system.cpu1.icache.ReadReq_accesses::total 202880530 # number of ReadReq accesses(hits+misses)
2459system.cpu1.icache.demand_accesses::cpu1.inst 202880530 # number of demand (read+write) accesses
2460system.cpu1.icache.demand_accesses::total 202880530 # number of demand (read+write) accesses
2461system.cpu1.icache.overall_accesses::cpu1.inst 202880530 # number of overall (read+write) accesses
2462system.cpu1.icache.overall_accesses::total 202880530 # number of overall (read+write) accesses
2463system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028223 # miss rate for ReadReq accesses
2464system.cpu1.icache.ReadReq_miss_rate::total 0.028223 # miss rate for ReadReq accesses
2465system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028223 # miss rate for demand accesses
2466system.cpu1.icache.demand_miss_rate::total 0.028223 # miss rate for demand accesses
2467system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028223 # miss rate for overall accesses
2468system.cpu1.icache.overall_miss_rate::total 0.028223 # miss rate for overall accesses
2469system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10447.295794 # average ReadReq miss latency
2470system.cpu1.icache.ReadReq_avg_miss_latency::total 10447.295794 # average ReadReq miss latency
2471system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10447.295794 # average overall miss latency
2472system.cpu1.icache.demand_avg_miss_latency::total 10447.295794 # average overall miss latency
2473system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10447.295794 # average overall miss latency
2474system.cpu1.icache.overall_avg_miss_latency::total 10447.295794 # average overall miss latency
2475system.cpu1.icache.blocked_cycles::no_mshrs 8523796 # number of cycles access was blocked
2476system.cpu1.icache.blocked_cycles::no_targets 288 # number of cycles access was blocked
2477system.cpu1.icache.blocked::no_mshrs 664103 # number of cycles access was blocked
2478system.cpu1.icache.blocked::no_targets 3 # number of cycles access was blocked
2479system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.835051 # average number of cycles each access was blocked
2480system.cpu1.icache.avg_blocked_cycles::no_targets 96 # average number of cycles each access was blocked
2481system.cpu1.icache.fast_writes 0 # number of fast writes performed
2482system.cpu1.icache.cache_copies 0 # number of cache copies performed
2483system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 321342 # number of ReadReq MSHR hits
2484system.cpu1.icache.ReadReq_mshr_hits::total 321342 # number of ReadReq MSHR hits
2485system.cpu1.icache.demand_mshr_hits::cpu1.inst 321342 # number of demand (read+write) MSHR hits
2486system.cpu1.icache.demand_mshr_hits::total 321342 # number of demand (read+write) MSHR hits
2487system.cpu1.icache.overall_mshr_hits::cpu1.inst 321342 # number of overall MSHR hits
2488system.cpu1.icache.overall_mshr_hits::total 321342 # number of overall MSHR hits
2489system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5404468 # number of ReadReq MSHR misses
2490system.cpu1.icache.ReadReq_mshr_misses::total 5404468 # number of ReadReq MSHR misses
2491system.cpu1.icache.demand_mshr_misses::cpu1.inst 5404468 # number of demand (read+write) MSHR misses
2492system.cpu1.icache.demand_mshr_misses::total 5404468 # number of demand (read+write) MSHR misses
2493system.cpu1.icache.overall_mshr_misses::cpu1.inst 5404468 # number of overall MSHR misses
2494system.cpu1.icache.overall_mshr_misses::total 5404468 # number of overall MSHR misses
2495system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
2496system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable
2497system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
2498system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses
2499system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 54260492010 # number of ReadReq MSHR miss cycles
2500system.cpu1.icache.ReadReq_mshr_miss_latency::total 54260492010 # number of ReadReq MSHR miss cycles
2501system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 54260492010 # number of demand (read+write) MSHR miss cycles
2502system.cpu1.icache.demand_mshr_miss_latency::total 54260492010 # number of demand (read+write) MSHR miss cycles
2503system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 54260492010 # number of overall MSHR miss cycles
2504system.cpu1.icache.overall_mshr_miss_latency::total 54260492010 # number of overall MSHR miss cycles
2505system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5791998 # number of ReadReq MSHR uncacheable cycles
2506system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5791998 # number of ReadReq MSHR uncacheable cycles
2507system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5791998 # number of overall MSHR uncacheable cycles
2508system.cpu1.icache.overall_mshr_uncacheable_latency::total 5791998 # number of overall MSHR uncacheable cycles
2509system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.026639 # mshr miss rate for ReadReq accesses
2510system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.026639 # mshr miss rate for ReadReq accesses
2511system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.026639 # mshr miss rate for demand accesses
2512system.cpu1.icache.demand_mshr_miss_rate::total 0.026639 # mshr miss rate for demand accesses
2513system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.026639 # mshr miss rate for overall accesses
2514system.cpu1.icache.overall_mshr_miss_rate::total 0.026639 # mshr miss rate for overall accesses
2515system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10039.932147 # average ReadReq mshr miss latency
2516system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10039.932147 # average ReadReq mshr miss latency
2517system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10039.932147 # average overall mshr miss latency
2518system.cpu1.icache.demand_avg_mshr_miss_latency::total 10039.932147 # average overall mshr miss latency
2519system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10039.932147 # average overall mshr miss latency
2520system.cpu1.icache.overall_avg_mshr_miss_latency::total 10039.932147 # average overall mshr miss latency
2521system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86447.731343 # average ReadReq mshr uncacheable latency
2522system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86447.731343 # average ReadReq mshr uncacheable latency
2523system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86447.731343 # average overall mshr uncacheable latency
2524system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86447.731343 # average overall mshr uncacheable latency
2525system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2526system.cpu1.l2cache.prefetcher.num_hwpf_issued 7840068 # number of hwpf issued
2527system.cpu1.l2cache.prefetcher.pfIdentified 7844426 # number of prefetch candidates identified
2528system.cpu1.l2cache.prefetcher.pfBufferHit 3981 # number of redundant prefetches already in prefetch queue
2529system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
2530system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2531system.cpu1.l2cache.prefetcher.pfSpanPage 944222 # number of prefetches not generated due to page crossing
2532system.cpu1.l2cache.tags.replacements 2377748 # number of replacements
2533system.cpu1.l2cache.tags.tagsinuse 13486.772220 # Cycle average of tags in use
2534system.cpu1.l2cache.tags.total_refs 18876475 # Total number of references to valid blocks.
2535system.cpu1.l2cache.tags.sampled_refs 2393818 # Sample count of references to valid blocks.
2536system.cpu1.l2cache.tags.avg_refs 7.885510 # Average number of references to valid blocks.
2537system.cpu1.l2cache.tags.warmup_cycle 10140216096000 # Cycle when the warmup percentage was hit.
2538system.cpu1.l2cache.tags.occ_blocks::writebacks 5055.984886 # Average occupied blocks per requestor
2539system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 70.053821 # Average occupied blocks per requestor
2540system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 84.713714 # Average occupied blocks per requestor
2541system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3027.541847 # Average occupied blocks per requestor
2542system.cpu1.l2cache.tags.occ_blocks::cpu1.data 4406.199695 # Average occupied blocks per requestor
2543system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 842.278257 # Average occupied blocks per requestor
2544system.cpu1.l2cache.tags.occ_percent::writebacks 0.308593 # Average percentage of cache occupancy
2545system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004276 # Average percentage of cache occupancy
2546system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005171 # Average percentage of cache occupancy
2547system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.184786 # Average percentage of cache occupancy
2548system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.268933 # Average percentage of cache occupancy
2549system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051409 # Average percentage of cache occupancy
2550system.cpu1.l2cache.tags.occ_percent::total 0.823167 # Average percentage of cache occupancy
2551system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1281 # Occupied blocks per task id
2552system.cpu1.l2cache.tags.occ_task_id_blocks::1023 69 # Occupied blocks per task id
2553system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14720 # Occupied blocks per task id
2554system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
2555system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 30 # Occupied blocks per task id
2556system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 223 # Occupied blocks per task id
2557system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 628 # Occupied blocks per task id
2558system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 392 # Occupied blocks per task id
2559system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id
2560system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 34 # Occupied blocks per task id
2561system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 14 # Occupied blocks per task id
2562system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 19 # Occupied blocks per task id
2563system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id
2564system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1431 # Occupied blocks per task id
2565system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5385 # Occupied blocks per task id
2566system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4653 # Occupied blocks per task id
2567system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3120 # Occupied blocks per task id
2568system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078186 # Percentage of cache occupancy per task id
2569system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004211 # Percentage of cache occupancy per task id
2570system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.898438 # Percentage of cache occupancy per task id
2571system.cpu1.l2cache.tags.tag_accesses 375099508 # Number of tag accesses
2572system.cpu1.l2cache.tags.data_accesses 375099508 # Number of data accesses
2573system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 592978 # number of ReadReq hits
2574system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 185889 # number of ReadReq hits
2575system.cpu1.l2cache.ReadReq_hits::total 778867 # number of ReadReq hits
2576system.cpu1.l2cache.Writeback_hits::writebacks 3566243 # number of Writeback hits
2577system.cpu1.l2cache.Writeback_hits::total 3566243 # number of Writeback hits
2578system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 83253 # number of UpgradeReq hits
2579system.cpu1.l2cache.UpgradeReq_hits::total 83253 # number of UpgradeReq hits
2580system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 35939 # number of SCUpgradeReq hits
2581system.cpu1.l2cache.SCUpgradeReq_hits::total 35939 # number of SCUpgradeReq hits
2582system.cpu1.l2cache.ReadExReq_hits::cpu1.data 957303 # number of ReadExReq hits
2583system.cpu1.l2cache.ReadExReq_hits::total 957303 # number of ReadExReq hits
2584system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4781175 # number of ReadCleanReq hits
2585system.cpu1.l2cache.ReadCleanReq_hits::total 4781175 # number of ReadCleanReq hits
2586system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2910784 # number of ReadSharedReq hits
2587system.cpu1.l2cache.ReadSharedReq_hits::total 2910784 # number of ReadSharedReq hits
2588system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 147109 # number of InvalidateReq hits
2589system.cpu1.l2cache.InvalidateReq_hits::total 147109 # number of InvalidateReq hits
2590system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 592978 # number of demand (read+write) hits
2591system.cpu1.l2cache.demand_hits::cpu1.itb.walker 185889 # number of demand (read+write) hits
2592system.cpu1.l2cache.demand_hits::cpu1.inst 4781175 # number of demand (read+write) hits
2593system.cpu1.l2cache.demand_hits::cpu1.data 3868087 # number of demand (read+write) hits
2594system.cpu1.l2cache.demand_hits::total 9428129 # number of demand (read+write) hits
2595system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 592978 # number of overall hits
2596system.cpu1.l2cache.overall_hits::cpu1.itb.walker 185889 # number of overall hits
2597system.cpu1.l2cache.overall_hits::cpu1.inst 4781175 # number of overall hits
2598system.cpu1.l2cache.overall_hits::cpu1.data 3868087 # number of overall hits
2599system.cpu1.l2cache.overall_hits::total 9428129 # number of overall hits
2600system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12789 # number of ReadReq misses
2601system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9475 # number of ReadReq misses
2602system.cpu1.l2cache.ReadReq_misses::total 22264 # number of ReadReq misses
2603system.cpu1.l2cache.Writeback_misses::writebacks 18 # number of Writeback misses
2604system.cpu1.l2cache.Writeback_misses::total 18 # number of Writeback misses
2605system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 144289 # number of UpgradeReq misses
2606system.cpu1.l2cache.UpgradeReq_misses::total 144289 # number of UpgradeReq misses
2607system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 172622 # number of SCUpgradeReq misses
2608system.cpu1.l2cache.SCUpgradeReq_misses::total 172622 # number of SCUpgradeReq misses
2609system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses
2610system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses
2611system.cpu1.l2cache.ReadExReq_misses::cpu1.data 255780 # number of ReadExReq misses
2612system.cpu1.l2cache.ReadExReq_misses::total 255780 # number of ReadExReq misses
2613system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 623287 # number of ReadCleanReq misses
2614system.cpu1.l2cache.ReadCleanReq_misses::total 623287 # number of ReadCleanReq misses
2615system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1065341 # number of ReadSharedReq misses
2616system.cpu1.l2cache.ReadSharedReq_misses::total 1065341 # number of ReadSharedReq misses
2617system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 258817 # number of InvalidateReq misses
2618system.cpu1.l2cache.InvalidateReq_misses::total 258817 # number of InvalidateReq misses
2619system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12789 # number of demand (read+write) misses
2620system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9475 # number of demand (read+write) misses
2621system.cpu1.l2cache.demand_misses::cpu1.inst 623287 # number of demand (read+write) misses
2622system.cpu1.l2cache.demand_misses::cpu1.data 1321121 # number of demand (read+write) misses
2623system.cpu1.l2cache.demand_misses::total 1966672 # number of demand (read+write) misses
2624system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12789 # number of overall misses
2625system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9475 # number of overall misses
2626system.cpu1.l2cache.overall_misses::cpu1.inst 623287 # number of overall misses
2627system.cpu1.l2cache.overall_misses::cpu1.data 1321121 # number of overall misses
2628system.cpu1.l2cache.overall_misses::total 1966672 # number of overall misses
2629system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 512874500 # number of ReadReq miss cycles
2630system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 430496500 # number of ReadReq miss cycles
2631system.cpu1.l2cache.ReadReq_miss_latency::total 943371000 # number of ReadReq miss cycles
2632system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3103492000 # number of UpgradeReq miss cycles
2633system.cpu1.l2cache.UpgradeReq_miss_latency::total 3103492000 # number of UpgradeReq miss cycles
2634system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3553775999 # number of SCUpgradeReq miss cycles
2635system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3553775999 # number of SCUpgradeReq miss cycles
2636system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3230499 # number of SCUpgradeFailReq miss cycles
2637system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3230499 # number of SCUpgradeFailReq miss cycles
2638system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 13173602496 # number of ReadExReq miss cycles
2639system.cpu1.l2cache.ReadExReq_miss_latency::total 13173602496 # number of ReadExReq miss cycles
2640system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 17677681000 # number of ReadCleanReq miss cycles
2641system.cpu1.l2cache.ReadCleanReq_miss_latency::total 17677681000 # number of ReadCleanReq miss cycles
2642system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 35240864484 # number of ReadSharedReq miss cycles
2643system.cpu1.l2cache.ReadSharedReq_miss_latency::total 35240864484 # number of ReadSharedReq miss cycles
2644system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 17868215998 # number of InvalidateReq miss cycles
2645system.cpu1.l2cache.InvalidateReq_miss_latency::total 17868215998 # number of InvalidateReq miss cycles
2646system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 512874500 # number of demand (read+write) miss cycles
2647system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 430496500 # number of demand (read+write) miss cycles
2648system.cpu1.l2cache.demand_miss_latency::cpu1.inst 17677681000 # number of demand (read+write) miss cycles
2649system.cpu1.l2cache.demand_miss_latency::cpu1.data 48414466980 # number of demand (read+write) miss cycles
2650system.cpu1.l2cache.demand_miss_latency::total 67035518980 # number of demand (read+write) miss cycles
2651system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 512874500 # number of overall miss cycles
2652system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 430496500 # number of overall miss cycles
2653system.cpu1.l2cache.overall_miss_latency::cpu1.inst 17677681000 # number of overall miss cycles
2654system.cpu1.l2cache.overall_miss_latency::cpu1.data 48414466980 # number of overall miss cycles
2655system.cpu1.l2cache.overall_miss_latency::total 67035518980 # number of overall miss cycles
2656system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 605767 # number of ReadReq accesses(hits+misses)
2657system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 195364 # number of ReadReq accesses(hits+misses)
2658system.cpu1.l2cache.ReadReq_accesses::total 801131 # number of ReadReq accesses(hits+misses)
2659system.cpu1.l2cache.Writeback_accesses::writebacks 3566261 # number of Writeback accesses(hits+misses)
2660system.cpu1.l2cache.Writeback_accesses::total 3566261 # number of Writeback accesses(hits+misses)
2661system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 227542 # number of UpgradeReq accesses(hits+misses)
2662system.cpu1.l2cache.UpgradeReq_accesses::total 227542 # number of UpgradeReq accesses(hits+misses)
2663system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 208561 # number of SCUpgradeReq accesses(hits+misses)
2664system.cpu1.l2cache.SCUpgradeReq_accesses::total 208561 # number of SCUpgradeReq accesses(hits+misses)
2665system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses)
2666system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses)
2667system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1213083 # number of ReadExReq accesses(hits+misses)
2668system.cpu1.l2cache.ReadExReq_accesses::total 1213083 # number of ReadExReq accesses(hits+misses)
2669system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5404462 # number of ReadCleanReq accesses(hits+misses)
2670system.cpu1.l2cache.ReadCleanReq_accesses::total 5404462 # number of ReadCleanReq accesses(hits+misses)
2671system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3976125 # number of ReadSharedReq accesses(hits+misses)
2672system.cpu1.l2cache.ReadSharedReq_accesses::total 3976125 # number of ReadSharedReq accesses(hits+misses)
2673system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 405926 # number of InvalidateReq accesses(hits+misses)
2674system.cpu1.l2cache.InvalidateReq_accesses::total 405926 # number of InvalidateReq accesses(hits+misses)
2675system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 605767 # number of demand (read+write) accesses
2676system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 195364 # number of demand (read+write) accesses
2677system.cpu1.l2cache.demand_accesses::cpu1.inst 5404462 # number of demand (read+write) accesses
2678system.cpu1.l2cache.demand_accesses::cpu1.data 5189208 # number of demand (read+write) accesses
2679system.cpu1.l2cache.demand_accesses::total 11394801 # number of demand (read+write) accesses
2680system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 605767 # number of overall (read+write) accesses
2681system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 195364 # number of overall (read+write) accesses
2682system.cpu1.l2cache.overall_accesses::cpu1.inst 5404462 # number of overall (read+write) accesses
2683system.cpu1.l2cache.overall_accesses::cpu1.data 5189208 # number of overall (read+write) accesses
2684system.cpu1.l2cache.overall_accesses::total 11394801 # number of overall (read+write) accesses
2685system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021112 # miss rate for ReadReq accesses
2686system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048499 # miss rate for ReadReq accesses
2687system.cpu1.l2cache.ReadReq_miss_rate::total 0.027791 # miss rate for ReadReq accesses
2688system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000005 # miss rate for Writeback accesses
2689system.cpu1.l2cache.Writeback_miss_rate::total 0.000005 # miss rate for Writeback accesses
2690system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.634120 # miss rate for UpgradeReq accesses
2691system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.634120 # miss rate for UpgradeReq accesses
2692system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.827681 # miss rate for SCUpgradeReq accesses
2693system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.827681 # miss rate for SCUpgradeReq accesses
2694system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2695system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2696system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.210851 # miss rate for ReadExReq accesses
2697system.cpu1.l2cache.ReadExReq_miss_rate::total 0.210851 # miss rate for ReadExReq accesses
2698system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.115328 # miss rate for ReadCleanReq accesses
2699system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.115328 # miss rate for ReadCleanReq accesses
2700system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.267934 # miss rate for ReadSharedReq accesses
2701system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.267934 # miss rate for ReadSharedReq accesses
2702system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.637597 # miss rate for InvalidateReq accesses
2703system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.637597 # miss rate for InvalidateReq accesses
2704system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021112 # miss rate for demand accesses
2705system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048499 # miss rate for demand accesses
2706system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.115328 # miss rate for demand accesses
2707system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.254590 # miss rate for demand accesses
2708system.cpu1.l2cache.demand_miss_rate::total 0.172594 # miss rate for demand accesses
2709system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021112 # miss rate for overall accesses
2710system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048499 # miss rate for overall accesses
2711system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.115328 # miss rate for overall accesses
2712system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.254590 # miss rate for overall accesses
2713system.cpu1.l2cache.overall_miss_rate::total 0.172594 # miss rate for overall accesses
2714system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 40102.783642 # average ReadReq miss latency
2715system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 45434.986807 # average ReadReq miss latency
2716system.cpu1.l2cache.ReadReq_avg_miss_latency::total 42372.035573 # average ReadReq miss latency
2717system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21508.860689 # average UpgradeReq miss latency
2718system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21508.860689 # average UpgradeReq miss latency
2719system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20587.039885 # average SCUpgradeReq miss latency
2720system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20587.039885 # average SCUpgradeReq miss latency
2721system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 646099.800000 # average SCUpgradeFailReq miss latency
2722system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 646099.800000 # average SCUpgradeFailReq miss latency
2723system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51503.645696 # average ReadExReq miss latency
2724system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51503.645696 # average ReadExReq miss latency
2725system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 28362.024236 # average ReadCleanReq miss latency
2726system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 28362.024236 # average ReadCleanReq miss latency
2727system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 33079.421973 # average ReadSharedReq miss latency
2728system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 33079.421973 # average ReadSharedReq miss latency
2729system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 69038.030724 # average InvalidateReq miss latency
2730system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 69038.030724 # average InvalidateReq miss latency
2731system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 40102.783642 # average overall miss latency
2732system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 45434.986807 # average overall miss latency
2733system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28362.024236 # average overall miss latency
2734system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36646.504733 # average overall miss latency
2735system.cpu1.l2cache.demand_avg_miss_latency::total 34085.764673 # average overall miss latency
2736system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 40102.783642 # average overall miss latency
2737system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 45434.986807 # average overall miss latency
2738system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28362.024236 # average overall miss latency
2739system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36646.504733 # average overall miss latency
2740system.cpu1.l2cache.overall_avg_miss_latency::total 34085.764673 # average overall miss latency
2741system.cpu1.l2cache.blocked_cycles::no_mshrs 3889 # number of cycles access was blocked
2742system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2743system.cpu1.l2cache.blocked::no_mshrs 13 # number of cycles access was blocked
2744system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2745system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 299.153846 # average number of cycles each access was blocked
2746system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2747system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2748system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2749system.cpu1.l2cache.writebacks::writebacks 1147174 # number of writebacks
2750system.cpu1.l2cache.writebacks::total 1147174 # number of writebacks
2751system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 3 # number of ReadReq MSHR hits
2752system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 177 # number of ReadReq MSHR hits
2753system.cpu1.l2cache.ReadReq_mshr_hits::total 180 # number of ReadReq MSHR hits
2754system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 16460 # number of ReadExReq MSHR hits
2755system.cpu1.l2cache.ReadExReq_mshr_hits::total 16460 # number of ReadExReq MSHR hits
2756system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits
2757system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
2758system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 3382 # number of ReadSharedReq MSHR hits
2759system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 3382 # number of ReadSharedReq MSHR hits
2760system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 3 # number of InvalidateReq MSHR hits
2761system.cpu1.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits
2762system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 3 # number of demand (read+write) MSHR hits
2763system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 177 # number of demand (read+write) MSHR hits
2764system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits
2765system.cpu1.l2cache.demand_mshr_hits::cpu1.data 19842 # number of demand (read+write) MSHR hits
2766system.cpu1.l2cache.demand_mshr_hits::total 20023 # number of demand (read+write) MSHR hits
2767system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 3 # number of overall MSHR hits
2768system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 177 # number of overall MSHR hits
2769system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits
2770system.cpu1.l2cache.overall_mshr_hits::cpu1.data 19842 # number of overall MSHR hits
2771system.cpu1.l2cache.overall_mshr_hits::total 20023 # number of overall MSHR hits
2772system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12786 # number of ReadReq MSHR misses
2773system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9298 # number of ReadReq MSHR misses
2774system.cpu1.l2cache.ReadReq_mshr_misses::total 22084 # number of ReadReq MSHR misses
2775system.cpu1.l2cache.Writeback_mshr_misses::writebacks 18 # number of Writeback MSHR misses
2776system.cpu1.l2cache.Writeback_mshr_misses::total 18 # number of Writeback MSHR misses
2777system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 111700 # number of CleanEvict MSHR misses
2778system.cpu1.l2cache.CleanEvict_mshr_misses::total 111700 # number of CleanEvict MSHR misses
2779system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 804888 # number of HardPFReq MSHR misses
2780system.cpu1.l2cache.HardPFReq_mshr_misses::total 804888 # number of HardPFReq MSHR misses
2781system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 144289 # number of UpgradeReq MSHR misses
2782system.cpu1.l2cache.UpgradeReq_mshr_misses::total 144289 # number of UpgradeReq MSHR misses
2783system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 172622 # number of SCUpgradeReq MSHR misses
2784system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 172622 # number of SCUpgradeReq MSHR misses
2785system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses
2786system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses
2787system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 239320 # number of ReadExReq MSHR misses
2788system.cpu1.l2cache.ReadExReq_mshr_misses::total 239320 # number of ReadExReq MSHR misses
2789system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 623286 # number of ReadCleanReq MSHR misses
2790system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 623286 # number of ReadCleanReq MSHR misses
2791system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 1061959 # number of ReadSharedReq MSHR misses
2792system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 1061959 # number of ReadSharedReq MSHR misses
2793system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 258814 # number of InvalidateReq MSHR misses
2794system.cpu1.l2cache.InvalidateReq_mshr_misses::total 258814 # number of InvalidateReq MSHR misses
2795system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12786 # number of demand (read+write) MSHR misses
2796system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9298 # number of demand (read+write) MSHR misses
2797system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 623286 # number of demand (read+write) MSHR misses
2798system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1301279 # number of demand (read+write) MSHR misses
2799system.cpu1.l2cache.demand_mshr_misses::total 1946649 # number of demand (read+write) MSHR misses
2800system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12786 # number of overall MSHR misses
2801system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9298 # number of overall MSHR misses
2802system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 623286 # number of overall MSHR misses
2803system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1301279 # number of overall MSHR misses
2804system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 804888 # number of overall MSHR misses
2805system.cpu1.l2cache.overall_mshr_misses::total 2751537 # number of overall MSHR misses
2806system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
2807system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 16935 # number of ReadReq MSHR uncacheable
2808system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 17002 # number of ReadReq MSHR uncacheable
2809system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 14896 # number of WriteReq MSHR uncacheable
2810system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 14896 # number of WriteReq MSHR uncacheable
2811system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
2812system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 31831 # number of overall MSHR uncacheable misses
2813system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 31898 # number of overall MSHR uncacheable misses
2814system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 436116500 # number of ReadReq MSHR miss cycles
2815system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 365754500 # number of ReadReq MSHR miss cycles
2816system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 801871000 # number of ReadReq MSHR miss cycles
2817system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 50468745441 # number of HardPFReq MSHR miss cycles
2818system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 50468745441 # number of HardPFReq MSHR miss cycles
2819system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2875133996 # number of UpgradeReq MSHR miss cycles
2820system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2875133996 # number of UpgradeReq MSHR miss cycles
2821system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2601766497 # number of SCUpgradeReq MSHR miss cycles
2822system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2601766497 # number of SCUpgradeReq MSHR miss cycles
2823system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2804499 # number of SCUpgradeFailReq MSHR miss cycles
2824system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2804499 # number of SCUpgradeFailReq MSHR miss cycles
2825system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9250303496 # number of ReadExReq MSHR miss cycles
2826system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9250303496 # number of ReadExReq MSHR miss cycles
2827system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 13937951500 # number of ReadCleanReq MSHR miss cycles
2828system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 13937951500 # number of ReadCleanReq MSHR miss cycles
2829system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 28711604984 # number of ReadSharedReq MSHR miss cycles
2830system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 28711604984 # number of ReadSharedReq MSHR miss cycles
2831system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 16314942498 # number of InvalidateReq MSHR miss cycles
2832system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 16314942498 # number of InvalidateReq MSHR miss cycles
2833system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 436116500 # number of demand (read+write) MSHR miss cycles
2834system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 365754500 # number of demand (read+write) MSHR miss cycles
2835system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 13937951500 # number of demand (read+write) MSHR miss cycles
2836system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 37961908480 # number of demand (read+write) MSHR miss cycles
2837system.cpu1.l2cache.demand_mshr_miss_latency::total 52701730980 # number of demand (read+write) MSHR miss cycles
2838system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 436116500 # number of overall MSHR miss cycles
2839system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 365754500 # number of overall MSHR miss cycles
2840system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 13937951500 # number of overall MSHR miss cycles
2841system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 37961908480 # number of overall MSHR miss cycles
2842system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 50468745441 # number of overall MSHR miss cycles
2843system.cpu1.l2cache.overall_mshr_miss_latency::total 103170476421 # number of overall MSHR miss cycles
2844system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5288500 # number of ReadReq MSHR uncacheable cycles
2845system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2468909500 # number of ReadReq MSHR uncacheable cycles
2846system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2474198000 # number of ReadReq MSHR uncacheable cycles
2847system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2188801500 # number of WriteReq MSHR uncacheable cycles
2848system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2188801500 # number of WriteReq MSHR uncacheable cycles
2849system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 5288500 # number of overall MSHR uncacheable cycles
2850system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 4657711000 # number of overall MSHR uncacheable cycles
2851system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 4662999500 # number of overall MSHR uncacheable cycles
2852system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021107 # mshr miss rate for ReadReq accesses
2853system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.047593 # mshr miss rate for ReadReq accesses
2854system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027566 # mshr miss rate for ReadReq accesses
2855system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000005 # mshr miss rate for Writeback accesses
2856system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000005 # mshr miss rate for Writeback accesses
2857system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
2858system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
2859system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2860system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2861system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.634120 # mshr miss rate for UpgradeReq accesses
2862system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.634120 # mshr miss rate for UpgradeReq accesses
2863system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.827681 # mshr miss rate for SCUpgradeReq accesses
2864system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.827681 # mshr miss rate for SCUpgradeReq accesses
2865system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2866system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2867system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.197282 # mshr miss rate for ReadExReq accesses
2868system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.197282 # mshr miss rate for ReadExReq accesses
2869system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.115328 # mshr miss rate for ReadCleanReq accesses
2870system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.115328 # mshr miss rate for ReadCleanReq accesses
2871system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.267084 # mshr miss rate for ReadSharedReq accesses
2872system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.267084 # mshr miss rate for ReadSharedReq accesses
2873system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.637589 # mshr miss rate for InvalidateReq accesses
2874system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.637589 # mshr miss rate for InvalidateReq accesses
2875system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021107 # mshr miss rate for demand accesses
2876system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.047593 # mshr miss rate for demand accesses
2877system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.115328 # mshr miss rate for demand accesses
2878system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.250766 # mshr miss rate for demand accesses
2879system.cpu1.l2cache.demand_mshr_miss_rate::total 0.170837 # mshr miss rate for demand accesses
2880system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021107 # mshr miss rate for overall accesses
2881system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.047593 # mshr miss rate for overall accesses
2882system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.115328 # mshr miss rate for overall accesses
2883system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.250766 # mshr miss rate for overall accesses
2884system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2885system.cpu1.l2cache.overall_mshr_miss_rate::total 0.241473 # mshr miss rate for overall accesses
2886system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 34108.908181 # average ReadReq mshr miss latency
2887system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 39336.900409 # average ReadReq mshr miss latency
2888system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 36310.043470 # average ReadReq mshr miss latency
2889system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62702.817586 # average HardPFReq mshr miss latency
2890system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 62702.817586 # average HardPFReq mshr miss latency
2891system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19926.217494 # average UpgradeReq mshr miss latency
2892system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19926.217494 # average UpgradeReq mshr miss latency
2893system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15072.044681 # average SCUpgradeReq mshr miss latency
2894system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15072.044681 # average SCUpgradeReq mshr miss latency
2895system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 560899.800000 # average SCUpgradeFailReq mshr miss latency
2896system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 560899.800000 # average SCUpgradeFailReq mshr miss latency
2897system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 38652.446498 # average ReadExReq mshr miss latency
2898system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 38652.446498 # average ReadExReq mshr miss latency
2899system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 22362.048081 # average ReadCleanReq mshr miss latency
2900system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 22362.048081 # average ReadCleanReq mshr miss latency
2901system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 27036.453370 # average ReadSharedReq mshr miss latency
2902system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27036.453370 # average ReadSharedReq mshr miss latency
2903system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 63037.326026 # average InvalidateReq mshr miss latency
2904system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 63037.326026 # average InvalidateReq mshr miss latency
2905system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 34108.908181 # average overall mshr miss latency
2906system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 39336.900409 # average overall mshr miss latency
2907system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22362.048081 # average overall mshr miss latency
2908system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29172.766547 # average overall mshr miss latency
2909system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27073.052707 # average overall mshr miss latency
2910system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 34108.908181 # average overall mshr miss latency
2911system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 39336.900409 # average overall mshr miss latency
2912system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22362.048081 # average overall mshr miss latency
2913system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29172.766547 # average overall mshr miss latency
2914system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62702.817586 # average overall mshr miss latency
2915system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37495.580260 # average overall mshr miss latency
2916system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78932.835821 # average ReadReq mshr uncacheable latency
2917system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 145787.392973 # average ReadReq mshr uncacheable latency
2918system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 145523.938360 # average ReadReq mshr uncacheable latency
2919system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146938.876208 # average WriteReq mshr uncacheable latency
2920system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 146938.876208 # average WriteReq mshr uncacheable latency
2921system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78932.835821 # average overall mshr uncacheable latency
2922system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 146326.254280 # average overall mshr uncacheable latency
2923system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 146184.698100 # average overall mshr uncacheable latency
2924system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2925system.cpu1.toL2Bus.trans_dist::ReadReq 997626 # Transaction distribution
2926system.cpu1.toL2Bus.trans_dist::ReadResp 10426628 # Transaction distribution
2927system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
2928system.cpu1.toL2Bus.trans_dist::WriteReq 38204 # Transaction distribution
2929system.cpu1.toL2Bus.trans_dist::WriteResp 14896 # Transaction distribution
2930system.cpu1.toL2Bus.trans_dist::Writeback 7712009 # Transaction distribution
2931system.cpu1.toL2Bus.trans_dist::CleanEvict 10305258 # Transaction distribution
2932system.cpu1.toL2Bus.trans_dist::HardPFReq 1022601 # Transaction distribution
2933system.cpu1.toL2Bus.trans_dist::HardPFResp 10 # Transaction distribution
2934system.cpu1.toL2Bus.trans_dist::UpgradeReq 482744 # Transaction distribution
2935system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 380034 # Transaction distribution
2936system.cpu1.toL2Bus.trans_dist::UpgradeResp 500528 # Transaction distribution
2937system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 70 # Transaction distribution
2938system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 136 # Transaction distribution
2939system.cpu1.toL2Bus.trans_dist::ReadExReq 1988029 # Transaction distribution
2940system.cpu1.toL2Bus.trans_dist::ReadExResp 1220428 # Transaction distribution
2941system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5404468 # Transaction distribution
2942system.cpu1.toL2Bus.trans_dist::ReadSharedReq 6543941 # Transaction distribution
2943system.cpu1.toL2Bus.trans_dist::InvalidateReq 512654 # Transaction distribution
2944system.cpu1.toL2Bus.trans_dist::InvalidateResp 405926 # Transaction distribution
2945system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16212466 # Packet count per connected master and slave (bytes)
2946system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17789160 # Packet count per connected master and slave (bytes)
2947system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 422162 # Packet count per connected master and slave (bytes)
2948system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1316947 # Packet count per connected master and slave (bytes)
2949system.cpu1.toL2Bus.pkt_count::total 35740735 # Packet count per connected master and slave (bytes)
2950system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 345886640 # Cumulative packet size per connected master and slave (bytes)
2951system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 566771243 # Cumulative packet size per connected master and slave (bytes)
2952system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1562912 # Cumulative packet size per connected master and slave (bytes)
2953system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4846136 # Cumulative packet size per connected master and slave (bytes)
2954system.cpu1.toL2Bus.pkt_size::total 919066931 # Cumulative packet size per connected master and slave (bytes)
2955system.cpu1.toL2Bus.snoops 12378423 # Total snoops (count)
2956system.cpu1.toL2Bus.snoop_fanout::samples 35388761 # Request fanout histogram
2957system.cpu1.toL2Bus.snoop_fanout::mean 1.367817 # Request fanout histogram
2958system.cpu1.toL2Bus.snoop_fanout::stdev 0.482211 # Request fanout histogram
2959system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2960system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2961system.cpu1.toL2Bus.snoop_fanout::1 22372180 63.22% 63.22% # Request fanout histogram
2962system.cpu1.toL2Bus.snoop_fanout::2 13016581 36.78% 100.00% # Request fanout histogram
2963system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2964system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
2965system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2966system.cpu1.toL2Bus.snoop_fanout::total 35388761 # Request fanout histogram
2967system.cpu1.toL2Bus.reqLayer0.occupancy 15228808958 # Layer occupancy (ticks)
2968system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2969system.cpu1.toL2Bus.snoopLayer0.occupancy 179948989 # Layer occupancy (ticks)
2970system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2971system.cpu1.toL2Bus.respLayer0.occupancy 8110869278 # Layer occupancy (ticks)
2972system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2973system.cpu1.toL2Bus.respLayer1.occupancy 8234240098 # Layer occupancy (ticks)
2974system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2975system.cpu1.toL2Bus.respLayer2.occupancy 227095399 # Layer occupancy (ticks)
2976system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2977system.cpu1.toL2Bus.respLayer3.occupancy 711723893 # Layer occupancy (ticks)
2978system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2979system.iobus.trans_dist::ReadReq 40342 # Transaction distribution
2980system.iobus.trans_dist::ReadResp 40342 # Transaction distribution
2981system.iobus.trans_dist::WriteReq 136642 # Transaction distribution
2982system.iobus.trans_dist::WriteResp 136642 # Transaction distribution
2983system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47708 # Packet count per connected master and slave (bytes)
2984system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2985system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2986system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2987system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2988system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2989system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2990system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2991system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2992system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2993system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
2994system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
2995system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2996system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
2997system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
2998system.iobus.pkt_count_system.bridge.master::total 122642 # Packet count per connected master and slave (bytes)
2999system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231246 # Packet count per connected master and slave (bytes)
3000system.iobus.pkt_count_system.realview.ide.dma::total 231246 # Packet count per connected master and slave (bytes)
3001system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
3002system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
3003system.iobus.pkt_count::total 353968 # Packet count per connected master and slave (bytes)
3004system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47728 # Cumulative packet size per connected master and slave (bytes)
3005system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
3006system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
3007system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
3008system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
3009system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
3010system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
3011system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
3012system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
3013system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
3014system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
3015system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
3016system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
3017system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
3018system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
3019system.iobus.pkt_size_system.bridge.master::total 155749 # Cumulative packet size per connected master and slave (bytes)
3020system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339000 # Cumulative packet size per connected master and slave (bytes)
3021system.iobus.pkt_size_system.realview.ide.dma::total 7339000 # Cumulative packet size per connected master and slave (bytes)
3022system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
3023system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
3024system.iobus.pkt_size::total 7496835 # Cumulative packet size per connected master and slave (bytes)
3025system.iobus.reqLayer0.occupancy 36238000 # Layer occupancy (ticks)
3026system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
3027system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
3028system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
3029system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
3030system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
3031system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
3032system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
3033system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)

--- 11 unchanged lines hidden (view full) ---

3045system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks)
3046system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
3047system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
3048system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
3049system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
3050system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
3051system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
3052system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
3053system.iobus.reqLayer27.occupancy 569545477 # Layer occupancy (ticks)
3054system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
3055system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
3056system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
3057system.iobus.respLayer0.occupancy 92731000 # Layer occupancy (ticks)
3058system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
3059system.iobus.respLayer3.occupancy 147942000 # Layer occupancy (ticks)
3060system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
3061system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
3062system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
3063system.iocache.tags.replacements 115612 # number of replacements
3064system.iocache.tags.tagsinuse 11.307418 # Cycle average of tags in use
3065system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
3066system.iocache.tags.sampled_refs 115628 # Sample count of references to valid blocks.
3067system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
3068system.iocache.tags.warmup_cycle 9081354759000 # Cycle when the warmup percentage was hit.
3069system.iocache.tags.occ_blocks::realview.ethernet 3.848836 # Average occupied blocks per requestor
3070system.iocache.tags.occ_blocks::realview.ide 7.458583 # Average occupied blocks per requestor
3071system.iocache.tags.occ_percent::realview.ethernet 0.240552 # Average percentage of cache occupancy
3072system.iocache.tags.occ_percent::realview.ide 0.466161 # Average percentage of cache occupancy
3073system.iocache.tags.occ_percent::total 0.706714 # Average percentage of cache occupancy
3074system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
3075system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
3076system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
3077system.iocache.tags.tag_accesses 1040964 # Number of tag accesses
3078system.iocache.tags.data_accesses 1040964 # Number of data accesses
3079system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
3080system.iocache.ReadReq_misses::realview.ide 8895 # number of ReadReq misses
3081system.iocache.ReadReq_misses::total 8932 # number of ReadReq misses
3082system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
3083system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
3084system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
3085system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
3086system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
3087system.iocache.demand_misses::realview.ide 8895 # number of demand (read+write) misses
3088system.iocache.demand_misses::total 8935 # number of demand (read+write) misses
3089system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
3090system.iocache.overall_misses::realview.ide 8895 # number of overall misses
3091system.iocache.overall_misses::total 8935 # number of overall misses
3092system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles
3093system.iocache.ReadReq_miss_latency::realview.ide 1662593136 # number of ReadReq miss cycles
3094system.iocache.ReadReq_miss_latency::total 1667788136 # number of ReadReq miss cycles
3095system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
3096system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
3097system.iocache.WriteLineReq_miss_latency::realview.ide 12635360341 # number of WriteLineReq miss cycles
3098system.iocache.WriteLineReq_miss_latency::total 12635360341 # number of WriteLineReq miss cycles
3099system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles
3100system.iocache.demand_miss_latency::realview.ide 1662593136 # number of demand (read+write) miss cycles
3101system.iocache.demand_miss_latency::total 1668157136 # number of demand (read+write) miss cycles
3102system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles
3103system.iocache.overall_miss_latency::realview.ide 1662593136 # number of overall miss cycles
3104system.iocache.overall_miss_latency::total 1668157136 # number of overall miss cycles
3105system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
3106system.iocache.ReadReq_accesses::realview.ide 8895 # number of ReadReq accesses(hits+misses)
3107system.iocache.ReadReq_accesses::total 8932 # number of ReadReq accesses(hits+misses)
3108system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
3109system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
3110system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
3111system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
3112system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
3113system.iocache.demand_accesses::realview.ide 8895 # number of demand (read+write) accesses
3114system.iocache.demand_accesses::total 8935 # number of demand (read+write) accesses
3115system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
3116system.iocache.overall_accesses::realview.ide 8895 # number of overall (read+write) accesses
3117system.iocache.overall_accesses::total 8935 # number of overall (read+write) accesses
3118system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
3119system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
3120system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
3121system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
3122system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
3123system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
3124system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
3125system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
3126system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
3127system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
3128system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
3129system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
3130system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
3131system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency
3132system.iocache.ReadReq_avg_miss_latency::realview.ide 186913.224958 # average ReadReq miss latency
3133system.iocache.ReadReq_avg_miss_latency::total 186720.570533 # average ReadReq miss latency
3134system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
3135system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
3136system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118388.429850 # average WriteLineReq miss latency
3137system.iocache.WriteLineReq_avg_miss_latency::total 118388.429850 # average WriteLineReq miss latency
3138system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency
3139system.iocache.demand_avg_miss_latency::realview.ide 186913.224958 # average overall miss latency
3140system.iocache.demand_avg_miss_latency::total 186699.175825 # average overall miss latency
3141system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency
3142system.iocache.overall_avg_miss_latency::realview.ide 186913.224958 # average overall miss latency
3143system.iocache.overall_avg_miss_latency::total 186699.175825 # average overall miss latency
3144system.iocache.blocked_cycles::no_mshrs 32654 # number of cycles access was blocked
3145system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
3146system.iocache.blocked::no_mshrs 3383 # number of cycles access was blocked
3147system.iocache.blocked::no_targets 0 # number of cycles access was blocked
3148system.iocache.avg_blocked_cycles::no_mshrs 9.652380 # average number of cycles each access was blocked
3149system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3150system.iocache.fast_writes 0 # number of fast writes performed
3151system.iocache.cache_copies 0 # number of cache copies performed
3152system.iocache.writebacks::writebacks 106702 # number of writebacks
3153system.iocache.writebacks::total 106702 # number of writebacks
3154system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
3155system.iocache.ReadReq_mshr_misses::realview.ide 8895 # number of ReadReq MSHR misses
3156system.iocache.ReadReq_mshr_misses::total 8932 # number of ReadReq MSHR misses
3157system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
3158system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
3159system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
3160system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
3161system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
3162system.iocache.demand_mshr_misses::realview.ide 8895 # number of demand (read+write) MSHR misses
3163system.iocache.demand_mshr_misses::total 8935 # number of demand (read+write) MSHR misses
3164system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
3165system.iocache.overall_mshr_misses::realview.ide 8895 # number of overall MSHR misses
3166system.iocache.overall_mshr_misses::total 8935 # number of overall MSHR misses
3167system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles
3168system.iocache.ReadReq_mshr_miss_latency::realview.ide 1217843136 # number of ReadReq MSHR miss cycles
3169system.iocache.ReadReq_mshr_miss_latency::total 1221188136 # number of ReadReq MSHR miss cycles
3170system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
3171system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
3172system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7298960341 # number of WriteLineReq MSHR miss cycles
3173system.iocache.WriteLineReq_mshr_miss_latency::total 7298960341 # number of WriteLineReq MSHR miss cycles
3174system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles
3175system.iocache.demand_mshr_miss_latency::realview.ide 1217843136 # number of demand (read+write) MSHR miss cycles
3176system.iocache.demand_mshr_miss_latency::total 1221407136 # number of demand (read+write) MSHR miss cycles
3177system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles
3178system.iocache.overall_mshr_miss_latency::realview.ide 1217843136 # number of overall MSHR miss cycles
3179system.iocache.overall_mshr_miss_latency::total 1221407136 # number of overall MSHR miss cycles
3180system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
3181system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
3182system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
3183system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
3184system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
3185system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
3186system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
3187system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
3188system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
3189system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
3190system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
3191system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
3192system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
3193system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency
3194system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136913.224958 # average ReadReq mshr miss latency
3195system.iocache.ReadReq_avg_mshr_miss_latency::total 136720.570533 # average ReadReq mshr miss latency
3196system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
3197system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
3198system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68388.429850 # average WriteLineReq mshr miss latency
3199system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68388.429850 # average WriteLineReq mshr miss latency
3200system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency
3201system.iocache.demand_avg_mshr_miss_latency::realview.ide 136913.224958 # average overall mshr miss latency
3202system.iocache.demand_avg_mshr_miss_latency::total 136699.175825 # average overall mshr miss latency
3203system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency
3204system.iocache.overall_avg_mshr_miss_latency::realview.ide 136913.224958 # average overall mshr miss latency
3205system.iocache.overall_avg_mshr_miss_latency::total 136699.175825 # average overall mshr miss latency
3206system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
3207system.l2c.tags.replacements 1760747 # number of replacements
3208system.l2c.tags.tagsinuse 63871.601453 # Cycle average of tags in use
3209system.l2c.tags.total_refs 6095006 # Total number of references to valid blocks.
3210system.l2c.tags.sampled_refs 1821172 # Sample count of references to valid blocks.
3211system.l2c.tags.avg_refs 3.346749 # Average number of references to valid blocks.
3212system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
3213system.l2c.tags.occ_blocks::writebacks 18326.572985 # Average occupied blocks per requestor
3214system.l2c.tags.occ_blocks::cpu0.dtb.walker 182.034797 # Average occupied blocks per requestor
3215system.l2c.tags.occ_blocks::cpu0.itb.walker 268.280441 # Average occupied blocks per requestor
3216system.l2c.tags.occ_blocks::cpu0.inst 4619.393037 # Average occupied blocks per requestor
3217system.l2c.tags.occ_blocks::cpu0.data 9002.087865 # Average occupied blocks per requestor
3218system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11374.868707 # Average occupied blocks per requestor
3219system.l2c.tags.occ_blocks::cpu1.dtb.walker 179.474155 # Average occupied blocks per requestor
3220system.l2c.tags.occ_blocks::cpu1.itb.walker 242.215899 # Average occupied blocks per requestor
3221system.l2c.tags.occ_blocks::cpu1.inst 2745.232497 # Average occupied blocks per requestor
3222system.l2c.tags.occ_blocks::cpu1.data 8268.941513 # Average occupied blocks per requestor
3223system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8662.499555 # Average occupied blocks per requestor
3224system.l2c.tags.occ_percent::writebacks 0.279641 # Average percentage of cache occupancy
3225system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002778 # Average percentage of cache occupancy
3226system.l2c.tags.occ_percent::cpu0.itb.walker 0.004094 # Average percentage of cache occupancy
3227system.l2c.tags.occ_percent::cpu0.inst 0.070486 # Average percentage of cache occupancy
3228system.l2c.tags.occ_percent::cpu0.data 0.137361 # Average percentage of cache occupancy
3229system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.173567 # Average percentage of cache occupancy
3230system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002739 # Average percentage of cache occupancy
3231system.l2c.tags.occ_percent::cpu1.itb.walker 0.003696 # Average percentage of cache occupancy
3232system.l2c.tags.occ_percent::cpu1.inst 0.041889 # Average percentage of cache occupancy
3233system.l2c.tags.occ_percent::cpu1.data 0.126174 # Average percentage of cache occupancy
3234system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.132179 # Average percentage of cache occupancy
3235system.l2c.tags.occ_percent::total 0.974603 # Average percentage of cache occupancy
3236system.l2c.tags.occ_task_id_blocks::1022 11384 # Occupied blocks per task id
3237system.l2c.tags.occ_task_id_blocks::1023 237 # Occupied blocks per task id
3238system.l2c.tags.occ_task_id_blocks::1024 48804 # Occupied blocks per task id
3239system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
3240system.l2c.tags.age_task_id_blocks_1022::2 1357 # Occupied blocks per task id
3241system.l2c.tags.age_task_id_blocks_1022::3 826 # Occupied blocks per task id
3242system.l2c.tags.age_task_id_blocks_1022::4 9193 # Occupied blocks per task id
3243system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id
3244system.l2c.tags.age_task_id_blocks_1023::4 233 # Occupied blocks per task id
3245system.l2c.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
3246system.l2c.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id
3247system.l2c.tags.age_task_id_blocks_1024::2 2623 # Occupied blocks per task id
3248system.l2c.tags.age_task_id_blocks_1024::3 5288 # Occupied blocks per task id
3249system.l2c.tags.age_task_id_blocks_1024::4 40501 # Occupied blocks per task id
3250system.l2c.tags.occ_task_id_percent::1022 0.173706 # Percentage of cache occupancy per task id
3251system.l2c.tags.occ_task_id_percent::1023 0.003616 # Percentage of cache occupancy per task id
3252system.l2c.tags.occ_task_id_percent::1024 0.744690 # Percentage of cache occupancy per task id
3253system.l2c.tags.tag_accesses 76795315 # Number of tag accesses
3254system.l2c.tags.data_accesses 76795315 # Number of data accesses
3255system.l2c.Writeback_hits::writebacks 2680735 # number of Writeback hits
3256system.l2c.Writeback_hits::total 2680735 # number of Writeback hits
3257system.l2c.UpgradeReq_hits::cpu0.data 32943 # number of UpgradeReq hits
3258system.l2c.UpgradeReq_hits::cpu1.data 31048 # number of UpgradeReq hits
3259system.l2c.UpgradeReq_hits::total 63991 # number of UpgradeReq hits
3260system.l2c.SCUpgradeReq_hits::cpu0.data 6336 # number of SCUpgradeReq hits
3261system.l2c.SCUpgradeReq_hits::cpu1.data 5767 # number of SCUpgradeReq hits
3262system.l2c.SCUpgradeReq_hits::total 12103 # number of SCUpgradeReq hits
3263system.l2c.ReadExReq_hits::cpu0.data 174506 # number of ReadExReq hits
3264system.l2c.ReadExReq_hits::cpu1.data 154775 # number of ReadExReq hits
3265system.l2c.ReadExReq_hits::total 329281 # number of ReadExReq hits
3266system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6806 # number of ReadSharedReq hits
3267system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4586 # number of ReadSharedReq hits
3268system.l2c.ReadSharedReq_hits::cpu0.inst 614111 # number of ReadSharedReq hits
3269system.l2c.ReadSharedReq_hits::cpu0.data 638498 # number of ReadSharedReq hits
3270system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 286433 # number of ReadSharedReq hits
3271system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6534 # number of ReadSharedReq hits
3272system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4346 # number of ReadSharedReq hits
3273system.l2c.ReadSharedReq_hits::cpu1.inst 583459 # number of ReadSharedReq hits
3274system.l2c.ReadSharedReq_hits::cpu1.data 618336 # number of ReadSharedReq hits
3275system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 287570 # number of ReadSharedReq hits
3276system.l2c.ReadSharedReq_hits::total 3050679 # number of ReadSharedReq hits
3277system.l2c.demand_hits::cpu0.dtb.walker 6806 # number of demand (read+write) hits
3278system.l2c.demand_hits::cpu0.itb.walker 4586 # number of demand (read+write) hits
3279system.l2c.demand_hits::cpu0.inst 614111 # number of demand (read+write) hits
3280system.l2c.demand_hits::cpu0.data 813004 # number of demand (read+write) hits
3281system.l2c.demand_hits::cpu0.l2cache.prefetcher 286433 # number of demand (read+write) hits
3282system.l2c.demand_hits::cpu1.dtb.walker 6534 # number of demand (read+write) hits
3283system.l2c.demand_hits::cpu1.itb.walker 4346 # number of demand (read+write) hits
3284system.l2c.demand_hits::cpu1.inst 583459 # number of demand (read+write) hits
3285system.l2c.demand_hits::cpu1.data 773111 # number of demand (read+write) hits
3286system.l2c.demand_hits::cpu1.l2cache.prefetcher 287570 # number of demand (read+write) hits
3287system.l2c.demand_hits::total 3379960 # number of demand (read+write) hits
3288system.l2c.overall_hits::cpu0.dtb.walker 6806 # number of overall hits
3289system.l2c.overall_hits::cpu0.itb.walker 4586 # number of overall hits
3290system.l2c.overall_hits::cpu0.inst 614111 # number of overall hits
3291system.l2c.overall_hits::cpu0.data 813004 # number of overall hits
3292system.l2c.overall_hits::cpu0.l2cache.prefetcher 286433 # number of overall hits
3293system.l2c.overall_hits::cpu1.dtb.walker 6534 # number of overall hits
3294system.l2c.overall_hits::cpu1.itb.walker 4346 # number of overall hits
3295system.l2c.overall_hits::cpu1.inst 583459 # number of overall hits
3296system.l2c.overall_hits::cpu1.data 773111 # number of overall hits
3297system.l2c.overall_hits::cpu1.l2cache.prefetcher 287570 # number of overall hits
3298system.l2c.overall_hits::total 3379960 # number of overall hits
3299system.l2c.UpgradeReq_misses::cpu0.data 48112 # number of UpgradeReq misses
3300system.l2c.UpgradeReq_misses::cpu1.data 44467 # number of UpgradeReq misses
3301system.l2c.UpgradeReq_misses::total 92579 # number of UpgradeReq misses
3302system.l2c.SCUpgradeReq_misses::cpu0.data 10023 # number of SCUpgradeReq misses
3303system.l2c.SCUpgradeReq_misses::cpu1.data 8706 # number of SCUpgradeReq misses
3304system.l2c.SCUpgradeReq_misses::total 18729 # number of SCUpgradeReq misses
3305system.l2c.ReadExReq_misses::cpu0.data 523780 # number of ReadExReq misses
3306system.l2c.ReadExReq_misses::cpu1.data 170521 # number of ReadExReq misses
3307system.l2c.ReadExReq_misses::total 694301 # number of ReadExReq misses
3308system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2882 # number of ReadSharedReq misses
3309system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2624 # number of ReadSharedReq misses
3310system.l2c.ReadSharedReq_misses::cpu0.inst 74362 # number of ReadSharedReq misses
3311system.l2c.ReadSharedReq_misses::cpu0.data 179746 # number of ReadSharedReq misses
3312system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 302363 # number of ReadSharedReq misses
3313system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2755 # number of ReadSharedReq misses
3314system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2528 # number of ReadSharedReq misses
3315system.l2c.ReadSharedReq_misses::cpu1.inst 39827 # number of ReadSharedReq misses
3316system.l2c.ReadSharedReq_misses::cpu1.data 128012 # number of ReadSharedReq misses
3317system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 323843 # number of ReadSharedReq misses
3318system.l2c.ReadSharedReq_misses::total 1058942 # number of ReadSharedReq misses
3319system.l2c.demand_misses::cpu0.dtb.walker 2882 # number of demand (read+write) misses
3320system.l2c.demand_misses::cpu0.itb.walker 2624 # number of demand (read+write) misses
3321system.l2c.demand_misses::cpu0.inst 74362 # number of demand (read+write) misses
3322system.l2c.demand_misses::cpu0.data 703526 # number of demand (read+write) misses
3323system.l2c.demand_misses::cpu0.l2cache.prefetcher 302363 # number of demand (read+write) misses
3324system.l2c.demand_misses::cpu1.dtb.walker 2755 # number of demand (read+write) misses
3325system.l2c.demand_misses::cpu1.itb.walker 2528 # number of demand (read+write) misses
3326system.l2c.demand_misses::cpu1.inst 39827 # number of demand (read+write) misses
3327system.l2c.demand_misses::cpu1.data 298533 # number of demand (read+write) misses
3328system.l2c.demand_misses::cpu1.l2cache.prefetcher 323843 # number of demand (read+write) misses
3329system.l2c.demand_misses::total 1753243 # number of demand (read+write) misses
3330system.l2c.overall_misses::cpu0.dtb.walker 2882 # number of overall misses
3331system.l2c.overall_misses::cpu0.itb.walker 2624 # number of overall misses
3332system.l2c.overall_misses::cpu0.inst 74362 # number of overall misses
3333system.l2c.overall_misses::cpu0.data 703526 # number of overall misses
3334system.l2c.overall_misses::cpu0.l2cache.prefetcher 302363 # number of overall misses
3335system.l2c.overall_misses::cpu1.dtb.walker 2755 # number of overall misses
3336system.l2c.overall_misses::cpu1.itb.walker 2528 # number of overall misses
3337system.l2c.overall_misses::cpu1.inst 39827 # number of overall misses
3338system.l2c.overall_misses::cpu1.data 298533 # number of overall misses
3339system.l2c.overall_misses::cpu1.l2cache.prefetcher 323843 # number of overall misses
3340system.l2c.overall_misses::total 1753243 # number of overall misses
3341system.l2c.UpgradeReq_miss_latency::cpu0.data 280230500 # number of UpgradeReq miss cycles
3342system.l2c.UpgradeReq_miss_latency::cpu1.data 263754000 # number of UpgradeReq miss cycles
3343system.l2c.UpgradeReq_miss_latency::total 543984500 # number of UpgradeReq miss cycles
3344system.l2c.SCUpgradeReq_miss_latency::cpu0.data 55711000 # number of SCUpgradeReq miss cycles
3345system.l2c.SCUpgradeReq_miss_latency::cpu1.data 50228500 # number of SCUpgradeReq miss cycles
3346system.l2c.SCUpgradeReq_miss_latency::total 105939500 # number of SCUpgradeReq miss cycles
3347system.l2c.ReadExReq_miss_latency::cpu0.data 68581440500 # number of ReadExReq miss cycles
3348system.l2c.ReadExReq_miss_latency::cpu1.data 18910817992 # number of ReadExReq miss cycles
3349system.l2c.ReadExReq_miss_latency::total 87492258492 # number of ReadExReq miss cycles
3350system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 268423000 # number of ReadSharedReq miss cycles
3351system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 251208500 # number of ReadSharedReq miss cycles
3352system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6463422502 # number of ReadSharedReq miss cycles
3353system.l2c.ReadSharedReq_miss_latency::cpu0.data 17884384500 # number of ReadSharedReq miss cycles
3354system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 42388472929 # number of ReadSharedReq miss cycles
3355system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 254889500 # number of ReadSharedReq miss cycles
3356system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 239052000 # number of ReadSharedReq miss cycles
3357system.l2c.ReadSharedReq_miss_latency::cpu1.inst 3438315000 # number of ReadSharedReq miss cycles
3358system.l2c.ReadSharedReq_miss_latency::cpu1.data 12527996000 # number of ReadSharedReq miss cycles
3359system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 45486797416 # number of ReadSharedReq miss cycles
3360system.l2c.ReadSharedReq_miss_latency::total 129202961347 # number of ReadSharedReq miss cycles
3361system.l2c.demand_miss_latency::cpu0.dtb.walker 268423000 # number of demand (read+write) miss cycles
3362system.l2c.demand_miss_latency::cpu0.itb.walker 251208500 # number of demand (read+write) miss cycles
3363system.l2c.demand_miss_latency::cpu0.inst 6463422502 # number of demand (read+write) miss cycles
3364system.l2c.demand_miss_latency::cpu0.data 86465825000 # number of demand (read+write) miss cycles
3365system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 42388472929 # number of demand (read+write) miss cycles
3366system.l2c.demand_miss_latency::cpu1.dtb.walker 254889500 # number of demand (read+write) miss cycles
3367system.l2c.demand_miss_latency::cpu1.itb.walker 239052000 # number of demand (read+write) miss cycles
3368system.l2c.demand_miss_latency::cpu1.inst 3438315000 # number of demand (read+write) miss cycles
3369system.l2c.demand_miss_latency::cpu1.data 31438813992 # number of demand (read+write) miss cycles
3370system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 45486797416 # number of demand (read+write) miss cycles
3371system.l2c.demand_miss_latency::total 216695219839 # number of demand (read+write) miss cycles
3372system.l2c.overall_miss_latency::cpu0.dtb.walker 268423000 # number of overall miss cycles
3373system.l2c.overall_miss_latency::cpu0.itb.walker 251208500 # number of overall miss cycles
3374system.l2c.overall_miss_latency::cpu0.inst 6463422502 # number of overall miss cycles
3375system.l2c.overall_miss_latency::cpu0.data 86465825000 # number of overall miss cycles
3376system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 42388472929 # number of overall miss cycles
3377system.l2c.overall_miss_latency::cpu1.dtb.walker 254889500 # number of overall miss cycles
3378system.l2c.overall_miss_latency::cpu1.itb.walker 239052000 # number of overall miss cycles
3379system.l2c.overall_miss_latency::cpu1.inst 3438315000 # number of overall miss cycles
3380system.l2c.overall_miss_latency::cpu1.data 31438813992 # number of overall miss cycles
3381system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 45486797416 # number of overall miss cycles
3382system.l2c.overall_miss_latency::total 216695219839 # number of overall miss cycles
3383system.l2c.Writeback_accesses::writebacks 2680735 # number of Writeback accesses(hits+misses)
3384system.l2c.Writeback_accesses::total 2680735 # number of Writeback accesses(hits+misses)
3385system.l2c.UpgradeReq_accesses::cpu0.data 81055 # number of UpgradeReq accesses(hits+misses)
3386system.l2c.UpgradeReq_accesses::cpu1.data 75515 # number of UpgradeReq accesses(hits+misses)
3387system.l2c.UpgradeReq_accesses::total 156570 # number of UpgradeReq accesses(hits+misses)
3388system.l2c.SCUpgradeReq_accesses::cpu0.data 16359 # number of SCUpgradeReq accesses(hits+misses)
3389system.l2c.SCUpgradeReq_accesses::cpu1.data 14473 # number of SCUpgradeReq accesses(hits+misses)
3390system.l2c.SCUpgradeReq_accesses::total 30832 # number of SCUpgradeReq accesses(hits+misses)
3391system.l2c.ReadExReq_accesses::cpu0.data 698286 # number of ReadExReq accesses(hits+misses)
3392system.l2c.ReadExReq_accesses::cpu1.data 325296 # number of ReadExReq accesses(hits+misses)
3393system.l2c.ReadExReq_accesses::total 1023582 # number of ReadExReq accesses(hits+misses)
3394system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 9688 # number of ReadSharedReq accesses(hits+misses)
3395system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7210 # number of ReadSharedReq accesses(hits+misses)
3396system.l2c.ReadSharedReq_accesses::cpu0.inst 688473 # number of ReadSharedReq accesses(hits+misses)
3397system.l2c.ReadSharedReq_accesses::cpu0.data 818244 # number of ReadSharedReq accesses(hits+misses)
3398system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 588796 # number of ReadSharedReq accesses(hits+misses)
3399system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9289 # number of ReadSharedReq accesses(hits+misses)
3400system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6874 # number of ReadSharedReq accesses(hits+misses)
3401system.l2c.ReadSharedReq_accesses::cpu1.inst 623286 # number of ReadSharedReq accesses(hits+misses)
3402system.l2c.ReadSharedReq_accesses::cpu1.data 746348 # number of ReadSharedReq accesses(hits+misses)
3403system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 611413 # number of ReadSharedReq accesses(hits+misses)
3404system.l2c.ReadSharedReq_accesses::total 4109621 # number of ReadSharedReq accesses(hits+misses)
3405system.l2c.demand_accesses::cpu0.dtb.walker 9688 # number of demand (read+write) accesses
3406system.l2c.demand_accesses::cpu0.itb.walker 7210 # number of demand (read+write) accesses
3407system.l2c.demand_accesses::cpu0.inst 688473 # number of demand (read+write) accesses
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3421system.l2c.overall_accesses::cpu1.dtb.walker 9289 # number of overall (read+write) accesses
3422system.l2c.overall_accesses::cpu1.itb.walker 6874 # number of overall (read+write) accesses
3423system.l2c.overall_accesses::cpu1.inst 623286 # number of overall (read+write) accesses
3424system.l2c.overall_accesses::cpu1.data 1071644 # number of overall (read+write) accesses
3425system.l2c.overall_accesses::cpu1.l2cache.prefetcher 611413 # number of overall (read+write) accesses
3426system.l2c.overall_accesses::total 5133203 # number of overall (read+write) accesses
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3428system.l2c.UpgradeReq_miss_rate::cpu1.data 0.588850 # miss rate for UpgradeReq accesses
3429system.l2c.UpgradeReq_miss_rate::total 0.591295 # miss rate for UpgradeReq accesses
3430system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.612690 # miss rate for SCUpgradeReq accesses
3431system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.601534 # miss rate for SCUpgradeReq accesses
3432system.l2c.SCUpgradeReq_miss_rate::total 0.607453 # miss rate for SCUpgradeReq accesses
3433system.l2c.ReadExReq_miss_rate::cpu0.data 0.750094 # miss rate for ReadExReq accesses
3434system.l2c.ReadExReq_miss_rate::cpu1.data 0.524203 # miss rate for ReadExReq accesses
3435system.l2c.ReadExReq_miss_rate::total 0.678305 # miss rate for ReadExReq accesses
3436system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.297481 # miss rate for ReadSharedReq accesses
3437system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.363939 # miss rate for ReadSharedReq accesses
3438system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.108010 # miss rate for ReadSharedReq accesses
3439system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.219673 # miss rate for ReadSharedReq accesses
3440system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.513528 # miss rate for ReadSharedReq accesses
3441system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.296587 # miss rate for ReadSharedReq accesses
3442system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.367763 # miss rate for ReadSharedReq accesses
3443system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.063898 # miss rate for ReadSharedReq accesses
3444system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.171518 # miss rate for ReadSharedReq accesses
3445system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.529663 # miss rate for ReadSharedReq accesses
3446system.l2c.ReadSharedReq_miss_rate::total 0.257674 # miss rate for ReadSharedReq accesses
3447system.l2c.demand_miss_rate::cpu0.dtb.walker 0.297481 # miss rate for demand accesses
3448system.l2c.demand_miss_rate::cpu0.itb.walker 0.363939 # miss rate for demand accesses
3449system.l2c.demand_miss_rate::cpu0.inst 0.108010 # miss rate for demand accesses
3450system.l2c.demand_miss_rate::cpu0.data 0.463905 # miss rate for demand accesses
3451system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.513528 # miss rate for demand accesses
3452system.l2c.demand_miss_rate::cpu1.dtb.walker 0.296587 # miss rate for demand accesses
3453system.l2c.demand_miss_rate::cpu1.itb.walker 0.367763 # miss rate for demand accesses
3454system.l2c.demand_miss_rate::cpu1.inst 0.063898 # miss rate for demand accesses
3455system.l2c.demand_miss_rate::cpu1.data 0.278575 # miss rate for demand accesses
3456system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.529663 # miss rate for demand accesses
3457system.l2c.demand_miss_rate::total 0.341550 # miss rate for demand accesses
3458system.l2c.overall_miss_rate::cpu0.dtb.walker 0.297481 # miss rate for overall accesses
3459system.l2c.overall_miss_rate::cpu0.itb.walker 0.363939 # miss rate for overall accesses
3460system.l2c.overall_miss_rate::cpu0.inst 0.108010 # miss rate for overall accesses
3461system.l2c.overall_miss_rate::cpu0.data 0.463905 # miss rate for overall accesses
3462system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.513528 # miss rate for overall accesses
3463system.l2c.overall_miss_rate::cpu1.dtb.walker 0.296587 # miss rate for overall accesses
3464system.l2c.overall_miss_rate::cpu1.itb.walker 0.367763 # miss rate for overall accesses
3465system.l2c.overall_miss_rate::cpu1.inst 0.063898 # miss rate for overall accesses
3466system.l2c.overall_miss_rate::cpu1.data 0.278575 # miss rate for overall accesses
3467system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.529663 # miss rate for overall accesses
3468system.l2c.overall_miss_rate::total 0.341550 # miss rate for overall accesses
3469system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5824.544812 # average UpgradeReq miss latency
3470system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5931.454787 # average UpgradeReq miss latency
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3472system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5558.315873 # average SCUpgradeReq miss latency
3473system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5769.411900 # average SCUpgradeReq miss latency
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3476system.l2c.ReadExReq_avg_miss_latency::cpu1.data 110900.229250 # average ReadExReq miss latency
3477system.l2c.ReadExReq_avg_miss_latency::total 126014.881862 # average ReadExReq miss latency
3478system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 93137.751561 # average ReadSharedReq miss latency
3479system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 95734.946646 # average ReadSharedReq miss latency
3480system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 86918.352142 # average ReadSharedReq miss latency
3481system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 99498.094533 # average ReadSharedReq miss latency
3482system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 140190.674550 # average ReadSharedReq miss latency
3483system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 92518.874773 # average ReadSharedReq miss latency
3484system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 94561.708861 # average ReadSharedReq miss latency
3485system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 86331.257690 # average ReadSharedReq miss latency
3486system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 97865.793832 # average ReadSharedReq miss latency
3487system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 140459.412172 # average ReadSharedReq miss latency
3488system.l2c.ReadSharedReq_avg_miss_latency::total 122011.367334 # average ReadSharedReq miss latency
3489system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 93137.751561 # average overall miss latency
3490system.l2c.demand_avg_miss_latency::cpu0.itb.walker 95734.946646 # average overall miss latency
3491system.l2c.demand_avg_miss_latency::cpu0.inst 86918.352142 # average overall miss latency
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3494system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92518.874773 # average overall miss latency
3495system.l2c.demand_avg_miss_latency::cpu1.itb.walker 94561.708861 # average overall miss latency
3496system.l2c.demand_avg_miss_latency::cpu1.inst 86331.257690 # average overall miss latency
3497system.l2c.demand_avg_miss_latency::cpu1.data 105311.017516 # average overall miss latency
3498system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 140459.412172 # average overall miss latency
3499system.l2c.demand_avg_miss_latency::total 123596.797386 # average overall miss latency
3500system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 93137.751561 # average overall miss latency
3501system.l2c.overall_avg_miss_latency::cpu0.itb.walker 95734.946646 # average overall miss latency
3502system.l2c.overall_avg_miss_latency::cpu0.inst 86918.352142 # average overall miss latency
3503system.l2c.overall_avg_miss_latency::cpu0.data 122903.524532 # average overall miss latency
3504system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 140190.674550 # average overall miss latency
3505system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92518.874773 # average overall miss latency
3506system.l2c.overall_avg_miss_latency::cpu1.itb.walker 94561.708861 # average overall miss latency
3507system.l2c.overall_avg_miss_latency::cpu1.inst 86331.257690 # average overall miss latency
3508system.l2c.overall_avg_miss_latency::cpu1.data 105311.017516 # average overall miss latency
3509system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 140459.412172 # average overall miss latency
3510system.l2c.overall_avg_miss_latency::total 123596.797386 # average overall miss latency
3511system.l2c.blocked_cycles::no_mshrs 12094 # number of cycles access was blocked
3512system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
3513system.l2c.blocked::no_mshrs 115 # number of cycles access was blocked
3514system.l2c.blocked::no_targets 0 # number of cycles access was blocked
3515system.l2c.avg_blocked_cycles::no_mshrs 105.165217 # average number of cycles each access was blocked
3516system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3517system.l2c.fast_writes 0 # number of fast writes performed
3518system.l2c.cache_copies 0 # number of cache copies performed
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3520system.l2c.writebacks::total 1358225 # number of writebacks
3521system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 229 # number of ReadSharedReq MSHR hits
3522system.l2c.ReadSharedReq_mshr_hits::cpu0.data 34 # number of ReadSharedReq MSHR hits
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3524system.l2c.ReadSharedReq_mshr_hits::cpu1.data 37 # number of ReadSharedReq MSHR hits
3525system.l2c.ReadSharedReq_mshr_hits::total 511 # number of ReadSharedReq MSHR hits
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3527system.l2c.demand_mshr_hits::cpu0.data 34 # number of demand (read+write) MSHR hits
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3529system.l2c.demand_mshr_hits::cpu1.data 37 # number of demand (read+write) MSHR hits
3530system.l2c.demand_mshr_hits::total 511 # number of demand (read+write) MSHR hits
3531system.l2c.overall_mshr_hits::cpu0.inst 229 # number of overall MSHR hits
3532system.l2c.overall_mshr_hits::cpu0.data 34 # number of overall MSHR hits
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3534system.l2c.overall_mshr_hits::cpu1.data 37 # number of overall MSHR hits
3535system.l2c.overall_mshr_hits::total 511 # number of overall MSHR hits
3536system.l2c.CleanEvict_mshr_misses::writebacks 57055 # number of CleanEvict MSHR misses
3537system.l2c.CleanEvict_mshr_misses::total 57055 # number of CleanEvict MSHR misses
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3626system.l2c.overall_mshr_miss_latency::cpu0.inst 5703318002 # number of overall MSHR miss cycles
3627system.l2c.overall_mshr_miss_latency::cpu0.data 79427605500 # number of overall MSHR miss cycles
3628system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 39364842929 # number of overall MSHR miss cycles
3629system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 227339500 # number of overall MSHR miss cycles
3630system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 213772000 # number of overall MSHR miss cycles
3631system.l2c.overall_mshr_miss_latency::cpu1.inst 3027081000 # number of overall MSHR miss cycles
3632system.l2c.overall_mshr_miss_latency::cpu1.data 28450102992 # number of overall MSHR miss cycles
3633system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 42248367416 # number of overall MSHR miss cycles
3634system.l2c.overall_mshr_miss_latency::total 199127000839 # number of overall MSHR miss cycles
3635system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1320748000 # number of ReadReq MSHR uncacheable cycles
3636system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3340995000 # number of ReadReq MSHR uncacheable cycles
3637system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4081500 # number of ReadReq MSHR uncacheable cycles
3638system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2164071000 # number of ReadReq MSHR uncacheable cycles
3639system.l2c.ReadReq_mshr_uncacheable_latency::total 6829895500 # number of ReadReq MSHR uncacheable cycles
3640system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3477095533 # number of WriteReq MSHR uncacheable cycles
3641system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1935550000 # number of WriteReq MSHR uncacheable cycles
3642system.l2c.WriteReq_mshr_uncacheable_latency::total 5412645533 # number of WriteReq MSHR uncacheable cycles
3643system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1320748000 # number of overall MSHR uncacheable cycles
3644system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6818090533 # number of overall MSHR uncacheable cycles
3645system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4081500 # number of overall MSHR uncacheable cycles
3646system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4099621000 # number of overall MSHR uncacheable cycles
3647system.l2c.overall_mshr_uncacheable_latency::total 12242541033 # number of overall MSHR uncacheable cycles
3648system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
3649system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
3650system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.593572 # mshr miss rate for UpgradeReq accesses
3651system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.588850 # mshr miss rate for UpgradeReq accesses
3652system.l2c.UpgradeReq_mshr_miss_rate::total 0.591295 # mshr miss rate for UpgradeReq accesses
3653system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.612690 # mshr miss rate for SCUpgradeReq accesses
3654system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.601534 # mshr miss rate for SCUpgradeReq accesses
3655system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.607453 # mshr miss rate for SCUpgradeReq accesses
3656system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.750094 # mshr miss rate for ReadExReq accesses
3657system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.524203 # mshr miss rate for ReadExReq accesses
3658system.l2c.ReadExReq_mshr_miss_rate::total 0.678305 # mshr miss rate for ReadExReq accesses
3659system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.297481 # mshr miss rate for ReadSharedReq accesses
3660system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.363939 # mshr miss rate for ReadSharedReq accesses
3661system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.107677 # mshr miss rate for ReadSharedReq accesses
3662system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.219631 # mshr miss rate for ReadSharedReq accesses
3663system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.513528 # mshr miss rate for ReadSharedReq accesses
3664system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.296587 # mshr miss rate for ReadSharedReq accesses
3665system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.367763 # mshr miss rate for ReadSharedReq accesses
3666system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.063560 # mshr miss rate for ReadSharedReq accesses
3667system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.171468 # mshr miss rate for ReadSharedReq accesses
3668system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529663 # mshr miss rate for ReadSharedReq accesses
3669system.l2c.ReadSharedReq_mshr_miss_rate::total 0.257550 # mshr miss rate for ReadSharedReq accesses
3670system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.297481 # mshr miss rate for demand accesses
3671system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.363939 # mshr miss rate for demand accesses
3672system.l2c.demand_mshr_miss_rate::cpu0.inst 0.107677 # mshr miss rate for demand accesses
3673system.l2c.demand_mshr_miss_rate::cpu0.data 0.463883 # mshr miss rate for demand accesses
3674system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.513528 # mshr miss rate for demand accesses
3675system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.296587 # mshr miss rate for demand accesses
3676system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.367763 # mshr miss rate for demand accesses
3677system.l2c.demand_mshr_miss_rate::cpu1.inst 0.063560 # mshr miss rate for demand accesses
3678system.l2c.demand_mshr_miss_rate::cpu1.data 0.278540 # mshr miss rate for demand accesses
3679system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529663 # mshr miss rate for demand accesses
3680system.l2c.demand_mshr_miss_rate::total 0.341450 # mshr miss rate for demand accesses
3681system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.297481 # mshr miss rate for overall accesses
3682system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.363939 # mshr miss rate for overall accesses
3683system.l2c.overall_mshr_miss_rate::cpu0.inst 0.107677 # mshr miss rate for overall accesses
3684system.l2c.overall_mshr_miss_rate::cpu0.data 0.463883 # mshr miss rate for overall accesses
3685system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.513528 # mshr miss rate for overall accesses
3686system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.296587 # mshr miss rate for overall accesses
3687system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.367763 # mshr miss rate for overall accesses
3688system.l2c.overall_mshr_miss_rate::cpu1.inst 0.063560 # mshr miss rate for overall accesses
3689system.l2c.overall_mshr_miss_rate::cpu1.data 0.278540 # mshr miss rate for overall accesses
3690system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529663 # mshr miss rate for overall accesses
3691system.l2c.overall_mshr_miss_rate::total 0.341450 # mshr miss rate for overall accesses
3692system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20800.621529 # average UpgradeReq mshr miss latency
3693system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20791.508332 # average UpgradeReq mshr miss latency
3694system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20796.244332 # average UpgradeReq mshr miss latency
3695system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20768.382919 # average SCUpgradeReq mshr miss latency
3696system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20789.283483 # average SCUpgradeReq mshr miss latency
3697system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20778.098350 # average SCUpgradeReq mshr miss latency
3698system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 120935.584597 # average ReadExReq mshr miss latency
3699system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 100900.229250 # average ReadExReq mshr miss latency
3700system.l2c.ReadExReq_avg_mshr_miss_latency::total 116014.881862 # average ReadExReq mshr miss latency
3701system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 83137.751561 # average ReadSharedReq mshr miss latency
3702system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 85734.946646 # average ReadSharedReq mshr miss latency
3703system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 76933.592354 # average ReadSharedReq mshr miss latency
3704system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 89498.558805 # average ReadSharedReq mshr miss latency
3705system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130190.674550 # average ReadSharedReq mshr miss latency
3706system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 82518.874773 # average ReadSharedReq mshr miss latency
3707system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 84561.708861 # average ReadSharedReq mshr miss latency
3708system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76410.566438 # average ReadSharedReq mshr miss latency
3709system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 87864.778277 # average ReadSharedReq mshr miss latency
3710system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130459.412172 # average ReadSharedReq mshr miss latency
3711system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 112031.632054 # average ReadSharedReq mshr miss latency
3712system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83137.751561 # average overall mshr miss latency
3713system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 85734.946646 # average overall mshr miss latency
3714system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76933.592354 # average overall mshr miss latency
3715system.l2c.demand_avg_mshr_miss_latency::cpu0.data 112904.774326 # average overall mshr miss latency
3716system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130190.674550 # average overall mshr miss latency
3717system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 82518.874773 # average overall mshr miss latency
3718system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 84561.708861 # average overall mshr miss latency
3719system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76410.566438 # average overall mshr miss latency
3720system.l2c.demand_avg_mshr_miss_latency::cpu1.data 95311.504985 # average overall mshr miss latency
3721system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130459.412172 # average overall mshr miss latency
3722system.l2c.demand_avg_mshr_miss_latency::total 113609.496968 # average overall mshr miss latency
3723system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83137.751561 # average overall mshr miss latency
3724system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 85734.946646 # average overall mshr miss latency
3725system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76933.592354 # average overall mshr miss latency
3726system.l2c.overall_avg_mshr_miss_latency::cpu0.data 112904.774326 # average overall mshr miss latency
3727system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 130190.674550 # average overall mshr miss latency
3728system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 82518.874773 # average overall mshr miss latency
3729system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 84561.708861 # average overall mshr miss latency
3730system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76410.566438 # average overall mshr miss latency
3731system.l2c.overall_avg_mshr_miss_latency::cpu1.data 95311.504985 # average overall mshr miss latency
3732system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130459.412172 # average overall mshr miss latency
3733system.l2c.overall_avg_mshr_miss_latency::total 113609.496968 # average overall mshr miss latency
3734system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024 # average ReadReq mshr uncacheable latency
3735system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156472.227426 # average ReadReq mshr uncacheable latency
3736system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60917.910448 # average ReadReq mshr uncacheable latency
3737system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 127801.984291 # average ReadReq mshr uncacheable latency
3738system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 114507.184053 # average ReadReq mshr uncacheable latency
3739system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 149180.347220 # average WriteReq mshr uncacheable latency
3740system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 129937.567132 # average WriteReq mshr uncacheable latency
3741system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141677.456104 # average WriteReq mshr uncacheable latency
3742system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 62024.420024 # average overall mshr uncacheable latency
3743system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 152666.603963 # average overall mshr uncacheable latency
3744system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60917.910448 # average overall mshr uncacheable latency
3745system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 128801.438939 # average overall mshr uncacheable latency
3746system.l2c.overall_avg_mshr_uncacheable_latency::total 125115.391242 # average overall mshr uncacheable latency
3747system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
3748system.membus.trans_dist::ReadReq 59646 # Transaction distribution
3749system.membus.trans_dist::ReadResp 1127009 # Transaction distribution
3750system.membus.trans_dist::WriteReq 38204 # Transaction distribution
3751system.membus.trans_dist::WriteResp 38204 # Transaction distribution
3752system.membus.trans_dist::Writeback 1464927 # Transaction distribution
3753system.membus.trans_dist::CleanEvict 280718 # Transaction distribution
3754system.membus.trans_dist::UpgradeReq 444619 # Transaction distribution
3755system.membus.trans_dist::SCUpgradeReq 331926 # Transaction distribution
3756system.membus.trans_dist::UpgradeResp 118163 # Transaction distribution
3757system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
3758system.membus.trans_dist::ReadExReq 708914 # Transaction distribution
3759system.membus.trans_dist::ReadExResp 687449 # Transaction distribution
3760system.membus.trans_dist::ReadSharedReq 1067363 # Transaction distribution
3761system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution
3762system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution
3763system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122642 # Packet count per connected master and slave (bytes)
3764system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes)
3765system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25116 # Packet count per connected master and slave (bytes)
3766system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6087631 # Packet count per connected master and slave (bytes)
3767system.membus.pkt_count_system.l2c.mem_side::total 6235467 # Packet count per connected master and slave (bytes)
3768system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342027 # Packet count per connected master and slave (bytes)
3769system.membus.pkt_count_system.iocache.mem_side::total 342027 # Packet count per connected master and slave (bytes)
3770system.membus.pkt_count::total 6577494 # Packet count per connected master and slave (bytes)
3771system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155749 # Cumulative packet size per connected master and slave (bytes)
3772system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes)
3773system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50232 # Cumulative packet size per connected master and slave (bytes)
3774system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 198978048 # Cumulative packet size per connected master and slave (bytes)
3775system.membus.pkt_size_system.l2c.mem_side::total 199184601 # Cumulative packet size per connected master and slave (bytes)
3776system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7249472 # Cumulative packet size per connected master and slave (bytes)
3777system.membus.pkt_size_system.iocache.mem_side::total 7249472 # Cumulative packet size per connected master and slave (bytes)
3778system.membus.pkt_size::total 206434073 # Cumulative packet size per connected master and slave (bytes)
3779system.membus.snoops 682959 # Total snoops (count)
3780system.membus.snoop_fanout::samples 4505681 # Request fanout histogram
3781system.membus.snoop_fanout::mean 1 # Request fanout histogram
3782system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3783system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3784system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3785system.membus.snoop_fanout::1 4505681 100.00% 100.00% # Request fanout histogram
3786system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3787system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3788system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3789system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3790system.membus.snoop_fanout::total 4505681 # Request fanout histogram
3791system.membus.reqLayer0.occupancy 98301494 # Layer occupancy (ticks)
3792system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3793system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks)
3794system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3795system.membus.reqLayer2.occupancy 21116985 # Layer occupancy (ticks)
3796system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3797system.membus.reqLayer5.occupancy 10136025529 # Layer occupancy (ticks)
3798system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3799system.membus.respLayer2.occupancy 9507659574 # Layer occupancy (ticks)
3800system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3801system.membus.respLayer3.occupancy 229108938 # Layer occupancy (ticks)
3802system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3803system.realview.ethernet.txBytes 966 # Bytes Transmitted
3804system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3805system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3806system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3807system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3808system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3809system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA

--- 27 unchanged lines hidden (view full) ---

3837system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
3838system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3839system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3840system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
3841system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3842system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3843system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3844system.realview.ethernet.droppedPackets 0 # number of packets dropped
3845system.toL2Bus.trans_dist::ReadReq 59648 # Transaction distribution
3846system.toL2Bus.trans_dist::ReadResp 5069827 # Transaction distribution
3847system.toL2Bus.trans_dist::WriteReq 38204 # Transaction distribution
3848system.toL2Bus.trans_dist::WriteResp 38204 # Transaction distribution
3849system.toL2Bus.trans_dist::Writeback 4145743 # Transaction distribution
3850system.toL2Bus.trans_dist::CleanEvict 1638680 # Transaction distribution
3851system.toL2Bus.trans_dist::UpgradeReq 501758 # Transaction distribution
3852system.toL2Bus.trans_dist::SCUpgradeReq 344029 # Transaction distribution
3853system.toL2Bus.trans_dist::UpgradeResp 845787 # Transaction distribution
3854system.toL2Bus.trans_dist::SCUpgradeFailReq 136 # Transaction distribution
3855system.toL2Bus.trans_dist::UpgradeFailResp 136 # Transaction distribution
3856system.toL2Bus.trans_dist::ReadExReq 1170821 # Transaction distribution
3857system.toL2Bus.trans_dist::ReadExResp 1170821 # Transaction distribution
3858system.toL2Bus.trans_dist::ReadSharedReq 5017419 # Transaction distribution
3859system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution
3860system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9001938 # Packet count per connected master and slave (bytes)
3861system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7449274 # Packet count per connected master and slave (bytes)
3862system.toL2Bus.pkt_count::total 16451212 # Packet count per connected master and slave (bytes)
3863system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 278573838 # Cumulative packet size per connected master and slave (bytes)
3864system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 222195147 # Cumulative packet size per connected master and slave (bytes)
3865system.toL2Bus.pkt_size::total 500768985 # Cumulative packet size per connected master and slave (bytes)
3866system.toL2Bus.snoops 3698425 # Total snoops (count)
3867system.toL2Bus.snoop_fanout::samples 14333755 # Request fanout histogram
3868system.toL2Bus.snoop_fanout::mean 1.138980 # Request fanout histogram
3869system.toL2Bus.snoop_fanout::stdev 0.345926 # Request fanout histogram
3870system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3871system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3872system.toL2Bus.snoop_fanout::1 12341651 86.10% 86.10% # Request fanout histogram
3873system.toL2Bus.snoop_fanout::2 1992104 13.90% 100.00% # Request fanout histogram
3874system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3875system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
3876system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3877system.toL2Bus.snoop_fanout::total 14333755 # Request fanout histogram
3878system.toL2Bus.reqLayer0.occupancy 9346036195 # Layer occupancy (ticks)
3879system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3880system.toL2Bus.snoopLayer0.occupancy 2541000 # Layer occupancy (ticks)
3881system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3882system.toL2Bus.respLayer0.occupancy 5271518855 # Layer occupancy (ticks)
3883system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3884system.toL2Bus.respLayer1.occupancy 4504542320 # Layer occupancy (ticks)
3885system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3886system.cpu0.kern.inst.arm 0 # number of arm instructions executed
3887system.cpu0.kern.inst.quiesce 4738 # number of quiesce instructions executed
3888system.cpu1.kern.inst.arm 0 # number of arm instructions executed
3889system.cpu1.kern.inst.quiesce 14252 # number of quiesce instructions executed
3890
3891---------- End Simulation Statistics ----------