1
2---------- Begin Simulation Statistics ----------
3sim_seconds 47.385466 # Number of seconds simulated
4sim_ticks 47385466309500 # Number of ticks simulated
5final_tick 47385466309500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 109383 # Simulator instruction rate (inst/s)
8host_op_rate 128637 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 5566054279 # Simulator tick rate (ticks/s)
10host_mem_usage 771804 # Number of bytes of host memory used
11host_seconds 8513.30 # Real time elapsed on the host
12sim_insts 931207580 # Number of instructions simulated
13sim_ops 1095127739 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker 167872 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker 148672 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst 4509472 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data 15471624 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu0.l2cache.prefetcher 18877376 # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.dtb.walker 171456 # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.itb.walker 164224 # Number of bytes read from this memory
23system.physmem.bytes_read::cpu1.inst 3092064 # Number of bytes read from this memory
24system.physmem.bytes_read::cpu1.data 12069648 # Number of bytes read from this memory
25system.physmem.bytes_read::cpu1.l2cache.prefetcher 17196544 # Number of bytes read from this memory
26system.physmem.bytes_read::realview.ide 427520 # Number of bytes read from this memory
27system.physmem.bytes_read::total 72296472 # Number of bytes read from this memory
28system.physmem.bytes_inst_read::cpu0.inst 4509472 # Number of instructions bytes read from this memory
29system.physmem.bytes_inst_read::cpu1.inst 3092064 # Number of instructions bytes read from this memory
30system.physmem.bytes_inst_read::total 7601536 # Number of instructions bytes read from this memory
31system.physmem.bytes_written::writebacks 87689472 # Number of bytes written to this memory
32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
34system.physmem.bytes_written::total 87710056 # Number of bytes written to this memory
35system.physmem.num_reads::cpu0.dtb.walker 2623 # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu0.itb.walker 2323 # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu0.inst 86413 # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu0.data 241757 # Number of read requests responded to by this memory
39system.physmem.num_reads::cpu0.l2cache.prefetcher 294959 # Number of read requests responded to by this memory
40system.physmem.num_reads::cpu1.dtb.walker 2679 # Number of read requests responded to by this memory
41system.physmem.num_reads::cpu1.itb.walker 2566 # Number of read requests responded to by this memory
42system.physmem.num_reads::cpu1.inst 48357 # Number of read requests responded to by this memory
43system.physmem.num_reads::cpu1.data 188601 # Number of read requests responded to by this memory
44system.physmem.num_reads::cpu1.l2cache.prefetcher 268696 # Number of read requests responded to by this memory
45system.physmem.num_reads::realview.ide 6680 # Number of read requests responded to by this memory
46system.physmem.num_reads::total 1145654 # Number of read requests responded to by this memory
47system.physmem.num_writes::writebacks 1370148 # Number of write requests responded to by this memory
48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
50system.physmem.num_writes::total 1372722 # Number of write requests responded to by this memory
51system.physmem.bw_read::cpu0.dtb.walker 3543 # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::cpu0.itb.walker 3138 # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::cpu0.inst 95166 # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_read::cpu0.data 326506 # Total read bandwidth from this memory (bytes/s)
55system.physmem.bw_read::cpu0.l2cache.prefetcher 398379 # Total read bandwidth from this memory (bytes/s)
56system.physmem.bw_read::cpu1.dtb.walker 3618 # Total read bandwidth from this memory (bytes/s)
57system.physmem.bw_read::cpu1.itb.walker 3466 # Total read bandwidth from this memory (bytes/s)
58system.physmem.bw_read::cpu1.inst 65253 # Total read bandwidth from this memory (bytes/s)
59system.physmem.bw_read::cpu1.data 254712 # Total read bandwidth from this memory (bytes/s)
60system.physmem.bw_read::cpu1.l2cache.prefetcher 362908 # Total read bandwidth from this memory (bytes/s)
61system.physmem.bw_read::realview.ide 9022 # Total read bandwidth from this memory (bytes/s)
62system.physmem.bw_read::total 1525710 # Total read bandwidth from this memory (bytes/s)
63system.physmem.bw_inst_read::cpu0.inst 95166 # Instruction read bandwidth from this memory (bytes/s)
64system.physmem.bw_inst_read::cpu1.inst 65253 # Instruction read bandwidth from this memory (bytes/s)
65system.physmem.bw_inst_read::total 160419 # Instruction read bandwidth from this memory (bytes/s)
66system.physmem.bw_write::writebacks 1850556 # Write bandwidth from this memory (bytes/s)
67system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
69system.physmem.bw_write::total 1850991 # Write bandwidth from this memory (bytes/s)
70system.physmem.bw_total::writebacks 1850556 # Total bandwidth to/from this memory (bytes/s)
71system.physmem.bw_total::cpu0.dtb.walker 3543 # Total bandwidth to/from this memory (bytes/s)
72system.physmem.bw_total::cpu0.itb.walker 3138 # Total bandwidth to/from this memory (bytes/s)
73system.physmem.bw_total::cpu0.inst 95166 # Total bandwidth to/from this memory (bytes/s)
74system.physmem.bw_total::cpu0.data 326940 # Total bandwidth to/from this memory (bytes/s)
75system.physmem.bw_total::cpu0.l2cache.prefetcher 398379 # Total bandwidth to/from this memory (bytes/s)
76system.physmem.bw_total::cpu1.dtb.walker 3618 # Total bandwidth to/from this memory (bytes/s)
77system.physmem.bw_total::cpu1.itb.walker 3466 # Total bandwidth to/from this memory (bytes/s)
78system.physmem.bw_total::cpu1.inst 65253 # Total bandwidth to/from this memory (bytes/s)
79system.physmem.bw_total::cpu1.data 254712 # Total bandwidth to/from this memory (bytes/s)
80system.physmem.bw_total::cpu1.l2cache.prefetcher 362908 # Total bandwidth to/from this memory (bytes/s)
81system.physmem.bw_total::realview.ide 9022 # Total bandwidth to/from this memory (bytes/s)
82system.physmem.bw_total::total 3376701 # Total bandwidth to/from this memory (bytes/s)
83system.physmem.readReqs 1145654 # Number of read requests accepted
84system.physmem.writeReqs 2060182 # Number of write requests accepted
85system.physmem.readBursts 1145654 # Number of DRAM read bursts, including those serviced by the write queue
86system.physmem.writeBursts 2060182 # Number of DRAM write bursts, including those merged in the write queue
87system.physmem.bytesReadDRAM 73301632 # Total number of bytes read from DRAM
88system.physmem.bytesReadWrQ 20224 # Total number of bytes read from write queue
89system.physmem.bytesWritten 128743424 # Total number of bytes written to DRAM
90system.physmem.bytesReadSys 72296472 # Total read bytes from the system interface side
91system.physmem.bytesWrittenSys 131707496 # Total written bytes from the system interface side
92system.physmem.servicedByWrQ 316 # Number of DRAM read bursts serviced by the write queue
93system.physmem.mergedWrBursts 48535 # Number of DRAM write bursts merged with an existing one
94system.physmem.neitherReadNorWriteReqs 120456 # Number of requests that are neither read nor write
95system.physmem.perBankRdBursts::0 65572 # Per bank write bursts
96system.physmem.perBankRdBursts::1 75328 # Per bank write bursts
97system.physmem.perBankRdBursts::2 66668 # Per bank write bursts
98system.physmem.perBankRdBursts::3 73797 # Per bank write bursts
99system.physmem.perBankRdBursts::4 73498 # Per bank write bursts
100system.physmem.perBankRdBursts::5 82651 # Per bank write bursts
101system.physmem.perBankRdBursts::6 70750 # Per bank write bursts
102system.physmem.perBankRdBursts::7 70075 # Per bank write bursts
103system.physmem.perBankRdBursts::8 62480 # Per bank write bursts
104system.physmem.perBankRdBursts::9 88491 # Per bank write bursts
105system.physmem.perBankRdBursts::10 66146 # Per bank write bursts
106system.physmem.perBankRdBursts::11 72268 # Per bank write bursts
107system.physmem.perBankRdBursts::12 67491 # Per bank write bursts
108system.physmem.perBankRdBursts::13 74959 # Per bank write bursts
109system.physmem.perBankRdBursts::14 69333 # Per bank write bursts
110system.physmem.perBankRdBursts::15 65831 # Per bank write bursts
111system.physmem.perBankWrBursts::0 122352 # Per bank write bursts
112system.physmem.perBankWrBursts::1 129436 # Per bank write bursts
113system.physmem.perBankWrBursts::2 124260 # Per bank write bursts
114system.physmem.perBankWrBursts::3 131298 # Per bank write bursts
115system.physmem.perBankWrBursts::4 127700 # Per bank write bursts
116system.physmem.perBankWrBursts::5 133890 # Per bank write bursts
117system.physmem.perBankWrBursts::6 125807 # Per bank write bursts
118system.physmem.perBankWrBursts::7 124647 # Per bank write bursts
119system.physmem.perBankWrBursts::8 116114 # Per bank write bursts
120system.physmem.perBankWrBursts::9 124444 # Per bank write bursts
121system.physmem.perBankWrBursts::10 122980 # Per bank write bursts
122system.physmem.perBankWrBursts::11 126137 # Per bank write bursts
123system.physmem.perBankWrBursts::12 123363 # Per bank write bursts
124system.physmem.perBankWrBursts::13 128612 # Per bank write bursts
125system.physmem.perBankWrBursts::14 126014 # Per bank write bursts
126system.physmem.perBankWrBursts::15 124562 # Per bank write bursts
127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
128system.physmem.numWrRetry 81198 # Number of times write queue was full causing retry
129system.physmem.totGap 47385464863500 # Total gap between requests
130system.physmem.readPktSize::0 0 # Read request sizes (log2)
131system.physmem.readPktSize::1 0 # Read request sizes (log2)
132system.physmem.readPktSize::2 0 # Read request sizes (log2)
133system.physmem.readPktSize::3 25 # Read request sizes (log2)
134system.physmem.readPktSize::4 21333 # Read request sizes (log2)
135system.physmem.readPktSize::5 0 # Read request sizes (log2)
136system.physmem.readPktSize::6 1124296 # Read request sizes (log2)
137system.physmem.writePktSize::0 0 # Write request sizes (log2)
138system.physmem.writePktSize::1 0 # Write request sizes (log2)
139system.physmem.writePktSize::2 2 # Write request sizes (log2)
140system.physmem.writePktSize::3 2572 # Write request sizes (log2)
141system.physmem.writePktSize::4 0 # Write request sizes (log2)
142system.physmem.writePktSize::5 0 # Write request sizes (log2)
143system.physmem.writePktSize::6 2057608 # Write request sizes (log2)
144system.physmem.rdQLenPdf::0 487455 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::1 272298 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::2 106854 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::3 72030 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::4 47157 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::5 39210 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::6 35683 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::7 33198 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::8 29456 # What read queue length does an incoming req see
153system.physmem.rdQLenPdf::9 9611 # What read queue length does an incoming req see
154system.physmem.rdQLenPdf::10 4248 # What read queue length does an incoming req see
155system.physmem.rdQLenPdf::11 2678 # What read queue length does an incoming req see
156system.physmem.rdQLenPdf::12 1608 # What read queue length does an incoming req see
157system.physmem.rdQLenPdf::13 1189 # What read queue length does an incoming req see
158system.physmem.rdQLenPdf::14 723 # What read queue length does an incoming req see
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162system.physmem.rdQLenPdf::18 170 # What read queue length does an incoming req see
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183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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192system.physmem.wrQLenPdf::16 35267 # What write queue length does an incoming req see
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198system.physmem.wrQLenPdf::22 81647 # What write queue length does an incoming req see
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204system.physmem.wrQLenPdf::28 99736 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::29 122228 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::30 105767 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::31 99735 # What write queue length does an incoming req see
208system.physmem.wrQLenPdf::32 90681 # What write queue length does an incoming req see
209system.physmem.wrQLenPdf::33 12739 # What write queue length does an incoming req see
210system.physmem.wrQLenPdf::34 9828 # What write queue length does an incoming req see
211system.physmem.wrQLenPdf::35 8966 # What write queue length does an incoming req see
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213system.physmem.wrQLenPdf::37 10412 # What write queue length does an incoming req see
214system.physmem.wrQLenPdf::38 8782 # What write queue length does an incoming req see
215system.physmem.wrQLenPdf::39 8556 # What write queue length does an incoming req see
216system.physmem.wrQLenPdf::40 10053 # What write queue length does an incoming req see
217system.physmem.wrQLenPdf::41 8187 # What write queue length does an incoming req see
218system.physmem.wrQLenPdf::42 7840 # What write queue length does an incoming req see
219system.physmem.wrQLenPdf::43 7194 # What write queue length does an incoming req see
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221system.physmem.wrQLenPdf::45 6708 # What write queue length does an incoming req see
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224system.physmem.wrQLenPdf::48 5369 # What write queue length does an incoming req see
225system.physmem.wrQLenPdf::49 4788 # What write queue length does an incoming req see
226system.physmem.wrQLenPdf::50 3634 # What write queue length does an incoming req see
227system.physmem.wrQLenPdf::51 3586 # What write queue length does an incoming req see
228system.physmem.wrQLenPdf::52 3218 # What write queue length does an incoming req see
229system.physmem.wrQLenPdf::53 2942 # What write queue length does an incoming req see
230system.physmem.wrQLenPdf::54 2942 # What write queue length does an incoming req see
231system.physmem.wrQLenPdf::55 2916 # What write queue length does an incoming req see
232system.physmem.wrQLenPdf::56 2764 # What write queue length does an incoming req see
233system.physmem.wrQLenPdf::57 2992 # What write queue length does an incoming req see
234system.physmem.wrQLenPdf::58 3448 # What write queue length does an incoming req see
235system.physmem.wrQLenPdf::59 3971 # What write queue length does an incoming req see
236system.physmem.wrQLenPdf::60 4529 # What write queue length does an incoming req see
237system.physmem.wrQLenPdf::61 7153 # What write queue length does an incoming req see
238system.physmem.wrQLenPdf::62 8045 # What write queue length does an incoming req see
239system.physmem.wrQLenPdf::63 352485 # What write queue length does an incoming req see
240system.physmem.bytesPerActivate::samples 1120451 # Bytes accessed per row activation
241system.physmem.bytesPerActivate::mean 180.324302 # Bytes accessed per row activation
242system.physmem.bytesPerActivate::gmean 110.099448 # Bytes accessed per row activation
243system.physmem.bytesPerActivate::stdev 247.440504 # Bytes accessed per row activation
244system.physmem.bytesPerActivate::0-127 698811 62.37% 62.37% # Bytes accessed per row activation
245system.physmem.bytesPerActivate::128-255 221320 19.75% 82.12% # Bytes accessed per row activation
246system.physmem.bytesPerActivate::256-383 61667 5.50% 87.63% # Bytes accessed per row activation
247system.physmem.bytesPerActivate::384-511 27543 2.46% 90.08% # Bytes accessed per row activation
248system.physmem.bytesPerActivate::512-639 21267 1.90% 91.98% # Bytes accessed per row activation
249system.physmem.bytesPerActivate::640-767 12605 1.12% 93.11% # Bytes accessed per row activation
250system.physmem.bytesPerActivate::768-895 9064 0.81% 93.92% # Bytes accessed per row activation
251system.physmem.bytesPerActivate::896-1023 8274 0.74% 94.65% # Bytes accessed per row activation
252system.physmem.bytesPerActivate::1024-1151 59900 5.35% 100.00% # Bytes accessed per row activation
253system.physmem.bytesPerActivate::total 1120451 # Bytes accessed per row activation
254system.physmem.rdPerTurnAround::samples 73379 # Reads before turning the bus around for writes
255system.physmem.rdPerTurnAround::mean 15.608158 # Reads before turning the bus around for writes
256system.physmem.rdPerTurnAround::stdev 65.872388 # Reads before turning the bus around for writes
257system.physmem.rdPerTurnAround::0-511 73373 99.99% 99.99% # Reads before turning the bus around for writes
258system.physmem.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes
259system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes
260system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
261system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
262system.physmem.rdPerTurnAround::total 73379 # Reads before turning the bus around for writes
263system.physmem.wrPerTurnAround::samples 73379 # Writes before turning the bus around for reads
264system.physmem.wrPerTurnAround::mean 27.414056 # Writes before turning the bus around for reads
265system.physmem.wrPerTurnAround::gmean 19.095862 # Writes before turning the bus around for reads
266system.physmem.wrPerTurnAround::stdev 903.451601 # Writes before turning the bus around for reads
267system.physmem.wrPerTurnAround::0-4095 73376 100.00% 100.00% # Writes before turning the bus around for reads
268system.physmem.wrPerTurnAround::98304-102399 1 0.00% 100.00% # Writes before turning the bus around for reads
269system.physmem.wrPerTurnAround::102400-106495 1 0.00% 100.00% # Writes before turning the bus around for reads
270system.physmem.wrPerTurnAround::192512-196607 1 0.00% 100.00% # Writes before turning the bus around for reads
271system.physmem.wrPerTurnAround::total 73379 # Writes before turning the bus around for reads
272system.physmem.totQLat 58866128789 # Total ticks spent queuing
273system.physmem.totMemAccLat 80341216289 # Total ticks spent from burst creation until serviced by the DRAM
274system.physmem.totBusLat 5726690000 # Total ticks spent in databus transfers
275system.physmem.avgQLat 51396.29 # Average queueing delay per DRAM burst
276system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
277system.physmem.avgMemAccLat 70146.29 # Average memory access latency per DRAM burst
278system.physmem.avgRdBW 1.55 # Average DRAM read bandwidth in MiByte/s
279system.physmem.avgWrBW 2.72 # Average achieved write bandwidth in MiByte/s
280system.physmem.avgRdBWSys 1.53 # Average system read bandwidth in MiByte/s
281system.physmem.avgWrBWSys 2.78 # Average system write bandwidth in MiByte/s
282system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
283system.physmem.busUtil 0.03 # Data bus utilization in percentage
284system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
285system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
286system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing
287system.physmem.avgWrQLen 25.33 # Average write queue length when enqueuing
288system.physmem.readRowHits 867894 # Number of row buffer hits during reads
289system.physmem.writeRowHits 1168605 # Number of row buffer hits during writes
290system.physmem.readRowHitRate 75.78 # Row buffer hit rate for reads
291system.physmem.writeRowHitRate 58.09 # Row buffer hit rate for writes
292system.physmem.avgGap 14781000.92 # Average gap between requests
293system.physmem.pageHitRate 64.51 # Row buffer hit rate, read and write combined
294system.physmem_0.actEnergy 4336385760 # Energy for activate commands per rank (pJ)
295system.physmem_0.preEnergy 2366083500 # Energy for precharge commands per rank (pJ)
296system.physmem_0.readEnergy 4510974000 # Energy for read commands per rank (pJ)
297system.physmem_0.writeEnergy 6605647200 # Energy for write commands per rank (pJ)
298system.physmem_0.refreshEnergy 3094987836720 # Energy for refresh commands per rank (pJ)
299system.physmem_0.actBackEnergy 1170067048560 # Energy for active background per rank (pJ)
300system.physmem_0.preBackEnergy 27404900969250 # Energy for precharge background per rank (pJ)
301system.physmem_0.totalEnergy 31687774944990 # Total energy per rank (pJ)
302system.physmem_0.averagePower 668.723600 # Core power per rank (mW)
303system.physmem_0.memoryStateTime::IDLE 45590272941113 # Time in different power states
304system.physmem_0.memoryStateTime::REF 1582304620000 # Time in different power states
305system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
306system.physmem_0.memoryStateTime::ACT 212884395887 # Time in different power states
307system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
308system.physmem_1.actEnergy 4134208680 # Energy for activate commands per rank (pJ)
309system.physmem_1.preEnergy 2255768625 # Energy for precharge commands per rank (pJ)
310system.physmem_1.readEnergy 4422568800 # Energy for read commands per rank (pJ)
311system.physmem_1.writeEnergy 6429624480 # Energy for write commands per rank (pJ)
312system.physmem_1.refreshEnergy 3094987836720 # Energy for refresh commands per rank (pJ)
313system.physmem_1.actBackEnergy 1167604821270 # Energy for active background per rank (pJ)
314system.physmem_1.preBackEnergy 27407060817750 # Energy for precharge background per rank (pJ)
315system.physmem_1.totalEnergy 31686895646325 # Total energy per rank (pJ)
316system.physmem_1.averagePower 668.705044 # Core power per rank (mW)
317system.physmem_1.memoryStateTime::IDLE 45593855726560 # Time in different power states
318system.physmem_1.memoryStateTime::REF 1582304620000 # Time in different power states
319system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
320system.physmem_1.memoryStateTime::ACT 209300747940 # Time in different power states
321system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
322system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory
323system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
324system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
325system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
326system.realview.nvmem.bytes_read::total 572 # Number of bytes read from this memory
327system.realview.nvmem.bytes_inst_read::cpu0.inst 384 # Number of instructions bytes read from this memory
328system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory

--- 17 unchanged lines hidden (view full) ---

346system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
347system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
348system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
349system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
350system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
351system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
352system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
353system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
354system.cpu0.branchPred.lookups 143219505 # Number of BP lookups
355system.cpu0.branchPred.condPredicted 95215917 # Number of conditional branches predicted
356system.cpu0.branchPred.condIncorrect 6874228 # Number of conditional branches incorrect
357system.cpu0.branchPred.BTBLookups 100849572 # Number of BTB lookups
358system.cpu0.branchPred.BTBHits 65904871 # Number of BTB hits
359system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
360system.cpu0.branchPred.BTBHitPct 65.349678 # BTB Hit Percentage
361system.cpu0.branchPred.usedRAS 19505246 # Number of times the RAS was used to get a target.
362system.cpu0.branchPred.RASInCorrect 190029 # Number of incorrect RAS predictions.
363system.cpu_clk_domain.clock 500 # Clock period in ticks
364system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
365system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
366system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
367system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
368system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
369system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
370system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

385system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
386system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
387system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
388system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
389system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
390system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
391system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
392system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
393system.cpu0.dtb.walker.walks 557114 # Table walker walks requested
394system.cpu0.dtb.walker.walksLong 557114 # Table walker walks initiated with long descriptors
395system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11925 # Level at which table walker walks with long descriptors terminate
396system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88835 # Level at which table walker walks with long descriptors terminate
397system.cpu0.dtb.walker.walksSquashedBefore 245678 # Table walks squashed before starting
398system.cpu0.dtb.walker.walkWaitTime::samples 311436 # Table walker wait (enqueue to first request) latency
399system.cpu0.dtb.walker.walkWaitTime::mean 1783.814331 # Table walker wait (enqueue to first request) latency
400system.cpu0.dtb.walker.walkWaitTime::stdev 11278.873416 # Table walker wait (enqueue to first request) latency
401system.cpu0.dtb.walker.walkWaitTime::0-65535 309571 99.40% 99.40% # Table walker wait (enqueue to first request) latency
402system.cpu0.dtb.walker.walkWaitTime::65536-131071 1396 0.45% 99.85% # Table walker wait (enqueue to first request) latency
403system.cpu0.dtb.walker.walkWaitTime::131072-196607 332 0.11% 99.96% # Table walker wait (enqueue to first request) latency
404system.cpu0.dtb.walker.walkWaitTime::196608-262143 57 0.02% 99.97% # Table walker wait (enqueue to first request) latency
405system.cpu0.dtb.walker.walkWaitTime::262144-327679 59 0.02% 99.99% # Table walker wait (enqueue to first request) latency
406system.cpu0.dtb.walker.walkWaitTime::327680-393215 14 0.00% 100.00% # Table walker wait (enqueue to first request) latency
407system.cpu0.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
408system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
409system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
410system.cpu0.dtb.walker.walkWaitTime::total 311436 # Table walker wait (enqueue to first request) latency
411system.cpu0.dtb.walker.walkCompletionTime::samples 275434 # Table walker service (enqueue to completion) latency
412system.cpu0.dtb.walker.walkCompletionTime::mean 16916.133019 # Table walker service (enqueue to completion) latency
413system.cpu0.dtb.walker.walkCompletionTime::gmean 14128.427647 # Table walker service (enqueue to completion) latency
414system.cpu0.dtb.walker.walkCompletionTime::stdev 15086.481481 # Table walker service (enqueue to completion) latency
415system.cpu0.dtb.walker.walkCompletionTime::0-32767 261399 94.90% 94.90% # Table walker service (enqueue to completion) latency
416system.cpu0.dtb.walker.walkCompletionTime::32768-65535 11343 4.12% 99.02% # Table walker service (enqueue to completion) latency
417system.cpu0.dtb.walker.walkCompletionTime::65536-98303 1146 0.42% 99.44% # Table walker service (enqueue to completion) latency
418system.cpu0.dtb.walker.walkCompletionTime::98304-131071 802 0.29% 99.73% # Table walker service (enqueue to completion) latency
419system.cpu0.dtb.walker.walkCompletionTime::131072-163839 102 0.04% 99.77% # Table walker service (enqueue to completion) latency
420system.cpu0.dtb.walker.walkCompletionTime::163840-196607 163 0.06% 99.83% # Table walker service (enqueue to completion) latency
421system.cpu0.dtb.walker.walkCompletionTime::196608-229375 287 0.10% 99.93% # Table walker service (enqueue to completion) latency
422system.cpu0.dtb.walker.walkCompletionTime::229376-262143 70 0.03% 99.96% # Table walker service (enqueue to completion) latency
423system.cpu0.dtb.walker.walkCompletionTime::262144-294911 43 0.02% 99.97% # Table walker service (enqueue to completion) latency
424system.cpu0.dtb.walker.walkCompletionTime::294912-327679 36 0.01% 99.98% # Table walker service (enqueue to completion) latency
425system.cpu0.dtb.walker.walkCompletionTime::327680-360447 22 0.01% 99.99% # Table walker service (enqueue to completion) latency
426system.cpu0.dtb.walker.walkCompletionTime::360448-393215 9 0.00% 100.00% # Table walker service (enqueue to completion) latency
427system.cpu0.dtb.walker.walkCompletionTime::393216-425983 9 0.00% 100.00% # Table walker service (enqueue to completion) latency
428system.cpu0.dtb.walker.walkCompletionTime::425984-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
429system.cpu0.dtb.walker.walkCompletionTime::total 275434 # Table walker service (enqueue to completion) latency
430system.cpu0.dtb.walker.walksPending::samples 527372589640 # Table walker pending requests distribution
431system.cpu0.dtb.walker.walksPending::mean 0.581951 # Table walker pending requests distribution
432system.cpu0.dtb.walker.walksPending::stdev 0.533395 # Table walker pending requests distribution
433system.cpu0.dtb.walker.walksPending::0-1 526425698140 99.82% 99.82% # Table walker pending requests distribution
434system.cpu0.dtb.walker.walksPending::2-3 513345500 0.10% 99.92% # Table walker pending requests distribution
435system.cpu0.dtb.walker.walksPending::4-5 204440500 0.04% 99.96% # Table walker pending requests distribution
436system.cpu0.dtb.walker.walksPending::6-7 94120000 0.02% 99.97% # Table walker pending requests distribution
437system.cpu0.dtb.walker.walksPending::8-9 67519500 0.01% 99.99% # Table walker pending requests distribution
438system.cpu0.dtb.walker.walksPending::10-11 37561500 0.01% 99.99% # Table walker pending requests distribution
439system.cpu0.dtb.walker.walksPending::12-13 13535000 0.00% 100.00% # Table walker pending requests distribution
440system.cpu0.dtb.walker.walksPending::14-15 16113500 0.00% 100.00% # Table walker pending requests distribution
441system.cpu0.dtb.walker.walksPending::16-17 245000 0.00% 100.00% # Table walker pending requests distribution
442system.cpu0.dtb.walker.walksPending::18-19 11000 0.00% 100.00% # Table walker pending requests distribution
443system.cpu0.dtb.walker.walksPending::total 527372589640 # Table walker pending requests distribution
444system.cpu0.dtb.walker.walkPageSizes::4K 88835 88.16% 88.16% # Table walker page sizes translated
445system.cpu0.dtb.walker.walkPageSizes::2M 11925 11.84% 100.00% # Table walker page sizes translated
446system.cpu0.dtb.walker.walkPageSizes::total 100760 # Table walker page sizes translated
447system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 557114 # Table walker requests started/completed, data/inst
448system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
449system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 557114 # Table walker requests started/completed, data/inst
450system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 100760 # Table walker requests started/completed, data/inst
451system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
452system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 100760 # Table walker requests started/completed, data/inst
453system.cpu0.dtb.walker.walkRequestOrigin::total 657874 # Table walker requests started/completed, data/inst
454system.cpu0.dtb.inst_hits 0 # ITB inst hits
455system.cpu0.dtb.inst_misses 0 # ITB inst misses
456system.cpu0.dtb.read_hits 103903304 # DTB read hits
457system.cpu0.dtb.read_misses 386941 # DTB read misses
458system.cpu0.dtb.write_hits 87265042 # DTB write hits
459system.cpu0.dtb.write_misses 170173 # DTB write misses
460system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
461system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
462system.cpu0.dtb.flush_tlb_mva_asid 44809 # Number of times TLB was flushed by MVA & ASID
463system.cpu0.dtb.flush_tlb_asid 1073 # Number of times TLB was flushed by ASID
464system.cpu0.dtb.flush_entries 37535 # Number of entries that have been flushed from TLB
465system.cpu0.dtb.align_faults 216 # Number of TLB faults due to alignment restrictions
466system.cpu0.dtb.prefetch_faults 6819 # Number of TLB faults due to prefetch
467system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
468system.cpu0.dtb.perms_faults 40407 # Number of TLB faults due to permissions restrictions
469system.cpu0.dtb.read_accesses 104290245 # DTB read accesses
470system.cpu0.dtb.write_accesses 87435215 # DTB write accesses
471system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
472system.cpu0.dtb.hits 191168346 # DTB hits
473system.cpu0.dtb.misses 557114 # DTB misses
474system.cpu0.dtb.accesses 191725460 # DTB accesses
475system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
476system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
477system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
478system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
479system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
480system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
481system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

496system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
497system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
498system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
499system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
500system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
501system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
502system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
503system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
504system.cpu0.itb.walker.walks 85759 # Table walker walks requested
505system.cpu0.itb.walker.walksLong 85759 # Table walker walks initiated with long descriptors
506system.cpu0.itb.walker.walksLongTerminationLevel::Level2 908 # Level at which table walker walks with long descriptors terminate
507system.cpu0.itb.walker.walksLongTerminationLevel::Level3 62470 # Level at which table walker walks with long descriptors terminate
508system.cpu0.itb.walker.walksSquashedBefore 9907 # Table walks squashed before starting
509system.cpu0.itb.walker.walkWaitTime::samples 75852 # Table walker wait (enqueue to first request) latency
510system.cpu0.itb.walker.walkWaitTime::mean 1136.575173 # Table walker wait (enqueue to first request) latency
511system.cpu0.itb.walker.walkWaitTime::stdev 8938.964276 # Table walker wait (enqueue to first request) latency
512system.cpu0.itb.walker.walkWaitTime::0-32767 75266 99.23% 99.23% # Table walker wait (enqueue to first request) latency
513system.cpu0.itb.walker.walkWaitTime::32768-65535 257 0.34% 99.57% # Table walker wait (enqueue to first request) latency
514system.cpu0.itb.walker.walkWaitTime::65536-98303 133 0.18% 99.74% # Table walker wait (enqueue to first request) latency
515system.cpu0.itb.walker.walkWaitTime::98304-131071 159 0.21% 99.95% # Table walker wait (enqueue to first request) latency
516system.cpu0.itb.walker.walkWaitTime::131072-163839 9 0.01% 99.96% # Table walker wait (enqueue to first request) latency
517system.cpu0.itb.walker.walkWaitTime::163840-196607 8 0.01% 99.97% # Table walker wait (enqueue to first request) latency
518system.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency
519system.cpu0.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
520system.cpu0.itb.walker.walkWaitTime::262144-294911 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
521system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
522system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
523system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
524system.cpu0.itb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
525system.cpu0.itb.walker.walkWaitTime::total 75852 # Table walker wait (enqueue to first request) latency
526system.cpu0.itb.walker.walkCompletionTime::samples 73285 # Table walker service (enqueue to completion) latency
527system.cpu0.itb.walker.walkCompletionTime::mean 21415.899529 # Table walker service (enqueue to completion) latency
528system.cpu0.itb.walker.walkCompletionTime::gmean 18467.660437 # Table walker service (enqueue to completion) latency
529system.cpu0.itb.walker.walkCompletionTime::stdev 19009.032462 # Table walker service (enqueue to completion) latency
530system.cpu0.itb.walker.walkCompletionTime::0-65535 71796 97.97% 97.97% # Table walker service (enqueue to completion) latency
531system.cpu0.itb.walker.walkCompletionTime::65536-131071 1220 1.66% 99.63% # Table walker service (enqueue to completion) latency
532system.cpu0.itb.walker.walkCompletionTime::131072-196607 122 0.17% 99.80% # Table walker service (enqueue to completion) latency
533system.cpu0.itb.walker.walkCompletionTime::196608-262143 69 0.09% 99.89% # Table walker service (enqueue to completion) latency
534system.cpu0.itb.walker.walkCompletionTime::262144-327679 44 0.06% 99.95% # Table walker service (enqueue to completion) latency
535system.cpu0.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.98% # Table walker service (enqueue to completion) latency
536system.cpu0.itb.walker.walkCompletionTime::393216-458751 12 0.02% 100.00% # Table walker service (enqueue to completion) latency
537system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
538system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
539system.cpu0.itb.walker.walkCompletionTime::total 73285 # Table walker service (enqueue to completion) latency
540system.cpu0.itb.walker.walksPending::samples 394225556964 # Table walker pending requests distribution
541system.cpu0.itb.walker.walksPending::mean 0.858766 # Table walker pending requests distribution
542system.cpu0.itb.walker.walksPending::stdev 0.348387 # Table walker pending requests distribution
543system.cpu0.itb.walker.walksPending::0 55694159292 14.13% 14.13% # Table walker pending requests distribution
544system.cpu0.itb.walker.walksPending::1 338516533172 85.87% 100.00% # Table walker pending requests distribution
545system.cpu0.itb.walker.walksPending::2 13791500 0.00% 100.00% # Table walker pending requests distribution
546system.cpu0.itb.walker.walksPending::3 1055500 0.00% 100.00% # Table walker pending requests distribution
547system.cpu0.itb.walker.walksPending::4 17500 0.00% 100.00% # Table walker pending requests distribution
548system.cpu0.itb.walker.walksPending::total 394225556964 # Table walker pending requests distribution
549system.cpu0.itb.walker.walkPageSizes::4K 62470 98.57% 98.57% # Table walker page sizes translated
550system.cpu0.itb.walker.walkPageSizes::2M 908 1.43% 100.00% # Table walker page sizes translated
551system.cpu0.itb.walker.walkPageSizes::total 63378 # Table walker page sizes translated
552system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
553system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85759 # Table walker requests started/completed, data/inst
554system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85759 # Table walker requests started/completed, data/inst
555system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
556system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 63378 # Table walker requests started/completed, data/inst
557system.cpu0.itb.walker.walkRequestOrigin_Completed::total 63378 # Table walker requests started/completed, data/inst
558system.cpu0.itb.walker.walkRequestOrigin::total 149137 # Table walker requests started/completed, data/inst
559system.cpu0.itb.inst_hits 225166936 # ITB inst hits
560system.cpu0.itb.inst_misses 85759 # ITB inst misses
561system.cpu0.itb.read_hits 0 # DTB read hits
562system.cpu0.itb.read_misses 0 # DTB read misses
563system.cpu0.itb.write_hits 0 # DTB write hits
564system.cpu0.itb.write_misses 0 # DTB write misses
565system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
566system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
567system.cpu0.itb.flush_tlb_mva_asid 44809 # Number of times TLB was flushed by MVA & ASID
568system.cpu0.itb.flush_tlb_asid 1073 # Number of times TLB was flushed by ASID
569system.cpu0.itb.flush_entries 26709 # Number of entries that have been flushed from TLB
570system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
571system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
572system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
573system.cpu0.itb.perms_faults 217420 # Number of TLB faults due to permissions restrictions
574system.cpu0.itb.read_accesses 0 # DTB read accesses
575system.cpu0.itb.write_accesses 0 # DTB write accesses
576system.cpu0.itb.inst_accesses 225252695 # ITB inst accesses
577system.cpu0.itb.hits 225166936 # DTB hits
578system.cpu0.itb.misses 85759 # DTB misses
579system.cpu0.itb.accesses 225252695 # DTB accesses
580system.cpu0.numCycles 777590959 # number of cpu cycles simulated
581system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
582system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
583system.cpu0.fetch.icacheStallCycles 90148881 # Number of cycles fetch is stalled on an Icache miss
584system.cpu0.fetch.Insts 632830647 # Number of instructions fetch has processed
585system.cpu0.fetch.Branches 143219505 # Number of branches that fetch encountered
586system.cpu0.fetch.predictedBranches 85410117 # Number of branches that fetch has predicted taken
587system.cpu0.fetch.Cycles 647310508 # Number of cycles fetch has run and was not squashing or blocked
588system.cpu0.fetch.SquashCycles 14846236 # Number of cycles fetch has spent squashing
589system.cpu0.fetch.TlbCycles 1771940 # Number of cycles fetch has spent waiting for tlb
590system.cpu0.fetch.MiscStallCycles 282653 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
591system.cpu0.fetch.PendingTrapStallCycles 6199385 # Number of stall cycles due to pending traps
592system.cpu0.fetch.PendingQuiesceStallCycles 737729 # Number of stall cycles due to pending quiesce instructions
593system.cpu0.fetch.IcacheWaitRetryStallCycles 721364 # Number of stall cycles due to full MSHR
594system.cpu0.fetch.CacheLines 224948990 # Number of cache lines fetched
595system.cpu0.fetch.IcacheSquashes 1718929 # Number of outstanding Icache misses that were squashed
596system.cpu0.fetch.ItlbSquashes 28705 # Number of outstanding ITLB misses that were squashed
597system.cpu0.fetch.rateDist::samples 754595578 # Number of instructions fetched each cycle (Total)
598system.cpu0.fetch.rateDist::mean 0.984480 # Number of instructions fetched each cycle (Total)
599system.cpu0.fetch.rateDist::stdev 1.221164 # Number of instructions fetched each cycle (Total)
600system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
601system.cpu0.fetch.rateDist::0 398817072 52.85% 52.85% # Number of instructions fetched each cycle (Total)
602system.cpu0.fetch.rateDist::1 138444624 18.35% 71.20% # Number of instructions fetched each cycle (Total)
603system.cpu0.fetch.rateDist::2 47562041 6.30% 77.50% # Number of instructions fetched each cycle (Total)
604system.cpu0.fetch.rateDist::3 169771841 22.50% 100.00% # Number of instructions fetched each cycle (Total)
605system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
606system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
607system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
608system.cpu0.fetch.rateDist::total 754595578 # Number of instructions fetched each cycle (Total)
609system.cpu0.fetch.branchRate 0.184184 # Number of branch fetches per cycle
610system.cpu0.fetch.rate 0.813835 # Number of inst fetches per cycle
611system.cpu0.decode.IdleCycles 107688832 # Number of cycles decode is idle
612system.cpu0.decode.BlockedCycles 365256192 # Number of cycles decode is blocked
613system.cpu0.decode.RunCycles 237731032 # Number of cycles decode is running
614system.cpu0.decode.UnblockCycles 38638584 # Number of cycles decode is unblocking
615system.cpu0.decode.SquashCycles 5280938 # Number of cycles decode is squashing
616system.cpu0.decode.BranchResolved 20683549 # Number of times decode resolved a branch
617system.cpu0.decode.BranchMispred 2184734 # Number of times decode detected a branch misprediction
618system.cpu0.decode.DecodedInsts 657953246 # Number of instructions handled by decode
619system.cpu0.decode.SquashedInsts 23988018 # Number of squashed instructions handled by decode
620system.cpu0.rename.SquashCycles 5280938 # Number of cycles rename is squashing
621system.cpu0.rename.IdleCycles 144086550 # Number of cycles rename is idle
622system.cpu0.rename.BlockCycles 51798126 # Number of cycles rename is blocking
623system.cpu0.rename.serializeStallCycles 247348242 # count of cycles rename stalled for serializing inst
624system.cpu0.rename.RunCycles 239349699 # Number of cycles rename is running
625system.cpu0.rename.UnblockCycles 66732023 # Number of cycles rename is unblocking
626system.cpu0.rename.RenamedInsts 640403541 # Number of instructions processed by rename
627system.cpu0.rename.SquashedInsts 6134927 # Number of squashed instructions processed by rename
628system.cpu0.rename.ROBFullEvents 9593053 # Number of times rename has blocked due to ROB full
629system.cpu0.rename.IQFullEvents 279391 # Number of times rename has blocked due to IQ full
630system.cpu0.rename.LQFullEvents 288384 # Number of times rename has blocked due to LQ full
631system.cpu0.rename.SQFullEvents 30790790 # Number of times rename has blocked due to SQ full
632system.cpu0.rename.FullRegisterEvents 11378 # Number of times there has been no free registers
633system.cpu0.rename.RenamedOperands 609803525 # Number of destination operands rename has renamed
634system.cpu0.rename.RenameLookups 987601051 # Number of register rename lookups that rename has made
635system.cpu0.rename.int_rename_lookups 757009838 # Number of integer rename lookups
636system.cpu0.rename.fp_rename_lookups 819226 # Number of floating rename lookups
637system.cpu0.rename.CommittedMaps 550929032 # Number of HB maps that are committed
638system.cpu0.rename.UndoneMaps 58874487 # Number of HB maps that are undone due to squashing
639system.cpu0.rename.serializingInsts 16040201 # count of serializing insts renamed
640system.cpu0.rename.tempSerializingInsts 14019715 # count of temporary serializing insts renamed
641system.cpu0.rename.skidInsts 78263207 # count of insts added to the skid buffer
642system.cpu0.memDep0.insertedLoads 104115554 # Number of loads inserted to the mem dependence unit.
643system.cpu0.memDep0.insertedStores 90761559 # Number of stores inserted to the mem dependence unit.
644system.cpu0.memDep0.conflictingLoads 9526213 # Number of conflicting loads.
645system.cpu0.memDep0.conflictingStores 8179417 # Number of conflicting stores.
646system.cpu0.iq.iqInstsAdded 617656959 # Number of instructions added to the IQ (excludes non-spec)
647system.cpu0.iq.iqNonSpecInstsAdded 16134834 # Number of non-speculative instructions added to the IQ
648system.cpu0.iq.iqInstsIssued 622248752 # Number of instructions issued
649system.cpu0.iq.iqSquashedInstsIssued 2762846 # Number of squashed instructions issued
650system.cpu0.iq.iqSquashedInstsExamined 55648828 # Number of squashed instructions iterated over during squash; mainly for profiling
651system.cpu0.iq.iqSquashedOperandsExamined 35830856 # Number of squashed operands that are examined and possibly removed from graph
652system.cpu0.iq.iqSquashedNonSpecRemoved 282296 # Number of squashed non-spec instructions that were removed
653system.cpu0.iq.issued_per_cycle::samples 754595578 # Number of insts issued each cycle
654system.cpu0.iq.issued_per_cycle::mean 0.824612 # Number of insts issued each cycle
655system.cpu0.iq.issued_per_cycle::stdev 1.071196 # Number of insts issued each cycle
656system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
657system.cpu0.iq.issued_per_cycle::0 416444489 55.19% 55.19% # Number of insts issued each cycle
658system.cpu0.iq.issued_per_cycle::1 139981431 18.55% 73.74% # Number of insts issued each cycle
659system.cpu0.iq.issued_per_cycle::2 120577545 15.98% 89.72% # Number of insts issued each cycle
660system.cpu0.iq.issued_per_cycle::3 69261363 9.18% 98.90% # Number of insts issued each cycle
661system.cpu0.iq.issued_per_cycle::4 8325608 1.10% 100.00% # Number of insts issued each cycle
662system.cpu0.iq.issued_per_cycle::5 5142 0.00% 100.00% # Number of insts issued each cycle
663system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
664system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
665system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
666system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
667system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
668system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
669system.cpu0.iq.issued_per_cycle::total 754595578 # Number of insts issued each cycle
670system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
671system.cpu0.iq.fu_full::IntAlu 64632492 45.32% 45.32% # attempts to use FU when none available
672system.cpu0.iq.fu_full::IntMult 49764 0.03% 45.35% # attempts to use FU when none available
673system.cpu0.iq.fu_full::IntDiv 24321 0.02% 45.37% # attempts to use FU when none available
674system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.37% # attempts to use FU when none available
675system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.37% # attempts to use FU when none available
676system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.37% # attempts to use FU when none available
677system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.37% # attempts to use FU when none available
678system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.37% # attempts to use FU when none available
679system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.37% # attempts to use FU when none available
680system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.37% # attempts to use FU when none available
681system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.37% # attempts to use FU when none available
682system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.37% # attempts to use FU when none available
683system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.37% # attempts to use FU when none available
684system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.37% # attempts to use FU when none available
685system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.37% # attempts to use FU when none available
686system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.37% # attempts to use FU when none available
687system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.37% # attempts to use FU when none available
688system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.37% # attempts to use FU when none available
689system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.37% # attempts to use FU when none available
690system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.37% # attempts to use FU when none available
691system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.37% # attempts to use FU when none available
692system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.37% # attempts to use FU when none available
693system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.37% # attempts to use FU when none available
694system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.37% # attempts to use FU when none available
695system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.37% # attempts to use FU when none available
696system.cpu0.iq.fu_full::SimdFloatMisc 8 0.00% 45.37% # attempts to use FU when none available
697system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.37% # attempts to use FU when none available
698system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.37% # attempts to use FU when none available
699system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.37% # attempts to use FU when none available
700system.cpu0.iq.fu_full::MemRead 36912792 25.88% 71.25% # attempts to use FU when none available
701system.cpu0.iq.fu_full::MemWrite 41006253 28.75% 100.00% # attempts to use FU when none available
702system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
703system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
704system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
705system.cpu0.iq.FU_type_0::IntAlu 425093937 68.32% 68.32% # Type of FU issued
706system.cpu0.iq.FU_type_0::IntMult 1435088 0.23% 68.55% # Type of FU issued
707system.cpu0.iq.FU_type_0::IntDiv 72707 0.01% 68.56% # Type of FU issued
708system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 68.56% # Type of FU issued
709system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.56% # Type of FU issued
710system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.56% # Type of FU issued
711system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.56% # Type of FU issued
712system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.56% # Type of FU issued
713system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.56% # Type of FU issued
714system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.56% # Type of FU issued
715system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.56% # Type of FU issued
716system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.56% # Type of FU issued
717system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.56% # Type of FU issued
718system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.56% # Type of FU issued
719system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.56% # Type of FU issued
720system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.56% # Type of FU issued
721system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.56% # Type of FU issued
722system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.56% # Type of FU issued
723system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.56% # Type of FU issued
724system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.56% # Type of FU issued
725system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.56% # Type of FU issued
726system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.56% # Type of FU issued
727system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.56% # Type of FU issued
728system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.56% # Type of FU issued
729system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.56% # Type of FU issued
730system.cpu0.iq.FU_type_0::SimdFloatMisc 80017 0.01% 68.57% # Type of FU issued
731system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.57% # Type of FU issued
732system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.57% # Type of FU issued
733system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.57% # Type of FU issued
734system.cpu0.iq.FU_type_0::MemRead 106973715 17.19% 85.76% # Type of FU issued
735system.cpu0.iq.FU_type_0::MemWrite 88593239 14.24% 100.00% # Type of FU issued
736system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
737system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
738system.cpu0.iq.FU_type_0::total 622248752 # Type of FU issued
739system.cpu0.iq.rate 0.800226 # Inst issue rate
740system.cpu0.iq.fu_busy_cnt 142625630 # FU busy when requested
741system.cpu0.iq.fu_busy_rate 0.229210 # FU busy rate (busy events/executed inst)
742system.cpu0.iq.int_inst_queue_reads 2143120412 # Number of integer instruction queue reads
743system.cpu0.iq.int_inst_queue_writes 689044772 # Number of integer instruction queue writes
744system.cpu0.iq.int_inst_queue_wakeup_accesses 604966692 # Number of integer instruction queue wakeup accesses
745system.cpu0.iq.fp_inst_queue_reads 1361144 # Number of floating instruction queue reads
746system.cpu0.iq.fp_inst_queue_writes 552290 # Number of floating instruction queue writes
747system.cpu0.iq.fp_inst_queue_wakeup_accesses 506244 # Number of floating instruction queue wakeup accesses
748system.cpu0.iq.int_alu_accesses 764032585 # Number of integer alu accesses
749system.cpu0.iq.fp_alu_accesses 841796 # Number of floating point alu accesses
750system.cpu0.iew.lsq.thread0.forwLoads 2890526 # Number of loads that had data forwarded from stores
751system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
752system.cpu0.iew.lsq.thread0.squashedLoads 12594321 # Number of loads squashed
753system.cpu0.iew.lsq.thread0.ignoredResponses 16775 # Number of memory responses ignored because the instruction is squashed
754system.cpu0.iew.lsq.thread0.memOrderViolation 157768 # Number of memory ordering violations
755system.cpu0.iew.lsq.thread0.squashedStores 6060902 # Number of stores squashed
756system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
757system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
758system.cpu0.iew.lsq.thread0.rescheduledLoads 2889033 # Number of loads that were rescheduled
759system.cpu0.iew.lsq.thread0.cacheBlocked 4437246 # Number of times an access to memory failed due to the cache being blocked
760system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
761system.cpu0.iew.iewSquashCycles 5280938 # Number of cycles IEW is squashing
762system.cpu0.iew.iewBlockCycles 6404578 # Number of cycles IEW is blocking
763system.cpu0.iew.iewUnblockCycles 3121375 # Number of cycles IEW is unblocking
764system.cpu0.iew.iewDispatchedInsts 633914393 # Number of instructions dispatched to IQ
765system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
766system.cpu0.iew.iewDispLoadInsts 104115554 # Number of dispatched load instructions
767system.cpu0.iew.iewDispStoreInsts 90761559 # Number of dispatched store instructions
768system.cpu0.iew.iewDispNonSpecInsts 13746258 # Number of dispatched non-speculative instructions
769system.cpu0.iew.iewIQFullEvents 66239 # Number of times the IQ has become full, causing a stall
770system.cpu0.iew.iewLSQFullEvents 2987519 # Number of times the LSQ has become full, causing a stall
771system.cpu0.iew.memOrderViolationEvents 157768 # Number of memory order violations
772system.cpu0.iew.predictedTakenIncorrect 2095186 # Number of branches that were predicted taken incorrectly
773system.cpu0.iew.predictedNotTakenIncorrect 2941806 # Number of branches that were predicted not taken incorrectly
774system.cpu0.iew.branchMispredicts 5036992 # Number of branch mispredicts detected at execute
775system.cpu0.iew.iewExecutedInsts 614307958 # Number of executed instructions
776system.cpu0.iew.iewExecLoadInsts 103896068 # Number of load instructions executed
777system.cpu0.iew.iewExecSquashedInsts 7396426 # Number of squashed instructions skipped in execute
778system.cpu0.iew.exec_swp 0 # number of swp insts executed
779system.cpu0.iew.exec_nop 122600 # number of nop insts executed
780system.cpu0.iew.exec_refs 191163401 # number of memory reference insts executed
781system.cpu0.iew.exec_branches 115873704 # Number of branches executed
782system.cpu0.iew.exec_stores 87267333 # Number of stores executed
783system.cpu0.iew.exec_rate 0.790014 # Inst execution rate
784system.cpu0.iew.wb_sent 606266119 # cumulative count of insts sent to commit
785system.cpu0.iew.wb_count 605472936 # cumulative count of insts written-back
786system.cpu0.iew.wb_producers 293481694 # num instructions producing a value
787system.cpu0.iew.wb_consumers 481488998 # num instructions consuming a value
788system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
789system.cpu0.iew.wb_rate 0.778652 # insts written-back per cycle
790system.cpu0.iew.wb_fanout 0.609529 # average fanout of values written-back
791system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
792system.cpu0.commit.commitSquashedInsts 48614829 # The number of squashed insts skipped by commit
793system.cpu0.commit.commitNonSpecStalls 15852538 # The number of times commit has been forced to stall to communicate backwards
794system.cpu0.commit.branchMispredicts 4732048 # The number of times a branch was mispredicted
795system.cpu0.commit.committed_per_cycle::samples 745378077 # Number of insts commited each cycle
796system.cpu0.commit.committed_per_cycle::mean 0.775637 # Number of insts commited each cycle
797system.cpu0.commit.committed_per_cycle::stdev 1.576449 # Number of insts commited each cycle
798system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
799system.cpu0.commit.committed_per_cycle::0 493396348 66.19% 66.19% # Number of insts commited each cycle
800system.cpu0.commit.committed_per_cycle::1 129662648 17.40% 83.59% # Number of insts commited each cycle
801system.cpu0.commit.committed_per_cycle::2 56044004 7.52% 91.11% # Number of insts commited each cycle
802system.cpu0.commit.committed_per_cycle::3 18992920 2.55% 93.66% # Number of insts commited each cycle
803system.cpu0.commit.committed_per_cycle::4 13761945 1.85% 95.50% # Number of insts commited each cycle
804system.cpu0.commit.committed_per_cycle::5 9179296 1.23% 96.73% # Number of insts commited each cycle
805system.cpu0.commit.committed_per_cycle::6 6220016 0.83% 97.57% # Number of insts commited each cycle
806system.cpu0.commit.committed_per_cycle::7 3818014 0.51% 98.08% # Number of insts commited each cycle
807system.cpu0.commit.committed_per_cycle::8 14302886 1.92% 100.00% # Number of insts commited each cycle
808system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
809system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
810system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
811system.cpu0.commit.committed_per_cycle::total 745378077 # Number of insts commited each cycle
812system.cpu0.commit.committedInsts 491403423 # Number of instructions committed
813system.cpu0.commit.committedOps 578142958 # Number of ops (including micro ops) committed
814system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
815system.cpu0.commit.refs 176221889 # Number of memory references committed
816system.cpu0.commit.loads 91521232 # Number of loads committed
817system.cpu0.commit.membars 3904419 # Number of memory barriers committed
818system.cpu0.commit.branches 110044339 # Number of branches committed
819system.cpu0.commit.fp_insts 493876 # Number of committed floating point instructions.
820system.cpu0.commit.int_insts 530522943 # Number of committed integer instructions.
821system.cpu0.commit.function_calls 14584303 # Number of function calls committed.
822system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
823system.cpu0.commit.op_class_0::IntAlu 400598379 69.29% 69.29% # Class of committed instruction
824system.cpu0.commit.op_class_0::IntMult 1193753 0.21% 69.50% # Class of committed instruction
825system.cpu0.commit.op_class_0::IntDiv 57671 0.01% 69.51% # Class of committed instruction
826system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction
827system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction
828system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction
829system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction
830system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction
831system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction
832system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction
833system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction
834system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction
835system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction
836system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction
837system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.51% # Class of committed instruction
838system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.51% # Class of committed instruction
839system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.51% # Class of committed instruction
840system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.51% # Class of committed instruction
841system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.51% # Class of committed instruction
842system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.51% # Class of committed instruction
843system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.51% # Class of committed instruction
844system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.51% # Class of committed instruction
845system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.51% # Class of committed instruction
846system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.51% # Class of committed instruction
847system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.51% # Class of committed instruction
848system.cpu0.commit.op_class_0::SimdFloatMisc 71224 0.01% 69.52% # Class of committed instruction
849system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.52% # Class of committed instruction
850system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.52% # Class of committed instruction
851system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.52% # Class of committed instruction
852system.cpu0.commit.op_class_0::MemRead 91521232 15.83% 85.35% # Class of committed instruction
853system.cpu0.commit.op_class_0::MemWrite 84700657 14.65% 100.00% # Class of committed instruction
854system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
855system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
856system.cpu0.commit.op_class_0::total 578142958 # Class of committed instruction
857system.cpu0.commit.bw_lim_events 14302886 # number cycles where commit BW limit reached
858system.cpu0.rob.rob_reads 1353470869 # The number of ROB reads
859system.cpu0.rob.rob_writes 1262695982 # The number of ROB writes
860system.cpu0.timesIdled 1015060 # Number of times that the entire CPU went into an idle state and unscheduled itself
861system.cpu0.idleCycles 22995381 # Total number of cycles that the CPU has spent unscheduled due to idling
862system.cpu0.quiesceCycles 93993341722 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
863system.cpu0.committedInsts 491403423 # Number of Instructions Simulated
864system.cpu0.committedOps 578142958 # Number of Ops (including micro ops) Simulated
865system.cpu0.cpi 1.582388 # CPI: Cycles Per Instruction
866system.cpu0.cpi_total 1.582388 # CPI: Total CPI of All Threads
867system.cpu0.ipc 0.631956 # IPC: Instructions Per Cycle
868system.cpu0.ipc_total 0.631956 # IPC: Total IPC of All Threads
869system.cpu0.int_regfile_reads 725839901 # number of integer regfile reads
870system.cpu0.int_regfile_writes 430463320 # number of integer regfile writes
871system.cpu0.fp_regfile_reads 805500 # number of floating regfile reads
872system.cpu0.fp_regfile_writes 450680 # number of floating regfile writes
873system.cpu0.cc_regfile_reads 133543353 # number of cc regfile reads
874system.cpu0.cc_regfile_writes 134332816 # number of cc regfile writes
875system.cpu0.misc_regfile_reads 3015329804 # number of misc regfile reads
876system.cpu0.misc_regfile_writes 16059632 # number of misc regfile writes
877system.cpu0.dcache.tags.replacements 6141043 # number of replacements
878system.cpu0.dcache.tags.tagsinuse 503.422627 # Cycle average of tags in use
879system.cpu0.dcache.tags.total_refs 163818652 # Total number of references to valid blocks.
880system.cpu0.dcache.tags.sampled_refs 6141554 # Sample count of references to valid blocks.
881system.cpu0.dcache.tags.avg_refs 26.673811 # Average number of references to valid blocks.
882system.cpu0.dcache.tags.warmup_cycle 1929842500 # Cycle when the warmup percentage was hit.
883system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.422627 # Average occupied blocks per requestor
884system.cpu0.dcache.tags.occ_percent::cpu0.data 0.983247 # Average percentage of cache occupancy
885system.cpu0.dcache.tags.occ_percent::total 0.983247 # Average percentage of cache occupancy
886system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
887system.cpu0.dcache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
888system.cpu0.dcache.tags.age_task_id_blocks_1024::1 366 # Occupied blocks per task id
889system.cpu0.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id
890system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
891system.cpu0.dcache.tags.tag_accesses 365108655 # Number of tag accesses
892system.cpu0.dcache.tags.data_accesses 365108655 # Number of data accesses
893system.cpu0.dcache.ReadReq_hits::cpu0.data 84789793 # number of ReadReq hits
894system.cpu0.dcache.ReadReq_hits::total 84789793 # number of ReadReq hits
895system.cpu0.dcache.WriteReq_hits::cpu0.data 73815215 # number of WriteReq hits
896system.cpu0.dcache.WriteReq_hits::total 73815215 # number of WriteReq hits
897system.cpu0.dcache.SoftPFReq_hits::cpu0.data 223529 # number of SoftPFReq hits
898system.cpu0.dcache.SoftPFReq_hits::total 223529 # number of SoftPFReq hits
899system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 254722 # number of WriteInvalidateReq hits
900system.cpu0.dcache.WriteInvalidateReq_hits::total 254722 # number of WriteInvalidateReq hits
901system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1935633 # number of LoadLockedReq hits
902system.cpu0.dcache.LoadLockedReq_hits::total 1935633 # number of LoadLockedReq hits
903system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1977053 # number of StoreCondReq hits
904system.cpu0.dcache.StoreCondReq_hits::total 1977053 # number of StoreCondReq hits
905system.cpu0.dcache.demand_hits::cpu0.data 158605008 # number of demand (read+write) hits
906system.cpu0.dcache.demand_hits::total 158605008 # number of demand (read+write) hits
907system.cpu0.dcache.overall_hits::cpu0.data 158828537 # number of overall hits
908system.cpu0.dcache.overall_hits::total 158828537 # number of overall hits
909system.cpu0.dcache.ReadReq_misses::cpu0.data 6791004 # number of ReadReq misses
910system.cpu0.dcache.ReadReq_misses::total 6791004 # number of ReadReq misses
911system.cpu0.dcache.WriteReq_misses::cpu0.data 7631461 # number of WriteReq misses
912system.cpu0.dcache.WriteReq_misses::total 7631461 # number of WriteReq misses
913system.cpu0.dcache.SoftPFReq_misses::cpu0.data 739012 # number of SoftPFReq misses
914system.cpu0.dcache.SoftPFReq_misses::total 739012 # number of SoftPFReq misses
915system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 806083 # number of WriteInvalidateReq misses
916system.cpu0.dcache.WriteInvalidateReq_misses::total 806083 # number of WriteInvalidateReq misses
917system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 273207 # number of LoadLockedReq misses
918system.cpu0.dcache.LoadLockedReq_misses::total 273207 # number of LoadLockedReq misses
919system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195599 # number of StoreCondReq misses
920system.cpu0.dcache.StoreCondReq_misses::total 195599 # number of StoreCondReq misses
921system.cpu0.dcache.demand_misses::cpu0.data 14422465 # number of demand (read+write) misses
922system.cpu0.dcache.demand_misses::total 14422465 # number of demand (read+write) misses
923system.cpu0.dcache.overall_misses::cpu0.data 15161477 # number of overall misses
924system.cpu0.dcache.overall_misses::total 15161477 # number of overall misses
925system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 101570086088 # number of ReadReq miss cycles
926system.cpu0.dcache.ReadReq_miss_latency::total 101570086088 # number of ReadReq miss cycles
927system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 139050346077 # number of WriteReq miss cycles
928system.cpu0.dcache.WriteReq_miss_latency::total 139050346077 # number of WriteReq miss cycles
929system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 37625975422 # number of WriteInvalidateReq miss cycles
930system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 37625975422 # number of WriteInvalidateReq miss cycles
931system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3995007021 # number of LoadLockedReq miss cycles
932system.cpu0.dcache.LoadLockedReq_miss_latency::total 3995007021 # number of LoadLockedReq miss cycles
933system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4127543324 # number of StoreCondReq miss cycles
934system.cpu0.dcache.StoreCondReq_miss_latency::total 4127543324 # number of StoreCondReq miss cycles
935system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2928500 # number of StoreCondFailReq miss cycles
936system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2928500 # number of StoreCondFailReq miss cycles
937system.cpu0.dcache.demand_miss_latency::cpu0.data 240620432165 # number of demand (read+write) miss cycles
938system.cpu0.dcache.demand_miss_latency::total 240620432165 # number of demand (read+write) miss cycles
939system.cpu0.dcache.overall_miss_latency::cpu0.data 240620432165 # number of overall miss cycles
940system.cpu0.dcache.overall_miss_latency::total 240620432165 # number of overall miss cycles
941system.cpu0.dcache.ReadReq_accesses::cpu0.data 91580797 # number of ReadReq accesses(hits+misses)
942system.cpu0.dcache.ReadReq_accesses::total 91580797 # number of ReadReq accesses(hits+misses)
943system.cpu0.dcache.WriteReq_accesses::cpu0.data 81446676 # number of WriteReq accesses(hits+misses)
944system.cpu0.dcache.WriteReq_accesses::total 81446676 # number of WriteReq accesses(hits+misses)
945system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 962541 # number of SoftPFReq accesses(hits+misses)
946system.cpu0.dcache.SoftPFReq_accesses::total 962541 # number of SoftPFReq accesses(hits+misses)
947system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1060805 # number of WriteInvalidateReq accesses(hits+misses)
948system.cpu0.dcache.WriteInvalidateReq_accesses::total 1060805 # number of WriteInvalidateReq accesses(hits+misses)
949system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2208840 # number of LoadLockedReq accesses(hits+misses)
950system.cpu0.dcache.LoadLockedReq_accesses::total 2208840 # number of LoadLockedReq accesses(hits+misses)
951system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2172652 # number of StoreCondReq accesses(hits+misses)
952system.cpu0.dcache.StoreCondReq_accesses::total 2172652 # number of StoreCondReq accesses(hits+misses)
953system.cpu0.dcache.demand_accesses::cpu0.data 173027473 # number of demand (read+write) accesses
954system.cpu0.dcache.demand_accesses::total 173027473 # number of demand (read+write) accesses
955system.cpu0.dcache.overall_accesses::cpu0.data 173990014 # number of overall (read+write) accesses
956system.cpu0.dcache.overall_accesses::total 173990014 # number of overall (read+write) accesses
957system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.074153 # miss rate for ReadReq accesses
958system.cpu0.dcache.ReadReq_miss_rate::total 0.074153 # miss rate for ReadReq accesses
959system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.093699 # miss rate for WriteReq accesses
960system.cpu0.dcache.WriteReq_miss_rate::total 0.093699 # miss rate for WriteReq accesses
961system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.767772 # miss rate for SoftPFReq accesses
962system.cpu0.dcache.SoftPFReq_miss_rate::total 0.767772 # miss rate for SoftPFReq accesses
963system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.759879 # miss rate for WriteInvalidateReq accesses
964system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.759879 # miss rate for WriteInvalidateReq accesses
965system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.123688 # miss rate for LoadLockedReq accesses
966system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.123688 # miss rate for LoadLockedReq accesses
967system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.090028 # miss rate for StoreCondReq accesses
968system.cpu0.dcache.StoreCondReq_miss_rate::total 0.090028 # miss rate for StoreCondReq accesses
969system.cpu0.dcache.demand_miss_rate::cpu0.data 0.083354 # miss rate for demand accesses
970system.cpu0.dcache.demand_miss_rate::total 0.083354 # miss rate for demand accesses
971system.cpu0.dcache.overall_miss_rate::cpu0.data 0.087140 # miss rate for overall accesses
972system.cpu0.dcache.overall_miss_rate::total 0.087140 # miss rate for overall accesses
973system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14956.564020 # average ReadReq miss latency
974system.cpu0.dcache.ReadReq_avg_miss_latency::total 14956.564020 # average ReadReq miss latency
975system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18220.671779 # average WriteReq miss latency
976system.cpu0.dcache.WriteReq_avg_miss_latency::total 18220.671779 # average WriteReq miss latency
977system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 46677.544896 # average WriteInvalidateReq miss latency
978system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 46677.544896 # average WriteInvalidateReq miss latency
979system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14622.637857 # average LoadLockedReq miss latency
980system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14622.637857 # average LoadLockedReq miss latency
981system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21102.067618 # average StoreCondReq miss latency
982system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21102.067618 # average StoreCondReq miss latency
983system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
984system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
985system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16683.724465 # average overall miss latency
986system.cpu0.dcache.demand_avg_miss_latency::total 16683.724465 # average overall miss latency
987system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15870.513946 # average overall miss latency
988system.cpu0.dcache.overall_avg_miss_latency::total 15870.513946 # average overall miss latency
989system.cpu0.dcache.blocked_cycles::no_mshrs 10994171 # number of cycles access was blocked
990system.cpu0.dcache.blocked_cycles::no_targets 20243365 # number of cycles access was blocked
991system.cpu0.dcache.blocked::no_mshrs 733732 # number of cycles access was blocked
992system.cpu0.dcache.blocked::no_targets 746062 # number of cycles access was blocked
993system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.983906 # average number of cycles each access was blocked
994system.cpu0.dcache.avg_blocked_cycles::no_targets 27.133623 # average number of cycles each access was blocked
995system.cpu0.dcache.fast_writes 0 # number of fast writes performed
996system.cpu0.dcache.cache_copies 0 # number of cache copies performed
997system.cpu0.dcache.writebacks::writebacks 4196368 # number of writebacks
998system.cpu0.dcache.writebacks::total 4196368 # number of writebacks
999system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3475469 # number of ReadReq MSHR hits
1000system.cpu0.dcache.ReadReq_mshr_hits::total 3475469 # number of ReadReq MSHR hits
1001system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6119501 # number of WriteReq MSHR hits
1002system.cpu0.dcache.WriteReq_mshr_hits::total 6119501 # number of WriteReq MSHR hits
1003system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 4173 # number of WriteInvalidateReq MSHR hits
1004system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4173 # number of WriteInvalidateReq MSHR hits
1005system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 141236 # number of LoadLockedReq MSHR hits
1006system.cpu0.dcache.LoadLockedReq_mshr_hits::total 141236 # number of LoadLockedReq MSHR hits
1007system.cpu0.dcache.demand_mshr_hits::cpu0.data 9594970 # number of demand (read+write) MSHR hits
1008system.cpu0.dcache.demand_mshr_hits::total 9594970 # number of demand (read+write) MSHR hits
1009system.cpu0.dcache.overall_mshr_hits::cpu0.data 9594970 # number of overall MSHR hits
1010system.cpu0.dcache.overall_mshr_hits::total 9594970 # number of overall MSHR hits
1011system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3315535 # number of ReadReq MSHR misses
1012system.cpu0.dcache.ReadReq_mshr_misses::total 3315535 # number of ReadReq MSHR misses
1013system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1511960 # number of WriteReq MSHR misses
1014system.cpu0.dcache.WriteReq_mshr_misses::total 1511960 # number of WriteReq MSHR misses
1015system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 732291 # number of SoftPFReq MSHR misses
1016system.cpu0.dcache.SoftPFReq_mshr_misses::total 732291 # number of SoftPFReq MSHR misses
1017system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 801910 # number of WriteInvalidateReq MSHR misses
1018system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 801910 # number of WriteInvalidateReq MSHR misses
1019system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 131971 # number of LoadLockedReq MSHR misses
1020system.cpu0.dcache.LoadLockedReq_mshr_misses::total 131971 # number of LoadLockedReq MSHR misses
1021system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195594 # number of StoreCondReq MSHR misses
1022system.cpu0.dcache.StoreCondReq_mshr_misses::total 195594 # number of StoreCondReq MSHR misses
1023system.cpu0.dcache.demand_mshr_misses::cpu0.data 4827495 # number of demand (read+write) MSHR misses
1024system.cpu0.dcache.demand_mshr_misses::total 4827495 # number of demand (read+write) MSHR misses
1025system.cpu0.dcache.overall_mshr_misses::cpu0.data 5559786 # number of overall MSHR misses
1026system.cpu0.dcache.overall_mshr_misses::total 5559786 # number of overall MSHR misses
1027system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31767 # number of ReadReq MSHR uncacheable
1028system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31767 # number of ReadReq MSHR uncacheable
1029system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31179 # number of WriteReq MSHR uncacheable
1030system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31179 # number of WriteReq MSHR uncacheable
1031system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62946 # number of overall MSHR uncacheable misses
1032system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62946 # number of overall MSHR uncacheable misses
1033system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45402822425 # number of ReadReq MSHR miss cycles
1034system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45402822425 # number of ReadReq MSHR miss cycles
1035system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 28839272084 # number of WriteReq MSHR miss cycles
1036system.cpu0.dcache.WriteReq_mshr_miss_latency::total 28839272084 # number of WriteReq MSHR miss cycles
1037system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16627256811 # number of SoftPFReq MSHR miss cycles
1038system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16627256811 # number of SoftPFReq MSHR miss cycles
1039system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 36253693272 # number of WriteInvalidateReq MSHR miss cycles
1040system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 36253693272 # number of WriteInvalidateReq MSHR miss cycles
1041system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1734403771 # number of LoadLockedReq MSHR miss cycles
1042system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1734403771 # number of LoadLockedReq MSHR miss cycles
1043system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3825076676 # number of StoreCondReq MSHR miss cycles
1044system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3825076676 # number of StoreCondReq MSHR miss cycles
1045system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2835500 # number of StoreCondFailReq MSHR miss cycles
1046system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2835500 # number of StoreCondFailReq MSHR miss cycles
1047system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 74242094509 # number of demand (read+write) MSHR miss cycles
1048system.cpu0.dcache.demand_mshr_miss_latency::total 74242094509 # number of demand (read+write) MSHR miss cycles
1049system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 90869351320 # number of overall MSHR miss cycles
1050system.cpu0.dcache.overall_mshr_miss_latency::total 90869351320 # number of overall MSHR miss cycles
1051system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5616435750 # number of ReadReq MSHR uncacheable cycles
1052system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5616435750 # number of ReadReq MSHR uncacheable cycles
1053system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5304462017 # number of WriteReq MSHR uncacheable cycles
1054system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5304462017 # number of WriteReq MSHR uncacheable cycles
1055system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10920897767 # number of overall MSHR uncacheable cycles
1056system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10920897767 # number of overall MSHR uncacheable cycles
1057system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036203 # mshr miss rate for ReadReq accesses
1058system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036203 # mshr miss rate for ReadReq accesses
1059system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018564 # mshr miss rate for WriteReq accesses
1060system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018564 # mshr miss rate for WriteReq accesses
1061system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.760789 # mshr miss rate for SoftPFReq accesses
1062system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.760789 # mshr miss rate for SoftPFReq accesses
1063system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.755945 # mshr miss rate for WriteInvalidateReq accesses
1064system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.755945 # mshr miss rate for WriteInvalidateReq accesses
1065system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059747 # mshr miss rate for LoadLockedReq accesses
1066system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059747 # mshr miss rate for LoadLockedReq accesses
1067system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.090025 # mshr miss rate for StoreCondReq accesses
1068system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.090025 # mshr miss rate for StoreCondReq accesses
1069system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027900 # mshr miss rate for demand accesses
1070system.cpu0.dcache.demand_mshr_miss_rate::total 0.027900 # mshr miss rate for demand accesses
1071system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031955 # mshr miss rate for overall accesses
1072system.cpu0.dcache.overall_mshr_miss_rate::total 0.031955 # mshr miss rate for overall accesses
1073system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13693.965657 # average ReadReq mshr miss latency
1074system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13693.965657 # average ReadReq mshr miss latency
1075system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19074.097254 # average WriteReq mshr miss latency
1076system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19074.097254 # average WriteReq mshr miss latency
1077system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22705.805221 # average SoftPFReq mshr miss latency
1078system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22705.805221 # average SoftPFReq mshr miss latency
1079system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 45209.179674 # average WriteInvalidateReq mshr miss latency
1080system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 45209.179674 # average WriteInvalidateReq mshr miss latency
1081system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13142.309833 # average LoadLockedReq mshr miss latency
1082system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13142.309833 # average LoadLockedReq mshr miss latency
1083system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19556.206612 # average StoreCondReq mshr miss latency
1084system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19556.206612 # average StoreCondReq mshr miss latency
1085system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
1086system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
1087system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15379.010130 # average overall mshr miss latency
1088system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15379.010130 # average overall mshr miss latency
1089system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16344.037580 # average overall mshr miss latency
1090system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16344.037580 # average overall mshr miss latency
1091system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176800.949098 # average ReadReq mshr uncacheable latency
1092system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176800.949098 # average ReadReq mshr uncacheable latency
1093system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170129.318355 # average WriteReq mshr uncacheable latency
1094system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170129.318355 # average WriteReq mshr uncacheable latency
1095system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 173496.294713 # average overall mshr uncacheable latency
1096system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 173496.294713 # average overall mshr uncacheable latency
1097system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1098system.cpu0.icache.tags.replacements 6182706 # number of replacements
1099system.cpu0.icache.tags.tagsinuse 511.960451 # Cycle average of tags in use
1100system.cpu0.icache.tags.total_refs 218406038 # Total number of references to valid blocks.
1101system.cpu0.icache.tags.sampled_refs 6183218 # Sample count of references to valid blocks.
1102system.cpu0.icache.tags.avg_refs 35.322390 # Average number of references to valid blocks.
1103system.cpu0.icache.tags.warmup_cycle 14060425250 # Cycle when the warmup percentage was hit.
1104system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960451 # Average occupied blocks per requestor
1105system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999923 # Average percentage of cache occupancy
1106system.cpu0.icache.tags.occ_percent::total 0.999923 # Average percentage of cache occupancy
1107system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
1108system.cpu0.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id
1109system.cpu0.icache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id
1110system.cpu0.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id
1111system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
1112system.cpu0.icache.tags.tag_accesses 456025787 # Number of tag accesses
1113system.cpu0.icache.tags.data_accesses 456025787 # Number of data accesses
1114system.cpu0.icache.ReadReq_hits::cpu0.inst 218406038 # number of ReadReq hits
1115system.cpu0.icache.ReadReq_hits::total 218406038 # number of ReadReq hits
1116system.cpu0.icache.demand_hits::cpu0.inst 218406038 # number of demand (read+write) hits
1117system.cpu0.icache.demand_hits::total 218406038 # number of demand (read+write) hits
1118system.cpu0.icache.overall_hits::cpu0.inst 218406038 # number of overall hits
1119system.cpu0.icache.overall_hits::total 218406038 # number of overall hits
1120system.cpu0.icache.ReadReq_misses::cpu0.inst 6515233 # number of ReadReq misses
1121system.cpu0.icache.ReadReq_misses::total 6515233 # number of ReadReq misses
1122system.cpu0.icache.demand_misses::cpu0.inst 6515233 # number of demand (read+write) misses
1123system.cpu0.icache.demand_misses::total 6515233 # number of demand (read+write) misses
1124system.cpu0.icache.overall_misses::cpu0.inst 6515233 # number of overall misses
1125system.cpu0.icache.overall_misses::total 6515233 # number of overall misses
1126system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 69121769887 # number of ReadReq miss cycles
1127system.cpu0.icache.ReadReq_miss_latency::total 69121769887 # number of ReadReq miss cycles
1128system.cpu0.icache.demand_miss_latency::cpu0.inst 69121769887 # number of demand (read+write) miss cycles
1129system.cpu0.icache.demand_miss_latency::total 69121769887 # number of demand (read+write) miss cycles
1130system.cpu0.icache.overall_miss_latency::cpu0.inst 69121769887 # number of overall miss cycles
1131system.cpu0.icache.overall_miss_latency::total 69121769887 # number of overall miss cycles
1132system.cpu0.icache.ReadReq_accesses::cpu0.inst 224921271 # number of ReadReq accesses(hits+misses)
1133system.cpu0.icache.ReadReq_accesses::total 224921271 # number of ReadReq accesses(hits+misses)
1134system.cpu0.icache.demand_accesses::cpu0.inst 224921271 # number of demand (read+write) accesses
1135system.cpu0.icache.demand_accesses::total 224921271 # number of demand (read+write) accesses
1136system.cpu0.icache.overall_accesses::cpu0.inst 224921271 # number of overall (read+write) accesses
1137system.cpu0.icache.overall_accesses::total 224921271 # number of overall (read+write) accesses
1138system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028967 # miss rate for ReadReq accesses
1139system.cpu0.icache.ReadReq_miss_rate::total 0.028967 # miss rate for ReadReq accesses
1140system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028967 # miss rate for demand accesses
1141system.cpu0.icache.demand_miss_rate::total 0.028967 # miss rate for demand accesses
1142system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028967 # miss rate for overall accesses
1143system.cpu0.icache.overall_miss_rate::total 0.028967 # miss rate for overall accesses
1144system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10609.255246 # average ReadReq miss latency
1145system.cpu0.icache.ReadReq_avg_miss_latency::total 10609.255246 # average ReadReq miss latency
1146system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10609.255246 # average overall miss latency
1147system.cpu0.icache.demand_avg_miss_latency::total 10609.255246 # average overall miss latency
1148system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10609.255246 # average overall miss latency
1149system.cpu0.icache.overall_avg_miss_latency::total 10609.255246 # average overall miss latency
1150system.cpu0.icache.blocked_cycles::no_mshrs 9343070 # number of cycles access was blocked
1151system.cpu0.icache.blocked_cycles::no_targets 429 # number of cycles access was blocked
1152system.cpu0.icache.blocked::no_mshrs 716553 # number of cycles access was blocked
1153system.cpu0.icache.blocked::no_targets 9 # number of cycles access was blocked
1154system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.038910 # average number of cycles each access was blocked
1155system.cpu0.icache.avg_blocked_cycles::no_targets 47.666667 # average number of cycles each access was blocked
1156system.cpu0.icache.fast_writes 0 # number of fast writes performed
1157system.cpu0.icache.cache_copies 0 # number of cache copies performed
1158system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 331988 # number of ReadReq MSHR hits
1159system.cpu0.icache.ReadReq_mshr_hits::total 331988 # number of ReadReq MSHR hits
1160system.cpu0.icache.demand_mshr_hits::cpu0.inst 331988 # number of demand (read+write) MSHR hits
1161system.cpu0.icache.demand_mshr_hits::total 331988 # number of demand (read+write) MSHR hits
1162system.cpu0.icache.overall_mshr_hits::cpu0.inst 331988 # number of overall MSHR hits
1163system.cpu0.icache.overall_mshr_hits::total 331988 # number of overall MSHR hits
1164system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6183245 # number of ReadReq MSHR misses
1165system.cpu0.icache.ReadReq_mshr_misses::total 6183245 # number of ReadReq MSHR misses
1166system.cpu0.icache.demand_mshr_misses::cpu0.inst 6183245 # number of demand (read+write) MSHR misses
1167system.cpu0.icache.demand_mshr_misses::total 6183245 # number of demand (read+write) MSHR misses
1168system.cpu0.icache.overall_mshr_misses::cpu0.inst 6183245 # number of overall MSHR misses
1169system.cpu0.icache.overall_mshr_misses::total 6183245 # number of overall MSHR misses
1170system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable
1171system.cpu0.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable
1172system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses
1173system.cpu0.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses
1174system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 59487086557 # number of ReadReq MSHR miss cycles
1175system.cpu0.icache.ReadReq_mshr_miss_latency::total 59487086557 # number of ReadReq MSHR miss cycles
1176system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 59487086557 # number of demand (read+write) MSHR miss cycles
1177system.cpu0.icache.demand_mshr_miss_latency::total 59487086557 # number of demand (read+write) MSHR miss cycles
1178system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 59487086557 # number of overall MSHR miss cycles
1179system.cpu0.icache.overall_mshr_miss_latency::total 59487086557 # number of overall MSHR miss cycles
1180system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1881164498 # number of ReadReq MSHR uncacheable cycles
1181system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1881164498 # number of ReadReq MSHR uncacheable cycles
1182system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1881164498 # number of overall MSHR uncacheable cycles
1183system.cpu0.icache.overall_mshr_uncacheable_latency::total 1881164498 # number of overall MSHR uncacheable cycles
1184system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027491 # mshr miss rate for ReadReq accesses
1185system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027491 # mshr miss rate for ReadReq accesses
1186system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027491 # mshr miss rate for demand accesses
1187system.cpu0.icache.demand_mshr_miss_rate::total 0.027491 # mshr miss rate for demand accesses
1188system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027491 # mshr miss rate for overall accesses
1189system.cpu0.icache.overall_mshr_miss_rate::total 0.027491 # mshr miss rate for overall accesses
1190system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9620.690520 # average ReadReq mshr miss latency
1191system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9620.690520 # average ReadReq mshr miss latency
1192system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9620.690520 # average overall mshr miss latency
1193system.cpu0.icache.demand_avg_mshr_miss_latency::total 9620.690520 # average overall mshr miss latency
1194system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9620.690520 # average overall mshr miss latency
1195system.cpu0.icache.overall_avg_mshr_miss_latency::total 9620.690520 # average overall mshr miss latency
1196system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88342.467268 # average ReadReq mshr uncacheable latency
1197system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88342.467268 # average ReadReq mshr uncacheable latency
1198system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88342.467268 # average overall mshr uncacheable latency
1199system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88342.467268 # average overall mshr uncacheable latency
1200system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1201system.cpu0.l2cache.prefetcher.num_hwpf_issued 7927934 # number of hwpf issued
1202system.cpu0.l2cache.prefetcher.pfIdentified 8230587 # number of prefetch candidates identified
1203system.cpu0.l2cache.prefetcher.pfBufferHit 262068 # number of redundant prefetches already in prefetch queue
1204system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
1205system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
1206system.cpu0.l2cache.prefetcher.pfSpanPage 1052933 # number of prefetches not generated due to page crossing
1207system.cpu0.l2cache.tags.replacements 2785828 # number of replacements
1208system.cpu0.l2cache.tags.tagsinuse 16244.844688 # Cycle average of tags in use
1209system.cpu0.l2cache.tags.total_refs 12810731 # Total number of references to valid blocks.
1210system.cpu0.l2cache.tags.sampled_refs 2801890 # Sample count of references to valid blocks.
1211system.cpu0.l2cache.tags.avg_refs 4.572175 # Average number of references to valid blocks.
1212system.cpu0.l2cache.tags.warmup_cycle 2265530500 # Cycle when the warmup percentage was hit.
1213system.cpu0.l2cache.tags.occ_blocks::writebacks 7084.641278 # Average occupied blocks per requestor
1214system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 80.581753 # Average occupied blocks per requestor
1215system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 91.908936 # Average occupied blocks per requestor
1216system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4232.509595 # Average occupied blocks per requestor
1217system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3861.356831 # Average occupied blocks per requestor
1218system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 893.846295 # Average occupied blocks per requestor
1219system.cpu0.l2cache.tags.occ_percent::writebacks 0.432412 # Average percentage of cache occupancy
1220system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004918 # Average percentage of cache occupancy
1221system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005610 # Average percentage of cache occupancy
1222system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.258332 # Average percentage of cache occupancy
1223system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.235679 # Average percentage of cache occupancy
1224system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.054556 # Average percentage of cache occupancy
1225system.cpu0.l2cache.tags.occ_percent::total 0.991507 # Average percentage of cache occupancy
1226system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1296 # Occupied blocks per task id
1227system.cpu0.l2cache.tags.occ_task_id_blocks::1023 85 # Occupied blocks per task id
1228system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14681 # Occupied blocks per task id
1229system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 27 # Occupied blocks per task id
1230system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 251 # Occupied blocks per task id
1231system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 612 # Occupied blocks per task id
1232system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 406 # Occupied blocks per task id
1233system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
1234system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 47 # Occupied blocks per task id
1235system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id
1236system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id
1237system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id
1238system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1442 # Occupied blocks per task id
1239system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5343 # Occupied blocks per task id
1240system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4502 # Occupied blocks per task id
1241system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3254 # Occupied blocks per task id
1242system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.079102 # Percentage of cache occupancy per task id
1243system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id
1244system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.896057 # Percentage of cache occupancy per task id
1245system.cpu0.l2cache.tags.tag_accesses 290229122 # Number of tag accesses
1246system.cpu0.l2cache.tags.data_accesses 290229122 # Number of data accesses
1247system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 541748 # number of ReadReq hits
1248system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 180817 # number of ReadReq hits
1249system.cpu0.l2cache.ReadReq_hits::cpu0.inst 5534153 # number of ReadReq hits
1250system.cpu0.l2cache.ReadReq_hits::cpu0.data 3094433 # number of ReadReq hits
1251system.cpu0.l2cache.ReadReq_hits::total 9351151 # number of ReadReq hits
1252system.cpu0.l2cache.Writeback_hits::writebacks 4196351 # number of Writeback hits
1253system.cpu0.l2cache.Writeback_hits::total 4196351 # number of Writeback hits
1254system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 207942 # number of WriteInvalidateReq hits
1255system.cpu0.l2cache.WriteInvalidateReq_hits::total 207942 # number of WriteInvalidateReq hits
1256system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 120308 # number of UpgradeReq hits
1257system.cpu0.l2cache.UpgradeReq_hits::total 120308 # number of UpgradeReq hits
1258system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 36466 # number of SCUpgradeReq hits
1259system.cpu0.l2cache.SCUpgradeReq_hits::total 36466 # number of SCUpgradeReq hits
1260system.cpu0.l2cache.ReadExReq_hits::cpu0.data 968728 # number of ReadExReq hits
1261system.cpu0.l2cache.ReadExReq_hits::total 968728 # number of ReadExReq hits
1262system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 541748 # number of demand (read+write) hits
1263system.cpu0.l2cache.demand_hits::cpu0.itb.walker 180817 # number of demand (read+write) hits
1264system.cpu0.l2cache.demand_hits::cpu0.inst 5534153 # number of demand (read+write) hits
1265system.cpu0.l2cache.demand_hits::cpu0.data 4063161 # number of demand (read+write) hits
1266system.cpu0.l2cache.demand_hits::total 10319879 # number of demand (read+write) hits
1267system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 541748 # number of overall hits
1268system.cpu0.l2cache.overall_hits::cpu0.itb.walker 180817 # number of overall hits
1269system.cpu0.l2cache.overall_hits::cpu0.inst 5534153 # number of overall hits
1270system.cpu0.l2cache.overall_hits::cpu0.data 4063161 # number of overall hits
1271system.cpu0.l2cache.overall_hits::total 10319879 # number of overall hits
1272system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12343 # number of ReadReq misses
1273system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9059 # number of ReadReq misses
1274system.cpu0.l2cache.ReadReq_misses::cpu0.inst 649075 # number of ReadReq misses
1275system.cpu0.l2cache.ReadReq_misses::cpu0.data 1080475 # number of ReadReq misses
1276system.cpu0.l2cache.ReadReq_misses::total 1750952 # number of ReadReq misses
1277system.cpu0.l2cache.Writeback_misses::writebacks 10 # number of Writeback misses
1278system.cpu0.l2cache.Writeback_misses::total 10 # number of Writeback misses
1279system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 592445 # number of WriteInvalidateReq misses
1280system.cpu0.l2cache.WriteInvalidateReq_misses::total 592445 # number of WriteInvalidateReq misses
1281system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 136302 # number of UpgradeReq misses
1282system.cpu0.l2cache.UpgradeReq_misses::total 136302 # number of UpgradeReq misses
1283system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 159123 # number of SCUpgradeReq misses
1284system.cpu0.l2cache.SCUpgradeReq_misses::total 159123 # number of SCUpgradeReq misses
1285system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses
1286system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses
1287system.cpu0.l2cache.ReadExReq_misses::cpu0.data 299943 # number of ReadExReq misses
1288system.cpu0.l2cache.ReadExReq_misses::total 299943 # number of ReadExReq misses
1289system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12343 # number of demand (read+write) misses
1290system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9059 # number of demand (read+write) misses
1291system.cpu0.l2cache.demand_misses::cpu0.inst 649075 # number of demand (read+write) misses
1292system.cpu0.l2cache.demand_misses::cpu0.data 1380418 # number of demand (read+write) misses
1293system.cpu0.l2cache.demand_misses::total 2050895 # number of demand (read+write) misses
1294system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12343 # number of overall misses
1295system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9059 # number of overall misses
1296system.cpu0.l2cache.overall_misses::cpu0.inst 649075 # number of overall misses
1297system.cpu0.l2cache.overall_misses::cpu0.data 1380418 # number of overall misses
1298system.cpu0.l2cache.overall_misses::total 2050895 # number of overall misses
1299system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 496433453 # number of ReadReq miss cycles
1300system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 403677084 # number of ReadReq miss cycles
1301system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 20306210078 # number of ReadReq miss cycles
1302system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 39087285353 # number of ReadReq miss cycles
1303system.cpu0.l2cache.ReadReq_miss_latency::total 60293605968 # number of ReadReq miss cycles
1304system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 252817543 # number of WriteInvalidateReq miss cycles
1305system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 252817543 # number of WriteInvalidateReq miss cycles
1306system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2986484321 # number of UpgradeReq miss cycles
1307system.cpu0.l2cache.UpgradeReq_miss_latency::total 2986484321 # number of UpgradeReq miss cycles
1308system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3304695138 # number of SCUpgradeReq miss cycles
1309system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3304695138 # number of SCUpgradeReq miss cycles
1310system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2772999 # number of SCUpgradeFailReq miss cycles
1311system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2772999 # number of SCUpgradeFailReq miss cycles
1312system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16034165055 # number of ReadExReq miss cycles
1313system.cpu0.l2cache.ReadExReq_miss_latency::total 16034165055 # number of ReadExReq miss cycles
1314system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 496433453 # number of demand (read+write) miss cycles
1315system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 403677084 # number of demand (read+write) miss cycles
1316system.cpu0.l2cache.demand_miss_latency::cpu0.inst 20306210078 # number of demand (read+write) miss cycles
1317system.cpu0.l2cache.demand_miss_latency::cpu0.data 55121450408 # number of demand (read+write) miss cycles
1318system.cpu0.l2cache.demand_miss_latency::total 76327771023 # number of demand (read+write) miss cycles
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1322system.cpu0.l2cache.overall_miss_latency::cpu0.data 55121450408 # number of overall miss cycles
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1325system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 189876 # number of ReadReq accesses(hits+misses)
1326system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 6183228 # number of ReadReq accesses(hits+misses)
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1328system.cpu0.l2cache.ReadReq_accesses::total 11102103 # number of ReadReq accesses(hits+misses)
1329system.cpu0.l2cache.Writeback_accesses::writebacks 4196361 # number of Writeback accesses(hits+misses)
1330system.cpu0.l2cache.Writeback_accesses::total 4196361 # number of Writeback accesses(hits+misses)
1331system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 800387 # number of WriteInvalidateReq accesses(hits+misses)
1332system.cpu0.l2cache.WriteInvalidateReq_accesses::total 800387 # number of WriteInvalidateReq accesses(hits+misses)
1333system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 256610 # number of UpgradeReq accesses(hits+misses)
1334system.cpu0.l2cache.UpgradeReq_accesses::total 256610 # number of UpgradeReq accesses(hits+misses)
1335system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 195589 # number of SCUpgradeReq accesses(hits+misses)
1336system.cpu0.l2cache.SCUpgradeReq_accesses::total 195589 # number of SCUpgradeReq accesses(hits+misses)
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1338system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses)
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1347system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 189876 # number of overall (read+write) accesses
1348system.cpu0.l2cache.overall_accesses::cpu0.inst 6183228 # number of overall (read+write) accesses
1349system.cpu0.l2cache.overall_accesses::cpu0.data 5443579 # number of overall (read+write) accesses
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1352system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.047710 # miss rate for ReadReq accesses
1353system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.104973 # miss rate for ReadReq accesses
1354system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.258802 # miss rate for ReadReq accesses
1355system.cpu0.l2cache.ReadReq_miss_rate::total 0.157714 # miss rate for ReadReq accesses
1356system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses
1357system.cpu0.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses
1358system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.740198 # miss rate for WriteInvalidateReq accesses
1359system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.740198 # miss rate for WriteInvalidateReq accesses
1360system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.531164 # miss rate for UpgradeReq accesses
1361system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.531164 # miss rate for UpgradeReq accesses
1362system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.813558 # miss rate for SCUpgradeReq accesses
1363system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.813558 # miss rate for SCUpgradeReq accesses
1364system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses
1365system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
1366system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.236423 # miss rate for ReadExReq accesses
1367system.cpu0.l2cache.ReadExReq_miss_rate::total 0.236423 # miss rate for ReadExReq accesses
1368system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022276 # miss rate for demand accesses
1369system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.047710 # miss rate for demand accesses
1370system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.104973 # miss rate for demand accesses
1371system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.253586 # miss rate for demand accesses
1372system.cpu0.l2cache.demand_miss_rate::total 0.165786 # miss rate for demand accesses
1373system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022276 # miss rate for overall accesses
1374system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.047710 # miss rate for overall accesses
1375system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.104973 # miss rate for overall accesses
1376system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.253586 # miss rate for overall accesses
1377system.cpu0.l2cache.overall_miss_rate::total 0.165786 # miss rate for overall accesses
1378system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 40219.837398 # average ReadReq miss latency
1379system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 44560.887957 # average ReadReq miss latency
1380system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 31284.843936 # average ReadReq miss latency
1381system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 36176.020133 # average ReadReq miss latency
1382system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34434.756617 # average ReadReq miss latency
1383system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 426.735888 # average WriteInvalidateReq miss latency
1384system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 426.735888 # average WriteInvalidateReq miss latency
1385system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21910.788697 # average UpgradeReq miss latency
1386system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21910.788697 # average UpgradeReq miss latency
1387system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20768.180200 # average SCUpgradeReq miss latency
1388system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20768.180200 # average SCUpgradeReq miss latency
1389system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 554599.800000 # average SCUpgradeFailReq miss latency
1390system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 554599.800000 # average SCUpgradeFailReq miss latency
1391system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 53457.373751 # average ReadExReq miss latency
1392system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 53457.373751 # average ReadExReq miss latency
1393system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 40219.837398 # average overall miss latency
1394system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 44560.887957 # average overall miss latency
1395system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31284.843936 # average overall miss latency
1396system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 39930.984968 # average overall miss latency
1397system.cpu0.l2cache.demand_avg_miss_latency::total 37216.810721 # average overall miss latency
1398system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 40219.837398 # average overall miss latency
1399system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 44560.887957 # average overall miss latency
1400system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31284.843936 # average overall miss latency
1401system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 39930.984968 # average overall miss latency
1402system.cpu0.l2cache.overall_avg_miss_latency::total 37216.810721 # average overall miss latency
1403system.cpu0.l2cache.blocked_cycles::no_mshrs 70 # number of cycles access was blocked
1404system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1405system.cpu0.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked
1406system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1407system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 35 # average number of cycles each access was blocked
1408system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1409system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
1410system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
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1412system.cpu0.l2cache.writebacks::total 1537125 # number of writebacks
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1418system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 18 # number of WriteInvalidateReq MSHR hits
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1430system.cpu0.l2cache.overall_mshr_hits::cpu0.data 26527 # number of overall MSHR hits
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1435system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 1076438 # number of ReadReq MSHR misses
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1437system.cpu0.l2cache.Writeback_mshr_misses::writebacks 10 # number of Writeback MSHR misses
1438system.cpu0.l2cache.Writeback_mshr_misses::total 10 # number of Writeback MSHR misses
1439system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 790245 # number of HardPFReq MSHR misses
1440system.cpu0.l2cache.HardPFReq_mshr_misses::total 790245 # number of HardPFReq MSHR misses
1441system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 592427 # number of WriteInvalidateReq MSHR misses
1442system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 592427 # number of WriteInvalidateReq MSHR misses
1443system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 136302 # number of UpgradeReq MSHR misses
1444system.cpu0.l2cache.UpgradeReq_mshr_misses::total 136302 # number of UpgradeReq MSHR misses
1445system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 159123 # number of SCUpgradeReq MSHR misses
1446system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 159123 # number of SCUpgradeReq MSHR misses
1447system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses
1448system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses
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1451system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12340 # number of demand (read+write) MSHR misses
1452system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8913 # number of demand (read+write) MSHR misses
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1457system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8913 # number of overall MSHR misses
1458system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 649065 # number of overall MSHR misses
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1461system.cpu0.l2cache.overall_mshr_misses::total 2814454 # number of overall MSHR misses
1462system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable
1463system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31767 # number of ReadReq MSHR uncacheable
1464system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 53061 # number of ReadReq MSHR uncacheable
1465system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31179 # number of WriteReq MSHR uncacheable
1466system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31179 # number of WriteReq MSHR uncacheable
1467system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses
1468system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 62946 # number of overall MSHR uncacheable misses
1469system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 84240 # number of overall MSHR uncacheable misses
1470system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 415403075 # number of ReadReq MSHR miss cycles
1471system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 337276526 # number of ReadReq MSHR miss cycles
1472system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 16064432920 # number of ReadReq MSHR miss cycles
1473system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 31701439881 # number of ReadReq MSHR miss cycles
1474system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 48518552402 # number of ReadReq MSHR miss cycles
1475system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 48655967065 # number of HardPFReq MSHR miss cycles
1476system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 48655967065 # number of HardPFReq MSHR miss cycles
1477system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 28919407002 # number of WriteInvalidateReq MSHR miss cycles
1478system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 28919407002 # number of WriteInvalidateReq MSHR miss cycles
1479system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2740989495 # number of UpgradeReq MSHR miss cycles
1480system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2740989495 # number of UpgradeReq MSHR miss cycles
1481system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2358203392 # number of SCUpgradeReq MSHR miss cycles
1482system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2358203392 # number of SCUpgradeReq MSHR miss cycles
1483system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2369999 # number of SCUpgradeFailReq MSHR miss cycles
1484system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2369999 # number of SCUpgradeFailReq MSHR miss cycles
1485system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11491009195 # number of ReadExReq MSHR miss cycles
1486system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11491009195 # number of ReadExReq MSHR miss cycles
1487system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 415403075 # number of demand (read+write) MSHR miss cycles
1488system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 337276526 # number of demand (read+write) MSHR miss cycles
1489system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 16064432920 # number of demand (read+write) MSHR miss cycles
1490system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 43192449076 # number of demand (read+write) MSHR miss cycles
1491system.cpu0.l2cache.demand_mshr_miss_latency::total 60009561597 # number of demand (read+write) MSHR miss cycles
1492system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 415403075 # number of overall MSHR miss cycles
1493system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 337276526 # number of overall MSHR miss cycles
1494system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 16064432920 # number of overall MSHR miss cycles
1495system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 43192449076 # number of overall MSHR miss cycles
1496system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 48655967065 # number of overall MSHR miss cycles
1497system.cpu0.l2cache.overall_mshr_miss_latency::total 108665528662 # number of overall MSHR miss cycles
1498system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1711512000 # number of ReadReq MSHR uncacheable cycles
1499system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5362208750 # number of ReadReq MSHR uncacheable cycles
1500system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7073720750 # number of ReadReq MSHR uncacheable cycles
1501system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5065245463 # number of WriteReq MSHR uncacheable cycles
1502system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5065245463 # number of WriteReq MSHR uncacheable cycles
1503system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1711512000 # number of overall MSHR uncacheable cycles
1504system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10427454213 # number of overall MSHR uncacheable cycles
1505system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12138966213 # number of overall MSHR uncacheable cycles
1506system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022271 # mshr miss rate for ReadReq accesses
1507system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.046941 # mshr miss rate for ReadReq accesses
1508system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.104972 # mshr miss rate for ReadReq accesses
1509system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.257835 # mshr miss rate for ReadReq accesses
1510system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.157336 # mshr miss rate for ReadReq accesses
1511system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses
1512system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses
1513system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1514system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1515system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.740176 # mshr miss rate for WriteInvalidateReq accesses
1516system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.740176 # mshr miss rate for WriteInvalidateReq accesses
1517system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.531164 # mshr miss rate for UpgradeReq accesses
1518system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.531164 # mshr miss rate for UpgradeReq accesses
1519system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.813558 # mshr miss rate for SCUpgradeReq accesses
1520system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.813558 # mshr miss rate for SCUpgradeReq accesses
1521system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
1522system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
1523system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.218696 # mshr miss rate for ReadExReq accesses
1524system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.218696 # mshr miss rate for ReadExReq accesses
1525system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022271 # mshr miss rate for demand accesses
1526system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046941 # mshr miss rate for demand accesses
1527system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.104972 # mshr miss rate for demand accesses
1528system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.248713 # mshr miss rate for demand accesses
1529system.cpu0.l2cache.demand_mshr_miss_rate::total 0.163628 # mshr miss rate for demand accesses
1530system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022271 # mshr miss rate for overall accesses
1531system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046941 # mshr miss rate for overall accesses
1532system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.104972 # mshr miss rate for overall accesses
1533system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.248713 # mshr miss rate for overall accesses
1534system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
1535system.cpu0.l2cache.overall_mshr_miss_rate::total 0.227508 # mshr miss rate for overall accesses
1536system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 33663.134117 # average ReadReq mshr miss latency
1537system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 37840.965556 # average ReadReq mshr miss latency
1538system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24750.114272 # average ReadReq mshr miss latency
1539system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 29450.316582 # average ReadReq mshr miss latency
1540system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27776.376553 # average ReadReq mshr miss latency
1541system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61570.737006 # average HardPFReq mshr miss latency
1542system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 61570.737006 # average HardPFReq mshr miss latency
1543system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 48815.140097 # average WriteInvalidateReq mshr miss latency
1544system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 48815.140097 # average WriteInvalidateReq mshr miss latency
1545system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20109.679205 # average UpgradeReq mshr miss latency
1546system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20109.679205 # average UpgradeReq mshr miss latency
1547system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14820.003343 # average SCUpgradeReq mshr miss latency
1548system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14820.003343 # average SCUpgradeReq mshr miss latency
1549system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 473999.800000 # average SCUpgradeFailReq mshr miss latency
1550system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 473999.800000 # average SCUpgradeFailReq mshr miss latency
1551system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41416.056756 # average ReadExReq mshr miss latency
1552system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41416.056756 # average ReadExReq mshr miss latency
1553system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 33663.134117 # average overall mshr miss latency
1554system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 37840.965556 # average overall mshr miss latency
1555system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24750.114272 # average overall mshr miss latency
1556system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31902.456753 # average overall mshr miss latency
1557system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 29645.931619 # average overall mshr miss latency
1558system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 33663.134117 # average overall mshr miss latency
1559system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 37840.965556 # average overall mshr miss latency
1560system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24750.114272 # average overall mshr miss latency
1561system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31902.456753 # average overall mshr miss latency
1562system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61570.737006 # average overall mshr miss latency
1563system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38609.808035 # average overall mshr miss latency
1564system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80375.316991 # average ReadReq mshr uncacheable latency
1565system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168798.084490 # average ReadReq mshr uncacheable latency
1566system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133312.993536 # average ReadReq mshr uncacheable latency
1567system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162456.957022 # average WriteReq mshr uncacheable latency
1568system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162456.957022 # average WriteReq mshr uncacheable latency
1569system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80375.316991 # average overall mshr uncacheable latency
1570system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 165657.138071 # average overall mshr uncacheable latency
1571system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 144099.788853 # average overall mshr uncacheable latency
1572system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1573system.cpu0.toL2Bus.trans_dist::ReadReq 13667246 # Transaction distribution
1574system.cpu0.toL2Bus.trans_dist::ReadResp 11407678 # Transaction distribution
1575system.cpu0.toL2Bus.trans_dist::WriteReq 38779 # Transaction distribution
1576system.cpu0.toL2Bus.trans_dist::WriteResp 31179 # Transaction distribution
1577system.cpu0.toL2Bus.trans_dist::Writeback 4196361 # Transaction distribution
1578system.cpu0.toL2Bus.trans_dist::HardPFReq 1120333 # Transaction distribution
1579system.cpu0.toL2Bus.trans_dist::HardPFResp 10 # Transaction distribution
1580system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1176973 # Transaction distribution
1581system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 800387 # Transaction distribution
1582system.cpu0.toL2Bus.trans_dist::UpgradeReq 496358 # Transaction distribution
1583system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 355576 # Transaction distribution
1584system.cpu0.toL2Bus.trans_dist::UpgradeResp 523512 # Transaction distribution
1585system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 86 # Transaction distribution
1586system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 143 # Transaction distribution
1587system.cpu0.toL2Bus.trans_dist::ReadExReq 1407436 # Transaction distribution
1588system.cpu0.toL2Bus.trans_dist::ReadExResp 1277584 # Transaction distribution
1589system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12409061 # Packet count per connected master and slave (bytes)
1590system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17898439 # Packet count per connected master and slave (bytes)
1591system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 414925 # Packet count per connected master and slave (bytes)
1592system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1222034 # Packet count per connected master and slave (bytes)
1593system.cpu0.toL2Bus.pkt_count::total 31944459 # Packet count per connected master and slave (bytes)
1594system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 396067296 # Cumulative packet size per connected master and slave (bytes)
1595system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 675577736 # Cumulative packet size per connected master and slave (bytes)
1596system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1519008 # Cumulative packet size per connected master and slave (bytes)
1597system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4432728 # Cumulative packet size per connected master and slave (bytes)
1598system.cpu0.toL2Bus.pkt_size::total 1077596768 # Cumulative packet size per connected master and slave (bytes)
1599system.cpu0.toL2Bus.snoops 4739028 # Total snoops (count)
1600system.cpu0.toL2Bus.snoop_fanout::samples 22459193 # Request fanout histogram
1601system.cpu0.toL2Bus.snoop_fanout::mean 1.235945 # Request fanout histogram
1602system.cpu0.toL2Bus.snoop_fanout::stdev 0.424588 # Request fanout histogram
1603system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1604system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1605system.cpu0.toL2Bus.snoop_fanout::1 17160060 76.41% 76.41% # Request fanout histogram
1606system.cpu0.toL2Bus.snoop_fanout::2 5299133 23.59% 100.00% # Request fanout histogram
1607system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1608system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
1609system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1610system.cpu0.toL2Bus.snoop_fanout::total 22459193 # Request fanout histogram
1611system.cpu0.toL2Bus.reqLayer0.occupancy 14039414488 # Layer occupancy (ticks)
1612system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
1613system.cpu0.toL2Bus.snoopLayer0.occupancy 204401970 # Layer occupancy (ticks)
1614system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1615system.cpu0.toL2Bus.respLayer0.occupancy 9316604024 # Layer occupancy (ticks)
1616system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1617system.cpu0.toL2Bus.respLayer1.occupancy 8912883405 # Layer occupancy (ticks)
1618system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
1619system.cpu0.toL2Bus.respLayer2.occupancy 225880552 # Layer occupancy (ticks)
1620system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1621system.cpu0.toL2Bus.respLayer3.occupancy 669143268 # Layer occupancy (ticks)
1622system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1623system.cpu1.branchPred.lookups 128543512 # Number of BP lookups
1624system.cpu1.branchPred.condPredicted 85865577 # Number of conditional branches predicted
1625system.cpu1.branchPred.condIncorrect 6421624 # Number of conditional branches incorrect
1626system.cpu1.branchPred.BTBLookups 90850028 # Number of BTB lookups
1627system.cpu1.branchPred.BTBHits 59627534 # Number of BTB hits
1628system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
1629system.cpu1.branchPred.BTBHitPct 65.632929 # BTB Hit Percentage
1630system.cpu1.branchPred.usedRAS 17292026 # Number of times the RAS was used to get a target.
1631system.cpu1.branchPred.RASInCorrect 181846 # Number of incorrect RAS predictions.
1632system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1633system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1634system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1635system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1636system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1637system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1638system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1639system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1653system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1654system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1655system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1656system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1657system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1658system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
1659system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
1660system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1661system.cpu1.dtb.walker.walks 599268 # Table walker walks requested
1662system.cpu1.dtb.walker.walksLong 599268 # Table walker walks initiated with long descriptors
1663system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 13824 # Level at which table walker walks with long descriptors terminate
1664system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 99235 # Level at which table walker walks with long descriptors terminate
1665system.cpu1.dtb.walker.walksSquashedBefore 280644 # Table walks squashed before starting
1666system.cpu1.dtb.walker.walkWaitTime::samples 318624 # Table walker wait (enqueue to first request) latency
1667system.cpu1.dtb.walker.walkWaitTime::mean 1973.247464 # Table walker wait (enqueue to first request) latency
1668system.cpu1.dtb.walker.walkWaitTime::stdev 12034.928654 # Table walker wait (enqueue to first request) latency
1669system.cpu1.dtb.walker.walkWaitTime::0-65535 316338 99.28% 99.28% # Table walker wait (enqueue to first request) latency
1670system.cpu1.dtb.walker.walkWaitTime::65536-131071 1742 0.55% 99.83% # Table walker wait (enqueue to first request) latency
1671system.cpu1.dtb.walker.walkWaitTime::131072-196607 377 0.12% 99.95% # Table walker wait (enqueue to first request) latency
1672system.cpu1.dtb.walker.walkWaitTime::196608-262143 71 0.02% 99.97% # Table walker wait (enqueue to first request) latency
1673system.cpu1.dtb.walker.walkWaitTime::262144-327679 83 0.03% 100.00% # Table walker wait (enqueue to first request) latency
1674system.cpu1.dtb.walker.walkWaitTime::327680-393215 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1675system.cpu1.dtb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1676system.cpu1.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1677system.cpu1.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1678system.cpu1.dtb.walker.walkWaitTime::total 318624 # Table walker wait (enqueue to first request) latency
1679system.cpu1.dtb.walker.walkCompletionTime::samples 319817 # Table walker service (enqueue to completion) latency
1680system.cpu1.dtb.walker.walkCompletionTime::mean 17305.058052 # Table walker service (enqueue to completion) latency
1681system.cpu1.dtb.walker.walkCompletionTime::gmean 14691.969456 # Table walker service (enqueue to completion) latency
1682system.cpu1.dtb.walker.walkCompletionTime::stdev 15678.724582 # Table walker service (enqueue to completion) latency
1683system.cpu1.dtb.walker.walkCompletionTime::0-65535 316762 99.04% 99.04% # Table walker service (enqueue to completion) latency
1684system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2191 0.69% 99.73% # Table walker service (enqueue to completion) latency
1685system.cpu1.dtb.walker.walkCompletionTime::131072-196607 345 0.11% 99.84% # Table walker service (enqueue to completion) latency
1686system.cpu1.dtb.walker.walkCompletionTime::196608-262143 267 0.08% 99.92% # Table walker service (enqueue to completion) latency
1687system.cpu1.dtb.walker.walkCompletionTime::262144-327679 157 0.05% 99.97% # Table walker service (enqueue to completion) latency
1688system.cpu1.dtb.walker.walkCompletionTime::327680-393215 61 0.02% 99.99% # Table walker service (enqueue to completion) latency
1689system.cpu1.dtb.walker.walkCompletionTime::393216-458751 16 0.01% 99.99% # Table walker service (enqueue to completion) latency
1690system.cpu1.dtb.walker.walkCompletionTime::458752-524287 8 0.00% 100.00% # Table walker service (enqueue to completion) latency
1691system.cpu1.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency
1692system.cpu1.dtb.walker.walkCompletionTime::total 319817 # Table walker service (enqueue to completion) latency
1693system.cpu1.dtb.walker.walksPending::samples 467242764496 # Table walker pending requests distribution
1694system.cpu1.dtb.walker.walksPending::mean 0.609754 # Table walker pending requests distribution
1695system.cpu1.dtb.walker.walksPending::stdev 0.540089 # Table walker pending requests distribution
1696system.cpu1.dtb.walker.walksPending::0-1 466086530996 99.75% 99.75% # Table walker pending requests distribution
1697system.cpu1.dtb.walker.walksPending::2-3 677505500 0.15% 99.90% # Table walker pending requests distribution
1698system.cpu1.dtb.walker.walksPending::4-5 222526000 0.05% 99.95% # Table walker pending requests distribution
1699system.cpu1.dtb.walker.walksPending::6-7 100711000 0.02% 99.97% # Table walker pending requests distribution
1700system.cpu1.dtb.walker.walksPending::8-9 81855500 0.02% 99.98% # Table walker pending requests distribution
1701system.cpu1.dtb.walker.walksPending::10-11 40422000 0.01% 99.99% # Table walker pending requests distribution
1702system.cpu1.dtb.walker.walksPending::12-13 15395000 0.00% 100.00% # Table walker pending requests distribution
1703system.cpu1.dtb.walker.walksPending::14-15 17231500 0.00% 100.00% # Table walker pending requests distribution
1704system.cpu1.dtb.walker.walksPending::16-17 579500 0.00% 100.00% # Table walker pending requests distribution
1705system.cpu1.dtb.walker.walksPending::18-19 7500 0.00% 100.00% # Table walker pending requests distribution
1706system.cpu1.dtb.walker.walksPending::total 467242764496 # Table walker pending requests distribution
1707system.cpu1.dtb.walker.walkPageSizes::4K 99236 87.77% 87.77% # Table walker page sizes translated
1708system.cpu1.dtb.walker.walkPageSizes::2M 13824 12.23% 100.00% # Table walker page sizes translated
1709system.cpu1.dtb.walker.walkPageSizes::total 113060 # Table walker page sizes translated
1710system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 599268 # Table walker requests started/completed, data/inst
1711system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1712system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 599268 # Table walker requests started/completed, data/inst
1713system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 113060 # Table walker requests started/completed, data/inst
1714system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1715system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 113060 # Table walker requests started/completed, data/inst
1716system.cpu1.dtb.walker.walkRequestOrigin::total 712328 # Table walker requests started/completed, data/inst
1717system.cpu1.dtb.inst_hits 0 # ITB inst hits
1718system.cpu1.dtb.inst_misses 0 # ITB inst misses
1719system.cpu1.dtb.read_hits 95146273 # DTB read hits
1720system.cpu1.dtb.read_misses 436726 # DTB read misses
1721system.cpu1.dtb.write_hits 76756681 # DTB write hits
1722system.cpu1.dtb.write_misses 162542 # DTB write misses
1723system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
1724system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1725system.cpu1.dtb.flush_tlb_mva_asid 44809 # Number of times TLB was flushed by MVA & ASID
1726system.cpu1.dtb.flush_tlb_asid 1073 # Number of times TLB was flushed by ASID
1727system.cpu1.dtb.flush_entries 41064 # Number of entries that have been flushed from TLB
1728system.cpu1.dtb.align_faults 604 # Number of TLB faults due to alignment restrictions
1729system.cpu1.dtb.prefetch_faults 6738 # Number of TLB faults due to prefetch
1730system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
1731system.cpu1.dtb.perms_faults 39860 # Number of TLB faults due to permissions restrictions
1732system.cpu1.dtb.read_accesses 95582999 # DTB read accesses
1733system.cpu1.dtb.write_accesses 76919223 # DTB write accesses
1734system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
1735system.cpu1.dtb.hits 171902954 # DTB hits
1736system.cpu1.dtb.misses 599268 # DTB misses
1737system.cpu1.dtb.accesses 172502222 # DTB accesses
1738system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
1739system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1740system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
1741system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
1742system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1743system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
1744system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
1745system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

1759system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
1760system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
1761system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
1762system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
1763system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
1764system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
1765system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
1766system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
1767system.cpu1.itb.walker.walks 83675 # Table walker walks requested
1768system.cpu1.itb.walker.walksLong 83675 # Table walker walks initiated with long descriptors
1769system.cpu1.itb.walker.walksLongTerminationLevel::Level2 922 # Level at which table walker walks with long descriptors terminate
1770system.cpu1.itb.walker.walksLongTerminationLevel::Level3 60249 # Level at which table walker walks with long descriptors terminate
1771system.cpu1.itb.walker.walksSquashedBefore 9641 # Table walks squashed before starting
1772system.cpu1.itb.walker.walkWaitTime::samples 74034 # Table walker wait (enqueue to first request) latency
1773system.cpu1.itb.walker.walkWaitTime::mean 1137.571926 # Table walker wait (enqueue to first request) latency
1774system.cpu1.itb.walker.walkWaitTime::stdev 8570.962609 # Table walker wait (enqueue to first request) latency
1775system.cpu1.itb.walker.walkWaitTime::0-32767 73376 99.11% 99.11% # Table walker wait (enqueue to first request) latency
1776system.cpu1.itb.walker.walkWaitTime::32768-65535 334 0.45% 99.56% # Table walker wait (enqueue to first request) latency
1777system.cpu1.itb.walker.walkWaitTime::65536-98303 142 0.19% 99.75% # Table walker wait (enqueue to first request) latency
1778system.cpu1.itb.walker.walkWaitTime::98304-131071 157 0.21% 99.97% # Table walker wait (enqueue to first request) latency
1779system.cpu1.itb.walker.walkWaitTime::131072-163839 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency
1780system.cpu1.itb.walker.walkWaitTime::163840-196607 7 0.01% 99.98% # Table walker wait (enqueue to first request) latency
1781system.cpu1.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
1782system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
1783system.cpu1.itb.walker.walkWaitTime::262144-294911 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
1784system.cpu1.itb.walker.walkWaitTime::294912-327679 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency
1785system.cpu1.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1786system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
1787system.cpu1.itb.walker.walkWaitTime::total 74034 # Table walker wait (enqueue to first request) latency
1788system.cpu1.itb.walker.walkCompletionTime::samples 70812 # Table walker service (enqueue to completion) latency
1789system.cpu1.itb.walker.walkCompletionTime::mean 21947.603838 # Table walker service (enqueue to completion) latency
1790system.cpu1.itb.walker.walkCompletionTime::gmean 18689.139556 # Table walker service (enqueue to completion) latency
1791system.cpu1.itb.walker.walkCompletionTime::stdev 20589.258424 # Table walker service (enqueue to completion) latency
1792system.cpu1.itb.walker.walkCompletionTime::0-65535 68933 97.35% 97.35% # Table walker service (enqueue to completion) latency
1793system.cpu1.itb.walker.walkCompletionTime::65536-131071 1547 2.18% 99.53% # Table walker service (enqueue to completion) latency
1794system.cpu1.itb.walker.walkCompletionTime::131072-196607 153 0.22% 99.75% # Table walker service (enqueue to completion) latency
1795system.cpu1.itb.walker.walkCompletionTime::196608-262143 111 0.16% 99.90% # Table walker service (enqueue to completion) latency
1796system.cpu1.itb.walker.walkCompletionTime::262144-327679 33 0.05% 99.95% # Table walker service (enqueue to completion) latency
1797system.cpu1.itb.walker.walkCompletionTime::327680-393215 27 0.04% 99.99% # Table walker service (enqueue to completion) latency
1798system.cpu1.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
1799system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1800system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
1801system.cpu1.itb.walker.walkCompletionTime::total 70812 # Table walker service (enqueue to completion) latency
1802system.cpu1.itb.walker.walksPending::samples 419972060240 # Table walker pending requests distribution
1803system.cpu1.itb.walker.walksPending::mean 0.852209 # Table walker pending requests distribution
1804system.cpu1.itb.walker.walksPending::stdev 0.355033 # Table walker pending requests distribution
1805system.cpu1.itb.walker.walksPending::0 62087724216 14.78% 14.78% # Table walker pending requests distribution
1806system.cpu1.itb.walker.walksPending::1 357865938524 85.21% 100.00% # Table walker pending requests distribution
1807system.cpu1.itb.walker.walksPending::2 17105000 0.00% 100.00% # Table walker pending requests distribution
1808system.cpu1.itb.walker.walksPending::3 1290000 0.00% 100.00% # Table walker pending requests distribution
1809system.cpu1.itb.walker.walksPending::4 2500 0.00% 100.00% # Table walker pending requests distribution
1810system.cpu1.itb.walker.walksPending::total 419972060240 # Table walker pending requests distribution
1811system.cpu1.itb.walker.walkPageSizes::4K 60249 98.49% 98.49% # Table walker page sizes translated
1812system.cpu1.itb.walker.walkPageSizes::2M 922 1.51% 100.00% # Table walker page sizes translated
1813system.cpu1.itb.walker.walkPageSizes::total 61171 # Table walker page sizes translated
1814system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
1815system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 83675 # Table walker requests started/completed, data/inst
1816system.cpu1.itb.walker.walkRequestOrigin_Requested::total 83675 # Table walker requests started/completed, data/inst
1817system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
1818system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61171 # Table walker requests started/completed, data/inst
1819system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61171 # Table walker requests started/completed, data/inst
1820system.cpu1.itb.walker.walkRequestOrigin::total 144846 # Table walker requests started/completed, data/inst
1821system.cpu1.itb.inst_hits 203060553 # ITB inst hits
1822system.cpu1.itb.inst_misses 83675 # ITB inst misses
1823system.cpu1.itb.read_hits 0 # DTB read hits
1824system.cpu1.itb.read_misses 0 # DTB read misses
1825system.cpu1.itb.write_hits 0 # DTB write hits
1826system.cpu1.itb.write_misses 0 # DTB write misses
1827system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
1828system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
1829system.cpu1.itb.flush_tlb_mva_asid 44809 # Number of times TLB was flushed by MVA & ASID
1830system.cpu1.itb.flush_tlb_asid 1073 # Number of times TLB was flushed by ASID
1831system.cpu1.itb.flush_entries 29792 # Number of entries that have been flushed from TLB
1832system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
1833system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
1834system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
1835system.cpu1.itb.perms_faults 217868 # Number of TLB faults due to permissions restrictions
1836system.cpu1.itb.read_accesses 0 # DTB read accesses
1837system.cpu1.itb.write_accesses 0 # DTB write accesses
1838system.cpu1.itb.inst_accesses 203144228 # ITB inst accesses
1839system.cpu1.itb.hits 203060553 # DTB hits
1840system.cpu1.itb.misses 83675 # DTB misses
1841system.cpu1.itb.accesses 203144228 # DTB accesses
1842system.cpu1.numCycles 689224896 # number of cpu cycles simulated
1843system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
1844system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
1845system.cpu1.fetch.icacheStallCycles 83111859 # Number of cycles fetch is stalled on an Icache miss
1846system.cpu1.fetch.Insts 570743281 # Number of instructions fetch has processed
1847system.cpu1.fetch.Branches 128543512 # Number of branches that fetch encountered
1848system.cpu1.fetch.predictedBranches 76919560 # Number of branches that fetch has predicted taken
1849system.cpu1.fetch.Cycles 571668142 # Number of cycles fetch has run and was not squashing or blocked
1850system.cpu1.fetch.SquashCycles 13828506 # Number of cycles fetch has spent squashing
1851system.cpu1.fetch.TlbCycles 1777982 # Number of cycles fetch has spent waiting for tlb
1852system.cpu1.fetch.MiscStallCycles 253475 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
1853system.cpu1.fetch.PendingTrapStallCycles 6260799 # Number of stall cycles due to pending traps
1854system.cpu1.fetch.PendingQuiesceStallCycles 781198 # Number of stall cycles due to pending quiesce instructions
1855system.cpu1.fetch.IcacheWaitRetryStallCycles 699050 # Number of stall cycles due to full MSHR
1856system.cpu1.fetch.CacheLines 202821648 # Number of cache lines fetched
1857system.cpu1.fetch.IcacheSquashes 1630400 # Number of outstanding Icache misses that were squashed
1858system.cpu1.fetch.ItlbSquashes 27635 # Number of outstanding ITLB misses that were squashed
1859system.cpu1.fetch.rateDist::samples 671466758 # Number of instructions fetched each cycle (Total)
1860system.cpu1.fetch.rateDist::mean 0.996773 # Number of instructions fetched each cycle (Total)
1861system.cpu1.fetch.rateDist::stdev 1.223843 # Number of instructions fetched each cycle (Total)
1862system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
1863system.cpu1.fetch.rateDist::0 351036099 52.28% 52.28% # Number of instructions fetched each cycle (Total)
1864system.cpu1.fetch.rateDist::1 124470987 18.54% 70.82% # Number of instructions fetched each cycle (Total)
1865system.cpu1.fetch.rateDist::2 43050208 6.41% 77.23% # Number of instructions fetched each cycle (Total)
1866system.cpu1.fetch.rateDist::3 152909464 22.77% 100.00% # Number of instructions fetched each cycle (Total)
1867system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
1868system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
1869system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
1870system.cpu1.fetch.rateDist::total 671466758 # Number of instructions fetched each cycle (Total)
1871system.cpu1.fetch.branchRate 0.186504 # Number of branch fetches per cycle
1872system.cpu1.fetch.rate 0.828094 # Number of inst fetches per cycle
1873system.cpu1.decode.IdleCycles 100354838 # Number of cycles decode is idle
1874system.cpu1.decode.BlockedCycles 318587695 # Number of cycles decode is blocked
1875system.cpu1.decode.RunCycles 211284340 # Number of cycles decode is running
1876system.cpu1.decode.UnblockCycles 36331371 # Number of cycles decode is unblocking
1877system.cpu1.decode.SquashCycles 4908514 # Number of cycles decode is squashing
1878system.cpu1.decode.BranchResolved 18177231 # Number of times decode resolved a branch
1879system.cpu1.decode.BranchMispred 2045887 # Number of times decode detected a branch misprediction
1880system.cpu1.decode.DecodedInsts 591006296 # Number of instructions handled by decode
1881system.cpu1.decode.SquashedInsts 22089664 # Number of squashed instructions handled by decode
1882system.cpu1.rename.SquashCycles 4908514 # Number of cycles rename is squashing
1883system.cpu1.rename.IdleCycles 134210773 # Number of cycles rename is idle
1884system.cpu1.rename.BlockCycles 44178364 # Number of cycles rename is blocking
1885system.cpu1.rename.serializeStallCycles 216212349 # count of cycles rename stalled for serializing inst
1886system.cpu1.rename.RunCycles 213325919 # Number of cycles rename is running
1887system.cpu1.rename.UnblockCycles 58630839 # Number of cycles rename is unblocking
1888system.cpu1.rename.RenamedInsts 574898328 # Number of instructions processed by rename
1889system.cpu1.rename.SquashedInsts 5600894 # Number of squashed instructions processed by rename
1890system.cpu1.rename.ROBFullEvents 8989963 # Number of times rename has blocked due to ROB full
1891system.cpu1.rename.IQFullEvents 383271 # Number of times rename has blocked due to IQ full
1892system.cpu1.rename.LQFullEvents 860464 # Number of times rename has blocked due to LQ full
1893system.cpu1.rename.SQFullEvents 24265786 # Number of times rename has blocked due to SQ full
1894system.cpu1.rename.FullRegisterEvents 10988 # Number of times there has been no free registers
1895system.cpu1.rename.RenamedOperands 548407946 # Number of destination operands rename has renamed
1896system.cpu1.rename.RenameLookups 889065279 # Number of register rename lookups that rename has made
1897system.cpu1.rename.int_rename_lookups 679031773 # Number of integer rename lookups
1898system.cpu1.rename.fp_rename_lookups 678204 # Number of floating rename lookups
1899system.cpu1.rename.CommittedMaps 493384651 # Number of HB maps that are committed
1900system.cpu1.rename.UndoneMaps 55023295 # Number of HB maps that are undone due to squashing
1901system.cpu1.rename.serializingInsts 15514043 # count of serializing insts renamed
1902system.cpu1.rename.tempSerializingInsts 13585261 # count of temporary serializing insts renamed
1903system.cpu1.rename.skidInsts 73076002 # count of insts added to the skid buffer
1904system.cpu1.memDep0.insertedLoads 95606432 # Number of loads inserted to the mem dependence unit.
1905system.cpu1.memDep0.insertedStores 79961275 # Number of stores inserted to the mem dependence unit.
1906system.cpu1.memDep0.conflictingLoads 8917606 # Number of conflicting loads.
1907system.cpu1.memDep0.conflictingStores 7761424 # Number of conflicting stores.
1908system.cpu1.iq.iqInstsAdded 553073173 # Number of instructions added to the IQ (excludes non-spec)
1909system.cpu1.iq.iqNonSpecInstsAdded 15730545 # Number of non-speculative instructions added to the IQ
1910system.cpu1.iq.iqInstsIssued 557717167 # Number of instructions issued
1911system.cpu1.iq.iqSquashedInstsIssued 2597694 # Number of squashed instructions issued
1912system.cpu1.iq.iqSquashedInstsExamined 51818937 # Number of squashed instructions iterated over during squash; mainly for profiling
1913system.cpu1.iq.iqSquashedOperandsExamined 33853803 # Number of squashed operands that are examined and possibly removed from graph
1914system.cpu1.iq.iqSquashedNonSpecRemoved 272876 # Number of squashed non-spec instructions that were removed
1915system.cpu1.iq.issued_per_cycle::samples 671466758 # Number of insts issued each cycle
1916system.cpu1.iq.issued_per_cycle::mean 0.830595 # Number of insts issued each cycle
1917system.cpu1.iq.issued_per_cycle::stdev 1.066249 # Number of insts issued each cycle
1918system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
1919system.cpu1.iq.issued_per_cycle::0 364901654 54.34% 54.34% # Number of insts issued each cycle
1920system.cpu1.iq.issued_per_cycle::1 131371089 19.56% 73.91% # Number of insts issued each cycle
1921system.cpu1.iq.issued_per_cycle::2 106572496 15.87% 89.78% # Number of insts issued each cycle
1922system.cpu1.iq.issued_per_cycle::3 61289322 9.13% 98.91% # Number of insts issued each cycle
1923system.cpu1.iq.issued_per_cycle::4 7327865 1.09% 100.00% # Number of insts issued each cycle
1924system.cpu1.iq.issued_per_cycle::5 4332 0.00% 100.00% # Number of insts issued each cycle
1925system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
1926system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
1927system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
1928system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
1929system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
1930system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
1931system.cpu1.iq.issued_per_cycle::total 671466758 # Number of insts issued each cycle
1932system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
1933system.cpu1.iq.fu_full::IntAlu 55930906 44.08% 44.08% # attempts to use FU when none available
1934system.cpu1.iq.fu_full::IntMult 67479 0.05% 44.13% # attempts to use FU when none available
1935system.cpu1.iq.fu_full::IntDiv 9405 0.01% 44.14% # attempts to use FU when none available
1936system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.14% # attempts to use FU when none available
1937system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.14% # attempts to use FU when none available
1938system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.14% # attempts to use FU when none available
1939system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.14% # attempts to use FU when none available
1940system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.14% # attempts to use FU when none available
1941system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.14% # attempts to use FU when none available
1942system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.14% # attempts to use FU when none available
1943system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.14% # attempts to use FU when none available
1944system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.14% # attempts to use FU when none available
1945system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.14% # attempts to use FU when none available
1946system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.14% # attempts to use FU when none available
1947system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.14% # attempts to use FU when none available
1948system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.14% # attempts to use FU when none available
1949system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.14% # attempts to use FU when none available
1950system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.14% # attempts to use FU when none available
1951system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.14% # attempts to use FU when none available
1952system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.14% # attempts to use FU when none available
1953system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.14% # attempts to use FU when none available
1954system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.14% # attempts to use FU when none available
1955system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.14% # attempts to use FU when none available
1956system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.14% # attempts to use FU when none available
1957system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.14% # attempts to use FU when none available
1958system.cpu1.iq.fu_full::SimdFloatMisc 14 0.00% 44.14% # attempts to use FU when none available
1959system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.14% # attempts to use FU when none available
1960system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.14% # attempts to use FU when none available
1961system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.14% # attempts to use FU when none available
1962system.cpu1.iq.fu_full::MemRead 34760931 27.40% 71.54% # attempts to use FU when none available
1963system.cpu1.iq.fu_full::MemWrite 36114343 28.46% 100.00% # attempts to use FU when none available
1964system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
1965system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
1966system.cpu1.iq.FU_type_0::No_OpClass 41 0.00% 0.00% # Type of FU issued
1967system.cpu1.iq.FU_type_0::IntAlu 380161908 68.16% 68.16% # Type of FU issued
1968system.cpu1.iq.FU_type_0::IntMult 1344725 0.24% 68.41% # Type of FU issued
1969system.cpu1.iq.FU_type_0::IntDiv 78828 0.01% 68.42% # Type of FU issued
1970system.cpu1.iq.FU_type_0::FloatAdd 3 0.00% 68.42% # Type of FU issued
1971system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.42% # Type of FU issued
1972system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.42% # Type of FU issued
1973system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.42% # Type of FU issued
1974system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.42% # Type of FU issued
1975system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.42% # Type of FU issued
1976system.cpu1.iq.FU_type_0::SimdAdd 5 0.00% 68.42% # Type of FU issued
1977system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.42% # Type of FU issued
1978system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.42% # Type of FU issued
1979system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.42% # Type of FU issued
1980system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.42% # Type of FU issued
1981system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.42% # Type of FU issued
1982system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.42% # Type of FU issued
1983system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.42% # Type of FU issued
1984system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.42% # Type of FU issued
1985system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.42% # Type of FU issued
1986system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.42% # Type of FU issued
1987system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.42% # Type of FU issued
1988system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.42% # Type of FU issued
1989system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.42% # Type of FU issued
1990system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.42% # Type of FU issued
1991system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.42% # Type of FU issued
1992system.cpu1.iq.FU_type_0::SimdFloatMisc 45642 0.01% 68.43% # Type of FU issued
1993system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued
1994system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued
1995system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued
1996system.cpu1.iq.FU_type_0::MemRead 98115732 17.59% 86.02% # Type of FU issued
1997system.cpu1.iq.FU_type_0::MemWrite 77970283 13.98% 100.00% # Type of FU issued
1998system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
1999system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
2000system.cpu1.iq.FU_type_0::total 557717167 # Type of FU issued
2001system.cpu1.iq.rate 0.809195 # Inst issue rate
2002system.cpu1.iq.fu_busy_cnt 126883078 # FU busy when requested
2003system.cpu1.iq.fu_busy_rate 0.227504 # FU busy rate (busy events/executed inst)
2004system.cpu1.iq.int_inst_queue_reads 1915274546 # Number of integer instruction queue reads
2005system.cpu1.iq.int_inst_queue_writes 620324151 # Number of integer instruction queue writes
2006system.cpu1.iq.int_inst_queue_wakeup_accesses 541832642 # Number of integer instruction queue wakeup accesses
2007system.cpu1.iq.fp_inst_queue_reads 1107318 # Number of floating instruction queue reads
2008system.cpu1.iq.fp_inst_queue_writes 438573 # Number of floating instruction queue writes
2009system.cpu1.iq.fp_inst_queue_wakeup_accesses 407875 # Number of floating instruction queue wakeup accesses
2010system.cpu1.iq.int_alu_accesses 683910466 # Number of integer alu accesses
2011system.cpu1.iq.fp_alu_accesses 689738 # Number of floating point alu accesses
2012system.cpu1.iew.lsq.thread0.forwLoads 2496582 # Number of loads that had data forwarded from stores
2013system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
2014system.cpu1.iew.lsq.thread0.squashedLoads 11949439 # Number of loads squashed
2015system.cpu1.iew.lsq.thread0.ignoredResponses 17528 # Number of memory responses ignored because the instruction is squashed
2016system.cpu1.iew.lsq.thread0.memOrderViolation 140940 # Number of memory ordering violations
2017system.cpu1.iew.lsq.thread0.squashedStores 5567236 # Number of stores squashed
2018system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
2019system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
2020system.cpu1.iew.lsq.thread0.rescheduledLoads 2504839 # Number of loads that were rescheduled
2021system.cpu1.iew.lsq.thread0.cacheBlocked 3936319 # Number of times an access to memory failed due to the cache being blocked
2022system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
2023system.cpu1.iew.iewSquashCycles 4908514 # Number of cycles IEW is squashing
2024system.cpu1.iew.iewBlockCycles 7583348 # Number of cycles IEW is blocking
2025system.cpu1.iew.iewUnblockCycles 1594599 # Number of cycles IEW is unblocking
2026system.cpu1.iew.iewDispatchedInsts 568926208 # Number of instructions dispatched to IQ
2027system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
2028system.cpu1.iew.iewDispLoadInsts 95606432 # Number of dispatched load instructions
2029system.cpu1.iew.iewDispStoreInsts 79961275 # Number of dispatched store instructions
2030system.cpu1.iew.iewDispNonSpecInsts 13359998 # Number of dispatched non-speculative instructions
2031system.cpu1.iew.iewIQFullEvents 58436 # Number of times the IQ has become full, causing a stall
2032system.cpu1.iew.iewLSQFullEvents 1466228 # Number of times the LSQ has become full, causing a stall
2033system.cpu1.iew.memOrderViolationEvents 140940 # Number of memory order violations
2034system.cpu1.iew.predictedTakenIncorrect 1941130 # Number of branches that were predicted taken incorrectly
2035system.cpu1.iew.predictedNotTakenIncorrect 2763310 # Number of branches that were predicted not taken incorrectly
2036system.cpu1.iew.branchMispredicts 4704440 # Number of branch mispredicts detected at execute
2037system.cpu1.iew.iewExecutedInsts 550354066 # Number of executed instructions
2038system.cpu1.iew.iewExecLoadInsts 95142052 # Number of load instructions executed
2039system.cpu1.iew.iewExecSquashedInsts 6771828 # Number of squashed instructions skipped in execute
2040system.cpu1.iew.exec_swp 0 # number of swp insts executed
2041system.cpu1.iew.exec_nop 122490 # number of nop insts executed
2042system.cpu1.iew.exec_refs 171896040 # number of memory reference insts executed
2043system.cpu1.iew.exec_branches 103292614 # Number of branches executed
2044system.cpu1.iew.exec_stores 76753988 # Number of stores executed
2045system.cpu1.iew.exec_rate 0.798512 # Inst execution rate
2046system.cpu1.iew.wb_sent 542951378 # cumulative count of insts sent to commit
2047system.cpu1.iew.wb_count 542240517 # cumulative count of insts written-back
2048system.cpu1.iew.wb_producers 263529127 # num instructions producing a value
2049system.cpu1.iew.wb_consumers 431811268 # num instructions consuming a value
2050system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
2051system.cpu1.iew.wb_rate 0.786740 # insts written-back per cycle
2052system.cpu1.iew.wb_fanout 0.610288 # average fanout of values written-back
2053system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
2054system.cpu1.commit.commitSquashedInsts 45371481 # The number of squashed insts skipped by commit
2055system.cpu1.commit.commitNonSpecStalls 15457669 # The number of times commit has been forced to stall to communicate backwards
2056system.cpu1.commit.branchMispredicts 4415885 # The number of times a branch was mispredicted
2057system.cpu1.commit.committed_per_cycle::samples 662874998 # Number of insts commited each cycle
2058system.cpu1.commit.committed_per_cycle::mean 0.779913 # Number of insts commited each cycle
2059system.cpu1.commit.committed_per_cycle::stdev 1.574524 # Number of insts commited each cycle
2060system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
2061system.cpu1.commit.committed_per_cycle::0 435019222 65.63% 65.63% # Number of insts commited each cycle
2062system.cpu1.commit.committed_per_cycle::1 119535237 18.03% 83.66% # Number of insts commited each cycle
2063system.cpu1.commit.committed_per_cycle::2 49733246 7.50% 91.16% # Number of insts commited each cycle
2064system.cpu1.commit.committed_per_cycle::3 16752738 2.53% 93.69% # Number of insts commited each cycle
2065system.cpu1.commit.committed_per_cycle::4 12005106 1.81% 95.50% # Number of insts commited each cycle
2066system.cpu1.commit.committed_per_cycle::5 8186664 1.24% 96.74% # Number of insts commited each cycle
2067system.cpu1.commit.committed_per_cycle::6 5495672 0.83% 97.56% # Number of insts commited each cycle
2068system.cpu1.commit.committed_per_cycle::7 3379842 0.51% 98.07% # Number of insts commited each cycle
2069system.cpu1.commit.committed_per_cycle::8 12767271 1.93% 100.00% # Number of insts commited each cycle
2070system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
2071system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
2072system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
2073system.cpu1.commit.committed_per_cycle::total 662874998 # Number of insts commited each cycle
2074system.cpu1.commit.committedInsts 439804157 # Number of instructions committed
2075system.cpu1.commit.committedOps 516984781 # Number of ops (including micro ops) committed
2076system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
2077system.cpu1.commit.refs 158051032 # Number of memory references committed
2078system.cpu1.commit.loads 83656993 # Number of loads committed
2079system.cpu1.commit.membars 3709079 # Number of memory barriers committed
2080system.cpu1.commit.branches 98009532 # Number of branches committed
2081system.cpu1.commit.fp_insts 399401 # Number of committed floating point instructions.
2082system.cpu1.commit.int_insts 474457036 # Number of committed integer instructions.
2083system.cpu1.commit.function_calls 12875376 # Number of function calls committed.
2084system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
2085system.cpu1.commit.op_class_0::IntAlu 357731742 69.20% 69.20% # Class of committed instruction
2086system.cpu1.commit.op_class_0::IntMult 1099808 0.21% 69.41% # Class of committed instruction
2087system.cpu1.commit.op_class_0::IntDiv 62550 0.01% 69.42% # Class of committed instruction
2088system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction
2089system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction
2090system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction
2091system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction
2092system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction
2093system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction
2094system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction
2095system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction
2096system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction
2097system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction
2098system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction
2099system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction
2100system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction
2101system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction
2102system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction
2103system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction
2104system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction
2105system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.42% # Class of committed instruction
2106system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction
2107system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.42% # Class of committed instruction
2108system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.42% # Class of committed instruction
2109system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction
2110system.cpu1.commit.op_class_0::SimdFloatMisc 39649 0.01% 69.43% # Class of committed instruction
2111system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction
2112system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction
2113system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction
2114system.cpu1.commit.op_class_0::MemRead 83656993 16.18% 85.61% # Class of committed instruction
2115system.cpu1.commit.op_class_0::MemWrite 74394039 14.39% 100.00% # Class of committed instruction
2116system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
2117system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
2118system.cpu1.commit.op_class_0::total 516984781 # Class of committed instruction
2119system.cpu1.commit.bw_lim_events 12767271 # number cycles where commit BW limit reached
2120system.cpu1.rob.rob_reads 1208536006 # The number of ROB reads
2121system.cpu1.rob.rob_writes 1133266670 # The number of ROB writes
2122system.cpu1.timesIdled 962801 # Number of times that the entire CPU went into an idle state and unscheduled itself
2123system.cpu1.idleCycles 17758138 # Total number of cycles that the CPU has spent unscheduled due to idling
2124system.cpu1.quiesceCycles 94081707774 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
2125system.cpu1.committedInsts 439804157 # Number of Instructions Simulated
2126system.cpu1.committedOps 516984781 # Number of Ops (including micro ops) Simulated
2127system.cpu1.cpi 1.567118 # CPI: Cycles Per Instruction
2128system.cpu1.cpi_total 1.567118 # CPI: Total CPI of All Threads
2129system.cpu1.ipc 0.638114 # IPC: Instructions Per Cycle
2130system.cpu1.ipc_total 0.638114 # IPC: Total IPC of All Threads
2131system.cpu1.int_regfile_reads 649922276 # number of integer regfile reads
2132system.cpu1.int_regfile_writes 385926927 # number of integer regfile writes
2133system.cpu1.fp_regfile_reads 666608 # number of floating regfile reads
2134system.cpu1.fp_regfile_writes 325148 # number of floating regfile writes
2135system.cpu1.cc_regfile_reads 119080359 # number of cc regfile reads
2136system.cpu1.cc_regfile_writes 119756232 # number of cc regfile writes
2137system.cpu1.misc_regfile_reads 2706897787 # number of misc regfile reads
2138system.cpu1.misc_regfile_writes 15455536 # number of misc regfile writes
2139system.cpu1.dcache.tags.replacements 5466279 # number of replacements
2140system.cpu1.dcache.tags.tagsinuse 430.006906 # Cycle average of tags in use
2141system.cpu1.dcache.tags.total_refs 146874051 # Total number of references to valid blocks.
2142system.cpu1.dcache.tags.sampled_refs 5466791 # Sample count of references to valid blocks.
2143system.cpu1.dcache.tags.avg_refs 26.866593 # Average number of references to valid blocks.
2144system.cpu1.dcache.tags.warmup_cycle 8478589492000 # Cycle when the warmup percentage was hit.
2145system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.006906 # Average occupied blocks per requestor
2146system.cpu1.dcache.tags.occ_percent::cpu1.data 0.839857 # Average percentage of cache occupancy
2147system.cpu1.dcache.tags.occ_percent::total 0.839857 # Average percentage of cache occupancy
2148system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2149system.cpu1.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
2150system.cpu1.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
2151system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
2152system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2153system.cpu1.dcache.tags.tag_accesses 328243838 # Number of tag accesses
2154system.cpu1.dcache.tags.data_accesses 328243838 # Number of data accesses
2155system.cpu1.dcache.ReadReq_hits::cpu1.data 77663514 # number of ReadReq hits
2156system.cpu1.dcache.ReadReq_hits::total 77663514 # number of ReadReq hits
2157system.cpu1.dcache.WriteReq_hits::cpu1.data 64795157 # number of WriteReq hits
2158system.cpu1.dcache.WriteReq_hits::total 64795157 # number of WriteReq hits
2159system.cpu1.dcache.SoftPFReq_hits::cpu1.data 170774 # number of SoftPFReq hits
2160system.cpu1.dcache.SoftPFReq_hits::total 170774 # number of SoftPFReq hits
2161system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 62879 # number of WriteInvalidateReq hits
2162system.cpu1.dcache.WriteInvalidateReq_hits::total 62879 # number of WriteInvalidateReq hits
2163system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1733317 # number of LoadLockedReq hits
2164system.cpu1.dcache.LoadLockedReq_hits::total 1733317 # number of LoadLockedReq hits
2165system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1753267 # number of StoreCondReq hits
2166system.cpu1.dcache.StoreCondReq_hits::total 1753267 # number of StoreCondReq hits
2167system.cpu1.dcache.demand_hits::cpu1.data 142458671 # number of demand (read+write) hits
2168system.cpu1.dcache.demand_hits::total 142458671 # number of demand (read+write) hits
2169system.cpu1.dcache.overall_hits::cpu1.data 142629445 # number of overall hits
2170system.cpu1.dcache.overall_hits::total 142629445 # number of overall hits
2171system.cpu1.dcache.ReadReq_misses::cpu1.data 6440843 # number of ReadReq misses
2172system.cpu1.dcache.ReadReq_misses::total 6440843 # number of ReadReq misses
2173system.cpu1.dcache.WriteReq_misses::cpu1.data 7141641 # number of WriteReq misses
2174system.cpu1.dcache.WriteReq_misses::total 7141641 # number of WriteReq misses
2175system.cpu1.dcache.SoftPFReq_misses::cpu1.data 671959 # number of SoftPFReq misses
2176system.cpu1.dcache.SoftPFReq_misses::total 671959 # number of SoftPFReq misses
2177system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 448993 # number of WriteInvalidateReq misses
2178system.cpu1.dcache.WriteInvalidateReq_misses::total 448993 # number of WriteInvalidateReq misses
2179system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 259783 # number of LoadLockedReq misses
2180system.cpu1.dcache.LoadLockedReq_misses::total 259783 # number of LoadLockedReq misses
2181system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195367 # number of StoreCondReq misses
2182system.cpu1.dcache.StoreCondReq_misses::total 195367 # number of StoreCondReq misses
2183system.cpu1.dcache.demand_misses::cpu1.data 13582484 # number of demand (read+write) misses
2184system.cpu1.dcache.demand_misses::total 13582484 # number of demand (read+write) misses
2185system.cpu1.dcache.overall_misses::cpu1.data 14254443 # number of overall misses
2186system.cpu1.dcache.overall_misses::total 14254443 # number of overall misses
2187system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96129677540 # number of ReadReq miss cycles
2188system.cpu1.dcache.ReadReq_miss_latency::total 96129677540 # number of ReadReq miss cycles
2189system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 127902484654 # number of WriteReq miss cycles
2190system.cpu1.dcache.WriteReq_miss_latency::total 127902484654 # number of WriteReq miss cycles
2191system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 14399209171 # number of WriteInvalidateReq miss cycles
2192system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 14399209171 # number of WriteInvalidateReq miss cycles
2193system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3810993278 # number of LoadLockedReq miss cycles
2194system.cpu1.dcache.LoadLockedReq_miss_latency::total 3810993278 # number of LoadLockedReq miss cycles
2195system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4142660469 # number of StoreCondReq miss cycles
2196system.cpu1.dcache.StoreCondReq_miss_latency::total 4142660469 # number of StoreCondReq miss cycles
2197system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3781500 # number of StoreCondFailReq miss cycles
2198system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3781500 # number of StoreCondFailReq miss cycles
2199system.cpu1.dcache.demand_miss_latency::cpu1.data 224032162194 # number of demand (read+write) miss cycles
2200system.cpu1.dcache.demand_miss_latency::total 224032162194 # number of demand (read+write) miss cycles
2201system.cpu1.dcache.overall_miss_latency::cpu1.data 224032162194 # number of overall miss cycles
2202system.cpu1.dcache.overall_miss_latency::total 224032162194 # number of overall miss cycles
2203system.cpu1.dcache.ReadReq_accesses::cpu1.data 84104357 # number of ReadReq accesses(hits+misses)
2204system.cpu1.dcache.ReadReq_accesses::total 84104357 # number of ReadReq accesses(hits+misses)
2205system.cpu1.dcache.WriteReq_accesses::cpu1.data 71936798 # number of WriteReq accesses(hits+misses)
2206system.cpu1.dcache.WriteReq_accesses::total 71936798 # number of WriteReq accesses(hits+misses)
2207system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 842733 # number of SoftPFReq accesses(hits+misses)
2208system.cpu1.dcache.SoftPFReq_accesses::total 842733 # number of SoftPFReq accesses(hits+misses)
2209system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 511872 # number of WriteInvalidateReq accesses(hits+misses)
2210system.cpu1.dcache.WriteInvalidateReq_accesses::total 511872 # number of WriteInvalidateReq accesses(hits+misses)
2211system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1993100 # number of LoadLockedReq accesses(hits+misses)
2212system.cpu1.dcache.LoadLockedReq_accesses::total 1993100 # number of LoadLockedReq accesses(hits+misses)
2213system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1948634 # number of StoreCondReq accesses(hits+misses)
2214system.cpu1.dcache.StoreCondReq_accesses::total 1948634 # number of StoreCondReq accesses(hits+misses)
2215system.cpu1.dcache.demand_accesses::cpu1.data 156041155 # number of demand (read+write) accesses
2216system.cpu1.dcache.demand_accesses::total 156041155 # number of demand (read+write) accesses
2217system.cpu1.dcache.overall_accesses::cpu1.data 156883888 # number of overall (read+write) accesses
2218system.cpu1.dcache.overall_accesses::total 156883888 # number of overall (read+write) accesses
2219system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.076582 # miss rate for ReadReq accesses
2220system.cpu1.dcache.ReadReq_miss_rate::total 0.076582 # miss rate for ReadReq accesses
2221system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.099277 # miss rate for WriteReq accesses
2222system.cpu1.dcache.WriteReq_miss_rate::total 0.099277 # miss rate for WriteReq accesses
2223system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.797357 # miss rate for SoftPFReq accesses
2224system.cpu1.dcache.SoftPFReq_miss_rate::total 0.797357 # miss rate for SoftPFReq accesses
2225system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.877159 # miss rate for WriteInvalidateReq accesses
2226system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.877159 # miss rate for WriteInvalidateReq accesses
2227system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.130341 # miss rate for LoadLockedReq accesses
2228system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.130341 # miss rate for LoadLockedReq accesses
2229system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100258 # miss rate for StoreCondReq accesses
2230system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100258 # miss rate for StoreCondReq accesses
2231system.cpu1.dcache.demand_miss_rate::cpu1.data 0.087044 # miss rate for demand accesses
2232system.cpu1.dcache.demand_miss_rate::total 0.087044 # miss rate for demand accesses
2233system.cpu1.dcache.overall_miss_rate::cpu1.data 0.090860 # miss rate for overall accesses
2234system.cpu1.dcache.overall_miss_rate::total 0.090860 # miss rate for overall accesses
2235system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14925.014868 # average ReadReq miss latency
2236system.cpu1.dcache.ReadReq_avg_miss_latency::total 14925.014868 # average ReadReq miss latency
2237system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17909.397106 # average WriteReq miss latency
2238system.cpu1.dcache.WriteReq_avg_miss_latency::total 17909.397106 # average WriteReq miss latency
2239system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 32070.008154 # average WriteInvalidateReq miss latency
2240system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 32070.008154 # average WriteInvalidateReq miss latency
2241system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14669.910187 # average LoadLockedReq miss latency
2242system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14669.910187 # average LoadLockedReq miss latency
2243system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21204.504696 # average StoreCondReq miss latency
2244system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21204.504696 # average StoreCondReq miss latency
2245system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
2246system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
2247system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16494.196658 # average overall miss latency
2248system.cpu1.dcache.demand_avg_miss_latency::total 16494.196658 # average overall miss latency
2249system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15716.654954 # average overall miss latency
2250system.cpu1.dcache.overall_avg_miss_latency::total 15716.654954 # average overall miss latency
2251system.cpu1.dcache.blocked_cycles::no_mshrs 3725007 # number of cycles access was blocked
2252system.cpu1.dcache.blocked_cycles::no_targets 19991584 # number of cycles access was blocked
2253system.cpu1.dcache.blocked::no_mshrs 377661 # number of cycles access was blocked
2254system.cpu1.dcache.blocked::no_targets 721598 # number of cycles access was blocked
2255system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.863362 # average number of cycles each access was blocked
2256system.cpu1.dcache.avg_blocked_cycles::no_targets 27.704600 # average number of cycles each access was blocked
2257system.cpu1.dcache.fast_writes 0 # number of fast writes performed
2258system.cpu1.dcache.cache_copies 0 # number of cache copies performed
2259system.cpu1.dcache.writebacks::writebacks 3504875 # number of writebacks
2260system.cpu1.dcache.writebacks::total 3504875 # number of writebacks
2261system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3270021 # number of ReadReq MSHR hits
2262system.cpu1.dcache.ReadReq_mshr_hits::total 3270021 # number of ReadReq MSHR hits
2263system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5779466 # number of WriteReq MSHR hits
2264system.cpu1.dcache.WriteReq_mshr_hits::total 5779466 # number of WriteReq MSHR hits
2265system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3415 # number of WriteInvalidateReq MSHR hits
2266system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3415 # number of WriteInvalidateReq MSHR hits
2267system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 132178 # number of LoadLockedReq MSHR hits
2268system.cpu1.dcache.LoadLockedReq_mshr_hits::total 132178 # number of LoadLockedReq MSHR hits
2269system.cpu1.dcache.demand_mshr_hits::cpu1.data 9049487 # number of demand (read+write) MSHR hits
2270system.cpu1.dcache.demand_mshr_hits::total 9049487 # number of demand (read+write) MSHR hits
2271system.cpu1.dcache.overall_mshr_hits::cpu1.data 9049487 # number of overall MSHR hits
2272system.cpu1.dcache.overall_mshr_hits::total 9049487 # number of overall MSHR hits
2273system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3170822 # number of ReadReq MSHR misses
2274system.cpu1.dcache.ReadReq_mshr_misses::total 3170822 # number of ReadReq MSHR misses
2275system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1362175 # number of WriteReq MSHR misses
2276system.cpu1.dcache.WriteReq_mshr_misses::total 1362175 # number of WriteReq MSHR misses
2277system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 671771 # number of SoftPFReq MSHR misses
2278system.cpu1.dcache.SoftPFReq_mshr_misses::total 671771 # number of SoftPFReq MSHR misses
2279system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 445578 # number of WriteInvalidateReq MSHR misses
2280system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 445578 # number of WriteInvalidateReq MSHR misses
2281system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 127605 # number of LoadLockedReq MSHR misses
2282system.cpu1.dcache.LoadLockedReq_mshr_misses::total 127605 # number of LoadLockedReq MSHR misses
2283system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195366 # number of StoreCondReq MSHR misses
2284system.cpu1.dcache.StoreCondReq_mshr_misses::total 195366 # number of StoreCondReq MSHR misses
2285system.cpu1.dcache.demand_mshr_misses::cpu1.data 4532997 # number of demand (read+write) MSHR misses
2286system.cpu1.dcache.demand_mshr_misses::total 4532997 # number of demand (read+write) MSHR misses
2287system.cpu1.dcache.overall_mshr_misses::cpu1.data 5204768 # number of overall MSHR misses
2288system.cpu1.dcache.overall_mshr_misses::total 5204768 # number of overall MSHR misses
2289system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7126 # number of ReadReq MSHR uncacheable
2290system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7126 # number of ReadReq MSHR uncacheable
2291system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7600 # number of WriteReq MSHR uncacheable
2292system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7600 # number of WriteReq MSHR uncacheable
2293system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14726 # number of overall MSHR uncacheable misses
2294system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14726 # number of overall MSHR uncacheable misses
2295system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42364690330 # number of ReadReq MSHR miss cycles
2296system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42364690330 # number of ReadReq MSHR miss cycles
2297system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24508372089 # number of WriteReq MSHR miss cycles
2298system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24508372089 # number of WriteReq MSHR miss cycles
2299system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14203530799 # number of SoftPFReq MSHR miss cycles
2300system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14203530799 # number of SoftPFReq MSHR miss cycles
2301system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 13616215076 # number of WriteInvalidateReq MSHR miss cycles
2302system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 13616215076 # number of WriteInvalidateReq MSHR miss cycles
2303system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1679833771 # number of LoadLockedReq MSHR miss cycles
2304system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1679833771 # number of LoadLockedReq MSHR miss cycles
2305system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3840214031 # number of StoreCondReq MSHR miss cycles
2306system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3840214031 # number of StoreCondReq MSHR miss cycles
2307system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3660000 # number of StoreCondFailReq MSHR miss cycles
2308system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3660000 # number of StoreCondFailReq MSHR miss cycles
2309system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 66873062419 # number of demand (read+write) MSHR miss cycles
2310system.cpu1.dcache.demand_mshr_miss_latency::total 66873062419 # number of demand (read+write) MSHR miss cycles
2311system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 81076593218 # number of overall MSHR miss cycles
2312system.cpu1.dcache.overall_mshr_miss_latency::total 81076593218 # number of overall MSHR miss cycles
2313system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 831425000 # number of ReadReq MSHR uncacheable cycles
2314system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 831425000 # number of ReadReq MSHR uncacheable cycles
2315system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 995372500 # number of WriteReq MSHR uncacheable cycles
2316system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 995372500 # number of WriteReq MSHR uncacheable cycles
2317system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1826797500 # number of overall MSHR uncacheable cycles
2318system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1826797500 # number of overall MSHR uncacheable cycles
2319system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037701 # mshr miss rate for ReadReq accesses
2320system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037701 # mshr miss rate for ReadReq accesses
2321system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018936 # mshr miss rate for WriteReq accesses
2322system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018936 # mshr miss rate for WriteReq accesses
2323system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.797134 # mshr miss rate for SoftPFReq accesses
2324system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.797134 # mshr miss rate for SoftPFReq accesses
2325system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.870487 # mshr miss rate for WriteInvalidateReq accesses
2326system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.870487 # mshr miss rate for WriteInvalidateReq accesses
2327system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064023 # mshr miss rate for LoadLockedReq accesses
2328system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064023 # mshr miss rate for LoadLockedReq accesses
2329system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100258 # mshr miss rate for StoreCondReq accesses
2330system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100258 # mshr miss rate for StoreCondReq accesses
2331system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029050 # mshr miss rate for demand accesses
2332system.cpu1.dcache.demand_mshr_miss_rate::total 0.029050 # mshr miss rate for demand accesses
2333system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033176 # mshr miss rate for overall accesses
2334system.cpu1.dcache.overall_mshr_miss_rate::total 0.033176 # mshr miss rate for overall accesses
2335system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13360.791091 # average ReadReq mshr miss latency
2336system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13360.791091 # average ReadReq mshr miss latency
2337system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17992.087719 # average WriteReq mshr miss latency
2338system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17992.087719 # average WriteReq mshr miss latency
2339system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21143.411667 # average SoftPFReq mshr miss latency
2340system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21143.411667 # average SoftPFReq mshr miss latency
2341system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30558.544354 # average WriteInvalidateReq mshr miss latency
2342system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 30558.544354 # average WriteInvalidateReq mshr miss latency
2343system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13164.325622 # average LoadLockedReq mshr miss latency
2344system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13164.325622 # average LoadLockedReq mshr miss latency
2345system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19656.511527 # average StoreCondReq mshr miss latency
2346system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19656.511527 # average StoreCondReq mshr miss latency
2347system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
2348system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
2349system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14752.505333 # average overall mshr miss latency
2350system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14752.505333 # average overall mshr miss latency
2351system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15577.369293 # average overall mshr miss latency
2352system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15577.369293 # average overall mshr miss latency
2353system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116674.852652 # average ReadReq mshr uncacheable latency
2354system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 116674.852652 # average ReadReq mshr uncacheable latency
2355system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 130970.065789 # average WriteReq mshr uncacheable latency
2356system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 130970.065789 # average WriteReq mshr uncacheable latency
2357system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124052.526144 # average overall mshr uncacheable latency
2358system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124052.526144 # average overall mshr uncacheable latency
2359system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
2360system.cpu1.icache.tags.replacements 5740789 # number of replacements
2361system.cpu1.icache.tags.tagsinuse 501.866118 # Cycle average of tags in use
2362system.cpu1.icache.tags.total_refs 196754052 # Total number of references to valid blocks.
2363system.cpu1.icache.tags.sampled_refs 5741301 # Sample count of references to valid blocks.
2364system.cpu1.icache.tags.avg_refs 34.269942 # Average number of references to valid blocks.
2365system.cpu1.icache.tags.warmup_cycle 8518317120500 # Cycle when the warmup percentage was hit.
2366system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.866118 # Average occupied blocks per requestor
2367system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980207 # Average percentage of cache occupancy
2368system.cpu1.icache.tags.occ_percent::total 0.980207 # Average percentage of cache occupancy
2369system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
2370system.cpu1.icache.tags.age_task_id_blocks_1024::0 334 # Occupied blocks per task id
2371system.cpu1.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id
2372system.cpu1.icache.tags.age_task_id_blocks_1024::2 124 # Occupied blocks per task id
2373system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
2374system.cpu1.icache.tags.tag_accesses 411371773 # Number of tag accesses
2375system.cpu1.icache.tags.data_accesses 411371773 # Number of data accesses
2376system.cpu1.icache.ReadReq_hits::cpu1.inst 196754052 # number of ReadReq hits
2377system.cpu1.icache.ReadReq_hits::total 196754052 # number of ReadReq hits
2378system.cpu1.icache.demand_hits::cpu1.inst 196754052 # number of demand (read+write) hits
2379system.cpu1.icache.demand_hits::total 196754052 # number of demand (read+write) hits
2380system.cpu1.icache.overall_hits::cpu1.inst 196754052 # number of overall hits
2381system.cpu1.icache.overall_hits::total 196754052 # number of overall hits
2382system.cpu1.icache.ReadReq_misses::cpu1.inst 6061167 # number of ReadReq misses
2383system.cpu1.icache.ReadReq_misses::total 6061167 # number of ReadReq misses
2384system.cpu1.icache.demand_misses::cpu1.inst 6061167 # number of demand (read+write) misses
2385system.cpu1.icache.demand_misses::total 6061167 # number of demand (read+write) misses
2386system.cpu1.icache.overall_misses::cpu1.inst 6061167 # number of overall misses
2387system.cpu1.icache.overall_misses::total 6061167 # number of overall misses
2388system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 63767181305 # number of ReadReq miss cycles
2389system.cpu1.icache.ReadReq_miss_latency::total 63767181305 # number of ReadReq miss cycles
2390system.cpu1.icache.demand_miss_latency::cpu1.inst 63767181305 # number of demand (read+write) miss cycles
2391system.cpu1.icache.demand_miss_latency::total 63767181305 # number of demand (read+write) miss cycles
2392system.cpu1.icache.overall_miss_latency::cpu1.inst 63767181305 # number of overall miss cycles
2393system.cpu1.icache.overall_miss_latency::total 63767181305 # number of overall miss cycles
2394system.cpu1.icache.ReadReq_accesses::cpu1.inst 202815219 # number of ReadReq accesses(hits+misses)
2395system.cpu1.icache.ReadReq_accesses::total 202815219 # number of ReadReq accesses(hits+misses)
2396system.cpu1.icache.demand_accesses::cpu1.inst 202815219 # number of demand (read+write) accesses
2397system.cpu1.icache.demand_accesses::total 202815219 # number of demand (read+write) accesses
2398system.cpu1.icache.overall_accesses::cpu1.inst 202815219 # number of overall (read+write) accesses
2399system.cpu1.icache.overall_accesses::total 202815219 # number of overall (read+write) accesses
2400system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029885 # miss rate for ReadReq accesses
2401system.cpu1.icache.ReadReq_miss_rate::total 0.029885 # miss rate for ReadReq accesses
2402system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029885 # miss rate for demand accesses
2403system.cpu1.icache.demand_miss_rate::total 0.029885 # miss rate for demand accesses
2404system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029885 # miss rate for overall accesses
2405system.cpu1.icache.overall_miss_rate::total 0.029885 # miss rate for overall accesses
2406system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10520.611180 # average ReadReq miss latency
2407system.cpu1.icache.ReadReq_avg_miss_latency::total 10520.611180 # average ReadReq miss latency
2408system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10520.611180 # average overall miss latency
2409system.cpu1.icache.demand_avg_miss_latency::total 10520.611180 # average overall miss latency
2410system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10520.611180 # average overall miss latency
2411system.cpu1.icache.overall_avg_miss_latency::total 10520.611180 # average overall miss latency
2412system.cpu1.icache.blocked_cycles::no_mshrs 8678948 # number of cycles access was blocked
2413system.cpu1.icache.blocked_cycles::no_targets 76 # number of cycles access was blocked
2414system.cpu1.icache.blocked::no_mshrs 693947 # number of cycles access was blocked
2415system.cpu1.icache.blocked::no_targets 2 # number of cycles access was blocked
2416system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.506644 # average number of cycles each access was blocked
2417system.cpu1.icache.avg_blocked_cycles::no_targets 38 # average number of cycles each access was blocked
2418system.cpu1.icache.fast_writes 0 # number of fast writes performed
2419system.cpu1.icache.cache_copies 0 # number of cache copies performed
2420system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 319831 # number of ReadReq MSHR hits
2421system.cpu1.icache.ReadReq_mshr_hits::total 319831 # number of ReadReq MSHR hits
2422system.cpu1.icache.demand_mshr_hits::cpu1.inst 319831 # number of demand (read+write) MSHR hits
2423system.cpu1.icache.demand_mshr_hits::total 319831 # number of demand (read+write) MSHR hits
2424system.cpu1.icache.overall_mshr_hits::cpu1.inst 319831 # number of overall MSHR hits
2425system.cpu1.icache.overall_mshr_hits::total 319831 # number of overall MSHR hits
2426system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5741336 # number of ReadReq MSHR misses
2427system.cpu1.icache.ReadReq_mshr_misses::total 5741336 # number of ReadReq MSHR misses
2428system.cpu1.icache.demand_mshr_misses::cpu1.inst 5741336 # number of demand (read+write) MSHR misses
2429system.cpu1.icache.demand_mshr_misses::total 5741336 # number of demand (read+write) MSHR misses
2430system.cpu1.icache.overall_mshr_misses::cpu1.inst 5741336 # number of overall MSHR misses
2431system.cpu1.icache.overall_mshr_misses::total 5741336 # number of overall MSHR misses
2432system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
2433system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable
2434system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
2435system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses
2436system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 54923658725 # number of ReadReq MSHR miss cycles
2437system.cpu1.icache.ReadReq_mshr_miss_latency::total 54923658725 # number of ReadReq MSHR miss cycles
2438system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 54923658725 # number of demand (read+write) MSHR miss cycles
2439system.cpu1.icache.demand_mshr_miss_latency::total 54923658725 # number of demand (read+write) MSHR miss cycles
2440system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 54923658725 # number of overall MSHR miss cycles
2441system.cpu1.icache.overall_mshr_miss_latency::total 54923658725 # number of overall MSHR miss cycles
2442system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6151998 # number of ReadReq MSHR uncacheable cycles
2443system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6151998 # number of ReadReq MSHR uncacheable cycles
2444system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6151998 # number of overall MSHR uncacheable cycles
2445system.cpu1.icache.overall_mshr_uncacheable_latency::total 6151998 # number of overall MSHR uncacheable cycles
2446system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028308 # mshr miss rate for ReadReq accesses
2447system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028308 # mshr miss rate for ReadReq accesses
2448system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028308 # mshr miss rate for demand accesses
2449system.cpu1.icache.demand_mshr_miss_rate::total 0.028308 # mshr miss rate for demand accesses
2450system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028308 # mshr miss rate for overall accesses
2451system.cpu1.icache.overall_mshr_miss_rate::total 0.028308 # mshr miss rate for overall accesses
2452system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9566.355065 # average ReadReq mshr miss latency
2453system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9566.355065 # average ReadReq mshr miss latency
2454system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9566.355065 # average overall mshr miss latency
2455system.cpu1.icache.demand_avg_mshr_miss_latency::total 9566.355065 # average overall mshr miss latency
2456system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9566.355065 # average overall mshr miss latency
2457system.cpu1.icache.overall_avg_mshr_miss_latency::total 9566.355065 # average overall mshr miss latency
2458system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91820.865672 # average ReadReq mshr uncacheable latency
2459system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 91820.865672 # average ReadReq mshr uncacheable latency
2460system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91820.865672 # average overall mshr uncacheable latency
2461system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 91820.865672 # average overall mshr uncacheable latency
2462system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2463system.cpu1.l2cache.prefetcher.num_hwpf_issued 7332494 # number of hwpf issued
2464system.cpu1.l2cache.prefetcher.pfIdentified 7535643 # number of prefetch candidates identified
2465system.cpu1.l2cache.prefetcher.pfBufferHit 175627 # number of redundant prefetches already in prefetch queue
2466system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
2467system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
2468system.cpu1.l2cache.prefetcher.pfSpanPage 929621 # number of prefetches not generated due to page crossing
2469system.cpu1.l2cache.tags.replacements 2299794 # number of replacements
2470system.cpu1.l2cache.tags.tagsinuse 13092.282613 # Cycle average of tags in use
2471system.cpu1.l2cache.tags.total_refs 11932680 # Total number of references to valid blocks.
2472system.cpu1.l2cache.tags.sampled_refs 2315440 # Sample count of references to valid blocks.
2473system.cpu1.l2cache.tags.avg_refs 5.153526 # Average number of references to valid blocks.
2474system.cpu1.l2cache.tags.warmup_cycle 9714628416493 # Cycle when the warmup percentage was hit.
2475system.cpu1.l2cache.tags.occ_blocks::writebacks 5051.662856 # Average occupied blocks per requestor
2476system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 84.315143 # Average occupied blocks per requestor
2477system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 91.749127 # Average occupied blocks per requestor
2478system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3269.093236 # Average occupied blocks per requestor
2479system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3705.071376 # Average occupied blocks per requestor
2480system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 890.390874 # Average occupied blocks per requestor
2481system.cpu1.l2cache.tags.occ_percent::writebacks 0.308329 # Average percentage of cache occupancy
2482system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.005146 # Average percentage of cache occupancy
2483system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005600 # Average percentage of cache occupancy
2484system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199530 # Average percentage of cache occupancy
2485system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.226140 # Average percentage of cache occupancy
2486system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.054345 # Average percentage of cache occupancy
2487system.cpu1.l2cache.tags.occ_percent::total 0.799090 # Average percentage of cache occupancy
2488system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1406 # Occupied blocks per task id
2489system.cpu1.l2cache.tags.occ_task_id_blocks::1023 105 # Occupied blocks per task id
2490system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14135 # Occupied blocks per task id
2491system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 76 # Occupied blocks per task id
2492system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 267 # Occupied blocks per task id
2493system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 643 # Occupied blocks per task id
2494system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 420 # Occupied blocks per task id
2495system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id
2496system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id
2497system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 73 # Occupied blocks per task id
2498system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id
2499system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id
2500system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id
2501system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 703 # Occupied blocks per task id
2502system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4677 # Occupied blocks per task id
2503system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4917 # Occupied blocks per task id
2504system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3606 # Occupied blocks per task id
2505system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.085815 # Percentage of cache occupancy per task id
2506system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006409 # Percentage of cache occupancy per task id
2507system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.862732 # Percentage of cache occupancy per task id
2508system.cpu1.l2cache.tags.tag_accesses 260544625 # Number of tag accesses
2509system.cpu1.l2cache.tags.data_accesses 260544625 # Number of data accesses
2510system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 585527 # number of ReadReq hits
2511system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 176354 # number of ReadReq hits
2512system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5103092 # number of ReadReq hits
2513system.cpu1.l2cache.ReadReq_hits::cpu1.data 2955317 # number of ReadReq hits
2514system.cpu1.l2cache.ReadReq_hits::total 8820290 # number of ReadReq hits
2515system.cpu1.l2cache.Writeback_hits::writebacks 3504868 # number of Writeback hits
2516system.cpu1.l2cache.Writeback_hits::total 3504868 # number of Writeback hits
2517system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 166502 # number of WriteInvalidateReq hits
2518system.cpu1.l2cache.WriteInvalidateReq_hits::total 166502 # number of WriteInvalidateReq hits
2519system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 71993 # number of UpgradeReq hits
2520system.cpu1.l2cache.UpgradeReq_hits::total 71993 # number of UpgradeReq hits
2521system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 35298 # number of SCUpgradeReq hits
2522system.cpu1.l2cache.SCUpgradeReq_hits::total 35298 # number of SCUpgradeReq hits
2523system.cpu1.l2cache.ReadExReq_hits::cpu1.data 907237 # number of ReadExReq hits
2524system.cpu1.l2cache.ReadExReq_hits::total 907237 # number of ReadExReq hits
2525system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 585527 # number of demand (read+write) hits
2526system.cpu1.l2cache.demand_hits::cpu1.itb.walker 176354 # number of demand (read+write) hits
2527system.cpu1.l2cache.demand_hits::cpu1.inst 5103092 # number of demand (read+write) hits
2528system.cpu1.l2cache.demand_hits::cpu1.data 3862554 # number of demand (read+write) hits
2529system.cpu1.l2cache.demand_hits::total 9727527 # number of demand (read+write) hits
2530system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 585527 # number of overall hits
2531system.cpu1.l2cache.overall_hits::cpu1.itb.walker 176354 # number of overall hits
2532system.cpu1.l2cache.overall_hits::cpu1.inst 5103092 # number of overall hits
2533system.cpu1.l2cache.overall_hits::cpu1.data 3862554 # number of overall hits
2534system.cpu1.l2cache.overall_hits::total 9727527 # number of overall hits
2535system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 13010 # number of ReadReq misses
2536system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9568 # number of ReadReq misses
2537system.cpu1.l2cache.ReadReq_misses::cpu1.inst 638215 # number of ReadReq misses
2538system.cpu1.l2cache.ReadReq_misses::cpu1.data 1012370 # number of ReadReq misses
2539system.cpu1.l2cache.ReadReq_misses::total 1673163 # number of ReadReq misses
2540system.cpu1.l2cache.Writeback_misses::writebacks 6 # number of Writeback misses
2541system.cpu1.l2cache.Writeback_misses::total 6 # number of Writeback misses
2542system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 277800 # number of WriteInvalidateReq misses
2543system.cpu1.l2cache.WriteInvalidateReq_misses::total 277800 # number of WriteInvalidateReq misses
2544system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 139883 # number of UpgradeReq misses
2545system.cpu1.l2cache.UpgradeReq_misses::total 139883 # number of UpgradeReq misses
2546system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 160055 # number of SCUpgradeReq misses
2547system.cpu1.l2cache.SCUpgradeReq_misses::total 160055 # number of SCUpgradeReq misses
2548system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 13 # number of SCUpgradeFailReq misses
2549system.cpu1.l2cache.SCUpgradeFailReq_misses::total 13 # number of SCUpgradeFailReq misses
2550system.cpu1.l2cache.ReadExReq_misses::cpu1.data 249549 # number of ReadExReq misses
2551system.cpu1.l2cache.ReadExReq_misses::total 249549 # number of ReadExReq misses
2552system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 13010 # number of demand (read+write) misses
2553system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9568 # number of demand (read+write) misses
2554system.cpu1.l2cache.demand_misses::cpu1.inst 638215 # number of demand (read+write) misses
2555system.cpu1.l2cache.demand_misses::cpu1.data 1261919 # number of demand (read+write) misses
2556system.cpu1.l2cache.demand_misses::total 1922712 # number of demand (read+write) misses
2557system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 13010 # number of overall misses
2558system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9568 # number of overall misses
2559system.cpu1.l2cache.overall_misses::cpu1.inst 638215 # number of overall misses
2560system.cpu1.l2cache.overall_misses::cpu1.data 1261919 # number of overall misses
2561system.cpu1.l2cache.overall_misses::total 1922712 # number of overall misses
2562system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 512958208 # number of ReadReq miss cycles
2563system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 430734867 # number of ReadReq miss cycles
2564system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 18770053212 # number of ReadReq miss cycles
2565system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 34728720424 # number of ReadReq miss cycles
2566system.cpu1.l2cache.ReadReq_miss_latency::total 54442466711 # number of ReadReq miss cycles
2567system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 206094146 # number of WriteInvalidateReq miss cycles
2568system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 206094146 # number of WriteInvalidateReq miss cycles
2569system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3019471858 # number of UpgradeReq miss cycles
2570system.cpu1.l2cache.UpgradeReq_miss_latency::total 3019471858 # number of UpgradeReq miss cycles
2571system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3326642430 # number of SCUpgradeReq miss cycles
2572system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3326642430 # number of SCUpgradeReq miss cycles
2573system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3578499 # number of SCUpgradeFailReq miss cycles
2574system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3578499 # number of SCUpgradeFailReq miss cycles
2575system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12555468370 # number of ReadExReq miss cycles
2576system.cpu1.l2cache.ReadExReq_miss_latency::total 12555468370 # number of ReadExReq miss cycles
2577system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 512958208 # number of demand (read+write) miss cycles
2578system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 430734867 # number of demand (read+write) miss cycles
2579system.cpu1.l2cache.demand_miss_latency::cpu1.inst 18770053212 # number of demand (read+write) miss cycles
2580system.cpu1.l2cache.demand_miss_latency::cpu1.data 47284188794 # number of demand (read+write) miss cycles
2581system.cpu1.l2cache.demand_miss_latency::total 66997935081 # number of demand (read+write) miss cycles
2582system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 512958208 # number of overall miss cycles
2583system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 430734867 # number of overall miss cycles
2584system.cpu1.l2cache.overall_miss_latency::cpu1.inst 18770053212 # number of overall miss cycles
2585system.cpu1.l2cache.overall_miss_latency::cpu1.data 47284188794 # number of overall miss cycles
2586system.cpu1.l2cache.overall_miss_latency::total 66997935081 # number of overall miss cycles
2587system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 598537 # number of ReadReq accesses(hits+misses)
2588system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 185922 # number of ReadReq accesses(hits+misses)
2589system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5741307 # number of ReadReq accesses(hits+misses)
2590system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3967687 # number of ReadReq accesses(hits+misses)
2591system.cpu1.l2cache.ReadReq_accesses::total 10493453 # number of ReadReq accesses(hits+misses)
2592system.cpu1.l2cache.Writeback_accesses::writebacks 3504874 # number of Writeback accesses(hits+misses)
2593system.cpu1.l2cache.Writeback_accesses::total 3504874 # number of Writeback accesses(hits+misses)
2594system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 444302 # number of WriteInvalidateReq accesses(hits+misses)
2595system.cpu1.l2cache.WriteInvalidateReq_accesses::total 444302 # number of WriteInvalidateReq accesses(hits+misses)
2596system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 211876 # number of UpgradeReq accesses(hits+misses)
2597system.cpu1.l2cache.UpgradeReq_accesses::total 211876 # number of UpgradeReq accesses(hits+misses)
2598system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195353 # number of SCUpgradeReq accesses(hits+misses)
2599system.cpu1.l2cache.SCUpgradeReq_accesses::total 195353 # number of SCUpgradeReq accesses(hits+misses)
2600system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 13 # number of SCUpgradeFailReq accesses(hits+misses)
2601system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 13 # number of SCUpgradeFailReq accesses(hits+misses)
2602system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1156786 # number of ReadExReq accesses(hits+misses)
2603system.cpu1.l2cache.ReadExReq_accesses::total 1156786 # number of ReadExReq accesses(hits+misses)
2604system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 598537 # number of demand (read+write) accesses
2605system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 185922 # number of demand (read+write) accesses
2606system.cpu1.l2cache.demand_accesses::cpu1.inst 5741307 # number of demand (read+write) accesses
2607system.cpu1.l2cache.demand_accesses::cpu1.data 5124473 # number of demand (read+write) accesses
2608system.cpu1.l2cache.demand_accesses::total 11650239 # number of demand (read+write) accesses
2609system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 598537 # number of overall (read+write) accesses
2610system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 185922 # number of overall (read+write) accesses
2611system.cpu1.l2cache.overall_accesses::cpu1.inst 5741307 # number of overall (read+write) accesses
2612system.cpu1.l2cache.overall_accesses::cpu1.data 5124473 # number of overall (read+write) accesses
2613system.cpu1.l2cache.overall_accesses::total 11650239 # number of overall (read+write) accesses
2614system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021736 # miss rate for ReadReq accesses
2615system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.051462 # miss rate for ReadReq accesses
2616system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.111162 # miss rate for ReadReq accesses
2617system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.255154 # miss rate for ReadReq accesses
2618system.cpu1.l2cache.ReadReq_miss_rate::total 0.159448 # miss rate for ReadReq accesses
2619system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses
2620system.cpu1.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses
2621system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.625250 # miss rate for WriteInvalidateReq accesses
2622system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.625250 # miss rate for WriteInvalidateReq accesses
2623system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.660212 # miss rate for UpgradeReq accesses
2624system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.660212 # miss rate for UpgradeReq accesses
2625system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.819312 # miss rate for SCUpgradeReq accesses
2626system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.819312 # miss rate for SCUpgradeReq accesses
2627system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
2628system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
2629system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.215726 # miss rate for ReadExReq accesses
2630system.cpu1.l2cache.ReadExReq_miss_rate::total 0.215726 # miss rate for ReadExReq accesses
2631system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021736 # miss rate for demand accesses
2632system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.051462 # miss rate for demand accesses
2633system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.111162 # miss rate for demand accesses
2634system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.246253 # miss rate for demand accesses
2635system.cpu1.l2cache.demand_miss_rate::total 0.165036 # miss rate for demand accesses
2636system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021736 # miss rate for overall accesses
2637system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.051462 # miss rate for overall accesses
2638system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.111162 # miss rate for overall accesses
2639system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.246253 # miss rate for overall accesses
2640system.cpu1.l2cache.overall_miss_rate::total 0.165036 # miss rate for overall accesses
2641system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39427.994466 # average ReadReq miss latency
2642system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 45018.276233 # average ReadReq miss latency
2643system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29410.235128 # average ReadReq miss latency
2644system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 34304.375302 # average ReadReq miss latency
2645system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32538.650873 # average ReadReq miss latency
2646system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 741.879575 # average WriteInvalidateReq miss latency
2647system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 741.879575 # average WriteInvalidateReq miss latency
2648system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21585.695603 # average UpgradeReq miss latency
2649system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21585.695603 # average UpgradeReq miss latency
2650system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20784.370560 # average SCUpgradeReq miss latency
2651system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20784.370560 # average SCUpgradeReq miss latency
2652system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 275269.153846 # average SCUpgradeFailReq miss latency
2653system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 275269.153846 # average SCUpgradeFailReq miss latency
2654system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 50312.637478 # average ReadExReq miss latency
2655system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 50312.637478 # average ReadExReq miss latency
2656system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39427.994466 # average overall miss latency
2657system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 45018.276233 # average overall miss latency
2658system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29410.235128 # average overall miss latency
2659system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 37470.066458 # average overall miss latency
2660system.cpu1.l2cache.demand_avg_miss_latency::total 34845.538532 # average overall miss latency
2661system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39427.994466 # average overall miss latency
2662system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 45018.276233 # average overall miss latency
2663system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29410.235128 # average overall miss latency
2664system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 37470.066458 # average overall miss latency
2665system.cpu1.l2cache.overall_avg_miss_latency::total 34845.538532 # average overall miss latency
2666system.cpu1.l2cache.blocked_cycles::no_mshrs 20 # number of cycles access was blocked
2667system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
2668system.cpu1.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked
2669system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
2670system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 6.666667 # average number of cycles each access was blocked
2671system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
2672system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
2673system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2674system.cpu1.l2cache.writebacks::writebacks 1059677 # number of writebacks
2675system.cpu1.l2cache.writebacks::total 1059677 # number of writebacks
2676system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 6 # number of ReadReq MSHR hits
2677system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 183 # number of ReadReq MSHR hits
2678system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 3574 # number of ReadReq MSHR hits
2679system.cpu1.l2cache.ReadReq_mshr_hits::total 3763 # number of ReadReq MSHR hits
2680system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 5 # number of WriteInvalidateReq MSHR hits
2681system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 5 # number of WriteInvalidateReq MSHR hits
2682system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 19034 # number of ReadExReq MSHR hits
2683system.cpu1.l2cache.ReadExReq_mshr_hits::total 19034 # number of ReadExReq MSHR hits
2684system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 6 # number of demand (read+write) MSHR hits
2685system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 183 # number of demand (read+write) MSHR hits
2686system.cpu1.l2cache.demand_mshr_hits::cpu1.data 22608 # number of demand (read+write) MSHR hits
2687system.cpu1.l2cache.demand_mshr_hits::total 22797 # number of demand (read+write) MSHR hits
2688system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 6 # number of overall MSHR hits
2689system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 183 # number of overall MSHR hits
2690system.cpu1.l2cache.overall_mshr_hits::cpu1.data 22608 # number of overall MSHR hits
2691system.cpu1.l2cache.overall_mshr_hits::total 22797 # number of overall MSHR hits
2692system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 13004 # number of ReadReq MSHR misses
2693system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9385 # number of ReadReq MSHR misses
2694system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 638215 # number of ReadReq MSHR misses
2695system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 1008796 # number of ReadReq MSHR misses
2696system.cpu1.l2cache.ReadReq_mshr_misses::total 1669400 # number of ReadReq MSHR misses
2697system.cpu1.l2cache.Writeback_mshr_misses::writebacks 6 # number of Writeback MSHR misses
2698system.cpu1.l2cache.Writeback_mshr_misses::total 6 # number of Writeback MSHR misses
2699system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 738806 # number of HardPFReq MSHR misses
2700system.cpu1.l2cache.HardPFReq_mshr_misses::total 738806 # number of HardPFReq MSHR misses
2701system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 277795 # number of WriteInvalidateReq MSHR misses
2702system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 277795 # number of WriteInvalidateReq MSHR misses
2703system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 139883 # number of UpgradeReq MSHR misses
2704system.cpu1.l2cache.UpgradeReq_mshr_misses::total 139883 # number of UpgradeReq MSHR misses
2705system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 160055 # number of SCUpgradeReq MSHR misses
2706system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 160055 # number of SCUpgradeReq MSHR misses
2707system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 13 # number of SCUpgradeFailReq MSHR misses
2708system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 13 # number of SCUpgradeFailReq MSHR misses
2709system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 230515 # number of ReadExReq MSHR misses
2710system.cpu1.l2cache.ReadExReq_mshr_misses::total 230515 # number of ReadExReq MSHR misses
2711system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 13004 # number of demand (read+write) MSHR misses
2712system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9385 # number of demand (read+write) MSHR misses
2713system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 638215 # number of demand (read+write) MSHR misses
2714system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1239311 # number of demand (read+write) MSHR misses
2715system.cpu1.l2cache.demand_mshr_misses::total 1899915 # number of demand (read+write) MSHR misses
2716system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 13004 # number of overall MSHR misses
2717system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9385 # number of overall MSHR misses
2718system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 638215 # number of overall MSHR misses
2719system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1239311 # number of overall MSHR misses
2720system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 738806 # number of overall MSHR misses
2721system.cpu1.l2cache.overall_mshr_misses::total 2638721 # number of overall MSHR misses
2722system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
2723system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 7126 # number of ReadReq MSHR uncacheable
2724system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 7193 # number of ReadReq MSHR uncacheable
2725system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7600 # number of WriteReq MSHR uncacheable
2726system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7600 # number of WriteReq MSHR uncacheable
2727system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses
2728system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 14726 # number of overall MSHR uncacheable misses
2729system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14793 # number of overall MSHR uncacheable misses
2730system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 427470062 # number of ReadReq MSHR miss cycles
2731system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 361612807 # number of ReadReq MSHR miss cycles
2732system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 14605198288 # number of ReadReq MSHR miss cycles
2733system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 27880753226 # number of ReadReq MSHR miss cycles
2734system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 43275034383 # number of ReadReq MSHR miss cycles
2735system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 44447581689 # number of HardPFReq MSHR miss cycles
2736system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 44447581689 # number of HardPFReq MSHR miss cycles
2737system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 9533570164 # number of WriteInvalidateReq MSHR miss cycles
2738system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 9533570164 # number of WriteInvalidateReq MSHR miss cycles
2739system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2794262081 # number of UpgradeReq MSHR miss cycles
2740system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2794262081 # number of UpgradeReq MSHR miss cycles
2741system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2375248051 # number of SCUpgradeReq MSHR miss cycles
2742system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2375248051 # number of SCUpgradeReq MSHR miss cycles
2743system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3051999 # number of SCUpgradeFailReq MSHR miss cycles
2744system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3051999 # number of SCUpgradeFailReq MSHR miss cycles
2745system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8594281659 # number of ReadExReq MSHR miss cycles
2746system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8594281659 # number of ReadExReq MSHR miss cycles
2747system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 427470062 # number of demand (read+write) MSHR miss cycles
2748system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 361612807 # number of demand (read+write) MSHR miss cycles
2749system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14605198288 # number of demand (read+write) MSHR miss cycles
2750system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 36475034885 # number of demand (read+write) MSHR miss cycles
2751system.cpu1.l2cache.demand_mshr_miss_latency::total 51869316042 # number of demand (read+write) MSHR miss cycles
2752system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 427470062 # number of overall MSHR miss cycles
2753system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 361612807 # number of overall MSHR miss cycles
2754system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14605198288 # number of overall MSHR miss cycles
2755system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 36475034885 # number of overall MSHR miss cycles
2756system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 44447581689 # number of overall MSHR miss cycles
2757system.cpu1.l2cache.overall_mshr_miss_latency::total 96316897731 # number of overall MSHR miss cycles
2758system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5626000 # number of ReadReq MSHR uncacheable cycles
2759system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 774397000 # number of ReadReq MSHR uncacheable cycles
2760system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 780023000 # number of ReadReq MSHR uncacheable cycles
2761system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 938365000 # number of WriteReq MSHR uncacheable cycles
2762system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 938365000 # number of WriteReq MSHR uncacheable cycles
2763system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 5626000 # number of overall MSHR uncacheable cycles
2764system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1712762000 # number of overall MSHR uncacheable cycles
2765system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1718388000 # number of overall MSHR uncacheable cycles
2766system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021726 # mshr miss rate for ReadReq accesses
2767system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050478 # mshr miss rate for ReadReq accesses
2768system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.111162 # mshr miss rate for ReadReq accesses
2769system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.254253 # mshr miss rate for ReadReq accesses
2770system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.159090 # mshr miss rate for ReadReq accesses
2771system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses
2772system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses
2773system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
2774system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
2775system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.625239 # mshr miss rate for WriteInvalidateReq accesses
2776system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.625239 # mshr miss rate for WriteInvalidateReq accesses
2777system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.660212 # mshr miss rate for UpgradeReq accesses
2778system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.660212 # mshr miss rate for UpgradeReq accesses
2779system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.819312 # mshr miss rate for SCUpgradeReq accesses
2780system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.819312 # mshr miss rate for SCUpgradeReq accesses
2781system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
2782system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
2783system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.199272 # mshr miss rate for ReadExReq accesses
2784system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.199272 # mshr miss rate for ReadExReq accesses
2785system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021726 # mshr miss rate for demand accesses
2786system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050478 # mshr miss rate for demand accesses
2787system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.111162 # mshr miss rate for demand accesses
2788system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.241842 # mshr miss rate for demand accesses
2789system.cpu1.l2cache.demand_mshr_miss_rate::total 0.163079 # mshr miss rate for demand accesses
2790system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021726 # mshr miss rate for overall accesses
2791system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050478 # mshr miss rate for overall accesses
2792system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.111162 # mshr miss rate for overall accesses
2793system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.241842 # mshr miss rate for overall accesses
2794system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
2795system.cpu1.l2cache.overall_mshr_miss_rate::total 0.226495 # mshr miss rate for overall accesses
2796system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32872.197939 # average ReadReq mshr miss latency
2797system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38530.933085 # average ReadReq mshr miss latency
2798system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22884.448482 # average ReadReq mshr miss latency
2799system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 27637.652435 # average ReadReq mshr miss latency
2800system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25922.507717 # average ReadReq mshr miss latency
2801system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 60161.370764 # average HardPFReq mshr miss latency
2802system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 60161.370764 # average HardPFReq mshr miss latency
2803system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 34318.724829 # average WriteInvalidateReq mshr miss latency
2804system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34318.724829 # average WriteInvalidateReq mshr miss latency
2805system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19975.708850 # average UpgradeReq mshr miss latency
2806system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19975.708850 # average UpgradeReq mshr miss latency
2807system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14840.199000 # average SCUpgradeReq mshr miss latency
2808system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14840.199000 # average SCUpgradeReq mshr miss latency
2809system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 234769.153846 # average SCUpgradeFailReq mshr miss latency
2810system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 234769.153846 # average SCUpgradeFailReq mshr miss latency
2811system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37282.960584 # average ReadExReq mshr miss latency
2812system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37282.960584 # average ReadExReq mshr miss latency
2813system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32872.197939 # average overall mshr miss latency
2814system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38530.933085 # average overall mshr miss latency
2815system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22884.448482 # average overall mshr miss latency
2816system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29431.704298 # average overall mshr miss latency
2817system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27300.861376 # average overall mshr miss latency
2818system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32872.197939 # average overall mshr miss latency
2819system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38530.933085 # average overall mshr miss latency
2820system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22884.448482 # average overall mshr miss latency
2821system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29431.704298 # average overall mshr miss latency
2822system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 60161.370764 # average overall mshr miss latency
2823system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36501.357184 # average overall mshr miss latency
2824system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83970.149254 # average ReadReq mshr uncacheable latency
2825system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 108672.046029 # average ReadReq mshr uncacheable latency
2826system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 108441.957459 # average ReadReq mshr uncacheable latency
2827system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 123469.078947 # average WriteReq mshr uncacheable latency
2828system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 123469.078947 # average WriteReq mshr uncacheable latency
2829system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83970.149254 # average overall mshr uncacheable latency
2830system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 116308.705691 # average overall mshr uncacheable latency
2831system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 116162.238897 # average overall mshr uncacheable latency
2832system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
2833system.cpu1.toL2Bus.trans_dist::ReadReq 13189135 # Transaction distribution
2834system.cpu1.toL2Bus.trans_dist::ReadResp 10749038 # Transaction distribution
2835system.cpu1.toL2Bus.trans_dist::WriteReq 38779 # Transaction distribution
2836system.cpu1.toL2Bus.trans_dist::WriteResp 7600 # Transaction distribution
2837system.cpu1.toL2Bus.trans_dist::Writeback 3504874 # Transaction distribution
2838system.cpu1.toL2Bus.trans_dist::HardPFReq 1040151 # Transaction distribution
2839system.cpu1.toL2Bus.trans_dist::HardPFResp 17 # Transaction distribution
2840system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1162830 # Transaction distribution
2841system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 444302 # Transaction distribution
2842system.cpu1.toL2Bus.trans_dist::UpgradeReq 468816 # Transaction distribution
2843system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 354419 # Transaction distribution
2844system.cpu1.toL2Bus.trans_dist::UpgradeResp 478843 # Transaction distribution
2845system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution
2846system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 143 # Transaction distribution
2847system.cpu1.toL2Bus.trans_dist::ReadExReq 1323230 # Transaction distribution
2848system.cpu1.toL2Bus.trans_dist::ReadExResp 1164313 # Transaction distribution
2849system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11482776 # Packet count per connected master and slave (bytes)
2850system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15667685 # Packet count per connected master and slave (bytes)
2851system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 405853 # Packet count per connected master and slave (bytes)
2852system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1309392 # Packet count per connected master and slave (bytes)
2853system.cpu1.toL2Bus.pkt_count::total 28865706 # Packet count per connected master and slave (bytes)
2854system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 367444720 # Cumulative packet size per connected master and slave (bytes)
2855system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 587773064 # Cumulative packet size per connected master and slave (bytes)
2856system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1487376 # Cumulative packet size per connected master and slave (bytes)
2857system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4788296 # Cumulative packet size per connected master and slave (bytes)
2858system.cpu1.toL2Bus.pkt_size::total 961493456 # Cumulative packet size per connected master and slave (bytes)
2859system.cpu1.toL2Bus.snoops 5242184 # Total snoops (count)
2860system.cpu1.toL2Bus.snoop_fanout::samples 21082310 # Request fanout histogram
2861system.cpu1.toL2Bus.snoop_fanout::mean 1.277260 # Request fanout histogram
2862system.cpu1.toL2Bus.snoop_fanout::stdev 0.447646 # Request fanout histogram
2863system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
2864system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
2865system.cpu1.toL2Bus.snoop_fanout::1 15237020 72.27% 72.27% # Request fanout histogram
2866system.cpu1.toL2Bus.snoop_fanout::2 5845290 27.73% 100.00% # Request fanout histogram
2867system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
2868system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
2869system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
2870system.cpu1.toL2Bus.snoop_fanout::total 21082310 # Request fanout histogram
2871system.cpu1.toL2Bus.reqLayer0.occupancy 12037419620 # Layer occupancy (ticks)
2872system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
2873system.cpu1.toL2Bus.snoopLayer0.occupancy 200301486 # Layer occupancy (ticks)
2874system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
2875system.cpu1.toL2Bus.respLayer0.occupancy 8624197196 # Layer occupancy (ticks)
2876system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
2877system.cpu1.toL2Bus.respLayer1.occupancy 8185098674 # Layer occupancy (ticks)
2878system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
2879system.cpu1.toL2Bus.respLayer2.occupancy 220844820 # Layer occupancy (ticks)
2880system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
2881system.cpu1.toL2Bus.respLayer3.occupancy 711986885 # Layer occupancy (ticks)
2882system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
2883system.iobus.trans_dist::ReadReq 40346 # Transaction distribution
2884system.iobus.trans_dist::ReadResp 40346 # Transaction distribution
2885system.iobus.trans_dist::WriteReq 136632 # Transaction distribution
2886system.iobus.trans_dist::WriteResp 29904 # Transaction distribution
2887system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
2888system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47732 # Packet count per connected master and slave (bytes)
2889system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
2890system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
2891system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
2892system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
2893system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
2894system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
2895system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
2896system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
2897system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
2898system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
2899system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
2900system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
2901system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
2902system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
2903system.iobus.pkt_count_system.bridge.master::total 122614 # Packet count per connected master and slave (bytes)
2904system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231262 # Packet count per connected master and slave (bytes)
2905system.iobus.pkt_count_system.realview.ide.dma::total 231262 # Packet count per connected master and slave (bytes)
2906system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
2907system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
2908system.iobus.pkt_count::total 353956 # Packet count per connected master and slave (bytes)
2909system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47752 # Cumulative packet size per connected master and slave (bytes)
2910system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
2911system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
2912system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
2913system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
2914system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2915system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2916system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2917system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
2918system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
2919system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
2920system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
2921system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
2922system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
2923system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
2924system.iobus.pkt_size_system.bridge.master::total 155744 # Cumulative packet size per connected master and slave (bytes)
2925system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339064 # Cumulative packet size per connected master and slave (bytes)
2926system.iobus.pkt_size_system.realview.ide.dma::total 7339064 # Cumulative packet size per connected master and slave (bytes)
2927system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
2928system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
2929system.iobus.pkt_size::total 7496894 # Cumulative packet size per connected master and slave (bytes)
2930system.iobus.reqLayer0.occupancy 36253000 # Layer occupancy (ticks)
2931system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
2932system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
2933system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
2934system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
2935system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
2936system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
2937system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
2938system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)

--- 11 unchanged lines hidden (view full) ---

2950system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks)
2951system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
2952system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
2953system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
2954system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
2955system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
2956system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
2957system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
2958system.iobus.reqLayer27.occupancy 607574888 # Layer occupancy (ticks)
2959system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
2960system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
2961system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
2962system.iobus.respLayer0.occupancy 92713000 # Layer occupancy (ticks)
2963system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
2964system.iobus.respLayer3.occupancy 148591827 # Layer occupancy (ticks)
2965system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
2966system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks)
2967system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
2968system.iocache.tags.replacements 115612 # number of replacements
2969system.iocache.tags.tagsinuse 11.304105 # Cycle average of tags in use
2970system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
2971system.iocache.tags.sampled_refs 115628 # Sample count of references to valid blocks.
2972system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
2973system.iocache.tags.warmup_cycle 9116941730000 # Cycle when the warmup percentage was hit.
2974system.iocache.tags.occ_blocks::realview.ethernet 3.838498 # Average occupied blocks per requestor
2975system.iocache.tags.occ_blocks::realview.ide 7.465607 # Average occupied blocks per requestor
2976system.iocache.tags.occ_percent::realview.ethernet 0.239906 # Average percentage of cache occupancy
2977system.iocache.tags.occ_percent::realview.ide 0.466600 # Average percentage of cache occupancy
2978system.iocache.tags.occ_percent::total 0.706507 # Average percentage of cache occupancy
2979system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
2980system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
2981system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
2982system.iocache.tags.tag_accesses 1041036 # Number of tag accesses
2983system.iocache.tags.data_accesses 1041036 # Number of data accesses
2984system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
2985system.iocache.ReadReq_misses::realview.ide 8903 # number of ReadReq misses
2986system.iocache.ReadReq_misses::total 8940 # number of ReadReq misses
2987system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
2988system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
2989system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses
2990system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses
2991system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
2992system.iocache.demand_misses::realview.ide 8903 # number of demand (read+write) misses
2993system.iocache.demand_misses::total 8943 # number of demand (read+write) misses
2994system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
2995system.iocache.overall_misses::realview.ide 8903 # number of overall misses
2996system.iocache.overall_misses::total 8943 # number of overall misses
2997system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles
2998system.iocache.ReadReq_miss_latency::realview.ide 1642618319 # number of ReadReq miss cycles
2999system.iocache.ReadReq_miss_latency::total 1647813819 # number of ReadReq miss cycles
3000system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
3001system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
3002system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19871992742 # number of WriteInvalidateReq miss cycles
3003system.iocache.WriteInvalidateReq_miss_latency::total 19871992742 # number of WriteInvalidateReq miss cycles
3004system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles
3005system.iocache.demand_miss_latency::realview.ide 1642618319 # number of demand (read+write) miss cycles
3006system.iocache.demand_miss_latency::total 1648182819 # number of demand (read+write) miss cycles
3007system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles
3008system.iocache.overall_miss_latency::realview.ide 1642618319 # number of overall miss cycles
3009system.iocache.overall_miss_latency::total 1648182819 # number of overall miss cycles
3010system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
3011system.iocache.ReadReq_accesses::realview.ide 8903 # number of ReadReq accesses(hits+misses)
3012system.iocache.ReadReq_accesses::total 8940 # number of ReadReq accesses(hits+misses)
3013system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
3014system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
3015system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses)
3016system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses)
3017system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
3018system.iocache.demand_accesses::realview.ide 8903 # number of demand (read+write) accesses
3019system.iocache.demand_accesses::total 8943 # number of demand (read+write) accesses
3020system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
3021system.iocache.overall_accesses::realview.ide 8903 # number of overall (read+write) accesses
3022system.iocache.overall_accesses::total 8943 # number of overall (read+write) accesses
3023system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
3024system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
3025system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
3026system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
3027system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
3028system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
3029system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
3030system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
3031system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
3032system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
3033system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
3034system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
3035system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
3036system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency
3037system.iocache.ReadReq_avg_miss_latency::realview.ide 184501.664495 # average ReadReq miss latency
3038system.iocache.ReadReq_avg_miss_latency::total 184319.219128 # average ReadReq miss latency
3039system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
3040system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
3041system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186192.871055 # average WriteInvalidateReq miss latency
3042system.iocache.WriteInvalidateReq_avg_miss_latency::total 186192.871055 # average WriteInvalidateReq miss latency
3043system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency
3044system.iocache.demand_avg_miss_latency::realview.ide 184501.664495 # average overall miss latency
3045system.iocache.demand_avg_miss_latency::total 184298.649111 # average overall miss latency
3046system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency
3047system.iocache.overall_avg_miss_latency::realview.ide 184501.664495 # average overall miss latency
3048system.iocache.overall_avg_miss_latency::total 184298.649111 # average overall miss latency
3049system.iocache.blocked_cycles::no_mshrs 111619 # number of cycles access was blocked
3050system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
3051system.iocache.blocked::no_mshrs 16154 # number of cycles access was blocked
3052system.iocache.blocked::no_targets 0 # number of cycles access was blocked
3053system.iocache.avg_blocked_cycles::no_mshrs 6.909682 # average number of cycles each access was blocked
3054system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3055system.iocache.fast_writes 0 # number of fast writes performed
3056system.iocache.cache_copies 0 # number of cache copies performed
3057system.iocache.writebacks::writebacks 106694 # number of writebacks
3058system.iocache.writebacks::total 106694 # number of writebacks
3059system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
3060system.iocache.ReadReq_mshr_misses::realview.ide 8903 # number of ReadReq MSHR misses
3061system.iocache.ReadReq_mshr_misses::total 8940 # number of ReadReq MSHR misses
3062system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
3063system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
3064system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses
3065system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses
3066system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
3067system.iocache.demand_mshr_misses::realview.ide 8903 # number of demand (read+write) MSHR misses
3068system.iocache.demand_mshr_misses::total 8943 # number of demand (read+write) MSHR misses
3069system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
3070system.iocache.overall_mshr_misses::realview.ide 8903 # number of overall MSHR misses
3071system.iocache.overall_mshr_misses::total 8943 # number of overall MSHR misses
3072system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles
3073system.iocache.ReadReq_mshr_miss_latency::realview.ide 1178449871 # number of ReadReq MSHR miss cycles
3074system.iocache.ReadReq_mshr_miss_latency::total 1181720371 # number of ReadReq MSHR miss cycles
3075system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles
3076system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles
3077system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14322034844 # number of WriteInvalidateReq MSHR miss cycles
3078system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14322034844 # number of WriteInvalidateReq MSHR miss cycles
3079system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles
3080system.iocache.demand_mshr_miss_latency::realview.ide 1178449871 # number of demand (read+write) MSHR miss cycles
3081system.iocache.demand_mshr_miss_latency::total 1181933371 # number of demand (read+write) MSHR miss cycles
3082system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles
3083system.iocache.overall_mshr_miss_latency::realview.ide 1178449871 # number of overall MSHR miss cycles
3084system.iocache.overall_mshr_miss_latency::total 1181933371 # number of overall MSHR miss cycles
3085system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
3086system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
3087system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
3088system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
3089system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
3090system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
3091system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
3092system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
3093system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
3094system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
3095system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
3096system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
3097system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
3098system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency
3099system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132365.480288 # average ReadReq mshr miss latency
3100system.iocache.ReadReq_avg_mshr_miss_latency::total 132183.486689 # average ReadReq mshr miss latency
3101system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency
3102system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency
3103system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134191.916311 # average WriteInvalidateReq mshr miss latency
3104system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134191.916311 # average WriteInvalidateReq mshr miss latency
3105system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency
3106system.iocache.demand_avg_mshr_miss_latency::realview.ide 132365.480288 # average overall mshr miss latency
3107system.iocache.demand_avg_mshr_miss_latency::total 132162.962205 # average overall mshr miss latency
3108system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency
3109system.iocache.overall_avg_mshr_miss_latency::realview.ide 132365.480288 # average overall mshr miss latency
3110system.iocache.overall_avg_mshr_miss_latency::total 132162.962205 # average overall mshr miss latency
3111system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
3112system.l2c.tags.replacements 1633733 # number of replacements
3113system.l2c.tags.tagsinuse 64442.276820 # Cycle average of tags in use
3114system.l2c.tags.total_refs 4812382 # Total number of references to valid blocks.
3115system.l2c.tags.sampled_refs 1694389 # Sample count of references to valid blocks.
3116system.l2c.tags.avg_refs 2.840187 # Average number of references to valid blocks.
3117system.l2c.tags.warmup_cycle 3265660000 # Cycle when the warmup percentage was hit.
3118system.l2c.tags.occ_blocks::writebacks 17567.436669 # Average occupied blocks per requestor
3119system.l2c.tags.occ_blocks::cpu0.dtb.walker 345.231271 # Average occupied blocks per requestor
3120system.l2c.tags.occ_blocks::cpu0.itb.walker 471.940947 # Average occupied blocks per requestor
3121system.l2c.tags.occ_blocks::cpu0.inst 4509.499901 # Average occupied blocks per requestor
3122system.l2c.tags.occ_blocks::cpu0.data 13049.127195 # Average occupied blocks per requestor
3123system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 17952.495565 # Average occupied blocks per requestor
3124system.l2c.tags.occ_blocks::cpu1.dtb.walker 52.864907 # Average occupied blocks per requestor
3125system.l2c.tags.occ_blocks::cpu1.itb.walker 70.453845 # Average occupied blocks per requestor
3126system.l2c.tags.occ_blocks::cpu1.inst 2659.379343 # Average occupied blocks per requestor
3127system.l2c.tags.occ_blocks::cpu1.data 4127.659130 # Average occupied blocks per requestor
3128system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3636.188048 # Average occupied blocks per requestor
3129system.l2c.tags.occ_percent::writebacks 0.268058 # Average percentage of cache occupancy
3130system.l2c.tags.occ_percent::cpu0.dtb.walker 0.005268 # Average percentage of cache occupancy
3131system.l2c.tags.occ_percent::cpu0.itb.walker 0.007201 # Average percentage of cache occupancy
3132system.l2c.tags.occ_percent::cpu0.inst 0.068810 # Average percentage of cache occupancy
3133system.l2c.tags.occ_percent::cpu0.data 0.199114 # Average percentage of cache occupancy
3134system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.273933 # Average percentage of cache occupancy
3135system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000807 # Average percentage of cache occupancy
3136system.l2c.tags.occ_percent::cpu1.itb.walker 0.001075 # Average percentage of cache occupancy
3137system.l2c.tags.occ_percent::cpu1.inst 0.040579 # Average percentage of cache occupancy
3138system.l2c.tags.occ_percent::cpu1.data 0.062983 # Average percentage of cache occupancy
3139system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.055484 # Average percentage of cache occupancy
3140system.l2c.tags.occ_percent::total 0.983311 # Average percentage of cache occupancy
3141system.l2c.tags.occ_task_id_blocks::1022 10750 # Occupied blocks per task id
3142system.l2c.tags.occ_task_id_blocks::1023 247 # Occupied blocks per task id
3143system.l2c.tags.occ_task_id_blocks::1024 49659 # Occupied blocks per task id
3144system.l2c.tags.age_task_id_blocks_1022::2 1276 # Occupied blocks per task id
3145system.l2c.tags.age_task_id_blocks_1022::3 687 # Occupied blocks per task id
3146system.l2c.tags.age_task_id_blocks_1022::4 8787 # Occupied blocks per task id
3147system.l2c.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id
3148system.l2c.tags.age_task_id_blocks_1023::4 238 # Occupied blocks per task id
3149system.l2c.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
3150system.l2c.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id
3151system.l2c.tags.age_task_id_blocks_1024::2 2518 # Occupied blocks per task id
3152system.l2c.tags.age_task_id_blocks_1024::3 4806 # Occupied blocks per task id
3153system.l2c.tags.age_task_id_blocks_1024::4 41987 # Occupied blocks per task id
3154system.l2c.tags.occ_task_id_percent::1022 0.164032 # Percentage of cache occupancy per task id
3155system.l2c.tags.occ_task_id_percent::1023 0.003769 # Percentage of cache occupancy per task id
3156system.l2c.tags.occ_task_id_percent::1024 0.757736 # Percentage of cache occupancy per task id
3157system.l2c.tags.tag_accesses 65067124 # Number of tag accesses
3158system.l2c.tags.data_accesses 65067124 # Number of data accesses
3159system.l2c.ReadReq_hits::cpu0.dtb.walker 6771 # number of ReadReq hits
3160system.l2c.ReadReq_hits::cpu0.itb.walker 4585 # number of ReadReq hits
3161system.l2c.ReadReq_hits::cpu0.inst 583685 # number of ReadReq hits
3162system.l2c.ReadReq_hits::cpu0.data 633203 # number of ReadReq hits
3163system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 298139 # number of ReadReq hits
3164system.l2c.ReadReq_hits::cpu1.dtb.walker 6546 # number of ReadReq hits
3165system.l2c.ReadReq_hits::cpu1.itb.walker 4209 # number of ReadReq hits
3166system.l2c.ReadReq_hits::cpu1.inst 589652 # number of ReadReq hits
3167system.l2c.ReadReq_hits::cpu1.data 570600 # number of ReadReq hits
3168system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 281047 # number of ReadReq hits
3169system.l2c.ReadReq_hits::total 2978437 # number of ReadReq hits
3170system.l2c.Writeback_hits::writebacks 2596817 # number of Writeback hits
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3250system.l2c.overall_misses::total 1122927 # number of overall misses
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3261system.l2c.ReadReq_miss_latency::total 123646486742 # number of ReadReq miss cycles
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3263system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 39165941 # number of WriteInvalidateReq miss cycles
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3266system.l2c.UpgradeReq_miss_latency::cpu1.data 263365265 # number of UpgradeReq miss cycles
3267system.l2c.UpgradeReq_miss_latency::total 571564616 # number of UpgradeReq miss cycles
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3284system.l2c.demand_miss_latency::total 136812680803 # number of demand (read+write) miss cycles
3285system.l2c.overall_miss_latency::cpu0.dtb.walker 244393039 # number of overall miss cycles
3286system.l2c.overall_miss_latency::cpu0.itb.walker 217850761 # number of overall miss cycles
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3295system.l2c.overall_miss_latency::total 136812680803 # number of overall miss cycles
3296system.l2c.ReadReq_accesses::cpu0.dtb.walker 9394 # number of ReadReq accesses(hits+misses)
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3306system.l2c.ReadReq_accesses::total 3959659 # number of ReadReq accesses(hits+misses)
3307system.l2c.Writeback_accesses::writebacks 2596817 # number of Writeback accesses(hits+misses)
3308system.l2c.Writeback_accesses::total 2596817 # number of Writeback accesses(hits+misses)
3309system.l2c.WriteInvalidateReq_accesses::cpu0.data 582852 # number of WriteInvalidateReq accesses(hits+misses)
3310system.l2c.WriteInvalidateReq_accesses::cpu1.data 269705 # number of WriteInvalidateReq accesses(hits+misses)
3311system.l2c.WriteInvalidateReq_accesses::total 852557 # number of WriteInvalidateReq accesses(hits+misses)
3312system.l2c.UpgradeReq_accesses::cpu0.data 82467 # number of UpgradeReq accesses(hits+misses)
3313system.l2c.UpgradeReq_accesses::cpu1.data 72695 # number of UpgradeReq accesses(hits+misses)
3314system.l2c.UpgradeReq_accesses::total 155162 # number of UpgradeReq accesses(hits+misses)
3315system.l2c.SCUpgradeReq_accesses::cpu0.data 15292 # number of SCUpgradeReq accesses(hits+misses)
3316system.l2c.SCUpgradeReq_accesses::cpu1.data 15623 # number of SCUpgradeReq accesses(hits+misses)
3317system.l2c.SCUpgradeReq_accesses::total 30915 # number of SCUpgradeReq accesses(hits+misses)
3318system.l2c.ReadExReq_accesses::cpu0.data 138632 # number of ReadExReq accesses(hits+misses)
3319system.l2c.ReadExReq_accesses::cpu1.data 108101 # number of ReadExReq accesses(hits+misses)
3320system.l2c.ReadExReq_accesses::total 246733 # number of ReadExReq accesses(hits+misses)
3321system.l2c.demand_accesses::cpu0.dtb.walker 9394 # number of demand (read+write) accesses
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3330system.l2c.demand_accesses::cpu1.l2cache.prefetcher 549947 # number of demand (read+write) accesses
3331system.l2c.demand_accesses::total 4206392 # number of demand (read+write) accesses
3332system.l2c.overall_accesses::cpu0.dtb.walker 9394 # number of overall (read+write) accesses
3333system.l2c.overall_accesses::cpu0.itb.walker 6908 # number of overall (read+write) accesses
3334system.l2c.overall_accesses::cpu0.inst 649063 # number of overall (read+write) accesses
3335system.l2c.overall_accesses::cpu0.data 932550 # number of overall (read+write) accesses
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3337system.l2c.overall_accesses::cpu1.dtb.walker 9225 # number of overall (read+write) accesses
3338system.l2c.overall_accesses::cpu1.itb.walker 6775 # number of overall (read+write) accesses
3339system.l2c.overall_accesses::cpu1.inst 638214 # number of overall (read+write) accesses
3340system.l2c.overall_accesses::cpu1.data 811176 # number of overall (read+write) accesses
3341system.l2c.overall_accesses::cpu1.l2cache.prefetcher 549947 # number of overall (read+write) accesses
3342system.l2c.overall_accesses::total 4206392 # number of overall (read+write) accesses
3343system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.279221 # miss rate for ReadReq accesses
3344system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.336277 # miss rate for ReadReq accesses
3345system.l2c.ReadReq_miss_rate::cpu0.inst 0.100727 # miss rate for ReadReq accesses
3346system.l2c.ReadReq_miss_rate::cpu0.data 0.202433 # miss rate for ReadReq accesses
3347system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.497355 # miss rate for ReadReq accesses
3348system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.290407 # miss rate for ReadReq accesses
3349system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.378745 # miss rate for ReadReq accesses
3350system.l2c.ReadReq_miss_rate::cpu1.inst 0.076090 # miss rate for ReadReq accesses
3351system.l2c.ReadReq_miss_rate::cpu1.data 0.188422 # miss rate for ReadReq accesses
3352system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.488956 # miss rate for ReadReq accesses
3353system.l2c.ReadReq_miss_rate::total 0.247805 # miss rate for ReadReq accesses
3354system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.762804 # miss rate for WriteInvalidateReq accesses
3355system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.515411 # miss rate for WriteInvalidateReq accesses
3356system.l2c.WriteInvalidateReq_miss_rate::total 0.684542 # miss rate for WriteInvalidateReq accesses
3357system.l2c.UpgradeReq_miss_rate::cpu0.data 0.584949 # miss rate for UpgradeReq accesses
3358system.l2c.UpgradeReq_miss_rate::cpu1.data 0.642273 # miss rate for UpgradeReq accesses
3359system.l2c.UpgradeReq_miss_rate::total 0.611806 # miss rate for UpgradeReq accesses
3360system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.599268 # miss rate for SCUpgradeReq accesses
3361system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.607950 # miss rate for SCUpgradeReq accesses
3362system.l2c.SCUpgradeReq_miss_rate::total 0.603655 # miss rate for SCUpgradeReq accesses
3363system.l2c.ReadExReq_miss_rate::cpu0.data 0.602949 # miss rate for ReadExReq accesses
3364system.l2c.ReadExReq_miss_rate::cpu1.data 0.537618 # miss rate for ReadExReq accesses
3365system.l2c.ReadExReq_miss_rate::total 0.574325 # miss rate for ReadExReq accesses
3366system.l2c.demand_miss_rate::cpu0.dtb.walker 0.279221 # miss rate for demand accesses
3367system.l2c.demand_miss_rate::cpu0.itb.walker 0.336277 # miss rate for demand accesses
3368system.l2c.demand_miss_rate::cpu0.inst 0.100727 # miss rate for demand accesses
3369system.l2c.demand_miss_rate::cpu0.data 0.261973 # miss rate for demand accesses
3370system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.497355 # miss rate for demand accesses
3371system.l2c.demand_miss_rate::cpu1.dtb.walker 0.290407 # miss rate for demand accesses
3372system.l2c.demand_miss_rate::cpu1.itb.walker 0.378745 # miss rate for demand accesses
3373system.l2c.demand_miss_rate::cpu1.inst 0.076090 # miss rate for demand accesses
3374system.l2c.demand_miss_rate::cpu1.data 0.234958 # miss rate for demand accesses
3375system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.488956 # miss rate for demand accesses
3376system.l2c.demand_miss_rate::total 0.266957 # miss rate for demand accesses
3377system.l2c.overall_miss_rate::cpu0.dtb.walker 0.279221 # miss rate for overall accesses
3378system.l2c.overall_miss_rate::cpu0.itb.walker 0.336277 # miss rate for overall accesses
3379system.l2c.overall_miss_rate::cpu0.inst 0.100727 # miss rate for overall accesses
3380system.l2c.overall_miss_rate::cpu0.data 0.261973 # miss rate for overall accesses
3381system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.497355 # miss rate for overall accesses
3382system.l2c.overall_miss_rate::cpu1.dtb.walker 0.290407 # miss rate for overall accesses
3383system.l2c.overall_miss_rate::cpu1.itb.walker 0.378745 # miss rate for overall accesses
3384system.l2c.overall_miss_rate::cpu1.inst 0.076090 # miss rate for overall accesses
3385system.l2c.overall_miss_rate::cpu1.data 0.234958 # miss rate for overall accesses
3386system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.488956 # miss rate for overall accesses
3387system.l2c.overall_miss_rate::total 0.266957 # miss rate for overall accesses
3388system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 93173.099123 # average ReadReq miss latency
3389system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 93779.922944 # average ReadReq miss latency
3390system.l2c.ReadReq_avg_miss_latency::cpu0.inst 87284.875019 # average ReadReq miss latency
3391system.l2c.ReadReq_avg_miss_latency::cpu0.data 99642.307034 # average ReadReq miss latency
3392system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 148249.247701 # average ReadReq miss latency
3393system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 92986.673012 # average ReadReq miss latency
3394system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 93177.619641 # average ReadReq miss latency
3395system.l2c.ReadReq_avg_miss_latency::cpu1.inst 87625.214901 # average ReadReq miss latency
3396system.l2c.ReadReq_avg_miss_latency::cpu1.data 99229.690953 # average ReadReq miss latency
3397system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 148163.364161 # average ReadReq miss latency
3398system.l2c.ReadReq_avg_miss_latency::total 126012.754241 # average ReadReq miss latency
3399system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 116.953307 # average WriteInvalidateReq miss latency
3400system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 281.751117 # average WriteInvalidateReq miss latency
3401system.l2c.WriteInvalidateReq_avg_miss_latency::total 156.206129 # average WriteInvalidateReq miss latency
3402system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6389.007877 # average UpgradeReq miss latency
3403system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5640.721032 # average UpgradeReq miss latency
3404system.l2c.UpgradeReq_avg_miss_latency::total 6020.969525 # average UpgradeReq miss latency
3405system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5140.168485 # average SCUpgradeReq miss latency
3406system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5729.445883 # average SCUpgradeReq miss latency
3407system.l2c.SCUpgradeReq_avg_miss_latency::total 5440.080431 # average SCUpgradeReq miss latency
3408system.l2c.ReadExReq_avg_miss_latency::cpu0.data 92860.842585 # average ReadExReq miss latency
3409system.l2c.ReadExReq_avg_miss_latency::cpu1.data 92987.283428 # average ReadExReq miss latency
3410system.l2c.ReadExReq_avg_miss_latency::total 92912.699347 # average ReadExReq miss latency
3411system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 93173.099123 # average overall miss latency
3412system.l2c.demand_avg_miss_latency::cpu0.itb.walker 93779.922944 # average overall miss latency
3413system.l2c.demand_avg_miss_latency::cpu0.inst 87284.875019 # average overall miss latency
3414system.l2c.demand_avg_miss_latency::cpu0.data 97322.036508 # average overall miss latency
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3416system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 92986.673012 # average overall miss latency
3417system.l2c.demand_avg_miss_latency::cpu1.itb.walker 93177.619641 # average overall miss latency
3418system.l2c.demand_avg_miss_latency::cpu1.inst 87625.214901 # average overall miss latency
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3420system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 148163.364161 # average overall miss latency
3421system.l2c.demand_avg_miss_latency::total 121835.774545 # average overall miss latency
3422system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 93173.099123 # average overall miss latency
3423system.l2c.overall_avg_miss_latency::cpu0.itb.walker 93779.922944 # average overall miss latency
3424system.l2c.overall_avg_miss_latency::cpu0.inst 87284.875019 # average overall miss latency
3425system.l2c.overall_avg_miss_latency::cpu0.data 97322.036508 # average overall miss latency
3426system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 148249.247701 # average overall miss latency
3427system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 92986.673012 # average overall miss latency
3428system.l2c.overall_avg_miss_latency::cpu1.itb.walker 93177.619641 # average overall miss latency
3429system.l2c.overall_avg_miss_latency::cpu1.inst 87625.214901 # average overall miss latency
3430system.l2c.overall_avg_miss_latency::cpu1.data 97326.200785 # average overall miss latency
3431system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 148163.364161 # average overall miss latency
3432system.l2c.overall_avg_miss_latency::total 121835.774545 # average overall miss latency
3433system.l2c.blocked_cycles::no_mshrs 14255 # number of cycles access was blocked
3434system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
3435system.l2c.blocked::no_mshrs 149 # number of cycles access was blocked
3436system.l2c.blocked::no_targets 0 # number of cycles access was blocked
3437system.l2c.avg_blocked_cycles::no_mshrs 95.671141 # average number of cycles each access was blocked
3438system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
3439system.l2c.fast_writes 0 # number of fast writes performed
3440system.l2c.cache_copies 0 # number of cache copies performed
3441system.l2c.writebacks::writebacks 1263454 # number of writebacks
3442system.l2c.writebacks::total 1263454 # number of writebacks
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3444system.l2c.ReadReq_mshr_hits::cpu0.data 55 # number of ReadReq MSHR hits
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3446system.l2c.ReadReq_mshr_hits::cpu1.data 31 # number of ReadReq MSHR hits
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3451system.l2c.demand_mshr_hits::cpu0.data 56 # number of demand (read+write) MSHR hits
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3458system.l2c.overall_mshr_hits::cpu1.data 31 # number of overall MSHR hits
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3472system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 139009 # number of WriteInvalidateReq MSHR misses
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3506system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31767 # number of ReadReq MSHR uncacheable
3507system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable
3508system.l2c.ReadReq_mshr_uncacheable::cpu1.data 7124 # number of ReadReq MSHR uncacheable
3509system.l2c.ReadReq_mshr_uncacheable::total 60252 # number of ReadReq MSHR uncacheable
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3511system.l2c.WriteReq_mshr_uncacheable::cpu1.data 7600 # number of WriteReq MSHR uncacheable
3512system.l2c.WriteReq_mshr_uncacheable::total 38779 # number of WriteReq MSHR uncacheable
3513system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses
3514system.l2c.overall_mshr_uncacheable_misses::cpu0.data 62946 # number of overall MSHR uncacheable misses
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3528system.l2c.ReadReq_mshr_miss_latency::total 111471516028 # number of ReadReq MSHR miss cycles
3529system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 17621248292 # number of WriteInvalidateReq MSHR miss cycles
3530system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 4582826059 # number of WriteInvalidateReq MSHR miss cycles
3531system.l2c.WriteInvalidateReq_mshr_miss_latency::total 22204074351 # number of WriteInvalidateReq MSHR miss cycles
3532system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 860739549 # number of UpgradeReq MSHR miss cycles
3533system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 832018870 # number of UpgradeReq MSHR miss cycles
3534system.l2c.UpgradeReq_mshr_miss_latency::total 1692758419 # number of UpgradeReq MSHR miss cycles
3535system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 163139115 # number of SCUpgradeReq MSHR miss cycles
3536system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 169125946 # number of SCUpgradeReq MSHR miss cycles
3537system.l2c.SCUpgradeReq_mshr_miss_latency::total 332265061 # number of SCUpgradeReq MSHR miss cycles
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3542system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 188610731 # number of demand (read+write) MSHR miss cycles
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3546system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 215342695 # number of demand (read+write) MSHR miss cycles
3547system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 206771700 # number of demand (read+write) MSHR miss cycles
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3551system.l2c.demand_mshr_miss_latency::total 122874175691 # number of demand (read+write) MSHR miss cycles
3552system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 211330935 # number of overall MSHR miss cycles
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3557system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 215342695 # number of overall MSHR miss cycles
3558system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 206771700 # number of overall MSHR miss cycles
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3563system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1285623000 # number of ReadReq MSHR uncacheable cycles
3564system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4741851751 # number of ReadReq MSHR uncacheable cycles
3565system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4289000 # number of ReadReq MSHR uncacheable cycles
3566system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 634532000 # number of ReadReq MSHR uncacheable cycles
3567system.l2c.ReadReq_mshr_uncacheable_latency::total 6666295751 # number of ReadReq MSHR uncacheable cycles
3568system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4487720539 # number of WriteReq MSHR uncacheable cycles
3569system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 797339000 # number of WriteReq MSHR uncacheable cycles
3570system.l2c.WriteReq_mshr_uncacheable_latency::total 5285059539 # number of WriteReq MSHR uncacheable cycles
3571system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1285623000 # number of overall MSHR uncacheable cycles
3572system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9229572290 # number of overall MSHR uncacheable cycles
3573system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4289000 # number of overall MSHR uncacheable cycles
3574system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1431871000 # number of overall MSHR uncacheable cycles
3575system.l2c.overall_mshr_uncacheable_latency::total 11951355290 # number of overall MSHR uncacheable cycles
3576system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.279221 # mshr miss rate for ReadReq accesses
3577system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.336277 # mshr miss rate for ReadReq accesses
3578system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.100365 # mshr miss rate for ReadReq accesses
3579system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.202363 # mshr miss rate for ReadReq accesses
3580system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.497355 # mshr miss rate for ReadReq accesses
3581system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.290407 # mshr miss rate for ReadReq accesses
3582system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.378745 # mshr miss rate for ReadReq accesses
3583system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.075700 # mshr miss rate for ReadReq accesses
3584system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.188378 # mshr miss rate for ReadReq accesses
3585system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.488956 # mshr miss rate for ReadReq accesses
3586system.l2c.ReadReq_mshr_miss_rate::total 0.247661 # mshr miss rate for ReadReq accesses
3587system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.762804 # mshr miss rate for WriteInvalidateReq accesses
3588system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.515411 # mshr miss rate for WriteInvalidateReq accesses
3589system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.684542 # mshr miss rate for WriteInvalidateReq accesses
3590system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.584949 # mshr miss rate for UpgradeReq accesses
3591system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.642273 # mshr miss rate for UpgradeReq accesses
3592system.l2c.UpgradeReq_mshr_miss_rate::total 0.611806 # mshr miss rate for UpgradeReq accesses
3593system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.599268 # mshr miss rate for SCUpgradeReq accesses
3594system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.607950 # mshr miss rate for SCUpgradeReq accesses
3595system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.603655 # mshr miss rate for SCUpgradeReq accesses
3596system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.602942 # mshr miss rate for ReadExReq accesses
3597system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.537618 # mshr miss rate for ReadExReq accesses
3598system.l2c.ReadExReq_mshr_miss_rate::total 0.574321 # mshr miss rate for ReadExReq accesses
3599system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.279221 # mshr miss rate for demand accesses
3600system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.336277 # mshr miss rate for demand accesses
3601system.l2c.demand_mshr_miss_rate::cpu0.inst 0.100365 # mshr miss rate for demand accesses
3602system.l2c.demand_mshr_miss_rate::cpu0.data 0.261913 # mshr miss rate for demand accesses
3603system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.497355 # mshr miss rate for demand accesses
3604system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.290407 # mshr miss rate for demand accesses
3605system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.378745 # mshr miss rate for demand accesses
3606system.l2c.demand_mshr_miss_rate::cpu1.inst 0.075700 # mshr miss rate for demand accesses
3607system.l2c.demand_mshr_miss_rate::cpu1.data 0.234919 # mshr miss rate for demand accesses
3608system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.488956 # mshr miss rate for demand accesses
3609system.l2c.demand_mshr_miss_rate::total 0.266822 # mshr miss rate for demand accesses
3610system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.279221 # mshr miss rate for overall accesses
3611system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.336277 # mshr miss rate for overall accesses
3612system.l2c.overall_mshr_miss_rate::cpu0.inst 0.100365 # mshr miss rate for overall accesses
3613system.l2c.overall_mshr_miss_rate::cpu0.data 0.261913 # mshr miss rate for overall accesses
3614system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.497355 # mshr miss rate for overall accesses
3615system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.290407 # mshr miss rate for overall accesses
3616system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.378745 # mshr miss rate for overall accesses
3617system.l2c.overall_mshr_miss_rate::cpu1.inst 0.075700 # mshr miss rate for overall accesses
3618system.l2c.overall_mshr_miss_rate::cpu1.data 0.234919 # mshr miss rate for overall accesses
3619system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.488956 # mshr miss rate for overall accesses
3620system.l2c.overall_mshr_miss_rate::total 0.266822 # mshr miss rate for overall accesses
3621system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 80568.408311 # average ReadReq mshr miss latency
3622system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 81192.738269 # average ReadReq mshr miss latency
3623system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74769.755661 # average ReadReq mshr miss latency
3624system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 87169.627673 # average ReadReq mshr miss latency
3625system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135981.037396 # average ReadReq mshr miss latency
3626system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 80381.745054 # average ReadReq mshr miss latency
3627system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 80581.332814 # average ReadReq mshr miss latency
3628system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75142.970070 # average ReadReq mshr miss latency
3629system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 86751.636095 # average ReadReq mshr miss latency
3630system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135884.728059 # average ReadReq mshr miss latency
3631system.l2c.ReadReq_avg_mshr_miss_latency::total 113670.819035 # average ReadReq mshr miss latency
3632system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39633.758490 # average WriteInvalidateReq mshr miss latency
3633system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32967.837039 # average WriteInvalidateReq mshr miss latency
3634system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 38046.017555 # average WriteInvalidateReq mshr miss latency
3635system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17843.229524 # average UpgradeReq mshr miss latency
3636system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17820.065753 # average UpgradeReq mshr miss latency
3637system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17831.836625 # average UpgradeReq mshr miss latency
3638system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17802.173178 # average SCUpgradeReq mshr miss latency
3639system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17806.479891 # average SCUpgradeReq mshr miss latency
3640system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17804.365073 # average SCUpgradeReq mshr miss latency
3641system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80406.356563 # average ReadExReq mshr miss latency
3642system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 80557.040745 # average ReadExReq mshr miss latency
3643system.l2c.ReadExReq_avg_mshr_miss_latency::total 80468.156601 # average ReadExReq mshr miss latency
3644system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80568.408311 # average overall mshr miss latency
3645system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 81192.738269 # average overall mshr miss latency
3646system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74769.755661 # average overall mshr miss latency
3647system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84855.079113 # average overall mshr miss latency
3648system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135981.037396 # average overall mshr miss latency
3649system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80381.745054 # average overall mshr miss latency
3650system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 80581.332814 # average overall mshr miss latency
3651system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75142.970070 # average overall mshr miss latency
3652system.l2c.demand_avg_mshr_miss_latency::cpu1.data 84862.417955 # average overall mshr miss latency
3653system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135884.728059 # average overall mshr miss latency
3654system.l2c.demand_avg_mshr_miss_latency::total 109478.788986 # average overall mshr miss latency
3655system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80568.408311 # average overall mshr miss latency
3656system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 81192.738269 # average overall mshr miss latency
3657system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74769.755661 # average overall mshr miss latency
3658system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84855.079113 # average overall mshr miss latency
3659system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135981.037396 # average overall mshr miss latency
3660system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80381.745054 # average overall mshr miss latency
3661system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 80581.332814 # average overall mshr miss latency
3662system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75142.970070 # average overall mshr miss latency
3663system.l2c.overall_avg_mshr_miss_latency::cpu1.data 84862.417955 # average overall mshr miss latency
3664system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135884.728059 # average overall mshr miss latency
3665system.l2c.overall_avg_mshr_miss_latency::total 109478.788986 # average overall mshr miss latency
3666system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60374.894336 # average ReadReq mshr uncacheable latency
3667system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 149269.737495 # average ReadReq mshr uncacheable latency
3668system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64014.925373 # average ReadReq mshr uncacheable latency
3669system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 89069.623807 # average ReadReq mshr uncacheable latency
3670system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 110640.240175 # average ReadReq mshr uncacheable latency
3671system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 143934.075467 # average WriteReq mshr uncacheable latency
3672system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 104913.026316 # average WriteReq mshr uncacheable latency
3673system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 136286.638103 # average WriteReq mshr uncacheable latency
3674system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60374.894336 # average overall mshr uncacheable latency
3675system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 146626.827598 # average overall mshr uncacheable latency
3676system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64014.925373 # average overall mshr uncacheable latency
3677system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 97247.419180 # average overall mshr uncacheable latency
3678system.l2c.overall_avg_mshr_uncacheable_latency::total 120682.970888 # average overall mshr uncacheable latency
3679system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
3680system.membus.trans_dist::ReadReq 1049844 # Transaction distribution
3681system.membus.trans_dist::ReadResp 1049844 # Transaction distribution
3682system.membus.trans_dist::WriteReq 38779 # Transaction distribution
3683system.membus.trans_dist::WriteResp 38779 # Transaction distribution
3684system.membus.trans_dist::Writeback 1370148 # Transaction distribution
3685system.membus.trans_dist::WriteInvalidateReq 687460 # Transaction distribution
3686system.membus.trans_dist::WriteInvalidateResp 687460 # Transaction distribution
3687system.membus.trans_dist::UpgradeReq 443336 # Transaction distribution
3688system.membus.trans_dist::SCUpgradeReq 306800 # Transaction distribution
3689system.membus.trans_dist::UpgradeResp 120479 # Transaction distribution
3690system.membus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution
3691system.membus.trans_dist::ReadExReq 155568 # Transaction distribution
3692system.membus.trans_dist::ReadExResp 137698 # Transaction distribution
3693system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122614 # Packet count per connected master and slave (bytes)
3694system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes)
3695system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27506 # Packet count per connected master and slave (bytes)
3696system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5597252 # Packet count per connected master and slave (bytes)
3697system.membus.pkt_count_system.l2c.mem_side::total 5747450 # Packet count per connected master and slave (bytes)
3698system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335773 # Packet count per connected master and slave (bytes)
3699system.membus.pkt_count_system.iocache.mem_side::total 335773 # Packet count per connected master and slave (bytes)
3700system.membus.pkt_count::total 6083223 # Packet count per connected master and slave (bytes)
3701system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155744 # Cumulative packet size per connected master and slave (bytes)
3702system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes)
3703system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55012 # Cumulative packet size per connected master and slave (bytes)
3704system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 189917440 # Cumulative packet size per connected master and slave (bytes)
3705system.membus.pkt_size_system.l2c.mem_side::total 190128768 # Cumulative packet size per connected master and slave (bytes)
3706system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14086528 # Cumulative packet size per connected master and slave (bytes)
3707system.membus.pkt_size_system.iocache.mem_side::total 14086528 # Cumulative packet size per connected master and slave (bytes)
3708system.membus.pkt_size::total 204215296 # Cumulative packet size per connected master and slave (bytes)
3709system.membus.snoops 650589 # Total snoops (count)
3710system.membus.snoop_fanout::samples 4133180 # Request fanout histogram
3711system.membus.snoop_fanout::mean 1 # Request fanout histogram
3712system.membus.snoop_fanout::stdev 0 # Request fanout histogram
3713system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3714system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3715system.membus.snoop_fanout::1 4133180 100.00% 100.00% # Request fanout histogram
3716system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
3717system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3718system.membus.snoop_fanout::min_value 1 # Request fanout histogram
3719system.membus.snoop_fanout::max_value 1 # Request fanout histogram
3720system.membus.snoop_fanout::total 4133180 # Request fanout histogram
3721system.membus.reqLayer0.occupancy 98178497 # Layer occupancy (ticks)
3722system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
3723system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks)
3724system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
3725system.membus.reqLayer2.occupancy 22861986 # Layer occupancy (ticks)
3726system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
3727system.membus.reqLayer5.occupancy 12090027529 # Layer occupancy (ticks)
3728system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
3729system.membus.respLayer2.occupancy 6852398799 # Layer occupancy (ticks)
3730system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
3731system.membus.respLayer3.occupancy 152088673 # Layer occupancy (ticks)
3732system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
3733system.realview.ethernet.txBytes 966 # Bytes Transmitted
3734system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
3735system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
3736system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
3737system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
3738system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
3739system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA

--- 27 unchanged lines hidden (view full) ---

3767system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
3768system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
3769system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
3770system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
3771system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
3772system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
3773system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
3774system.realview.ethernet.droppedPackets 0 # number of packets dropped
3775system.toL2Bus.trans_dist::ReadReq 4896771 # Transaction distribution
3776system.toL2Bus.trans_dist::ReadResp 4889534 # Transaction distribution
3777system.toL2Bus.trans_dist::WriteReq 38779 # Transaction distribution
3778system.toL2Bus.trans_dist::WriteResp 38779 # Transaction distribution
3779system.toL2Bus.trans_dist::Writeback 2596817 # Transaction distribution
3780system.toL2Bus.trans_dist::WriteInvalidateReq 959438 # Transaction distribution
3781system.toL2Bus.trans_dist::WriteInvalidateResp 852557 # Transaction distribution
3782system.toL2Bus.trans_dist::UpgradeReq 496684 # Transaction distribution
3783system.toL2Bus.trans_dist::SCUpgradeReq 319053 # Transaction distribution
3784system.toL2Bus.trans_dist::UpgradeResp 815737 # Transaction distribution
3785system.toL2Bus.trans_dist::SCUpgradeFailReq 143 # Transaction distribution
3786system.toL2Bus.trans_dist::UpgradeFailResp 143 # Transaction distribution
3787system.toL2Bus.trans_dist::ReadExReq 305200 # Transaction distribution
3788system.toL2Bus.trans_dist::ReadExResp 305200 # Transaction distribution
3789system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8223954 # Packet count per connected master and slave (bytes)
3790system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6618870 # Packet count per connected master and slave (bytes)
3791system.toL2Bus.pkt_count::total 14842824 # Packet count per connected master and slave (bytes)
3792system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 276507544 # Cumulative packet size per connected master and slave (bytes)
3793system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 214143912 # Cumulative packet size per connected master and slave (bytes)
3794system.toL2Bus.pkt_size::total 490651456 # Cumulative packet size per connected master and slave (bytes)
3795system.toL2Bus.snoops 1673717 # Total snoops (count)
3796system.toL2Bus.snoop_fanout::samples 9649223 # Request fanout histogram
3797system.toL2Bus.snoop_fanout::mean 1.012003 # Request fanout histogram
3798system.toL2Bus.snoop_fanout::stdev 0.108901 # Request fanout histogram
3799system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
3800system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
3801system.toL2Bus.snoop_fanout::1 9533399 98.80% 98.80% # Request fanout histogram
3802system.toL2Bus.snoop_fanout::2 115824 1.20% 100.00% # Request fanout histogram
3803system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
3804system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
3805system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
3806system.toL2Bus.snoop_fanout::total 9649223 # Request fanout histogram
3807system.toL2Bus.reqLayer0.occupancy 8593373447 # Layer occupancy (ticks)
3808system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
3809system.toL2Bus.snoopLayer0.occupancy 2556000 # Layer occupancy (ticks)
3810system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
3811system.toL2Bus.respLayer0.occupancy 4622045284 # Layer occupancy (ticks)
3812system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
3813system.toL2Bus.respLayer1.occupancy 4138277748 # Layer occupancy (ticks)
3814system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
3815system.cpu0.kern.inst.arm 0 # number of arm instructions executed
3816system.cpu0.kern.inst.quiesce 13964 # number of quiesce instructions executed
3817system.cpu1.kern.inst.arm 0 # number of arm instructions executed
3818system.cpu1.kern.inst.quiesce 5482 # number of quiesce instructions executed
3819
3820---------- End Simulation Statistics ----------