| config.ini (11589:af2f7fef4875) | config.ini (11680:b4d943429dc6) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 22 unchanged lines hidden (view full) --- 31highest_el_is_64=false 32init_param=0 33kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 34kernel_addr_check=true 35load_addr_mask=268435455 36load_offset=2147483648 37machine_type=VExpress_EMM64 38mem_mode=timing | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=true 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 22 unchanged lines hidden (view full) --- 31highest_el_is_64=false 32init_param=0 33kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch64.20140821 34kernel_addr_check=true 35load_addr_mask=268435455 36load_offset=2147483648 37machine_type=VExpress_EMM64 38mem_mode=timing |
| 39mem_ranges=2147483648:2415919103 | 39mem_ranges=2147483648:2415919103:0:0:0:0 |
| 40memories=system.physmem system.realview.nvmem system.realview.vram 41mmap_using_noreserve=false 42multi_proc=true 43multi_thread=false 44num_work_ids=16 45p_state_clk_gate_bins=20 46p_state_clk_gate_max=1000000000000 47p_state_clk_gate_min=1000 --- 20 unchanged lines hidden (view full) --- 68clk_domain=system.clk_domain 69default_p_state=UNDEFINED 70delay=50000 71eventq_index=0 72p_state_clk_gate_bins=20 73p_state_clk_gate_max=1000000000000 74p_state_clk_gate_min=1000 75power_model=Null | 40memories=system.physmem system.realview.nvmem system.realview.vram 41mmap_using_noreserve=false 42multi_proc=true 43multi_thread=false 44num_work_ids=16 45p_state_clk_gate_bins=20 46p_state_clk_gate_max=1000000000000 47p_state_clk_gate_min=1000 --- 20 unchanged lines hidden (view full) --- 68clk_domain=system.clk_domain 69default_p_state=UNDEFINED 70delay=50000 71eventq_index=0 72p_state_clk_gate_bins=20 73p_state_clk_gate_max=1000000000000 74p_state_clk_gate_min=1000 75power_model=Null |
| 76ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 | 76ranges=788529152:805306367:0:0:0:0 721420288:725614591:0:0:0:0 805306368:1073741823:0:0:0:0 1073741824:1610612735:0:0:0:0 402653184:469762047:0:0:0:0 469762048:536870911:0:0:0:0 |
| 77req_size=16 78resp_size=16 79master=system.iobus.slave[0] 80slave=system.membus.master[0] 81 82[system.cf0] 83type=IdeDisk 84children=image --- 139 unchanged lines hidden (view full) --- 224indirectWays=2 225instShiftAmt=2 226numThreads=1 227useIndirect=true 228 229[system.cpu0.dcache] 230type=Cache 231children=tags | 77req_size=16 78resp_size=16 79master=system.iobus.slave[0] 80slave=system.membus.master[0] 81 82[system.cf0] 83type=IdeDisk 84children=image --- 139 unchanged lines hidden (view full) --- 224indirectWays=2 225instShiftAmt=2 226numThreads=1 227useIndirect=true 228 229[system.cpu0.dcache] 230type=Cache 231children=tags |
| 232addr_ranges=0:18446744073709551615 | 232addr_ranges=0:18446744073709551615:0:0:0:0 |
| 233assoc=2 234clk_domain=system.cpu_clk_domain 235clusivity=mostly_incl 236default_p_state=UNDEFINED 237demand_mshr_reserve=1 238eventq_index=0 239hit_latency=2 240is_read_only=false --- 345 unchanged lines hidden (view full) --- 586eventq_index=0 587opClass=FloatMult 588opLat=4 589pipelined=true 590 591[system.cpu0.icache] 592type=Cache 593children=tags | 233assoc=2 234clk_domain=system.cpu_clk_domain 235clusivity=mostly_incl 236default_p_state=UNDEFINED 237demand_mshr_reserve=1 238eventq_index=0 239hit_latency=2 240is_read_only=false --- 345 unchanged lines hidden (view full) --- 586eventq_index=0 587opClass=FloatMult 588opLat=4 589pipelined=true 590 591[system.cpu0.icache] 592type=Cache 593children=tags |
| 594addr_ranges=0:18446744073709551615 | 594addr_ranges=0:18446744073709551615:0:0:0:0 |
| 595assoc=2 596clk_domain=system.cpu_clk_domain 597clusivity=mostly_incl 598default_p_state=UNDEFINED 599demand_mshr_reserve=1 600eventq_index=0 601hit_latency=1 602is_read_only=true --- 115 unchanged lines hidden (view full) --- 718p_state_clk_gate_min=1000 719power_model=Null 720sys=system 721port=system.cpu0.toL2Bus.slave[2] 722 723[system.cpu0.l2cache] 724type=Cache 725children=prefetcher tags | 595assoc=2 596clk_domain=system.cpu_clk_domain 597clusivity=mostly_incl 598default_p_state=UNDEFINED 599demand_mshr_reserve=1 600eventq_index=0 601hit_latency=1 602is_read_only=true --- 115 unchanged lines hidden (view full) --- 718p_state_clk_gate_min=1000 719power_model=Null 720sys=system 721port=system.cpu0.toL2Bus.slave[2] 722 723[system.cpu0.l2cache] 724type=Cache 725children=prefetcher tags |
| 726addr_ranges=0:18446744073709551615 | 726addr_ranges=0:18446744073709551615:0:0:0:0 |
| 727assoc=16 728clk_domain=system.cpu_clk_domain 729clusivity=mostly_excl 730default_p_state=UNDEFINED 731demand_mshr_reserve=1 732eventq_index=0 733hit_latency=12 734is_read_only=false --- 208 unchanged lines hidden (view full) --- 943indirectWays=2 944instShiftAmt=2 945numThreads=1 946useIndirect=true 947 948[system.cpu1.dcache] 949type=Cache 950children=tags | 727assoc=16 728clk_domain=system.cpu_clk_domain 729clusivity=mostly_excl 730default_p_state=UNDEFINED 731demand_mshr_reserve=1 732eventq_index=0 733hit_latency=12 734is_read_only=false --- 208 unchanged lines hidden (view full) --- 943indirectWays=2 944instShiftAmt=2 945numThreads=1 946useIndirect=true 947 948[system.cpu1.dcache] 949type=Cache 950children=tags |
| 951addr_ranges=0:18446744073709551615 | 951addr_ranges=0:18446744073709551615:0:0:0:0 |
| 952assoc=2 953clk_domain=system.cpu_clk_domain 954clusivity=mostly_incl 955default_p_state=UNDEFINED 956demand_mshr_reserve=1 957eventq_index=0 958hit_latency=2 959is_read_only=false --- 345 unchanged lines hidden (view full) --- 1305eventq_index=0 1306opClass=FloatMult 1307opLat=4 1308pipelined=true 1309 1310[system.cpu1.icache] 1311type=Cache 1312children=tags | 952assoc=2 953clk_domain=system.cpu_clk_domain 954clusivity=mostly_incl 955default_p_state=UNDEFINED 956demand_mshr_reserve=1 957eventq_index=0 958hit_latency=2 959is_read_only=false --- 345 unchanged lines hidden (view full) --- 1305eventq_index=0 1306opClass=FloatMult 1307opLat=4 1308pipelined=true 1309 1310[system.cpu1.icache] 1311type=Cache 1312children=tags |
| 1313addr_ranges=0:18446744073709551615 | 1313addr_ranges=0:18446744073709551615:0:0:0:0 |
| 1314assoc=2 1315clk_domain=system.cpu_clk_domain 1316clusivity=mostly_incl 1317default_p_state=UNDEFINED 1318demand_mshr_reserve=1 1319eventq_index=0 1320hit_latency=1 1321is_read_only=true --- 115 unchanged lines hidden (view full) --- 1437p_state_clk_gate_min=1000 1438power_model=Null 1439sys=system 1440port=system.cpu1.toL2Bus.slave[2] 1441 1442[system.cpu1.l2cache] 1443type=Cache 1444children=prefetcher tags | 1314assoc=2 1315clk_domain=system.cpu_clk_domain 1316clusivity=mostly_incl 1317default_p_state=UNDEFINED 1318demand_mshr_reserve=1 1319eventq_index=0 1320hit_latency=1 1321is_read_only=true --- 115 unchanged lines hidden (view full) --- 1437p_state_clk_gate_min=1000 1438power_model=Null 1439sys=system 1440port=system.cpu1.toL2Bus.slave[2] 1441 1442[system.cpu1.l2cache] 1443type=Cache 1444children=prefetcher tags |
| 1445addr_ranges=0:18446744073709551615 | 1445addr_ranges=0:18446744073709551615:0:0:0:0 |
| 1446assoc=16 1447clk_domain=system.cpu_clk_domain 1448clusivity=mostly_excl 1449default_p_state=UNDEFINED 1450demand_mshr_reserve=1 1451eventq_index=0 1452hit_latency=12 1453is_read_only=false --- 130 unchanged lines hidden (view full) --- 1584use_default_range=false 1585width=16 1586master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side 1587slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma 1588 1589[system.iocache] 1590type=Cache 1591children=tags | 1446assoc=16 1447clk_domain=system.cpu_clk_domain 1448clusivity=mostly_excl 1449default_p_state=UNDEFINED 1450demand_mshr_reserve=1 1451eventq_index=0 1452hit_latency=12 1453is_read_only=false --- 130 unchanged lines hidden (view full) --- 1584use_default_range=false 1585width=16 1586master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side 1587slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma 1588 1589[system.iocache] 1590type=Cache 1591children=tags |
| 1592addr_ranges=2147483648:2415919103 | 1592addr_ranges=2147483648:2415919103:0:0:0:0 |
| 1593assoc=8 1594clk_domain=system.clk_domain 1595clusivity=mostly_incl 1596default_p_state=UNDEFINED 1597demand_mshr_reserve=1 1598eventq_index=0 1599hit_latency=50 1600is_read_only=false --- 29 unchanged lines hidden (view full) --- 1630p_state_clk_gate_min=1000 1631power_model=Null 1632sequential_access=false 1633size=1024 1634 1635[system.l2c] 1636type=Cache 1637children=tags | 1593assoc=8 1594clk_domain=system.clk_domain 1595clusivity=mostly_incl 1596default_p_state=UNDEFINED 1597demand_mshr_reserve=1 1598eventq_index=0 1599hit_latency=50 1600is_read_only=false --- 29 unchanged lines hidden (view full) --- 1630p_state_clk_gate_min=1000 1631power_model=Null 1632sequential_access=false 1633size=1024 1634 1635[system.l2c] 1636type=Cache 1637children=tags |
| 1638addr_ranges=0:18446744073709551615 | 1638addr_ranges=0:18446744073709551615:0:0:0:0 |
| 1639assoc=8 1640clk_domain=system.cpu_clk_domain 1641clusivity=mostly_incl 1642default_p_state=UNDEFINED 1643demand_mshr_reserve=1 1644eventq_index=0 1645hit_latency=20 1646is_read_only=false --- 81 unchanged lines hidden (view full) --- 1728type=SnoopFilter 1729eventq_index=0 1730lookup_latency=1 1731max_capacity=8388608 1732system=system 1733 1734[system.physmem] 1735type=DRAMCtrl | 1639assoc=8 1640clk_domain=system.cpu_clk_domain 1641clusivity=mostly_incl 1642default_p_state=UNDEFINED 1643demand_mshr_reserve=1 1644eventq_index=0 1645hit_latency=20 1646is_read_only=false --- 81 unchanged lines hidden (view full) --- 1728type=SnoopFilter 1729eventq_index=0 1730lookup_latency=1 1731max_capacity=8388608 1732system=system 1733 1734[system.physmem] 1735type=DRAMCtrl |
| 1736IDD0=0.075000 | 1736IDD0=0.055000 |
| 1737IDD02=0.000000 | 1737IDD02=0.000000 |
| 1738IDD2N=0.050000 | 1738IDD2N=0.032000 |
| 1739IDD2N2=0.000000 1740IDD2P0=0.000000 1741IDD2P02=0.000000 | 1739IDD2N2=0.000000 1740IDD2P0=0.000000 1741IDD2P02=0.000000 |
| 1742IDD2P1=0.000000 | 1742IDD2P1=0.032000 |
| 1743IDD2P12=0.000000 | 1743IDD2P12=0.000000 |
| 1744IDD3N=0.057000 | 1744IDD3N=0.038000 |
| 1745IDD3N2=0.000000 1746IDD3P0=0.000000 1747IDD3P02=0.000000 | 1745IDD3N2=0.000000 1746IDD3P0=0.000000 1747IDD3P02=0.000000 |
| 1748IDD3P1=0.000000 | 1748IDD3P1=0.038000 |
| 1749IDD3P12=0.000000 | 1749IDD3P12=0.000000 |
| 1750IDD4R=0.187000 | 1750IDD4R=0.157000 |
| 1751IDD4R2=0.000000 | 1751IDD4R2=0.000000 |
| 1752IDD4W=0.165000 | 1752IDD4W=0.125000 |
| 1753IDD4W2=0.000000 | 1753IDD4W2=0.000000 |
| 1754IDD5=0.220000 | 1754IDD5=0.235000 |
| 1755IDD52=0.000000 | 1755IDD52=0.000000 |
| 1756IDD6=0.000000 | 1756IDD6=0.020000 |
| 1757IDD62=0.000000 1758VDD=1.500000 1759VDD2=0.000000 1760activation_limit=4 1761addr_mapping=RoRaBaCoCh 1762bank_groups_per_rank=0 1763banks_per_rank=8 1764burst_length=8 1765channels=1 1766clk_domain=system.clk_domain 1767conf_table_reported=true 1768default_p_state=UNDEFINED 1769device_bus_width=8 1770device_rowbuffer_size=1024 1771device_size=536870912 1772devices_per_rank=8 1773dll=true 1774eventq_index=0 1775in_addr_map=true | 1757IDD62=0.000000 1758VDD=1.500000 1759VDD2=0.000000 1760activation_limit=4 1761addr_mapping=RoRaBaCoCh 1762bank_groups_per_rank=0 1763banks_per_rank=8 1764burst_length=8 1765channels=1 1766clk_domain=system.clk_domain 1767conf_table_reported=true 1768default_p_state=UNDEFINED 1769device_bus_width=8 1770device_rowbuffer_size=1024 1771device_size=536870912 1772devices_per_rank=8 1773dll=true 1774eventq_index=0 1775in_addr_map=true |
| 1776kvm_map=true |
|
| 1776max_accesses_per_row=16 1777mem_sched_policy=frfcfs 1778min_writes_per_switch=16 1779null=false 1780p_state_clk_gate_bins=20 1781p_state_clk_gate_max=1000000000000 1782p_state_clk_gate_min=1000 1783page_policy=open_adaptive 1784power_model=Null | 1777max_accesses_per_row=16 1778mem_sched_policy=frfcfs 1779min_writes_per_switch=16 1780null=false 1781p_state_clk_gate_bins=20 1782p_state_clk_gate_max=1000000000000 1783p_state_clk_gate_min=1000 1784page_policy=open_adaptive 1785power_model=Null |
| 1785range=2147483648:2415919103 | 1786range=2147483648:2415919103:0:0:0:0 |
| 1786ranks_per_channel=2 1787read_buffer_size=32 1788static_backend_latency=10000 1789static_frontend_latency=10000 1790tBURST=5000 1791tCCD_L=0 1792tCK=1250 1793tCL=13750 --- 5 unchanged lines hidden (view full) --- 1799tRP=13750 1800tRRD=6000 1801tRRD_L=0 1802tRTP=7500 1803tRTW=2500 1804tWR=15000 1805tWTR=7500 1806tXAW=30000 | 1787ranks_per_channel=2 1788read_buffer_size=32 1789static_backend_latency=10000 1790static_frontend_latency=10000 1791tBURST=5000 1792tCCD_L=0 1793tCK=1250 1794tCL=13750 --- 5 unchanged lines hidden (view full) --- 1800tRP=13750 1801tRRD=6000 1802tRRD_L=0 1803tRTP=7500 1804tRTW=2500 1805tWR=15000 1806tWTR=7500 1807tXAW=30000 |
| 1807tXP=0 | 1808tXP=6000 |
| 1808tXPDLL=0 | 1809tXPDLL=0 |
| 1809tXS=0 | 1810tXS=270000 |
| 1810tXSDLL=0 1811write_buffer_size=64 1812write_high_thresh_perc=85 1813write_low_thresh_perc=50 1814port=system.membus.master[5] 1815 1816[system.realview] 1817type=RealView --- 336 unchanged lines hidden (view full) --- 2154type=Pl390 2155clk_domain=system.clk_domain 2156cpu_addr=738205696 2157cpu_pio_delay=10000 2158default_p_state=UNDEFINED 2159dist_addr=738201600 2160dist_pio_delay=10000 2161eventq_index=0 | 1811tXSDLL=0 1812write_buffer_size=64 1813write_high_thresh_perc=85 1814write_low_thresh_perc=50 1815port=system.membus.master[5] 1816 1817[system.realview] 1818type=RealView --- 336 unchanged lines hidden (view full) --- 2155type=Pl390 2156clk_domain=system.clk_domain 2157cpu_addr=738205696 2158cpu_pio_delay=10000 2159default_p_state=UNDEFINED 2160dist_addr=738201600 2161dist_pio_delay=10000 2162eventq_index=0 |
| 2162gem5_extensions=true | 2163gem5_extensions=false |
| 2163int_latency=10000 2164it_lines=128 2165p_state_clk_gate_bins=20 2166p_state_clk_gate_max=1000000000000 2167p_state_clk_gate_min=1000 2168platform=system.realview 2169power_model=Null 2170system=system --- 296 unchanged lines hidden (view full) --- 2467power_model=Null 2468system=system 2469pio=system.iobus.master[21] 2470 2471[system.realview.nvmem] 2472type=SimpleMemory 2473bandwidth=73.000000 2474clk_domain=system.clk_domain | 2164int_latency=10000 2165it_lines=128 2166p_state_clk_gate_bins=20 2167p_state_clk_gate_max=1000000000000 2168p_state_clk_gate_min=1000 2169platform=system.realview 2170power_model=Null 2171system=system --- 296 unchanged lines hidden (view full) --- 2468power_model=Null 2469system=system 2470pio=system.iobus.master[21] 2471 2472[system.realview.nvmem] 2473type=SimpleMemory 2474bandwidth=73.000000 2475clk_domain=system.clk_domain |
| 2475conf_table_reported=true | 2476conf_table_reported=false |
| 2476default_p_state=UNDEFINED 2477eventq_index=0 2478in_addr_map=true | 2477default_p_state=UNDEFINED 2478eventq_index=0 2479in_addr_map=true |
| 2480kvm_map=true |
|
| 2479latency=30000 2480latency_var=0 2481null=false 2482p_state_clk_gate_bins=20 2483p_state_clk_gate_max=1000000000000 2484p_state_clk_gate_min=1000 2485power_model=Null | 2481latency=30000 2482latency_var=0 2483null=false 2484p_state_clk_gate_bins=20 2485p_state_clk_gate_max=1000000000000 2486p_state_clk_gate_min=1000 2487power_model=Null |
| 2486range=0:67108863 | 2488range=0:67108863:0:0:0:0 |
| 2487port=system.membus.master[1] 2488 2489[system.realview.pci_host] 2490type=GenericPciHost 2491clk_domain=system.clk_domain 2492conf_base=805306368 2493conf_device_bits=12 2494conf_size=268435456 --- 214 unchanged lines hidden (view full) --- 2709[system.realview.vram] 2710type=SimpleMemory 2711bandwidth=73.000000 2712clk_domain=system.clk_domain 2713conf_table_reported=false 2714default_p_state=UNDEFINED 2715eventq_index=0 2716in_addr_map=true | 2489port=system.membus.master[1] 2490 2491[system.realview.pci_host] 2492type=GenericPciHost 2493clk_domain=system.clk_domain 2494conf_base=805306368 2495conf_device_bits=12 2496conf_size=268435456 --- 214 unchanged lines hidden (view full) --- 2711[system.realview.vram] 2712type=SimpleMemory 2713bandwidth=73.000000 2714clk_domain=system.clk_domain 2715conf_table_reported=false 2716default_p_state=UNDEFINED 2717eventq_index=0 2718in_addr_map=true |
| 2719kvm_map=true |
|
| 2717latency=30000 2718latency_var=0 2719null=false 2720p_state_clk_gate_bins=20 2721p_state_clk_gate_max=1000000000000 2722p_state_clk_gate_min=1000 2723power_model=Null | 2720latency=30000 2721latency_var=0 2722null=false 2723p_state_clk_gate_bins=20 2724p_state_clk_gate_max=1000000000000 2725p_state_clk_gate_min=1000 2726power_model=Null |
| 2724range=402653184:436207615 | 2727range=402653184:436207615:0:0:0:0 |
| 2725port=system.iobus.master[11] 2726 2727[system.realview.watchdog_fake] 2728type=AmbaFake 2729amba_id=0 2730clk_domain=system.clk_domain 2731default_p_state=UNDEFINED 2732eventq_index=0 --- 59 unchanged lines hidden --- | 2728port=system.iobus.master[11] 2729 2730[system.realview.watchdog_fake] 2731type=AmbaFake 2732amba_id=0 2733clk_domain=system.clk_domain 2734default_p_state=UNDEFINED 2735eventq_index=0 --- 59 unchanged lines hidden --- |