| stats.txt (11530:6e143fd2cabf) | stats.txt (11547:dd6dfd38b6c2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.355903 # Number of seconds simulated 4sim_ticks 47355903328000 # Number of ticks simulated 5final_tick 47355903328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.355903 # Number of seconds simulated 4sim_ticks 47355903328000 # Number of ticks simulated 5final_tick 47355903328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 277163 # Simulator instruction rate (inst/s) 8host_op_rate 325991 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 14856975599 # Simulator tick rate (ticks/s) 10host_mem_usage 813232 # Number of bytes of host memory used 11host_seconds 3187.45 # Real time elapsed on the host | 7host_inst_rate 170836 # Simulator instruction rate (inst/s) 8host_op_rate 200933 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9157476763 # Simulator tick rate (ticks/s) 10host_mem_usage 772600 # Number of bytes of host memory used 11host_seconds 5171.28 # Real time elapsed on the host |
| 12sim_insts 883443630 # Number of instructions simulated 13sim_ops 1039082168 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 131584 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 123776 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 7567040 # Number of bytes read from this memory --- 458 unchanged lines hidden (view full) --- 478system.cpu0.dtb.read_hits 93899745 # DTB read hits 479system.cpu0.dtb.read_misses 250404 # DTB read misses 480system.cpu0.dtb.write_hits 82108561 # DTB write hits 481system.cpu0.dtb.write_misses 47900 # DTB write misses 482system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 483system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 484system.cpu0.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID 485system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID | 12sim_insts 883443630 # Number of instructions simulated 13sim_ops 1039082168 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 131584 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 123776 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 7567040 # Number of bytes read from this memory --- 458 unchanged lines hidden (view full) --- 478system.cpu0.dtb.read_hits 93899745 # DTB read hits 479system.cpu0.dtb.read_misses 250404 # DTB read misses 480system.cpu0.dtb.write_hits 82108561 # DTB write hits 481system.cpu0.dtb.write_misses 47900 # DTB write misses 482system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 483system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 484system.cpu0.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID 485system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID |
| 486system.cpu0.dtb.flush_entries 39156 # Number of entries that have been flushed from TLB | 486system.cpu0.dtb.flush_entries 39092 # Number of entries that have been flushed from TLB |
| 487system.cpu0.dtb.align_faults 2185 # Number of TLB faults due to alignment restrictions 488system.cpu0.dtb.prefetch_faults 10307 # Number of TLB faults due to prefetch 489system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 490system.cpu0.dtb.perms_faults 10956 # Number of TLB faults due to permissions restrictions 491system.cpu0.dtb.read_accesses 94150149 # DTB read accesses 492system.cpu0.dtb.write_accesses 82156461 # DTB write accesses 493system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 494system.cpu0.dtb.hits 176008306 # DTB hits --- 74 unchanged lines hidden (view full) --- 569system.cpu0.itb.read_hits 0 # DTB read hits 570system.cpu0.itb.read_misses 0 # DTB read misses 571system.cpu0.itb.write_hits 0 # DTB write hits 572system.cpu0.itb.write_misses 0 # DTB write misses 573system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 574system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 575system.cpu0.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID 576system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID | 487system.cpu0.dtb.align_faults 2185 # Number of TLB faults due to alignment restrictions 488system.cpu0.dtb.prefetch_faults 10307 # Number of TLB faults due to prefetch 489system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 490system.cpu0.dtb.perms_faults 10956 # Number of TLB faults due to permissions restrictions 491system.cpu0.dtb.read_accesses 94150149 # DTB read accesses 492system.cpu0.dtb.write_accesses 82156461 # DTB write accesses 493system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 494system.cpu0.dtb.hits 176008306 # DTB hits --- 74 unchanged lines hidden (view full) --- 569system.cpu0.itb.read_hits 0 # DTB read hits 570system.cpu0.itb.read_misses 0 # DTB read misses 571system.cpu0.itb.write_hits 0 # DTB write hits 572system.cpu0.itb.write_misses 0 # DTB write misses 573system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 574system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 575system.cpu0.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID 576system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID |
| 577system.cpu0.itb.flush_entries 28333 # Number of entries that have been flushed from TLB | 577system.cpu0.itb.flush_entries 28269 # Number of entries that have been flushed from TLB |
| 578system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 579system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 580system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 581system.cpu0.itb.perms_faults 171713 # Number of TLB faults due to permissions restrictions 582system.cpu0.itb.read_accesses 0 # DTB read accesses 583system.cpu0.itb.write_accesses 0 # DTB write accesses 584system.cpu0.itb.inst_accesses 259268632 # ITB inst accesses 585system.cpu0.itb.hits 259203584 # DTB hits --- 905 unchanged lines hidden (view full) --- 1491system.cpu1.dtb.read_hits 78594683 # DTB read hits 1492system.cpu1.dtb.read_misses 208094 # DTB read misses 1493system.cpu1.dtb.write_hits 69544419 # DTB write hits 1494system.cpu1.dtb.write_misses 47130 # DTB write misses 1495system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1496system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1497system.cpu1.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID 1498system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID | 578system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 579system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 580system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 581system.cpu0.itb.perms_faults 171713 # Number of TLB faults due to permissions restrictions 582system.cpu0.itb.read_accesses 0 # DTB read accesses 583system.cpu0.itb.write_accesses 0 # DTB write accesses 584system.cpu0.itb.inst_accesses 259268632 # ITB inst accesses 585system.cpu0.itb.hits 259203584 # DTB hits --- 905 unchanged lines hidden (view full) --- 1491system.cpu1.dtb.read_hits 78594683 # DTB read hits 1492system.cpu1.dtb.read_misses 208094 # DTB read misses 1493system.cpu1.dtb.write_hits 69544419 # DTB write hits 1494system.cpu1.dtb.write_misses 47130 # DTB write misses 1495system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1496system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1497system.cpu1.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID 1498system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID |
| 1499system.cpu1.dtb.flush_entries 35846 # Number of entries that have been flushed from TLB | 1499system.cpu1.dtb.flush_entries 35782 # Number of entries that have been flushed from TLB |
| 1500system.cpu1.dtb.align_faults 839 # Number of TLB faults due to alignment restrictions 1501system.cpu1.dtb.prefetch_faults 6709 # Number of TLB faults due to prefetch 1502system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1503system.cpu1.dtb.perms_faults 11450 # Number of TLB faults due to permissions restrictions 1504system.cpu1.dtb.read_accesses 78802777 # DTB read accesses 1505system.cpu1.dtb.write_accesses 69591549 # DTB write accesses 1506system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1507system.cpu1.dtb.hits 148139102 # DTB hits --- 74 unchanged lines hidden (view full) --- 1582system.cpu1.itb.read_hits 0 # DTB read hits 1583system.cpu1.itb.read_misses 0 # DTB read misses 1584system.cpu1.itb.write_hits 0 # DTB write hits 1585system.cpu1.itb.write_misses 0 # DTB write misses 1586system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1587system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1588system.cpu1.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID 1589system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID | 1500system.cpu1.dtb.align_faults 839 # Number of TLB faults due to alignment restrictions 1501system.cpu1.dtb.prefetch_faults 6709 # Number of TLB faults due to prefetch 1502system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1503system.cpu1.dtb.perms_faults 11450 # Number of TLB faults due to permissions restrictions 1504system.cpu1.dtb.read_accesses 78802777 # DTB read accesses 1505system.cpu1.dtb.write_accesses 69591549 # DTB write accesses 1506system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1507system.cpu1.dtb.hits 148139102 # DTB hits --- 74 unchanged lines hidden (view full) --- 1582system.cpu1.itb.read_hits 0 # DTB read hits 1583system.cpu1.itb.read_misses 0 # DTB read misses 1584system.cpu1.itb.write_hits 0 # DTB write hits 1585system.cpu1.itb.write_misses 0 # DTB write misses 1586system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1587system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1588system.cpu1.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID 1589system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID |
| 1590system.cpu1.itb.flush_entries 25383 # Number of entries that have been flushed from TLB | 1590system.cpu1.itb.flush_entries 25319 # Number of entries that have been flushed from TLB |
| 1591system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1592system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1593system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1594system.cpu1.itb.perms_faults 167002 # Number of TLB faults due to permissions restrictions 1595system.cpu1.itb.read_accesses 0 # DTB read accesses 1596system.cpu1.itb.write_accesses 0 # DTB write accesses 1597system.cpu1.itb.inst_accesses 219399751 # ITB inst accesses 1598system.cpu1.itb.hits 219337574 # DTB hits --- 1821 unchanged lines hidden --- | 1591system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1592system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1593system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1594system.cpu1.itb.perms_faults 167002 # Number of TLB faults due to permissions restrictions 1595system.cpu1.itb.read_accesses 0 # DTB read accesses 1596system.cpu1.itb.write_accesses 0 # DTB write accesses 1597system.cpu1.itb.inst_accesses 219399751 # ITB inst accesses 1598system.cpu1.itb.hits 219337574 # DTB hits --- 1821 unchanged lines hidden --- |