| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.355903 # Number of seconds simulated 4sim_ticks 47355903328000 # Number of ticks simulated 5final_tick 47355903328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.355903 # Number of seconds simulated 4sim_ticks 47355903328000 # Number of ticks simulated 5final_tick 47355903328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 234942 # Simulator instruction rate (inst/s) 8host_op_rate 276333 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 12593783431 # Simulator tick rate (ticks/s) 10host_mem_usage 765460 # Number of bytes of host memory used 11host_seconds 3760.26 # Real time elapsed on the host | 7host_inst_rate 277163 # Simulator instruction rate (inst/s) 8host_op_rate 325991 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 14856975599 # Simulator tick rate (ticks/s) 10host_mem_usage 813232 # Number of bytes of host memory used 11host_seconds 3187.45 # Real time elapsed on the host |
| 12sim_insts 883443630 # Number of instructions simulated 13sim_ops 1039082168 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 883443630 # Number of instructions simulated 13sim_ops 1039082168 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu0.dtb.walker 131584 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 123776 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 7567040 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 14160840 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 16409728 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 122112 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 100992 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 3330560 # Number of bytes read from this memory --- 328 unchanged lines hidden (view full) --- 352system.physmem_1.preBackEnergy 27380291180250 # Energy for precharge background per rank (pJ) 353system.physmem_1.totalEnergy 31664580366120 # Total energy per rank (pJ) 354system.physmem_1.averagePower 668.651183 # Core power per rank (mW) 355system.physmem_1.memoryStateTime::IDLE 45549316476567 # Time in different power states 356system.physmem_1.memoryStateTime::REF 1581317660000 # Time in different power states 357system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 358system.physmem_1.memoryStateTime::ACT 225268560933 # Time in different power states 359system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu0.dtb.walker 131584 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 123776 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 7567040 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 14160840 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 16409728 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 122112 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 100992 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 3330560 # Number of bytes read from this memory --- 328 unchanged lines hidden (view full) --- 353system.physmem_1.preBackEnergy 27380291180250 # Energy for precharge background per rank (pJ) 354system.physmem_1.totalEnergy 31664580366120 # Total energy per rank (pJ) 355system.physmem_1.averagePower 668.651183 # Core power per rank (mW) 356system.physmem_1.memoryStateTime::IDLE 45549316476567 # Time in different power states 357system.physmem_1.memoryStateTime::REF 1581317660000 # Time in different power states 358system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 359system.physmem_1.memoryStateTime::ACT 225268560933 # Time in different power states 360system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 361system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 360system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 361system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 362system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 363system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 364system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 365system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 366system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 367system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory --- 10 unchanged lines hidden (view full) --- 378system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 379system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 380system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 381system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 382system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 383system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 384system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 385system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) | 362system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 363system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 364system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 365system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 366system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 367system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 368system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory 369system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory --- 10 unchanged lines hidden (view full) --- 380system.realview.nvmem.bw_inst_read::cpu0.inst 15 # Instruction read bandwidth from this memory (bytes/s) 381system.realview.nvmem.bw_inst_read::cpu1.inst 12 # Instruction read bandwidth from this memory (bytes/s) 382system.realview.nvmem.bw_inst_read::total 27 # Instruction read bandwidth from this memory (bytes/s) 383system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 384system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 385system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 386system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 387system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) |
| 388system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 389system.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 390system.bridge.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 386system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 387system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 388system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 389system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 390system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 391system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 392system.cpu0.branchPred.lookups 145452632 # Number of BP lookups 393system.cpu0.branchPred.condPredicted 102233764 # Number of conditional branches predicted --- 4 unchanged lines hidden (view full) --- 398system.cpu0.branchPred.BTBHitPct 70.005246 # BTB Hit Percentage 399system.cpu0.branchPred.usedRAS 17327542 # Number of times the RAS was used to get a target. 400system.cpu0.branchPred.RASInCorrect 1162135 # Number of incorrect RAS predictions. 401system.cpu0.branchPred.indirectLookups 3835403 # Number of indirect predictor lookups. 402system.cpu0.branchPred.indirectHits 2658726 # Number of indirect target hits. 403system.cpu0.branchPred.indirectMisses 1176677 # Number of indirect misses. 404system.cpu0.branchPredindirectMispredicted 420775 # Number of mispredicted indirect branches. 405system.cpu_clk_domain.clock 500 # Clock period in ticks | 391system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 392system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 393system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 394system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 395system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 396system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 397system.cpu0.branchPred.lookups 145452632 # Number of BP lookups 398system.cpu0.branchPred.condPredicted 102233764 # Number of conditional branches predicted --- 4 unchanged lines hidden (view full) --- 403system.cpu0.branchPred.BTBHitPct 70.005246 # BTB Hit Percentage 404system.cpu0.branchPred.usedRAS 17327542 # Number of times the RAS was used to get a target. 405system.cpu0.branchPred.RASInCorrect 1162135 # Number of incorrect RAS predictions. 406system.cpu0.branchPred.indirectLookups 3835403 # Number of indirect predictor lookups. 407system.cpu0.branchPred.indirectHits 2658726 # Number of indirect target hits. 408system.cpu0.branchPred.indirectMisses 1176677 # Number of indirect misses. 409system.cpu0.branchPredindirectMispredicted 420775 # Number of mispredicted indirect branches. 410system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 411system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 406system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 407system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 408system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 409system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 410system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 411system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 412system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 413system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 427system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 428system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 429system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 430system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 431system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 432system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 433system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 434system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 412system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 413system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 414system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 415system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 416system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 417system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 418system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 419system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 433system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 434system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 435system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 436system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 437system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 438system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 439system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 440system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 441system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 435system.cpu0.dtb.walker.walks 298304 # Table walker walks requested 436system.cpu0.dtb.walker.walksLong 298304 # Table walker walks initiated with long descriptors 437system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10716 # Level at which table walker walks with long descriptors terminate 438system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 85635 # Level at which table walker walks with long descriptors terminate 439system.cpu0.dtb.walker.walkWaitTime::samples 298304 # Table walker wait (enqueue to first request) latency 440system.cpu0.dtb.walker.walkWaitTime::0 298304 100.00% 100.00% # Table walker wait (enqueue to first request) latency 441system.cpu0.dtb.walker.walkWaitTime::total 298304 # Table walker wait (enqueue to first request) latency 442system.cpu0.dtb.walker.walkCompletionTime::samples 96351 # Table walker service (enqueue to completion) latency --- 39 unchanged lines hidden (view full) --- 482system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 483system.cpu0.dtb.perms_faults 10956 # Number of TLB faults due to permissions restrictions 484system.cpu0.dtb.read_accesses 94150149 # DTB read accesses 485system.cpu0.dtb.write_accesses 82156461 # DTB write accesses 486system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 487system.cpu0.dtb.hits 176008306 # DTB hits 488system.cpu0.dtb.misses 298304 # DTB misses 489system.cpu0.dtb.accesses 176306610 # DTB accesses | 442system.cpu0.dtb.walker.walks 298304 # Table walker walks requested 443system.cpu0.dtb.walker.walksLong 298304 # Table walker walks initiated with long descriptors 444system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10716 # Level at which table walker walks with long descriptors terminate 445system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 85635 # Level at which table walker walks with long descriptors terminate 446system.cpu0.dtb.walker.walkWaitTime::samples 298304 # Table walker wait (enqueue to first request) latency 447system.cpu0.dtb.walker.walkWaitTime::0 298304 100.00% 100.00% # Table walker wait (enqueue to first request) latency 448system.cpu0.dtb.walker.walkWaitTime::total 298304 # Table walker wait (enqueue to first request) latency 449system.cpu0.dtb.walker.walkCompletionTime::samples 96351 # Table walker service (enqueue to completion) latency --- 39 unchanged lines hidden (view full) --- 489system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 490system.cpu0.dtb.perms_faults 10956 # Number of TLB faults due to permissions restrictions 491system.cpu0.dtb.read_accesses 94150149 # DTB read accesses 492system.cpu0.dtb.write_accesses 82156461 # DTB write accesses 493system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 494system.cpu0.dtb.hits 176008306 # DTB hits 495system.cpu0.dtb.misses 298304 # DTB misses 496system.cpu0.dtb.accesses 176306610 # DTB accesses |
| 497system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 490system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 491system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 492system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 493system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 494system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 495system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 496system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 497system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 511system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 512system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 513system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 514system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 515system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 516system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 517system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 518system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 498system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 499system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 500system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 501system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 502system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 503system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 504system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 505system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 519system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 520system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 521system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 522system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 523system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 524system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 525system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 526system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 527system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 519system.cpu0.itb.walker.walks 65048 # Table walker walks requested 520system.cpu0.itb.walker.walksLong 65048 # Table walker walks initiated with long descriptors 521system.cpu0.itb.walker.walksLongTerminationLevel::Level2 515 # Level at which table walker walks with long descriptors terminate 522system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52970 # Level at which table walker walks with long descriptors terminate 523system.cpu0.itb.walker.walkWaitTime::samples 65048 # Table walker wait (enqueue to first request) latency 524system.cpu0.itb.walker.walkWaitTime::0 65048 100.00% 100.00% # Table walker wait (enqueue to first request) latency 525system.cpu0.itb.walker.walkWaitTime::total 65048 # Table walker wait (enqueue to first request) latency 526system.cpu0.itb.walker.walkCompletionTime::samples 53485 # Table walker service (enqueue to completion) latency --- 44 unchanged lines hidden (view full) --- 571system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 572system.cpu0.itb.perms_faults 171713 # Number of TLB faults due to permissions restrictions 573system.cpu0.itb.read_accesses 0 # DTB read accesses 574system.cpu0.itb.write_accesses 0 # DTB write accesses 575system.cpu0.itb.inst_accesses 259268632 # ITB inst accesses 576system.cpu0.itb.hits 259203584 # DTB hits 577system.cpu0.itb.misses 65048 # DTB misses 578system.cpu0.itb.accesses 259268632 # DTB accesses | 528system.cpu0.itb.walker.walks 65048 # Table walker walks requested 529system.cpu0.itb.walker.walksLong 65048 # Table walker walks initiated with long descriptors 530system.cpu0.itb.walker.walksLongTerminationLevel::Level2 515 # Level at which table walker walks with long descriptors terminate 531system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52970 # Level at which table walker walks with long descriptors terminate 532system.cpu0.itb.walker.walkWaitTime::samples 65048 # Table walker wait (enqueue to first request) latency 533system.cpu0.itb.walker.walkWaitTime::0 65048 100.00% 100.00% # Table walker wait (enqueue to first request) latency 534system.cpu0.itb.walker.walkWaitTime::total 65048 # Table walker wait (enqueue to first request) latency 535system.cpu0.itb.walker.walkCompletionTime::samples 53485 # Table walker service (enqueue to completion) latency --- 44 unchanged lines hidden (view full) --- 580system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 581system.cpu0.itb.perms_faults 171713 # Number of TLB faults due to permissions restrictions 582system.cpu0.itb.read_accesses 0 # DTB read accesses 583system.cpu0.itb.write_accesses 0 # DTB write accesses 584system.cpu0.itb.inst_accesses 259268632 # ITB inst accesses 585system.cpu0.itb.hits 259203584 # DTB hits 586system.cpu0.itb.misses 65048 # DTB misses 587system.cpu0.itb.accesses 259268632 # DTB accesses |
| 588system.cpu0.numPwrStateTransitions 26040 # Number of power state transitions 589system.cpu0.pwrStateClkGateDist::samples 13020 # Distribution of time spent in the clock gated state 590system.cpu0.pwrStateClkGateDist::mean 3597852748.702535 # Distribution of time spent in the clock gated state 591system.cpu0.pwrStateClkGateDist::stdev 96451622625.318069 # Distribution of time spent in the clock gated state 592system.cpu0.pwrStateClkGateDist::underflows 3172 24.36% 24.36% # Distribution of time spent in the clock gated state 593system.cpu0.pwrStateClkGateDist::1000-5e+10 9818 75.41% 99.77% # Distribution of time spent in the clock gated state 594system.cpu0.pwrStateClkGateDist::5e+10-1e+11 12 0.09% 99.86% # Distribution of time spent in the clock gated state 595system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 596system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 597system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 598system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 599system.cpu0.pwrStateClkGateDist::5.5e+11-6e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state 600system.cpu0.pwrStateClkGateDist::overflows 13 0.10% 100.00% # Distribution of time spent in the clock gated state 601system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 602system.cpu0.pwrStateClkGateDist::max_value 7033291450000 # Distribution of time spent in the clock gated state 603system.cpu0.pwrStateClkGateDist::total 13020 # Distribution of time spent in the clock gated state 604system.cpu0.pwrStateResidencyTicks::ON 511860539893 # Cumulative time (in ticks) in various power states 605system.cpu0.pwrStateResidencyTicks::CLK_GATED 46844042788107 # Cumulative time (in ticks) in various power states |
|
| 579system.cpu0.numCycles 1023758481 # number of cpu cycles simulated 580system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 581system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 582system.cpu0.committedInsts 483101155 # Number of instructions committed 583system.cpu0.committedOps 567019823 # Number of ops (including micro ops) committed 584system.cpu0.discardedOps 47457065 # Number of ops (including micro ops) which were discarded before commit 585system.cpu0.numFetchSuspends 4178 # Number of times Execute suspended instruction fetching 586system.cpu0.quiesceCycles 93688785177 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt --- 33 unchanged lines hidden (view full) --- 620system.cpu0.op_class_0::MemWrite 81764563 14.42% 100.00% # Class of committed instruction 621system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 622system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 623system.cpu0.op_class_0::total 567019823 # Class of committed instruction 624system.cpu0.kern.inst.arm 0 # number of arm instructions executed 625system.cpu0.kern.inst.quiesce 13020 # number of quiesce instructions executed 626system.cpu0.tickCycles 768761843 # Number of cycles that the object actually ticked 627system.cpu0.idleCycles 254996638 # Total number of cycles that the object has spent stopped | 606system.cpu0.numCycles 1023758481 # number of cpu cycles simulated 607system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 608system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 609system.cpu0.committedInsts 483101155 # Number of instructions committed 610system.cpu0.committedOps 567019823 # Number of ops (including micro ops) committed 611system.cpu0.discardedOps 47457065 # Number of ops (including micro ops) which were discarded before commit 612system.cpu0.numFetchSuspends 4178 # Number of times Execute suspended instruction fetching 613system.cpu0.quiesceCycles 93688785177 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt --- 33 unchanged lines hidden (view full) --- 647system.cpu0.op_class_0::MemWrite 81764563 14.42% 100.00% # Class of committed instruction 648system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 649system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 650system.cpu0.op_class_0::total 567019823 # Class of committed instruction 651system.cpu0.kern.inst.arm 0 # number of arm instructions executed 652system.cpu0.kern.inst.quiesce 13020 # number of quiesce instructions executed 653system.cpu0.tickCycles 768761843 # Number of cycles that the object actually ticked 654system.cpu0.idleCycles 254996638 # Total number of cycles that the object has spent stopped |
| 655system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 628system.cpu0.dcache.tags.replacements 6026209 # number of replacements 629system.cpu0.dcache.tags.tagsinuse 478.505782 # Cycle average of tags in use 630system.cpu0.dcache.tags.total_refs 166971566 # Total number of references to valid blocks. 631system.cpu0.dcache.tags.sampled_refs 6026721 # Sample count of references to valid blocks. 632system.cpu0.dcache.tags.avg_refs 27.705209 # Average number of references to valid blocks. 633system.cpu0.dcache.tags.warmup_cycle 5039130000 # Cycle when the warmup percentage was hit. 634system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.505782 # Average occupied blocks per requestor 635system.cpu0.dcache.tags.occ_percent::cpu0.data 0.934582 # Average percentage of cache occupancy 636system.cpu0.dcache.tags.occ_percent::total 0.934582 # Average percentage of cache occupancy 637system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 638system.cpu0.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id 639system.cpu0.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id 640system.cpu0.dcache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id 641system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 642system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 643system.cpu0.dcache.tags.tag_accesses 355154483 # Number of tag accesses 644system.cpu0.dcache.tags.data_accesses 355154483 # Number of data accesses | 656system.cpu0.dcache.tags.replacements 6026209 # number of replacements 657system.cpu0.dcache.tags.tagsinuse 478.505782 # Cycle average of tags in use 658system.cpu0.dcache.tags.total_refs 166971566 # Total number of references to valid blocks. 659system.cpu0.dcache.tags.sampled_refs 6026721 # Sample count of references to valid blocks. 660system.cpu0.dcache.tags.avg_refs 27.705209 # Average number of references to valid blocks. 661system.cpu0.dcache.tags.warmup_cycle 5039130000 # Cycle when the warmup percentage was hit. 662system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.505782 # Average occupied blocks per requestor 663system.cpu0.dcache.tags.occ_percent::cpu0.data 0.934582 # Average percentage of cache occupancy 664system.cpu0.dcache.tags.occ_percent::total 0.934582 # Average percentage of cache occupancy 665system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 666system.cpu0.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id 667system.cpu0.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id 668system.cpu0.dcache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id 669system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 670system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 671system.cpu0.dcache.tags.tag_accesses 355154483 # Number of tag accesses 672system.cpu0.dcache.tags.data_accesses 355154483 # Number of data accesses |
| 673system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 645system.cpu0.dcache.ReadReq_hits::cpu0.data 85976696 # number of ReadReq hits 646system.cpu0.dcache.ReadReq_hits::total 85976696 # number of ReadReq hits 647system.cpu0.dcache.WriteReq_hits::cpu0.data 76051356 # number of WriteReq hits 648system.cpu0.dcache.WriteReq_hits::total 76051356 # number of WriteReq hits 649system.cpu0.dcache.SoftPFReq_hits::cpu0.data 300861 # number of SoftPFReq hits 650system.cpu0.dcache.SoftPFReq_hits::total 300861 # number of SoftPFReq hits 651system.cpu0.dcache.WriteLineReq_hits::cpu0.data 281214 # number of WriteLineReq hits 652system.cpu0.dcache.WriteLineReq_hits::total 281214 # number of WriteLineReq hits --- 184 unchanged lines hidden (view full) --- 837system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18263.086208 # average overall mshr miss latency 838system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18263.086208 # average overall mshr miss latency 839system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18623.032104 # average overall mshr miss latency 840system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18623.032104 # average overall mshr miss latency 841system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193581.572141 # average ReadReq mshr uncacheable latency 842system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193581.572141 # average ReadReq mshr uncacheable latency 843system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97524.480748 # average overall mshr uncacheable latency 844system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97524.480748 # average overall mshr uncacheable latency | 674system.cpu0.dcache.ReadReq_hits::cpu0.data 85976696 # number of ReadReq hits 675system.cpu0.dcache.ReadReq_hits::total 85976696 # number of ReadReq hits 676system.cpu0.dcache.WriteReq_hits::cpu0.data 76051356 # number of WriteReq hits 677system.cpu0.dcache.WriteReq_hits::total 76051356 # number of WriteReq hits 678system.cpu0.dcache.SoftPFReq_hits::cpu0.data 300861 # number of SoftPFReq hits 679system.cpu0.dcache.SoftPFReq_hits::total 300861 # number of SoftPFReq hits 680system.cpu0.dcache.WriteLineReq_hits::cpu0.data 281214 # number of WriteLineReq hits 681system.cpu0.dcache.WriteLineReq_hits::total 281214 # number of WriteLineReq hits --- 184 unchanged lines hidden (view full) --- 866system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18263.086208 # average overall mshr miss latency 867system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18263.086208 # average overall mshr miss latency 868system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18623.032104 # average overall mshr miss latency 869system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18623.032104 # average overall mshr miss latency 870system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193581.572141 # average ReadReq mshr uncacheable latency 871system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193581.572141 # average ReadReq mshr uncacheable latency 872system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97524.480748 # average overall mshr uncacheable latency 873system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97524.480748 # average overall mshr uncacheable latency |
| 874system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 845system.cpu0.icache.tags.replacements 9817579 # number of replacements 846system.cpu0.icache.tags.tagsinuse 511.932451 # Cycle average of tags in use 847system.cpu0.icache.tags.total_refs 249208397 # Total number of references to valid blocks. 848system.cpu0.icache.tags.sampled_refs 9818091 # Sample count of references to valid blocks. 849system.cpu0.icache.tags.avg_refs 25.382572 # Average number of references to valid blocks. 850system.cpu0.icache.tags.warmup_cycle 22021065000 # Cycle when the warmup percentage was hit. 851system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932451 # Average occupied blocks per requestor 852system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999868 # Average percentage of cache occupancy 853system.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy 854system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 855system.cpu0.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id 856system.cpu0.icache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id 857system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id 858system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 859system.cpu0.icache.tags.tag_accesses 527871096 # Number of tag accesses 860system.cpu0.icache.tags.data_accesses 527871096 # Number of data accesses | 875system.cpu0.icache.tags.replacements 9817579 # number of replacements 876system.cpu0.icache.tags.tagsinuse 511.932451 # Cycle average of tags in use 877system.cpu0.icache.tags.total_refs 249208397 # Total number of references to valid blocks. 878system.cpu0.icache.tags.sampled_refs 9818091 # Sample count of references to valid blocks. 879system.cpu0.icache.tags.avg_refs 25.382572 # Average number of references to valid blocks. 880system.cpu0.icache.tags.warmup_cycle 22021065000 # Cycle when the warmup percentage was hit. 881system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932451 # Average occupied blocks per requestor 882system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999868 # Average percentage of cache occupancy 883system.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy 884system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 885system.cpu0.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id 886system.cpu0.icache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id 887system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id 888system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 889system.cpu0.icache.tags.tag_accesses 527871096 # Number of tag accesses 890system.cpu0.icache.tags.data_accesses 527871096 # Number of data accesses |
| 891system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 861system.cpu0.icache.ReadReq_hits::cpu0.inst 249208397 # number of ReadReq hits 862system.cpu0.icache.ReadReq_hits::total 249208397 # number of ReadReq hits 863system.cpu0.icache.demand_hits::cpu0.inst 249208397 # number of demand (read+write) hits 864system.cpu0.icache.demand_hits::total 249208397 # number of demand (read+write) hits 865system.cpu0.icache.overall_hits::cpu0.inst 249208397 # number of overall hits 866system.cpu0.icache.overall_hits::total 249208397 # number of overall hits 867system.cpu0.icache.ReadReq_misses::cpu0.inst 9818101 # number of ReadReq misses 868system.cpu0.icache.ReadReq_misses::total 9818101 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 933system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9583.632110 # average overall mshr miss latency 934system.cpu0.icache.demand_avg_mshr_miss_latency::total 9583.632110 # average overall mshr miss latency 935system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9583.632110 # average overall mshr miss latency 936system.cpu0.icache.overall_avg_mshr_miss_latency::total 9583.632110 # average overall mshr miss latency 937system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92491.166179 # average ReadReq mshr uncacheable latency 938system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92491.166179 # average ReadReq mshr uncacheable latency 939system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92491.166179 # average overall mshr uncacheable latency 940system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92491.166179 # average overall mshr uncacheable latency | 892system.cpu0.icache.ReadReq_hits::cpu0.inst 249208397 # number of ReadReq hits 893system.cpu0.icache.ReadReq_hits::total 249208397 # number of ReadReq hits 894system.cpu0.icache.demand_hits::cpu0.inst 249208397 # number of demand (read+write) hits 895system.cpu0.icache.demand_hits::total 249208397 # number of demand (read+write) hits 896system.cpu0.icache.overall_hits::cpu0.inst 249208397 # number of overall hits 897system.cpu0.icache.overall_hits::total 249208397 # number of overall hits 898system.cpu0.icache.ReadReq_misses::cpu0.inst 9818101 # number of ReadReq misses 899system.cpu0.icache.ReadReq_misses::total 9818101 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 964system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9583.632110 # average overall mshr miss latency 965system.cpu0.icache.demand_avg_mshr_miss_latency::total 9583.632110 # average overall mshr miss latency 966system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9583.632110 # average overall mshr miss latency 967system.cpu0.icache.overall_avg_mshr_miss_latency::total 9583.632110 # average overall mshr miss latency 968system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92491.166179 # average ReadReq mshr uncacheable latency 969system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92491.166179 # average ReadReq mshr uncacheable latency 970system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92491.166179 # average overall mshr uncacheable latency 971system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92491.166179 # average overall mshr uncacheable latency |
| 972system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 941system.cpu0.l2cache.prefetcher.num_hwpf_issued 8242304 # number of hwpf issued 942system.cpu0.l2cache.prefetcher.pfIdentified 8243665 # number of prefetch candidates identified 943system.cpu0.l2cache.prefetcher.pfBufferHit 1198 # number of redundant prefetches already in prefetch queue 944system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 945system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 946system.cpu0.l2cache.prefetcher.pfSpanPage 1073071 # number of prefetches not generated due to page crossing | 973system.cpu0.l2cache.prefetcher.num_hwpf_issued 8242304 # number of hwpf issued 974system.cpu0.l2cache.prefetcher.pfIdentified 8243665 # number of prefetch candidates identified 975system.cpu0.l2cache.prefetcher.pfBufferHit 1198 # number of redundant prefetches already in prefetch queue 976system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 977system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 978system.cpu0.l2cache.prefetcher.pfSpanPage 1073071 # number of prefetches not generated due to page crossing |
| 979system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 947system.cpu0.l2cache.tags.replacements 2829183 # number of replacements 948system.cpu0.l2cache.tags.tagsinuse 16163.343057 # Cycle average of tags in use 949system.cpu0.l2cache.tags.total_refs 24764914 # Total number of references to valid blocks. 950system.cpu0.l2cache.tags.sampled_refs 2845343 # Sample count of references to valid blocks. 951system.cpu0.l2cache.tags.avg_refs 8.703666 # Average number of references to valid blocks. 952system.cpu0.l2cache.tags.warmup_cycle 5659477500 # Cycle when the warmup percentage was hit. 953system.cpu0.l2cache.tags.occ_blocks::writebacks 15257.249232 # Average occupied blocks per requestor 954system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.561913 # Average occupied blocks per requestor --- 19 unchanged lines hidden (view full) --- 974system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2616 # Occupied blocks per task id 975system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5298 # Occupied blocks per task id 976system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5548 # Occupied blocks per task id 977system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.082764 # Percentage of cache occupancy per task id 978system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003418 # Percentage of cache occupancy per task id 979system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.900146 # Percentage of cache occupancy per task id 980system.cpu0.l2cache.tags.tag_accesses 533961635 # Number of tag accesses 981system.cpu0.l2cache.tags.data_accesses 533961635 # Number of data accesses | 980system.cpu0.l2cache.tags.replacements 2829183 # number of replacements 981system.cpu0.l2cache.tags.tagsinuse 16163.343057 # Cycle average of tags in use 982system.cpu0.l2cache.tags.total_refs 24764914 # Total number of references to valid blocks. 983system.cpu0.l2cache.tags.sampled_refs 2845343 # Sample count of references to valid blocks. 984system.cpu0.l2cache.tags.avg_refs 8.703666 # Average number of references to valid blocks. 985system.cpu0.l2cache.tags.warmup_cycle 5659477500 # Cycle when the warmup percentage was hit. 986system.cpu0.l2cache.tags.occ_blocks::writebacks 15257.249232 # Average occupied blocks per requestor 987system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.561913 # Average occupied blocks per requestor --- 19 unchanged lines hidden (view full) --- 1007system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2616 # Occupied blocks per task id 1008system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5298 # Occupied blocks per task id 1009system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5548 # Occupied blocks per task id 1010system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.082764 # Percentage of cache occupancy per task id 1011system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003418 # Percentage of cache occupancy per task id 1012system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.900146 # Percentage of cache occupancy per task id 1013system.cpu0.l2cache.tags.tag_accesses 533961635 # Number of tag accesses 1014system.cpu0.l2cache.tags.data_accesses 533961635 # Number of data accesses |
| 1015system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 982system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 561309 # number of ReadReq hits 983system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 167224 # number of ReadReq hits 984system.cpu0.l2cache.ReadReq_hits::total 728533 # number of ReadReq hits 985system.cpu0.l2cache.WritebackDirty_hits::writebacks 3942058 # number of WritebackDirty hits 986system.cpu0.l2cache.WritebackDirty_hits::total 3942058 # number of WritebackDirty hits 987system.cpu0.l2cache.WritebackClean_hits::writebacks 11898812 # number of WritebackClean hits 988system.cpu0.l2cache.WritebackClean_hits::total 11898812 # number of WritebackClean hits 989system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits --- 323 unchanged lines hidden (view full) --- 1313system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93491.577542 # average overall mshr uncacheable latency 1314system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89406.453405 # average overall mshr uncacheable latency 1315system.cpu0.toL2Bus.snoop_filter.tot_requests 32574371 # Total number of requests made to the snoop filter. 1316system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16625689 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1317system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2928 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1318system.cpu0.toL2Bus.snoop_filter.tot_snoops 2229520 # Total number of snoops made to the snoop filter. 1319system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2229086 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1320system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 434 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1016system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 561309 # number of ReadReq hits 1017system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 167224 # number of ReadReq hits 1018system.cpu0.l2cache.ReadReq_hits::total 728533 # number of ReadReq hits 1019system.cpu0.l2cache.WritebackDirty_hits::writebacks 3942058 # number of WritebackDirty hits 1020system.cpu0.l2cache.WritebackDirty_hits::total 3942058 # number of WritebackDirty hits 1021system.cpu0.l2cache.WritebackClean_hits::writebacks 11898812 # number of WritebackClean hits 1022system.cpu0.l2cache.WritebackClean_hits::total 11898812 # number of WritebackClean hits 1023system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits --- 323 unchanged lines hidden (view full) --- 1347system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93491.577542 # average overall mshr uncacheable latency 1348system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89406.453405 # average overall mshr uncacheable latency 1349system.cpu0.toL2Bus.snoop_filter.tot_requests 32574371 # Total number of requests made to the snoop filter. 1350system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16625689 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1351system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2928 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1352system.cpu0.toL2Bus.snoop_filter.tot_snoops 2229520 # Total number of snoops made to the snoop filter. 1353system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2229086 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1354system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 434 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1355system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 1321system.cpu0.toL2Bus.trans_dist::ReadReq 913111 # Transaction distribution 1322system.cpu0.toL2Bus.trans_dist::ReadResp 14927613 # Transaction distribution 1323system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 1324system.cpu0.toL2Bus.trans_dist::WriteReq 31225 # Transaction distribution 1325system.cpu0.toL2Bus.trans_dist::WriteResp 31225 # Transaction distribution 1326system.cpu0.toL2Bus.trans_dist::WritebackDirty 5591471 # Transaction distribution 1327system.cpu0.toL2Bus.trans_dist::WritebackClean 11901739 # Transaction distribution 1328system.cpu0.toL2Bus.trans_dist::CleanEvict 2979875 # Transaction distribution --- 52 unchanged lines hidden (view full) --- 1381system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1382system.cpu1.branchPred.BTBHitPct 69.840703 # BTB Hit Percentage 1383system.cpu1.branchPred.usedRAS 14217829 # Number of times the RAS was used to get a target. 1384system.cpu1.branchPred.RASInCorrect 926540 # Number of incorrect RAS predictions. 1385system.cpu1.branchPred.indirectLookups 3290763 # Number of indirect predictor lookups. 1386system.cpu1.branchPred.indirectHits 2135700 # Number of indirect target hits. 1387system.cpu1.branchPred.indirectMisses 1155063 # Number of indirect misses. 1388system.cpu1.branchPredindirectMispredicted 419705 # Number of mispredicted indirect branches. | 1356system.cpu0.toL2Bus.trans_dist::ReadReq 913111 # Transaction distribution 1357system.cpu0.toL2Bus.trans_dist::ReadResp 14927613 # Transaction distribution 1358system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 1359system.cpu0.toL2Bus.trans_dist::WriteReq 31225 # Transaction distribution 1360system.cpu0.toL2Bus.trans_dist::WriteResp 31225 # Transaction distribution 1361system.cpu0.toL2Bus.trans_dist::WritebackDirty 5591471 # Transaction distribution 1362system.cpu0.toL2Bus.trans_dist::WritebackClean 11901739 # Transaction distribution 1363system.cpu0.toL2Bus.trans_dist::CleanEvict 2979875 # Transaction distribution --- 52 unchanged lines hidden (view full) --- 1416system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1417system.cpu1.branchPred.BTBHitPct 69.840703 # BTB Hit Percentage 1418system.cpu1.branchPred.usedRAS 14217829 # Number of times the RAS was used to get a target. 1419system.cpu1.branchPred.RASInCorrect 926540 # Number of incorrect RAS predictions. 1420system.cpu1.branchPred.indirectLookups 3290763 # Number of indirect predictor lookups. 1421system.cpu1.branchPred.indirectHits 2135700 # Number of indirect target hits. 1422system.cpu1.branchPred.indirectMisses 1155063 # Number of indirect misses. 1423system.cpu1.branchPredindirectMispredicted 419705 # Number of mispredicted indirect branches. |
| 1424system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 1389system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1390system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1391system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1392system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1393system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1394system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1395system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1396system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1410system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1411system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1412system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1413system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1414system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1415system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1416system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1417system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1425system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1426system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1427system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1428system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1429system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1430system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1431system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1432system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1446system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1447system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1448system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1449system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1450system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1451system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1452system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1453system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1454system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 1418system.cpu1.dtb.walker.walks 255224 # Table walker walks requested 1419system.cpu1.dtb.walker.walksLong 255224 # Table walker walks initiated with long descriptors 1420system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8861 # Level at which table walker walks with long descriptors terminate 1421system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76574 # Level at which table walker walks with long descriptors terminate 1422system.cpu1.dtb.walker.walkWaitTime::samples 255224 # Table walker wait (enqueue to first request) latency 1423system.cpu1.dtb.walker.walkWaitTime::0 255224 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1424system.cpu1.dtb.walker.walkWaitTime::total 255224 # Table walker wait (enqueue to first request) latency 1425system.cpu1.dtb.walker.walkCompletionTime::samples 85435 # Table walker service (enqueue to completion) latency --- 39 unchanged lines hidden (view full) --- 1465system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1466system.cpu1.dtb.perms_faults 11450 # Number of TLB faults due to permissions restrictions 1467system.cpu1.dtb.read_accesses 78802777 # DTB read accesses 1468system.cpu1.dtb.write_accesses 69591549 # DTB write accesses 1469system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1470system.cpu1.dtb.hits 148139102 # DTB hits 1471system.cpu1.dtb.misses 255224 # DTB misses 1472system.cpu1.dtb.accesses 148394326 # DTB accesses | 1455system.cpu1.dtb.walker.walks 255224 # Table walker walks requested 1456system.cpu1.dtb.walker.walksLong 255224 # Table walker walks initiated with long descriptors 1457system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8861 # Level at which table walker walks with long descriptors terminate 1458system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76574 # Level at which table walker walks with long descriptors terminate 1459system.cpu1.dtb.walker.walkWaitTime::samples 255224 # Table walker wait (enqueue to first request) latency 1460system.cpu1.dtb.walker.walkWaitTime::0 255224 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1461system.cpu1.dtb.walker.walkWaitTime::total 255224 # Table walker wait (enqueue to first request) latency 1462system.cpu1.dtb.walker.walkCompletionTime::samples 85435 # Table walker service (enqueue to completion) latency --- 39 unchanged lines hidden (view full) --- 1502system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1503system.cpu1.dtb.perms_faults 11450 # Number of TLB faults due to permissions restrictions 1504system.cpu1.dtb.read_accesses 78802777 # DTB read accesses 1505system.cpu1.dtb.write_accesses 69591549 # DTB write accesses 1506system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1507system.cpu1.dtb.hits 148139102 # DTB hits 1508system.cpu1.dtb.misses 255224 # DTB misses 1509system.cpu1.dtb.accesses 148394326 # DTB accesses |
| 1510system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 1473system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1474system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1475system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1476system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1477system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1478system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1479system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1480system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1494system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1495system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1496system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1497system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1498system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1499system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1500system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1501system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1511system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1512system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1513system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1514system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1515system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1516system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1517system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1518system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1532system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1533system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1534system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1535system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1536system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1537system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1538system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1539system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1540system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 1502system.cpu1.itb.walker.walks 62177 # Table walker walks requested 1503system.cpu1.itb.walker.walksLong 62177 # Table walker walks initiated with long descriptors 1504system.cpu1.itb.walker.walksLongTerminationLevel::Level2 630 # Level at which table walker walks with long descriptors terminate 1505system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54596 # Level at which table walker walks with long descriptors terminate 1506system.cpu1.itb.walker.walkWaitTime::samples 62177 # Table walker wait (enqueue to first request) latency 1507system.cpu1.itb.walker.walkWaitTime::0 62177 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1508system.cpu1.itb.walker.walkWaitTime::total 62177 # Table walker wait (enqueue to first request) latency 1509system.cpu1.itb.walker.walkCompletionTime::samples 55226 # Table walker service (enqueue to completion) latency --- 44 unchanged lines hidden (view full) --- 1554system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1555system.cpu1.itb.perms_faults 167002 # Number of TLB faults due to permissions restrictions 1556system.cpu1.itb.read_accesses 0 # DTB read accesses 1557system.cpu1.itb.write_accesses 0 # DTB write accesses 1558system.cpu1.itb.inst_accesses 219399751 # ITB inst accesses 1559system.cpu1.itb.hits 219337574 # DTB hits 1560system.cpu1.itb.misses 62177 # DTB misses 1561system.cpu1.itb.accesses 219399751 # DTB accesses | 1541system.cpu1.itb.walker.walks 62177 # Table walker walks requested 1542system.cpu1.itb.walker.walksLong 62177 # Table walker walks initiated with long descriptors 1543system.cpu1.itb.walker.walksLongTerminationLevel::Level2 630 # Level at which table walker walks with long descriptors terminate 1544system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54596 # Level at which table walker walks with long descriptors terminate 1545system.cpu1.itb.walker.walkWaitTime::samples 62177 # Table walker wait (enqueue to first request) latency 1546system.cpu1.itb.walker.walkWaitTime::0 62177 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1547system.cpu1.itb.walker.walkWaitTime::total 62177 # Table walker wait (enqueue to first request) latency 1548system.cpu1.itb.walker.walkCompletionTime::samples 55226 # Table walker service (enqueue to completion) latency --- 44 unchanged lines hidden (view full) --- 1593system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1594system.cpu1.itb.perms_faults 167002 # Number of TLB faults due to permissions restrictions 1595system.cpu1.itb.read_accesses 0 # DTB read accesses 1596system.cpu1.itb.write_accesses 0 # DTB write accesses 1597system.cpu1.itb.inst_accesses 219399751 # ITB inst accesses 1598system.cpu1.itb.hits 219337574 # DTB hits 1599system.cpu1.itb.misses 62177 # DTB misses 1600system.cpu1.itb.accesses 219399751 # DTB accesses |
| 1601system.cpu1.numPwrStateTransitions 10996 # Number of power state transitions 1602system.cpu1.pwrStateClkGateDist::samples 5498 # Distribution of time spent in the clock gated state 1603system.cpu1.pwrStateClkGateDist::mean 8537078490.682248 # Distribution of time spent in the clock gated state 1604system.cpu1.pwrStateClkGateDist::stdev 139542991677.263855 # Distribution of time spent in the clock gated state 1605system.cpu1.pwrStateClkGateDist::underflows 3923 71.35% 71.35% # Distribution of time spent in the clock gated state 1606system.cpu1.pwrStateClkGateDist::1000-5e+10 1550 28.19% 99.55% # Distribution of time spent in the clock gated state 1607system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.02% 99.56% # Distribution of time spent in the clock gated state 1608system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 5 0.09% 99.65% # Distribution of time spent in the clock gated state 1609system.cpu1.pwrStateClkGateDist::3e+11-3.5e+11 2 0.04% 99.69% # Distribution of time spent in the clock gated state 1610system.cpu1.pwrStateClkGateDist::5.5e+11-6e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state 1611system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state 1612system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state 1613system.cpu1.pwrStateClkGateDist::overflows 14 0.25% 100.00% # Distribution of time spent in the clock gated state 1614system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 1615system.cpu1.pwrStateClkGateDist::max_value 7470355729396 # Distribution of time spent in the clock gated state 1616system.cpu1.pwrStateClkGateDist::total 5498 # Distribution of time spent in the clock gated state 1617system.cpu1.pwrStateResidencyTicks::ON 419045786229 # Cumulative time (in ticks) in various power states 1618system.cpu1.pwrStateResidencyTicks::CLK_GATED 46936857541771 # Cumulative time (in ticks) in various power states |
|
| 1562system.cpu1.numCycles 838096745 # number of cpu cycles simulated 1563system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1564system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1565system.cpu1.committedInsts 400342475 # Number of instructions committed 1566system.cpu1.committedOps 472062345 # Number of ops (including micro ops) committed 1567system.cpu1.discardedOps 44700411 # Number of ops (including micro ops) which were discarded before commit 1568system.cpu1.numFetchSuspends 5381 # Number of times Execute suspended instruction fetching 1569system.cpu1.quiesceCycles 93874475142 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt --- 33 unchanged lines hidden (view full) --- 1603system.cpu1.op_class_0::MemWrite 69244510 14.67% 100.00% # Class of committed instruction 1604system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1605system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1606system.cpu1.op_class_0::total 472062345 # Class of committed instruction 1607system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1608system.cpu1.kern.inst.quiesce 5498 # number of quiesce instructions executed 1609system.cpu1.tickCycles 657140254 # Number of cycles that the object actually ticked 1610system.cpu1.idleCycles 180956491 # Total number of cycles that the object has spent stopped | 1619system.cpu1.numCycles 838096745 # number of cpu cycles simulated 1620system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1621system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1622system.cpu1.committedInsts 400342475 # Number of instructions committed 1623system.cpu1.committedOps 472062345 # Number of ops (including micro ops) committed 1624system.cpu1.discardedOps 44700411 # Number of ops (including micro ops) which were discarded before commit 1625system.cpu1.numFetchSuspends 5381 # Number of times Execute suspended instruction fetching 1626system.cpu1.quiesceCycles 93874475142 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt --- 33 unchanged lines hidden (view full) --- 1660system.cpu1.op_class_0::MemWrite 69244510 14.67% 100.00% # Class of committed instruction 1661system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1662system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 1663system.cpu1.op_class_0::total 472062345 # Class of committed instruction 1664system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1665system.cpu1.kern.inst.quiesce 5498 # number of quiesce instructions executed 1666system.cpu1.tickCycles 657140254 # Number of cycles that the object actually ticked 1667system.cpu1.idleCycles 180956491 # Total number of cycles that the object has spent stopped |
| 1668system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 1611system.cpu1.dcache.tags.replacements 4810857 # number of replacements 1612system.cpu1.dcache.tags.tagsinuse 458.623346 # Cycle average of tags in use 1613system.cpu1.dcache.tags.total_refs 140763490 # Total number of references to valid blocks. 1614system.cpu1.dcache.tags.sampled_refs 4811366 # Sample count of references to valid blocks. 1615system.cpu1.dcache.tags.avg_refs 29.256450 # Average number of references to valid blocks. 1616system.cpu1.dcache.tags.warmup_cycle 8377530544000 # Cycle when the warmup percentage was hit. 1617system.cpu1.dcache.tags.occ_blocks::cpu1.data 458.623346 # Average occupied blocks per requestor 1618system.cpu1.dcache.tags.occ_percent::cpu1.data 0.895749 # Average percentage of cache occupancy 1619system.cpu1.dcache.tags.occ_percent::total 0.895749 # Average percentage of cache occupancy 1620system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id 1621system.cpu1.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1622system.cpu1.dcache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id 1623system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id 1624system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id 1625system.cpu1.dcache.tags.tag_accesses 298669128 # Number of tag accesses 1626system.cpu1.dcache.tags.data_accesses 298669128 # Number of data accesses | 1669system.cpu1.dcache.tags.replacements 4810857 # number of replacements 1670system.cpu1.dcache.tags.tagsinuse 458.623346 # Cycle average of tags in use 1671system.cpu1.dcache.tags.total_refs 140763490 # Total number of references to valid blocks. 1672system.cpu1.dcache.tags.sampled_refs 4811366 # Sample count of references to valid blocks. 1673system.cpu1.dcache.tags.avg_refs 29.256450 # Average number of references to valid blocks. 1674system.cpu1.dcache.tags.warmup_cycle 8377530544000 # Cycle when the warmup percentage was hit. 1675system.cpu1.dcache.tags.occ_blocks::cpu1.data 458.623346 # Average occupied blocks per requestor 1676system.cpu1.dcache.tags.occ_percent::cpu1.data 0.895749 # Average percentage of cache occupancy 1677system.cpu1.dcache.tags.occ_percent::total 0.895749 # Average percentage of cache occupancy 1678system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id 1679system.cpu1.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1680system.cpu1.dcache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id 1681system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id 1682system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id 1683system.cpu1.dcache.tags.tag_accesses 298669128 # Number of tag accesses 1684system.cpu1.dcache.tags.data_accesses 298669128 # Number of data accesses |
| 1685system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 1627system.cpu1.dcache.ReadReq_hits::cpu1.data 72030058 # number of ReadReq hits 1628system.cpu1.dcache.ReadReq_hits::total 72030058 # number of ReadReq hits 1629system.cpu1.dcache.WriteReq_hits::cpu1.data 64877267 # number of WriteReq hits 1630system.cpu1.dcache.WriteReq_hits::total 64877267 # number of WriteReq hits 1631system.cpu1.dcache.SoftPFReq_hits::cpu1.data 197389 # number of SoftPFReq hits 1632system.cpu1.dcache.SoftPFReq_hits::total 197389 # number of SoftPFReq hits 1633system.cpu1.dcache.WriteLineReq_hits::cpu1.data 40268 # number of WriteLineReq hits 1634system.cpu1.dcache.WriteLineReq_hits::total 40268 # number of WriteLineReq hits --- 184 unchanged lines hidden (view full) --- 1819system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15880.928497 # average overall mshr miss latency 1820system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15880.928497 # average overall mshr miss latency 1821system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16712.041426 # average overall mshr miss latency 1822system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16712.041426 # average overall mshr miss latency 1823system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 120622.748883 # average ReadReq mshr uncacheable latency 1824system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 120622.748883 # average ReadReq mshr uncacheable latency 1825system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 58873.672738 # average overall mshr uncacheable latency 1826system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 58873.672738 # average overall mshr uncacheable latency | 1686system.cpu1.dcache.ReadReq_hits::cpu1.data 72030058 # number of ReadReq hits 1687system.cpu1.dcache.ReadReq_hits::total 72030058 # number of ReadReq hits 1688system.cpu1.dcache.WriteReq_hits::cpu1.data 64877267 # number of WriteReq hits 1689system.cpu1.dcache.WriteReq_hits::total 64877267 # number of WriteReq hits 1690system.cpu1.dcache.SoftPFReq_hits::cpu1.data 197389 # number of SoftPFReq hits 1691system.cpu1.dcache.SoftPFReq_hits::total 197389 # number of SoftPFReq hits 1692system.cpu1.dcache.WriteLineReq_hits::cpu1.data 40268 # number of WriteLineReq hits 1693system.cpu1.dcache.WriteLineReq_hits::total 40268 # number of WriteLineReq hits --- 184 unchanged lines hidden (view full) --- 1878system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15880.928497 # average overall mshr miss latency 1879system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15880.928497 # average overall mshr miss latency 1880system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16712.041426 # average overall mshr miss latency 1881system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16712.041426 # average overall mshr miss latency 1882system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 120622.748883 # average ReadReq mshr uncacheable latency 1883system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 120622.748883 # average ReadReq mshr uncacheable latency 1884system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 58873.672738 # average overall mshr uncacheable latency 1885system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 58873.672738 # average overall mshr uncacheable latency |
| 1886system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 1827system.cpu1.icache.tags.replacements 8744967 # number of replacements 1828system.cpu1.icache.tags.tagsinuse 507.224680 # Cycle average of tags in use 1829system.cpu1.icache.tags.total_refs 210419103 # Total number of references to valid blocks. 1830system.cpu1.icache.tags.sampled_refs 8745479 # Sample count of references to valid blocks. 1831system.cpu1.icache.tags.avg_refs 24.060329 # Average number of references to valid blocks. 1832system.cpu1.icache.tags.warmup_cycle 8367967785000 # Cycle when the warmup percentage was hit. 1833system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.224680 # Average occupied blocks per requestor 1834system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990673 # Average percentage of cache occupancy 1835system.cpu1.icache.tags.occ_percent::total 0.990673 # Average percentage of cache occupancy 1836system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1837system.cpu1.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 1838system.cpu1.icache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id 1839system.cpu1.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id 1840system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1841system.cpu1.icache.tags.tag_accesses 447074643 # Number of tag accesses 1842system.cpu1.icache.tags.data_accesses 447074643 # Number of data accesses | 1887system.cpu1.icache.tags.replacements 8744967 # number of replacements 1888system.cpu1.icache.tags.tagsinuse 507.224680 # Cycle average of tags in use 1889system.cpu1.icache.tags.total_refs 210419103 # Total number of references to valid blocks. 1890system.cpu1.icache.tags.sampled_refs 8745479 # Sample count of references to valid blocks. 1891system.cpu1.icache.tags.avg_refs 24.060329 # Average number of references to valid blocks. 1892system.cpu1.icache.tags.warmup_cycle 8367967785000 # Cycle when the warmup percentage was hit. 1893system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.224680 # Average occupied blocks per requestor 1894system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990673 # Average percentage of cache occupancy 1895system.cpu1.icache.tags.occ_percent::total 0.990673 # Average percentage of cache occupancy 1896system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1897system.cpu1.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 1898system.cpu1.icache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id 1899system.cpu1.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id 1900system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1901system.cpu1.icache.tags.tag_accesses 447074643 # Number of tag accesses 1902system.cpu1.icache.tags.data_accesses 447074643 # Number of data accesses |
| 1903system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 1843system.cpu1.icache.ReadReq_hits::cpu1.inst 210419103 # number of ReadReq hits 1844system.cpu1.icache.ReadReq_hits::total 210419103 # number of ReadReq hits 1845system.cpu1.icache.demand_hits::cpu1.inst 210419103 # number of demand (read+write) hits 1846system.cpu1.icache.demand_hits::total 210419103 # number of demand (read+write) hits 1847system.cpu1.icache.overall_hits::cpu1.inst 210419103 # number of overall hits 1848system.cpu1.icache.overall_hits::total 210419103 # number of overall hits 1849system.cpu1.icache.ReadReq_misses::cpu1.inst 8745479 # number of ReadReq misses 1850system.cpu1.icache.ReadReq_misses::total 8745479 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 1915system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average overall mshr miss latency 1916system.cpu1.icache.demand_avg_mshr_miss_latency::total 9593.006284 # average overall mshr miss latency 1917system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average overall mshr miss latency 1918system.cpu1.icache.overall_avg_mshr_miss_latency::total 9593.006284 # average overall mshr miss latency 1919system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average ReadReq mshr uncacheable latency 1920system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90860.215054 # average ReadReq mshr uncacheable latency 1921system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average overall mshr uncacheable latency 1922system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90860.215054 # average overall mshr uncacheable latency | 1904system.cpu1.icache.ReadReq_hits::cpu1.inst 210419103 # number of ReadReq hits 1905system.cpu1.icache.ReadReq_hits::total 210419103 # number of ReadReq hits 1906system.cpu1.icache.demand_hits::cpu1.inst 210419103 # number of demand (read+write) hits 1907system.cpu1.icache.demand_hits::total 210419103 # number of demand (read+write) hits 1908system.cpu1.icache.overall_hits::cpu1.inst 210419103 # number of overall hits 1909system.cpu1.icache.overall_hits::total 210419103 # number of overall hits 1910system.cpu1.icache.ReadReq_misses::cpu1.inst 8745479 # number of ReadReq misses 1911system.cpu1.icache.ReadReq_misses::total 8745479 # number of ReadReq misses --- 64 unchanged lines hidden (view full) --- 1976system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average overall mshr miss latency 1977system.cpu1.icache.demand_avg_mshr_miss_latency::total 9593.006284 # average overall mshr miss latency 1978system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average overall mshr miss latency 1979system.cpu1.icache.overall_avg_mshr_miss_latency::total 9593.006284 # average overall mshr miss latency 1980system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average ReadReq mshr uncacheable latency 1981system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90860.215054 # average ReadReq mshr uncacheable latency 1982system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average overall mshr uncacheable latency 1983system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90860.215054 # average overall mshr uncacheable latency |
| 1984system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 1923system.cpu1.l2cache.prefetcher.num_hwpf_issued 6641051 # number of hwpf issued 1924system.cpu1.l2cache.prefetcher.pfIdentified 6641093 # number of prefetch candidates identified 1925system.cpu1.l2cache.prefetcher.pfBufferHit 36 # number of redundant prefetches already in prefetch queue 1926system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1927system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1928system.cpu1.l2cache.prefetcher.pfSpanPage 796339 # number of prefetches not generated due to page crossing | 1985system.cpu1.l2cache.prefetcher.num_hwpf_issued 6641051 # number of hwpf issued 1986system.cpu1.l2cache.prefetcher.pfIdentified 6641093 # number of prefetch candidates identified 1987system.cpu1.l2cache.prefetcher.pfBufferHit 36 # number of redundant prefetches already in prefetch queue 1988system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1989system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1990system.cpu1.l2cache.prefetcher.pfSpanPage 796339 # number of prefetches not generated due to page crossing |
| 1991system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 1929system.cpu1.l2cache.tags.replacements 2218428 # number of replacements 1930system.cpu1.l2cache.tags.tagsinuse 13419.558556 # Cycle average of tags in use 1931system.cpu1.l2cache.tags.total_refs 21617433 # Total number of references to valid blocks. 1932system.cpu1.l2cache.tags.sampled_refs 2233865 # Sample count of references to valid blocks. 1933system.cpu1.l2cache.tags.avg_refs 9.677144 # Average number of references to valid blocks. 1934system.cpu1.l2cache.tags.warmup_cycle 10005238958500 # Cycle when the warmup percentage was hit. 1935system.cpu1.l2cache.tags.occ_blocks::writebacks 12516.094704 # Average occupied blocks per requestor 1936system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 63.377354 # Average occupied blocks per requestor --- 19 unchanged lines hidden (view full) --- 1956system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4872 # Occupied blocks per task id 1957system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6319 # Occupied blocks per task id 1958system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2682 # Occupied blocks per task id 1959system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.072754 # Percentage of cache occupancy per task id 1960system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004944 # Percentage of cache occupancy per task id 1961system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.864502 # Percentage of cache occupancy per task id 1962system.cpu1.l2cache.tags.tag_accesses 457671450 # Number of tag accesses 1963system.cpu1.l2cache.tags.data_accesses 457671450 # Number of data accesses | 1992system.cpu1.l2cache.tags.replacements 2218428 # number of replacements 1993system.cpu1.l2cache.tags.tagsinuse 13419.558556 # Cycle average of tags in use 1994system.cpu1.l2cache.tags.total_refs 21617433 # Total number of references to valid blocks. 1995system.cpu1.l2cache.tags.sampled_refs 2233865 # Sample count of references to valid blocks. 1996system.cpu1.l2cache.tags.avg_refs 9.677144 # Average number of references to valid blocks. 1997system.cpu1.l2cache.tags.warmup_cycle 10005238958500 # Cycle when the warmup percentage was hit. 1998system.cpu1.l2cache.tags.occ_blocks::writebacks 12516.094704 # Average occupied blocks per requestor 1999system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 63.377354 # Average occupied blocks per requestor --- 19 unchanged lines hidden (view full) --- 2019system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4872 # Occupied blocks per task id 2020system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6319 # Occupied blocks per task id 2021system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2682 # Occupied blocks per task id 2022system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.072754 # Percentage of cache occupancy per task id 2023system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004944 # Percentage of cache occupancy per task id 2024system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.864502 # Percentage of cache occupancy per task id 2025system.cpu1.l2cache.tags.tag_accesses 457671450 # Number of tag accesses 2026system.cpu1.l2cache.tags.data_accesses 457671450 # Number of data accesses |
| 2027system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 1964system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 494400 # number of ReadReq hits 1965system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 160613 # number of ReadReq hits 1966system.cpu1.l2cache.ReadReq_hits::total 655013 # number of ReadReq hits 1967system.cpu1.l2cache.WritebackDirty_hits::writebacks 3026488 # number of WritebackDirty hits 1968system.cpu1.l2cache.WritebackDirty_hits::total 3026488 # number of WritebackDirty hits 1969system.cpu1.l2cache.WritebackClean_hits::writebacks 10527430 # number of WritebackClean hits 1970system.cpu1.l2cache.WritebackClean_hits::total 10527430 # number of WritebackClean hits 1971system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 434 # number of UpgradeReq hits --- 340 unchanged lines hidden (view full) --- 2312system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 54961.043527 # average overall mshr uncacheable latency 2313system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 55142.308230 # average overall mshr uncacheable latency 2314system.cpu1.toL2Bus.snoop_filter.tot_requests 27911552 # Total number of requests made to the snoop filter. 2315system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14263179 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2316system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2317system.cpu1.toL2Bus.snoop_filter.tot_snoops 2035614 # Total number of snoops made to the snoop filter. 2318system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2035313 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2319system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 2028system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 494400 # number of ReadReq hits 2029system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 160613 # number of ReadReq hits 2030system.cpu1.l2cache.ReadReq_hits::total 655013 # number of ReadReq hits 2031system.cpu1.l2cache.WritebackDirty_hits::writebacks 3026488 # number of WritebackDirty hits 2032system.cpu1.l2cache.WritebackDirty_hits::total 3026488 # number of WritebackDirty hits 2033system.cpu1.l2cache.WritebackClean_hits::writebacks 10527430 # number of WritebackClean hits 2034system.cpu1.l2cache.WritebackClean_hits::total 10527430 # number of WritebackClean hits 2035system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 434 # number of UpgradeReq hits --- 340 unchanged lines hidden (view full) --- 2376system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 54961.043527 # average overall mshr uncacheable latency 2377system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 55142.308230 # average overall mshr uncacheable latency 2378system.cpu1.toL2Bus.snoop_filter.tot_requests 27911552 # Total number of requests made to the snoop filter. 2379system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14263179 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2380system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2381system.cpu1.toL2Bus.snoop_filter.tot_snoops 2035614 # Total number of snoops made to the snoop filter. 2382system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2035313 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2383system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 2384system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 2320system.cpu1.toL2Bus.trans_dist::ReadReq 755700 # Transaction distribution 2321system.cpu1.toL2Bus.trans_dist::ReadResp 13030335 # Transaction distribution 2322system.cpu1.toL2Bus.trans_dist::WriteReq 7280 # Transaction distribution 2323system.cpu1.toL2Bus.trans_dist::WriteResp 7280 # Transaction distribution 2324system.cpu1.toL2Bus.trans_dist::WritebackDirty 4134671 # Transaction distribution 2325system.cpu1.toL2Bus.trans_dist::WritebackClean 10529340 # Transaction distribution 2326system.cpu1.toL2Bus.trans_dist::CleanEvict 2783515 # Transaction distribution 2327system.cpu1.toL2Bus.trans_dist::HardPFReq 903944 # Transaction distribution --- 38 unchanged lines hidden (view full) --- 2366system.cpu1.toL2Bus.respLayer0.occupancy 13121677843 # Layer occupancy (ticks) 2367system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2368system.cpu1.toL2Bus.respLayer1.occupancy 7163335235 # Layer occupancy (ticks) 2369system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2370system.cpu1.toL2Bus.respLayer2.occupancy 185802393 # Layer occupancy (ticks) 2371system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2372system.cpu1.toL2Bus.respLayer3.occupancy 563017795 # Layer occupancy (ticks) 2373system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2385system.cpu1.toL2Bus.trans_dist::ReadReq 755700 # Transaction distribution 2386system.cpu1.toL2Bus.trans_dist::ReadResp 13030335 # Transaction distribution 2387system.cpu1.toL2Bus.trans_dist::WriteReq 7280 # Transaction distribution 2388system.cpu1.toL2Bus.trans_dist::WriteResp 7280 # Transaction distribution 2389system.cpu1.toL2Bus.trans_dist::WritebackDirty 4134671 # Transaction distribution 2390system.cpu1.toL2Bus.trans_dist::WritebackClean 10529340 # Transaction distribution 2391system.cpu1.toL2Bus.trans_dist::CleanEvict 2783515 # Transaction distribution 2392system.cpu1.toL2Bus.trans_dist::HardPFReq 903944 # Transaction distribution --- 38 unchanged lines hidden (view full) --- 2431system.cpu1.toL2Bus.respLayer0.occupancy 13121677843 # Layer occupancy (ticks) 2432system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2433system.cpu1.toL2Bus.respLayer1.occupancy 7163335235 # Layer occupancy (ticks) 2434system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2435system.cpu1.toL2Bus.respLayer2.occupancy 185802393 # Layer occupancy (ticks) 2436system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2437system.cpu1.toL2Bus.respLayer3.occupancy 563017795 # Layer occupancy (ticks) 2438system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2439system.iobus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 2374system.iobus.trans_dist::ReadReq 40337 # Transaction distribution 2375system.iobus.trans_dist::ReadResp 40337 # Transaction distribution 2376system.iobus.trans_dist::WriteReq 136616 # Transaction distribution 2377system.iobus.trans_dist::WriteResp 136616 # Transaction distribution 2378system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47664 # Packet count per connected master and slave (bytes) 2379system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2380system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2381system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) --- 60 unchanged lines hidden (view full) --- 2442system.iobus.reqLayer25.occupancy 569469754 # Layer occupancy (ticks) 2443system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2444system.iobus.respLayer0.occupancy 92713000 # Layer occupancy (ticks) 2445system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2446system.iobus.respLayer3.occupancy 147924000 # Layer occupancy (ticks) 2447system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2448system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2449system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) | 2440system.iobus.trans_dist::ReadReq 40337 # Transaction distribution 2441system.iobus.trans_dist::ReadResp 40337 # Transaction distribution 2442system.iobus.trans_dist::WriteReq 136616 # Transaction distribution 2443system.iobus.trans_dist::WriteResp 136616 # Transaction distribution 2444system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47664 # Packet count per connected master and slave (bytes) 2445system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2446system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2447system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) --- 60 unchanged lines hidden (view full) --- 2508system.iobus.reqLayer25.occupancy 569469754 # Layer occupancy (ticks) 2509system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2510system.iobus.respLayer0.occupancy 92713000 # Layer occupancy (ticks) 2511system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2512system.iobus.respLayer3.occupancy 147924000 # Layer occupancy (ticks) 2513system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2514system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2515system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) |
| 2516system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 2450system.iocache.tags.replacements 115611 # number of replacements 2451system.iocache.tags.tagsinuse 11.284790 # Cycle average of tags in use 2452system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2453system.iocache.tags.sampled_refs 115627 # Sample count of references to valid blocks. 2454system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2455system.iocache.tags.warmup_cycle 9167417766000 # Cycle when the warmup percentage was hit. 2456system.iocache.tags.occ_blocks::realview.ethernet 7.418888 # Average occupied blocks per requestor 2457system.iocache.tags.occ_blocks::realview.ide 3.865902 # Average occupied blocks per requestor 2458system.iocache.tags.occ_percent::realview.ethernet 0.463681 # Average percentage of cache occupancy 2459system.iocache.tags.occ_percent::realview.ide 0.241619 # Average percentage of cache occupancy 2460system.iocache.tags.occ_percent::total 0.705299 # Average percentage of cache occupancy 2461system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2462system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2463system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2464system.iocache.tags.tag_accesses 1040883 # Number of tag accesses 2465system.iocache.tags.data_accesses 1040883 # Number of data accesses | 2517system.iocache.tags.replacements 115611 # number of replacements 2518system.iocache.tags.tagsinuse 11.284790 # Cycle average of tags in use 2519system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2520system.iocache.tags.sampled_refs 115627 # Sample count of references to valid blocks. 2521system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2522system.iocache.tags.warmup_cycle 9167417766000 # Cycle when the warmup percentage was hit. 2523system.iocache.tags.occ_blocks::realview.ethernet 7.418888 # Average occupied blocks per requestor 2524system.iocache.tags.occ_blocks::realview.ide 3.865902 # Average occupied blocks per requestor 2525system.iocache.tags.occ_percent::realview.ethernet 0.463681 # Average percentage of cache occupancy 2526system.iocache.tags.occ_percent::realview.ide 0.241619 # Average percentage of cache occupancy 2527system.iocache.tags.occ_percent::total 0.705299 # Average percentage of cache occupancy 2528system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2529system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2530system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2531system.iocache.tags.tag_accesses 1040883 # Number of tag accesses 2532system.iocache.tags.data_accesses 1040883 # Number of data accesses |
| 2533system.iocache.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 2466system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2467system.iocache.ReadReq_misses::realview.ide 8886 # number of ReadReq misses 2468system.iocache.ReadReq_misses::total 8923 # number of ReadReq misses 2469system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2470system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2471system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 2472system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 2473system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses --- 109 unchanged lines hidden (view full) --- 2583system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70391.738204 # average WriteLineReq mshr miss latency 2584system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70391.738204 # average WriteLineReq mshr miss latency 2585system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 2586system.iocache.demand_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency 2587system.iocache.demand_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency 2588system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 2589system.iocache.overall_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency 2590system.iocache.overall_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency | 2534system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2535system.iocache.ReadReq_misses::realview.ide 8886 # number of ReadReq misses 2536system.iocache.ReadReq_misses::total 8923 # number of ReadReq misses 2537system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2538system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2539system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 2540system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 2541system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses --- 109 unchanged lines hidden (view full) --- 2651system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70391.738204 # average WriteLineReq mshr miss latency 2652system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70391.738204 # average WriteLineReq mshr miss latency 2653system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 2654system.iocache.demand_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency 2655system.iocache.demand_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency 2656system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 2657system.iocache.overall_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency 2658system.iocache.overall_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency |
| 2659system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 2591system.l2c.tags.replacements 1371243 # number of replacements 2592system.l2c.tags.tagsinuse 63411.869664 # Cycle average of tags in use 2593system.l2c.tags.total_refs 6460055 # Total number of references to valid blocks. 2594system.l2c.tags.sampled_refs 1430877 # Sample count of references to valid blocks. 2595system.l2c.tags.avg_refs 4.514752 # Average number of references to valid blocks. 2596system.l2c.tags.warmup_cycle 7876910500 # Cycle when the warmup percentage was hit. 2597system.l2c.tags.occ_blocks::writebacks 21329.379338 # Average occupied blocks per requestor 2598system.l2c.tags.occ_blocks::cpu0.dtb.walker 243.549056 # Average occupied blocks per requestor --- 32 unchanged lines hidden (view full) --- 2631system.l2c.tags.age_task_id_blocks_1024::2 1961 # Occupied blocks per task id 2632system.l2c.tags.age_task_id_blocks_1024::3 5894 # Occupied blocks per task id 2633system.l2c.tags.age_task_id_blocks_1024::4 42105 # Occupied blocks per task id 2634system.l2c.tags.occ_task_id_percent::1022 0.140717 # Percentage of cache occupancy per task id 2635system.l2c.tags.occ_task_id_percent::1023 0.003891 # Percentage of cache occupancy per task id 2636system.l2c.tags.occ_task_id_percent::1024 0.765335 # Percentage of cache occupancy per task id 2637system.l2c.tags.tag_accesses 79235647 # Number of tag accesses 2638system.l2c.tags.data_accesses 79235647 # Number of data accesses | 2660system.l2c.tags.replacements 1371243 # number of replacements 2661system.l2c.tags.tagsinuse 63411.869664 # Cycle average of tags in use 2662system.l2c.tags.total_refs 6460055 # Total number of references to valid blocks. 2663system.l2c.tags.sampled_refs 1430877 # Sample count of references to valid blocks. 2664system.l2c.tags.avg_refs 4.514752 # Average number of references to valid blocks. 2665system.l2c.tags.warmup_cycle 7876910500 # Cycle when the warmup percentage was hit. 2666system.l2c.tags.occ_blocks::writebacks 21329.379338 # Average occupied blocks per requestor 2667system.l2c.tags.occ_blocks::cpu0.dtb.walker 243.549056 # Average occupied blocks per requestor --- 32 unchanged lines hidden (view full) --- 2700system.l2c.tags.age_task_id_blocks_1024::2 1961 # Occupied blocks per task id 2701system.l2c.tags.age_task_id_blocks_1024::3 5894 # Occupied blocks per task id 2702system.l2c.tags.age_task_id_blocks_1024::4 42105 # Occupied blocks per task id 2703system.l2c.tags.occ_task_id_percent::1022 0.140717 # Percentage of cache occupancy per task id 2704system.l2c.tags.occ_task_id_percent::1023 0.003891 # Percentage of cache occupancy per task id 2705system.l2c.tags.occ_task_id_percent::1024 0.765335 # Percentage of cache occupancy per task id 2706system.l2c.tags.tag_accesses 79235647 # Number of tag accesses 2707system.l2c.tags.data_accesses 79235647 # Number of data accesses |
| 2708system.l2c.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 2639system.l2c.WritebackDirty_hits::writebacks 2747527 # number of WritebackDirty hits 2640system.l2c.WritebackDirty_hits::total 2747527 # number of WritebackDirty hits 2641system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 2642system.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits 2643system.l2c.UpgradeReq_hits::cpu0.data 170119 # number of UpgradeReq hits 2644system.l2c.UpgradeReq_hits::cpu1.data 132427 # number of UpgradeReq hits 2645system.l2c.UpgradeReq_hits::total 302546 # number of UpgradeReq hits 2646system.l2c.SCUpgradeReq_hits::cpu0.data 41747 # number of SCUpgradeReq hits --- 508 unchanged lines hidden (view full) --- 3155system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 46177.192630 # average overall mshr uncacheable latency 3156system.l2c.overall_avg_mshr_uncacheable_latency::total 71756.492357 # average overall mshr uncacheable latency 3157system.membus.snoop_filter.tot_requests 3789204 # Total number of requests made to the snoop filter. 3158system.membus.snoop_filter.hit_single_requests 2296931 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3159system.membus.snoop_filter.hit_multi_requests 2908 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3160system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3161system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3162system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 2709system.l2c.WritebackDirty_hits::writebacks 2747527 # number of WritebackDirty hits 2710system.l2c.WritebackDirty_hits::total 2747527 # number of WritebackDirty hits 2711system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 2712system.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits 2713system.l2c.UpgradeReq_hits::cpu0.data 170119 # number of UpgradeReq hits 2714system.l2c.UpgradeReq_hits::cpu1.data 132427 # number of UpgradeReq hits 2715system.l2c.UpgradeReq_hits::total 302546 # number of UpgradeReq hits 2716system.l2c.SCUpgradeReq_hits::cpu0.data 41747 # number of SCUpgradeReq hits --- 508 unchanged lines hidden (view full) --- 3225system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 46177.192630 # average overall mshr uncacheable latency 3226system.l2c.overall_avg_mshr_uncacheable_latency::total 71756.492357 # average overall mshr uncacheable latency 3227system.membus.snoop_filter.tot_requests 3789204 # Total number of requests made to the snoop filter. 3228system.membus.snoop_filter.hit_single_requests 2296931 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3229system.membus.snoop_filter.hit_multi_requests 2908 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3230system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3231system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3232system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 3233system.membus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 3163system.membus.trans_dist::ReadReq 91033 # Transaction distribution 3164system.membus.trans_dist::ReadResp 892432 # Transaction distribution 3165system.membus.trans_dist::WriteReq 38505 # Transaction distribution 3166system.membus.trans_dist::WriteResp 38505 # Transaction distribution 3167system.membus.trans_dist::WritebackDirty 1181777 # Transaction distribution 3168system.membus.trans_dist::CleanEvict 252869 # Transaction distribution 3169system.membus.trans_dist::UpgradeReq 437143 # Transaction distribution 3170system.membus.trans_dist::SCUpgradeReq 308404 # Transaction distribution --- 38 unchanged lines hidden (view full) --- 3209system.membus.reqLayer2.occupancy 22316500 # Layer occupancy (ticks) 3210system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3211system.membus.reqLayer5.occupancy 8304045809 # Layer occupancy (ticks) 3212system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3213system.membus.respLayer2.occupancy 5231778477 # Layer occupancy (ticks) 3214system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3215system.membus.respLayer3.occupancy 45499333 # Layer occupancy (ticks) 3216system.membus.respLayer3.utilization 0.0 # Layer utilization (%) | 3234system.membus.trans_dist::ReadReq 91033 # Transaction distribution 3235system.membus.trans_dist::ReadResp 892432 # Transaction distribution 3236system.membus.trans_dist::WriteReq 38505 # Transaction distribution 3237system.membus.trans_dist::WriteResp 38505 # Transaction distribution 3238system.membus.trans_dist::WritebackDirty 1181777 # Transaction distribution 3239system.membus.trans_dist::CleanEvict 252869 # Transaction distribution 3240system.membus.trans_dist::UpgradeReq 437143 # Transaction distribution 3241system.membus.trans_dist::SCUpgradeReq 308404 # Transaction distribution --- 38 unchanged lines hidden (view full) --- 3280system.membus.reqLayer2.occupancy 22316500 # Layer occupancy (ticks) 3281system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3282system.membus.reqLayer5.occupancy 8304045809 # Layer occupancy (ticks) 3283system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3284system.membus.respLayer2.occupancy 5231778477 # Layer occupancy (ticks) 3285system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3286system.membus.respLayer3.occupancy 45499333 # Layer occupancy (ticks) 3287system.membus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 3288system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3289system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3290system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3291system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3292system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3293system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3294system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 3217system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3218system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3219system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3220system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3221system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3222system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks | 3295system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3296system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3297system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3298system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3299system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3300system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks |
| 3301system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3302system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 3223system.realview.ethernet.txBytes 966 # Bytes Transmitted 3224system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3225system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3226system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3227system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3228system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3229system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3230system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA --- 26 unchanged lines hidden (view full) --- 3257system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3258system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3259system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3260system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3261system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3262system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3263system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3264system.realview.ethernet.droppedPackets 0 # number of packets dropped | 3303system.realview.ethernet.txBytes 966 # Bytes Transmitted 3304system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3305system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3306system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3307system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3308system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3309system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3310system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA --- 26 unchanged lines hidden (view full) --- 3337system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3338system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3339system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3340system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3341system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3342system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3343system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3344system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 3345system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3346system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3347system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3348system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3349system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3350system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3351system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 3265system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3266system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3267system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3268system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 3352system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3353system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3354system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3355system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 3356system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3357system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3358system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3359system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3360system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3361system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3362system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3363system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3364system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3365system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3366system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states 3367system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 3269system.toL2Bus.snoop_filter.tot_requests 12326432 # Total number of requests made to the snoop filter. 3270system.toL2Bus.snoop_filter.hit_single_requests 6670511 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3271system.toL2Bus.snoop_filter.hit_multi_requests 2086069 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3272system.toL2Bus.snoop_filter.tot_snoops 130580 # Total number of snoops made to the snoop filter. 3273system.toL2Bus.snoop_filter.hit_single_snoops 118652 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3274system.toL2Bus.snoop_filter.hit_multi_snoops 11928 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 3368system.toL2Bus.snoop_filter.tot_requests 12326432 # Total number of requests made to the snoop filter. 3369system.toL2Bus.snoop_filter.hit_single_requests 6670511 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3370system.toL2Bus.snoop_filter.hit_multi_requests 2086069 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3371system.toL2Bus.snoop_filter.tot_snoops 130580 # Total number of snoops made to the snoop filter. 3372system.toL2Bus.snoop_filter.hit_single_snoops 118652 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3373system.toL2Bus.snoop_filter.hit_multi_snoops 11928 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 3374system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47355903328000 # Cumulative time (in ticks) in various power states |
|
| 3275system.toL2Bus.trans_dist::ReadReq 91035 # Transaction distribution 3276system.toL2Bus.trans_dist::ReadResp 4782322 # Transaction distribution 3277system.toL2Bus.trans_dist::WriteReq 38505 # Transaction distribution 3278system.toL2Bus.trans_dist::WriteResp 38505 # Transaction distribution 3279system.toL2Bus.trans_dist::WritebackDirty 3822609 # Transaction distribution 3280system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution 3281system.toL2Bus.trans_dist::CleanEvict 2941580 # Transaction distribution 3282system.toL2Bus.trans_dist::UpgradeReq 730122 # Transaction distribution --- 37 unchanged lines hidden --- | 3375system.toL2Bus.trans_dist::ReadReq 91035 # Transaction distribution 3376system.toL2Bus.trans_dist::ReadResp 4782322 # Transaction distribution 3377system.toL2Bus.trans_dist::WriteReq 38505 # Transaction distribution 3378system.toL2Bus.trans_dist::WriteResp 38505 # Transaction distribution 3379system.toL2Bus.trans_dist::WritebackDirty 3822609 # Transaction distribution 3380system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution 3381system.toL2Bus.trans_dist::CleanEvict 2941580 # Transaction distribution 3382system.toL2Bus.trans_dist::UpgradeReq 730122 # Transaction distribution --- 37 unchanged lines hidden --- |