| stats.txt (11456:c0fb4435b80f) | stats.txt (11502:e273e86a873d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 47.535940 # Number of seconds simulated 4sim_ticks 47535940136000 # Number of ticks simulated 5final_tick 47535940136000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 47.355903 # Number of seconds simulated 4sim_ticks 47355903328000 # Number of ticks simulated 5final_tick 47355903328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 200561 # Simulator instruction rate (inst/s) 8host_op_rate 235891 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 10615931561 # Simulator tick rate (ticks/s) 10host_mem_usage 769436 # Number of bytes of host memory used 11host_seconds 4477.79 # Real time elapsed on the host 12sim_insts 898069628 # Number of instructions simulated 13sim_ops 1056270581 # Number of ops (including micro ops) simulated | 7host_inst_rate 234942 # Simulator instruction rate (inst/s) 8host_op_rate 276333 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 12593783431 # Simulator tick rate (ticks/s) 10host_mem_usage 765460 # Number of bytes of host memory used 11host_seconds 3760.26 # Real time elapsed on the host 12sim_insts 883443630 # Number of instructions simulated 13sim_ops 1039082168 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu0.dtb.walker 98944 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 89728 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 8161024 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 14243656 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 14782784 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 150400 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 127744 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 3048640 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 9523856 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 12507584 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 413056 # Number of bytes read from this memory 27system.physmem.bytes_read::total 63147416 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 8161024 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 3048640 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 11209664 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 75703424 # Number of bytes written to this memory | 16system.physmem.bytes_read::cpu0.dtb.walker 131584 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 123776 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 7567040 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 14160840 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 16409728 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 122112 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 100992 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 3330560 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 9705936 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 10452736 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 444224 # Number of bytes read from this memory 27system.physmem.bytes_read::total 62549528 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 7567040 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 3330560 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 10897600 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 75633728 # Number of bytes written to this memory |
| 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory | 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory |
| 34system.physmem.bytes_written::total 75724008 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 1546 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1402 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 127516 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 222570 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 230981 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 2350 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 1996 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 47635 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 148823 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 195431 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6454 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 986704 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1182866 # Number of write requests responded to by this memory | 34system.physmem.bytes_written::total 75654312 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 2056 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1934 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 118235 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 221276 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 256402 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 1908 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 1578 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 52040 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 151668 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 163324 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6941 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 977362 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1181777 # Number of write requests responded to by this memory |
| 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory | 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory |
| 50system.physmem.num_writes::total 1185440 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 2081 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 1888 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 171681 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 299640 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 310981 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 3164 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 2687 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 64133 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 200351 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 263118 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 8689 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1328414 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 171681 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 64133 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 235815 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1592551 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) | 50system.physmem.num_writes::total 1184351 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 2779 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 2614 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 159791 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 299030 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 346519 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 2579 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 2133 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 70330 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 204957 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 220727 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9381 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1320839 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 159791 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 70330 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 230121 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1597134 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) |
| 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) | 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) |
| 69system.physmem.bw_write::total 1592984 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1592551 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 2081 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 1888 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 171681 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 300073 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 310981 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 3164 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 2687 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 64133 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 200351 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 263118 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 8689 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 2921398 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 986704 # Number of read requests accepted 84system.physmem.writeReqs 1185440 # Number of write requests accepted 85system.physmem.readBursts 986704 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1185440 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 63115328 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 33728 # Total number of bytes read from write queue 89system.physmem.bytesWritten 75722560 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 63147416 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 75724008 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 527 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 2258 # Number of DRAM write bursts merged with an existing one | 69system.physmem.bw_write::total 1597569 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1597134 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 2779 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 2614 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 159791 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 299465 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 346519 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 2579 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 2133 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 70330 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 204957 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 220727 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9381 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 2918408 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 977362 # Number of read requests accepted 84system.physmem.writeReqs 1184351 # Number of write requests accepted 85system.physmem.readBursts 977362 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1184351 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 62527296 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 23872 # Total number of bytes read from write queue 89system.physmem.bytesWritten 75653504 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 62549528 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 75654312 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 373 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one |
| 94system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 94system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 95system.physmem.perBankRdBursts::0 63842 # Per bank write bursts 96system.physmem.perBankRdBursts::1 66317 # Per bank write bursts 97system.physmem.perBankRdBursts::2 58522 # Per bank write bursts 98system.physmem.perBankRdBursts::3 64863 # Per bank write bursts 99system.physmem.perBankRdBursts::4 59095 # Per bank write bursts 100system.physmem.perBankRdBursts::5 67998 # Per bank write bursts 101system.physmem.perBankRdBursts::6 58322 # Per bank write bursts 102system.physmem.perBankRdBursts::7 56006 # Per bank write bursts 103system.physmem.perBankRdBursts::8 52486 # Per bank write bursts 104system.physmem.perBankRdBursts::9 111449 # Per bank write bursts 105system.physmem.perBankRdBursts::10 50777 # Per bank write bursts 106system.physmem.perBankRdBursts::11 58061 # Per bank write bursts 107system.physmem.perBankRdBursts::12 51458 # Per bank write bursts 108system.physmem.perBankRdBursts::13 52890 # Per bank write bursts 109system.physmem.perBankRdBursts::14 54883 # Per bank write bursts 110system.physmem.perBankRdBursts::15 59208 # Per bank write bursts 111system.physmem.perBankWrBursts::0 77123 # Per bank write bursts 112system.physmem.perBankWrBursts::1 81948 # Per bank write bursts 113system.physmem.perBankWrBursts::2 74623 # Per bank write bursts 114system.physmem.perBankWrBursts::3 80009 # Per bank write bursts 115system.physmem.perBankWrBursts::4 75007 # Per bank write bursts 116system.physmem.perBankWrBursts::5 80611 # Per bank write bursts 117system.physmem.perBankWrBursts::6 72005 # Per bank write bursts 118system.physmem.perBankWrBursts::7 72012 # Per bank write bursts 119system.physmem.perBankWrBursts::8 68266 # Per bank write bursts 120system.physmem.perBankWrBursts::9 73887 # Per bank write bursts 121system.physmem.perBankWrBursts::10 67546 # Per bank write bursts 122system.physmem.perBankWrBursts::11 72517 # Per bank write bursts 123system.physmem.perBankWrBursts::12 68786 # Per bank write bursts 124system.physmem.perBankWrBursts::13 69993 # Per bank write bursts 125system.physmem.perBankWrBursts::14 72865 # Per bank write bursts 126system.physmem.perBankWrBursts::15 75967 # Per bank write bursts | 95system.physmem.perBankRdBursts::0 54912 # Per bank write bursts 96system.physmem.perBankRdBursts::1 56908 # Per bank write bursts 97system.physmem.perBankRdBursts::2 51582 # Per bank write bursts 98system.physmem.perBankRdBursts::3 63469 # Per bank write bursts 99system.physmem.perBankRdBursts::4 61411 # Per bank write bursts 100system.physmem.perBankRdBursts::5 61841 # Per bank write bursts 101system.physmem.perBankRdBursts::6 57272 # Per bank write bursts 102system.physmem.perBankRdBursts::7 62841 # Per bank write bursts 103system.physmem.perBankRdBursts::8 51834 # Per bank write bursts 104system.physmem.perBankRdBursts::9 112088 # Per bank write bursts 105system.physmem.perBankRdBursts::10 55237 # Per bank write bursts 106system.physmem.perBankRdBursts::11 58857 # Per bank write bursts 107system.physmem.perBankRdBursts::12 56745 # Per bank write bursts 108system.physmem.perBankRdBursts::13 58205 # Per bank write bursts 109system.physmem.perBankRdBursts::14 53859 # Per bank write bursts 110system.physmem.perBankRdBursts::15 59928 # Per bank write bursts 111system.physmem.perBankWrBursts::0 69820 # Per bank write bursts 112system.physmem.perBankWrBursts::1 73385 # Per bank write bursts 113system.physmem.perBankWrBursts::2 70846 # Per bank write bursts 114system.physmem.perBankWrBursts::3 76844 # Per bank write bursts 115system.physmem.perBankWrBursts::4 76655 # Per bank write bursts 116system.physmem.perBankWrBursts::5 78828 # Per bank write bursts 117system.physmem.perBankWrBursts::6 72793 # Per bank write bursts 118system.physmem.perBankWrBursts::7 76848 # Per bank write bursts 119system.physmem.perBankWrBursts::8 69899 # Per bank write bursts 120system.physmem.perBankWrBursts::9 74878 # Per bank write bursts 121system.physmem.perBankWrBursts::10 69893 # Per bank write bursts 122system.physmem.perBankWrBursts::11 73658 # Per bank write bursts 123system.physmem.perBankWrBursts::12 73258 # Per bank write bursts 124system.physmem.perBankWrBursts::13 76164 # Per bank write bursts 125system.physmem.perBankWrBursts::14 72361 # Per bank write bursts 126system.physmem.perBankWrBursts::15 75956 # Per bank write bursts |
| 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 128system.physmem.numWrRetry 44 # Number of times write queue was full causing retry 129system.physmem.totGap 47535938023500 # Total gap between requests | 128system.physmem.numWrRetry 28 # Number of times write queue was full causing retry 129system.physmem.totGap 47355901307500 # Total gap between requests |
| 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 5 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) | 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 5 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 136system.physmem.readPktSize::6 986674 # Read request sizes (log2) | 136system.physmem.readPktSize::6 977332 # Read request sizes (log2) |
| 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) | 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 143system.physmem.writePktSize::6 1182866 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 668450 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 115815 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 42206 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 32986 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 28484 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 26396 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 23877 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 21311 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 18072 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 3298 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 1542 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 1045 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 854 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 616 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 345 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 301 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 241 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 189 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 88 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 2 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see | 143system.physmem.writePktSize::6 1181777 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 653624 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 118392 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 43298 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 33441 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 28719 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 26608 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 24389 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 21172 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 19081 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 3369 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 1474 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 993 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 791 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 539 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 292 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 238 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 181 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 95 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 68 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see |
| 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see --- 9 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see --- 9 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 191system.physmem.wrQLenPdf::15 31147 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 37996 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 51637 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 54968 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 59491 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 61707 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 64761 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 68893 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 71932 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 72504 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 73761 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 76926 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 74288 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 75236 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 82718 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 73770 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 68266 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 65794 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 4098 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 2036 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 1439 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 1105 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 896 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 756 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 640 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 509 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 526 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 444 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 328 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 386 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 373 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 283 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 314 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 286 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 288 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 274 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 232 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 270 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 191 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 251 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 159 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 174 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 172 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 147 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 178 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 188 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 200 # What write queue length does an incoming req see | 191system.physmem.wrQLenPdf::15 26534 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 34947 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 50320 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 57992 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 63163 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 65860 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 68534 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 70437 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 72935 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 73131 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 75636 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 78760 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 75174 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 74381 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 78953 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 69890 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 64098 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 61316 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 3117 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 2352 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 1927 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 1425 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 1156 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 977 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 837 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 699 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 531 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 599 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 547 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 500 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 401 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 502 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 396 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 357 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 372 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 385 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 328 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 331 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 310 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 300 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 259 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 273 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 241 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 225 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 168 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 172 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 147 # What write queue length does an incoming req see |
| 238system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see | 238system.physmem.wrQLenPdf::62 94 # What write queue length does an incoming req see |
| 239system.physmem.wrQLenPdf::63 135 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 984595 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 141.009629 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 96.339121 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 189.114371 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 670707 68.12% 68.12% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 190612 19.36% 87.48% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 44448 4.51% 91.99% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 20648 2.10% 94.09% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 14900 1.51% 95.60% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 9763 0.99% 96.60% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 5507 0.56% 97.16% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 4424 0.45% 97.60% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 23586 2.40% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 984595 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 61315 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 16.083617 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 159.391032 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-1023 61313 100.00% 100.00% # Reads before turning the bus around for writes | 239system.physmem.wrQLenPdf::63 102 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 973522 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 141.938602 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 96.538228 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 191.263762 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 662821 68.08% 68.08% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 188353 19.35% 87.43% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 43865 4.51% 91.94% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 19742 2.03% 93.97% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 14303 1.47% 95.44% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 9443 0.97% 96.41% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 6391 0.66% 97.06% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 5216 0.54% 97.60% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 23388 2.40% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 973522 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 57494 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 16.992747 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 164.605284 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-1023 57491 99.99% 99.99% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes |
| 258system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes | 259system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::29696-30719 1 0.00% 100.00% # Reads before turning the bus around for writes |
| 260system.physmem.rdPerTurnAround::total 61315 # Reads before turning the bus around for writes 261system.physmem.wrPerTurnAround::samples 61315 # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::mean 19.296502 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::gmean 18.510563 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::stdev 8.190386 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::16-19 48917 79.78% 79.78% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::20-23 5503 8.97% 88.75% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::24-27 3053 4.98% 93.73% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::28-31 1653 2.70% 96.43% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::32-35 478 0.78% 97.21% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::36-39 276 0.45% 97.66% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::40-43 266 0.43% 98.09% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::44-47 90 0.15% 98.24% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::48-51 261 0.43% 98.67% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::52-55 71 0.12% 98.78% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::56-59 38 0.06% 98.84% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::60-63 55 0.09% 98.93% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::64-67 246 0.40% 99.33% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::68-71 32 0.05% 99.39% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::72-75 47 0.08% 99.46% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::76-79 108 0.18% 99.64% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::80-83 156 0.25% 99.89% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::84-87 1 0.00% 99.90% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::88-91 1 0.00% 99.90% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::92-95 1 0.00% 99.90% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::96-99 1 0.00% 99.90% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::100-103 1 0.00% 99.90% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::112-115 1 0.00% 99.90% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::120-123 1 0.00% 99.91% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::124-127 1 0.00% 99.91% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::128-131 24 0.04% 99.95% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::132-135 1 0.00% 99.95% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::136-139 1 0.00% 99.95% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::140-143 1 0.00% 99.95% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::144-147 11 0.02% 99.97% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::148-151 2 0.00% 99.97% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::156-159 1 0.00% 99.97% # Writes before turning the bus around for reads | 261system.physmem.rdPerTurnAround::total 57494 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 57494 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 20.560163 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 18.793170 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 13.728131 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 49230 85.63% 85.63% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 2347 4.08% 89.71% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 805 1.40% 91.11% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 601 1.05% 92.15% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 998 1.74% 93.89% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 486 0.85% 94.74% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 329 0.57% 95.31% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 263 0.46% 95.76% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 216 0.38% 96.14% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 180 0.31% 96.45% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 129 0.22% 96.68% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 154 0.27% 96.95% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 478 0.83% 97.78% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 131 0.23% 98.01% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 143 0.25% 98.25% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 111 0.19% 98.45% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 107 0.19% 98.63% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::84-87 71 0.12% 98.76% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::88-91 85 0.15% 98.90% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::92-95 71 0.12% 99.03% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::96-99 101 0.18% 99.20% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::100-103 73 0.13% 99.33% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::104-107 62 0.11% 99.44% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::108-111 52 0.09% 99.53% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::112-115 38 0.07% 99.59% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::116-119 47 0.08% 99.68% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::120-123 26 0.05% 99.72% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::124-127 37 0.06% 99.79% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::128-131 49 0.09% 99.87% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::132-135 22 0.04% 99.91% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::136-139 8 0.01% 99.92% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::140-143 12 0.02% 99.94% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::144-147 6 0.01% 99.95% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::148-151 5 0.01% 99.96% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::152-155 2 0.00% 99.97% # Writes before turning the bus around for reads |
| 297system.physmem.wrPerTurnAround::160-163 6 0.01% 99.98% # Writes before turning the bus around for reads | 301system.physmem.wrPerTurnAround::160-163 6 0.01% 99.98% # Writes before turning the bus around for reads |
| 298system.physmem.wrPerTurnAround::164-167 1 0.00% 99.99% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::176-179 8 0.01% 100.00% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::total 61315 # Writes before turning the bus around for reads 302system.physmem.totQLat 31916274746 # Total ticks spent queuing 303system.physmem.totMemAccLat 50407093496 # Total ticks spent from burst creation until serviced by the DRAM 304system.physmem.totBusLat 4930885000 # Total ticks spent in databus transfers 305system.physmem.avgQLat 32363.64 # Average queueing delay per DRAM burst | 302system.physmem.wrPerTurnAround::172-175 4 0.01% 99.98% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::184-187 1 0.00% 99.99% # Writes before turning the bus around for reads 305system.physmem.wrPerTurnAround::188-191 2 0.00% 99.99% # Writes before turning the bus around for reads 306system.physmem.wrPerTurnAround::192-195 3 0.01% 100.00% # Writes before turning the bus around for reads 307system.physmem.wrPerTurnAround::220-223 1 0.00% 100.00% # Writes before turning the bus around for reads 308system.physmem.wrPerTurnAround::236-239 1 0.00% 100.00% # Writes before turning the bus around for reads 309system.physmem.wrPerTurnAround::total 57494 # Writes before turning the bus around for reads 310system.physmem.totQLat 32578317305 # Total ticks spent queuing 311system.physmem.totMemAccLat 50896861055 # Total ticks spent from burst creation until serviced by the DRAM 312system.physmem.totBusLat 4884945000 # Total ticks spent in databus transfers 313system.physmem.avgQLat 33345.63 # Average queueing delay per DRAM burst |
| 306system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 314system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 307system.physmem.avgMemAccLat 51113.64 # Average memory access latency per DRAM burst 308system.physmem.avgRdBW 1.33 # Average DRAM read bandwidth in MiByte/s 309system.physmem.avgWrBW 1.59 # Average achieved write bandwidth in MiByte/s 310system.physmem.avgRdBWSys 1.33 # Average system read bandwidth in MiByte/s 311system.physmem.avgWrBWSys 1.59 # Average system write bandwidth in MiByte/s | 315system.physmem.avgMemAccLat 52095.63 # Average memory access latency per DRAM burst 316system.physmem.avgRdBW 1.32 # Average DRAM read bandwidth in MiByte/s 317system.physmem.avgWrBW 1.60 # Average achieved write bandwidth in MiByte/s 318system.physmem.avgRdBWSys 1.32 # Average system read bandwidth in MiByte/s 319system.physmem.avgWrBWSys 1.60 # Average system write bandwidth in MiByte/s |
| 312system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 313system.physmem.busUtil 0.02 # Data bus utilization in percentage 314system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 315system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes | 320system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 321system.physmem.busUtil 0.02 # Data bus utilization in percentage 322system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 323system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes |
| 316system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing 317system.physmem.avgWrQLen 24.32 # Average write queue length when enqueuing 318system.physmem.readRowHits 734466 # Number of row buffer hits during reads 319system.physmem.writeRowHits 450279 # Number of row buffer hits during writes 320system.physmem.readRowHitRate 74.48 # Row buffer hit rate for reads 321system.physmem.writeRowHitRate 38.06 # Row buffer hit rate for writes 322system.physmem.avgGap 21884340.09 # Average gap between requests 323system.physmem.pageHitRate 54.61 # Row buffer hit rate, read and write combined 324system.physmem_0.actEnergy 3920933520 # Energy for activate commands per rank (pJ) 325system.physmem_0.preEnergy 2139398250 # Energy for precharge commands per rank (pJ) 326system.physmem_0.readEnergy 3860672400 # Energy for read commands per rank (pJ) 327system.physmem_0.writeEnergy 3974430240 # Energy for write commands per rank (pJ) 328system.physmem_0.refreshEnergy 3104816267280 # Energy for refresh commands per rank (pJ) 329system.physmem_0.actBackEnergy 1203845511330 # Energy for active background per rank (pJ) 330system.physmem_0.preBackEnergy 27465556979250 # Energy for precharge background per rank (pJ) 331system.physmem_0.totalEnergy 31788114192270 # Total energy per rank (pJ) 332system.physmem_0.averagePower 668.717535 # Core power per rank (mW) 333system.physmem_0.memoryStateTime::IDLE 45690953287273 # Time in different power states 334system.physmem_0.memoryStateTime::REF 1587329380000 # Time in different power states | 324system.physmem.avgRdQLen 1.15 # Average read queue length when enqueuing 325system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing 326system.physmem.readRowHits 734277 # Number of row buffer hits during reads 327system.physmem.writeRowHits 451275 # Number of row buffer hits during writes 328system.physmem.readRowHitRate 75.16 # Row buffer hit rate for reads 329system.physmem.writeRowHitRate 38.18 # Row buffer hit rate for writes 330system.physmem.avgGap 21906655.19 # Average gap between requests 331system.physmem.pageHitRate 54.91 # Row buffer hit rate, read and write combined 332system.physmem_0.actEnergy 3752269920 # Energy for activate commands per rank (pJ) 333system.physmem_0.preEnergy 2047369500 # Energy for precharge commands per rank (pJ) 334system.physmem_0.readEnergy 3667786200 # Energy for read commands per rank (pJ) 335system.physmem_0.writeEnergy 3862203120 # Energy for write commands per rank (pJ) 336system.physmem_0.refreshEnergy 3093057342960 # Energy for refresh commands per rank (pJ) 337system.physmem_0.actBackEnergy 1180767055500 # Energy for active background per rank (pJ) 338system.physmem_0.preBackEnergy 27377781027000 # Energy for precharge background per rank (pJ) 339system.physmem_0.totalEnergy 31664935054200 # Total energy per rank (pJ) 340system.physmem_0.averagePower 668.658673 # Core power per rank (mW) 341system.physmem_0.memoryStateTime::IDLE 45545161867023 # Time in different power states 342system.physmem_0.memoryStateTime::REF 1581317660000 # Time in different power states |
| 335system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 343system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 336system.physmem_0.memoryStateTime::ACT 257656491727 # Time in different power states | 344system.physmem_0.memoryStateTime::ACT 229423166977 # Time in different power states |
| 337system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 345system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 338system.physmem_1.actEnergy 3522604680 # Energy for activate commands per rank (pJ) 339system.physmem_1.preEnergy 1922056125 # Energy for precharge commands per rank (pJ) 340system.physmem_1.readEnergy 3831445800 # Energy for read commands per rank (pJ) 341system.physmem_1.writeEnergy 3692478960 # Energy for write commands per rank (pJ) 342system.physmem_1.refreshEnergy 3104816267280 # Energy for refresh commands per rank (pJ) 343system.physmem_1.actBackEnergy 1196085851100 # Energy for active background per rank (pJ) 344system.physmem_1.preBackEnergy 27472363698750 # Energy for precharge background per rank (pJ) 345system.physmem_1.totalEnergy 31786234402695 # Total energy per rank (pJ) 346system.physmem_1.averagePower 668.677991 # Core power per rank (mW) 347system.physmem_1.memoryStateTime::IDLE 45702273449121 # Time in different power states 348system.physmem_1.memoryStateTime::REF 1587329380000 # Time in different power states | 346system.physmem_1.actEnergy 3607556400 # Energy for activate commands per rank (pJ) 347system.physmem_1.preEnergy 1968408750 # Energy for precharge commands per rank (pJ) 348system.physmem_1.readEnergy 3952673400 # Energy for read commands per rank (pJ) 349system.physmem_1.writeEnergy 3797714160 # Energy for write commands per rank (pJ) 350system.physmem_1.refreshEnergy 3093057342960 # Energy for refresh commands per rank (pJ) 351system.physmem_1.actBackEnergy 1177905490200 # Energy for active background per rank (pJ) 352system.physmem_1.preBackEnergy 27380291180250 # Energy for precharge background per rank (pJ) 353system.physmem_1.totalEnergy 31664580366120 # Total energy per rank (pJ) 354system.physmem_1.averagePower 668.651183 # Core power per rank (mW) 355system.physmem_1.memoryStateTime::IDLE 45549316476567 # Time in different power states 356system.physmem_1.memoryStateTime::REF 1581317660000 # Time in different power states |
| 349system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 357system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 350system.physmem_1.memoryStateTime::ACT 246336261879 # Time in different power states | 358system.physmem_1.memoryStateTime::ACT 225268560933 # Time in different power states |
| 351system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 352system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 353system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 354system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 355system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 356system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 357system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 358system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory --- 14 unchanged lines hidden (view full) --- 373system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 374system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 375system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 376system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 377system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 378system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 379system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 380system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). | 359system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 360system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 361system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 362system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 363system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 364system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 365system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 366system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory --- 14 unchanged lines hidden (view full) --- 381system.realview.nvmem.bw_total::cpu0.inst 15 # Total bandwidth to/from this memory (bytes/s) 382system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 383system.realview.nvmem.bw_total::cpu1.inst 12 # Total bandwidth to/from this memory (bytes/s) 384system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 385system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 386system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 387system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 388system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). |
| 381system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. 382system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. 383system.cf0.dma_write_txs 1674 # Number of DMA write transactions. 384system.cpu0.branchPred.lookups 146462396 # Number of BP lookups 385system.cpu0.branchPred.condPredicted 102364881 # Number of conditional branches predicted 386system.cpu0.branchPred.condIncorrect 6839955 # Number of conditional branches incorrect 387system.cpu0.branchPred.BTBLookups 108739004 # Number of BTB lookups 388system.cpu0.branchPred.BTBHits 75372629 # Number of BTB hits | 389system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 390system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 391system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 392system.cpu0.branchPred.lookups 145452632 # Number of BP lookups 393system.cpu0.branchPred.condPredicted 102233764 # Number of conditional branches predicted 394system.cpu0.branchPred.condIncorrect 6537956 # Number of conditional branches incorrect 395system.cpu0.branchPred.BTBLookups 107843095 # Number of BTB lookups 396system.cpu0.branchPred.BTBHits 75495824 # Number of BTB hits |
| 389system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 397system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 390system.cpu0.branchPred.BTBHitPct 69.315173 # BTB Hit Percentage 391system.cpu0.branchPred.usedRAS 17612403 # Number of times the RAS was used to get a target. 392system.cpu0.branchPred.RASInCorrect 1195732 # Number of incorrect RAS predictions. 393system.cpu0.branchPred.indirectLookups 3915449 # Number of indirect predictor lookups. 394system.cpu0.branchPred.indirectHits 2665463 # Number of indirect target hits. 395system.cpu0.branchPred.indirectMisses 1249986 # Number of indirect misses. 396system.cpu0.branchPredindirectMispredicted 447212 # Number of mispredicted indirect branches. | 398system.cpu0.branchPred.BTBHitPct 70.005246 # BTB Hit Percentage 399system.cpu0.branchPred.usedRAS 17327542 # Number of times the RAS was used to get a target. 400system.cpu0.branchPred.RASInCorrect 1162135 # Number of incorrect RAS predictions. 401system.cpu0.branchPred.indirectLookups 3835403 # Number of indirect predictor lookups. 402system.cpu0.branchPred.indirectHits 2658726 # Number of indirect target hits. 403system.cpu0.branchPred.indirectMisses 1176677 # Number of indirect misses. 404system.cpu0.branchPredindirectMispredicted 420775 # Number of mispredicted indirect branches. |
| 397system.cpu_clk_domain.clock 500 # Clock period in ticks 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 401system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 402system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 403system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 404system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 419system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 420system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 421system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 422system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 423system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 424system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 425system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 426system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 405system.cpu_clk_domain.clock 500 # Clock period in ticks 406system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 407system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 408system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 409system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 410system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 411system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 412system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 427system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 428system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 429system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 430system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 431system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 432system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 433system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 434system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 427system.cpu0.dtb.walker.walks 302048 # Table walker walks requested 428system.cpu0.dtb.walker.walksLong 302048 # Table walker walks initiated with long descriptors 429system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10564 # Level at which table walker walks with long descriptors terminate 430system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 84260 # Level at which table walker walks with long descriptors terminate 431system.cpu0.dtb.walker.walkWaitTime::samples 302048 # Table walker wait (enqueue to first request) latency 432system.cpu0.dtb.walker.walkWaitTime::0 302048 100.00% 100.00% # Table walker wait (enqueue to first request) latency 433system.cpu0.dtb.walker.walkWaitTime::total 302048 # Table walker wait (enqueue to first request) latency 434system.cpu0.dtb.walker.walkCompletionTime::samples 94824 # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::mean 22896.634818 # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::gmean 21259.302446 # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::stdev 17613.215135 # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::0-65535 93928 99.06% 99.06% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::65536-131071 167 0.18% 99.23% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::131072-196607 600 0.63% 99.86% # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::196608-262143 30 0.03% 99.90% # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::262144-327679 32 0.03% 99.93% # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::327680-393215 18 0.02% 99.95% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::393216-458751 34 0.04% 99.98% # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::total 94824 # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walksPending::samples -909613592 # Table walker pending requests distribution 450system.cpu0.dtb.walker.walksPending::0 -909613592 100.00% 100.00% # Table walker pending requests distribution 451system.cpu0.dtb.walker.walksPending::total -909613592 # Table walker pending requests distribution 452system.cpu0.dtb.walker.walkPageSizes::4K 84260 88.86% 88.86% # Table walker page sizes translated 453system.cpu0.dtb.walker.walkPageSizes::2M 10564 11.14% 100.00% # Table walker page sizes translated 454system.cpu0.dtb.walker.walkPageSizes::total 94824 # Table walker page sizes translated 455system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 302048 # Table walker requests started/completed, data/inst | 435system.cpu0.dtb.walker.walks 298304 # Table walker walks requested 436system.cpu0.dtb.walker.walksLong 298304 # Table walker walks initiated with long descriptors 437system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10716 # Level at which table walker walks with long descriptors terminate 438system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 85635 # Level at which table walker walks with long descriptors terminate 439system.cpu0.dtb.walker.walkWaitTime::samples 298304 # Table walker wait (enqueue to first request) latency 440system.cpu0.dtb.walker.walkWaitTime::0 298304 100.00% 100.00% # Table walker wait (enqueue to first request) latency 441system.cpu0.dtb.walker.walkWaitTime::total 298304 # Table walker wait (enqueue to first request) latency 442system.cpu0.dtb.walker.walkCompletionTime::samples 96351 # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::mean 22754.257870 # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::gmean 21300.315388 # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::stdev 14215.969550 # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::0-65535 95122 98.72% 98.72% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1073 1.11% 99.84% # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::131072-196607 26 0.03% 99.87% # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walkCompletionTime::196608-262143 56 0.06% 99.92% # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::262144-327679 56 0.06% 99.98% # Table walker service (enqueue to completion) latency 451system.cpu0.dtb.walker.walkCompletionTime::327680-393215 10 0.01% 99.99% # Table walker service (enqueue to completion) latency 452system.cpu0.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency 453system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 454system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 455system.cpu0.dtb.walker.walkCompletionTime::total 96351 # Table walker service (enqueue to completion) latency 456system.cpu0.dtb.walker.walksPending::samples 734209704 # Table walker pending requests distribution 457system.cpu0.dtb.walker.walksPending::0 734209704 100.00% 100.00% # Table walker pending requests distribution 458system.cpu0.dtb.walker.walksPending::total 734209704 # Table walker pending requests distribution 459system.cpu0.dtb.walker.walkPageSizes::4K 85635 88.88% 88.88% # Table walker page sizes translated 460system.cpu0.dtb.walker.walkPageSizes::2M 10716 11.12% 100.00% # Table walker page sizes translated 461system.cpu0.dtb.walker.walkPageSizes::total 96351 # Table walker page sizes translated 462system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 298304 # Table walker requests started/completed, data/inst |
| 456system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 463system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 457system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 302048 # Table walker requests started/completed, data/inst 458system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 94824 # Table walker requests started/completed, data/inst | 464system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 298304 # Table walker requests started/completed, data/inst 465system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 96351 # Table walker requests started/completed, data/inst |
| 459system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 466system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 460system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 94824 # Table walker requests started/completed, data/inst 461system.cpu0.dtb.walker.walkRequestOrigin::total 396872 # Table walker requests started/completed, data/inst | 467system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 96351 # Table walker requests started/completed, data/inst 468system.cpu0.dtb.walker.walkRequestOrigin::total 394655 # Table walker requests started/completed, data/inst |
| 462system.cpu0.dtb.inst_hits 0 # ITB inst hits 463system.cpu0.dtb.inst_misses 0 # ITB inst misses | 469system.cpu0.dtb.inst_hits 0 # ITB inst hits 470system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 464system.cpu0.dtb.read_hits 94909868 # DTB read hits 465system.cpu0.dtb.read_misses 253021 # DTB read misses 466system.cpu0.dtb.write_hits 83284387 # DTB write hits 467system.cpu0.dtb.write_misses 49027 # DTB write misses | 471system.cpu0.dtb.read_hits 93899745 # DTB read hits 472system.cpu0.dtb.read_misses 250404 # DTB read misses 473system.cpu0.dtb.write_hits 82108561 # DTB write hits 474system.cpu0.dtb.write_misses 47900 # DTB write misses |
| 468system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 469system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 475system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 476system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 470system.cpu0.dtb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID 471system.cpu0.dtb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID 472system.cpu0.dtb.flush_entries 38313 # Number of entries that have been flushed from TLB 473system.cpu0.dtb.align_faults 2113 # Number of TLB faults due to alignment restrictions 474system.cpu0.dtb.prefetch_faults 10577 # Number of TLB faults due to prefetch | 477system.cpu0.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID 478system.cpu0.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 479system.cpu0.dtb.flush_entries 39156 # Number of entries that have been flushed from TLB 480system.cpu0.dtb.align_faults 2185 # Number of TLB faults due to alignment restrictions 481system.cpu0.dtb.prefetch_faults 10307 # Number of TLB faults due to prefetch |
| 475system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 482system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 476system.cpu0.dtb.perms_faults 10792 # Number of TLB faults due to permissions restrictions 477system.cpu0.dtb.read_accesses 95162889 # DTB read accesses 478system.cpu0.dtb.write_accesses 83333414 # DTB write accesses | 483system.cpu0.dtb.perms_faults 10956 # Number of TLB faults due to permissions restrictions 484system.cpu0.dtb.read_accesses 94150149 # DTB read accesses 485system.cpu0.dtb.write_accesses 82156461 # DTB write accesses |
| 479system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 486system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 480system.cpu0.dtb.hits 178194255 # DTB hits 481system.cpu0.dtb.misses 302048 # DTB misses 482system.cpu0.dtb.accesses 178496303 # DTB accesses | 487system.cpu0.dtb.hits 176008306 # DTB hits 488system.cpu0.dtb.misses 298304 # DTB misses 489system.cpu0.dtb.accesses 176306610 # DTB accesses |
| 483system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 489system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 490system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 504system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 505system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 506system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 507system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 508system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 509system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 510system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 511system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 490system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 491system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 492system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 493system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 494system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 495system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 496system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 497system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 511system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 512system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 513system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 514system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 515system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 516system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 517system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 518system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 512system.cpu0.itb.walker.walks 66529 # Table walker walks requested 513system.cpu0.itb.walker.walksLong 66529 # Table walker walks initiated with long descriptors 514system.cpu0.itb.walker.walksLongTerminationLevel::Level2 603 # Level at which table walker walks with long descriptors terminate 515system.cpu0.itb.walker.walksLongTerminationLevel::Level3 54822 # Level at which table walker walks with long descriptors terminate 516system.cpu0.itb.walker.walkWaitTime::samples 66529 # Table walker wait (enqueue to first request) latency 517system.cpu0.itb.walker.walkWaitTime::0 66529 100.00% 100.00% # Table walker wait (enqueue to first request) latency 518system.cpu0.itb.walker.walkWaitTime::total 66529 # Table walker wait (enqueue to first request) latency 519system.cpu0.itb.walker.walkCompletionTime::samples 55425 # Table walker service (enqueue to completion) latency 520system.cpu0.itb.walker.walkCompletionTime::mean 25786.567433 # Table walker service (enqueue to completion) latency 521system.cpu0.itb.walker.walkCompletionTime::gmean 23469.117152 # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walkCompletionTime::stdev 20785.804114 # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walkCompletionTime::0-32767 51379 92.70% 92.70% # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walkCompletionTime::32768-65535 3140 5.67% 98.37% # Table walker service (enqueue to completion) latency 525system.cpu0.itb.walker.walkCompletionTime::65536-98303 12 0.02% 98.39% # Table walker service (enqueue to completion) latency 526system.cpu0.itb.walker.walkCompletionTime::98304-131071 1 0.00% 98.39% # Table walker service (enqueue to completion) latency 527system.cpu0.itb.walker.walkCompletionTime::131072-163839 536 0.97% 99.36% # Table walker service (enqueue to completion) latency 528system.cpu0.itb.walker.walkCompletionTime::163840-196607 270 0.49% 99.84% # Table walker service (enqueue to completion) latency 529system.cpu0.itb.walker.walkCompletionTime::196608-229375 8 0.01% 99.86% # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walkCompletionTime::229376-262143 14 0.03% 99.88% # Table walker service (enqueue to completion) latency 531system.cpu0.itb.walker.walkCompletionTime::262144-294911 15 0.03% 99.91% # Table walker service (enqueue to completion) latency 532system.cpu0.itb.walker.walkCompletionTime::294912-327679 29 0.05% 99.96% # Table walker service (enqueue to completion) latency 533system.cpu0.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.98% # Table walker service (enqueue to completion) latency 534system.cpu0.itb.walker.walkCompletionTime::360448-393215 2 0.00% 99.98% # Table walker service (enqueue to completion) latency 535system.cpu0.itb.walker.walkCompletionTime::393216-425983 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 536system.cpu0.itb.walker.walkCompletionTime::425984-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 537system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 538system.cpu0.itb.walker.walkCompletionTime::total 55425 # Table walker service (enqueue to completion) latency 539system.cpu0.itb.walker.walksPending::samples -910742092 # Table walker pending requests distribution 540system.cpu0.itb.walker.walksPending::0 -910742092 100.00% 100.00% # Table walker pending requests distribution 541system.cpu0.itb.walker.walksPending::total -910742092 # Table walker pending requests distribution 542system.cpu0.itb.walker.walkPageSizes::4K 54822 98.91% 98.91% # Table walker page sizes translated 543system.cpu0.itb.walker.walkPageSizes::2M 603 1.09% 100.00% # Table walker page sizes translated 544system.cpu0.itb.walker.walkPageSizes::total 55425 # Table walker page sizes translated | 519system.cpu0.itb.walker.walks 65048 # Table walker walks requested 520system.cpu0.itb.walker.walksLong 65048 # Table walker walks initiated with long descriptors 521system.cpu0.itb.walker.walksLongTerminationLevel::Level2 515 # Level at which table walker walks with long descriptors terminate 522system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52970 # Level at which table walker walks with long descriptors terminate 523system.cpu0.itb.walker.walkWaitTime::samples 65048 # Table walker wait (enqueue to first request) latency 524system.cpu0.itb.walker.walkWaitTime::0 65048 100.00% 100.00% # Table walker wait (enqueue to first request) latency 525system.cpu0.itb.walker.walkWaitTime::total 65048 # Table walker wait (enqueue to first request) latency 526system.cpu0.itb.walker.walkCompletionTime::samples 53485 # Table walker service (enqueue to completion) latency 527system.cpu0.itb.walker.walkCompletionTime::mean 25497.494625 # Table walker service (enqueue to completion) latency 528system.cpu0.itb.walker.walkCompletionTime::gmean 23453.450778 # Table walker service (enqueue to completion) latency 529system.cpu0.itb.walker.walkCompletionTime::stdev 17328.133028 # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walkCompletionTime::0-32767 49469 92.49% 92.49% # Table walker service (enqueue to completion) latency 531system.cpu0.itb.walker.walkCompletionTime::32768-65535 2789 5.21% 97.71% # Table walker service (enqueue to completion) latency 532system.cpu0.itb.walker.walkCompletionTime::65536-98303 9 0.02% 97.72% # Table walker service (enqueue to completion) latency 533system.cpu0.itb.walker.walkCompletionTime::98304-131071 1088 2.03% 99.76% # Table walker service (enqueue to completion) latency 534system.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.04% 99.80% # Table walker service (enqueue to completion) latency 535system.cpu0.itb.walker.walkCompletionTime::163840-196607 14 0.03% 99.82% # Table walker service (enqueue to completion) latency 536system.cpu0.itb.walker.walkCompletionTime::196608-229375 47 0.09% 99.91% # Table walker service (enqueue to completion) latency 537system.cpu0.itb.walker.walkCompletionTime::229376-262143 18 0.03% 99.94% # Table walker service (enqueue to completion) latency 538system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.96% # Table walker service (enqueue to completion) latency 539system.cpu0.itb.walker.walkCompletionTime::294912-327679 8 0.01% 99.97% # Table walker service (enqueue to completion) latency 540system.cpu0.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.98% # Table walker service (enqueue to completion) latency 541system.cpu0.itb.walker.walkCompletionTime::360448-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency 542system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 543system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 544system.cpu0.itb.walker.walkCompletionTime::total 53485 # Table walker service (enqueue to completion) latency 545system.cpu0.itb.walker.walksPending::samples 733487204 # Table walker pending requests distribution 546system.cpu0.itb.walker.walksPending::0 733487204 100.00% 100.00% # Table walker pending requests distribution 547system.cpu0.itb.walker.walksPending::total 733487204 # Table walker pending requests distribution 548system.cpu0.itb.walker.walkPageSizes::4K 52970 99.04% 99.04% # Table walker page sizes translated 549system.cpu0.itb.walker.walkPageSizes::2M 515 0.96% 100.00% # Table walker page sizes translated 550system.cpu0.itb.walker.walkPageSizes::total 53485 # Table walker page sizes translated |
| 545system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 551system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 546system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66529 # Table walker requests started/completed, data/inst 547system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66529 # Table walker requests started/completed, data/inst | 552system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 65048 # Table walker requests started/completed, data/inst 553system.cpu0.itb.walker.walkRequestOrigin_Requested::total 65048 # Table walker requests started/completed, data/inst |
| 548system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 554system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 549system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 55425 # Table walker requests started/completed, data/inst 550system.cpu0.itb.walker.walkRequestOrigin_Completed::total 55425 # Table walker requests started/completed, data/inst 551system.cpu0.itb.walker.walkRequestOrigin::total 121954 # Table walker requests started/completed, data/inst 552system.cpu0.itb.inst_hits 260612167 # ITB inst hits 553system.cpu0.itb.inst_misses 66529 # ITB inst misses | 555system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 53485 # Table walker requests started/completed, data/inst 556system.cpu0.itb.walker.walkRequestOrigin_Completed::total 53485 # Table walker requests started/completed, data/inst 557system.cpu0.itb.walker.walkRequestOrigin::total 118533 # Table walker requests started/completed, data/inst 558system.cpu0.itb.inst_hits 259203584 # ITB inst hits 559system.cpu0.itb.inst_misses 65048 # ITB inst misses |
| 554system.cpu0.itb.read_hits 0 # DTB read hits 555system.cpu0.itb.read_misses 0 # DTB read misses 556system.cpu0.itb.write_hits 0 # DTB write hits 557system.cpu0.itb.write_misses 0 # DTB write misses 558system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 559system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 560system.cpu0.itb.read_hits 0 # DTB read hits 561system.cpu0.itb.read_misses 0 # DTB read misses 562system.cpu0.itb.write_hits 0 # DTB write hits 563system.cpu0.itb.write_misses 0 # DTB write misses 564system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 565system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 560system.cpu0.itb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID 561system.cpu0.itb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID 562system.cpu0.itb.flush_entries 27578 # Number of entries that have been flushed from TLB | 566system.cpu0.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID 567system.cpu0.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 568system.cpu0.itb.flush_entries 28333 # Number of entries that have been flushed from TLB |
| 563system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 564system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 565system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 569system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 570system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 571system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 566system.cpu0.itb.perms_faults 178681 # Number of TLB faults due to permissions restrictions | 572system.cpu0.itb.perms_faults 171713 # Number of TLB faults due to permissions restrictions |
| 567system.cpu0.itb.read_accesses 0 # DTB read accesses 568system.cpu0.itb.write_accesses 0 # DTB write accesses | 573system.cpu0.itb.read_accesses 0 # DTB read accesses 574system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 569system.cpu0.itb.inst_accesses 260678696 # ITB inst accesses 570system.cpu0.itb.hits 260612167 # DTB hits 571system.cpu0.itb.misses 66529 # DTB misses 572system.cpu0.itb.accesses 260678696 # DTB accesses 573system.cpu0.numCycles 1099930824 # number of cpu cycles simulated | 575system.cpu0.itb.inst_accesses 259268632 # ITB inst accesses 576system.cpu0.itb.hits 259203584 # DTB hits 577system.cpu0.itb.misses 65048 # DTB misses 578system.cpu0.itb.accesses 259268632 # DTB accesses 579system.cpu0.numCycles 1023758481 # number of cpu cycles simulated |
| 574system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 575system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 580system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 581system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 576system.cpu0.committedInsts 487305462 # Number of instructions committed 577system.cpu0.committedOps 572197777 # Number of ops (including micro ops) committed 578system.cpu0.discardedOps 47186623 # Number of ops (including micro ops) which were discarded before commit 579system.cpu0.numFetchSuspends 4440 # Number of times Execute suspended instruction fetching 580system.cpu0.quiesceCycles 93972724601 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 581system.cpu0.cpi 2.257169 # CPI: cycles per instruction 582system.cpu0.ipc 0.443033 # IPC: instructions per cycle | 582system.cpu0.committedInsts 483101155 # Number of instructions committed 583system.cpu0.committedOps 567019823 # Number of ops (including micro ops) committed 584system.cpu0.discardedOps 47457065 # Number of ops (including micro ops) which were discarded before commit 585system.cpu0.numFetchSuspends 4178 # Number of times Execute suspended instruction fetching 586system.cpu0.quiesceCycles 93688785177 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 587system.cpu0.cpi 2.119139 # CPI: cycles per instruction 588system.cpu0.ipc 0.471890 # IPC: instructions per cycle |
| 583system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction | 589system.cpu0.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction |
| 584system.cpu0.op_class_0::IntAlu 396450876 69.29% 69.29% # Class of committed instruction 585system.cpu0.op_class_0::IntMult 1302433 0.23% 69.51% # Class of committed instruction 586system.cpu0.op_class_0::IntDiv 64217 0.01% 69.52% # Class of committed instruction 587system.cpu0.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction 588system.cpu0.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction 589system.cpu0.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction 590system.cpu0.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction 591system.cpu0.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction 592system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction 593system.cpu0.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction 594system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction 595system.cpu0.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction 596system.cpu0.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction 597system.cpu0.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction 598system.cpu0.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction 599system.cpu0.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction 600system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction 601system.cpu0.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction 602system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction 603system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction 604system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.52% # Class of committed instruction 605system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction 606system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.52% # Class of committed instruction 607system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.52% # Class of committed instruction 608system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction 609system.cpu0.op_class_0::SimdFloatMisc 76920 0.01% 69.54% # Class of committed instruction 610system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction 611system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction 612system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction 613system.cpu0.op_class_0::MemRead 91382938 15.97% 85.51% # Class of committed instruction 614system.cpu0.op_class_0::MemWrite 82920392 14.49% 100.00% # Class of committed instruction | 590system.cpu0.op_class_0::IntAlu 393333975 69.37% 69.37% # Class of committed instruction 591system.cpu0.op_class_0::IntMult 1298911 0.23% 69.60% # Class of committed instruction 592system.cpu0.op_class_0::IntDiv 62117 0.01% 69.61% # Class of committed instruction 593system.cpu0.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction 594system.cpu0.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction 595system.cpu0.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction 596system.cpu0.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction 597system.cpu0.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction 598system.cpu0.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction 599system.cpu0.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction 600system.cpu0.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction 601system.cpu0.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction 602system.cpu0.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction 603system.cpu0.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction 604system.cpu0.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction 605system.cpu0.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction 606system.cpu0.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction 607system.cpu0.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction 608system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction 609system.cpu0.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction 610system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction 611system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction 612system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction 613system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction 614system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction 615system.cpu0.op_class_0::SimdFloatMisc 39633 0.01% 69.62% # Class of committed instruction 616system.cpu0.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction 617system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction 618system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction 619system.cpu0.op_class_0::MemRead 90520623 15.96% 85.58% # Class of committed instruction 620system.cpu0.op_class_0::MemWrite 81764563 14.42% 100.00% # Class of committed instruction |
| 615system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 616system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 621system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 622system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 617system.cpu0.op_class_0::total 572197777 # Class of committed instruction | 623system.cpu0.op_class_0::total 567019823 # Class of committed instruction |
| 618system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 624system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 619system.cpu0.kern.inst.quiesce 13277 # number of quiesce instructions executed 620system.cpu0.tickCycles 780613530 # Number of cycles that the object actually ticked 621system.cpu0.idleCycles 319317294 # Total number of cycles that the object has spent stopped 622system.cpu0.dcache.tags.replacements 5972011 # number of replacements 623system.cpu0.dcache.tags.tagsinuse 508.033077 # Cycle average of tags in use 624system.cpu0.dcache.tags.total_refs 169168179 # Total number of references to valid blocks. 625system.cpu0.dcache.tags.sampled_refs 5972523 # Sample count of references to valid blocks. 626system.cpu0.dcache.tags.avg_refs 28.324408 # Average number of references to valid blocks. 627system.cpu0.dcache.tags.warmup_cycle 7690769000 # Cycle when the warmup percentage was hit. 628system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.033077 # Average occupied blocks per requestor 629system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992252 # Average percentage of cache occupancy 630system.cpu0.dcache.tags.occ_percent::total 0.992252 # Average percentage of cache occupancy | 625system.cpu0.kern.inst.quiesce 13020 # number of quiesce instructions executed 626system.cpu0.tickCycles 768761843 # Number of cycles that the object actually ticked 627system.cpu0.idleCycles 254996638 # Total number of cycles that the object has spent stopped 628system.cpu0.dcache.tags.replacements 6026209 # number of replacements 629system.cpu0.dcache.tags.tagsinuse 478.505782 # Cycle average of tags in use 630system.cpu0.dcache.tags.total_refs 166971566 # Total number of references to valid blocks. 631system.cpu0.dcache.tags.sampled_refs 6026721 # Sample count of references to valid blocks. 632system.cpu0.dcache.tags.avg_refs 27.705209 # Average number of references to valid blocks. 633system.cpu0.dcache.tags.warmup_cycle 5039130000 # Cycle when the warmup percentage was hit. 634system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.505782 # Average occupied blocks per requestor 635system.cpu0.dcache.tags.occ_percent::cpu0.data 0.934582 # Average percentage of cache occupancy 636system.cpu0.dcache.tags.occ_percent::total 0.934582 # Average percentage of cache occupancy |
| 631system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 637system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 632system.cpu0.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id 633system.cpu0.dcache.tags.age_task_id_blocks_1024::1 388 # Occupied blocks per task id 634system.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id | 638system.cpu0.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id 639system.cpu0.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id 640system.cpu0.dcache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id 641system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id |
| 635system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 642system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 636system.cpu0.dcache.tags.tag_accesses 359361260 # Number of tag accesses 637system.cpu0.dcache.tags.data_accesses 359361260 # Number of data accesses 638system.cpu0.dcache.ReadReq_hits::cpu0.data 87043361 # number of ReadReq hits 639system.cpu0.dcache.ReadReq_hits::total 87043361 # number of ReadReq hits 640system.cpu0.dcache.WriteReq_hits::cpu0.data 77242749 # number of WriteReq hits 641system.cpu0.dcache.WriteReq_hits::total 77242749 # number of WriteReq hits 642system.cpu0.dcache.SoftPFReq_hits::cpu0.data 305030 # number of SoftPFReq hits 643system.cpu0.dcache.SoftPFReq_hits::total 305030 # number of SoftPFReq hits 644system.cpu0.dcache.WriteLineReq_hits::cpu0.data 287060 # number of WriteLineReq hits 645system.cpu0.dcache.WriteLineReq_hits::total 287060 # number of WriteLineReq hits 646system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1877481 # number of LoadLockedReq hits 647system.cpu0.dcache.LoadLockedReq_hits::total 1877481 # number of LoadLockedReq hits 648system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1849167 # number of StoreCondReq hits 649system.cpu0.dcache.StoreCondReq_hits::total 1849167 # number of StoreCondReq hits 650system.cpu0.dcache.demand_hits::cpu0.data 164573170 # number of demand (read+write) hits 651system.cpu0.dcache.demand_hits::total 164573170 # number of demand (read+write) hits 652system.cpu0.dcache.overall_hits::cpu0.data 164878200 # number of overall hits 653system.cpu0.dcache.overall_hits::total 164878200 # number of overall hits 654system.cpu0.dcache.ReadReq_misses::cpu0.data 3693348 # number of ReadReq misses 655system.cpu0.dcache.ReadReq_misses::total 3693348 # number of ReadReq misses 656system.cpu0.dcache.WriteReq_misses::cpu0.data 2460225 # number of WriteReq misses 657system.cpu0.dcache.WriteReq_misses::total 2460225 # number of WriteReq misses 658system.cpu0.dcache.SoftPFReq_misses::cpu0.data 661742 # number of SoftPFReq misses 659system.cpu0.dcache.SoftPFReq_misses::total 661742 # number of SoftPFReq misses 660system.cpu0.dcache.WriteLineReq_misses::cpu0.data 847892 # number of WriteLineReq misses 661system.cpu0.dcache.WriteLineReq_misses::total 847892 # number of WriteLineReq misses 662system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173543 # number of LoadLockedReq misses 663system.cpu0.dcache.LoadLockedReq_misses::total 173543 # number of LoadLockedReq misses 664system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200600 # number of StoreCondReq misses 665system.cpu0.dcache.StoreCondReq_misses::total 200600 # number of StoreCondReq misses 666system.cpu0.dcache.demand_misses::cpu0.data 7001465 # number of demand (read+write) misses 667system.cpu0.dcache.demand_misses::total 7001465 # number of demand (read+write) misses 668system.cpu0.dcache.overall_misses::cpu0.data 7663207 # number of overall misses 669system.cpu0.dcache.overall_misses::total 7663207 # number of overall misses 670system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 64125292500 # number of ReadReq miss cycles 671system.cpu0.dcache.ReadReq_miss_latency::total 64125292500 # number of ReadReq miss cycles 672system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 62047058000 # number of WriteReq miss cycles 673system.cpu0.dcache.WriteReq_miss_latency::total 62047058000 # number of WriteReq miss cycles 674system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 51167444000 # number of WriteLineReq miss cycles 675system.cpu0.dcache.WriteLineReq_miss_latency::total 51167444000 # number of WriteLineReq miss cycles 676system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2860725000 # number of LoadLockedReq miss cycles 677system.cpu0.dcache.LoadLockedReq_miss_latency::total 2860725000 # number of LoadLockedReq miss cycles 678system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5699610500 # number of StoreCondReq miss cycles 679system.cpu0.dcache.StoreCondReq_miss_latency::total 5699610500 # number of StoreCondReq miss cycles 680system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5746000 # number of StoreCondFailReq miss cycles 681system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5746000 # number of StoreCondFailReq miss cycles 682system.cpu0.dcache.demand_miss_latency::cpu0.data 177339794500 # number of demand (read+write) miss cycles 683system.cpu0.dcache.demand_miss_latency::total 177339794500 # number of demand (read+write) miss cycles 684system.cpu0.dcache.overall_miss_latency::cpu0.data 177339794500 # number of overall miss cycles 685system.cpu0.dcache.overall_miss_latency::total 177339794500 # number of overall miss cycles 686system.cpu0.dcache.ReadReq_accesses::cpu0.data 90736709 # number of ReadReq accesses(hits+misses) 687system.cpu0.dcache.ReadReq_accesses::total 90736709 # number of ReadReq accesses(hits+misses) 688system.cpu0.dcache.WriteReq_accesses::cpu0.data 79702974 # number of WriteReq accesses(hits+misses) 689system.cpu0.dcache.WriteReq_accesses::total 79702974 # number of WriteReq accesses(hits+misses) 690system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 966772 # number of SoftPFReq accesses(hits+misses) 691system.cpu0.dcache.SoftPFReq_accesses::total 966772 # number of SoftPFReq accesses(hits+misses) 692system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1134952 # number of WriteLineReq accesses(hits+misses) 693system.cpu0.dcache.WriteLineReq_accesses::total 1134952 # number of WriteLineReq accesses(hits+misses) 694system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2051024 # number of LoadLockedReq accesses(hits+misses) 695system.cpu0.dcache.LoadLockedReq_accesses::total 2051024 # number of LoadLockedReq accesses(hits+misses) 696system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2049767 # number of StoreCondReq accesses(hits+misses) 697system.cpu0.dcache.StoreCondReq_accesses::total 2049767 # number of StoreCondReq accesses(hits+misses) 698system.cpu0.dcache.demand_accesses::cpu0.data 171574635 # number of demand (read+write) accesses 699system.cpu0.dcache.demand_accesses::total 171574635 # number of demand (read+write) accesses 700system.cpu0.dcache.overall_accesses::cpu0.data 172541407 # number of overall (read+write) accesses 701system.cpu0.dcache.overall_accesses::total 172541407 # number of overall (read+write) accesses 702system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040704 # miss rate for ReadReq accesses 703system.cpu0.dcache.ReadReq_miss_rate::total 0.040704 # miss rate for ReadReq accesses 704system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030867 # miss rate for WriteReq accesses 705system.cpu0.dcache.WriteReq_miss_rate::total 0.030867 # miss rate for WriteReq accesses 706system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.684486 # miss rate for SoftPFReq accesses 707system.cpu0.dcache.SoftPFReq_miss_rate::total 0.684486 # miss rate for SoftPFReq accesses 708system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.747073 # miss rate for WriteLineReq accesses 709system.cpu0.dcache.WriteLineReq_miss_rate::total 0.747073 # miss rate for WriteLineReq accesses 710system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084613 # miss rate for LoadLockedReq accesses 711system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084613 # miss rate for LoadLockedReq accesses 712system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097865 # miss rate for StoreCondReq accesses 713system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097865 # miss rate for StoreCondReq accesses 714system.cpu0.dcache.demand_miss_rate::cpu0.data 0.040807 # miss rate for demand accesses 715system.cpu0.dcache.demand_miss_rate::total 0.040807 # miss rate for demand accesses 716system.cpu0.dcache.overall_miss_rate::cpu0.data 0.044414 # miss rate for overall accesses 717system.cpu0.dcache.overall_miss_rate::total 0.044414 # miss rate for overall accesses 718system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17362.374870 # average ReadReq miss latency 719system.cpu0.dcache.ReadReq_avg_miss_latency::total 17362.374870 # average ReadReq miss latency 720system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25220.074587 # average WriteReq miss latency 721system.cpu0.dcache.WriteReq_avg_miss_latency::total 25220.074587 # average WriteReq miss latency 722system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 60346.652640 # average WriteLineReq miss latency 723system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 60346.652640 # average WriteLineReq miss latency 724system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16484.243098 # average LoadLockedReq miss latency 725system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16484.243098 # average LoadLockedReq miss latency 726system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28412.814058 # average StoreCondReq miss latency 727system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28412.814058 # average StoreCondReq miss latency | 643system.cpu0.dcache.tags.tag_accesses 355154483 # Number of tag accesses 644system.cpu0.dcache.tags.data_accesses 355154483 # Number of data accesses 645system.cpu0.dcache.ReadReq_hits::cpu0.data 85976696 # number of ReadReq hits 646system.cpu0.dcache.ReadReq_hits::total 85976696 # number of ReadReq hits 647system.cpu0.dcache.WriteReq_hits::cpu0.data 76051356 # number of WriteReq hits 648system.cpu0.dcache.WriteReq_hits::total 76051356 # number of WriteReq hits 649system.cpu0.dcache.SoftPFReq_hits::cpu0.data 300861 # number of SoftPFReq hits 650system.cpu0.dcache.SoftPFReq_hits::total 300861 # number of SoftPFReq hits 651system.cpu0.dcache.WriteLineReq_hits::cpu0.data 281214 # number of WriteLineReq hits 652system.cpu0.dcache.WriteLineReq_hits::total 281214 # number of WriteLineReq hits 653system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1915398 # number of LoadLockedReq hits 654system.cpu0.dcache.LoadLockedReq_hits::total 1915398 # number of LoadLockedReq hits 655system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1894723 # number of StoreCondReq hits 656system.cpu0.dcache.StoreCondReq_hits::total 1894723 # number of StoreCondReq hits 657system.cpu0.dcache.demand_hits::cpu0.data 162309266 # number of demand (read+write) hits 658system.cpu0.dcache.demand_hits::total 162309266 # number of demand (read+write) hits 659system.cpu0.dcache.overall_hits::cpu0.data 162610127 # number of overall hits 660system.cpu0.dcache.overall_hits::total 162610127 # number of overall hits 661system.cpu0.dcache.ReadReq_misses::cpu0.data 3729679 # number of ReadReq misses 662system.cpu0.dcache.ReadReq_misses::total 3729679 # number of ReadReq misses 663system.cpu0.dcache.WriteReq_misses::cpu0.data 2481919 # number of WriteReq misses 664system.cpu0.dcache.WriteReq_misses::total 2481919 # number of WriteReq misses 665system.cpu0.dcache.SoftPFReq_misses::cpu0.data 681303 # number of SoftPFReq misses 666system.cpu0.dcache.SoftPFReq_misses::total 681303 # number of SoftPFReq misses 667system.cpu0.dcache.WriteLineReq_misses::cpu0.data 827220 # number of WriteLineReq misses 668system.cpu0.dcache.WriteLineReq_misses::total 827220 # number of WriteLineReq misses 669system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 176003 # number of LoadLockedReq misses 670system.cpu0.dcache.LoadLockedReq_misses::total 176003 # number of LoadLockedReq misses 671system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195484 # number of StoreCondReq misses 672system.cpu0.dcache.StoreCondReq_misses::total 195484 # number of StoreCondReq misses 673system.cpu0.dcache.demand_misses::cpu0.data 7038818 # number of demand (read+write) misses 674system.cpu0.dcache.demand_misses::total 7038818 # number of demand (read+write) misses 675system.cpu0.dcache.overall_misses::cpu0.data 7720121 # number of overall misses 676system.cpu0.dcache.overall_misses::total 7720121 # number of overall misses 677system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 57503024000 # number of ReadReq miss cycles 678system.cpu0.dcache.ReadReq_miss_latency::total 57503024000 # number of ReadReq miss cycles 679system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 50806938500 # number of WriteReq miss cycles 680system.cpu0.dcache.WriteReq_miss_latency::total 50806938500 # number of WriteReq miss cycles 681system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 27591387500 # number of WriteLineReq miss cycles 682system.cpu0.dcache.WriteLineReq_miss_latency::total 27591387500 # number of WriteLineReq miss cycles 683system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2577956500 # number of LoadLockedReq miss cycles 684system.cpu0.dcache.LoadLockedReq_miss_latency::total 2577956500 # number of LoadLockedReq miss cycles 685system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4885048500 # number of StoreCondReq miss cycles 686system.cpu0.dcache.StoreCondReq_miss_latency::total 4885048500 # number of StoreCondReq miss cycles 687system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3405000 # number of StoreCondFailReq miss cycles 688system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3405000 # number of StoreCondFailReq miss cycles 689system.cpu0.dcache.demand_miss_latency::cpu0.data 135901350000 # number of demand (read+write) miss cycles 690system.cpu0.dcache.demand_miss_latency::total 135901350000 # number of demand (read+write) miss cycles 691system.cpu0.dcache.overall_miss_latency::cpu0.data 135901350000 # number of overall miss cycles 692system.cpu0.dcache.overall_miss_latency::total 135901350000 # number of overall miss cycles 693system.cpu0.dcache.ReadReq_accesses::cpu0.data 89706375 # number of ReadReq accesses(hits+misses) 694system.cpu0.dcache.ReadReq_accesses::total 89706375 # number of ReadReq accesses(hits+misses) 695system.cpu0.dcache.WriteReq_accesses::cpu0.data 78533275 # number of WriteReq accesses(hits+misses) 696system.cpu0.dcache.WriteReq_accesses::total 78533275 # number of WriteReq accesses(hits+misses) 697system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 982164 # number of SoftPFReq accesses(hits+misses) 698system.cpu0.dcache.SoftPFReq_accesses::total 982164 # number of SoftPFReq accesses(hits+misses) 699system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1108434 # number of WriteLineReq accesses(hits+misses) 700system.cpu0.dcache.WriteLineReq_accesses::total 1108434 # number of WriteLineReq accesses(hits+misses) 701system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2091401 # number of LoadLockedReq accesses(hits+misses) 702system.cpu0.dcache.LoadLockedReq_accesses::total 2091401 # number of LoadLockedReq accesses(hits+misses) 703system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2090207 # number of StoreCondReq accesses(hits+misses) 704system.cpu0.dcache.StoreCondReq_accesses::total 2090207 # number of StoreCondReq accesses(hits+misses) 705system.cpu0.dcache.demand_accesses::cpu0.data 169348084 # number of demand (read+write) accesses 706system.cpu0.dcache.demand_accesses::total 169348084 # number of demand (read+write) accesses 707system.cpu0.dcache.overall_accesses::cpu0.data 170330248 # number of overall (read+write) accesses 708system.cpu0.dcache.overall_accesses::total 170330248 # number of overall (read+write) accesses 709system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041577 # miss rate for ReadReq accesses 710system.cpu0.dcache.ReadReq_miss_rate::total 0.041577 # miss rate for ReadReq accesses 711system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031603 # miss rate for WriteReq accesses 712system.cpu0.dcache.WriteReq_miss_rate::total 0.031603 # miss rate for WriteReq accesses 713system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.693675 # miss rate for SoftPFReq accesses 714system.cpu0.dcache.SoftPFReq_miss_rate::total 0.693675 # miss rate for SoftPFReq accesses 715system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.746296 # miss rate for WriteLineReq accesses 716system.cpu0.dcache.WriteLineReq_miss_rate::total 0.746296 # miss rate for WriteLineReq accesses 717system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084156 # miss rate for LoadLockedReq accesses 718system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084156 # miss rate for LoadLockedReq accesses 719system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.093524 # miss rate for StoreCondReq accesses 720system.cpu0.dcache.StoreCondReq_miss_rate::total 0.093524 # miss rate for StoreCondReq accesses 721system.cpu0.dcache.demand_miss_rate::cpu0.data 0.041564 # miss rate for demand accesses 722system.cpu0.dcache.demand_miss_rate::total 0.041564 # miss rate for demand accesses 723system.cpu0.dcache.overall_miss_rate::cpu0.data 0.045324 # miss rate for overall accesses 724system.cpu0.dcache.overall_miss_rate::total 0.045324 # miss rate for overall accesses 725system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15417.687152 # average ReadReq miss latency 726system.cpu0.dcache.ReadReq_avg_miss_latency::total 15417.687152 # average ReadReq miss latency 727system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20470.828621 # average WriteReq miss latency 728system.cpu0.dcache.WriteReq_avg_miss_latency::total 20470.828621 # average WriteReq miss latency 729system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33354.352530 # average WriteLineReq miss latency 730system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33354.352530 # average WriteLineReq miss latency 731system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14647.230445 # average LoadLockedReq miss latency 732system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14647.230445 # average LoadLockedReq miss latency 733system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24989.505535 # average StoreCondReq miss latency 734system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24989.505535 # average StoreCondReq miss latency |
| 728system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 729system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 735system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 736system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 730system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25328.955369 # average overall miss latency 731system.cpu0.dcache.demand_avg_miss_latency::total 25328.955369 # average overall miss latency 732system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23141.720496 # average overall miss latency 733system.cpu0.dcache.overall_avg_miss_latency::total 23141.720496 # average overall miss latency | 737system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19307.410704 # average overall miss latency 738system.cpu0.dcache.demand_avg_miss_latency::total 19307.410704 # average overall miss latency 739system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17603.525903 # average overall miss latency 740system.cpu0.dcache.overall_avg_miss_latency::total 17603.525903 # average overall miss latency |
| 734system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 735system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 736system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 737system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 738system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 739system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 741system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 742system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 743system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 744system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 745system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 746system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 740system.cpu0.dcache.writebacks::writebacks 5972043 # number of writebacks 741system.cpu0.dcache.writebacks::total 5972043 # number of writebacks 742system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 444932 # number of ReadReq MSHR hits 743system.cpu0.dcache.ReadReq_mshr_hits::total 444932 # number of ReadReq MSHR hits 744system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1012331 # number of WriteReq MSHR hits 745system.cpu0.dcache.WriteReq_mshr_hits::total 1012331 # number of WriteReq MSHR hits 746system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 90 # number of WriteLineReq MSHR hits 747system.cpu0.dcache.WriteLineReq_mshr_hits::total 90 # number of WriteLineReq MSHR hits 748system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 46565 # number of LoadLockedReq MSHR hits 749system.cpu0.dcache.LoadLockedReq_mshr_hits::total 46565 # number of LoadLockedReq MSHR hits 750system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 65 # number of StoreCondReq MSHR hits 751system.cpu0.dcache.StoreCondReq_mshr_hits::total 65 # number of StoreCondReq MSHR hits 752system.cpu0.dcache.demand_mshr_hits::cpu0.data 1457353 # number of demand (read+write) MSHR hits 753system.cpu0.dcache.demand_mshr_hits::total 1457353 # number of demand (read+write) MSHR hits 754system.cpu0.dcache.overall_mshr_hits::cpu0.data 1457353 # number of overall MSHR hits 755system.cpu0.dcache.overall_mshr_hits::total 1457353 # number of overall MSHR hits 756system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3248416 # number of ReadReq MSHR misses 757system.cpu0.dcache.ReadReq_mshr_misses::total 3248416 # number of ReadReq MSHR misses 758system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1447894 # number of WriteReq MSHR misses 759system.cpu0.dcache.WriteReq_mshr_misses::total 1447894 # number of WriteReq MSHR misses 760system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 660170 # number of SoftPFReq MSHR misses 761system.cpu0.dcache.SoftPFReq_mshr_misses::total 660170 # number of SoftPFReq MSHR misses 762system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 847802 # number of WriteLineReq MSHR misses 763system.cpu0.dcache.WriteLineReq_mshr_misses::total 847802 # number of WriteLineReq MSHR misses 764system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 126978 # number of LoadLockedReq MSHR misses 765system.cpu0.dcache.LoadLockedReq_mshr_misses::total 126978 # number of LoadLockedReq MSHR misses 766system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200535 # number of StoreCondReq MSHR misses 767system.cpu0.dcache.StoreCondReq_mshr_misses::total 200535 # number of StoreCondReq MSHR misses 768system.cpu0.dcache.demand_mshr_misses::cpu0.data 5544112 # number of demand (read+write) MSHR misses 769system.cpu0.dcache.demand_mshr_misses::total 5544112 # number of demand (read+write) MSHR misses 770system.cpu0.dcache.overall_mshr_misses::cpu0.data 6204282 # number of overall MSHR misses 771system.cpu0.dcache.overall_mshr_misses::total 6204282 # number of overall MSHR misses 772system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31552 # number of ReadReq MSHR uncacheable 773system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31552 # number of ReadReq MSHR uncacheable 774system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31148 # number of WriteReq MSHR uncacheable 775system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31148 # number of WriteReq MSHR uncacheable 776system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62700 # number of overall MSHR uncacheable misses 777system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62700 # number of overall MSHR uncacheable misses 778system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50756784000 # number of ReadReq MSHR miss cycles 779system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50756784000 # number of ReadReq MSHR miss cycles 780system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 36350818500 # number of WriteReq MSHR miss cycles 781system.cpu0.dcache.WriteReq_mshr_miss_latency::total 36350818500 # number of WriteReq MSHR miss cycles 782system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16579433500 # number of SoftPFReq MSHR miss cycles 783system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16579433500 # number of SoftPFReq MSHR miss cycles 784system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 50311370000 # number of WriteLineReq MSHR miss cycles 785system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 50311370000 # number of WriteLineReq MSHR miss cycles 786system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1783759500 # number of LoadLockedReq MSHR miss cycles 787system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1783759500 # number of LoadLockedReq MSHR miss cycles 788system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5494928000 # number of StoreCondReq MSHR miss cycles 789system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5494928000 # number of StoreCondReq MSHR miss cycles 790system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5416500 # number of StoreCondFailReq MSHR miss cycles 791system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5416500 # number of StoreCondFailReq MSHR miss cycles 792system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 137418972500 # number of demand (read+write) MSHR miss cycles 793system.cpu0.dcache.demand_mshr_miss_latency::total 137418972500 # number of demand (read+write) MSHR miss cycles 794system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 153998406000 # number of overall MSHR miss cycles 795system.cpu0.dcache.overall_mshr_miss_latency::total 153998406000 # number of overall MSHR miss cycles 796system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6041391000 # number of ReadReq MSHR uncacheable cycles 797system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6041391000 # number of ReadReq MSHR uncacheable cycles 798system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6041391000 # number of overall MSHR uncacheable cycles 799system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6041391000 # number of overall MSHR uncacheable cycles 800system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035800 # mshr miss rate for ReadReq accesses 801system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035800 # mshr miss rate for ReadReq accesses 802system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018166 # mshr miss rate for WriteReq accesses 803system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018166 # mshr miss rate for WriteReq accesses 804system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.682860 # mshr miss rate for SoftPFReq accesses 805system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.682860 # mshr miss rate for SoftPFReq accesses 806system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746994 # mshr miss rate for WriteLineReq accesses 807system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746994 # mshr miss rate for WriteLineReq accesses 808system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061910 # mshr miss rate for LoadLockedReq accesses 809system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061910 # mshr miss rate for LoadLockedReq accesses 810system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097833 # mshr miss rate for StoreCondReq accesses 811system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097833 # mshr miss rate for StoreCondReq accesses 812system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032313 # mshr miss rate for demand accesses 813system.cpu0.dcache.demand_mshr_miss_rate::total 0.032313 # mshr miss rate for demand accesses 814system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.035958 # mshr miss rate for overall accesses 815system.cpu0.dcache.overall_mshr_miss_rate::total 0.035958 # mshr miss rate for overall accesses 816system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15625.087427 # average ReadReq mshr miss latency 817system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15625.087427 # average ReadReq mshr miss latency 818system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25105.994292 # average WriteReq mshr miss latency 819system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25105.994292 # average WriteReq mshr miss latency 820system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25113.885060 # average SoftPFReq mshr miss latency 821system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25113.885060 # average SoftPFReq mshr miss latency 822system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 59343.301856 # average WriteLineReq mshr miss latency 823system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 59343.301856 # average WriteLineReq mshr miss latency 824system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14047.783868 # average LoadLockedReq mshr miss latency 825system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14047.783868 # average LoadLockedReq mshr miss latency 826system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27401.341412 # average StoreCondReq mshr miss latency 827system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27401.341412 # average StoreCondReq mshr miss latency | 747system.cpu0.dcache.writebacks::writebacks 6026220 # number of writebacks 748system.cpu0.dcache.writebacks::total 6026220 # number of writebacks 749system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 447326 # number of ReadReq MSHR hits 750system.cpu0.dcache.ReadReq_mshr_hits::total 447326 # number of ReadReq MSHR hits 751system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1020420 # number of WriteReq MSHR hits 752system.cpu0.dcache.WriteReq_mshr_hits::total 1020420 # number of WriteReq MSHR hits 753system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 73 # number of WriteLineReq MSHR hits 754system.cpu0.dcache.WriteLineReq_mshr_hits::total 73 # number of WriteLineReq MSHR hits 755system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 44988 # number of LoadLockedReq MSHR hits 756system.cpu0.dcache.LoadLockedReq_mshr_hits::total 44988 # number of LoadLockedReq MSHR hits 757system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 67 # number of StoreCondReq MSHR hits 758system.cpu0.dcache.StoreCondReq_mshr_hits::total 67 # number of StoreCondReq MSHR hits 759system.cpu0.dcache.demand_mshr_hits::cpu0.data 1467819 # number of demand (read+write) MSHR hits 760system.cpu0.dcache.demand_mshr_hits::total 1467819 # number of demand (read+write) MSHR hits 761system.cpu0.dcache.overall_mshr_hits::cpu0.data 1467819 # number of overall MSHR hits 762system.cpu0.dcache.overall_mshr_hits::total 1467819 # number of overall MSHR hits 763system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3282353 # number of ReadReq MSHR misses 764system.cpu0.dcache.ReadReq_mshr_misses::total 3282353 # number of ReadReq MSHR misses 765system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1461499 # number of WriteReq MSHR misses 766system.cpu0.dcache.WriteReq_mshr_misses::total 1461499 # number of WriteReq MSHR misses 767system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 679841 # number of SoftPFReq MSHR misses 768system.cpu0.dcache.SoftPFReq_mshr_misses::total 679841 # number of SoftPFReq MSHR misses 769system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 827147 # number of WriteLineReq MSHR misses 770system.cpu0.dcache.WriteLineReq_mshr_misses::total 827147 # number of WriteLineReq MSHR misses 771system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 131015 # number of LoadLockedReq MSHR misses 772system.cpu0.dcache.LoadLockedReq_mshr_misses::total 131015 # number of LoadLockedReq MSHR misses 773system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195417 # number of StoreCondReq MSHR misses 774system.cpu0.dcache.StoreCondReq_mshr_misses::total 195417 # number of StoreCondReq MSHR misses 775system.cpu0.dcache.demand_mshr_misses::cpu0.data 5570999 # number of demand (read+write) MSHR misses 776system.cpu0.dcache.demand_mshr_misses::total 5570999 # number of demand (read+write) MSHR misses 777system.cpu0.dcache.overall_mshr_misses::cpu0.data 6250840 # number of overall MSHR misses 778system.cpu0.dcache.overall_mshr_misses::total 6250840 # number of overall MSHR misses 779system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31702 # number of ReadReq MSHR uncacheable 780system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31702 # number of ReadReq MSHR uncacheable 781system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31225 # number of WriteReq MSHR uncacheable 782system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31225 # number of WriteReq MSHR uncacheable 783system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62927 # number of overall MSHR uncacheable misses 784system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62927 # number of overall MSHR uncacheable misses 785system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 45702695000 # number of ReadReq MSHR miss cycles 786system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45702695000 # number of ReadReq MSHR miss cycles 787system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 29281044500 # number of WriteReq MSHR miss cycles 788system.cpu0.dcache.WriteReq_mshr_miss_latency::total 29281044500 # number of WriteReq MSHR miss cycles 789system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14665959000 # number of SoftPFReq MSHR miss cycles 790system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14665959000 # number of SoftPFReq MSHR miss cycles 791system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 26759895500 # number of WriteLineReq MSHR miss cycles 792system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 26759895500 # number of WriteLineReq MSHR miss cycles 793system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1703041500 # number of LoadLockedReq MSHR miss cycles 794system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1703041500 # number of LoadLockedReq MSHR miss cycles 795system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4687173500 # number of StoreCondReq MSHR miss cycles 796system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4687173500 # number of StoreCondReq MSHR miss cycles 797system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3267500 # number of StoreCondFailReq MSHR miss cycles 798system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3267500 # number of StoreCondFailReq MSHR miss cycles 799system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 101743635000 # number of demand (read+write) MSHR miss cycles 800system.cpu0.dcache.demand_mshr_miss_latency::total 101743635000 # number of demand (read+write) MSHR miss cycles 801system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 116409594000 # number of overall MSHR miss cycles 802system.cpu0.dcache.overall_mshr_miss_latency::total 116409594000 # number of overall MSHR miss cycles 803system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6136923000 # number of ReadReq MSHR uncacheable cycles 804system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6136923000 # number of ReadReq MSHR uncacheable cycles 805system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6136923000 # number of overall MSHR uncacheable cycles 806system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6136923000 # number of overall MSHR uncacheable cycles 807system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036590 # mshr miss rate for ReadReq accesses 808system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036590 # mshr miss rate for ReadReq accesses 809system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018610 # mshr miss rate for WriteReq accesses 810system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018610 # mshr miss rate for WriteReq accesses 811system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.692187 # mshr miss rate for SoftPFReq accesses 812system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.692187 # mshr miss rate for SoftPFReq accesses 813system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746230 # mshr miss rate for WriteLineReq accesses 814system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746230 # mshr miss rate for WriteLineReq accesses 815system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.062645 # mshr miss rate for LoadLockedReq accesses 816system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.062645 # mshr miss rate for LoadLockedReq accesses 817system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.093492 # mshr miss rate for StoreCondReq accesses 818system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.093492 # mshr miss rate for StoreCondReq accesses 819system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032897 # mshr miss rate for demand accesses 820system.cpu0.dcache.demand_mshr_miss_rate::total 0.032897 # mshr miss rate for demand accesses 821system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036698 # mshr miss rate for overall accesses 822system.cpu0.dcache.overall_mshr_miss_rate::total 0.036698 # mshr miss rate for overall accesses 823system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13923.759876 # average ReadReq mshr miss latency 824system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13923.759876 # average ReadReq mshr miss latency 825system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20034.939812 # average WriteReq mshr miss latency 826system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20034.939812 # average WriteReq mshr miss latency 827system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21572.630953 # average SoftPFReq mshr miss latency 828system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21572.630953 # average SoftPFReq mshr miss latency 829system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32352.043228 # average WriteLineReq mshr miss latency 830system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32352.043228 # average WriteLineReq mshr miss latency 831system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12998.828378 # average LoadLockedReq mshr miss latency 832system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12998.828378 # average LoadLockedReq mshr miss latency 833system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23985.495121 # average StoreCondReq mshr miss latency 834system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23985.495121 # average StoreCondReq mshr miss latency |
| 828system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 829system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 835system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 836system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 830system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24786.471215 # average overall mshr miss latency 831system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24786.471215 # average overall mshr miss latency 832system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24821.309863 # average overall mshr miss latency 833system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24821.309863 # average overall mshr miss latency 834system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191474.106237 # average ReadReq mshr uncacheable latency 835system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191474.106237 # average ReadReq mshr uncacheable latency 836system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96353.923445 # average overall mshr uncacheable latency 837system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96353.923445 # average overall mshr uncacheable latency 838system.cpu0.icache.tags.replacements 10516028 # number of replacements 839system.cpu0.icache.tags.tagsinuse 511.897153 # Cycle average of tags in use 840system.cpu0.icache.tags.total_refs 249911266 # Total number of references to valid blocks. 841system.cpu0.icache.tags.sampled_refs 10516540 # Sample count of references to valid blocks. 842system.cpu0.icache.tags.avg_refs 23.763640 # Average number of references to valid blocks. 843system.cpu0.icache.tags.warmup_cycle 33054279000 # Cycle when the warmup percentage was hit. 844system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.897153 # Average occupied blocks per requestor 845system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999799 # Average percentage of cache occupancy 846system.cpu0.icache.tags.occ_percent::total 0.999799 # Average percentage of cache occupancy | 837system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18263.086208 # average overall mshr miss latency 838system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18263.086208 # average overall mshr miss latency 839system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18623.032104 # average overall mshr miss latency 840system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18623.032104 # average overall mshr miss latency 841system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193581.572141 # average ReadReq mshr uncacheable latency 842system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193581.572141 # average ReadReq mshr uncacheable latency 843system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 97524.480748 # average overall mshr uncacheable latency 844system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 97524.480748 # average overall mshr uncacheable latency 845system.cpu0.icache.tags.replacements 9817579 # number of replacements 846system.cpu0.icache.tags.tagsinuse 511.932451 # Cycle average of tags in use 847system.cpu0.icache.tags.total_refs 249208397 # Total number of references to valid blocks. 848system.cpu0.icache.tags.sampled_refs 9818091 # Sample count of references to valid blocks. 849system.cpu0.icache.tags.avg_refs 25.382572 # Average number of references to valid blocks. 850system.cpu0.icache.tags.warmup_cycle 22021065000 # Cycle when the warmup percentage was hit. 851system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932451 # Average occupied blocks per requestor 852system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999868 # Average percentage of cache occupancy 853system.cpu0.icache.tags.occ_percent::total 0.999868 # Average percentage of cache occupancy |
| 847system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 854system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 848system.cpu0.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id 849system.cpu0.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id 850system.cpu0.icache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id | 855system.cpu0.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id 856system.cpu0.icache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id 857system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id |
| 851system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 858system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 852system.cpu0.icache.tags.tag_accesses 531372181 # Number of tag accesses 853system.cpu0.icache.tags.data_accesses 531372181 # Number of data accesses 854system.cpu0.icache.ReadReq_hits::cpu0.inst 249911266 # number of ReadReq hits 855system.cpu0.icache.ReadReq_hits::total 249911266 # number of ReadReq hits 856system.cpu0.icache.demand_hits::cpu0.inst 249911266 # number of demand (read+write) hits 857system.cpu0.icache.demand_hits::total 249911266 # number of demand (read+write) hits 858system.cpu0.icache.overall_hits::cpu0.inst 249911266 # number of overall hits 859system.cpu0.icache.overall_hits::total 249911266 # number of overall hits 860system.cpu0.icache.ReadReq_misses::cpu0.inst 10516550 # number of ReadReq misses 861system.cpu0.icache.ReadReq_misses::total 10516550 # number of ReadReq misses 862system.cpu0.icache.demand_misses::cpu0.inst 10516550 # number of demand (read+write) misses 863system.cpu0.icache.demand_misses::total 10516550 # number of demand (read+write) misses 864system.cpu0.icache.overall_misses::cpu0.inst 10516550 # number of overall misses 865system.cpu0.icache.overall_misses::total 10516550 # number of overall misses 866system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 109481334000 # number of ReadReq miss cycles 867system.cpu0.icache.ReadReq_miss_latency::total 109481334000 # number of ReadReq miss cycles 868system.cpu0.icache.demand_miss_latency::cpu0.inst 109481334000 # number of demand (read+write) miss cycles 869system.cpu0.icache.demand_miss_latency::total 109481334000 # number of demand (read+write) miss cycles 870system.cpu0.icache.overall_miss_latency::cpu0.inst 109481334000 # number of overall miss cycles 871system.cpu0.icache.overall_miss_latency::total 109481334000 # number of overall miss cycles 872system.cpu0.icache.ReadReq_accesses::cpu0.inst 260427816 # number of ReadReq accesses(hits+misses) 873system.cpu0.icache.ReadReq_accesses::total 260427816 # number of ReadReq accesses(hits+misses) 874system.cpu0.icache.demand_accesses::cpu0.inst 260427816 # number of demand (read+write) accesses 875system.cpu0.icache.demand_accesses::total 260427816 # number of demand (read+write) accesses 876system.cpu0.icache.overall_accesses::cpu0.inst 260427816 # number of overall (read+write) accesses 877system.cpu0.icache.overall_accesses::total 260427816 # number of overall (read+write) accesses 878system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.040382 # miss rate for ReadReq accesses 879system.cpu0.icache.ReadReq_miss_rate::total 0.040382 # miss rate for ReadReq accesses 880system.cpu0.icache.demand_miss_rate::cpu0.inst 0.040382 # miss rate for demand accesses 881system.cpu0.icache.demand_miss_rate::total 0.040382 # miss rate for demand accesses 882system.cpu0.icache.overall_miss_rate::cpu0.inst 0.040382 # miss rate for overall accesses 883system.cpu0.icache.overall_miss_rate::total 0.040382 # miss rate for overall accesses 884system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10410.384965 # average ReadReq miss latency 885system.cpu0.icache.ReadReq_avg_miss_latency::total 10410.384965 # average ReadReq miss latency 886system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10410.384965 # average overall miss latency 887system.cpu0.icache.demand_avg_miss_latency::total 10410.384965 # average overall miss latency 888system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10410.384965 # average overall miss latency 889system.cpu0.icache.overall_avg_miss_latency::total 10410.384965 # average overall miss latency | 859system.cpu0.icache.tags.tag_accesses 527871096 # Number of tag accesses 860system.cpu0.icache.tags.data_accesses 527871096 # Number of data accesses 861system.cpu0.icache.ReadReq_hits::cpu0.inst 249208397 # number of ReadReq hits 862system.cpu0.icache.ReadReq_hits::total 249208397 # number of ReadReq hits 863system.cpu0.icache.demand_hits::cpu0.inst 249208397 # number of demand (read+write) hits 864system.cpu0.icache.demand_hits::total 249208397 # number of demand (read+write) hits 865system.cpu0.icache.overall_hits::cpu0.inst 249208397 # number of overall hits 866system.cpu0.icache.overall_hits::total 249208397 # number of overall hits 867system.cpu0.icache.ReadReq_misses::cpu0.inst 9818101 # number of ReadReq misses 868system.cpu0.icache.ReadReq_misses::total 9818101 # number of ReadReq misses 869system.cpu0.icache.demand_misses::cpu0.inst 9818101 # number of demand (read+write) misses 870system.cpu0.icache.demand_misses::total 9818101 # number of demand (read+write) misses 871system.cpu0.icache.overall_misses::cpu0.inst 9818101 # number of overall misses 872system.cpu0.icache.overall_misses::total 9818101 # number of overall misses 873system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 99002118000 # number of ReadReq miss cycles 874system.cpu0.icache.ReadReq_miss_latency::total 99002118000 # number of ReadReq miss cycles 875system.cpu0.icache.demand_miss_latency::cpu0.inst 99002118000 # number of demand (read+write) miss cycles 876system.cpu0.icache.demand_miss_latency::total 99002118000 # number of demand (read+write) miss cycles 877system.cpu0.icache.overall_miss_latency::cpu0.inst 99002118000 # number of overall miss cycles 878system.cpu0.icache.overall_miss_latency::total 99002118000 # number of overall miss cycles 879system.cpu0.icache.ReadReq_accesses::cpu0.inst 259026498 # number of ReadReq accesses(hits+misses) 880system.cpu0.icache.ReadReq_accesses::total 259026498 # number of ReadReq accesses(hits+misses) 881system.cpu0.icache.demand_accesses::cpu0.inst 259026498 # number of demand (read+write) accesses 882system.cpu0.icache.demand_accesses::total 259026498 # number of demand (read+write) accesses 883system.cpu0.icache.overall_accesses::cpu0.inst 259026498 # number of overall (read+write) accesses 884system.cpu0.icache.overall_accesses::total 259026498 # number of overall (read+write) accesses 885system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037904 # miss rate for ReadReq accesses 886system.cpu0.icache.ReadReq_miss_rate::total 0.037904 # miss rate for ReadReq accesses 887system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037904 # miss rate for demand accesses 888system.cpu0.icache.demand_miss_rate::total 0.037904 # miss rate for demand accesses 889system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037904 # miss rate for overall accesses 890system.cpu0.icache.overall_miss_rate::total 0.037904 # miss rate for overall accesses 891system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10083.632059 # average ReadReq miss latency 892system.cpu0.icache.ReadReq_avg_miss_latency::total 10083.632059 # average ReadReq miss latency 893system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10083.632059 # average overall miss latency 894system.cpu0.icache.demand_avg_miss_latency::total 10083.632059 # average overall miss latency 895system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10083.632059 # average overall miss latency 896system.cpu0.icache.overall_avg_miss_latency::total 10083.632059 # average overall miss latency |
| 890system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 891system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 892system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 893system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 894system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 895system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 897system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 898system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 899system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 900system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 901system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 902system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 896system.cpu0.icache.writebacks::writebacks 10516028 # number of writebacks 897system.cpu0.icache.writebacks::total 10516028 # number of writebacks 898system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10516550 # number of ReadReq MSHR misses 899system.cpu0.icache.ReadReq_mshr_misses::total 10516550 # number of ReadReq MSHR misses 900system.cpu0.icache.demand_mshr_misses::cpu0.inst 10516550 # number of demand (read+write) MSHR misses 901system.cpu0.icache.demand_mshr_misses::total 10516550 # number of demand (read+write) MSHR misses 902system.cpu0.icache.overall_mshr_misses::cpu0.inst 10516550 # number of overall MSHR misses 903system.cpu0.icache.overall_mshr_misses::total 10516550 # number of overall MSHR misses 904system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 905system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable 906system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 907system.cpu0.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses 908system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 104223059500 # number of ReadReq MSHR miss cycles 909system.cpu0.icache.ReadReq_mshr_miss_latency::total 104223059500 # number of ReadReq MSHR miss cycles 910system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 104223059500 # number of demand (read+write) MSHR miss cycles 911system.cpu0.icache.demand_mshr_miss_latency::total 104223059500 # number of demand (read+write) MSHR miss cycles 912system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 104223059500 # number of overall MSHR miss cycles 913system.cpu0.icache.overall_mshr_miss_latency::total 104223059500 # number of overall MSHR miss cycles 914system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of ReadReq MSHR uncacheable cycles 915system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7414627000 # number of ReadReq MSHR uncacheable cycles 916system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7414627000 # number of overall MSHR uncacheable cycles 917system.cpu0.icache.overall_mshr_uncacheable_latency::total 7414627000 # number of overall MSHR uncacheable cycles 918system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.040382 # mshr miss rate for ReadReq accesses 919system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.040382 # mshr miss rate for ReadReq accesses 920system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.040382 # mshr miss rate for demand accesses 921system.cpu0.icache.demand_mshr_miss_rate::total 0.040382 # mshr miss rate for demand accesses 922system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.040382 # mshr miss rate for overall accesses 923system.cpu0.icache.overall_mshr_miss_rate::total 0.040382 # mshr miss rate for overall accesses 924system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9910.385012 # average ReadReq mshr miss latency 925system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9910.385012 # average ReadReq mshr miss latency 926system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9910.385012 # average overall mshr miss latency 927system.cpu0.icache.demand_avg_mshr_miss_latency::total 9910.385012 # average overall mshr miss latency 928system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9910.385012 # average overall mshr miss latency 929system.cpu0.icache.overall_avg_mshr_miss_latency::total 9910.385012 # average overall mshr miss latency 930system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency 931system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency 932system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency 933system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency 934system.cpu0.l2cache.prefetcher.num_hwpf_issued 8036343 # number of hwpf issued 935system.cpu0.l2cache.prefetcher.pfIdentified 8037705 # number of prefetch candidates identified 936system.cpu0.l2cache.prefetcher.pfBufferHit 1205 # number of redundant prefetches already in prefetch queue | 903system.cpu0.icache.writebacks::writebacks 9817579 # number of writebacks 904system.cpu0.icache.writebacks::total 9817579 # number of writebacks 905system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9818101 # number of ReadReq MSHR misses 906system.cpu0.icache.ReadReq_mshr_misses::total 9818101 # number of ReadReq MSHR misses 907system.cpu0.icache.demand_mshr_misses::cpu0.inst 9818101 # number of demand (read+write) MSHR misses 908system.cpu0.icache.demand_mshr_misses::total 9818101 # number of demand (read+write) MSHR misses 909system.cpu0.icache.overall_mshr_misses::cpu0.inst 9818101 # number of overall MSHR misses 910system.cpu0.icache.overall_mshr_misses::total 9818101 # number of overall MSHR misses 911system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52299 # number of ReadReq MSHR uncacheable 912system.cpu0.icache.ReadReq_mshr_uncacheable::total 52299 # number of ReadReq MSHR uncacheable 913system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52299 # number of overall MSHR uncacheable misses 914system.cpu0.icache.overall_mshr_uncacheable_misses::total 52299 # number of overall MSHR uncacheable misses 915system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 94093068000 # number of ReadReq MSHR miss cycles 916system.cpu0.icache.ReadReq_mshr_miss_latency::total 94093068000 # number of ReadReq MSHR miss cycles 917system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 94093068000 # number of demand (read+write) MSHR miss cycles 918system.cpu0.icache.demand_mshr_miss_latency::total 94093068000 # number of demand (read+write) MSHR miss cycles 919system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 94093068000 # number of overall MSHR miss cycles 920system.cpu0.icache.overall_mshr_miss_latency::total 94093068000 # number of overall MSHR miss cycles 921system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4837195500 # number of ReadReq MSHR uncacheable cycles 922system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4837195500 # number of ReadReq MSHR uncacheable cycles 923system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4837195500 # number of overall MSHR uncacheable cycles 924system.cpu0.icache.overall_mshr_uncacheable_latency::total 4837195500 # number of overall MSHR uncacheable cycles 925system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.037904 # mshr miss rate for ReadReq accesses 926system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.037904 # mshr miss rate for ReadReq accesses 927system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.037904 # mshr miss rate for demand accesses 928system.cpu0.icache.demand_mshr_miss_rate::total 0.037904 # mshr miss rate for demand accesses 929system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.037904 # mshr miss rate for overall accesses 930system.cpu0.icache.overall_mshr_miss_rate::total 0.037904 # mshr miss rate for overall accesses 931system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9583.632110 # average ReadReq mshr miss latency 932system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9583.632110 # average ReadReq mshr miss latency 933system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9583.632110 # average overall mshr miss latency 934system.cpu0.icache.demand_avg_mshr_miss_latency::total 9583.632110 # average overall mshr miss latency 935system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9583.632110 # average overall mshr miss latency 936system.cpu0.icache.overall_avg_mshr_miss_latency::total 9583.632110 # average overall mshr miss latency 937system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92491.166179 # average ReadReq mshr uncacheable latency 938system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92491.166179 # average ReadReq mshr uncacheable latency 939system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92491.166179 # average overall mshr uncacheable latency 940system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92491.166179 # average overall mshr uncacheable latency 941system.cpu0.l2cache.prefetcher.num_hwpf_issued 8242304 # number of hwpf issued 942system.cpu0.l2cache.prefetcher.pfIdentified 8243665 # number of prefetch candidates identified 943system.cpu0.l2cache.prefetcher.pfBufferHit 1198 # number of redundant prefetches already in prefetch queue |
| 937system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 938system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 944system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 945system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 939system.cpu0.l2cache.prefetcher.pfSpanPage 1038823 # number of prefetches not generated due to page crossing 940system.cpu0.l2cache.tags.replacements 2850300 # number of replacements 941system.cpu0.l2cache.tags.tagsinuse 16126.746563 # Cycle average of tags in use 942system.cpu0.l2cache.tags.total_refs 26039957 # Total number of references to valid blocks. 943system.cpu0.l2cache.tags.sampled_refs 2866458 # Sample count of references to valid blocks. 944system.cpu0.l2cache.tags.avg_refs 9.084367 # Average number of references to valid blocks. 945system.cpu0.l2cache.tags.warmup_cycle 8707838500 # Cycle when the warmup percentage was hit. 946system.cpu0.l2cache.tags.occ_blocks::writebacks 15278.163009 # Average occupied blocks per requestor 947system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 75.302883 # Average occupied blocks per requestor 948system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 76.950246 # Average occupied blocks per requestor 949system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 696.330425 # Average occupied blocks per requestor 950system.cpu0.l2cache.tags.occ_percent::writebacks 0.932505 # Average percentage of cache occupancy 951system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004596 # Average percentage of cache occupancy 952system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004697 # Average percentage of cache occupancy 953system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.042501 # Average percentage of cache occupancy 954system.cpu0.l2cache.tags.occ_percent::total 0.984298 # Average percentage of cache occupancy 955system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1240 # Occupied blocks per task id 956system.cpu0.l2cache.tags.occ_task_id_blocks::1023 58 # Occupied blocks per task id 957system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14860 # Occupied blocks per task id 958system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 23 # Occupied blocks per task id 959system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 522 # Occupied blocks per task id 960system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 622 # Occupied blocks per task id 961system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 73 # Occupied blocks per task id 962system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 14 # Occupied blocks per task id 963system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 43 # Occupied blocks per task id 964system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 965system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 966system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1092 # Occupied blocks per task id 967system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5314 # Occupied blocks per task id 968system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7823 # Occupied blocks per task id 969system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 536 # Occupied blocks per task id 970system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.075684 # Percentage of cache occupancy per task id 971system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003540 # Percentage of cache occupancy per task id 972system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.906982 # Percentage of cache occupancy per task id 973system.cpu0.l2cache.tags.tag_accesses 554897291 # Number of tag accesses 974system.cpu0.l2cache.tags.data_accesses 554897291 # Number of data accesses 975system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 569819 # number of ReadReq hits 976system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 172472 # number of ReadReq hits 977system.cpu0.l2cache.ReadReq_hits::total 742291 # number of ReadReq hits 978system.cpu0.l2cache.WritebackDirty_hits::writebacks 3893367 # number of WritebackDirty hits 979system.cpu0.l2cache.WritebackDirty_hits::total 3893367 # number of WritebackDirty hits 980system.cpu0.l2cache.WritebackClean_hits::writebacks 12591574 # number of WritebackClean hits 981system.cpu0.l2cache.WritebackClean_hits::total 12591574 # number of WritebackClean hits 982system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 369 # number of UpgradeReq hits 983system.cpu0.l2cache.UpgradeReq_hits::total 369 # number of UpgradeReq hits 984system.cpu0.l2cache.ReadExReq_hits::cpu0.data 917893 # number of ReadExReq hits 985system.cpu0.l2cache.ReadExReq_hits::total 917893 # number of ReadExReq hits 986system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9767058 # number of ReadCleanReq hits 987system.cpu0.l2cache.ReadCleanReq_hits::total 9767058 # number of ReadCleanReq hits 988system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3005656 # number of ReadSharedReq hits 989system.cpu0.l2cache.ReadSharedReq_hits::total 3005656 # number of ReadSharedReq hits 990system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 229746 # number of InvalidateReq hits 991system.cpu0.l2cache.InvalidateReq_hits::total 229746 # number of InvalidateReq hits 992system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 569819 # number of demand (read+write) hits 993system.cpu0.l2cache.demand_hits::cpu0.itb.walker 172472 # number of demand (read+write) hits 994system.cpu0.l2cache.demand_hits::cpu0.inst 9767058 # number of demand (read+write) hits 995system.cpu0.l2cache.demand_hits::cpu0.data 3923549 # number of demand (read+write) hits 996system.cpu0.l2cache.demand_hits::total 14432898 # number of demand (read+write) hits 997system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 569819 # number of overall hits 998system.cpu0.l2cache.overall_hits::cpu0.itb.walker 172472 # number of overall hits 999system.cpu0.l2cache.overall_hits::cpu0.inst 9767058 # number of overall hits 1000system.cpu0.l2cache.overall_hits::cpu0.data 3923549 # number of overall hits 1001system.cpu0.l2cache.overall_hits::total 14432898 # number of overall hits 1002system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11861 # number of ReadReq misses 1003system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8276 # number of ReadReq misses 1004system.cpu0.l2cache.ReadReq_misses::total 20137 # number of ReadReq misses 1005system.cpu0.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses 1006system.cpu0.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses 1007system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 260415 # number of UpgradeReq misses 1008system.cpu0.l2cache.UpgradeReq_misses::total 260415 # number of UpgradeReq misses 1009system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 200530 # number of SCUpgradeReq misses 1010system.cpu0.l2cache.SCUpgradeReq_misses::total 200530 # number of SCUpgradeReq misses 1011system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses 1012system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 1013system.cpu0.l2cache.ReadExReq_misses::cpu0.data 278151 # number of ReadExReq misses 1014system.cpu0.l2cache.ReadExReq_misses::total 278151 # number of ReadExReq misses 1015system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 749491 # number of ReadCleanReq misses 1016system.cpu0.l2cache.ReadCleanReq_misses::total 749491 # number of ReadCleanReq misses 1017system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1029564 # number of ReadSharedReq misses 1018system.cpu0.l2cache.ReadSharedReq_misses::total 1029564 # number of ReadSharedReq misses 1019system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 615811 # number of InvalidateReq misses 1020system.cpu0.l2cache.InvalidateReq_misses::total 615811 # number of InvalidateReq misses 1021system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11861 # number of demand (read+write) misses 1022system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8276 # number of demand (read+write) misses 1023system.cpu0.l2cache.demand_misses::cpu0.inst 749491 # number of demand (read+write) misses 1024system.cpu0.l2cache.demand_misses::cpu0.data 1307715 # number of demand (read+write) misses 1025system.cpu0.l2cache.demand_misses::total 2077343 # number of demand (read+write) misses 1026system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11861 # number of overall misses 1027system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8276 # number of overall misses 1028system.cpu0.l2cache.overall_misses::cpu0.inst 749491 # number of overall misses 1029system.cpu0.l2cache.overall_misses::cpu0.data 1307715 # number of overall misses 1030system.cpu0.l2cache.overall_misses::total 2077343 # number of overall misses 1031system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 476400500 # number of ReadReq miss cycles 1032system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 367251000 # number of ReadReq miss cycles 1033system.cpu0.l2cache.ReadReq_miss_latency::total 843651500 # number of ReadReq miss cycles 1034system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3484637000 # number of UpgradeReq miss cycles 1035system.cpu0.l2cache.UpgradeReq_miss_latency::total 3484637000 # number of UpgradeReq miss cycles 1036system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2105132000 # number of SCUpgradeReq miss cycles 1037system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2105132000 # number of SCUpgradeReq miss cycles 1038system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 5326000 # number of SCUpgradeFailReq miss cycles 1039system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 5326000 # number of SCUpgradeFailReq miss cycles 1040system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 18710306493 # number of ReadExReq miss cycles 1041system.cpu0.l2cache.ReadExReq_miss_latency::total 18710306493 # number of ReadExReq miss cycles 1042system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 29430808500 # number of ReadCleanReq miss cycles 1043system.cpu0.l2cache.ReadCleanReq_miss_latency::total 29430808500 # number of ReadCleanReq miss cycles 1044system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 43223836490 # number of ReadSharedReq miss cycles 1045system.cpu0.l2cache.ReadSharedReq_miss_latency::total 43223836490 # number of ReadSharedReq miss cycles 1046system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 408693500 # number of InvalidateReq miss cycles 1047system.cpu0.l2cache.InvalidateReq_miss_latency::total 408693500 # number of InvalidateReq miss cycles 1048system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 476400500 # number of demand (read+write) miss cycles 1049system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 367251000 # number of demand (read+write) miss cycles 1050system.cpu0.l2cache.demand_miss_latency::cpu0.inst 29430808500 # number of demand (read+write) miss cycles 1051system.cpu0.l2cache.demand_miss_latency::cpu0.data 61934142983 # number of demand (read+write) miss cycles 1052system.cpu0.l2cache.demand_miss_latency::total 92208602983 # number of demand (read+write) miss cycles 1053system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 476400500 # number of overall miss cycles 1054system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 367251000 # number of overall miss cycles 1055system.cpu0.l2cache.overall_miss_latency::cpu0.inst 29430808500 # number of overall miss cycles 1056system.cpu0.l2cache.overall_miss_latency::cpu0.data 61934142983 # number of overall miss cycles 1057system.cpu0.l2cache.overall_miss_latency::total 92208602983 # number of overall miss cycles 1058system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 581680 # number of ReadReq accesses(hits+misses) 1059system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 180748 # number of ReadReq accesses(hits+misses) 1060system.cpu0.l2cache.ReadReq_accesses::total 762428 # number of ReadReq accesses(hits+misses) 1061system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3893369 # number of WritebackDirty accesses(hits+misses) 1062system.cpu0.l2cache.WritebackDirty_accesses::total 3893369 # number of WritebackDirty accesses(hits+misses) 1063system.cpu0.l2cache.WritebackClean_accesses::writebacks 12591574 # number of WritebackClean accesses(hits+misses) 1064system.cpu0.l2cache.WritebackClean_accesses::total 12591574 # number of WritebackClean accesses(hits+misses) 1065system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 260784 # number of UpgradeReq accesses(hits+misses) 1066system.cpu0.l2cache.UpgradeReq_accesses::total 260784 # number of UpgradeReq accesses(hits+misses) 1067system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 200530 # number of SCUpgradeReq accesses(hits+misses) 1068system.cpu0.l2cache.SCUpgradeReq_accesses::total 200530 # number of SCUpgradeReq accesses(hits+misses) 1069system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 1070system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 1071system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1196044 # number of ReadExReq accesses(hits+misses) 1072system.cpu0.l2cache.ReadExReq_accesses::total 1196044 # number of ReadExReq accesses(hits+misses) 1073system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 10516549 # number of ReadCleanReq accesses(hits+misses) 1074system.cpu0.l2cache.ReadCleanReq_accesses::total 10516549 # number of ReadCleanReq accesses(hits+misses) 1075system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4035220 # number of ReadSharedReq accesses(hits+misses) 1076system.cpu0.l2cache.ReadSharedReq_accesses::total 4035220 # number of ReadSharedReq accesses(hits+misses) 1077system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 845557 # number of InvalidateReq accesses(hits+misses) 1078system.cpu0.l2cache.InvalidateReq_accesses::total 845557 # number of InvalidateReq accesses(hits+misses) 1079system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 581680 # number of demand (read+write) accesses 1080system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 180748 # number of demand (read+write) accesses 1081system.cpu0.l2cache.demand_accesses::cpu0.inst 10516549 # number of demand (read+write) accesses 1082system.cpu0.l2cache.demand_accesses::cpu0.data 5231264 # number of demand (read+write) accesses 1083system.cpu0.l2cache.demand_accesses::total 16510241 # number of demand (read+write) accesses 1084system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 581680 # number of overall (read+write) accesses 1085system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 180748 # number of overall (read+write) accesses 1086system.cpu0.l2cache.overall_accesses::cpu0.inst 10516549 # number of overall (read+write) accesses 1087system.cpu0.l2cache.overall_accesses::cpu0.data 5231264 # number of overall (read+write) accesses 1088system.cpu0.l2cache.overall_accesses::total 16510241 # number of overall (read+write) accesses 1089system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020391 # miss rate for ReadReq accesses 1090system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.045788 # miss rate for ReadReq accesses 1091system.cpu0.l2cache.ReadReq_miss_rate::total 0.026412 # miss rate for ReadReq accesses 1092system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses 1093system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses 1094system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.998585 # miss rate for UpgradeReq accesses 1095system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.998585 # miss rate for UpgradeReq accesses | 946system.cpu0.l2cache.prefetcher.pfSpanPage 1073071 # number of prefetches not generated due to page crossing 947system.cpu0.l2cache.tags.replacements 2829183 # number of replacements 948system.cpu0.l2cache.tags.tagsinuse 16163.343057 # Cycle average of tags in use 949system.cpu0.l2cache.tags.total_refs 24764914 # Total number of references to valid blocks. 950system.cpu0.l2cache.tags.sampled_refs 2845343 # Sample count of references to valid blocks. 951system.cpu0.l2cache.tags.avg_refs 8.703666 # Average number of references to valid blocks. 952system.cpu0.l2cache.tags.warmup_cycle 5659477500 # Cycle when the warmup percentage was hit. 953system.cpu0.l2cache.tags.occ_blocks::writebacks 15257.249232 # Average occupied blocks per requestor 954system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.561913 # Average occupied blocks per requestor 955system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 60.708141 # Average occupied blocks per requestor 956system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 787.823770 # Average occupied blocks per requestor 957system.cpu0.l2cache.tags.occ_percent::writebacks 0.931229 # Average percentage of cache occupancy 958system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003513 # Average percentage of cache occupancy 959system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003705 # Average percentage of cache occupancy 960system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.048085 # Average percentage of cache occupancy 961system.cpu0.l2cache.tags.occ_percent::total 0.986532 # Average percentage of cache occupancy 962system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1356 # Occupied blocks per task id 963system.cpu0.l2cache.tags.occ_task_id_blocks::1023 56 # Occupied blocks per task id 964system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14748 # Occupied blocks per task id 965system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id 966system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 123 # Occupied blocks per task id 967system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 574 # Occupied blocks per task id 968system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 643 # Occupied blocks per task id 969system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 23 # Occupied blocks per task id 970system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 22 # Occupied blocks per task id 971system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id 972system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id 973system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1176 # Occupied blocks per task id 974system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2616 # Occupied blocks per task id 975system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5298 # Occupied blocks per task id 976system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5548 # Occupied blocks per task id 977system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.082764 # Percentage of cache occupancy per task id 978system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003418 # Percentage of cache occupancy per task id 979system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.900146 # Percentage of cache occupancy per task id 980system.cpu0.l2cache.tags.tag_accesses 533961635 # Number of tag accesses 981system.cpu0.l2cache.tags.data_accesses 533961635 # Number of data accesses 982system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 561309 # number of ReadReq hits 983system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 167224 # number of ReadReq hits 984system.cpu0.l2cache.ReadReq_hits::total 728533 # number of ReadReq hits 985system.cpu0.l2cache.WritebackDirty_hits::writebacks 3942058 # number of WritebackDirty hits 986system.cpu0.l2cache.WritebackDirty_hits::total 3942058 # number of WritebackDirty hits 987system.cpu0.l2cache.WritebackClean_hits::writebacks 11898812 # number of WritebackClean hits 988system.cpu0.l2cache.WritebackClean_hits::total 11898812 # number of WritebackClean hits 989system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits 990system.cpu0.l2cache.UpgradeReq_hits::total 611 # number of UpgradeReq hits 991system.cpu0.l2cache.ReadExReq_hits::cpu0.data 933174 # number of ReadExReq hits 992system.cpu0.l2cache.ReadExReq_hits::total 933174 # number of ReadExReq hits 993system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 9093916 # number of ReadCleanReq hits 994system.cpu0.l2cache.ReadCleanReq_hits::total 9093916 # number of ReadCleanReq hits 995system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3073539 # number of ReadSharedReq hits 996system.cpu0.l2cache.ReadSharedReq_hits::total 3073539 # number of ReadSharedReq hits 997system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 216814 # number of InvalidateReq hits 998system.cpu0.l2cache.InvalidateReq_hits::total 216814 # number of InvalidateReq hits 999system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 561309 # number of demand (read+write) hits 1000system.cpu0.l2cache.demand_hits::cpu0.itb.walker 167224 # number of demand (read+write) hits 1001system.cpu0.l2cache.demand_hits::cpu0.inst 9093916 # number of demand (read+write) hits 1002system.cpu0.l2cache.demand_hits::cpu0.data 4006713 # number of demand (read+write) hits 1003system.cpu0.l2cache.demand_hits::total 13829162 # number of demand (read+write) hits 1004system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 561309 # number of overall hits 1005system.cpu0.l2cache.overall_hits::cpu0.itb.walker 167224 # number of overall hits 1006system.cpu0.l2cache.overall_hits::cpu0.inst 9093916 # number of overall hits 1007system.cpu0.l2cache.overall_hits::cpu0.data 4006713 # number of overall hits 1008system.cpu0.l2cache.overall_hits::total 13829162 # number of overall hits 1009system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12299 # number of ReadReq misses 1010system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8468 # number of ReadReq misses 1011system.cpu0.l2cache.ReadReq_misses::total 20767 # number of ReadReq misses 1012system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 256901 # number of UpgradeReq misses 1013system.cpu0.l2cache.UpgradeReq_misses::total 256901 # number of UpgradeReq misses 1014system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 195411 # number of SCUpgradeReq misses 1015system.cpu0.l2cache.SCUpgradeReq_misses::total 195411 # number of SCUpgradeReq misses 1016system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses 1017system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 1018system.cpu0.l2cache.ReadExReq_misses::cpu0.data 279617 # number of ReadExReq misses 1019system.cpu0.l2cache.ReadExReq_misses::total 279617 # number of ReadExReq misses 1020system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 724184 # number of ReadCleanReq misses 1021system.cpu0.l2cache.ReadCleanReq_misses::total 724184 # number of ReadCleanReq misses 1022system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1019232 # number of ReadSharedReq misses 1023system.cpu0.l2cache.ReadSharedReq_misses::total 1019232 # number of ReadSharedReq misses 1024system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 608335 # number of InvalidateReq misses 1025system.cpu0.l2cache.InvalidateReq_misses::total 608335 # number of InvalidateReq misses 1026system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12299 # number of demand (read+write) misses 1027system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8468 # number of demand (read+write) misses 1028system.cpu0.l2cache.demand_misses::cpu0.inst 724184 # number of demand (read+write) misses 1029system.cpu0.l2cache.demand_misses::cpu0.data 1298849 # number of demand (read+write) misses 1030system.cpu0.l2cache.demand_misses::total 2043800 # number of demand (read+write) misses 1031system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12299 # number of overall misses 1032system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8468 # number of overall misses 1033system.cpu0.l2cache.overall_misses::cpu0.inst 724184 # number of overall misses 1034system.cpu0.l2cache.overall_misses::cpu0.data 1298849 # number of overall misses 1035system.cpu0.l2cache.overall_misses::total 2043800 # number of overall misses 1036system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 444586500 # number of ReadReq miss cycles 1037system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 341709500 # number of ReadReq miss cycles 1038system.cpu0.l2cache.ReadReq_miss_latency::total 786296000 # number of ReadReq miss cycles 1039system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2032659000 # number of UpgradeReq miss cycles 1040system.cpu0.l2cache.UpgradeReq_miss_latency::total 2032659000 # number of UpgradeReq miss cycles 1041system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 1558169000 # number of SCUpgradeReq miss cycles 1042system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 1558169000 # number of SCUpgradeReq miss cycles 1043system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3166000 # number of SCUpgradeFailReq miss cycles 1044system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3166000 # number of SCUpgradeFailReq miss cycles 1045system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 14018472997 # number of ReadExReq miss cycles 1046system.cpu0.l2cache.ReadExReq_miss_latency::total 14018472997 # number of ReadExReq miss cycles 1047system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 24426242000 # number of ReadCleanReq miss cycles 1048system.cpu0.l2cache.ReadCleanReq_miss_latency::total 24426242000 # number of ReadCleanReq miss cycles 1049system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 35646536993 # number of ReadSharedReq miss cycles 1050system.cpu0.l2cache.ReadSharedReq_miss_latency::total 35646536993 # number of ReadSharedReq miss cycles 1051system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 333062000 # number of InvalidateReq miss cycles 1052system.cpu0.l2cache.InvalidateReq_miss_latency::total 333062000 # number of InvalidateReq miss cycles 1053system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 444586500 # number of demand (read+write) miss cycles 1054system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 341709500 # number of demand (read+write) miss cycles 1055system.cpu0.l2cache.demand_miss_latency::cpu0.inst 24426242000 # number of demand (read+write) miss cycles 1056system.cpu0.l2cache.demand_miss_latency::cpu0.data 49665009990 # number of demand (read+write) miss cycles 1057system.cpu0.l2cache.demand_miss_latency::total 74877547990 # number of demand (read+write) miss cycles 1058system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 444586500 # number of overall miss cycles 1059system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 341709500 # number of overall miss cycles 1060system.cpu0.l2cache.overall_miss_latency::cpu0.inst 24426242000 # number of overall miss cycles 1061system.cpu0.l2cache.overall_miss_latency::cpu0.data 49665009990 # number of overall miss cycles 1062system.cpu0.l2cache.overall_miss_latency::total 74877547990 # number of overall miss cycles 1063system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 573608 # number of ReadReq accesses(hits+misses) 1064system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 175692 # number of ReadReq accesses(hits+misses) 1065system.cpu0.l2cache.ReadReq_accesses::total 749300 # number of ReadReq accesses(hits+misses) 1066system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3942058 # number of WritebackDirty accesses(hits+misses) 1067system.cpu0.l2cache.WritebackDirty_accesses::total 3942058 # number of WritebackDirty accesses(hits+misses) 1068system.cpu0.l2cache.WritebackClean_accesses::writebacks 11898812 # number of WritebackClean accesses(hits+misses) 1069system.cpu0.l2cache.WritebackClean_accesses::total 11898812 # number of WritebackClean accesses(hits+misses) 1070system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 257512 # number of UpgradeReq accesses(hits+misses) 1071system.cpu0.l2cache.UpgradeReq_accesses::total 257512 # number of UpgradeReq accesses(hits+misses) 1072system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 195411 # number of SCUpgradeReq accesses(hits+misses) 1073system.cpu0.l2cache.SCUpgradeReq_accesses::total 195411 # number of SCUpgradeReq accesses(hits+misses) 1074system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 6 # number of SCUpgradeFailReq accesses(hits+misses) 1075system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) 1076system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1212791 # number of ReadExReq accesses(hits+misses) 1077system.cpu0.l2cache.ReadExReq_accesses::total 1212791 # number of ReadExReq accesses(hits+misses) 1078system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 9818100 # number of ReadCleanReq accesses(hits+misses) 1079system.cpu0.l2cache.ReadCleanReq_accesses::total 9818100 # number of ReadCleanReq accesses(hits+misses) 1080system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4092771 # number of ReadSharedReq accesses(hits+misses) 1081system.cpu0.l2cache.ReadSharedReq_accesses::total 4092771 # number of ReadSharedReq accesses(hits+misses) 1082system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 825149 # number of InvalidateReq accesses(hits+misses) 1083system.cpu0.l2cache.InvalidateReq_accesses::total 825149 # number of InvalidateReq accesses(hits+misses) 1084system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 573608 # number of demand (read+write) accesses 1085system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 175692 # number of demand (read+write) accesses 1086system.cpu0.l2cache.demand_accesses::cpu0.inst 9818100 # number of demand (read+write) accesses 1087system.cpu0.l2cache.demand_accesses::cpu0.data 5305562 # number of demand (read+write) accesses 1088system.cpu0.l2cache.demand_accesses::total 15872962 # number of demand (read+write) accesses 1089system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 573608 # number of overall (read+write) accesses 1090system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 175692 # number of overall (read+write) accesses 1091system.cpu0.l2cache.overall_accesses::cpu0.inst 9818100 # number of overall (read+write) accesses 1092system.cpu0.l2cache.overall_accesses::cpu0.data 5305562 # number of overall (read+write) accesses 1093system.cpu0.l2cache.overall_accesses::total 15872962 # number of overall (read+write) accesses 1094system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021441 # miss rate for ReadReq accesses 1095system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.048198 # miss rate for ReadReq accesses 1096system.cpu0.l2cache.ReadReq_miss_rate::total 0.027715 # miss rate for ReadReq accesses 1097system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.997627 # miss rate for UpgradeReq accesses 1098system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.997627 # miss rate for UpgradeReq accesses |
| 1096system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1097system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1098system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1099system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 1099system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1100system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1101system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1102system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 1100system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.232559 # miss rate for ReadExReq accesses 1101system.cpu0.l2cache.ReadExReq_miss_rate::total 0.232559 # miss rate for ReadExReq accesses 1102system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.071268 # miss rate for ReadCleanReq accesses 1103system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.071268 # miss rate for ReadCleanReq accesses 1104system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.255144 # miss rate for ReadSharedReq accesses 1105system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.255144 # miss rate for ReadSharedReq accesses 1106system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.728290 # miss rate for InvalidateReq accesses 1107system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.728290 # miss rate for InvalidateReq accesses 1108system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020391 # miss rate for demand accesses 1109system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.045788 # miss rate for demand accesses 1110system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.071268 # miss rate for demand accesses 1111system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.249981 # miss rate for demand accesses 1112system.cpu0.l2cache.demand_miss_rate::total 0.125821 # miss rate for demand accesses 1113system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020391 # miss rate for overall accesses 1114system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.045788 # miss rate for overall accesses 1115system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.071268 # miss rate for overall accesses 1116system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.249981 # miss rate for overall accesses 1117system.cpu0.l2cache.overall_miss_rate::total 0.125821 # miss rate for overall accesses 1118system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 40165.289605 # average ReadReq miss latency 1119system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 44375.422910 # average ReadReq miss latency 1120system.cpu0.l2cache.ReadReq_avg_miss_latency::total 41895.590207 # average ReadReq miss latency 1121system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13381.091719 # average UpgradeReq miss latency 1122system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13381.091719 # average UpgradeReq miss latency 1123system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10497.840722 # average SCUpgradeReq miss latency 1124system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10497.840722 # average SCUpgradeReq miss latency 1125system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 1065200 # average SCUpgradeFailReq miss latency 1126system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1065200 # average SCUpgradeFailReq miss latency 1127system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 67266.723805 # average ReadExReq miss latency 1128system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 67266.723805 # average ReadExReq miss latency 1129system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39267.727698 # average ReadCleanReq miss latency 1130system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39267.727698 # average ReadCleanReq miss latency 1131system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41982.661097 # average ReadSharedReq miss latency 1132system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41982.661097 # average ReadSharedReq miss latency 1133system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 663.667099 # average InvalidateReq miss latency 1134system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 663.667099 # average InvalidateReq miss latency 1135system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 40165.289605 # average overall miss latency 1136system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 44375.422910 # average overall miss latency 1137system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39267.727698 # average overall miss latency 1138system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 47360.581612 # average overall miss latency 1139system.cpu0.l2cache.demand_avg_miss_latency::total 44387.760222 # average overall miss latency 1140system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 40165.289605 # average overall miss latency 1141system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 44375.422910 # average overall miss latency 1142system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39267.727698 # average overall miss latency 1143system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 47360.581612 # average overall miss latency 1144system.cpu0.l2cache.overall_avg_miss_latency::total 44387.760222 # average overall miss latency 1145system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 1103system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.230557 # miss rate for ReadExReq accesses 1104system.cpu0.l2cache.ReadExReq_miss_rate::total 0.230557 # miss rate for ReadExReq accesses 1105system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.073760 # miss rate for ReadCleanReq accesses 1106system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.073760 # miss rate for ReadCleanReq accesses 1107system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.249032 # miss rate for ReadSharedReq accesses 1108system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.249032 # miss rate for ReadSharedReq accesses 1109system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.737243 # miss rate for InvalidateReq accesses 1110system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.737243 # miss rate for InvalidateReq accesses 1111system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021441 # miss rate for demand accesses 1112system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.048198 # miss rate for demand accesses 1113system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.073760 # miss rate for demand accesses 1114system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.244809 # miss rate for demand accesses 1115system.cpu0.l2cache.demand_miss_rate::total 0.128760 # miss rate for demand accesses 1116system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021441 # miss rate for overall accesses 1117system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.048198 # miss rate for overall accesses 1118system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.073760 # miss rate for overall accesses 1119system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.244809 # miss rate for overall accesses 1120system.cpu0.l2cache.overall_miss_rate::total 0.128760 # miss rate for overall accesses 1121system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36148.182779 # average ReadReq miss latency 1122system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 40353.034955 # average ReadReq miss latency 1123system.cpu0.l2cache.ReadReq_avg_miss_latency::total 37862.763038 # average ReadReq miss latency 1124system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 7912.226889 # average UpgradeReq miss latency 1125system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 7912.226889 # average UpgradeReq miss latency 1126system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 7973.803931 # average SCUpgradeReq miss latency 1127system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 7973.803931 # average SCUpgradeReq miss latency 1128system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 527666.666667 # average SCUpgradeFailReq miss latency 1129system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 527666.666667 # average SCUpgradeFailReq miss latency 1130system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50134.551894 # average ReadExReq miss latency 1131system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50134.551894 # average ReadExReq miss latency 1132system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 33729.331220 # average ReadCleanReq miss latency 1133system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 33729.331220 # average ReadCleanReq miss latency 1134system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34973.918591 # average ReadSharedReq miss latency 1135system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34973.918591 # average ReadSharedReq miss latency 1136system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 547.497678 # average InvalidateReq miss latency 1137system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 547.497678 # average InvalidateReq miss latency 1138system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36148.182779 # average overall miss latency 1139system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 40353.034955 # average overall miss latency 1140system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 33729.331220 # average overall miss latency 1141system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38237.708918 # average overall miss latency 1142system.cpu0.l2cache.demand_avg_miss_latency::total 36636.436046 # average overall miss latency 1143system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36148.182779 # average overall miss latency 1144system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 40353.034955 # average overall miss latency 1145system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 33729.331220 # average overall miss latency 1146system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38237.708918 # average overall miss latency 1147system.cpu0.l2cache.overall_avg_miss_latency::total 36636.436046 # average overall miss latency 1148system.cpu0.l2cache.blocked_cycles::no_mshrs 90 # number of cycles access was blocked |
| 1146system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1149system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1147system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked | 1150system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked |
| 1148system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1151system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1149system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 1152system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 90 # average number of cycles each access was blocked |
| 1150system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1153system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1151system.cpu0.l2cache.unused_prefetches 49728 # number of HardPF blocks evicted w/o reference 1152system.cpu0.l2cache.writebacks::writebacks 1630983 # number of writebacks 1153system.cpu0.l2cache.writebacks::total 1630983 # number of writebacks 1154system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 1155system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 2 # number of ReadReq MSHR hits | 1154system.cpu0.l2cache.unused_prefetches 48128 # number of HardPF blocks evicted w/o reference 1155system.cpu0.l2cache.writebacks::writebacks 1646117 # number of writebacks 1156system.cpu0.l2cache.writebacks::total 1646117 # number of writebacks 1157system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 3 # number of ReadReq MSHR hits |
| 1156system.cpu0.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits | 1158system.cpu0.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits |
| 1157system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9619 # number of ReadExReq MSHR hits 1158system.cpu0.l2cache.ReadExReq_mshr_hits::total 9619 # number of ReadExReq MSHR hits 1159system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 7 # number of ReadCleanReq MSHR hits 1160system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits 1161system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 1673 # number of ReadSharedReq MSHR hits 1162system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 1673 # number of ReadSharedReq MSHR hits 1163system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 1164system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 2 # number of demand (read+write) MSHR hits 1165system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits 1166system.cpu0.l2cache.demand_mshr_hits::cpu0.data 11292 # number of demand (read+write) MSHR hits 1167system.cpu0.l2cache.demand_mshr_hits::total 11302 # number of demand (read+write) MSHR hits 1168system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 1169system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 2 # number of overall MSHR hits 1170system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits 1171system.cpu0.l2cache.overall_mshr_hits::cpu0.data 11292 # number of overall MSHR hits 1172system.cpu0.l2cache.overall_mshr_hits::total 11302 # number of overall MSHR hits 1173system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 11860 # number of ReadReq MSHR misses 1174system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8274 # number of ReadReq MSHR misses 1175system.cpu0.l2cache.ReadReq_mshr_misses::total 20134 # number of ReadReq MSHR misses 1176system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 2 # number of WritebackDirty MSHR misses 1177system.cpu0.l2cache.WritebackDirty_mshr_misses::total 2 # number of WritebackDirty MSHR misses 1178system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 816392 # number of HardPFReq MSHR misses 1179system.cpu0.l2cache.HardPFReq_mshr_misses::total 816392 # number of HardPFReq MSHR misses 1180system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 260415 # number of UpgradeReq MSHR misses 1181system.cpu0.l2cache.UpgradeReq_mshr_misses::total 260415 # number of UpgradeReq MSHR misses 1182system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 200530 # number of SCUpgradeReq MSHR misses 1183system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 200530 # number of SCUpgradeReq MSHR misses 1184system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses 1185system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 1186system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 268532 # number of ReadExReq MSHR misses 1187system.cpu0.l2cache.ReadExReq_mshr_misses::total 268532 # number of ReadExReq MSHR misses 1188system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 749484 # number of ReadCleanReq MSHR misses 1189system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 749484 # number of ReadCleanReq MSHR misses 1190system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1027891 # number of ReadSharedReq MSHR misses 1191system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1027891 # number of ReadSharedReq MSHR misses 1192system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 615811 # number of InvalidateReq MSHR misses 1193system.cpu0.l2cache.InvalidateReq_mshr_misses::total 615811 # number of InvalidateReq MSHR misses 1194system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 11860 # number of demand (read+write) MSHR misses 1195system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8274 # number of demand (read+write) MSHR misses 1196system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 749484 # number of demand (read+write) MSHR misses 1197system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1296423 # number of demand (read+write) MSHR misses 1198system.cpu0.l2cache.demand_mshr_misses::total 2066041 # number of demand (read+write) MSHR misses 1199system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11860 # number of overall MSHR misses 1200system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8274 # number of overall MSHR misses 1201system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 749484 # number of overall MSHR misses 1202system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1296423 # number of overall MSHR misses 1203system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 816392 # number of overall MSHR misses 1204system.cpu0.l2cache.overall_mshr_misses::total 2882433 # number of overall MSHR misses 1205system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 1206system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31552 # number of ReadReq MSHR uncacheable 1207system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 83861 # number of ReadReq MSHR uncacheable 1208system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31148 # number of WriteReq MSHR uncacheable 1209system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31148 # number of WriteReq MSHR uncacheable 1210system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 1211system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 62700 # number of overall MSHR uncacheable misses 1212system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 115009 # number of overall MSHR uncacheable misses 1213system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 405225500 # number of ReadReq MSHR miss cycles 1214system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 317581000 # number of ReadReq MSHR miss cycles 1215system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 722806500 # number of ReadReq MSHR miss cycles 1216system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 46297805758 # number of HardPFReq MSHR miss cycles 1217system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 46297805758 # number of HardPFReq MSHR miss cycles 1218system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7801522496 # number of UpgradeReq MSHR miss cycles 1219system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7801522496 # number of UpgradeReq MSHR miss cycles 1220system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3985601996 # number of SCUpgradeReq MSHR miss cycles 1221system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3985601996 # number of SCUpgradeReq MSHR miss cycles 1222system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4972000 # number of SCUpgradeFailReq MSHR miss cycles 1223system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4972000 # number of SCUpgradeFailReq MSHR miss cycles 1224system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 15679279493 # number of ReadExReq MSHR miss cycles 1225system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 15679279493 # number of ReadExReq MSHR miss cycles 1226system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 24933652500 # number of ReadCleanReq MSHR miss cycles 1227system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 24933652500 # number of ReadCleanReq MSHR miss cycles 1228system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 36914926990 # number of ReadSharedReq MSHR miss cycles 1229system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 36914926990 # number of ReadSharedReq MSHR miss cycles 1230system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 43692307000 # number of InvalidateReq MSHR miss cycles 1231system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 43692307000 # number of InvalidateReq MSHR miss cycles 1232system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 405225500 # number of demand (read+write) MSHR miss cycles 1233system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 317581000 # number of demand (read+write) MSHR miss cycles 1234system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 24933652500 # number of demand (read+write) MSHR miss cycles 1235system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 52594206483 # number of demand (read+write) MSHR miss cycles 1236system.cpu0.l2cache.demand_mshr_miss_latency::total 78250665483 # number of demand (read+write) MSHR miss cycles 1237system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 405225500 # number of overall MSHR miss cycles 1238system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 317581000 # number of overall MSHR miss cycles 1239system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 24933652500 # number of overall MSHR miss cycles 1240system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 52594206483 # number of overall MSHR miss cycles 1241system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 46297805758 # number of overall MSHR miss cycles 1242system.cpu0.l2cache.overall_mshr_miss_latency::total 124548471241 # number of overall MSHR miss cycles 1243system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of ReadReq MSHR uncacheable cycles 1244system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5788797000 # number of ReadReq MSHR uncacheable cycles 1245system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 12784952000 # number of ReadReq MSHR uncacheable cycles 1246system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles 1247system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5788797000 # number of overall MSHR uncacheable cycles 1248system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12784952000 # number of overall MSHR uncacheable cycles 1249system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020389 # mshr miss rate for ReadReq accesses 1250system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045776 # mshr miss rate for ReadReq accesses 1251system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.026408 # mshr miss rate for ReadReq accesses 1252system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 1253system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses | 1159system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9808 # number of ReadExReq MSHR hits 1160system.cpu0.l2cache.ReadExReq_mshr_hits::total 9808 # number of ReadExReq MSHR hits 1161system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 9 # number of ReadCleanReq MSHR hits 1162system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 9 # number of ReadCleanReq MSHR hits 1163system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 898 # number of ReadSharedReq MSHR hits 1164system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 898 # number of ReadSharedReq MSHR hits 1165system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 3 # number of InvalidateReq MSHR hits 1166system.cpu0.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits 1167system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 3 # number of demand (read+write) MSHR hits 1168system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits 1169system.cpu0.l2cache.demand_mshr_hits::cpu0.data 10706 # number of demand (read+write) MSHR hits 1170system.cpu0.l2cache.demand_mshr_hits::total 10718 # number of demand (read+write) MSHR hits 1171system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 3 # number of overall MSHR hits 1172system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits 1173system.cpu0.l2cache.overall_mshr_hits::cpu0.data 10706 # number of overall MSHR hits 1174system.cpu0.l2cache.overall_mshr_hits::total 10718 # number of overall MSHR hits 1175system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12299 # number of ReadReq MSHR misses 1176system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8465 # number of ReadReq MSHR misses 1177system.cpu0.l2cache.ReadReq_mshr_misses::total 20764 # number of ReadReq MSHR misses 1178system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 828377 # number of HardPFReq MSHR misses 1179system.cpu0.l2cache.HardPFReq_mshr_misses::total 828377 # number of HardPFReq MSHR misses 1180system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 256901 # number of UpgradeReq MSHR misses 1181system.cpu0.l2cache.UpgradeReq_mshr_misses::total 256901 # number of UpgradeReq MSHR misses 1182system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 195411 # number of SCUpgradeReq MSHR misses 1183system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 195411 # number of SCUpgradeReq MSHR misses 1184system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses 1185system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses 1186system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 269809 # number of ReadExReq MSHR misses 1187system.cpu0.l2cache.ReadExReq_mshr_misses::total 269809 # number of ReadExReq MSHR misses 1188system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 724175 # number of ReadCleanReq MSHR misses 1189system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 724175 # number of ReadCleanReq MSHR misses 1190system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1018334 # number of ReadSharedReq MSHR misses 1191system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1018334 # number of ReadSharedReq MSHR misses 1192system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 608332 # number of InvalidateReq MSHR misses 1193system.cpu0.l2cache.InvalidateReq_mshr_misses::total 608332 # number of InvalidateReq MSHR misses 1194system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12299 # number of demand (read+write) MSHR misses 1195system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8465 # number of demand (read+write) MSHR misses 1196system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 724175 # number of demand (read+write) MSHR misses 1197system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1288143 # number of demand (read+write) MSHR misses 1198system.cpu0.l2cache.demand_mshr_misses::total 2033082 # number of demand (read+write) MSHR misses 1199system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12299 # number of overall MSHR misses 1200system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8465 # number of overall MSHR misses 1201system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 724175 # number of overall MSHR misses 1202system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1288143 # number of overall MSHR misses 1203system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 828377 # number of overall MSHR misses 1204system.cpu0.l2cache.overall_mshr_misses::total 2861459 # number of overall MSHR misses 1205system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52299 # number of ReadReq MSHR uncacheable 1206system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31702 # number of ReadReq MSHR uncacheable 1207system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 84001 # number of ReadReq MSHR uncacheable 1208system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31225 # number of WriteReq MSHR uncacheable 1209system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31225 # number of WriteReq MSHR uncacheable 1210system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52299 # number of overall MSHR uncacheable misses 1211system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 62927 # number of overall MSHR uncacheable misses 1212system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 115226 # number of overall MSHR uncacheable misses 1213system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 370792500 # number of ReadReq MSHR miss cycles 1214system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 290829500 # number of ReadReq MSHR miss cycles 1215system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 661622000 # number of ReadReq MSHR miss cycles 1216system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38426708957 # number of HardPFReq MSHR miss cycles 1217system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 38426708957 # number of HardPFReq MSHR miss cycles 1218system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 5314605493 # number of UpgradeReq MSHR miss cycles 1219system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 5314605493 # number of UpgradeReq MSHR miss cycles 1220system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3216326998 # number of SCUpgradeReq MSHR miss cycles 1221system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3216326998 # number of SCUpgradeReq MSHR miss cycles 1222system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2770000 # number of SCUpgradeFailReq MSHR miss cycles 1223system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2770000 # number of SCUpgradeFailReq MSHR miss cycles 1224system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11196985497 # number of ReadExReq MSHR miss cycles 1225system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11196985497 # number of ReadExReq MSHR miss cycles 1226system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 20080949000 # number of ReadCleanReq MSHR miss cycles 1227system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 20080949000 # number of ReadCleanReq MSHR miss cycles 1228system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 29451947493 # number of ReadSharedReq MSHR miss cycles 1229system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 29451947493 # number of ReadSharedReq MSHR miss cycles 1230system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 20309675000 # number of InvalidateReq MSHR miss cycles 1231system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 20309675000 # number of InvalidateReq MSHR miss cycles 1232system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 370792500 # number of demand (read+write) MSHR miss cycles 1233system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 290829500 # number of demand (read+write) MSHR miss cycles 1234system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 20080949000 # number of demand (read+write) MSHR miss cycles 1235system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 40648932990 # number of demand (read+write) MSHR miss cycles 1236system.cpu0.l2cache.demand_mshr_miss_latency::total 61391503990 # number of demand (read+write) MSHR miss cycles 1237system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 370792500 # number of overall MSHR miss cycles 1238system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 290829500 # number of overall MSHR miss cycles 1239system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 20080949000 # number of overall MSHR miss cycles 1240system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 40648932990 # number of overall MSHR miss cycles 1241system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38426708957 # number of overall MSHR miss cycles 1242system.cpu0.l2cache.overall_mshr_miss_latency::total 99818212947 # number of overall MSHR miss cycles 1243system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4418803500 # number of ReadReq MSHR uncacheable cycles 1244system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5883144500 # number of ReadReq MSHR uncacheable cycles 1245system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10301948000 # number of ReadReq MSHR uncacheable cycles 1246system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4418803500 # number of overall MSHR uncacheable cycles 1247system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5883144500 # number of overall MSHR uncacheable cycles 1248system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10301948000 # number of overall MSHR uncacheable cycles 1249system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for ReadReq accesses 1250system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for ReadReq accesses 1251system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027711 # mshr miss rate for ReadReq accesses |
| 1254system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1255system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1252system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1253system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1256system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998585 # mshr miss rate for UpgradeReq accesses 1257system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.998585 # mshr miss rate for UpgradeReq accesses | 1254system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997627 # mshr miss rate for UpgradeReq accesses 1255system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997627 # mshr miss rate for UpgradeReq accesses |
| 1258system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1259system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1260system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1261system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 1256system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1257system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1258system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1259system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 1262system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.224517 # mshr miss rate for ReadExReq accesses 1263system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.224517 # mshr miss rate for ReadExReq accesses 1264system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.071267 # mshr miss rate for ReadCleanReq accesses 1265system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.071267 # mshr miss rate for ReadCleanReq accesses 1266system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.254730 # mshr miss rate for ReadSharedReq accesses 1267system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254730 # mshr miss rate for ReadSharedReq accesses 1268system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.728290 # mshr miss rate for InvalidateReq accesses 1269system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.728290 # mshr miss rate for InvalidateReq accesses 1270system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.020389 # mshr miss rate for demand accesses 1271system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045776 # mshr miss rate for demand accesses 1272system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.071267 # mshr miss rate for demand accesses 1273system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.247822 # mshr miss rate for demand accesses 1274system.cpu0.l2cache.demand_mshr_miss_rate::total 0.125137 # mshr miss rate for demand accesses 1275system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.020389 # mshr miss rate for overall accesses 1276system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045776 # mshr miss rate for overall accesses 1277system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.071267 # mshr miss rate for overall accesses 1278system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.247822 # mshr miss rate for overall accesses | 1260system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.222469 # mshr miss rate for ReadExReq accesses 1261system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.222469 # mshr miss rate for ReadExReq accesses 1262system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for ReadCleanReq accesses 1263system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.073759 # mshr miss rate for ReadCleanReq accesses 1264system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.248813 # mshr miss rate for ReadSharedReq accesses 1265system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248813 # mshr miss rate for ReadSharedReq accesses 1266system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.737239 # mshr miss rate for InvalidateReq accesses 1267system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.737239 # mshr miss rate for InvalidateReq accesses 1268system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for demand accesses 1269system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for demand accesses 1270system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for demand accesses 1271system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242791 # mshr miss rate for demand accesses 1272system.cpu0.l2cache.demand_mshr_miss_rate::total 0.128085 # mshr miss rate for demand accesses 1273system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021441 # mshr miss rate for overall accesses 1274system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.048181 # mshr miss rate for overall accesses 1275system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.073759 # mshr miss rate for overall accesses 1276system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242791 # mshr miss rate for overall accesses |
| 1279system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1277system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1280system.cpu0.l2cache.overall_mshr_miss_rate::total 0.174585 # mshr miss rate for overall accesses 1281system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467 # average ReadReq mshr miss latency 1282system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average ReadReq mshr miss latency 1283system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35899.796364 # average ReadReq mshr miss latency 1284system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56710.263890 # average HardPFReq mshr miss latency 1285system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56710.263890 # average HardPFReq mshr miss latency 1286system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29958.038116 # average UpgradeReq mshr miss latency 1287system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29958.038116 # average UpgradeReq mshr miss latency 1288system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19875.340328 # average SCUpgradeReq mshr miss latency 1289system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19875.340328 # average SCUpgradeReq mshr miss latency 1290system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 994400 # average SCUpgradeFailReq mshr miss latency 1291system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 994400 # average SCUpgradeFailReq mshr miss latency 1292system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 58388.867967 # average ReadExReq mshr miss latency 1293system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 58388.867967 # average ReadExReq mshr miss latency 1294system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average ReadCleanReq mshr miss latency 1295system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33267.758218 # average ReadCleanReq mshr miss latency 1296system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35913.269977 # average ReadSharedReq mshr miss latency 1297system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35913.269977 # average ReadSharedReq mshr miss latency 1298system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70950.838813 # average InvalidateReq mshr miss latency 1299system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 70950.838813 # average InvalidateReq mshr miss latency 1300system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467 # average overall mshr miss latency 1301system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average overall mshr miss latency 1302system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average overall mshr miss latency 1303system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 40568.708271 # average overall mshr miss latency 1304system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37874.691491 # average overall mshr miss latency 1305system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34167.411467 # average overall mshr miss latency 1306system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average overall mshr miss latency 1307system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average overall mshr miss latency 1308system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40568.708271 # average overall mshr miss latency 1309system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56710.263890 # average overall mshr miss latency 1310system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43209.493938 # average overall mshr miss latency 1311system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency 1312system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183468.464757 # average ReadReq mshr uncacheable latency 1313system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152454.084735 # average ReadReq mshr uncacheable latency 1314system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency 1315system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92325.311005 # average overall mshr uncacheable latency 1316system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 111164.795799 # average overall mshr uncacheable latency 1317system.cpu0.toL2Bus.snoop_filter.tot_requests 33857668 # Total number of requests made to the snoop filter. 1318system.cpu0.toL2Bus.snoop_filter.hit_single_requests 17264460 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1319system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3128 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1320system.cpu0.toL2Bus.snoop_filter.tot_snoops 2263959 # Total number of snoops made to the snoop filter. 1321system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2263472 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1322system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 487 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1323system.cpu0.toL2Bus.trans_dist::ReadReq 924227 # Transaction distribution 1324system.cpu0.toL2Bus.trans_dist::ReadResp 15578589 # Transaction distribution 1325system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution 1326system.cpu0.toL2Bus.trans_dist::WriteReq 31149 # Transaction distribution 1327system.cpu0.toL2Bus.trans_dist::WriteResp 31148 # Transaction distribution 1328system.cpu0.toL2Bus.trans_dist::WritebackDirty 5528357 # Transaction distribution 1329system.cpu0.toL2Bus.trans_dist::WritebackClean 12594701 # Transaction distribution 1330system.cpu0.toL2Bus.trans_dist::CleanEvict 3060195 # Transaction distribution 1331system.cpu0.toL2Bus.trans_dist::HardPFReq 1058289 # Transaction distribution 1332system.cpu0.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution 1333system.cpu0.toL2Bus.trans_dist::UpgradeReq 483217 # Transaction distribution 1334system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 361321 # Transaction distribution 1335system.cpu0.toL2Bus.trans_dist::UpgradeResp 533499 # Transaction distribution 1336system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 62 # Transaction distribution 1337system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution 1338system.cpu0.toL2Bus.trans_dist::ReadExReq 1230571 # Transaction distribution 1339system.cpu0.toL2Bus.trans_dist::ReadExResp 1205955 # Transaction distribution 1340system.cpu0.toL2Bus.trans_dist::ReadCleanReq 10516550 # Transaction distribution 1341system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5115631 # Transaction distribution 1342system.cpu0.toL2Bus.trans_dist::InvalidateReq 898497 # Transaction distribution 1343system.cpu0.toL2Bus.trans_dist::InvalidateResp 845557 # Transaction distribution 1344system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 31653744 # Packet count per connected master and slave (bytes) 1345system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19358528 # Packet count per connected master and slave (bytes) 1346system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 379556 # Packet count per connected master and slave (bytes) 1347system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1223236 # Packet count per connected master and slave (bytes) 1348system.cpu0.toL2Bus.pkt_count::total 52615064 # Packet count per connected master and slave (bytes) 1349system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1349432640 # Cumulative packet size per connected master and slave (bytes) 1350system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 724409976 # Cumulative packet size per connected master and slave (bytes) 1351system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1445984 # Cumulative packet size per connected master and slave (bytes) 1352system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4653440 # Cumulative packet size per connected master and slave (bytes) 1353system.cpu0.toL2Bus.pkt_size::total 2079942040 # Cumulative packet size per connected master and slave (bytes) 1354system.cpu0.toL2Bus.snoops 7567377 # Total snoops (count) 1355system.cpu0.toL2Bus.snoop_fanout::samples 25314697 # Request fanout histogram 1356system.cpu0.toL2Bus.snoop_fanout::mean 0.102016 # Request fanout histogram 1357system.cpu0.toL2Bus.snoop_fanout::stdev 0.302732 # Request fanout histogram | 1278system.cpu0.l2cache.overall_mshr_miss_rate::total 0.180273 # mshr miss rate for overall accesses 1279system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average ReadReq mshr miss latency 1280system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average ReadReq mshr miss latency 1281system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 31863.899056 # average ReadReq mshr miss latency 1282system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46387.947706 # average HardPFReq mshr miss latency 1283system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46387.947706 # average HardPFReq mshr miss latency 1284system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20687.367869 # average UpgradeReq mshr miss latency 1285system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20687.367869 # average UpgradeReq mshr miss latency 1286system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 16459.293479 # average SCUpgradeReq mshr miss latency 1287system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16459.293479 # average SCUpgradeReq mshr miss latency 1288system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 461666.666667 # average SCUpgradeFailReq mshr miss latency 1289system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 461666.666667 # average SCUpgradeFailReq mshr miss latency 1290system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41499.673832 # average ReadExReq mshr miss latency 1291system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41499.673832 # average ReadExReq mshr miss latency 1292system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average ReadCleanReq mshr miss latency 1293system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 27729.414851 # average ReadCleanReq mshr miss latency 1294system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28921.697098 # average ReadSharedReq mshr miss latency 1295system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28921.697098 # average ReadSharedReq mshr miss latency 1296system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 33385.840298 # average InvalidateReq mshr miss latency 1297system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 33385.840298 # average InvalidateReq mshr miss latency 1298system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average overall mshr miss latency 1299system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average overall mshr miss latency 1300system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average overall mshr miss latency 1301system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31556.227057 # average overall mshr miss latency 1302system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30196.275404 # average overall mshr miss latency 1303system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30148.182779 # average overall mshr miss latency 1304system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34356.704076 # average overall mshr miss latency 1305system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 27729.414851 # average overall mshr miss latency 1306system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31556.227057 # average overall mshr miss latency 1307system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46387.947706 # average overall mshr miss latency 1308system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34883.677504 # average overall mshr miss latency 1309system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 84491.166179 # average ReadReq mshr uncacheable latency 1310system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185576.446281 # average ReadReq mshr uncacheable latency 1311system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 122640.778086 # average ReadReq mshr uncacheable latency 1312system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 84491.166179 # average overall mshr uncacheable latency 1313system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 93491.577542 # average overall mshr uncacheable latency 1314system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 89406.453405 # average overall mshr uncacheable latency 1315system.cpu0.toL2Bus.snoop_filter.tot_requests 32574371 # Total number of requests made to the snoop filter. 1316system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16625689 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1317system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2928 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1318system.cpu0.toL2Bus.snoop_filter.tot_snoops 2229520 # Total number of snoops made to the snoop filter. 1319system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2229086 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1320system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 434 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1321system.cpu0.toL2Bus.trans_dist::ReadReq 913111 # Transaction distribution 1322system.cpu0.toL2Bus.trans_dist::ReadResp 14927613 # Transaction distribution 1323system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 1324system.cpu0.toL2Bus.trans_dist::WriteReq 31225 # Transaction distribution 1325system.cpu0.toL2Bus.trans_dist::WriteResp 31225 # Transaction distribution 1326system.cpu0.toL2Bus.trans_dist::WritebackDirty 5591471 # Transaction distribution 1327system.cpu0.toL2Bus.trans_dist::WritebackClean 11901739 # Transaction distribution 1328system.cpu0.toL2Bus.trans_dist::CleanEvict 2979875 # Transaction distribution 1329system.cpu0.toL2Bus.trans_dist::HardPFReq 1058098 # Transaction distribution 1330system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution 1331system.cpu0.toL2Bus.trans_dist::UpgradeReq 473129 # Transaction distribution 1332system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352230 # Transaction distribution 1333system.cpu0.toL2Bus.trans_dist::UpgradeResp 525861 # Transaction distribution 1334system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution 1335system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution 1336system.cpu0.toL2Bus.trans_dist::ReadExReq 1247048 # Transaction distribution 1337system.cpu0.toL2Bus.trans_dist::ReadExResp 1223348 # Transaction distribution 1338system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9818101 # Transaction distribution 1339system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5127973 # Transaction distribution 1340system.cpu0.toL2Bus.trans_dist::InvalidateReq 875849 # Transaction distribution 1341system.cpu0.toL2Bus.trans_dist::InvalidateResp 825149 # Transaction distribution 1342system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29558377 # Packet count per connected master and slave (bytes) 1343system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19506589 # Packet count per connected master and slave (bytes) 1344system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 370132 # Packet count per connected master and slave (bytes) 1345system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1208276 # Packet count per connected master and slave (bytes) 1346system.cpu0.toL2Bus.pkt_count::total 50643374 # Packet count per connected master and slave (bytes) 1347system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1260030528 # Cumulative packet size per connected master and slave (bytes) 1348system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 732739948 # Cumulative packet size per connected master and slave (bytes) 1349system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1405536 # Cumulative packet size per connected master and slave (bytes) 1350system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4588864 # Cumulative packet size per connected master and slave (bytes) 1351system.cpu0.toL2Bus.pkt_size::total 1998764876 # Cumulative packet size per connected master and slave (bytes) 1352system.cpu0.toL2Bus.snoops 7447074 # Total snoops (count) 1353system.cpu0.toL2Bus.snoop_fanout::samples 24526103 # Request fanout histogram 1354system.cpu0.toL2Bus.snoop_fanout::mean 0.104449 # Request fanout histogram 1355system.cpu0.toL2Bus.snoop_fanout::stdev 0.305900 # Request fanout histogram |
| 1358system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1356system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1359system.cpu0.toL2Bus.snoop_fanout::0 22732690 89.80% 89.80% # Request fanout histogram 1360system.cpu0.toL2Bus.snoop_fanout::1 2581520 10.20% 100.00% # Request fanout histogram 1361system.cpu0.toL2Bus.snoop_fanout::2 487 0.00% 100.00% # Request fanout histogram | 1357system.cpu0.toL2Bus.snoop_fanout::0 21964812 89.56% 89.56% # Request fanout histogram 1358system.cpu0.toL2Bus.snoop_fanout::1 2560857 10.44% 100.00% # Request fanout histogram 1359system.cpu0.toL2Bus.snoop_fanout::2 434 0.00% 100.00% # Request fanout histogram |
| 1362system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1363system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1364system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1360system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1361system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1362system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1365system.cpu0.toL2Bus.snoop_fanout::total 25314697 # Request fanout histogram 1366system.cpu0.toL2Bus.reqLayer0.occupancy 33752723480 # Layer occupancy (ticks) | 1363system.cpu0.toL2Bus.snoop_fanout::total 24526103 # Request fanout histogram 1364system.cpu0.toL2Bus.reqLayer0.occupancy 32454354981 # Layer occupancy (ticks) |
| 1367system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1365system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1368system.cpu0.toL2Bus.snoopLayer0.occupancy 205163062 # Layer occupancy (ticks) | 1366system.cpu0.toL2Bus.snoopLayer0.occupancy 208052919 # Layer occupancy (ticks) |
| 1369system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1367system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1370system.cpu0.toL2Bus.respLayer0.occupancy 15856801952 # Layer occupancy (ticks) | 1368system.cpu0.toL2Bus.respLayer0.occupancy 14809077024 # Layer occupancy (ticks) |
| 1371system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1369system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1372system.cpu0.toL2Bus.respLayer1.occupancy 8551593856 # Layer occupancy (ticks) | 1370system.cpu0.toL2Bus.respLayer1.occupancy 8648892723 # Layer occupancy (ticks) |
| 1373system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1371system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1374system.cpu0.toL2Bus.respLayer2.occupancy 198848419 # Layer occupancy (ticks) | 1372system.cpu0.toL2Bus.respLayer2.occupancy 194486906 # Layer occupancy (ticks) |
| 1375system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1373system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1376system.cpu0.toL2Bus.respLayer3.occupancy 641675758 # Layer occupancy (ticks) | 1374system.cpu0.toL2Bus.respLayer3.occupancy 634782270 # Layer occupancy (ticks) |
| 1377system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1375system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1378system.cpu1.branchPred.lookups 127453033 # Number of BP lookups 1379system.cpu1.branchPred.condPredicted 91217282 # Number of conditional branches predicted 1380system.cpu1.branchPred.condIncorrect 5663830 # Number of conditional branches incorrect 1381system.cpu1.branchPred.BTBLookups 96224557 # Number of BTB lookups 1382system.cpu1.branchPred.BTBHits 67852361 # Number of BTB hits | 1376system.cpu1.branchPred.lookups 123875539 # Number of BP lookups 1377system.cpu1.branchPred.condPredicted 88073767 # Number of conditional branches predicted 1378system.cpu1.branchPred.condIncorrect 5721607 # Number of conditional branches incorrect 1379system.cpu1.branchPred.BTBLookups 93465185 # Number of BTB lookups 1380system.cpu1.branchPred.BTBHits 65276742 # Number of BTB hits |
| 1383system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1381system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1384system.cpu1.branchPred.BTBHitPct 70.514600 # BTB Hit Percentage 1385system.cpu1.branchPred.usedRAS 14431851 # Number of times the RAS was used to get a target. 1386system.cpu1.branchPred.RASInCorrect 916644 # Number of incorrect RAS predictions. 1387system.cpu1.branchPred.indirectLookups 3338859 # Number of indirect predictor lookups. 1388system.cpu1.branchPred.indirectHits 2197659 # Number of indirect target hits. 1389system.cpu1.branchPred.indirectMisses 1141200 # Number of indirect misses. 1390system.cpu1.branchPredindirectMispredicted 412569 # Number of mispredicted indirect branches. | 1382system.cpu1.branchPred.BTBHitPct 69.840703 # BTB Hit Percentage 1383system.cpu1.branchPred.usedRAS 14217829 # Number of times the RAS was used to get a target. 1384system.cpu1.branchPred.RASInCorrect 926540 # Number of incorrect RAS predictions. 1385system.cpu1.branchPred.indirectLookups 3290763 # Number of indirect predictor lookups. 1386system.cpu1.branchPred.indirectHits 2135700 # Number of indirect target hits. 1387system.cpu1.branchPred.indirectMisses 1155063 # Number of indirect misses. 1388system.cpu1.branchPredindirectMispredicted 419705 # Number of mispredicted indirect branches. |
| 1391system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1392system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1393system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1394system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1395system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1396system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1397system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1398system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1412system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1413system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1414system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1415system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1416system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1417system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1418system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1419system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1389system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1390system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1391system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1392system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1393system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1394system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1395system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1396system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1410system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1411system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1412system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1413system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1414system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1415system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1416system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1417system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1420system.cpu1.dtb.walker.walks 261031 # Table walker walks requested 1421system.cpu1.dtb.walker.walksLong 261031 # Table walker walks initiated with long descriptors 1422system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9619 # Level at which table walker walks with long descriptors terminate 1423system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80662 # Level at which table walker walks with long descriptors terminate 1424system.cpu1.dtb.walker.walkWaitTime::samples 261031 # Table walker wait (enqueue to first request) latency 1425system.cpu1.dtb.walker.walkWaitTime::0 261031 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1426system.cpu1.dtb.walker.walkWaitTime::total 261031 # Table walker wait (enqueue to first request) latency 1427system.cpu1.dtb.walker.walkCompletionTime::samples 90281 # Table walker service (enqueue to completion) latency 1428system.cpu1.dtb.walker.walkCompletionTime::mean 23808.564371 # Table walker service (enqueue to completion) latency 1429system.cpu1.dtb.walker.walkCompletionTime::gmean 21471.713865 # Table walker service (enqueue to completion) latency 1430system.cpu1.dtb.walker.walkCompletionTime::stdev 22312.583155 # Table walker service (enqueue to completion) latency 1431system.cpu1.dtb.walker.walkCompletionTime::0-65535 88920 98.49% 98.49% # Table walker service (enqueue to completion) latency 1432system.cpu1.dtb.walker.walkCompletionTime::65536-131071 187 0.21% 98.70% # Table walker service (enqueue to completion) latency 1433system.cpu1.dtb.walker.walkCompletionTime::131072-196607 992 1.10% 99.80% # Table walker service (enqueue to completion) latency 1434system.cpu1.dtb.walker.walkCompletionTime::196608-262143 43 0.05% 99.85% # Table walker service (enqueue to completion) latency 1435system.cpu1.dtb.walker.walkCompletionTime::262144-327679 45 0.05% 99.90% # Table walker service (enqueue to completion) latency 1436system.cpu1.dtb.walker.walkCompletionTime::327680-393215 26 0.03% 99.92% # Table walker service (enqueue to completion) latency 1437system.cpu1.dtb.walker.walkCompletionTime::393216-458751 33 0.04% 99.96% # Table walker service (enqueue to completion) latency 1438system.cpu1.dtb.walker.walkCompletionTime::458752-524287 21 0.02% 99.98% # Table walker service (enqueue to completion) latency 1439system.cpu1.dtb.walker.walkCompletionTime::524288-589823 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 1440system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 1441system.cpu1.dtb.walker.walkCompletionTime::655360-720895 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 1442system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1443system.cpu1.dtb.walker.walkCompletionTime::total 90281 # Table walker service (enqueue to completion) latency 1444system.cpu1.dtb.walker.walksPending::samples 1786242352 # Table walker pending requests distribution 1445system.cpu1.dtb.walker.walksPending::0 1786242352 100.00% 100.00% # Table walker pending requests distribution 1446system.cpu1.dtb.walker.walksPending::total 1786242352 # Table walker pending requests distribution 1447system.cpu1.dtb.walker.walkPageSizes::4K 80662 89.35% 89.35% # Table walker page sizes translated 1448system.cpu1.dtb.walker.walkPageSizes::2M 9619 10.65% 100.00% # Table walker page sizes translated 1449system.cpu1.dtb.walker.walkPageSizes::total 90281 # Table walker page sizes translated 1450system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 261031 # Table walker requests started/completed, data/inst | 1418system.cpu1.dtb.walker.walks 255224 # Table walker walks requested 1419system.cpu1.dtb.walker.walksLong 255224 # Table walker walks initiated with long descriptors 1420system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8861 # Level at which table walker walks with long descriptors terminate 1421system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76574 # Level at which table walker walks with long descriptors terminate 1422system.cpu1.dtb.walker.walkWaitTime::samples 255224 # Table walker wait (enqueue to first request) latency 1423system.cpu1.dtb.walker.walkWaitTime::0 255224 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1424system.cpu1.dtb.walker.walkWaitTime::total 255224 # Table walker wait (enqueue to first request) latency 1425system.cpu1.dtb.walker.walkCompletionTime::samples 85435 # Table walker service (enqueue to completion) latency 1426system.cpu1.dtb.walker.walkCompletionTime::mean 22815.538128 # Table walker service (enqueue to completion) latency 1427system.cpu1.dtb.walker.walkCompletionTime::gmean 21300.261475 # Table walker service (enqueue to completion) latency 1428system.cpu1.dtb.walker.walkCompletionTime::stdev 14551.493747 # Table walker service (enqueue to completion) latency 1429system.cpu1.dtb.walker.walkCompletionTime::0-65535 84387 98.77% 98.77% # Table walker service (enqueue to completion) latency 1430system.cpu1.dtb.walker.walkCompletionTime::65536-131071 897 1.05% 99.82% # Table walker service (enqueue to completion) latency 1431system.cpu1.dtb.walker.walkCompletionTime::131072-196607 42 0.05% 99.87% # Table walker service (enqueue to completion) latency 1432system.cpu1.dtb.walker.walkCompletionTime::196608-262143 51 0.06% 99.93% # Table walker service (enqueue to completion) latency 1433system.cpu1.dtb.walker.walkCompletionTime::262144-327679 31 0.04% 99.97% # Table walker service (enqueue to completion) latency 1434system.cpu1.dtb.walker.walkCompletionTime::327680-393215 13 0.02% 99.98% # Table walker service (enqueue to completion) latency 1435system.cpu1.dtb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency 1436system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 1437system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 1438system.cpu1.dtb.walker.walkCompletionTime::total 85435 # Table walker service (enqueue to completion) latency 1439system.cpu1.dtb.walker.walksPending::samples -788977056 # Table walker pending requests distribution 1440system.cpu1.dtb.walker.walksPending::0 -788977056 100.00% 100.00% # Table walker pending requests distribution 1441system.cpu1.dtb.walker.walksPending::total -788977056 # Table walker pending requests distribution 1442system.cpu1.dtb.walker.walkPageSizes::4K 76574 89.63% 89.63% # Table walker page sizes translated 1443system.cpu1.dtb.walker.walkPageSizes::2M 8861 10.37% 100.00% # Table walker page sizes translated 1444system.cpu1.dtb.walker.walkPageSizes::total 85435 # Table walker page sizes translated 1445system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 255224 # Table walker requests started/completed, data/inst |
| 1451system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 1446system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 1452system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 261031 # Table walker requests started/completed, data/inst 1453system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90281 # Table walker requests started/completed, data/inst | 1447system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 255224 # Table walker requests started/completed, data/inst 1448system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 85435 # Table walker requests started/completed, data/inst |
| 1454system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 1449system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 1455system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90281 # Table walker requests started/completed, data/inst 1456system.cpu1.dtb.walker.walkRequestOrigin::total 351312 # Table walker requests started/completed, data/inst | 1450system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 85435 # Table walker requests started/completed, data/inst 1451system.cpu1.dtb.walker.walkRequestOrigin::total 340659 # Table walker requests started/completed, data/inst |
| 1457system.cpu1.dtb.inst_hits 0 # ITB inst hits 1458system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1452system.cpu1.dtb.inst_hits 0 # ITB inst hits 1453system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1459system.cpu1.dtb.read_hits 80497438 # DTB read hits 1460system.cpu1.dtb.read_misses 213464 # DTB read misses 1461system.cpu1.dtb.write_hits 70911031 # DTB write hits 1462system.cpu1.dtb.write_misses 47567 # DTB write misses | 1454system.cpu1.dtb.read_hits 78594683 # DTB read hits 1455system.cpu1.dtb.read_misses 208094 # DTB read misses 1456system.cpu1.dtb.write_hits 69544419 # DTB write hits 1457system.cpu1.dtb.write_misses 47130 # DTB write misses |
| 1463system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1464system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 1458system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1459system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 1465system.cpu1.dtb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID 1466system.cpu1.dtb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID 1467system.cpu1.dtb.flush_entries 37751 # Number of entries that have been flushed from TLB 1468system.cpu1.dtb.align_faults 1110 # Number of TLB faults due to alignment restrictions 1469system.cpu1.dtb.prefetch_faults 7072 # Number of TLB faults due to prefetch | 1460system.cpu1.dtb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID 1461system.cpu1.dtb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 1462system.cpu1.dtb.flush_entries 35846 # Number of entries that have been flushed from TLB 1463system.cpu1.dtb.align_faults 839 # Number of TLB faults due to alignment restrictions 1464system.cpu1.dtb.prefetch_faults 6709 # Number of TLB faults due to prefetch |
| 1470system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1465system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1471system.cpu1.dtb.perms_faults 11967 # Number of TLB faults due to permissions restrictions 1472system.cpu1.dtb.read_accesses 80710902 # DTB read accesses 1473system.cpu1.dtb.write_accesses 70958598 # DTB write accesses | 1466system.cpu1.dtb.perms_faults 11450 # Number of TLB faults due to permissions restrictions 1467system.cpu1.dtb.read_accesses 78802777 # DTB read accesses 1468system.cpu1.dtb.write_accesses 69591549 # DTB write accesses |
| 1474system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1469system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1475system.cpu1.dtb.hits 151408469 # DTB hits 1476system.cpu1.dtb.misses 261031 # DTB misses 1477system.cpu1.dtb.accesses 151669500 # DTB accesses | 1470system.cpu1.dtb.hits 148139102 # DTB hits 1471system.cpu1.dtb.misses 255224 # DTB misses 1472system.cpu1.dtb.accesses 148394326 # DTB accesses |
| 1478system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1479system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1480system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1481system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1482system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1483system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1484system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1485system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1499system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1500system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1501system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1502system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1503system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1504system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1505system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1506system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1473system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1474system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1475system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1476system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1477system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1478system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1479system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1480system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1494system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1495system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1496system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1497system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1498system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1499system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1500system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1501system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1507system.cpu1.itb.walker.walks 64962 # Table walker walks requested 1508system.cpu1.itb.walker.walksLong 64962 # Table walker walks initiated with long descriptors 1509system.cpu1.itb.walker.walksLongTerminationLevel::Level2 549 # Level at which table walker walks with long descriptors terminate 1510system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55482 # Level at which table walker walks with long descriptors terminate 1511system.cpu1.itb.walker.walkWaitTime::samples 64962 # Table walker wait (enqueue to first request) latency 1512system.cpu1.itb.walker.walkWaitTime::0 64962 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1513system.cpu1.itb.walker.walkWaitTime::total 64962 # Table walker wait (enqueue to first request) latency 1514system.cpu1.itb.walker.walkCompletionTime::samples 56031 # Table walker service (enqueue to completion) latency 1515system.cpu1.itb.walker.walkCompletionTime::mean 27185.022577 # Table walker service (enqueue to completion) latency 1516system.cpu1.itb.walker.walkCompletionTime::gmean 24059.100661 # Table walker service (enqueue to completion) latency 1517system.cpu1.itb.walker.walkCompletionTime::stdev 24848.225124 # Table walker service (enqueue to completion) latency 1518system.cpu1.itb.walker.walkCompletionTime::0-65535 54737 97.69% 97.69% # Table walker service (enqueue to completion) latency 1519system.cpu1.itb.walker.walkCompletionTime::65536-131071 10 0.02% 97.71% # Table walker service (enqueue to completion) latency 1520system.cpu1.itb.walker.walkCompletionTime::131072-196607 1140 2.03% 99.74% # Table walker service (enqueue to completion) latency 1521system.cpu1.itb.walker.walkCompletionTime::196608-262143 44 0.08% 99.82% # Table walker service (enqueue to completion) latency 1522system.cpu1.itb.walker.walkCompletionTime::262144-327679 63 0.11% 99.93% # Table walker service (enqueue to completion) latency 1523system.cpu1.itb.walker.walkCompletionTime::327680-393215 23 0.04% 99.98% # Table walker service (enqueue to completion) latency 1524system.cpu1.itb.walker.walkCompletionTime::393216-458751 11 0.02% 99.99% # Table walker service (enqueue to completion) latency 1525system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1526system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1527system.cpu1.itb.walker.walkCompletionTime::total 56031 # Table walker service (enqueue to completion) latency 1528system.cpu1.itb.walker.walksPending::samples 1785244852 # Table walker pending requests distribution 1529system.cpu1.itb.walker.walksPending::0 1785244852 100.00% 100.00% # Table walker pending requests distribution 1530system.cpu1.itb.walker.walksPending::total 1785244852 # Table walker pending requests distribution 1531system.cpu1.itb.walker.walkPageSizes::4K 55482 99.02% 99.02% # Table walker page sizes translated 1532system.cpu1.itb.walker.walkPageSizes::2M 549 0.98% 100.00% # Table walker page sizes translated 1533system.cpu1.itb.walker.walkPageSizes::total 56031 # Table walker page sizes translated | 1502system.cpu1.itb.walker.walks 62177 # Table walker walks requested 1503system.cpu1.itb.walker.walksLong 62177 # Table walker walks initiated with long descriptors 1504system.cpu1.itb.walker.walksLongTerminationLevel::Level2 630 # Level at which table walker walks with long descriptors terminate 1505system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54596 # Level at which table walker walks with long descriptors terminate 1506system.cpu1.itb.walker.walkWaitTime::samples 62177 # Table walker wait (enqueue to first request) latency 1507system.cpu1.itb.walker.walkWaitTime::0 62177 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1508system.cpu1.itb.walker.walkWaitTime::total 62177 # Table walker wait (enqueue to first request) latency 1509system.cpu1.itb.walker.walkCompletionTime::samples 55226 # Table walker service (enqueue to completion) latency 1510system.cpu1.itb.walker.walkCompletionTime::mean 25650.988665 # Table walker service (enqueue to completion) latency 1511system.cpu1.itb.walker.walkCompletionTime::gmean 23787.605646 # Table walker service (enqueue to completion) latency 1512system.cpu1.itb.walker.walkCompletionTime::stdev 16059.408850 # Table walker service (enqueue to completion) latency 1513system.cpu1.itb.walker.walkCompletionTime::0-32767 49961 90.47% 90.47% # Table walker service (enqueue to completion) latency 1514system.cpu1.itb.walker.walkCompletionTime::32768-65535 4236 7.67% 98.14% # Table walker service (enqueue to completion) latency 1515system.cpu1.itb.walker.walkCompletionTime::65536-98303 9 0.02% 98.15% # Table walker service (enqueue to completion) latency 1516system.cpu1.itb.walker.walkCompletionTime::98304-131071 906 1.64% 99.79% # Table walker service (enqueue to completion) latency 1517system.cpu1.itb.walker.walkCompletionTime::131072-163839 24 0.04% 99.84% # Table walker service (enqueue to completion) latency 1518system.cpu1.itb.walker.walkCompletionTime::163840-196607 14 0.03% 99.86% # Table walker service (enqueue to completion) latency 1519system.cpu1.itb.walker.walkCompletionTime::196608-229375 28 0.05% 99.91% # Table walker service (enqueue to completion) latency 1520system.cpu1.itb.walker.walkCompletionTime::229376-262143 21 0.04% 99.95% # Table walker service (enqueue to completion) latency 1521system.cpu1.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.97% # Table walker service (enqueue to completion) latency 1522system.cpu1.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency 1523system.cpu1.itb.walker.walkCompletionTime::327680-360447 3 0.01% 99.98% # Table walker service (enqueue to completion) latency 1524system.cpu1.itb.walker.walkCompletionTime::360448-393215 7 0.01% 99.99% # Table walker service (enqueue to completion) latency 1525system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1526system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1527system.cpu1.itb.walker.walkCompletionTime::total 55226 # Table walker service (enqueue to completion) latency 1528system.cpu1.itb.walker.walksPending::samples -789630556 # Table walker pending requests distribution 1529system.cpu1.itb.walker.walksPending::0 -789630556 100.00% 100.00% # Table walker pending requests distribution 1530system.cpu1.itb.walker.walksPending::total -789630556 # Table walker pending requests distribution 1531system.cpu1.itb.walker.walkPageSizes::4K 54596 98.86% 98.86% # Table walker page sizes translated 1532system.cpu1.itb.walker.walkPageSizes::2M 630 1.14% 100.00% # Table walker page sizes translated 1533system.cpu1.itb.walker.walkPageSizes::total 55226 # Table walker page sizes translated |
| 1534system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 1534system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 1535system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64962 # Table walker requests started/completed, data/inst 1536system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64962 # Table walker requests started/completed, data/inst | 1535system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 62177 # Table walker requests started/completed, data/inst 1536system.cpu1.itb.walker.walkRequestOrigin_Requested::total 62177 # Table walker requests started/completed, data/inst |
| 1537system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 1537system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 1538system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56031 # Table walker requests started/completed, data/inst 1539system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56031 # Table walker requests started/completed, data/inst 1540system.cpu1.itb.walker.walkRequestOrigin::total 120993 # Table walker requests started/completed, data/inst 1541system.cpu1.itb.inst_hits 225980528 # ITB inst hits 1542system.cpu1.itb.inst_misses 64962 # ITB inst misses | 1538system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55226 # Table walker requests started/completed, data/inst 1539system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55226 # Table walker requests started/completed, data/inst 1540system.cpu1.itb.walker.walkRequestOrigin::total 117403 # Table walker requests started/completed, data/inst 1541system.cpu1.itb.inst_hits 219337574 # ITB inst hits 1542system.cpu1.itb.inst_misses 62177 # ITB inst misses |
| 1543system.cpu1.itb.read_hits 0 # DTB read hits 1544system.cpu1.itb.read_misses 0 # DTB read misses 1545system.cpu1.itb.write_hits 0 # DTB write hits 1546system.cpu1.itb.write_misses 0 # DTB write misses 1547system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1548system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 1543system.cpu1.itb.read_hits 0 # DTB read hits 1544system.cpu1.itb.read_misses 0 # DTB read misses 1545system.cpu1.itb.write_hits 0 # DTB write hits 1546system.cpu1.itb.write_misses 0 # DTB write misses 1547system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1548system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 1549system.cpu1.itb.flush_tlb_mva_asid 42028 # Number of times TLB was flushed by MVA & ASID 1550system.cpu1.itb.flush_tlb_asid 1061 # Number of times TLB was flushed by ASID 1551system.cpu1.itb.flush_entries 26783 # Number of entries that have been flushed from TLB | 1549system.cpu1.itb.flush_tlb_mva_asid 41340 # Number of times TLB was flushed by MVA & ASID 1550system.cpu1.itb.flush_tlb_asid 1040 # Number of times TLB was flushed by ASID 1551system.cpu1.itb.flush_entries 25383 # Number of entries that have been flushed from TLB |
| 1552system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1553system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1554system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1552system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1553system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1554system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1555system.cpu1.itb.perms_faults 166792 # Number of TLB faults due to permissions restrictions | 1555system.cpu1.itb.perms_faults 167002 # Number of TLB faults due to permissions restrictions |
| 1556system.cpu1.itb.read_accesses 0 # DTB read accesses 1557system.cpu1.itb.write_accesses 0 # DTB write accesses | 1556system.cpu1.itb.read_accesses 0 # DTB read accesses 1557system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1558system.cpu1.itb.inst_accesses 226045490 # ITB inst accesses 1559system.cpu1.itb.hits 225980528 # DTB hits 1560system.cpu1.itb.misses 64962 # DTB misses 1561system.cpu1.itb.accesses 226045490 # DTB accesses 1562system.cpu1.numCycles 884296043 # number of cpu cycles simulated | 1558system.cpu1.itb.inst_accesses 219399751 # ITB inst accesses 1559system.cpu1.itb.hits 219337574 # DTB hits 1560system.cpu1.itb.misses 62177 # DTB misses 1561system.cpu1.itb.accesses 219399751 # DTB accesses 1562system.cpu1.numCycles 838096745 # number of cpu cycles simulated |
| 1563system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1564system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1563system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1564system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1565system.cpu1.committedInsts 410764166 # Number of instructions committed 1566system.cpu1.committedOps 484072804 # Number of ops (including micro ops) committed 1567system.cpu1.discardedOps 46607969 # Number of ops (including micro ops) which were discarded before commit 1568system.cpu1.numFetchSuspends 5245 # Number of times Execute suspended instruction fetching 1569system.cpu1.quiesceCycles 94188329171 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1570system.cpu1.cpi 2.152807 # CPI: cycles per instruction 1571system.cpu1.ipc 0.464510 # IPC: instructions per cycle | 1565system.cpu1.committedInsts 400342475 # Number of instructions committed 1566system.cpu1.committedOps 472062345 # Number of ops (including micro ops) committed 1567system.cpu1.discardedOps 44700411 # Number of ops (including micro ops) which were discarded before commit 1568system.cpu1.numFetchSuspends 5381 # Number of times Execute suspended instruction fetching 1569system.cpu1.quiesceCycles 93874475142 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1570system.cpu1.cpi 2.093449 # CPI: cycles per instruction 1571system.cpu1.ipc 0.477681 # IPC: instructions per cycle |
| 1572system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction | 1572system.cpu1.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| 1573system.cpu1.op_class_0::IntAlu 334821764 69.17% 69.17% # Class of committed instruction 1574system.cpu1.op_class_0::IntMult 956339 0.20% 69.37% # Class of committed instruction 1575system.cpu1.op_class_0::IntDiv 55233 0.01% 69.38% # Class of committed instruction 1576system.cpu1.op_class_0::FloatAdd 0 0.00% 69.38% # Class of committed instruction 1577system.cpu1.op_class_0::FloatCmp 0 0.00% 69.38% # Class of committed instruction 1578system.cpu1.op_class_0::FloatCvt 0 0.00% 69.38% # Class of committed instruction 1579system.cpu1.op_class_0::FloatMult 0 0.00% 69.38% # Class of committed instruction 1580system.cpu1.op_class_0::FloatDiv 0 0.00% 69.38% # Class of committed instruction 1581system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.38% # Class of committed instruction 1582system.cpu1.op_class_0::SimdAdd 0 0.00% 69.38% # Class of committed instruction 1583system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.38% # Class of committed instruction 1584system.cpu1.op_class_0::SimdAlu 0 0.00% 69.38% # Class of committed instruction 1585system.cpu1.op_class_0::SimdCmp 0 0.00% 69.38% # Class of committed instruction 1586system.cpu1.op_class_0::SimdCvt 0 0.00% 69.38% # Class of committed instruction 1587system.cpu1.op_class_0::SimdMisc 0 0.00% 69.38% # Class of committed instruction 1588system.cpu1.op_class_0::SimdMult 0 0.00% 69.38% # Class of committed instruction 1589system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.38% # Class of committed instruction 1590system.cpu1.op_class_0::SimdShift 0 0.00% 69.38% # Class of committed instruction 1591system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.38% # Class of committed instruction 1592system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.38% # Class of committed instruction 1593system.cpu1.op_class_0::SimdFloatAdd 8 0.00% 69.38% # Class of committed instruction 1594system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.38% # Class of committed instruction 1595system.cpu1.op_class_0::SimdFloatCmp 13 0.00% 69.38% # Class of committed instruction 1596system.cpu1.op_class_0::SimdFloatCvt 21 0.00% 69.38% # Class of committed instruction 1597system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.38% # Class of committed instruction 1598system.cpu1.op_class_0::SimdFloatMisc 37353 0.01% 69.38% # Class of committed instruction 1599system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.38% # Class of committed instruction 1600system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.38% # Class of committed instruction 1601system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.38% # Class of committed instruction 1602system.cpu1.op_class_0::MemRead 77588616 16.03% 85.41% # Class of committed instruction 1603system.cpu1.op_class_0::MemWrite 70613457 14.59% 100.00% # Class of committed instruction | 1573system.cpu1.op_class_0::IntAlu 326101667 69.08% 69.08% # Class of committed instruction 1574system.cpu1.op_class_0::IntMult 925373 0.20% 69.28% # Class of committed instruction 1575system.cpu1.op_class_0::IntDiv 54057 0.01% 69.29% # Class of committed instruction 1576system.cpu1.op_class_0::FloatAdd 0 0.00% 69.29% # Class of committed instruction 1577system.cpu1.op_class_0::FloatCmp 0 0.00% 69.29% # Class of committed instruction 1578system.cpu1.op_class_0::FloatCvt 0 0.00% 69.29% # Class of committed instruction 1579system.cpu1.op_class_0::FloatMult 0 0.00% 69.29% # Class of committed instruction 1580system.cpu1.op_class_0::FloatDiv 0 0.00% 69.29% # Class of committed instruction 1581system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.29% # Class of committed instruction 1582system.cpu1.op_class_0::SimdAdd 0 0.00% 69.29% # Class of committed instruction 1583system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.29% # Class of committed instruction 1584system.cpu1.op_class_0::SimdAlu 0 0.00% 69.29% # Class of committed instruction 1585system.cpu1.op_class_0::SimdCmp 0 0.00% 69.29% # Class of committed instruction 1586system.cpu1.op_class_0::SimdCvt 0 0.00% 69.29% # Class of committed instruction 1587system.cpu1.op_class_0::SimdMisc 0 0.00% 69.29% # Class of committed instruction 1588system.cpu1.op_class_0::SimdMult 0 0.00% 69.29% # Class of committed instruction 1589system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.29% # Class of committed instruction 1590system.cpu1.op_class_0::SimdShift 0 0.00% 69.29% # Class of committed instruction 1591system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.29% # Class of committed instruction 1592system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.29% # Class of committed instruction 1593system.cpu1.op_class_0::SimdFloatAdd 8 0.00% 69.29% # Class of committed instruction 1594system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.29% # Class of committed instruction 1595system.cpu1.op_class_0::SimdFloatCmp 13 0.00% 69.29% # Class of committed instruction 1596system.cpu1.op_class_0::SimdFloatCvt 21 0.00% 69.29% # Class of committed instruction 1597system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.29% # Class of committed instruction 1598system.cpu1.op_class_0::SimdFloatMisc 72329 0.02% 69.30% # Class of committed instruction 1599system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.30% # Class of committed instruction 1600system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.30% # Class of committed instruction 1601system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.30% # Class of committed instruction 1602system.cpu1.op_class_0::MemRead 75664367 16.03% 85.33% # Class of committed instruction 1603system.cpu1.op_class_0::MemWrite 69244510 14.67% 100.00% # Class of committed instruction |
| 1604system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1605system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 1604system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 1605system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 1606system.cpu1.op_class_0::total 484072804 # Class of committed instruction | 1606system.cpu1.op_class_0::total 472062345 # Class of committed instruction |
| 1607system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1607system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1608system.cpu1.kern.inst.quiesce 5362 # number of quiesce instructions executed 1609system.cpu1.tickCycles 676945147 # Number of cycles that the object actually ticked 1610system.cpu1.idleCycles 207350896 # Total number of cycles that the object has spent stopped 1611system.cpu1.dcache.tags.replacements 5011869 # number of replacements 1612system.cpu1.dcache.tags.tagsinuse 436.764256 # Cycle average of tags in use 1613system.cpu1.dcache.tags.total_refs 143763031 # Total number of references to valid blocks. 1614system.cpu1.dcache.tags.sampled_refs 5012381 # Sample count of references to valid blocks. 1615system.cpu1.dcache.tags.avg_refs 28.681585 # Average number of references to valid blocks. 1616system.cpu1.dcache.tags.warmup_cycle 8498279834500 # Cycle when the warmup percentage was hit. 1617system.cpu1.dcache.tags.occ_blocks::cpu1.data 436.764256 # Average occupied blocks per requestor 1618system.cpu1.dcache.tags.occ_percent::cpu1.data 0.853055 # Average percentage of cache occupancy 1619system.cpu1.dcache.tags.occ_percent::total 0.853055 # Average percentage of cache occupancy 1620system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1621system.cpu1.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 1622system.cpu1.dcache.tags.age_task_id_blocks_1024::1 376 # Occupied blocks per task id 1623system.cpu1.dcache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id 1624system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1625system.cpu1.dcache.tags.tag_accesses 305397096 # Number of tag accesses 1626system.cpu1.dcache.tags.data_accesses 305397096 # Number of data accesses 1627system.cpu1.dcache.ReadReq_hits::cpu1.data 73662807 # number of ReadReq hits 1628system.cpu1.dcache.ReadReq_hits::total 73662807 # number of ReadReq hits 1629system.cpu1.dcache.WriteReq_hits::cpu1.data 66040616 # number of WriteReq hits 1630system.cpu1.dcache.WriteReq_hits::total 66040616 # number of WriteReq hits 1631system.cpu1.dcache.SoftPFReq_hits::cpu1.data 200864 # number of SoftPFReq hits 1632system.cpu1.dcache.SoftPFReq_hits::total 200864 # number of SoftPFReq hits 1633system.cpu1.dcache.WriteLineReq_hits::cpu1.data 33950 # number of WriteLineReq hits 1634system.cpu1.dcache.WriteLineReq_hits::total 33950 # number of WriteLineReq hits 1635system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1678906 # number of LoadLockedReq hits 1636system.cpu1.dcache.LoadLockedReq_hits::total 1678906 # number of LoadLockedReq hits 1637system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1638259 # number of StoreCondReq hits 1638system.cpu1.dcache.StoreCondReq_hits::total 1638259 # number of StoreCondReq hits 1639system.cpu1.dcache.demand_hits::cpu1.data 139737373 # number of demand (read+write) hits 1640system.cpu1.dcache.demand_hits::total 139737373 # number of demand (read+write) hits 1641system.cpu1.dcache.overall_hits::cpu1.data 139938237 # number of overall hits 1642system.cpu1.dcache.overall_hits::total 139938237 # number of overall hits 1643system.cpu1.dcache.ReadReq_misses::cpu1.data 3193197 # number of ReadReq misses 1644system.cpu1.dcache.ReadReq_misses::total 3193197 # number of ReadReq misses 1645system.cpu1.dcache.WriteReq_misses::cpu1.data 2277873 # number of WriteReq misses 1646system.cpu1.dcache.WriteReq_misses::total 2277873 # number of WriteReq misses 1647system.cpu1.dcache.SoftPFReq_misses::cpu1.data 648992 # number of SoftPFReq misses 1648system.cpu1.dcache.SoftPFReq_misses::total 648992 # number of SoftPFReq misses 1649system.cpu1.dcache.WriteLineReq_misses::cpu1.data 409957 # number of WriteLineReq misses 1650system.cpu1.dcache.WriteLineReq_misses::total 409957 # number of WriteLineReq misses 1651system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 159945 # number of LoadLockedReq misses 1652system.cpu1.dcache.LoadLockedReq_misses::total 159945 # number of LoadLockedReq misses 1653system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199493 # number of StoreCondReq misses 1654system.cpu1.dcache.StoreCondReq_misses::total 199493 # number of StoreCondReq misses 1655system.cpu1.dcache.demand_misses::cpu1.data 5881027 # number of demand (read+write) misses 1656system.cpu1.dcache.demand_misses::total 5881027 # number of demand (read+write) misses 1657system.cpu1.dcache.overall_misses::cpu1.data 6530019 # number of overall misses 1658system.cpu1.dcache.overall_misses::total 6530019 # number of overall misses 1659system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 52208022500 # number of ReadReq miss cycles 1660system.cpu1.dcache.ReadReq_miss_latency::total 52208022500 # number of ReadReq miss cycles 1661system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 51224639500 # number of WriteReq miss cycles 1662system.cpu1.dcache.WriteReq_miss_latency::total 51224639500 # number of WriteReq miss cycles 1663system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 14899741000 # number of WriteLineReq miss cycles 1664system.cpu1.dcache.WriteLineReq_miss_latency::total 14899741000 # number of WriteLineReq miss cycles 1665system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2555092000 # number of LoadLockedReq miss cycles 1666system.cpu1.dcache.LoadLockedReq_miss_latency::total 2555092000 # number of LoadLockedReq miss cycles 1667system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5532212500 # number of StoreCondReq miss cycles 1668system.cpu1.dcache.StoreCondReq_miss_latency::total 5532212500 # number of StoreCondReq miss cycles 1669system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5344000 # number of StoreCondFailReq miss cycles 1670system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5344000 # number of StoreCondFailReq miss cycles 1671system.cpu1.dcache.demand_miss_latency::cpu1.data 118332403000 # number of demand (read+write) miss cycles 1672system.cpu1.dcache.demand_miss_latency::total 118332403000 # number of demand (read+write) miss cycles 1673system.cpu1.dcache.overall_miss_latency::cpu1.data 118332403000 # number of overall miss cycles 1674system.cpu1.dcache.overall_miss_latency::total 118332403000 # number of overall miss cycles 1675system.cpu1.dcache.ReadReq_accesses::cpu1.data 76856004 # number of ReadReq accesses(hits+misses) 1676system.cpu1.dcache.ReadReq_accesses::total 76856004 # number of ReadReq accesses(hits+misses) 1677system.cpu1.dcache.WriteReq_accesses::cpu1.data 68318489 # number of WriteReq accesses(hits+misses) 1678system.cpu1.dcache.WriteReq_accesses::total 68318489 # number of WriteReq accesses(hits+misses) 1679system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 849856 # number of SoftPFReq accesses(hits+misses) 1680system.cpu1.dcache.SoftPFReq_accesses::total 849856 # number of SoftPFReq accesses(hits+misses) 1681system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 443907 # number of WriteLineReq accesses(hits+misses) 1682system.cpu1.dcache.WriteLineReq_accesses::total 443907 # number of WriteLineReq accesses(hits+misses) 1683system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1838851 # number of LoadLockedReq accesses(hits+misses) 1684system.cpu1.dcache.LoadLockedReq_accesses::total 1838851 # number of LoadLockedReq accesses(hits+misses) 1685system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1837752 # number of StoreCondReq accesses(hits+misses) 1686system.cpu1.dcache.StoreCondReq_accesses::total 1837752 # number of StoreCondReq accesses(hits+misses) 1687system.cpu1.dcache.demand_accesses::cpu1.data 145618400 # number of demand (read+write) accesses 1688system.cpu1.dcache.demand_accesses::total 145618400 # number of demand (read+write) accesses 1689system.cpu1.dcache.overall_accesses::cpu1.data 146468256 # number of overall (read+write) accesses 1690system.cpu1.dcache.overall_accesses::total 146468256 # number of overall (read+write) accesses 1691system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041548 # miss rate for ReadReq accesses 1692system.cpu1.dcache.ReadReq_miss_rate::total 0.041548 # miss rate for ReadReq accesses 1693system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.033342 # miss rate for WriteReq accesses 1694system.cpu1.dcache.WriteReq_miss_rate::total 0.033342 # miss rate for WriteReq accesses 1695system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.763649 # miss rate for SoftPFReq accesses 1696system.cpu1.dcache.SoftPFReq_miss_rate::total 0.763649 # miss rate for SoftPFReq accesses 1697system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.923520 # miss rate for WriteLineReq accesses 1698system.cpu1.dcache.WriteLineReq_miss_rate::total 0.923520 # miss rate for WriteLineReq accesses 1699system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086981 # miss rate for LoadLockedReq accesses 1700system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086981 # miss rate for LoadLockedReq accesses 1701system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108553 # miss rate for StoreCondReq accesses 1702system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108553 # miss rate for StoreCondReq accesses 1703system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040387 # miss rate for demand accesses 1704system.cpu1.dcache.demand_miss_rate::total 0.040387 # miss rate for demand accesses 1705system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044583 # miss rate for overall accesses 1706system.cpu1.dcache.overall_miss_rate::total 0.044583 # miss rate for overall accesses 1707system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16349.765611 # average ReadReq miss latency 1708system.cpu1.dcache.ReadReq_avg_miss_latency::total 16349.765611 # average ReadReq miss latency 1709system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22487.926017 # average WriteReq miss latency 1710system.cpu1.dcache.WriteReq_avg_miss_latency::total 22487.926017 # average WriteReq miss latency 1711system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 36344.643463 # average WriteLineReq miss latency 1712system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 36344.643463 # average WriteLineReq miss latency 1713system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15974.816343 # average LoadLockedReq miss latency 1714system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15974.816343 # average LoadLockedReq miss latency 1715system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27731.361501 # average StoreCondReq miss latency 1716system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27731.361501 # average StoreCondReq miss latency | 1608system.cpu1.kern.inst.quiesce 5498 # number of quiesce instructions executed 1609system.cpu1.tickCycles 657140254 # Number of cycles that the object actually ticked 1610system.cpu1.idleCycles 180956491 # Total number of cycles that the object has spent stopped 1611system.cpu1.dcache.tags.replacements 4810857 # number of replacements 1612system.cpu1.dcache.tags.tagsinuse 458.623346 # Cycle average of tags in use 1613system.cpu1.dcache.tags.total_refs 140763490 # Total number of references to valid blocks. 1614system.cpu1.dcache.tags.sampled_refs 4811366 # Sample count of references to valid blocks. 1615system.cpu1.dcache.tags.avg_refs 29.256450 # Average number of references to valid blocks. 1616system.cpu1.dcache.tags.warmup_cycle 8377530544000 # Cycle when the warmup percentage was hit. 1617system.cpu1.dcache.tags.occ_blocks::cpu1.data 458.623346 # Average occupied blocks per requestor 1618system.cpu1.dcache.tags.occ_percent::cpu1.data 0.895749 # Average percentage of cache occupancy 1619system.cpu1.dcache.tags.occ_percent::total 0.895749 # Average percentage of cache occupancy 1620system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id 1621system.cpu1.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 1622system.cpu1.dcache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id 1623system.cpu1.dcache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id 1624system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id 1625system.cpu1.dcache.tags.tag_accesses 298669128 # Number of tag accesses 1626system.cpu1.dcache.tags.data_accesses 298669128 # Number of data accesses 1627system.cpu1.dcache.ReadReq_hits::cpu1.data 72030058 # number of ReadReq hits 1628system.cpu1.dcache.ReadReq_hits::total 72030058 # number of ReadReq hits 1629system.cpu1.dcache.WriteReq_hits::cpu1.data 64877267 # number of WriteReq hits 1630system.cpu1.dcache.WriteReq_hits::total 64877267 # number of WriteReq hits 1631system.cpu1.dcache.SoftPFReq_hits::cpu1.data 197389 # number of SoftPFReq hits 1632system.cpu1.dcache.SoftPFReq_hits::total 197389 # number of SoftPFReq hits 1633system.cpu1.dcache.WriteLineReq_hits::cpu1.data 40268 # number of WriteLineReq hits 1634system.cpu1.dcache.WriteLineReq_hits::total 40268 # number of WriteLineReq hits 1635system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1587155 # number of LoadLockedReq hits 1636system.cpu1.dcache.LoadLockedReq_hits::total 1587155 # number of LoadLockedReq hits 1637system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1543611 # number of StoreCondReq hits 1638system.cpu1.dcache.StoreCondReq_hits::total 1543611 # number of StoreCondReq hits 1639system.cpu1.dcache.demand_hits::cpu1.data 136947593 # number of demand (read+write) hits 1640system.cpu1.dcache.demand_hits::total 136947593 # number of demand (read+write) hits 1641system.cpu1.dcache.overall_hits::cpu1.data 137144982 # number of overall hits 1642system.cpu1.dcache.overall_hits::total 137144982 # number of overall hits 1643system.cpu1.dcache.ReadReq_misses::cpu1.data 3077185 # number of ReadReq misses 1644system.cpu1.dcache.ReadReq_misses::total 3077185 # number of ReadReq misses 1645system.cpu1.dcache.WriteReq_misses::cpu1.data 2162319 # number of WriteReq misses 1646system.cpu1.dcache.WriteReq_misses::total 2162319 # number of WriteReq misses 1647system.cpu1.dcache.SoftPFReq_misses::cpu1.data 609138 # number of SoftPFReq misses 1648system.cpu1.dcache.SoftPFReq_misses::total 609138 # number of SoftPFReq misses 1649system.cpu1.dcache.WriteLineReq_misses::cpu1.data 415243 # number of WriteLineReq misses 1650system.cpu1.dcache.WriteLineReq_misses::total 415243 # number of WriteLineReq misses 1651system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 150447 # number of LoadLockedReq misses 1652system.cpu1.dcache.LoadLockedReq_misses::total 150447 # number of LoadLockedReq misses 1653system.cpu1.dcache.StoreCondReq_misses::cpu1.data 192941 # number of StoreCondReq misses 1654system.cpu1.dcache.StoreCondReq_misses::total 192941 # number of StoreCondReq misses 1655system.cpu1.dcache.demand_misses::cpu1.data 5654747 # number of demand (read+write) misses 1656system.cpu1.dcache.demand_misses::total 5654747 # number of demand (read+write) misses 1657system.cpu1.dcache.overall_misses::cpu1.data 6263885 # number of overall misses 1658system.cpu1.dcache.overall_misses::total 6263885 # number of overall misses 1659system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46366444000 # number of ReadReq miss cycles 1660system.cpu1.dcache.ReadReq_miss_latency::total 46366444000 # number of ReadReq miss cycles 1661system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 40662976500 # number of WriteReq miss cycles 1662system.cpu1.dcache.WriteReq_miss_latency::total 40662976500 # number of WriteReq miss cycles 1663system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10070349000 # number of WriteLineReq miss cycles 1664system.cpu1.dcache.WriteLineReq_miss_latency::total 10070349000 # number of WriteLineReq miss cycles 1665system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2311960000 # number of LoadLockedReq miss cycles 1666system.cpu1.dcache.LoadLockedReq_miss_latency::total 2311960000 # number of LoadLockedReq miss cycles 1667system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4775235000 # number of StoreCondReq miss cycles 1668system.cpu1.dcache.StoreCondReq_miss_latency::total 4775235000 # number of StoreCondReq miss cycles 1669system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2623000 # number of StoreCondFailReq miss cycles 1670system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2623000 # number of StoreCondFailReq miss cycles 1671system.cpu1.dcache.demand_miss_latency::cpu1.data 97099769500 # number of demand (read+write) miss cycles 1672system.cpu1.dcache.demand_miss_latency::total 97099769500 # number of demand (read+write) miss cycles 1673system.cpu1.dcache.overall_miss_latency::cpu1.data 97099769500 # number of overall miss cycles 1674system.cpu1.dcache.overall_miss_latency::total 97099769500 # number of overall miss cycles 1675system.cpu1.dcache.ReadReq_accesses::cpu1.data 75107243 # number of ReadReq accesses(hits+misses) 1676system.cpu1.dcache.ReadReq_accesses::total 75107243 # number of ReadReq accesses(hits+misses) 1677system.cpu1.dcache.WriteReq_accesses::cpu1.data 67039586 # number of WriteReq accesses(hits+misses) 1678system.cpu1.dcache.WriteReq_accesses::total 67039586 # number of WriteReq accesses(hits+misses) 1679system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 806527 # number of SoftPFReq accesses(hits+misses) 1680system.cpu1.dcache.SoftPFReq_accesses::total 806527 # number of SoftPFReq accesses(hits+misses) 1681system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 455511 # number of WriteLineReq accesses(hits+misses) 1682system.cpu1.dcache.WriteLineReq_accesses::total 455511 # number of WriteLineReq accesses(hits+misses) 1683system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1737602 # number of LoadLockedReq accesses(hits+misses) 1684system.cpu1.dcache.LoadLockedReq_accesses::total 1737602 # number of LoadLockedReq accesses(hits+misses) 1685system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1736552 # number of StoreCondReq accesses(hits+misses) 1686system.cpu1.dcache.StoreCondReq_accesses::total 1736552 # number of StoreCondReq accesses(hits+misses) 1687system.cpu1.dcache.demand_accesses::cpu1.data 142602340 # number of demand (read+write) accesses 1688system.cpu1.dcache.demand_accesses::total 142602340 # number of demand (read+write) accesses 1689system.cpu1.dcache.overall_accesses::cpu1.data 143408867 # number of overall (read+write) accesses 1690system.cpu1.dcache.overall_accesses::total 143408867 # number of overall (read+write) accesses 1691system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040971 # miss rate for ReadReq accesses 1692system.cpu1.dcache.ReadReq_miss_rate::total 0.040971 # miss rate for ReadReq accesses 1693system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032254 # miss rate for WriteReq accesses 1694system.cpu1.dcache.WriteReq_miss_rate::total 0.032254 # miss rate for WriteReq accesses 1695system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.755261 # miss rate for SoftPFReq accesses 1696system.cpu1.dcache.SoftPFReq_miss_rate::total 0.755261 # miss rate for SoftPFReq accesses 1697system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.911598 # miss rate for WriteLineReq accesses 1698system.cpu1.dcache.WriteLineReq_miss_rate::total 0.911598 # miss rate for WriteLineReq accesses 1699system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086583 # miss rate for LoadLockedReq accesses 1700system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086583 # miss rate for LoadLockedReq accesses 1701system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.111106 # miss rate for StoreCondReq accesses 1702system.cpu1.dcache.StoreCondReq_miss_rate::total 0.111106 # miss rate for StoreCondReq accesses 1703system.cpu1.dcache.demand_miss_rate::cpu1.data 0.039654 # miss rate for demand accesses 1704system.cpu1.dcache.demand_miss_rate::total 0.039654 # miss rate for demand accesses 1705system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043679 # miss rate for overall accesses 1706system.cpu1.dcache.overall_miss_rate::total 0.043679 # miss rate for overall accesses 1707system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15067.811653 # average ReadReq miss latency 1708system.cpu1.dcache.ReadReq_avg_miss_latency::total 15067.811653 # average ReadReq miss latency 1709system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18805.262545 # average WriteReq miss latency 1710system.cpu1.dcache.WriteReq_avg_miss_latency::total 18805.262545 # average WriteReq miss latency 1711system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24251.700811 # average WriteLineReq miss latency 1712system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24251.700811 # average WriteLineReq miss latency 1713system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15367.272196 # average LoadLockedReq miss latency 1714system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15367.272196 # average LoadLockedReq miss latency 1715system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24749.716234 # average StoreCondReq miss latency 1716system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24749.716234 # average StoreCondReq miss latency |
| 1717system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1718system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 1717system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1718system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 1719system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20121.043995 # average overall miss latency 1720system.cpu1.dcache.demand_avg_miss_latency::total 20121.043995 # average overall miss latency 1721system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18121.295359 # average overall miss latency 1722system.cpu1.dcache.overall_avg_miss_latency::total 18121.295359 # average overall miss latency | 1719system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17171.372919 # average overall miss latency 1720system.cpu1.dcache.demand_avg_miss_latency::total 17171.372919 # average overall miss latency 1721system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15501.524932 # average overall miss latency 1722system.cpu1.dcache.overall_avg_miss_latency::total 15501.524932 # average overall miss latency |
| 1723system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1724system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1725system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1726system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1727system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1728system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1723system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1724system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1725system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1726system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1727system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1728system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1729system.cpu1.dcache.writebacks::writebacks 5011891 # number of writebacks 1730system.cpu1.dcache.writebacks::total 5011891 # number of writebacks 1731system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 367321 # number of ReadReq MSHR hits 1732system.cpu1.dcache.ReadReq_mshr_hits::total 367321 # number of ReadReq MSHR hits 1733system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 943211 # number of WriteReq MSHR hits 1734system.cpu1.dcache.WriteReq_mshr_hits::total 943211 # number of WriteReq MSHR hits 1735system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits 1736system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits 1737system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 40165 # number of LoadLockedReq MSHR hits 1738system.cpu1.dcache.LoadLockedReq_mshr_hits::total 40165 # number of LoadLockedReq MSHR hits 1739system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 85 # number of StoreCondReq MSHR hits 1740system.cpu1.dcache.StoreCondReq_mshr_hits::total 85 # number of StoreCondReq MSHR hits 1741system.cpu1.dcache.demand_mshr_hits::cpu1.data 1310590 # number of demand (read+write) MSHR hits 1742system.cpu1.dcache.demand_mshr_hits::total 1310590 # number of demand (read+write) MSHR hits 1743system.cpu1.dcache.overall_mshr_hits::cpu1.data 1310590 # number of overall MSHR hits 1744system.cpu1.dcache.overall_mshr_hits::total 1310590 # number of overall MSHR hits 1745system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2825876 # number of ReadReq MSHR misses 1746system.cpu1.dcache.ReadReq_mshr_misses::total 2825876 # number of ReadReq MSHR misses 1747system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1334662 # number of WriteReq MSHR misses 1748system.cpu1.dcache.WriteReq_mshr_misses::total 1334662 # number of WriteReq MSHR misses 1749system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 648629 # number of SoftPFReq MSHR misses 1750system.cpu1.dcache.SoftPFReq_mshr_misses::total 648629 # number of SoftPFReq MSHR misses 1751system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 409899 # number of WriteLineReq MSHR misses 1752system.cpu1.dcache.WriteLineReq_mshr_misses::total 409899 # number of WriteLineReq MSHR misses 1753system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 119780 # number of LoadLockedReq MSHR misses 1754system.cpu1.dcache.LoadLockedReq_mshr_misses::total 119780 # number of LoadLockedReq MSHR misses 1755system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199408 # number of StoreCondReq MSHR misses 1756system.cpu1.dcache.StoreCondReq_mshr_misses::total 199408 # number of StoreCondReq MSHR misses 1757system.cpu1.dcache.demand_mshr_misses::cpu1.data 4570437 # number of demand (read+write) MSHR misses 1758system.cpu1.dcache.demand_mshr_misses::total 4570437 # number of demand (read+write) MSHR misses 1759system.cpu1.dcache.overall_mshr_misses::cpu1.data 5219066 # number of overall MSHR misses 1760system.cpu1.dcache.overall_mshr_misses::total 5219066 # number of overall MSHR misses 1761system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7337 # number of ReadReq MSHR uncacheable 1762system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7337 # number of ReadReq MSHR uncacheable 1763system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7641 # number of WriteReq MSHR uncacheable 1764system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7641 # number of WriteReq MSHR uncacheable 1765system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14978 # number of overall MSHR uncacheable misses 1766system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14978 # number of overall MSHR uncacheable misses 1767system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41329046000 # number of ReadReq MSHR miss cycles 1768system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41329046000 # number of ReadReq MSHR miss cycles 1769system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 30034339000 # number of WriteReq MSHR miss cycles 1770system.cpu1.dcache.WriteReq_mshr_miss_latency::total 30034339000 # number of WriteReq MSHR miss cycles 1771system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15914789000 # number of SoftPFReq MSHR miss cycles 1772system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15914789000 # number of SoftPFReq MSHR miss cycles 1773system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 14484285500 # number of WriteLineReq MSHR miss cycles 1774system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 14484285500 # number of WriteLineReq MSHR miss cycles 1775system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1714801500 # number of LoadLockedReq MSHR miss cycles 1776system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1714801500 # number of LoadLockedReq MSHR miss cycles 1777system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5327664500 # number of StoreCondReq MSHR miss cycles 1778system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5327664500 # number of StoreCondReq MSHR miss cycles 1779system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4914500 # number of StoreCondFailReq MSHR miss cycles 1780system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4914500 # number of StoreCondFailReq MSHR miss cycles 1781system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 85847670500 # number of demand (read+write) MSHR miss cycles 1782system.cpu1.dcache.demand_mshr_miss_latency::total 85847670500 # number of demand (read+write) MSHR miss cycles 1783system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101762459500 # number of overall MSHR miss cycles 1784system.cpu1.dcache.overall_mshr_miss_latency::total 101762459500 # number of overall MSHR miss cycles 1785system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 919733500 # number of ReadReq MSHR uncacheable cycles 1786system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 919733500 # number of ReadReq MSHR uncacheable cycles 1787system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 919733500 # number of overall MSHR uncacheable cycles 1788system.cpu1.dcache.overall_mshr_uncacheable_latency::total 919733500 # number of overall MSHR uncacheable cycles 1789system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036768 # mshr miss rate for ReadReq accesses 1790system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036768 # mshr miss rate for ReadReq accesses 1791system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019536 # mshr miss rate for WriteReq accesses 1792system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019536 # mshr miss rate for WriteReq accesses 1793system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.763222 # mshr miss rate for SoftPFReq accesses 1794system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.763222 # mshr miss rate for SoftPFReq accesses 1795system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.923389 # mshr miss rate for WriteLineReq accesses 1796system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.923389 # mshr miss rate for WriteLineReq accesses 1797system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065139 # mshr miss rate for LoadLockedReq accesses 1798system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065139 # mshr miss rate for LoadLockedReq accesses 1799system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108506 # mshr miss rate for StoreCondReq accesses 1800system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108506 # mshr miss rate for StoreCondReq accesses 1801system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031386 # mshr miss rate for demand accesses 1802system.cpu1.dcache.demand_mshr_miss_rate::total 0.031386 # mshr miss rate for demand accesses 1803system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035633 # mshr miss rate for overall accesses 1804system.cpu1.dcache.overall_mshr_miss_rate::total 0.035633 # mshr miss rate for overall accesses 1805system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14625.215685 # average ReadReq mshr miss latency 1806system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14625.215685 # average ReadReq mshr miss latency 1807system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22503.329682 # average WriteReq mshr miss latency 1808system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22503.329682 # average WriteReq mshr miss latency 1809system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24536.042946 # average SoftPFReq mshr miss latency 1810system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24536.042946 # average SoftPFReq mshr miss latency 1811system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 35336.230388 # average WriteLineReq mshr miss latency 1812system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 35336.230388 # average WriteLineReq mshr miss latency 1813system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14316.258975 # average LoadLockedReq mshr miss latency 1814system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14316.258975 # average LoadLockedReq mshr miss latency 1815system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26717.406022 # average StoreCondReq mshr miss latency 1816system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26717.406022 # average StoreCondReq mshr miss latency | 1729system.cpu1.dcache.writebacks::writebacks 4810864 # number of writebacks 1730system.cpu1.dcache.writebacks::total 4810864 # number of writebacks 1731system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 357052 # number of ReadReq MSHR hits 1732system.cpu1.dcache.ReadReq_mshr_hits::total 357052 # number of ReadReq MSHR hits 1733system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 892415 # number of WriteReq MSHR hits 1734system.cpu1.dcache.WriteReq_mshr_hits::total 892415 # number of WriteReq MSHR hits 1735system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 74 # number of WriteLineReq MSHR hits 1736system.cpu1.dcache.WriteLineReq_mshr_hits::total 74 # number of WriteLineReq MSHR hits 1737system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 40665 # number of LoadLockedReq MSHR hits 1738system.cpu1.dcache.LoadLockedReq_mshr_hits::total 40665 # number of LoadLockedReq MSHR hits 1739system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 58 # number of StoreCondReq MSHR hits 1740system.cpu1.dcache.StoreCondReq_mshr_hits::total 58 # number of StoreCondReq MSHR hits 1741system.cpu1.dcache.demand_mshr_hits::cpu1.data 1249541 # number of demand (read+write) MSHR hits 1742system.cpu1.dcache.demand_mshr_hits::total 1249541 # number of demand (read+write) MSHR hits 1743system.cpu1.dcache.overall_mshr_hits::cpu1.data 1249541 # number of overall MSHR hits 1744system.cpu1.dcache.overall_mshr_hits::total 1249541 # number of overall MSHR hits 1745system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2720133 # number of ReadReq MSHR misses 1746system.cpu1.dcache.ReadReq_mshr_misses::total 2720133 # number of ReadReq MSHR misses 1747system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1269904 # number of WriteReq MSHR misses 1748system.cpu1.dcache.WriteReq_mshr_misses::total 1269904 # number of WriteReq MSHR misses 1749system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 608760 # number of SoftPFReq MSHR misses 1750system.cpu1.dcache.SoftPFReq_mshr_misses::total 608760 # number of SoftPFReq MSHR misses 1751system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 415169 # number of WriteLineReq MSHR misses 1752system.cpu1.dcache.WriteLineReq_mshr_misses::total 415169 # number of WriteLineReq MSHR misses 1753system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 109782 # number of LoadLockedReq MSHR misses 1754system.cpu1.dcache.LoadLockedReq_mshr_misses::total 109782 # number of LoadLockedReq MSHR misses 1755system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 192883 # number of StoreCondReq MSHR misses 1756system.cpu1.dcache.StoreCondReq_mshr_misses::total 192883 # number of StoreCondReq MSHR misses 1757system.cpu1.dcache.demand_mshr_misses::cpu1.data 4405206 # number of demand (read+write) MSHR misses 1758system.cpu1.dcache.demand_mshr_misses::total 4405206 # number of demand (read+write) MSHR misses 1759system.cpu1.dcache.overall_mshr_misses::cpu1.data 5013966 # number of overall MSHR misses 1760system.cpu1.dcache.overall_mshr_misses::total 5013966 # number of overall MSHR misses 1761system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6941 # number of ReadReq MSHR uncacheable 1762system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6941 # number of ReadReq MSHR uncacheable 1763system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7280 # number of WriteReq MSHR uncacheable 1764system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7280 # number of WriteReq MSHR uncacheable 1765system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14221 # number of overall MSHR uncacheable misses 1766system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14221 # number of overall MSHR uncacheable misses 1767system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36972803500 # number of ReadReq MSHR miss cycles 1768system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36972803500 # number of ReadReq MSHR miss cycles 1769system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 23335803000 # number of WriteReq MSHR miss cycles 1770system.cpu1.dcache.WriteReq_mshr_miss_latency::total 23335803000 # number of WriteReq MSHR miss cycles 1771system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13834846000 # number of SoftPFReq MSHR miss cycles 1772system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13834846000 # number of SoftPFReq MSHR miss cycles 1773system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 9650155000 # number of WriteLineReq MSHR miss cycles 1774system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 9650155000 # number of WriteLineReq MSHR miss cycles 1775system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1512082000 # number of LoadLockedReq MSHR miss cycles 1776system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1512082000 # number of LoadLockedReq MSHR miss cycles 1777system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4580259000 # number of StoreCondReq MSHR miss cycles 1778system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4580259000 # number of StoreCondReq MSHR miss cycles 1779system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2341500 # number of StoreCondFailReq MSHR miss cycles 1780system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2341500 # number of StoreCondFailReq MSHR miss cycles 1781system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 69958761500 # number of demand (read+write) MSHR miss cycles 1782system.cpu1.dcache.demand_mshr_miss_latency::total 69958761500 # number of demand (read+write) MSHR miss cycles 1783system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 83793607500 # number of overall MSHR miss cycles 1784system.cpu1.dcache.overall_mshr_miss_latency::total 83793607500 # number of overall MSHR miss cycles 1785system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 837242500 # number of ReadReq MSHR uncacheable cycles 1786system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 837242500 # number of ReadReq MSHR uncacheable cycles 1787system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 837242500 # number of overall MSHR uncacheable cycles 1788system.cpu1.dcache.overall_mshr_uncacheable_latency::total 837242500 # number of overall MSHR uncacheable cycles 1789system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036217 # mshr miss rate for ReadReq accesses 1790system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036217 # mshr miss rate for ReadReq accesses 1791system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018943 # mshr miss rate for WriteReq accesses 1792system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018943 # mshr miss rate for WriteReq accesses 1793system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.754792 # mshr miss rate for SoftPFReq accesses 1794system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.754792 # mshr miss rate for SoftPFReq accesses 1795system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.911436 # mshr miss rate for WriteLineReq accesses 1796system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.911436 # mshr miss rate for WriteLineReq accesses 1797system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063180 # mshr miss rate for LoadLockedReq accesses 1798system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063180 # mshr miss rate for LoadLockedReq accesses 1799system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.111072 # mshr miss rate for StoreCondReq accesses 1800system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.111072 # mshr miss rate for StoreCondReq accesses 1801system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030892 # mshr miss rate for demand accesses 1802system.cpu1.dcache.demand_mshr_miss_rate::total 0.030892 # mshr miss rate for demand accesses 1803system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034963 # mshr miss rate for overall accesses 1804system.cpu1.dcache.overall_mshr_miss_rate::total 0.034963 # mshr miss rate for overall accesses 1805system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13592.277841 # average ReadReq mshr miss latency 1806system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13592.277841 # average ReadReq mshr miss latency 1807system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18376.037086 # average WriteReq mshr miss latency 1808system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18376.037086 # average WriteReq mshr miss latency 1809system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22726.273080 # average SoftPFReq mshr miss latency 1810system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22726.273080 # average SoftPFReq mshr miss latency 1811system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23243.919946 # average WriteLineReq mshr miss latency 1812system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23243.919946 # average WriteLineReq mshr miss latency 1813system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13773.496566 # average LoadLockedReq mshr miss latency 1814system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13773.496566 # average LoadLockedReq mshr miss latency 1815system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23746.307347 # average StoreCondReq mshr miss latency 1816system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23746.307347 # average StoreCondReq mshr miss latency |
| 1817system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1818system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1817system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1818system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1819system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18783.252127 # average overall mshr miss latency 1820system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18783.252127 # average overall mshr miss latency 1821system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19498.212803 # average overall mshr miss latency 1822system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19498.212803 # average overall mshr miss latency 1823system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125355.526782 # average ReadReq mshr uncacheable latency 1824system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 125355.526782 # average ReadReq mshr uncacheable latency 1825system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 61405.628255 # average overall mshr uncacheable latency 1826system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 61405.628255 # average overall mshr uncacheable latency 1827system.cpu1.icache.tags.replacements 8449872 # number of replacements 1828system.cpu1.icache.tags.tagsinuse 506.781387 # Cycle average of tags in use 1829system.cpu1.icache.tags.total_refs 217357255 # Total number of references to valid blocks. 1830system.cpu1.icache.tags.sampled_refs 8450384 # Sample count of references to valid blocks. 1831system.cpu1.icache.tags.avg_refs 25.721583 # Average number of references to valid blocks. 1832system.cpu1.icache.tags.warmup_cycle 8379180185000 # Cycle when the warmup percentage was hit. 1833system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.781387 # Average occupied blocks per requestor 1834system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989807 # Average percentage of cache occupancy 1835system.cpu1.icache.tags.occ_percent::total 0.989807 # Average percentage of cache occupancy | 1819system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15880.928497 # average overall mshr miss latency 1820system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15880.928497 # average overall mshr miss latency 1821system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16712.041426 # average overall mshr miss latency 1822system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16712.041426 # average overall mshr miss latency 1823system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 120622.748883 # average ReadReq mshr uncacheable latency 1824system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 120622.748883 # average ReadReq mshr uncacheable latency 1825system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 58873.672738 # average overall mshr uncacheable latency 1826system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 58873.672738 # average overall mshr uncacheable latency 1827system.cpu1.icache.tags.replacements 8744967 # number of replacements 1828system.cpu1.icache.tags.tagsinuse 507.224680 # Cycle average of tags in use 1829system.cpu1.icache.tags.total_refs 210419103 # Total number of references to valid blocks. 1830system.cpu1.icache.tags.sampled_refs 8745479 # Sample count of references to valid blocks. 1831system.cpu1.icache.tags.avg_refs 24.060329 # Average number of references to valid blocks. 1832system.cpu1.icache.tags.warmup_cycle 8367967785000 # Cycle when the warmup percentage was hit. 1833system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.224680 # Average occupied blocks per requestor 1834system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990673 # Average percentage of cache occupancy 1835system.cpu1.icache.tags.occ_percent::total 0.990673 # Average percentage of cache occupancy |
| 1836system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1836system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1837system.cpu1.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id 1838system.cpu1.icache.tags.age_task_id_blocks_1024::1 365 # Occupied blocks per task id 1839system.cpu1.icache.tags.age_task_id_blocks_1024::2 63 # Occupied blocks per task id | 1837system.cpu1.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 1838system.cpu1.icache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id 1839system.cpu1.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id |
| 1840system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1840system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1841system.cpu1.icache.tags.tag_accesses 460065662 # Number of tag accesses 1842system.cpu1.icache.tags.data_accesses 460065662 # Number of data accesses 1843system.cpu1.icache.ReadReq_hits::cpu1.inst 217357255 # number of ReadReq hits 1844system.cpu1.icache.ReadReq_hits::total 217357255 # number of ReadReq hits 1845system.cpu1.icache.demand_hits::cpu1.inst 217357255 # number of demand (read+write) hits 1846system.cpu1.icache.demand_hits::total 217357255 # number of demand (read+write) hits 1847system.cpu1.icache.overall_hits::cpu1.inst 217357255 # number of overall hits 1848system.cpu1.icache.overall_hits::total 217357255 # number of overall hits 1849system.cpu1.icache.ReadReq_misses::cpu1.inst 8450384 # number of ReadReq misses 1850system.cpu1.icache.ReadReq_misses::total 8450384 # number of ReadReq misses 1851system.cpu1.icache.demand_misses::cpu1.inst 8450384 # number of demand (read+write) misses 1852system.cpu1.icache.demand_misses::total 8450384 # number of demand (read+write) misses 1853system.cpu1.icache.overall_misses::cpu1.inst 8450384 # number of overall misses 1854system.cpu1.icache.overall_misses::total 8450384 # number of overall misses 1855system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 88216596500 # number of ReadReq miss cycles 1856system.cpu1.icache.ReadReq_miss_latency::total 88216596500 # number of ReadReq miss cycles 1857system.cpu1.icache.demand_miss_latency::cpu1.inst 88216596500 # number of demand (read+write) miss cycles 1858system.cpu1.icache.demand_miss_latency::total 88216596500 # number of demand (read+write) miss cycles 1859system.cpu1.icache.overall_miss_latency::cpu1.inst 88216596500 # number of overall miss cycles 1860system.cpu1.icache.overall_miss_latency::total 88216596500 # number of overall miss cycles 1861system.cpu1.icache.ReadReq_accesses::cpu1.inst 225807639 # number of ReadReq accesses(hits+misses) 1862system.cpu1.icache.ReadReq_accesses::total 225807639 # number of ReadReq accesses(hits+misses) 1863system.cpu1.icache.demand_accesses::cpu1.inst 225807639 # number of demand (read+write) accesses 1864system.cpu1.icache.demand_accesses::total 225807639 # number of demand (read+write) accesses 1865system.cpu1.icache.overall_accesses::cpu1.inst 225807639 # number of overall (read+write) accesses 1866system.cpu1.icache.overall_accesses::total 225807639 # number of overall (read+write) accesses 1867system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037423 # miss rate for ReadReq accesses 1868system.cpu1.icache.ReadReq_miss_rate::total 0.037423 # miss rate for ReadReq accesses 1869system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037423 # miss rate for demand accesses 1870system.cpu1.icache.demand_miss_rate::total 0.037423 # miss rate for demand accesses 1871system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037423 # miss rate for overall accesses 1872system.cpu1.icache.overall_miss_rate::total 0.037423 # miss rate for overall accesses 1873system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10439.359501 # average ReadReq miss latency 1874system.cpu1.icache.ReadReq_avg_miss_latency::total 10439.359501 # average ReadReq miss latency 1875system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10439.359501 # average overall miss latency 1876system.cpu1.icache.demand_avg_miss_latency::total 10439.359501 # average overall miss latency 1877system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10439.359501 # average overall miss latency 1878system.cpu1.icache.overall_avg_miss_latency::total 10439.359501 # average overall miss latency | 1841system.cpu1.icache.tags.tag_accesses 447074643 # Number of tag accesses 1842system.cpu1.icache.tags.data_accesses 447074643 # Number of data accesses 1843system.cpu1.icache.ReadReq_hits::cpu1.inst 210419103 # number of ReadReq hits 1844system.cpu1.icache.ReadReq_hits::total 210419103 # number of ReadReq hits 1845system.cpu1.icache.demand_hits::cpu1.inst 210419103 # number of demand (read+write) hits 1846system.cpu1.icache.demand_hits::total 210419103 # number of demand (read+write) hits 1847system.cpu1.icache.overall_hits::cpu1.inst 210419103 # number of overall hits 1848system.cpu1.icache.overall_hits::total 210419103 # number of overall hits 1849system.cpu1.icache.ReadReq_misses::cpu1.inst 8745479 # number of ReadReq misses 1850system.cpu1.icache.ReadReq_misses::total 8745479 # number of ReadReq misses 1851system.cpu1.icache.demand_misses::cpu1.inst 8745479 # number of demand (read+write) misses 1852system.cpu1.icache.demand_misses::total 8745479 # number of demand (read+write) misses 1853system.cpu1.icache.overall_misses::cpu1.inst 8745479 # number of overall misses 1854system.cpu1.icache.overall_misses::total 8745479 # number of overall misses 1855system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 88268174500 # number of ReadReq miss cycles 1856system.cpu1.icache.ReadReq_miss_latency::total 88268174500 # number of ReadReq miss cycles 1857system.cpu1.icache.demand_miss_latency::cpu1.inst 88268174500 # number of demand (read+write) miss cycles 1858system.cpu1.icache.demand_miss_latency::total 88268174500 # number of demand (read+write) miss cycles 1859system.cpu1.icache.overall_miss_latency::cpu1.inst 88268174500 # number of overall miss cycles 1860system.cpu1.icache.overall_miss_latency::total 88268174500 # number of overall miss cycles 1861system.cpu1.icache.ReadReq_accesses::cpu1.inst 219164582 # number of ReadReq accesses(hits+misses) 1862system.cpu1.icache.ReadReq_accesses::total 219164582 # number of ReadReq accesses(hits+misses) 1863system.cpu1.icache.demand_accesses::cpu1.inst 219164582 # number of demand (read+write) accesses 1864system.cpu1.icache.demand_accesses::total 219164582 # number of demand (read+write) accesses 1865system.cpu1.icache.overall_accesses::cpu1.inst 219164582 # number of overall (read+write) accesses 1866system.cpu1.icache.overall_accesses::total 219164582 # number of overall (read+write) accesses 1867system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.039904 # miss rate for ReadReq accesses 1868system.cpu1.icache.ReadReq_miss_rate::total 0.039904 # miss rate for ReadReq accesses 1869system.cpu1.icache.demand_miss_rate::cpu1.inst 0.039904 # miss rate for demand accesses 1870system.cpu1.icache.demand_miss_rate::total 0.039904 # miss rate for demand accesses 1871system.cpu1.icache.overall_miss_rate::cpu1.inst 0.039904 # miss rate for overall accesses 1872system.cpu1.icache.overall_miss_rate::total 0.039904 # miss rate for overall accesses 1873system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10093.006284 # average ReadReq miss latency 1874system.cpu1.icache.ReadReq_avg_miss_latency::total 10093.006284 # average ReadReq miss latency 1875system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10093.006284 # average overall miss latency 1876system.cpu1.icache.demand_avg_miss_latency::total 10093.006284 # average overall miss latency 1877system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10093.006284 # average overall miss latency 1878system.cpu1.icache.overall_avg_miss_latency::total 10093.006284 # average overall miss latency |
| 1879system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1880system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1881system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1882system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1883system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1884system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1879system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1880system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1881system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1882system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1883system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1884system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1885system.cpu1.icache.writebacks::writebacks 8449872 # number of writebacks 1886system.cpu1.icache.writebacks::total 8449872 # number of writebacks 1887system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8450384 # number of ReadReq MSHR misses 1888system.cpu1.icache.ReadReq_mshr_misses::total 8450384 # number of ReadReq MSHR misses 1889system.cpu1.icache.demand_mshr_misses::cpu1.inst 8450384 # number of demand (read+write) MSHR misses 1890system.cpu1.icache.demand_mshr_misses::total 8450384 # number of demand (read+write) MSHR misses 1891system.cpu1.icache.overall_mshr_misses::cpu1.inst 8450384 # number of overall MSHR misses 1892system.cpu1.icache.overall_mshr_misses::total 8450384 # number of overall MSHR misses | 1885system.cpu1.icache.writebacks::writebacks 8744967 # number of writebacks 1886system.cpu1.icache.writebacks::total 8744967 # number of writebacks 1887system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8745479 # number of ReadReq MSHR misses 1888system.cpu1.icache.ReadReq_mshr_misses::total 8745479 # number of ReadReq MSHR misses 1889system.cpu1.icache.demand_mshr_misses::cpu1.inst 8745479 # number of demand (read+write) MSHR misses 1890system.cpu1.icache.demand_mshr_misses::total 8745479 # number of demand (read+write) MSHR misses 1891system.cpu1.icache.overall_mshr_misses::cpu1.inst 8745479 # number of overall MSHR misses 1892system.cpu1.icache.overall_mshr_misses::total 8745479 # number of overall MSHR misses |
| 1893system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 1894system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable 1895system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 1896system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses | 1893system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable 1894system.cpu1.icache.ReadReq_mshr_uncacheable::total 93 # number of ReadReq MSHR uncacheable 1895system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses 1896system.cpu1.icache.overall_mshr_uncacheable_misses::total 93 # number of overall MSHR uncacheable misses |
| 1897system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 83991404500 # number of ReadReq MSHR miss cycles 1898system.cpu1.icache.ReadReq_mshr_miss_latency::total 83991404500 # number of ReadReq MSHR miss cycles 1899system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 83991404500 # number of demand (read+write) MSHR miss cycles 1900system.cpu1.icache.demand_mshr_miss_latency::total 83991404500 # number of demand (read+write) MSHR miss cycles 1901system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 83991404500 # number of overall MSHR miss cycles 1902system.cpu1.icache.overall_mshr_miss_latency::total 83991404500 # number of overall MSHR miss cycles 1903system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13018000 # number of ReadReq MSHR uncacheable cycles 1904system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13018000 # number of ReadReq MSHR uncacheable cycles 1905system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13018000 # number of overall MSHR uncacheable cycles 1906system.cpu1.icache.overall_mshr_uncacheable_latency::total 13018000 # number of overall MSHR uncacheable cycles 1907system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037423 # mshr miss rate for ReadReq accesses 1908system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037423 # mshr miss rate for ReadReq accesses 1909system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037423 # mshr miss rate for demand accesses 1910system.cpu1.icache.demand_mshr_miss_rate::total 0.037423 # mshr miss rate for demand accesses 1911system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037423 # mshr miss rate for overall accesses 1912system.cpu1.icache.overall_mshr_miss_rate::total 0.037423 # mshr miss rate for overall accesses 1913system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9939.359501 # average ReadReq mshr miss latency 1914system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9939.359501 # average ReadReq mshr miss latency 1915system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9939.359501 # average overall mshr miss latency 1916system.cpu1.icache.demand_avg_mshr_miss_latency::total 9939.359501 # average overall mshr miss latency 1917system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9939.359501 # average overall mshr miss latency 1918system.cpu1.icache.overall_avg_mshr_miss_latency::total 9939.359501 # average overall mshr miss latency 1919system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 139978.494624 # average ReadReq mshr uncacheable latency 1920system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 139978.494624 # average ReadReq mshr uncacheable latency 1921system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 139978.494624 # average overall mshr uncacheable latency 1922system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 139978.494624 # average overall mshr uncacheable latency 1923system.cpu1.l2cache.prefetcher.num_hwpf_issued 7137751 # number of hwpf issued 1924system.cpu1.l2cache.prefetcher.pfIdentified 7137894 # number of prefetch candidates identified 1925system.cpu1.l2cache.prefetcher.pfBufferHit 127 # number of redundant prefetches already in prefetch queue | 1897system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 83895435000 # number of ReadReq MSHR miss cycles 1898system.cpu1.icache.ReadReq_mshr_miss_latency::total 83895435000 # number of ReadReq MSHR miss cycles 1899system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 83895435000 # number of demand (read+write) MSHR miss cycles 1900system.cpu1.icache.demand_mshr_miss_latency::total 83895435000 # number of demand (read+write) MSHR miss cycles 1901system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 83895435000 # number of overall MSHR miss cycles 1902system.cpu1.icache.overall_mshr_miss_latency::total 83895435000 # number of overall MSHR miss cycles 1903system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8450000 # number of ReadReq MSHR uncacheable cycles 1904system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8450000 # number of ReadReq MSHR uncacheable cycles 1905system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8450000 # number of overall MSHR uncacheable cycles 1906system.cpu1.icache.overall_mshr_uncacheable_latency::total 8450000 # number of overall MSHR uncacheable cycles 1907system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for ReadReq accesses 1908system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.039904 # mshr miss rate for ReadReq accesses 1909system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for demand accesses 1910system.cpu1.icache.demand_mshr_miss_rate::total 0.039904 # mshr miss rate for demand accesses 1911system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.039904 # mshr miss rate for overall accesses 1912system.cpu1.icache.overall_mshr_miss_rate::total 0.039904 # mshr miss rate for overall accesses 1913system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average ReadReq mshr miss latency 1914system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9593.006284 # average ReadReq mshr miss latency 1915system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average overall mshr miss latency 1916system.cpu1.icache.demand_avg_mshr_miss_latency::total 9593.006284 # average overall mshr miss latency 1917system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9593.006284 # average overall mshr miss latency 1918system.cpu1.icache.overall_avg_mshr_miss_latency::total 9593.006284 # average overall mshr miss latency 1919system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average ReadReq mshr uncacheable latency 1920system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90860.215054 # average ReadReq mshr uncacheable latency 1921system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90860.215054 # average overall mshr uncacheable latency 1922system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90860.215054 # average overall mshr uncacheable latency 1923system.cpu1.l2cache.prefetcher.num_hwpf_issued 6641051 # number of hwpf issued 1924system.cpu1.l2cache.prefetcher.pfIdentified 6641093 # number of prefetch candidates identified 1925system.cpu1.l2cache.prefetcher.pfBufferHit 36 # number of redundant prefetches already in prefetch queue |
| 1926system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1927system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 1926system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1927system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 1928system.cpu1.l2cache.prefetcher.pfSpanPage 851890 # number of prefetches not generated due to page crossing 1929system.cpu1.l2cache.tags.replacements 2314380 # number of replacements 1930system.cpu1.l2cache.tags.tagsinuse 13359.571881 # Cycle average of tags in use 1931system.cpu1.l2cache.tags.total_refs 21237271 # Total number of references to valid blocks. 1932system.cpu1.l2cache.tags.sampled_refs 2330274 # Sample count of references to valid blocks. 1933system.cpu1.l2cache.tags.avg_refs 9.113637 # Average number of references to valid blocks. 1934system.cpu1.l2cache.tags.warmup_cycle 10056444277000 # Cycle when the warmup percentage was hit. 1935system.cpu1.l2cache.tags.occ_blocks::writebacks 12441.859609 # Average occupied blocks per requestor 1936system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 52.856295 # Average occupied blocks per requestor 1937system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 59.323629 # Average occupied blocks per requestor 1938system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 805.532348 # Average occupied blocks per requestor 1939system.cpu1.l2cache.tags.occ_percent::writebacks 0.759391 # Average percentage of cache occupancy 1940system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003226 # Average percentage of cache occupancy 1941system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003621 # Average percentage of cache occupancy 1942system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.049166 # Average percentage of cache occupancy 1943system.cpu1.l2cache.tags.occ_percent::total 0.815404 # Average percentage of cache occupancy 1944system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1023 # Occupied blocks per task id 1945system.cpu1.l2cache.tags.occ_task_id_blocks::1023 70 # Occupied blocks per task id 1946system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14801 # Occupied blocks per task id 1947system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id 1948system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id 1949system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 326 # Occupied blocks per task id 1950system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 596 # Occupied blocks per task id 1951system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 82 # Occupied blocks per task id | 1928system.cpu1.l2cache.prefetcher.pfSpanPage 796339 # number of prefetches not generated due to page crossing 1929system.cpu1.l2cache.tags.replacements 2218428 # number of replacements 1930system.cpu1.l2cache.tags.tagsinuse 13419.558556 # Cycle average of tags in use 1931system.cpu1.l2cache.tags.total_refs 21617433 # Total number of references to valid blocks. 1932system.cpu1.l2cache.tags.sampled_refs 2233865 # Sample count of references to valid blocks. 1933system.cpu1.l2cache.tags.avg_refs 9.677144 # Average number of references to valid blocks. 1934system.cpu1.l2cache.tags.warmup_cycle 10005238958500 # Cycle when the warmup percentage was hit. 1935system.cpu1.l2cache.tags.occ_blocks::writebacks 12516.094704 # Average occupied blocks per requestor 1936system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 63.377354 # Average occupied blocks per requestor 1937system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 44.102544 # Average occupied blocks per requestor 1938system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 795.983954 # Average occupied blocks per requestor 1939system.cpu1.l2cache.tags.occ_percent::writebacks 0.763922 # Average percentage of cache occupancy 1940system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003868 # Average percentage of cache occupancy 1941system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.002692 # Average percentage of cache occupancy 1942system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048583 # Average percentage of cache occupancy 1943system.cpu1.l2cache.tags.occ_percent::total 0.819065 # Average percentage of cache occupancy 1944system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1192 # Occupied blocks per task id 1945system.cpu1.l2cache.tags.occ_task_id_blocks::1023 81 # Occupied blocks per task id 1946system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14164 # Occupied blocks per task id 1947system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 158 # Occupied blocks per task id 1948system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 771 # Occupied blocks per task id 1949system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 263 # Occupied blocks per task id |
| 1952system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id | 1950system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id |
| 1953system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 38 # Occupied blocks per task id 1954system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 29 # Occupied blocks per task id 1955system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 1956system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 1957system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 643 # Occupied blocks per task id 1958system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5454 # Occupied blocks per task id 1959system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8033 # Occupied blocks per task id 1960system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 613 # Occupied blocks per task id 1961system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.062439 # Percentage of cache occupancy per task id 1962system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004272 # Percentage of cache occupancy per task id 1963system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903381 # Percentage of cache occupancy per task id 1964system.cpu1.l2cache.tags.tag_accesses 455510636 # Number of tag accesses 1965system.cpu1.l2cache.tags.data_accesses 455510636 # Number of data accesses 1966system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 505028 # number of ReadReq hits 1967system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 167261 # number of ReadReq hits 1968system.cpu1.l2cache.ReadReq_hits::total 672289 # number of ReadReq hits 1969system.cpu1.l2cache.WritebackDirty_hits::writebacks 3161302 # number of WritebackDirty hits 1970system.cpu1.l2cache.WritebackDirty_hits::total 3161302 # number of WritebackDirty hits 1971system.cpu1.l2cache.WritebackClean_hits::writebacks 10298649 # number of WritebackClean hits 1972system.cpu1.l2cache.WritebackClean_hits::total 10298649 # number of WritebackClean hits 1973system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 586 # number of UpgradeReq hits 1974system.cpu1.l2cache.UpgradeReq_hits::total 586 # number of UpgradeReq hits 1975system.cpu1.l2cache.ReadExReq_hits::cpu1.data 836670 # number of ReadExReq hits 1976system.cpu1.l2cache.ReadExReq_hits::total 836670 # number of ReadExReq hits 1977system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 7769081 # number of ReadCleanReq hits 1978system.cpu1.l2cache.ReadCleanReq_hits::total 7769081 # number of ReadCleanReq hits 1979system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2629380 # number of ReadSharedReq hits 1980system.cpu1.l2cache.ReadSharedReq_hits::total 2629380 # number of ReadSharedReq hits 1981system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 161838 # number of InvalidateReq hits 1982system.cpu1.l2cache.InvalidateReq_hits::total 161838 # number of InvalidateReq hits 1983system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 505028 # number of demand (read+write) hits 1984system.cpu1.l2cache.demand_hits::cpu1.itb.walker 167261 # number of demand (read+write) hits 1985system.cpu1.l2cache.demand_hits::cpu1.inst 7769081 # number of demand (read+write) hits 1986system.cpu1.l2cache.demand_hits::cpu1.data 3466050 # number of demand (read+write) hits 1987system.cpu1.l2cache.demand_hits::total 11907420 # number of demand (read+write) hits 1988system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 505028 # number of overall hits 1989system.cpu1.l2cache.overall_hits::cpu1.itb.walker 167261 # number of overall hits 1990system.cpu1.l2cache.overall_hits::cpu1.inst 7769081 # number of overall hits 1991system.cpu1.l2cache.overall_hits::cpu1.data 3466050 # number of overall hits 1992system.cpu1.l2cache.overall_hits::total 11907420 # number of overall hits 1993system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12572 # number of ReadReq misses 1994system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9247 # number of ReadReq misses 1995system.cpu1.l2cache.ReadReq_misses::total 21819 # number of ReadReq misses 1996system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 231248 # number of UpgradeReq misses 1997system.cpu1.l2cache.UpgradeReq_misses::total 231248 # number of UpgradeReq misses 1998system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 199403 # number of SCUpgradeReq misses 1999system.cpu1.l2cache.SCUpgradeReq_misses::total 199403 # number of SCUpgradeReq misses 2000system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses 2001system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 2002system.cpu1.l2cache.ReadExReq_misses::cpu1.data 268541 # number of ReadExReq misses 2003system.cpu1.l2cache.ReadExReq_misses::total 268541 # number of ReadExReq misses 2004system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 681303 # number of ReadCleanReq misses 2005system.cpu1.l2cache.ReadCleanReq_misses::total 681303 # number of ReadCleanReq misses 2006system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 964682 # number of ReadSharedReq misses 2007system.cpu1.l2cache.ReadSharedReq_misses::total 964682 # number of ReadSharedReq misses 2008system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 246204 # number of InvalidateReq misses 2009system.cpu1.l2cache.InvalidateReq_misses::total 246204 # number of InvalidateReq misses 2010system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12572 # number of demand (read+write) misses 2011system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9247 # number of demand (read+write) misses 2012system.cpu1.l2cache.demand_misses::cpu1.inst 681303 # number of demand (read+write) misses 2013system.cpu1.l2cache.demand_misses::cpu1.data 1233223 # number of demand (read+write) misses 2014system.cpu1.l2cache.demand_misses::total 1936345 # number of demand (read+write) misses 2015system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12572 # number of overall misses 2016system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9247 # number of overall misses 2017system.cpu1.l2cache.overall_misses::cpu1.inst 681303 # number of overall misses 2018system.cpu1.l2cache.overall_misses::cpu1.data 1233223 # number of overall misses 2019system.cpu1.l2cache.overall_misses::total 1936345 # number of overall misses 2020system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 598416500 # number of ReadReq miss cycles 2021system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 470191500 # number of ReadReq miss cycles 2022system.cpu1.l2cache.ReadReq_miss_latency::total 1068608000 # number of ReadReq miss cycles 2023system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3369487000 # number of UpgradeReq miss cycles 2024system.cpu1.l2cache.UpgradeReq_miss_latency::total 3369487000 # number of UpgradeReq miss cycles 2025system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1909793500 # number of SCUpgradeReq miss cycles 2026system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1909793500 # number of SCUpgradeReq miss cycles 2027system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4827998 # number of SCUpgradeFailReq miss cycles 2028system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4827998 # number of SCUpgradeFailReq miss cycles 2029system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 14090220498 # number of ReadExReq miss cycles 2030system.cpu1.l2cache.ReadExReq_miss_latency::total 14090220498 # number of ReadExReq miss cycles 2031system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 24409955000 # number of ReadCleanReq miss cycles 2032system.cpu1.l2cache.ReadCleanReq_miss_latency::total 24409955000 # number of ReadCleanReq miss cycles 2033system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 36192984491 # number of ReadSharedReq miss cycles 2034system.cpu1.l2cache.ReadSharedReq_miss_latency::total 36192984491 # number of ReadSharedReq miss cycles 2035system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 484898500 # number of InvalidateReq miss cycles 2036system.cpu1.l2cache.InvalidateReq_miss_latency::total 484898500 # number of InvalidateReq miss cycles 2037system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 598416500 # number of demand (read+write) miss cycles 2038system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 470191500 # number of demand (read+write) miss cycles 2039system.cpu1.l2cache.demand_miss_latency::cpu1.inst 24409955000 # number of demand (read+write) miss cycles 2040system.cpu1.l2cache.demand_miss_latency::cpu1.data 50283204989 # number of demand (read+write) miss cycles 2041system.cpu1.l2cache.demand_miss_latency::total 75761767989 # number of demand (read+write) miss cycles 2042system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 598416500 # number of overall miss cycles 2043system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 470191500 # number of overall miss cycles 2044system.cpu1.l2cache.overall_miss_latency::cpu1.inst 24409955000 # number of overall miss cycles 2045system.cpu1.l2cache.overall_miss_latency::cpu1.data 50283204989 # number of overall miss cycles 2046system.cpu1.l2cache.overall_miss_latency::total 75761767989 # number of overall miss cycles 2047system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 517600 # number of ReadReq accesses(hits+misses) 2048system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 176508 # number of ReadReq accesses(hits+misses) 2049system.cpu1.l2cache.ReadReq_accesses::total 694108 # number of ReadReq accesses(hits+misses) 2050system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3161302 # number of WritebackDirty accesses(hits+misses) 2051system.cpu1.l2cache.WritebackDirty_accesses::total 3161302 # number of WritebackDirty accesses(hits+misses) 2052system.cpu1.l2cache.WritebackClean_accesses::writebacks 10298649 # number of WritebackClean accesses(hits+misses) 2053system.cpu1.l2cache.WritebackClean_accesses::total 10298649 # number of WritebackClean accesses(hits+misses) 2054system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 231834 # number of UpgradeReq accesses(hits+misses) 2055system.cpu1.l2cache.UpgradeReq_accesses::total 231834 # number of UpgradeReq accesses(hits+misses) 2056system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 199403 # number of SCUpgradeReq accesses(hits+misses) 2057system.cpu1.l2cache.SCUpgradeReq_accesses::total 199403 # number of SCUpgradeReq accesses(hits+misses) 2058system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 2059system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 2060system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1105211 # number of ReadExReq accesses(hits+misses) 2061system.cpu1.l2cache.ReadExReq_accesses::total 1105211 # number of ReadExReq accesses(hits+misses) 2062system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8450384 # number of ReadCleanReq accesses(hits+misses) 2063system.cpu1.l2cache.ReadCleanReq_accesses::total 8450384 # number of ReadCleanReq accesses(hits+misses) 2064system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3594062 # number of ReadSharedReq accesses(hits+misses) 2065system.cpu1.l2cache.ReadSharedReq_accesses::total 3594062 # number of ReadSharedReq accesses(hits+misses) 2066system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 408042 # number of InvalidateReq accesses(hits+misses) 2067system.cpu1.l2cache.InvalidateReq_accesses::total 408042 # number of InvalidateReq accesses(hits+misses) 2068system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 517600 # number of demand (read+write) accesses 2069system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 176508 # number of demand (read+write) accesses 2070system.cpu1.l2cache.demand_accesses::cpu1.inst 8450384 # number of demand (read+write) accesses 2071system.cpu1.l2cache.demand_accesses::cpu1.data 4699273 # number of demand (read+write) accesses 2072system.cpu1.l2cache.demand_accesses::total 13843765 # number of demand (read+write) accesses 2073system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 517600 # number of overall (read+write) accesses 2074system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 176508 # number of overall (read+write) accesses 2075system.cpu1.l2cache.overall_accesses::cpu1.inst 8450384 # number of overall (read+write) accesses 2076system.cpu1.l2cache.overall_accesses::cpu1.data 4699273 # number of overall (read+write) accesses 2077system.cpu1.l2cache.overall_accesses::total 13843765 # number of overall (read+write) accesses 2078system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.024289 # miss rate for ReadReq accesses 2079system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.052389 # miss rate for ReadReq accesses 2080system.cpu1.l2cache.ReadReq_miss_rate::total 0.031435 # miss rate for ReadReq accesses 2081system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.997472 # miss rate for UpgradeReq accesses 2082system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.997472 # miss rate for UpgradeReq accesses | 1951system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 54 # Occupied blocks per task id 1952system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1953system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 1954system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 1955system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id 1956system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4872 # Occupied blocks per task id 1957system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6319 # Occupied blocks per task id 1958system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2682 # Occupied blocks per task id 1959system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.072754 # Percentage of cache occupancy per task id 1960system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004944 # Percentage of cache occupancy per task id 1961system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.864502 # Percentage of cache occupancy per task id 1962system.cpu1.l2cache.tags.tag_accesses 457671450 # Number of tag accesses 1963system.cpu1.l2cache.tags.data_accesses 457671450 # Number of data accesses 1964system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 494400 # number of ReadReq hits 1965system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 160613 # number of ReadReq hits 1966system.cpu1.l2cache.ReadReq_hits::total 655013 # number of ReadReq hits 1967system.cpu1.l2cache.WritebackDirty_hits::writebacks 3026488 # number of WritebackDirty hits 1968system.cpu1.l2cache.WritebackDirty_hits::total 3026488 # number of WritebackDirty hits 1969system.cpu1.l2cache.WritebackClean_hits::writebacks 10527430 # number of WritebackClean hits 1970system.cpu1.l2cache.WritebackClean_hits::total 10527430 # number of WritebackClean hits 1971system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 434 # number of UpgradeReq hits 1972system.cpu1.l2cache.UpgradeReq_hits::total 434 # number of UpgradeReq hits 1973system.cpu1.l2cache.ReadExReq_hits::cpu1.data 789107 # number of ReadExReq hits 1974system.cpu1.l2cache.ReadExReq_hits::total 789107 # number of ReadExReq hits 1975system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 8072877 # number of ReadCleanReq hits 1976system.cpu1.l2cache.ReadCleanReq_hits::total 8072877 # number of ReadCleanReq hits 1977system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2507088 # number of ReadSharedReq hits 1978system.cpu1.l2cache.ReadSharedReq_hits::total 2507088 # number of ReadSharedReq hits 1979system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 171056 # number of InvalidateReq hits 1980system.cpu1.l2cache.InvalidateReq_hits::total 171056 # number of InvalidateReq hits 1981system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 494400 # number of demand (read+write) hits 1982system.cpu1.l2cache.demand_hits::cpu1.itb.walker 160613 # number of demand (read+write) hits 1983system.cpu1.l2cache.demand_hits::cpu1.inst 8072877 # number of demand (read+write) hits 1984system.cpu1.l2cache.demand_hits::cpu1.data 3296195 # number of demand (read+write) hits 1985system.cpu1.l2cache.demand_hits::total 12024085 # number of demand (read+write) hits 1986system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 494400 # number of overall hits 1987system.cpu1.l2cache.overall_hits::cpu1.itb.walker 160613 # number of overall hits 1988system.cpu1.l2cache.overall_hits::cpu1.inst 8072877 # number of overall hits 1989system.cpu1.l2cache.overall_hits::cpu1.data 3296195 # number of overall hits 1990system.cpu1.l2cache.overall_hits::total 12024085 # number of overall hits 1991system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11721 # number of ReadReq misses 1992system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8689 # number of ReadReq misses 1993system.cpu1.l2cache.ReadReq_misses::total 20410 # number of ReadReq misses 1994system.cpu1.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses 1995system.cpu1.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses 1996system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 1997system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses 1998system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 220631 # number of UpgradeReq misses 1999system.cpu1.l2cache.UpgradeReq_misses::total 220631 # number of UpgradeReq misses 2000system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 192879 # number of SCUpgradeReq misses 2001system.cpu1.l2cache.SCUpgradeReq_misses::total 192879 # number of SCUpgradeReq misses 2002system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses 2003system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 2004system.cpu1.l2cache.ReadExReq_misses::cpu1.data 261966 # number of ReadExReq misses 2005system.cpu1.l2cache.ReadExReq_misses::total 261966 # number of ReadExReq misses 2006system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 672602 # number of ReadCleanReq misses 2007system.cpu1.l2cache.ReadCleanReq_misses::total 672602 # number of ReadCleanReq misses 2008system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 931427 # number of ReadSharedReq misses 2009system.cpu1.l2cache.ReadSharedReq_misses::total 931427 # number of ReadSharedReq misses 2010system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 242391 # number of InvalidateReq misses 2011system.cpu1.l2cache.InvalidateReq_misses::total 242391 # number of InvalidateReq misses 2012system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11721 # number of demand (read+write) misses 2013system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8689 # number of demand (read+write) misses 2014system.cpu1.l2cache.demand_misses::cpu1.inst 672602 # number of demand (read+write) misses 2015system.cpu1.l2cache.demand_misses::cpu1.data 1193393 # number of demand (read+write) misses 2016system.cpu1.l2cache.demand_misses::total 1886405 # number of demand (read+write) misses 2017system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11721 # number of overall misses 2018system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8689 # number of overall misses 2019system.cpu1.l2cache.overall_misses::cpu1.inst 672602 # number of overall misses 2020system.cpu1.l2cache.overall_misses::cpu1.data 1193393 # number of overall misses 2021system.cpu1.l2cache.overall_misses::total 1886405 # number of overall misses 2022system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 429270500 # number of ReadReq miss cycles 2023system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 326619000 # number of ReadReq miss cycles 2024system.cpu1.l2cache.ReadReq_miss_latency::total 755889500 # number of ReadReq miss cycles 2025system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 1918862500 # number of UpgradeReq miss cycles 2026system.cpu1.l2cache.UpgradeReq_miss_latency::total 1918862500 # number of UpgradeReq miss cycles 2027system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1442678000 # number of SCUpgradeReq miss cycles 2028system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1442678000 # number of SCUpgradeReq miss cycles 2029system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2273499 # number of SCUpgradeFailReq miss cycles 2030system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2273499 # number of SCUpgradeFailReq miss cycles 2031system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10385042497 # number of ReadExReq miss cycles 2032system.cpu1.l2cache.ReadExReq_miss_latency::total 10385042497 # number of ReadExReq miss cycles 2033system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 22017991000 # number of ReadCleanReq miss cycles 2034system.cpu1.l2cache.ReadCleanReq_miss_latency::total 22017991000 # number of ReadCleanReq miss cycles 2035system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 30592821494 # number of ReadSharedReq miss cycles 2036system.cpu1.l2cache.ReadSharedReq_miss_latency::total 30592821494 # number of ReadSharedReq miss cycles 2037system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 352126000 # number of InvalidateReq miss cycles 2038system.cpu1.l2cache.InvalidateReq_miss_latency::total 352126000 # number of InvalidateReq miss cycles 2039system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 429270500 # number of demand (read+write) miss cycles 2040system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 326619000 # number of demand (read+write) miss cycles 2041system.cpu1.l2cache.demand_miss_latency::cpu1.inst 22017991000 # number of demand (read+write) miss cycles 2042system.cpu1.l2cache.demand_miss_latency::cpu1.data 40977863991 # number of demand (read+write) miss cycles 2043system.cpu1.l2cache.demand_miss_latency::total 63751744491 # number of demand (read+write) miss cycles 2044system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 429270500 # number of overall miss cycles 2045system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 326619000 # number of overall miss cycles 2046system.cpu1.l2cache.overall_miss_latency::cpu1.inst 22017991000 # number of overall miss cycles 2047system.cpu1.l2cache.overall_miss_latency::cpu1.data 40977863991 # number of overall miss cycles 2048system.cpu1.l2cache.overall_miss_latency::total 63751744491 # number of overall miss cycles 2049system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 506121 # number of ReadReq accesses(hits+misses) 2050system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 169302 # number of ReadReq accesses(hits+misses) 2051system.cpu1.l2cache.ReadReq_accesses::total 675423 # number of ReadReq accesses(hits+misses) 2052system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3026489 # number of WritebackDirty accesses(hits+misses) 2053system.cpu1.l2cache.WritebackDirty_accesses::total 3026489 # number of WritebackDirty accesses(hits+misses) 2054system.cpu1.l2cache.WritebackClean_accesses::writebacks 10527431 # number of WritebackClean accesses(hits+misses) 2055system.cpu1.l2cache.WritebackClean_accesses::total 10527431 # number of WritebackClean accesses(hits+misses) 2056system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 221065 # number of UpgradeReq accesses(hits+misses) 2057system.cpu1.l2cache.UpgradeReq_accesses::total 221065 # number of UpgradeReq accesses(hits+misses) 2058system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 192879 # number of SCUpgradeReq accesses(hits+misses) 2059system.cpu1.l2cache.SCUpgradeReq_accesses::total 192879 # number of SCUpgradeReq accesses(hits+misses) 2060system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 2061system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 2062system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1051073 # number of ReadExReq accesses(hits+misses) 2063system.cpu1.l2cache.ReadExReq_accesses::total 1051073 # number of ReadExReq accesses(hits+misses) 2064system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 8745479 # number of ReadCleanReq accesses(hits+misses) 2065system.cpu1.l2cache.ReadCleanReq_accesses::total 8745479 # number of ReadCleanReq accesses(hits+misses) 2066system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3438515 # number of ReadSharedReq accesses(hits+misses) 2067system.cpu1.l2cache.ReadSharedReq_accesses::total 3438515 # number of ReadSharedReq accesses(hits+misses) 2068system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 413447 # number of InvalidateReq accesses(hits+misses) 2069system.cpu1.l2cache.InvalidateReq_accesses::total 413447 # number of InvalidateReq accesses(hits+misses) 2070system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 506121 # number of demand (read+write) accesses 2071system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 169302 # number of demand (read+write) accesses 2072system.cpu1.l2cache.demand_accesses::cpu1.inst 8745479 # number of demand (read+write) accesses 2073system.cpu1.l2cache.demand_accesses::cpu1.data 4489588 # number of demand (read+write) accesses 2074system.cpu1.l2cache.demand_accesses::total 13910490 # number of demand (read+write) accesses 2075system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 506121 # number of overall (read+write) accesses 2076system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 169302 # number of overall (read+write) accesses 2077system.cpu1.l2cache.overall_accesses::cpu1.inst 8745479 # number of overall (read+write) accesses 2078system.cpu1.l2cache.overall_accesses::cpu1.data 4489588 # number of overall (read+write) accesses 2079system.cpu1.l2cache.overall_accesses::total 13910490 # number of overall (read+write) accesses 2080system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023158 # miss rate for ReadReq accesses 2081system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.051322 # miss rate for ReadReq accesses 2082system.cpu1.l2cache.ReadReq_miss_rate::total 0.030218 # miss rate for ReadReq accesses 2083system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses 2084system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses 2085system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 2086system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 2087system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.998037 # miss rate for UpgradeReq accesses 2088system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.998037 # miss rate for UpgradeReq accesses |
| 2083system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2084system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2085system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2086system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 2089system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2090system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2091system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2092system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 2087system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.242977 # miss rate for ReadExReq accesses 2088system.cpu1.l2cache.ReadExReq_miss_rate::total 0.242977 # miss rate for ReadExReq accesses 2089system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.080624 # miss rate for ReadCleanReq accesses 2090system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.080624 # miss rate for ReadCleanReq accesses 2091system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.268410 # miss rate for ReadSharedReq accesses 2092system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.268410 # miss rate for ReadSharedReq accesses 2093system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.603379 # miss rate for InvalidateReq accesses 2094system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.603379 # miss rate for InvalidateReq accesses 2095system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.024289 # miss rate for demand accesses 2096system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.052389 # miss rate for demand accesses 2097system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.080624 # miss rate for demand accesses 2098system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.262428 # miss rate for demand accesses 2099system.cpu1.l2cache.demand_miss_rate::total 0.139871 # miss rate for demand accesses 2100system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.024289 # miss rate for overall accesses 2101system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.052389 # miss rate for overall accesses 2102system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.080624 # miss rate for overall accesses 2103system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.262428 # miss rate for overall accesses 2104system.cpu1.l2cache.overall_miss_rate::total 0.139871 # miss rate for overall accesses 2105system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 47599.148902 # average ReadReq miss latency 2106system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 50848.004758 # average ReadReq miss latency 2107system.cpu1.l2cache.ReadReq_avg_miss_latency::total 48976.030066 # average ReadReq miss latency 2108system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14570.880613 # average UpgradeReq miss latency 2109system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14570.880613 # average UpgradeReq miss latency 2110system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9577.556506 # average SCUpgradeReq miss latency 2111system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9577.556506 # average SCUpgradeReq miss latency 2112system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 965599.600000 # average SCUpgradeFailReq miss latency 2113system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 965599.600000 # average SCUpgradeFailReq miss latency 2114system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 52469.531647 # average ReadExReq miss latency 2115system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 52469.531647 # average ReadExReq miss latency 2116system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35828.339226 # average ReadCleanReq miss latency 2117system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35828.339226 # average ReadCleanReq miss latency 2118system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 37518.046870 # average ReadSharedReq miss latency 2119system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 37518.046870 # average ReadSharedReq miss latency 2120system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1969.498871 # average InvalidateReq miss latency 2121system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1969.498871 # average InvalidateReq miss latency 2122system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 47599.148902 # average overall miss latency 2123system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 50848.004758 # average overall miss latency 2124system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35828.339226 # average overall miss latency 2125system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 40773.813811 # average overall miss latency 2126system.cpu1.l2cache.demand_avg_miss_latency::total 39126.172242 # average overall miss latency 2127system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 47599.148902 # average overall miss latency 2128system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 50848.004758 # average overall miss latency 2129system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35828.339226 # average overall miss latency 2130system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40773.813811 # average overall miss latency 2131system.cpu1.l2cache.overall_avg_miss_latency::total 39126.172242 # average overall miss latency | 2093system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.249237 # miss rate for ReadExReq accesses 2094system.cpu1.l2cache.ReadExReq_miss_rate::total 0.249237 # miss rate for ReadExReq accesses 2095system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.076909 # miss rate for ReadCleanReq accesses 2096system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.076909 # miss rate for ReadCleanReq accesses 2097system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.270881 # miss rate for ReadSharedReq accesses 2098system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.270881 # miss rate for ReadSharedReq accesses 2099system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.586269 # miss rate for InvalidateReq accesses 2100system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.586269 # miss rate for InvalidateReq accesses 2101system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023158 # miss rate for demand accesses 2102system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.051322 # miss rate for demand accesses 2103system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.076909 # miss rate for demand accesses 2104system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.265813 # miss rate for demand accesses 2105system.cpu1.l2cache.demand_miss_rate::total 0.135610 # miss rate for demand accesses 2106system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023158 # miss rate for overall accesses 2107system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.051322 # miss rate for overall accesses 2108system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.076909 # miss rate for overall accesses 2109system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.265813 # miss rate for overall accesses 2110system.cpu1.l2cache.overall_miss_rate::total 0.135610 # miss rate for overall accesses 2111system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 36624.050849 # average ReadReq miss latency 2112system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 37589.941305 # average ReadReq miss latency 2113system.cpu1.l2cache.ReadReq_avg_miss_latency::total 37035.252327 # average ReadReq miss latency 2114system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 8697.157244 # average UpgradeReq miss latency 2115system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 8697.157244 # average UpgradeReq miss latency 2116system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 7479.704893 # average SCUpgradeReq miss latency 2117system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 7479.704893 # average SCUpgradeReq miss latency 2118system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 568374.750000 # average SCUpgradeFailReq miss latency 2119system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 568374.750000 # average SCUpgradeFailReq miss latency 2120system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39642.711256 # average ReadExReq miss latency 2121system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39642.711256 # average ReadExReq miss latency 2122system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 32735.541970 # average ReadCleanReq miss latency 2123system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 32735.541970 # average ReadCleanReq miss latency 2124system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 32845.109165 # average ReadSharedReq miss latency 2125system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 32845.109165 # average ReadSharedReq miss latency 2126system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1452.718954 # average InvalidateReq miss latency 2127system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1452.718954 # average InvalidateReq miss latency 2128system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 36624.050849 # average overall miss latency 2129system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 37589.941305 # average overall miss latency 2130system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 32735.541970 # average overall miss latency 2131system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34337.275307 # average overall miss latency 2132system.cpu1.l2cache.demand_avg_miss_latency::total 33795.364458 # average overall miss latency 2133system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 36624.050849 # average overall miss latency 2134system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 37589.941305 # average overall miss latency 2135system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 32735.541970 # average overall miss latency 2136system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34337.275307 # average overall miss latency 2137system.cpu1.l2cache.overall_avg_miss_latency::total 33795.364458 # average overall miss latency |
| 2132system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2133system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2134system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2135system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2136system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2137system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2138system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2139system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2140system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2141system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2142system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2143system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2138system.cpu1.l2cache.unused_prefetches 46108 # number of HardPF blocks evicted w/o reference 2139system.cpu1.l2cache.writebacks::writebacks 1173247 # number of writebacks 2140system.cpu1.l2cache.writebacks::total 1173247 # number of writebacks 2141system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 3 # number of ReadReq MSHR hits | 2144system.cpu1.l2cache.unused_prefetches 43661 # number of HardPF blocks evicted w/o reference 2145system.cpu1.l2cache.writebacks::writebacks 1101410 # number of writebacks 2146system.cpu1.l2cache.writebacks::total 1101410 # number of writebacks 2147system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits 2148system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 2 # number of ReadReq MSHR hits |
| 2142system.cpu1.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits | 2149system.cpu1.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits |
| 2143system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6478 # number of ReadExReq MSHR hits 2144system.cpu1.l2cache.ReadExReq_mshr_hits::total 6478 # number of ReadExReq MSHR hits 2145system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits 2146system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 2147system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 790 # number of ReadSharedReq MSHR hits 2148system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 790 # number of ReadSharedReq MSHR hits 2149system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 13 # number of InvalidateReq MSHR hits 2150system.cpu1.l2cache.InvalidateReq_mshr_hits::total 13 # number of InvalidateReq MSHR hits 2151system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 3 # number of demand (read+write) MSHR hits 2152system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits 2153system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7268 # number of demand (read+write) MSHR hits 2154system.cpu1.l2cache.demand_mshr_hits::total 7272 # number of demand (read+write) MSHR hits 2155system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 3 # number of overall MSHR hits 2156system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits 2157system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7268 # number of overall MSHR hits 2158system.cpu1.l2cache.overall_mshr_hits::total 7272 # number of overall MSHR hits 2159system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12572 # number of ReadReq MSHR misses 2160system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9244 # number of ReadReq MSHR misses 2161system.cpu1.l2cache.ReadReq_mshr_misses::total 21816 # number of ReadReq MSHR misses 2162system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 768164 # number of HardPFReq MSHR misses 2163system.cpu1.l2cache.HardPFReq_mshr_misses::total 768164 # number of HardPFReq MSHR misses 2164system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 231248 # number of UpgradeReq MSHR misses 2165system.cpu1.l2cache.UpgradeReq_mshr_misses::total 231248 # number of UpgradeReq MSHR misses 2166system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 199403 # number of SCUpgradeReq MSHR misses 2167system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 199403 # number of SCUpgradeReq MSHR misses 2168system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses 2169system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 2170system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 262063 # number of ReadExReq MSHR misses 2171system.cpu1.l2cache.ReadExReq_mshr_misses::total 262063 # number of ReadExReq MSHR misses 2172system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 681302 # number of ReadCleanReq MSHR misses 2173system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 681302 # number of ReadCleanReq MSHR misses 2174system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 963892 # number of ReadSharedReq MSHR misses 2175system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 963892 # number of ReadSharedReq MSHR misses 2176system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 246191 # number of InvalidateReq MSHR misses 2177system.cpu1.l2cache.InvalidateReq_mshr_misses::total 246191 # number of InvalidateReq MSHR misses 2178system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12572 # number of demand (read+write) MSHR misses 2179system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9244 # number of demand (read+write) MSHR misses 2180system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 681302 # number of demand (read+write) MSHR misses 2181system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1225955 # number of demand (read+write) MSHR misses 2182system.cpu1.l2cache.demand_mshr_misses::total 1929073 # number of demand (read+write) MSHR misses 2183system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12572 # number of overall MSHR misses 2184system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9244 # number of overall MSHR misses 2185system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 681302 # number of overall MSHR misses 2186system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1225955 # number of overall MSHR misses 2187system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 768164 # number of overall MSHR misses 2188system.cpu1.l2cache.overall_mshr_misses::total 2697237 # number of overall MSHR misses | 2150system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 4694 # number of ReadExReq MSHR hits 2151system.cpu1.l2cache.ReadExReq_mshr_hits::total 4694 # number of ReadExReq MSHR hits 2152system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 3 # number of ReadCleanReq MSHR hits 2153system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 2154system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 558 # number of ReadSharedReq MSHR hits 2155system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 558 # number of ReadSharedReq MSHR hits 2156system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 2157system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 2 # number of demand (read+write) MSHR hits 2158system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits 2159system.cpu1.l2cache.demand_mshr_hits::cpu1.data 5252 # number of demand (read+write) MSHR hits 2160system.cpu1.l2cache.demand_mshr_hits::total 5258 # number of demand (read+write) MSHR hits 2161system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 2162system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 2 # number of overall MSHR hits 2163system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits 2164system.cpu1.l2cache.overall_mshr_hits::cpu1.data 5252 # number of overall MSHR hits 2165system.cpu1.l2cache.overall_mshr_hits::total 5258 # number of overall MSHR hits 2166system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11720 # number of ReadReq MSHR misses 2167system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8687 # number of ReadReq MSHR misses 2168system.cpu1.l2cache.ReadReq_mshr_misses::total 20407 # number of ReadReq MSHR misses 2169system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses 2170system.cpu1.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses 2171system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 2172system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses 2173system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 709103 # number of HardPFReq MSHR misses 2174system.cpu1.l2cache.HardPFReq_mshr_misses::total 709103 # number of HardPFReq MSHR misses 2175system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 220631 # number of UpgradeReq MSHR misses 2176system.cpu1.l2cache.UpgradeReq_mshr_misses::total 220631 # number of UpgradeReq MSHR misses 2177system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 192879 # number of SCUpgradeReq MSHR misses 2178system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 192879 # number of SCUpgradeReq MSHR misses 2179system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses 2180system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 2181system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 257272 # number of ReadExReq MSHR misses 2182system.cpu1.l2cache.ReadExReq_mshr_misses::total 257272 # number of ReadExReq MSHR misses 2183system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 672599 # number of ReadCleanReq MSHR misses 2184system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 672599 # number of ReadCleanReq MSHR misses 2185system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 930869 # number of ReadSharedReq MSHR misses 2186system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 930869 # number of ReadSharedReq MSHR misses 2187system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 242391 # number of InvalidateReq MSHR misses 2188system.cpu1.l2cache.InvalidateReq_mshr_misses::total 242391 # number of InvalidateReq MSHR misses 2189system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11720 # number of demand (read+write) MSHR misses 2190system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8687 # number of demand (read+write) MSHR misses 2191system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 672599 # number of demand (read+write) MSHR misses 2192system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1188141 # number of demand (read+write) MSHR misses 2193system.cpu1.l2cache.demand_mshr_misses::total 1881147 # number of demand (read+write) MSHR misses 2194system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11720 # number of overall MSHR misses 2195system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8687 # number of overall MSHR misses 2196system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 672599 # number of overall MSHR misses 2197system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1188141 # number of overall MSHR misses 2198system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 709103 # number of overall MSHR misses 2199system.cpu1.l2cache.overall_mshr_misses::total 2590250 # number of overall MSHR misses |
| 2189system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable | 2200system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable |
| 2190system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 7337 # number of ReadReq MSHR uncacheable 2191system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 7430 # number of ReadReq MSHR uncacheable 2192system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7641 # number of WriteReq MSHR uncacheable 2193system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7641 # number of WriteReq MSHR uncacheable | 2201system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6941 # number of ReadReq MSHR uncacheable 2202system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 7034 # number of ReadReq MSHR uncacheable 2203system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 7280 # number of WriteReq MSHR uncacheable 2204system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 7280 # number of WriteReq MSHR uncacheable |
| 2194system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses | 2205system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses |
| 2195system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 14978 # number of overall MSHR uncacheable misses 2196system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 15071 # number of overall MSHR uncacheable misses 2197system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 522984500 # number of ReadReq MSHR miss cycles 2198system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 414677500 # number of ReadReq MSHR miss cycles 2199system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 937662000 # number of ReadReq MSHR miss cycles 2200system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 38779162359 # number of HardPFReq MSHR miss cycles 2201system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 38779162359 # number of HardPFReq MSHR miss cycles 2202system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7121255497 # number of UpgradeReq MSHR miss cycles 2203system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7121255497 # number of UpgradeReq MSHR miss cycles 2204system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3827966500 # number of SCUpgradeReq MSHR miss cycles 2205system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3827966500 # number of SCUpgradeReq MSHR miss cycles 2206system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4485998 # number of SCUpgradeFailReq MSHR miss cycles 2207system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4485998 # number of SCUpgradeFailReq MSHR miss cycles 2208system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11549115998 # number of ReadExReq MSHR miss cycles 2209system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11549115998 # number of ReadExReq MSHR miss cycles 2210system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 20322130500 # number of ReadCleanReq MSHR miss cycles 2211system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 20322130500 # number of ReadCleanReq MSHR miss cycles 2212system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 30349496491 # number of ReadSharedReq MSHR miss cycles 2213system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 30349496491 # number of ReadSharedReq MSHR miss cycles 2214system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 11223039500 # number of InvalidateReq MSHR miss cycles 2215system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 11223039500 # number of InvalidateReq MSHR miss cycles 2216system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 522984500 # number of demand (read+write) MSHR miss cycles 2217system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 414677500 # number of demand (read+write) MSHR miss cycles 2218system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 20322130500 # number of demand (read+write) MSHR miss cycles 2219system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 41898612489 # number of demand (read+write) MSHR miss cycles 2220system.cpu1.l2cache.demand_mshr_miss_latency::total 63158404989 # number of demand (read+write) MSHR miss cycles 2221system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 522984500 # number of overall MSHR miss cycles 2222system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 414677500 # number of overall MSHR miss cycles 2223system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20322130500 # number of overall MSHR miss cycles 2224system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 41898612489 # number of overall MSHR miss cycles 2225system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 38779162359 # number of overall MSHR miss cycles 2226system.cpu1.l2cache.overall_mshr_miss_latency::total 101937567348 # number of overall MSHR miss cycles 2227system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12274000 # number of ReadReq MSHR uncacheable cycles 2228system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 860931500 # number of ReadReq MSHR uncacheable cycles 2229system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 873205500 # number of ReadReq MSHR uncacheable cycles 2230system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12274000 # number of overall MSHR uncacheable cycles 2231system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 860931500 # number of overall MSHR uncacheable cycles 2232system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 873205500 # number of overall MSHR uncacheable cycles 2233system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024289 # mshr miss rate for ReadReq accesses 2234system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.052372 # mshr miss rate for ReadReq accesses 2235system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.031430 # mshr miss rate for ReadReq accesses | 2206system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 14221 # number of overall MSHR uncacheable misses 2207system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 14314 # number of overall MSHR uncacheable misses 2208system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 358927500 # number of ReadReq MSHR miss cycles 2209system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 274457000 # number of ReadReq MSHR miss cycles 2210system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 633384500 # number of ReadReq MSHR miss cycles 2211system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 25470013765 # number of HardPFReq MSHR miss cycles 2212system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 25470013765 # number of HardPFReq MSHR miss cycles 2213system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4591069994 # number of UpgradeReq MSHR miss cycles 2214system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4591069994 # number of UpgradeReq MSHR miss cycles 2215system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3129353001 # number of SCUpgradeReq MSHR miss cycles 2216system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3129353001 # number of SCUpgradeReq MSHR miss cycles 2217system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2003499 # number of SCUpgradeFailReq MSHR miss cycles 2218system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2003499 # number of SCUpgradeFailReq MSHR miss cycles 2219system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8263742497 # number of ReadExReq MSHR miss cycles 2220system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8263742497 # number of ReadExReq MSHR miss cycles 2221system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 17982320500 # number of ReadCleanReq MSHR miss cycles 2222system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 17982320500 # number of ReadCleanReq MSHR miss cycles 2223system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 24961268994 # number of ReadSharedReq MSHR miss cycles 2224system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 24961268994 # number of ReadSharedReq MSHR miss cycles 2225system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6347282500 # number of InvalidateReq MSHR miss cycles 2226system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6347282500 # number of InvalidateReq MSHR miss cycles 2227system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 358927500 # number of demand (read+write) MSHR miss cycles 2228system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 274457000 # number of demand (read+write) MSHR miss cycles 2229system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 17982320500 # number of demand (read+write) MSHR miss cycles 2230system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 33225011491 # number of demand (read+write) MSHR miss cycles 2231system.cpu1.l2cache.demand_mshr_miss_latency::total 51840716491 # number of demand (read+write) MSHR miss cycles 2232system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 358927500 # number of overall MSHR miss cycles 2233system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 274457000 # number of overall MSHR miss cycles 2234system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 17982320500 # number of overall MSHR miss cycles 2235system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 33225011491 # number of overall MSHR miss cycles 2236system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 25470013765 # number of overall MSHR miss cycles 2237system.cpu1.l2cache.overall_mshr_miss_latency::total 77310730256 # number of overall MSHR miss cycles 2238system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7706000 # number of ReadReq MSHR uncacheable cycles 2239system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 781601000 # number of ReadReq MSHR uncacheable cycles 2240system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 789307000 # number of ReadReq MSHR uncacheable cycles 2241system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7706000 # number of overall MSHR uncacheable cycles 2242system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 781601000 # number of overall MSHR uncacheable cycles 2243system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 789307000 # number of overall MSHR uncacheable cycles 2244system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023157 # mshr miss rate for ReadReq accesses 2245system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.051311 # mshr miss rate for ReadReq accesses 2246system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.030214 # mshr miss rate for ReadReq accesses 2247system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses 2248system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses 2249system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 2250system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses |
| 2236system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2237system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 2251system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2252system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 2238system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997472 # mshr miss rate for UpgradeReq accesses 2239system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997472 # mshr miss rate for UpgradeReq accesses | 2253system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.998037 # mshr miss rate for UpgradeReq accesses 2254system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.998037 # mshr miss rate for UpgradeReq accesses |
| 2240system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2241system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2242system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2243system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 2255system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2256system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2257system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2258system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 2244system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.237116 # mshr miss rate for ReadExReq accesses 2245system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.237116 # mshr miss rate for ReadExReq accesses 2246system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.080624 # mshr miss rate for ReadCleanReq accesses 2247system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.080624 # mshr miss rate for ReadCleanReq accesses 2248system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.268190 # mshr miss rate for ReadSharedReq accesses 2249system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.268190 # mshr miss rate for ReadSharedReq accesses 2250system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.603347 # mshr miss rate for InvalidateReq accesses 2251system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.603347 # mshr miss rate for InvalidateReq accesses 2252system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024289 # mshr miss rate for demand accesses 2253system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.052372 # mshr miss rate for demand accesses 2254system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.080624 # mshr miss rate for demand accesses 2255system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.260882 # mshr miss rate for demand accesses 2256system.cpu1.l2cache.demand_mshr_miss_rate::total 0.139346 # mshr miss rate for demand accesses 2257system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024289 # mshr miss rate for overall accesses 2258system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.052372 # mshr miss rate for overall accesses 2259system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.080624 # mshr miss rate for overall accesses 2260system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.260882 # mshr miss rate for overall accesses | 2259system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.244771 # mshr miss rate for ReadExReq accesses 2260system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.244771 # mshr miss rate for ReadExReq accesses 2261system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for ReadCleanReq accesses 2262system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.076908 # mshr miss rate for ReadCleanReq accesses 2263system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.270718 # mshr miss rate for ReadSharedReq accesses 2264system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.270718 # mshr miss rate for ReadSharedReq accesses 2265system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.586269 # mshr miss rate for InvalidateReq accesses 2266system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.586269 # mshr miss rate for InvalidateReq accesses 2267system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023157 # mshr miss rate for demand accesses 2268system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.051311 # mshr miss rate for demand accesses 2269system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for demand accesses 2270system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.264644 # mshr miss rate for demand accesses 2271system.cpu1.l2cache.demand_mshr_miss_rate::total 0.135232 # mshr miss rate for demand accesses 2272system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023157 # mshr miss rate for overall accesses 2273system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.051311 # mshr miss rate for overall accesses 2274system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.076908 # mshr miss rate for overall accesses 2275system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.264644 # mshr miss rate for overall accesses |
| 2261system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 2276system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 2262system.cpu1.l2cache.overall_mshr_miss_rate::total 0.194834 # mshr miss rate for overall accesses 2263system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902 # average ReadReq mshr miss latency 2264system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average ReadReq mshr miss latency 2265system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 42980.473047 # average ReadReq mshr miss latency 2266system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50482.920781 # average HardPFReq mshr miss latency 2267system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50482.920781 # average HardPFReq mshr miss latency 2268system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 30794.884700 # average UpgradeReq mshr miss latency 2269system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30794.884700 # average UpgradeReq mshr miss latency 2270system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19197.135951 # average SCUpgradeReq mshr miss latency 2271system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19197.135951 # average SCUpgradeReq mshr miss latency 2272system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 897199.600000 # average SCUpgradeFailReq mshr miss latency 2273system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 897199.600000 # average SCUpgradeFailReq mshr miss latency 2274system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 44069.998428 # average ReadExReq mshr miss latency 2275system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 44069.998428 # average ReadExReq mshr miss latency 2276system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average ReadCleanReq mshr miss latency 2277system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29828.373467 # average ReadCleanReq mshr miss latency 2278system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31486.407700 # average ReadSharedReq mshr miss latency 2279system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31486.407700 # average ReadSharedReq mshr miss latency 2280system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 45586.717224 # average InvalidateReq mshr miss latency 2281system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 45586.717224 # average InvalidateReq mshr miss latency 2282system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902 # average overall mshr miss latency 2283system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average overall mshr miss latency 2284system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average overall mshr miss latency 2285system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34176.305402 # average overall mshr miss latency 2286system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32740.287687 # average overall mshr miss latency 2287system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41599.148902 # average overall mshr miss latency 2288system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average overall mshr miss latency 2289system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average overall mshr miss latency 2290system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34176.305402 # average overall mshr miss latency 2291system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50482.920781 # average overall mshr miss latency 2292system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37793.329747 # average overall mshr miss latency 2293system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average ReadReq mshr uncacheable latency 2294system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117341.079460 # average ReadReq mshr uncacheable latency 2295system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117524.293405 # average ReadReq mshr uncacheable latency 2296system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average overall mshr uncacheable latency 2297system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 57479.736948 # average overall mshr uncacheable latency 2298system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 57939.453255 # average overall mshr uncacheable latency 2299system.cpu1.toL2Bus.snoop_filter.tot_requests 27757324 # Total number of requests made to the snoop filter. 2300system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14199775 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2301system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1809 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2302system.cpu1.toL2Bus.snoop_filter.tot_snoops 2096264 # Total number of snoops made to the snoop filter. 2303system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2095922 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2304system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 342 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2305system.cpu1.toL2Bus.trans_dist::ReadReq 778911 # Transaction distribution 2306system.cpu1.toL2Bus.trans_dist::ReadResp 12918528 # Transaction distribution 2307system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 2308system.cpu1.toL2Bus.trans_dist::WriteReq 7641 # Transaction distribution 2309system.cpu1.toL2Bus.trans_dist::WriteResp 7641 # Transaction distribution 2310system.cpu1.toL2Bus.trans_dist::WritebackDirty 4342023 # Transaction distribution 2311system.cpu1.toL2Bus.trans_dist::WritebackClean 10300458 # Transaction distribution 2312system.cpu1.toL2Bus.trans_dist::CleanEvict 2852323 # Transaction distribution 2313system.cpu1.toL2Bus.trans_dist::HardPFReq 992320 # Transaction distribution 2314system.cpu1.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution 2315system.cpu1.toL2Bus.trans_dist::UpgradeReq 439929 # Transaction distribution 2316system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 359269 # Transaction distribution 2317system.cpu1.toL2Bus.trans_dist::UpgradeResp 498097 # Transaction distribution 2318system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 64 # Transaction distribution 2319system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution 2320system.cpu1.toL2Bus.trans_dist::ReadExReq 1135001 # Transaction distribution 2321system.cpu1.toL2Bus.trans_dist::ReadExResp 1111432 # Transaction distribution 2322system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8450384 # Transaction distribution 2323system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4652967 # Transaction distribution 2324system.cpu1.toL2Bus.trans_dist::InvalidateReq 462443 # Transaction distribution 2325system.cpu1.toL2Bus.trans_dist::InvalidateResp 408042 # Transaction distribution 2326system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 25350826 # Packet count per connected master and slave (bytes) 2327system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16287327 # Packet count per connected master and slave (bytes) 2328system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 370687 # Packet count per connected master and slave (bytes) 2329system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1094902 # Packet count per connected master and slave (bytes) 2330system.cpu1.toL2Bus.pkt_count::total 43103742 # Packet count per connected master and slave (bytes) 2331system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1081622336 # Cumulative packet size per connected master and slave (bytes) 2332system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 628052039 # Cumulative packet size per connected master and slave (bytes) 2333system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1412064 # Cumulative packet size per connected master and slave (bytes) 2334system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4140800 # Cumulative packet size per connected master and slave (bytes) 2335system.cpu1.toL2Bus.pkt_size::total 1715227239 # Cumulative packet size per connected master and slave (bytes) 2336system.cpu1.toL2Bus.snoops 6782222 # Total snoops (count) 2337system.cpu1.toL2Bus.snoop_fanout::samples 21311973 # Request fanout histogram 2338system.cpu1.toL2Bus.snoop_fanout::mean 0.112849 # Request fanout histogram 2339system.cpu1.toL2Bus.snoop_fanout::stdev 0.316459 # Request fanout histogram | 2277system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186208 # mshr miss rate for overall accesses 2278system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average ReadReq mshr miss latency 2279system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average ReadReq mshr miss latency 2280system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 31037.609644 # average ReadReq mshr miss latency 2281system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35918.637723 # average HardPFReq mshr miss latency 2282system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35918.637723 # average HardPFReq mshr miss latency 2283system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20808.816504 # average UpgradeReq mshr miss latency 2284system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20808.816504 # average UpgradeReq mshr miss latency 2285system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 16224.436051 # average SCUpgradeReq mshr miss latency 2286system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 16224.436051 # average SCUpgradeReq mshr miss latency 2287system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 500874.750000 # average SCUpgradeFailReq mshr miss latency 2288system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 500874.750000 # average SCUpgradeFailReq mshr miss latency 2289system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32120.644676 # average ReadExReq mshr miss latency 2290system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32120.644676 # average ReadExReq mshr miss latency 2291system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average ReadCleanReq mshr miss latency 2292system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 26735.574243 # average ReadCleanReq mshr miss latency 2293system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 26815.018004 # average ReadSharedReq mshr miss latency 2294system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26815.018004 # average ReadSharedReq mshr miss latency 2295system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26186.131086 # average InvalidateReq mshr miss latency 2296system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26186.131086 # average InvalidateReq mshr miss latency 2297system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average overall mshr miss latency 2298system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average overall mshr miss latency 2299system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average overall mshr miss latency 2300system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27963.862446 # average overall mshr miss latency 2301system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27558.035864 # average overall mshr miss latency 2302system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30625.213311 # average overall mshr miss latency 2303system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31593.991021 # average overall mshr miss latency 2304system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26735.574243 # average overall mshr miss latency 2305system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27963.862446 # average overall mshr miss latency 2306system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35918.637723 # average overall mshr miss latency 2307system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29846.821834 # average overall mshr miss latency 2308system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82860.215054 # average ReadReq mshr uncacheable latency 2309system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112606.396773 # average ReadReq mshr uncacheable latency 2310system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 112213.107762 # average ReadReq mshr uncacheable latency 2311system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82860.215054 # average overall mshr uncacheable latency 2312system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 54961.043527 # average overall mshr uncacheable latency 2313system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 55142.308230 # average overall mshr uncacheable latency 2314system.cpu1.toL2Bus.snoop_filter.tot_requests 27911552 # Total number of requests made to the snoop filter. 2315system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14263179 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2316system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1909 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2317system.cpu1.toL2Bus.snoop_filter.tot_snoops 2035614 # Total number of snoops made to the snoop filter. 2318system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2035313 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2319system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 301 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2320system.cpu1.toL2Bus.trans_dist::ReadReq 755700 # Transaction distribution 2321system.cpu1.toL2Bus.trans_dist::ReadResp 13030335 # Transaction distribution 2322system.cpu1.toL2Bus.trans_dist::WriteReq 7280 # Transaction distribution 2323system.cpu1.toL2Bus.trans_dist::WriteResp 7280 # Transaction distribution 2324system.cpu1.toL2Bus.trans_dist::WritebackDirty 4134671 # Transaction distribution 2325system.cpu1.toL2Bus.trans_dist::WritebackClean 10529340 # Transaction distribution 2326system.cpu1.toL2Bus.trans_dist::CleanEvict 2783515 # Transaction distribution 2327system.cpu1.toL2Bus.trans_dist::HardPFReq 903944 # Transaction distribution 2328system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution 2329system.cpu1.toL2Bus.trans_dist::UpgradeReq 426493 # Transaction distribution 2330system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 348519 # Transaction distribution 2331system.cpu1.toL2Bus.trans_dist::UpgradeResp 477830 # Transaction distribution 2332system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 70 # Transaction distribution 2333system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution 2334system.cpu1.toL2Bus.trans_dist::ReadExReq 1080105 # Transaction distribution 2335system.cpu1.toL2Bus.trans_dist::ReadExResp 1057121 # Transaction distribution 2336system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8745479 # Transaction distribution 2337system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4495606 # Transaction distribution 2338system.cpu1.toL2Bus.trans_dist::InvalidateReq 466229 # Transaction distribution 2339system.cpu1.toL2Bus.trans_dist::InvalidateResp 413447 # Transaction distribution 2340system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26236111 # Packet count per connected master and slave (bytes) 2341system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15633953 # Packet count per connected master and slave (bytes) 2342system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 355051 # Packet count per connected master and slave (bytes) 2343system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1069038 # Packet count per connected master and slave (bytes) 2344system.cpu1.toL2Bus.pkt_count::total 43294153 # Packet count per connected master and slave (bytes) 2345system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1119394496 # Cumulative packet size per connected master and slave (bytes) 2346system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 601463021 # Cumulative packet size per connected master and slave (bytes) 2347system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1354416 # Cumulative packet size per connected master and slave (bytes) 2348system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4048968 # Cumulative packet size per connected master and slave (bytes) 2349system.cpu1.toL2Bus.pkt_size::total 1726260901 # Cumulative packet size per connected master and slave (bytes) 2350system.cpu1.toL2Bus.snoops 6529606 # Total snoops (count) 2351system.cpu1.toL2Bus.snoop_fanout::samples 21121122 # Request fanout histogram 2352system.cpu1.toL2Bus.snoop_fanout::mean 0.110367 # Request fanout histogram 2353system.cpu1.toL2Bus.snoop_fanout::stdev 0.313393 # Request fanout histogram |
| 2340system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 2354system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 2341system.cpu1.toL2Bus.snoop_fanout::0 18907277 88.72% 88.72% # Request fanout histogram 2342system.cpu1.toL2Bus.snoop_fanout::1 2404354 11.28% 100.00% # Request fanout histogram 2343system.cpu1.toL2Bus.snoop_fanout::2 342 0.00% 100.00% # Request fanout histogram | 2355system.cpu1.toL2Bus.snoop_fanout::0 18790338 88.96% 88.96% # Request fanout histogram 2356system.cpu1.toL2Bus.snoop_fanout::1 2330483 11.03% 100.00% # Request fanout histogram 2357system.cpu1.toL2Bus.snoop_fanout::2 301 0.00% 100.00% # Request fanout histogram |
| 2344system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2345system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2346system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 2358system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2359system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2360system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 2347system.cpu1.toL2Bus.snoop_fanout::total 21311973 # Request fanout histogram 2348system.cpu1.toL2Bus.reqLayer0.occupancy 27584218481 # Layer occupancy (ticks) | 2361system.cpu1.toL2Bus.snoop_fanout::total 21121122 # Request fanout histogram 2362system.cpu1.toL2Bus.reqLayer0.occupancy 27750114484 # Layer occupancy (ticks) |
| 2349system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 2363system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 2350system.cpu1.toL2Bus.snoopLayer0.occupancy 185839513 # Layer occupancy (ticks) | 2364system.cpu1.toL2Bus.snoopLayer0.occupancy 177306545 # Layer occupancy (ticks) |
| 2351system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2365system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2352system.cpu1.toL2Bus.respLayer0.occupancy 12678955503 # Layer occupancy (ticks) | 2366system.cpu1.toL2Bus.respLayer0.occupancy 13121677843 # Layer occupancy (ticks) |
| 2353system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 2367system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2354system.cpu1.toL2Bus.respLayer1.occupancy 7484332893 # Layer occupancy (ticks) | 2368system.cpu1.toL2Bus.respLayer1.occupancy 7163335235 # Layer occupancy (ticks) |
| 2355system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 2369system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 2356system.cpu1.toL2Bus.respLayer2.occupancy 194250357 # Layer occupancy (ticks) | 2370system.cpu1.toL2Bus.respLayer2.occupancy 185802393 # Layer occupancy (ticks) |
| 2357system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 2371system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2358system.cpu1.toL2Bus.respLayer3.occupancy 577391819 # Layer occupancy (ticks) | 2372system.cpu1.toL2Bus.respLayer3.occupancy 563017795 # Layer occupancy (ticks) |
| 2359system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2373system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2360system.iobus.trans_dist::ReadReq 40390 # Transaction distribution 2361system.iobus.trans_dist::ReadResp 40390 # Transaction distribution 2362system.iobus.trans_dist::WriteReq 136973 # Transaction distribution 2363system.iobus.trans_dist::WriteResp 136973 # Transaction distribution 2364system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes) | 2374system.iobus.trans_dist::ReadReq 40337 # Transaction distribution 2375system.iobus.trans_dist::ReadResp 40337 # Transaction distribution 2376system.iobus.trans_dist::WriteReq 136616 # Transaction distribution 2377system.iobus.trans_dist::WriteResp 136616 # Transaction distribution 2378system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47664 # Packet count per connected master and slave (bytes) |
| 2365system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2366system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2367system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2368system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2369system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2370system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2371system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2372system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2373system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2374system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) | 2379system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2380system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2381system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2382system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2383system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2384system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2385system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2386system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2387system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2388system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) |
| 2375system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes) | 2389system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) |
| 2376system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) | 2390system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) |
| 2377system.iobus.pkt_count_system.bridge.master::total 122924 # Packet count per connected master and slave (bytes) 2378system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231722 # Packet count per connected master and slave (bytes) 2379system.iobus.pkt_count_system.realview.ide.dma::total 231722 # Packet count per connected master and slave (bytes) | 2391system.iobus.pkt_count_system.bridge.master::total 122598 # Packet count per connected master and slave (bytes) 2392system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231228 # Packet count per connected master and slave (bytes) 2393system.iobus.pkt_count_system.realview.ide.dma::total 231228 # Packet count per connected master and slave (bytes) |
| 2380system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2381system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) | 2394system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2395system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) |
| 2382system.iobus.pkt_count::total 354726 # Packet count per connected master and slave (bytes) 2383system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes) | 2396system.iobus.pkt_count::total 353906 # Packet count per connected master and slave (bytes) 2397system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47684 # Cumulative packet size per connected master and slave (bytes) |
| 2384system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2385system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 2386system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2387system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2388system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2389system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2390system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2391system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2392system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2393system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) | 2398system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2399system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 2400system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2401system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2402system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2403system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2404system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2405system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2406system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2407system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) |
| 2394system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17703 # Cumulative packet size per connected master and slave (bytes) | 2408system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) |
| 2395system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) | 2409system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) |
| 2396system.iobus.pkt_size_system.bridge.master::total 155939 # Cumulative packet size per connected master and slave (bytes) 2397system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355240 # Cumulative packet size per connected master and slave (bytes) 2398system.iobus.pkt_size_system.realview.ide.dma::total 7355240 # Cumulative packet size per connected master and slave (bytes) | 2410system.iobus.pkt_size_system.bridge.master::total 155705 # Cumulative packet size per connected master and slave (bytes) 2411system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338928 # Cumulative packet size per connected master and slave (bytes) 2412system.iobus.pkt_size_system.realview.ide.dma::total 7338928 # Cumulative packet size per connected master and slave (bytes) |
| 2399system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2400system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) | 2413system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2414system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) |
| 2401system.iobus.pkt_size::total 7513265 # Cumulative packet size per connected master and slave (bytes) 2402system.iobus.reqLayer0.occupancy 42523001 # Layer occupancy (ticks) | 2415system.iobus.pkt_size::total 7496719 # Cumulative packet size per connected master and slave (bytes) 2416system.iobus.reqLayer0.occupancy 43180502 # Layer occupancy (ticks) |
| 2403system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2404system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) 2405system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) | 2417system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2418system.iobus.reqLayer1.occupancy 11000 # Layer occupancy (ticks) 2419system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 2406system.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks) | 2420system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) |
| 2407system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) | 2421system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 2408system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) | 2422system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) |
| 2409system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) | 2423system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) |
| 2410system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) | 2424system.iobus.reqLayer4.occupancy 10000 # Layer occupancy (ticks) |
| 2411system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) | 2425system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) |
| 2412system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) | 2426system.iobus.reqLayer10.occupancy 9000 # Layer occupancy (ticks) |
| 2413system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) | 2427system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) |
| 2414system.iobus.reqLayer13.occupancy 10500 # Layer occupancy (ticks) | 2428system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) |
| 2415system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) | 2429system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) |
| 2416system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) | 2430system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) |
| 2417system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) | 2431system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) |
| 2418system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) | 2432system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) |
| 2419system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) | 2433system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) |
| 2420system.iobus.reqLayer16.occupancy 16500 # Layer occupancy (ticks) | 2434system.iobus.reqLayer16.occupancy 15500 # Layer occupancy (ticks) |
| 2421system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) | 2435system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) |
| 2422system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) | 2436system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) |
| 2423system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) | 2437system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) |
| 2424system.iobus.reqLayer23.occupancy 25802501 # Layer occupancy (ticks) | 2438system.iobus.reqLayer23.occupancy 25595502 # Layer occupancy (ticks) |
| 2425system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) | 2439system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) |
| 2426system.iobus.reqLayer24.occupancy 36398001 # Layer occupancy (ticks) | 2440system.iobus.reqLayer24.occupancy 36402501 # Layer occupancy (ticks) |
| 2427system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) | 2441system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) |
| 2428system.iobus.reqLayer25.occupancy 568577386 # Layer occupancy (ticks) | 2442system.iobus.reqLayer25.occupancy 569469754 # Layer occupancy (ticks) |
| 2429system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) | 2443system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) |
| 2430system.iobus.respLayer0.occupancy 92938000 # Layer occupancy (ticks) | 2444system.iobus.respLayer0.occupancy 92713000 # Layer occupancy (ticks) |
| 2431system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 2445system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2432system.iobus.respLayer3.occupancy 148162000 # Layer occupancy (ticks) | 2446system.iobus.respLayer3.occupancy 147924000 # Layer occupancy (ticks) |
| 2433system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2434system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2435system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) | 2447system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2448system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2449system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) |
| 2436system.iocache.tags.replacements 115843 # number of replacements 2437system.iocache.tags.tagsinuse 11.310828 # Cycle average of tags in use | 2450system.iocache.tags.replacements 115611 # number of replacements 2451system.iocache.tags.tagsinuse 11.284790 # Cycle average of tags in use |
| 2438system.iocache.tags.total_refs 3 # Total number of references to valid blocks. | 2452system.iocache.tags.total_refs 3 # Total number of references to valid blocks. |
| 2439system.iocache.tags.sampled_refs 115859 # Sample count of references to valid blocks. | 2453system.iocache.tags.sampled_refs 115627 # Sample count of references to valid blocks. |
| 2440system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. | 2454system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. |
| 2441system.iocache.tags.warmup_cycle 9138959017000 # Cycle when the warmup percentage was hit. 2442system.iocache.tags.occ_blocks::realview.ethernet 3.826637 # Average occupied blocks per requestor 2443system.iocache.tags.occ_blocks::realview.ide 7.484190 # Average occupied blocks per requestor 2444system.iocache.tags.occ_percent::realview.ethernet 0.239165 # Average percentage of cache occupancy 2445system.iocache.tags.occ_percent::realview.ide 0.467762 # Average percentage of cache occupancy 2446system.iocache.tags.occ_percent::total 0.706927 # Average percentage of cache occupancy | 2455system.iocache.tags.warmup_cycle 9167417766000 # Cycle when the warmup percentage was hit. 2456system.iocache.tags.occ_blocks::realview.ethernet 7.418888 # Average occupied blocks per requestor 2457system.iocache.tags.occ_blocks::realview.ide 3.865902 # Average occupied blocks per requestor 2458system.iocache.tags.occ_percent::realview.ethernet 0.463681 # Average percentage of cache occupancy 2459system.iocache.tags.occ_percent::realview.ide 0.241619 # Average percentage of cache occupancy 2460system.iocache.tags.occ_percent::total 0.705299 # Average percentage of cache occupancy |
| 2447system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2448system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2449system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 2461system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2462system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2463system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 2450system.iocache.tags.tag_accesses 1043106 # Number of tag accesses 2451system.iocache.tags.data_accesses 1043106 # Number of data accesses | 2464system.iocache.tags.tag_accesses 1040883 # Number of tag accesses 2465system.iocache.tags.data_accesses 1040883 # Number of data accesses |
| 2452system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses | 2466system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses |
| 2453system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses 2454system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses | 2467system.iocache.ReadReq_misses::realview.ide 8886 # number of ReadReq misses 2468system.iocache.ReadReq_misses::total 8923 # number of ReadReq misses |
| 2455system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2456system.iocache.WriteReq_misses::total 3 # number of WriteReq misses | 2469system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2470system.iocache.WriteReq_misses::total 3 # number of WriteReq misses |
| 2457system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses 2458system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses | 2471system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 2472system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses |
| 2459system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses | 2473system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses |
| 2460system.iocache.demand_misses::realview.ide 115861 # number of demand (read+write) misses 2461system.iocache.demand_misses::total 115901 # number of demand (read+write) misses | 2474system.iocache.demand_misses::realview.ide 115614 # number of demand (read+write) misses 2475system.iocache.demand_misses::total 115654 # number of demand (read+write) misses |
| 2462system.iocache.overall_misses::realview.ethernet 40 # number of overall misses | 2476system.iocache.overall_misses::realview.ethernet 40 # number of overall misses |
| 2463system.iocache.overall_misses::realview.ide 115861 # number of overall misses 2464system.iocache.overall_misses::total 115901 # number of overall misses 2465system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles 2466system.iocache.ReadReq_miss_latency::realview.ide 1651659585 # number of ReadReq miss cycles 2467system.iocache.ReadReq_miss_latency::total 1656859085 # number of ReadReq miss cycles | 2477system.iocache.overall_misses::realview.ide 115614 # number of overall misses 2478system.iocache.overall_misses::total 115654 # number of overall misses 2479system.iocache.ReadReq_miss_latency::realview.ethernet 5198000 # number of ReadReq miss cycles 2480system.iocache.ReadReq_miss_latency::realview.ide 1668794518 # number of ReadReq miss cycles 2481system.iocache.ReadReq_miss_latency::total 1673992518 # number of ReadReq miss cycles |
| 2468system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2469system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles | 2482system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2483system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles |
| 2470system.iocache.WriteLineReq_miss_latency::realview.ide 13563940301 # number of WriteLineReq miss cycles 2471system.iocache.WriteLineReq_miss_latency::total 13563940301 # number of WriteLineReq miss cycles 2472system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles 2473system.iocache.demand_miss_latency::realview.ide 15215599886 # number of demand (read+write) miss cycles 2474system.iocache.demand_miss_latency::total 15221168386 # number of demand (read+write) miss cycles 2475system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles 2476system.iocache.overall_miss_latency::realview.ide 15215599886 # number of overall miss cycles 2477system.iocache.overall_miss_latency::total 15221168386 # number of overall miss cycles | 2484system.iocache.WriteLineReq_miss_latency::realview.ide 12857701236 # number of WriteLineReq miss cycles 2485system.iocache.WriteLineReq_miss_latency::total 12857701236 # number of WriteLineReq miss cycles 2486system.iocache.demand_miss_latency::realview.ethernet 5567000 # number of demand (read+write) miss cycles 2487system.iocache.demand_miss_latency::realview.ide 14526495754 # number of demand (read+write) miss cycles 2488system.iocache.demand_miss_latency::total 14532062754 # number of demand (read+write) miss cycles 2489system.iocache.overall_miss_latency::realview.ethernet 5567000 # number of overall miss cycles 2490system.iocache.overall_miss_latency::realview.ide 14526495754 # number of overall miss cycles 2491system.iocache.overall_miss_latency::total 14532062754 # number of overall miss cycles |
| 2478system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) | 2492system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) |
| 2479system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses) 2480system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses) | 2493system.iocache.ReadReq_accesses::realview.ide 8886 # number of ReadReq accesses(hits+misses) 2494system.iocache.ReadReq_accesses::total 8923 # number of ReadReq accesses(hits+misses) |
| 2481system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2482system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) | 2495system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2496system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) |
| 2483system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) 2484system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) | 2497system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 2498system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) |
| 2485system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses | 2499system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses |
| 2486system.iocache.demand_accesses::realview.ide 115861 # number of demand (read+write) accesses 2487system.iocache.demand_accesses::total 115901 # number of demand (read+write) accesses | 2500system.iocache.demand_accesses::realview.ide 115614 # number of demand (read+write) accesses 2501system.iocache.demand_accesses::total 115654 # number of demand (read+write) accesses |
| 2488system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses | 2502system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses |
| 2489system.iocache.overall_accesses::realview.ide 115861 # number of overall (read+write) accesses 2490system.iocache.overall_accesses::total 115901 # number of overall (read+write) accesses | 2503system.iocache.overall_accesses::realview.ide 115614 # number of overall (read+write) accesses 2504system.iocache.overall_accesses::total 115654 # number of overall (read+write) accesses |
| 2491system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2492system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2493system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2494system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2495system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2496system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2497system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2498system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2499system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2500system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2501system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2502system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2503system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 2505system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2506system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2507system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2508system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2509system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2510system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2511system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2512system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2513system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2514system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2515system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2516system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2517system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 2504system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency 2505system.iocache.ReadReq_avg_miss_latency::realview.ide 186060.559311 # average ReadReq miss latency 2506system.iocache.ReadReq_avg_miss_latency::total 185871.559906 # average ReadReq miss latency | 2518system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140486.486486 # average ReadReq miss latency 2519system.iocache.ReadReq_avg_miss_latency::realview.ide 187800.418411 # average ReadReq miss latency 2520system.iocache.ReadReq_avg_miss_latency::total 187604.227054 # average ReadReq miss latency |
| 2507system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2508system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency | 2521system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2522system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency |
| 2509system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126784.755674 # average WriteLineReq miss latency 2510system.iocache.WriteLineReq_avg_miss_latency::total 126784.755674 # average WriteLineReq miss latency 2511system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency 2512system.iocache.demand_avg_miss_latency::realview.ide 131326.329705 # average overall miss latency 2513system.iocache.demand_avg_miss_latency::total 131329.051397 # average overall miss latency 2514system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency 2515system.iocache.overall_avg_miss_latency::realview.ide 131326.329705 # average overall miss latency 2516system.iocache.overall_avg_miss_latency::total 131329.051397 # average overall miss latency 2517system.iocache.blocked_cycles::no_mshrs 32764 # number of cycles access was blocked | 2523system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120471.677873 # average WriteLineReq miss latency 2524system.iocache.WriteLineReq_avg_miss_latency::total 120471.677873 # average WriteLineReq miss latency 2525system.iocache.demand_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 2526system.iocache.demand_avg_miss_latency::realview.ide 125646.511270 # average overall miss latency 2527system.iocache.demand_avg_miss_latency::total 125651.190223 # average overall miss latency 2528system.iocache.overall_avg_miss_latency::realview.ethernet 139175 # average overall miss latency 2529system.iocache.overall_avg_miss_latency::realview.ide 125646.511270 # average overall miss latency 2530system.iocache.overall_avg_miss_latency::total 125651.190223 # average overall miss latency 2531system.iocache.blocked_cycles::no_mshrs 33480 # number of cycles access was blocked |
| 2518system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2532system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2519system.iocache.blocked::no_mshrs 3385 # number of cycles access was blocked | 2533system.iocache.blocked::no_mshrs 3531 # number of cycles access was blocked |
| 2520system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 2534system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 2521system.iocache.avg_blocked_cycles::no_mshrs 9.679173 # average number of cycles each access was blocked | 2535system.iocache.avg_blocked_cycles::no_mshrs 9.481733 # average number of cycles each access was blocked |
| 2522system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2536system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2523system.iocache.writebacks::writebacks 106951 # number of writebacks 2524system.iocache.writebacks::total 106951 # number of writebacks | 2537system.iocache.writebacks::writebacks 106695 # number of writebacks 2538system.iocache.writebacks::total 106695 # number of writebacks |
| 2525system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses | 2539system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses |
| 2526system.iocache.ReadReq_mshr_misses::realview.ide 8877 # number of ReadReq MSHR misses 2527system.iocache.ReadReq_mshr_misses::total 8914 # number of ReadReq MSHR misses | 2540system.iocache.ReadReq_mshr_misses::realview.ide 8886 # number of ReadReq MSHR misses 2541system.iocache.ReadReq_mshr_misses::total 8923 # number of ReadReq MSHR misses |
| 2528system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2529system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses | 2542system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2543system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses |
| 2530system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses 2531system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses | 2544system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 2545system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses |
| 2532system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses | 2546system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses |
| 2533system.iocache.demand_mshr_misses::realview.ide 115861 # number of demand (read+write) MSHR misses 2534system.iocache.demand_mshr_misses::total 115901 # number of demand (read+write) MSHR misses | 2547system.iocache.demand_mshr_misses::realview.ide 115614 # number of demand (read+write) MSHR misses 2548system.iocache.demand_mshr_misses::total 115654 # number of demand (read+write) MSHR misses |
| 2535system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses | 2549system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses |
| 2536system.iocache.overall_mshr_misses::realview.ide 115861 # number of overall MSHR misses 2537system.iocache.overall_mshr_misses::total 115901 # number of overall MSHR misses 2538system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles 2539system.iocache.ReadReq_mshr_miss_latency::realview.ide 1207809585 # number of ReadReq MSHR miss cycles 2540system.iocache.ReadReq_mshr_miss_latency::total 1211159085 # number of ReadReq MSHR miss cycles | 2550system.iocache.overall_mshr_misses::realview.ide 115614 # number of overall MSHR misses 2551system.iocache.overall_mshr_misses::total 115654 # number of overall MSHR misses 2552system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3348000 # number of ReadReq MSHR miss cycles 2553system.iocache.ReadReq_mshr_miss_latency::realview.ide 1224494518 # number of ReadReq MSHR miss cycles 2554system.iocache.ReadReq_mshr_miss_latency::total 1227842518 # number of ReadReq MSHR miss cycles |
| 2541system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2542system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles | 2555system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2556system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles |
| 2543system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8208491858 # number of WriteLineReq MSHR miss cycles 2544system.iocache.WriteLineReq_mshr_miss_latency::total 8208491858 # number of WriteLineReq MSHR miss cycles 2545system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles 2546system.iocache.demand_mshr_miss_latency::realview.ide 9416301443 # number of demand (read+write) MSHR miss cycles 2547system.iocache.demand_mshr_miss_latency::total 9419869943 # number of demand (read+write) MSHR miss cycles 2548system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles 2549system.iocache.overall_mshr_miss_latency::realview.ide 9416301443 # number of overall MSHR miss cycles 2550system.iocache.overall_mshr_miss_latency::total 9419869943 # number of overall MSHR miss cycles | 2557system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7512769435 # number of WriteLineReq MSHR miss cycles 2558system.iocache.WriteLineReq_mshr_miss_latency::total 7512769435 # number of WriteLineReq MSHR miss cycles 2559system.iocache.demand_mshr_miss_latency::realview.ethernet 3567000 # number of demand (read+write) MSHR miss cycles 2560system.iocache.demand_mshr_miss_latency::realview.ide 8737263953 # number of demand (read+write) MSHR miss cycles 2561system.iocache.demand_mshr_miss_latency::total 8740830953 # number of demand (read+write) MSHR miss cycles 2562system.iocache.overall_mshr_miss_latency::realview.ethernet 3567000 # number of overall MSHR miss cycles 2563system.iocache.overall_mshr_miss_latency::realview.ide 8737263953 # number of overall MSHR miss cycles 2564system.iocache.overall_mshr_miss_latency::total 8740830953 # number of overall MSHR miss cycles |
| 2551system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2552system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2553system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2554system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2555system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2556system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2557system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2558system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2559system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2560system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2561system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2562system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2563system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 2565system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2566system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2567system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2568system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2569system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2570system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2571system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2572system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2573system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2574system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2575system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2576system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2577system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 2564system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency 2565system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136060.559311 # average ReadReq mshr miss latency 2566system.iocache.ReadReq_avg_mshr_miss_latency::total 135871.559906 # average ReadReq mshr miss latency | 2578system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90486.486486 # average ReadReq mshr miss latency 2579system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 137800.418411 # average ReadReq mshr miss latency 2580system.iocache.ReadReq_avg_mshr_miss_latency::total 137604.227054 # average ReadReq mshr miss latency |
| 2567system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2568system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency | 2581system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2582system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency |
| 2569system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76726.350277 # average WriteLineReq mshr miss latency 2570system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76726.350277 # average WriteLineReq mshr miss latency 2571system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 2572system.iocache.demand_avg_mshr_miss_latency::realview.ide 81272.399194 # average overall mshr miss latency 2573system.iocache.demand_avg_mshr_miss_latency::total 81275.139498 # average overall mshr miss latency 2574system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency 2575system.iocache.overall_avg_mshr_miss_latency::realview.ide 81272.399194 # average overall mshr miss latency 2576system.iocache.overall_avg_mshr_miss_latency::total 81275.139498 # average overall mshr miss latency 2577system.l2c.tags.replacements 1387428 # number of replacements 2578system.l2c.tags.tagsinuse 63551.257518 # Cycle average of tags in use 2579system.l2c.tags.total_refs 6641936 # Total number of references to valid blocks. 2580system.l2c.tags.sampled_refs 1448331 # Sample count of references to valid blocks. 2581system.l2c.tags.avg_refs 4.585924 # Average number of references to valid blocks. 2582system.l2c.tags.warmup_cycle 13283135500 # Cycle when the warmup percentage was hit. 2583system.l2c.tags.occ_blocks::writebacks 22018.288167 # Average occupied blocks per requestor 2584system.l2c.tags.occ_blocks::cpu0.dtb.walker 94.707462 # Average occupied blocks per requestor 2585system.l2c.tags.occ_blocks::cpu0.itb.walker 112.653017 # Average occupied blocks per requestor 2586system.l2c.tags.occ_blocks::cpu0.inst 5422.209579 # Average occupied blocks per requestor 2587system.l2c.tags.occ_blocks::cpu0.data 6394.892392 # Average occupied blocks per requestor 2588system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 5645.972820 # Average occupied blocks per requestor 2589system.l2c.tags.occ_blocks::cpu1.dtb.walker 238.578829 # Average occupied blocks per requestor 2590system.l2c.tags.occ_blocks::cpu1.itb.walker 322.014833 # Average occupied blocks per requestor 2591system.l2c.tags.occ_blocks::cpu1.inst 3724.645789 # Average occupied blocks per requestor 2592system.l2c.tags.occ_blocks::cpu1.data 6574.117531 # Average occupied blocks per requestor 2593system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13003.177099 # Average occupied blocks per requestor 2594system.l2c.tags.occ_percent::writebacks 0.335972 # Average percentage of cache occupancy 2595system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001445 # Average percentage of cache occupancy 2596system.l2c.tags.occ_percent::cpu0.itb.walker 0.001719 # Average percentage of cache occupancy 2597system.l2c.tags.occ_percent::cpu0.inst 0.082736 # Average percentage of cache occupancy 2598system.l2c.tags.occ_percent::cpu0.data 0.097578 # Average percentage of cache occupancy 2599system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.086151 # Average percentage of cache occupancy 2600system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003640 # Average percentage of cache occupancy 2601system.l2c.tags.occ_percent::cpu1.itb.walker 0.004914 # Average percentage of cache occupancy 2602system.l2c.tags.occ_percent::cpu1.inst 0.056834 # Average percentage of cache occupancy 2603system.l2c.tags.occ_percent::cpu1.data 0.100313 # Average percentage of cache occupancy 2604system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.198413 # Average percentage of cache occupancy 2605system.l2c.tags.occ_percent::total 0.969715 # Average percentage of cache occupancy 2606system.l2c.tags.occ_task_id_blocks::1022 10329 # Occupied blocks per task id 2607system.l2c.tags.occ_task_id_blocks::1023 221 # Occupied blocks per task id 2608system.l2c.tags.occ_task_id_blocks::1024 50353 # Occupied blocks per task id 2609system.l2c.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id 2610system.l2c.tags.age_task_id_blocks_1022::2 518 # Occupied blocks per task id 2611system.l2c.tags.age_task_id_blocks_1022::3 2097 # Occupied blocks per task id 2612system.l2c.tags.age_task_id_blocks_1022::4 7705 # Occupied blocks per task id 2613system.l2c.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id 2614system.l2c.tags.age_task_id_blocks_1023::4 212 # Occupied blocks per task id 2615system.l2c.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id 2616system.l2c.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id 2617system.l2c.tags.age_task_id_blocks_1024::2 2461 # Occupied blocks per task id 2618system.l2c.tags.age_task_id_blocks_1024::3 13754 # Occupied blocks per task id 2619system.l2c.tags.age_task_id_blocks_1024::4 33762 # Occupied blocks per task id 2620system.l2c.tags.occ_task_id_percent::1022 0.157608 # Percentage of cache occupancy per task id 2621system.l2c.tags.occ_task_id_percent::1023 0.003372 # Percentage of cache occupancy per task id 2622system.l2c.tags.occ_task_id_percent::1024 0.768326 # Percentage of cache occupancy per task id 2623system.l2c.tags.tag_accesses 81054625 # Number of tag accesses 2624system.l2c.tags.data_accesses 81054625 # Number of data accesses 2625system.l2c.WritebackDirty_hits::writebacks 2804232 # number of WritebackDirty hits 2626system.l2c.WritebackDirty_hits::total 2804232 # number of WritebackDirty hits 2627system.l2c.UpgradeReq_hits::cpu0.data 166858 # number of UpgradeReq hits 2628system.l2c.UpgradeReq_hits::cpu1.data 141079 # number of UpgradeReq hits 2629system.l2c.UpgradeReq_hits::total 307937 # number of UpgradeReq hits 2630system.l2c.SCUpgradeReq_hits::cpu0.data 43211 # number of SCUpgradeReq hits 2631system.l2c.SCUpgradeReq_hits::cpu1.data 40746 # number of SCUpgradeReq hits 2632system.l2c.SCUpgradeReq_hits::total 83957 # number of SCUpgradeReq hits 2633system.l2c.ReadExReq_hits::cpu0.data 52655 # number of ReadExReq hits 2634system.l2c.ReadExReq_hits::cpu1.data 61293 # number of ReadExReq hits 2635system.l2c.ReadExReq_hits::total 113948 # number of ReadExReq hits 2636system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6392 # number of ReadSharedReq hits 2637system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4086 # number of ReadSharedReq hits 2638system.l2c.ReadSharedReq_hits::cpu0.inst 674086 # number of ReadSharedReq hits 2639system.l2c.ReadSharedReq_hits::cpu0.data 617640 # number of ReadSharedReq hits 2640system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 331682 # number of ReadSharedReq hits 2641system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 7229 # number of ReadSharedReq hits 2642system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5312 # number of ReadSharedReq hits 2643system.l2c.ReadSharedReq_hits::cpu1.inst 633543 # number of ReadSharedReq hits 2644system.l2c.ReadSharedReq_hits::cpu1.data 593468 # number of ReadSharedReq hits 2645system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 330392 # number of ReadSharedReq hits 2646system.l2c.ReadSharedReq_hits::total 3203830 # number of ReadSharedReq hits 2647system.l2c.InvalidateReq_hits::cpu0.data 133432 # number of InvalidateReq hits 2648system.l2c.InvalidateReq_hits::cpu1.data 138176 # number of InvalidateReq hits 2649system.l2c.InvalidateReq_hits::total 271608 # number of InvalidateReq hits 2650system.l2c.demand_hits::cpu0.dtb.walker 6392 # number of demand (read+write) hits 2651system.l2c.demand_hits::cpu0.itb.walker 4086 # number of demand (read+write) hits 2652system.l2c.demand_hits::cpu0.inst 674086 # number of demand (read+write) hits 2653system.l2c.demand_hits::cpu0.data 670295 # number of demand (read+write) hits 2654system.l2c.demand_hits::cpu0.l2cache.prefetcher 331682 # number of demand (read+write) hits 2655system.l2c.demand_hits::cpu1.dtb.walker 7229 # number of demand (read+write) hits 2656system.l2c.demand_hits::cpu1.itb.walker 5312 # number of demand (read+write) hits 2657system.l2c.demand_hits::cpu1.inst 633543 # number of demand (read+write) hits 2658system.l2c.demand_hits::cpu1.data 654761 # number of demand (read+write) hits 2659system.l2c.demand_hits::cpu1.l2cache.prefetcher 330392 # number of demand (read+write) hits 2660system.l2c.demand_hits::total 3317778 # number of demand (read+write) hits 2661system.l2c.overall_hits::cpu0.dtb.walker 6392 # number of overall hits 2662system.l2c.overall_hits::cpu0.itb.walker 4086 # number of overall hits 2663system.l2c.overall_hits::cpu0.inst 674086 # number of overall hits 2664system.l2c.overall_hits::cpu0.data 670295 # number of overall hits 2665system.l2c.overall_hits::cpu0.l2cache.prefetcher 331682 # number of overall hits 2666system.l2c.overall_hits::cpu1.dtb.walker 7229 # number of overall hits 2667system.l2c.overall_hits::cpu1.itb.walker 5312 # number of overall hits 2668system.l2c.overall_hits::cpu1.inst 633543 # number of overall hits 2669system.l2c.overall_hits::cpu1.data 654761 # number of overall hits 2670system.l2c.overall_hits::cpu1.l2cache.prefetcher 330392 # number of overall hits 2671system.l2c.overall_hits::total 3317778 # number of overall hits 2672system.l2c.UpgradeReq_misses::cpu0.data 63565 # number of UpgradeReq misses 2673system.l2c.UpgradeReq_misses::cpu1.data 62220 # number of UpgradeReq misses 2674system.l2c.UpgradeReq_misses::total 125785 # number of UpgradeReq misses 2675system.l2c.SCUpgradeReq_misses::cpu0.data 13487 # number of SCUpgradeReq misses 2676system.l2c.SCUpgradeReq_misses::cpu1.data 11849 # number of SCUpgradeReq misses 2677system.l2c.SCUpgradeReq_misses::total 25336 # number of SCUpgradeReq misses 2678system.l2c.ReadExReq_misses::cpu0.data 80559 # number of ReadExReq misses 2679system.l2c.ReadExReq_misses::cpu1.data 50978 # number of ReadExReq misses 2680system.l2c.ReadExReq_misses::total 131537 # number of ReadExReq misses 2681system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 1546 # number of ReadSharedReq misses 2682system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1402 # number of ReadSharedReq misses 2683system.l2c.ReadSharedReq_misses::cpu0.inst 75397 # number of ReadSharedReq misses 2684system.l2c.ReadSharedReq_misses::cpu0.data 144871 # number of ReadSharedReq misses 2685system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 231057 # number of ReadSharedReq misses 2686system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2351 # number of ReadSharedReq misses 2687system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1996 # number of ReadSharedReq misses 2688system.l2c.ReadSharedReq_misses::cpu1.inst 47759 # number of ReadSharedReq misses 2689system.l2c.ReadSharedReq_misses::cpu1.data 100866 # number of ReadSharedReq misses 2690system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 195589 # number of ReadSharedReq misses 2691system.l2c.ReadSharedReq_misses::total 802834 # number of ReadSharedReq misses 2692system.l2c.InvalidateReq_misses::cpu0.data 470568 # number of InvalidateReq misses 2693system.l2c.InvalidateReq_misses::cpu1.data 95260 # number of InvalidateReq misses 2694system.l2c.InvalidateReq_misses::total 565828 # number of InvalidateReq misses 2695system.l2c.demand_misses::cpu0.dtb.walker 1546 # number of demand (read+write) misses 2696system.l2c.demand_misses::cpu0.itb.walker 1402 # number of demand (read+write) misses 2697system.l2c.demand_misses::cpu0.inst 75397 # number of demand (read+write) misses 2698system.l2c.demand_misses::cpu0.data 225430 # number of demand (read+write) misses 2699system.l2c.demand_misses::cpu0.l2cache.prefetcher 231057 # number of demand (read+write) misses 2700system.l2c.demand_misses::cpu1.dtb.walker 2351 # number of demand (read+write) misses 2701system.l2c.demand_misses::cpu1.itb.walker 1996 # number of demand (read+write) misses 2702system.l2c.demand_misses::cpu1.inst 47759 # number of demand (read+write) misses 2703system.l2c.demand_misses::cpu1.data 151844 # number of demand (read+write) misses 2704system.l2c.demand_misses::cpu1.l2cache.prefetcher 195589 # number of demand (read+write) misses 2705system.l2c.demand_misses::total 934371 # number of demand (read+write) misses 2706system.l2c.overall_misses::cpu0.dtb.walker 1546 # number of overall misses 2707system.l2c.overall_misses::cpu0.itb.walker 1402 # number of overall misses 2708system.l2c.overall_misses::cpu0.inst 75397 # number of overall misses 2709system.l2c.overall_misses::cpu0.data 225430 # number of overall misses 2710system.l2c.overall_misses::cpu0.l2cache.prefetcher 231057 # number of overall misses 2711system.l2c.overall_misses::cpu1.dtb.walker 2351 # number of overall misses 2712system.l2c.overall_misses::cpu1.itb.walker 1996 # number of overall misses 2713system.l2c.overall_misses::cpu1.inst 47759 # number of overall misses 2714system.l2c.overall_misses::cpu1.data 151844 # number of overall misses 2715system.l2c.overall_misses::cpu1.l2cache.prefetcher 195589 # number of overall misses 2716system.l2c.overall_misses::total 934371 # number of overall misses 2717system.l2c.UpgradeReq_miss_latency::cpu0.data 1159828500 # number of UpgradeReq miss cycles 2718system.l2c.UpgradeReq_miss_latency::cpu1.data 1086354500 # number of UpgradeReq miss cycles 2719system.l2c.UpgradeReq_miss_latency::total 2246183000 # number of UpgradeReq miss cycles 2720system.l2c.SCUpgradeReq_miss_latency::cpu0.data 232119500 # number of SCUpgradeReq miss cycles 2721system.l2c.SCUpgradeReq_miss_latency::cpu1.data 209371000 # number of SCUpgradeReq miss cycles 2722system.l2c.SCUpgradeReq_miss_latency::total 441490500 # number of SCUpgradeReq miss cycles 2723system.l2c.ReadExReq_miss_latency::cpu0.data 11149968000 # number of ReadExReq miss cycles 2724system.l2c.ReadExReq_miss_latency::cpu1.data 6797489000 # number of ReadExReq miss cycles 2725system.l2c.ReadExReq_miss_latency::total 17947457000 # number of ReadExReq miss cycles 2726system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 218104500 # number of ReadSharedReq miss cycles 2727system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 197814500 # number of ReadSharedReq miss cycles 2728system.l2c.ReadSharedReq_miss_latency::cpu0.inst 10138484000 # number of ReadSharedReq miss cycles 2729system.l2c.ReadSharedReq_miss_latency::cpu0.data 20222355000 # number of ReadSharedReq miss cycles 2730system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 40382282755 # number of ReadSharedReq miss cycles 2731system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 328460500 # number of ReadSharedReq miss cycles 2732system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 280819500 # number of ReadSharedReq miss cycles 2733system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6431697000 # number of ReadSharedReq miss cycles 2734system.l2c.ReadSharedReq_miss_latency::cpu1.data 14230471500 # number of ReadSharedReq miss cycles 2735system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 32826320681 # number of ReadSharedReq miss cycles 2736system.l2c.ReadSharedReq_miss_latency::total 125256809936 # number of ReadSharedReq miss cycles 2737system.l2c.InvalidateReq_miss_latency::cpu0.data 174062000 # number of InvalidateReq miss cycles 2738system.l2c.InvalidateReq_miss_latency::cpu1.data 150333500 # number of InvalidateReq miss cycles 2739system.l2c.InvalidateReq_miss_latency::total 324395500 # number of InvalidateReq miss cycles 2740system.l2c.demand_miss_latency::cpu0.dtb.walker 218104500 # number of demand (read+write) miss cycles 2741system.l2c.demand_miss_latency::cpu0.itb.walker 197814500 # number of demand (read+write) miss cycles 2742system.l2c.demand_miss_latency::cpu0.inst 10138484000 # number of demand (read+write) miss cycles 2743system.l2c.demand_miss_latency::cpu0.data 31372323000 # number of demand (read+write) miss cycles 2744system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 40382282755 # number of demand (read+write) miss cycles 2745system.l2c.demand_miss_latency::cpu1.dtb.walker 328460500 # number of demand (read+write) miss cycles 2746system.l2c.demand_miss_latency::cpu1.itb.walker 280819500 # number of demand (read+write) miss cycles 2747system.l2c.demand_miss_latency::cpu1.inst 6431697000 # number of demand (read+write) miss cycles 2748system.l2c.demand_miss_latency::cpu1.data 21027960500 # number of demand (read+write) miss cycles 2749system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 32826320681 # number of demand (read+write) miss cycles 2750system.l2c.demand_miss_latency::total 143204266936 # number of demand (read+write) miss cycles 2751system.l2c.overall_miss_latency::cpu0.dtb.walker 218104500 # number of overall miss cycles 2752system.l2c.overall_miss_latency::cpu0.itb.walker 197814500 # number of overall miss cycles 2753system.l2c.overall_miss_latency::cpu0.inst 10138484000 # number of overall miss cycles 2754system.l2c.overall_miss_latency::cpu0.data 31372323000 # number of overall miss cycles 2755system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 40382282755 # number of overall miss cycles 2756system.l2c.overall_miss_latency::cpu1.dtb.walker 328460500 # number of overall miss cycles 2757system.l2c.overall_miss_latency::cpu1.itb.walker 280819500 # number of overall miss cycles 2758system.l2c.overall_miss_latency::cpu1.inst 6431697000 # number of overall miss cycles 2759system.l2c.overall_miss_latency::cpu1.data 21027960500 # number of overall miss cycles 2760system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 32826320681 # number of overall miss cycles 2761system.l2c.overall_miss_latency::total 143204266936 # number of overall miss cycles 2762system.l2c.WritebackDirty_accesses::writebacks 2804232 # number of WritebackDirty accesses(hits+misses) 2763system.l2c.WritebackDirty_accesses::total 2804232 # number of WritebackDirty accesses(hits+misses) 2764system.l2c.UpgradeReq_accesses::cpu0.data 230423 # number of UpgradeReq accesses(hits+misses) 2765system.l2c.UpgradeReq_accesses::cpu1.data 203299 # number of UpgradeReq accesses(hits+misses) 2766system.l2c.UpgradeReq_accesses::total 433722 # number of UpgradeReq accesses(hits+misses) 2767system.l2c.SCUpgradeReq_accesses::cpu0.data 56698 # number of SCUpgradeReq accesses(hits+misses) 2768system.l2c.SCUpgradeReq_accesses::cpu1.data 52595 # number of SCUpgradeReq accesses(hits+misses) 2769system.l2c.SCUpgradeReq_accesses::total 109293 # number of SCUpgradeReq accesses(hits+misses) 2770system.l2c.ReadExReq_accesses::cpu0.data 133214 # number of ReadExReq accesses(hits+misses) 2771system.l2c.ReadExReq_accesses::cpu1.data 112271 # number of ReadExReq accesses(hits+misses) 2772system.l2c.ReadExReq_accesses::total 245485 # number of ReadExReq accesses(hits+misses) 2773system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7938 # number of ReadSharedReq accesses(hits+misses) 2774system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5488 # number of ReadSharedReq accesses(hits+misses) 2775system.l2c.ReadSharedReq_accesses::cpu0.inst 749483 # number of ReadSharedReq accesses(hits+misses) 2776system.l2c.ReadSharedReq_accesses::cpu0.data 762511 # number of ReadSharedReq accesses(hits+misses) 2777system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 562739 # number of ReadSharedReq accesses(hits+misses) 2778system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9580 # number of ReadSharedReq accesses(hits+misses) 2779system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7308 # number of ReadSharedReq accesses(hits+misses) 2780system.l2c.ReadSharedReq_accesses::cpu1.inst 681302 # number of ReadSharedReq accesses(hits+misses) 2781system.l2c.ReadSharedReq_accesses::cpu1.data 694334 # number of ReadSharedReq accesses(hits+misses) 2782system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 525981 # number of ReadSharedReq accesses(hits+misses) 2783system.l2c.ReadSharedReq_accesses::total 4006664 # number of ReadSharedReq accesses(hits+misses) 2784system.l2c.InvalidateReq_accesses::cpu0.data 604000 # number of InvalidateReq accesses(hits+misses) 2785system.l2c.InvalidateReq_accesses::cpu1.data 233436 # number of InvalidateReq accesses(hits+misses) 2786system.l2c.InvalidateReq_accesses::total 837436 # number of InvalidateReq accesses(hits+misses) 2787system.l2c.demand_accesses::cpu0.dtb.walker 7938 # number of demand (read+write) accesses 2788system.l2c.demand_accesses::cpu0.itb.walker 5488 # number of demand (read+write) accesses 2789system.l2c.demand_accesses::cpu0.inst 749483 # number of demand (read+write) accesses 2790system.l2c.demand_accesses::cpu0.data 895725 # number of demand (read+write) accesses 2791system.l2c.demand_accesses::cpu0.l2cache.prefetcher 562739 # number of demand (read+write) accesses 2792system.l2c.demand_accesses::cpu1.dtb.walker 9580 # number of demand (read+write) accesses 2793system.l2c.demand_accesses::cpu1.itb.walker 7308 # number of demand (read+write) accesses 2794system.l2c.demand_accesses::cpu1.inst 681302 # number of demand (read+write) accesses 2795system.l2c.demand_accesses::cpu1.data 806605 # number of demand (read+write) accesses 2796system.l2c.demand_accesses::cpu1.l2cache.prefetcher 525981 # number of demand (read+write) accesses 2797system.l2c.demand_accesses::total 4252149 # number of demand (read+write) accesses 2798system.l2c.overall_accesses::cpu0.dtb.walker 7938 # number of overall (read+write) accesses 2799system.l2c.overall_accesses::cpu0.itb.walker 5488 # number of overall (read+write) accesses 2800system.l2c.overall_accesses::cpu0.inst 749483 # number of overall (read+write) accesses 2801system.l2c.overall_accesses::cpu0.data 895725 # number of overall (read+write) accesses 2802system.l2c.overall_accesses::cpu0.l2cache.prefetcher 562739 # number of overall (read+write) accesses 2803system.l2c.overall_accesses::cpu1.dtb.walker 9580 # number of overall (read+write) accesses 2804system.l2c.overall_accesses::cpu1.itb.walker 7308 # number of overall (read+write) accesses 2805system.l2c.overall_accesses::cpu1.inst 681302 # number of overall (read+write) accesses 2806system.l2c.overall_accesses::cpu1.data 806605 # number of overall (read+write) accesses 2807system.l2c.overall_accesses::cpu1.l2cache.prefetcher 525981 # number of overall (read+write) accesses 2808system.l2c.overall_accesses::total 4252149 # number of overall (read+write) accesses 2809system.l2c.UpgradeReq_miss_rate::cpu0.data 0.275862 # miss rate for UpgradeReq accesses 2810system.l2c.UpgradeReq_miss_rate::cpu1.data 0.306052 # miss rate for UpgradeReq accesses 2811system.l2c.UpgradeReq_miss_rate::total 0.290013 # miss rate for UpgradeReq accesses 2812system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.237874 # miss rate for SCUpgradeReq accesses 2813system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.225288 # miss rate for SCUpgradeReq accesses 2814system.l2c.SCUpgradeReq_miss_rate::total 0.231817 # miss rate for SCUpgradeReq accesses 2815system.l2c.ReadExReq_miss_rate::cpu0.data 0.604734 # miss rate for ReadExReq accesses 2816system.l2c.ReadExReq_miss_rate::cpu1.data 0.454062 # miss rate for ReadExReq accesses 2817system.l2c.ReadExReq_miss_rate::total 0.535825 # miss rate for ReadExReq accesses 2818system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.194759 # miss rate for ReadSharedReq accesses 2819system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.255466 # miss rate for ReadSharedReq accesses 2820system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.100599 # miss rate for ReadSharedReq accesses 2821system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.189992 # miss rate for ReadSharedReq accesses 2822system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.410594 # miss rate for ReadSharedReq accesses 2823system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.245407 # miss rate for ReadSharedReq accesses 2824system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.273125 # miss rate for ReadSharedReq accesses 2825system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.070100 # miss rate for ReadSharedReq accesses 2826system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.145270 # miss rate for ReadSharedReq accesses 2827system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.371856 # miss rate for ReadSharedReq accesses 2828system.l2c.ReadSharedReq_miss_rate::total 0.200375 # miss rate for ReadSharedReq accesses 2829system.l2c.InvalidateReq_miss_rate::cpu0.data 0.779086 # miss rate for InvalidateReq accesses 2830system.l2c.InvalidateReq_miss_rate::cpu1.data 0.408078 # miss rate for InvalidateReq accesses 2831system.l2c.InvalidateReq_miss_rate::total 0.675667 # miss rate for InvalidateReq accesses 2832system.l2c.demand_miss_rate::cpu0.dtb.walker 0.194759 # miss rate for demand accesses 2833system.l2c.demand_miss_rate::cpu0.itb.walker 0.255466 # miss rate for demand accesses 2834system.l2c.demand_miss_rate::cpu0.inst 0.100599 # miss rate for demand accesses 2835system.l2c.demand_miss_rate::cpu0.data 0.251673 # miss rate for demand accesses 2836system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.410594 # miss rate for demand accesses 2837system.l2c.demand_miss_rate::cpu1.dtb.walker 0.245407 # miss rate for demand accesses 2838system.l2c.demand_miss_rate::cpu1.itb.walker 0.273125 # miss rate for demand accesses 2839system.l2c.demand_miss_rate::cpu1.inst 0.070100 # miss rate for demand accesses 2840system.l2c.demand_miss_rate::cpu1.data 0.188251 # miss rate for demand accesses 2841system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.371856 # miss rate for demand accesses 2842system.l2c.demand_miss_rate::total 0.219741 # miss rate for demand accesses 2843system.l2c.overall_miss_rate::cpu0.dtb.walker 0.194759 # miss rate for overall accesses 2844system.l2c.overall_miss_rate::cpu0.itb.walker 0.255466 # miss rate for overall accesses 2845system.l2c.overall_miss_rate::cpu0.inst 0.100599 # miss rate for overall accesses 2846system.l2c.overall_miss_rate::cpu0.data 0.251673 # miss rate for overall accesses 2847system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.410594 # miss rate for overall accesses 2848system.l2c.overall_miss_rate::cpu1.dtb.walker 0.245407 # miss rate for overall accesses 2849system.l2c.overall_miss_rate::cpu1.itb.walker 0.273125 # miss rate for overall accesses 2850system.l2c.overall_miss_rate::cpu1.inst 0.070100 # miss rate for overall accesses 2851system.l2c.overall_miss_rate::cpu1.data 0.188251 # miss rate for overall accesses 2852system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.371856 # miss rate for overall accesses 2853system.l2c.overall_miss_rate::total 0.219741 # miss rate for overall accesses 2854system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 18246.338394 # average UpgradeReq miss latency 2855system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17459.892318 # average UpgradeReq miss latency 2856system.l2c.UpgradeReq_avg_miss_latency::total 17857.320030 # average UpgradeReq miss latency 2857system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 17210.610217 # average SCUpgradeReq miss latency 2858system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17669.929952 # average SCUpgradeReq miss latency 2859system.l2c.SCUpgradeReq_avg_miss_latency::total 17425.422324 # average SCUpgradeReq miss latency 2860system.l2c.ReadExReq_avg_miss_latency::cpu0.data 138407.477749 # average ReadExReq miss latency 2861system.l2c.ReadExReq_avg_miss_latency::cpu1.data 133341.617953 # average ReadExReq miss latency 2862system.l2c.ReadExReq_avg_miss_latency::total 136444.171602 # average ReadExReq miss latency 2863system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 141076.649418 # average ReadSharedReq miss latency 2864system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141094.507846 # average ReadSharedReq miss latency 2865system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 134468.002706 # average ReadSharedReq miss latency 2866system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 139588.703053 # average ReadSharedReq miss latency 2867system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 174771.951315 # average ReadSharedReq miss latency 2868system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 139710.974054 # average ReadSharedReq miss latency 2869system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 140691.132265 # average ReadSharedReq miss latency 2870system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 134669.842333 # average ReadSharedReq miss latency 2871system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 141082.936768 # average ReadSharedReq miss latency 2872system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 167833.163833 # average ReadSharedReq miss latency 2873system.l2c.ReadSharedReq_avg_miss_latency::total 156018.317530 # average ReadSharedReq miss latency 2874system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 369.897656 # average InvalidateReq miss latency 2875system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 1578.138778 # average InvalidateReq miss latency 2876system.l2c.InvalidateReq_avg_miss_latency::total 573.311148 # average InvalidateReq miss latency 2877system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 141076.649418 # average overall miss latency 2878system.l2c.demand_avg_miss_latency::cpu0.itb.walker 141094.507846 # average overall miss latency 2879system.l2c.demand_avg_miss_latency::cpu0.inst 134468.002706 # average overall miss latency 2880system.l2c.demand_avg_miss_latency::cpu0.data 139166.583862 # average overall miss latency 2881system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 174771.951315 # average overall miss latency 2882system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 139710.974054 # average overall miss latency 2883system.l2c.demand_avg_miss_latency::cpu1.itb.walker 140691.132265 # average overall miss latency 2884system.l2c.demand_avg_miss_latency::cpu1.inst 134669.842333 # average overall miss latency 2885system.l2c.demand_avg_miss_latency::cpu1.data 138483.973684 # average overall miss latency 2886system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 167833.163833 # average overall miss latency 2887system.l2c.demand_avg_miss_latency::total 153262.747812 # average overall miss latency 2888system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 141076.649418 # average overall miss latency 2889system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141094.507846 # average overall miss latency 2890system.l2c.overall_avg_miss_latency::cpu0.inst 134468.002706 # average overall miss latency 2891system.l2c.overall_avg_miss_latency::cpu0.data 139166.583862 # average overall miss latency 2892system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 174771.951315 # average overall miss latency 2893system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 139710.974054 # average overall miss latency 2894system.l2c.overall_avg_miss_latency::cpu1.itb.walker 140691.132265 # average overall miss latency 2895system.l2c.overall_avg_miss_latency::cpu1.inst 134669.842333 # average overall miss latency 2896system.l2c.overall_avg_miss_latency::cpu1.data 138483.973684 # average overall miss latency 2897system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 167833.163833 # average overall miss latency 2898system.l2c.overall_avg_miss_latency::total 153262.747812 # average overall miss latency 2899system.l2c.blocked_cycles::no_mshrs 971 # number of cycles access was blocked | 2583system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70391.738204 # average WriteLineReq mshr miss latency 2584system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70391.738204 # average WriteLineReq mshr miss latency 2585system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 2586system.iocache.demand_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency 2587system.iocache.demand_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency 2588system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89175 # average overall mshr miss latency 2589system.iocache.overall_avg_mshr_miss_latency::realview.ide 75572.715701 # average overall mshr miss latency 2590system.iocache.overall_avg_mshr_miss_latency::total 75577.420176 # average overall mshr miss latency 2591system.l2c.tags.replacements 1371243 # number of replacements 2592system.l2c.tags.tagsinuse 63411.869664 # Cycle average of tags in use 2593system.l2c.tags.total_refs 6460055 # Total number of references to valid blocks. 2594system.l2c.tags.sampled_refs 1430877 # Sample count of references to valid blocks. 2595system.l2c.tags.avg_refs 4.514752 # Average number of references to valid blocks. 2596system.l2c.tags.warmup_cycle 7876910500 # Cycle when the warmup percentage was hit. 2597system.l2c.tags.occ_blocks::writebacks 21329.379338 # Average occupied blocks per requestor 2598system.l2c.tags.occ_blocks::cpu0.dtb.walker 243.549056 # Average occupied blocks per requestor 2599system.l2c.tags.occ_blocks::cpu0.itb.walker 346.213430 # Average occupied blocks per requestor 2600system.l2c.tags.occ_blocks::cpu0.inst 5332.164924 # Average occupied blocks per requestor 2601system.l2c.tags.occ_blocks::cpu0.data 9972.711960 # Average occupied blocks per requestor 2602system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14780.287325 # Average occupied blocks per requestor 2603system.l2c.tags.occ_blocks::cpu1.dtb.walker 85.709675 # Average occupied blocks per requestor 2604system.l2c.tags.occ_blocks::cpu1.itb.walker 92.474711 # Average occupied blocks per requestor 2605system.l2c.tags.occ_blocks::cpu1.inst 3611.694384 # Average occupied blocks per requestor 2606system.l2c.tags.occ_blocks::cpu1.data 3808.494767 # Average occupied blocks per requestor 2607system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3809.190093 # Average occupied blocks per requestor 2608system.l2c.tags.occ_percent::writebacks 0.325461 # Average percentage of cache occupancy 2609system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003716 # Average percentage of cache occupancy 2610system.l2c.tags.occ_percent::cpu0.itb.walker 0.005283 # Average percentage of cache occupancy 2611system.l2c.tags.occ_percent::cpu0.inst 0.081362 # Average percentage of cache occupancy 2612system.l2c.tags.occ_percent::cpu0.data 0.152172 # Average percentage of cache occupancy 2613system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.225529 # Average percentage of cache occupancy 2614system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001308 # Average percentage of cache occupancy 2615system.l2c.tags.occ_percent::cpu1.itb.walker 0.001411 # Average percentage of cache occupancy 2616system.l2c.tags.occ_percent::cpu1.inst 0.055110 # Average percentage of cache occupancy 2617system.l2c.tags.occ_percent::cpu1.data 0.058113 # Average percentage of cache occupancy 2618system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.058124 # Average percentage of cache occupancy 2619system.l2c.tags.occ_percent::total 0.967588 # Average percentage of cache occupancy 2620system.l2c.tags.occ_task_id_blocks::1022 9222 # Occupied blocks per task id 2621system.l2c.tags.occ_task_id_blocks::1023 255 # Occupied blocks per task id 2622system.l2c.tags.occ_task_id_blocks::1024 50157 # Occupied blocks per task id 2623system.l2c.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 2624system.l2c.tags.age_task_id_blocks_1022::2 98 # Occupied blocks per task id 2625system.l2c.tags.age_task_id_blocks_1022::3 408 # Occupied blocks per task id 2626system.l2c.tags.age_task_id_blocks_1022::4 8708 # Occupied blocks per task id 2627system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 2628system.l2c.tags.age_task_id_blocks_1023::4 254 # Occupied blocks per task id 2629system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 2630system.l2c.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id 2631system.l2c.tags.age_task_id_blocks_1024::2 1961 # Occupied blocks per task id 2632system.l2c.tags.age_task_id_blocks_1024::3 5894 # Occupied blocks per task id 2633system.l2c.tags.age_task_id_blocks_1024::4 42105 # Occupied blocks per task id 2634system.l2c.tags.occ_task_id_percent::1022 0.140717 # Percentage of cache occupancy per task id 2635system.l2c.tags.occ_task_id_percent::1023 0.003891 # Percentage of cache occupancy per task id 2636system.l2c.tags.occ_task_id_percent::1024 0.765335 # Percentage of cache occupancy per task id 2637system.l2c.tags.tag_accesses 79235647 # Number of tag accesses 2638system.l2c.tags.data_accesses 79235647 # Number of data accesses 2639system.l2c.WritebackDirty_hits::writebacks 2747527 # number of WritebackDirty hits 2640system.l2c.WritebackDirty_hits::total 2747527 # number of WritebackDirty hits 2641system.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 2642system.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits 2643system.l2c.UpgradeReq_hits::cpu0.data 170119 # number of UpgradeReq hits 2644system.l2c.UpgradeReq_hits::cpu1.data 132427 # number of UpgradeReq hits 2645system.l2c.UpgradeReq_hits::total 302546 # number of UpgradeReq hits 2646system.l2c.SCUpgradeReq_hits::cpu0.data 41747 # number of SCUpgradeReq hits 2647system.l2c.SCUpgradeReq_hits::cpu1.data 38038 # number of SCUpgradeReq hits 2648system.l2c.SCUpgradeReq_hits::total 79785 # number of SCUpgradeReq hits 2649system.l2c.ReadExReq_hits::cpu0.data 52086 # number of ReadExReq hits 2650system.l2c.ReadExReq_hits::cpu1.data 59057 # number of ReadExReq hits 2651system.l2c.ReadExReq_hits::total 111143 # number of ReadExReq hits 2652system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6348 # number of ReadSharedReq hits 2653system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3788 # number of ReadSharedReq hits 2654system.l2c.ReadSharedReq_hits::cpu0.inst 658119 # number of ReadSharedReq hits 2655system.l2c.ReadSharedReq_hits::cpu0.data 620329 # number of ReadSharedReq hits 2656system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 316694 # number of ReadSharedReq hits 2657system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6918 # number of ReadSharedReq hits 2658system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5196 # number of ReadSharedReq hits 2659system.l2c.ReadSharedReq_hits::cpu1.inst 620556 # number of ReadSharedReq hits 2660system.l2c.ReadSharedReq_hits::cpu1.data 563518 # number of ReadSharedReq hits 2661system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 312616 # number of ReadSharedReq hits 2662system.l2c.ReadSharedReq_hits::total 3114082 # number of ReadSharedReq hits 2663system.l2c.InvalidateReq_hits::cpu0.data 130339 # number of InvalidateReq hits 2664system.l2c.InvalidateReq_hits::cpu1.data 134354 # number of InvalidateReq hits 2665system.l2c.InvalidateReq_hits::total 264693 # number of InvalidateReq hits 2666system.l2c.demand_hits::cpu0.dtb.walker 6348 # number of demand (read+write) hits 2667system.l2c.demand_hits::cpu0.itb.walker 3788 # number of demand (read+write) hits 2668system.l2c.demand_hits::cpu0.inst 658119 # number of demand (read+write) hits 2669system.l2c.demand_hits::cpu0.data 672415 # number of demand (read+write) hits 2670system.l2c.demand_hits::cpu0.l2cache.prefetcher 316694 # number of demand (read+write) hits 2671system.l2c.demand_hits::cpu1.dtb.walker 6918 # number of demand (read+write) hits 2672system.l2c.demand_hits::cpu1.itb.walker 5196 # number of demand (read+write) hits 2673system.l2c.demand_hits::cpu1.inst 620556 # number of demand (read+write) hits 2674system.l2c.demand_hits::cpu1.data 622575 # number of demand (read+write) hits 2675system.l2c.demand_hits::cpu1.l2cache.prefetcher 312616 # number of demand (read+write) hits 2676system.l2c.demand_hits::total 3225225 # number of demand (read+write) hits 2677system.l2c.overall_hits::cpu0.dtb.walker 6348 # number of overall hits 2678system.l2c.overall_hits::cpu0.itb.walker 3788 # number of overall hits 2679system.l2c.overall_hits::cpu0.inst 658119 # number of overall hits 2680system.l2c.overall_hits::cpu0.data 672415 # number of overall hits 2681system.l2c.overall_hits::cpu0.l2cache.prefetcher 316694 # number of overall hits 2682system.l2c.overall_hits::cpu1.dtb.walker 6918 # number of overall hits 2683system.l2c.overall_hits::cpu1.itb.walker 5196 # number of overall hits 2684system.l2c.overall_hits::cpu1.inst 620556 # number of overall hits 2685system.l2c.overall_hits::cpu1.data 622575 # number of overall hits 2686system.l2c.overall_hits::cpu1.l2cache.prefetcher 312616 # number of overall hits 2687system.l2c.overall_hits::total 3225225 # number of overall hits 2688system.l2c.UpgradeReq_misses::cpu0.data 63896 # number of UpgradeReq misses 2689system.l2c.UpgradeReq_misses::cpu1.data 60301 # number of UpgradeReq misses 2690system.l2c.UpgradeReq_misses::total 124197 # number of UpgradeReq misses 2691system.l2c.SCUpgradeReq_misses::cpu0.data 12467 # number of SCUpgradeReq misses 2692system.l2c.SCUpgradeReq_misses::cpu1.data 11210 # number of SCUpgradeReq misses 2693system.l2c.SCUpgradeReq_misses::total 23677 # number of SCUpgradeReq misses 2694system.l2c.ReadExReq_misses::cpu0.data 80795 # number of ReadExReq misses 2695system.l2c.ReadExReq_misses::cpu1.data 51109 # number of ReadExReq misses 2696system.l2c.ReadExReq_misses::total 131904 # number of ReadExReq misses 2697system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2056 # number of ReadSharedReq misses 2698system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1934 # number of ReadSharedReq misses 2699system.l2c.ReadSharedReq_misses::cpu0.inst 66055 # number of ReadSharedReq misses 2700system.l2c.ReadSharedReq_misses::cpu0.data 143274 # number of ReadSharedReq misses 2701system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 256484 # number of ReadSharedReq misses 2702system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1908 # number of ReadSharedReq misses 2703system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1578 # number of ReadSharedReq misses 2704system.l2c.ReadSharedReq_misses::cpu1.inst 52043 # number of ReadSharedReq misses 2705system.l2c.ReadSharedReq_misses::cpu1.data 103878 # number of ReadSharedReq misses 2706system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 163476 # number of ReadSharedReq misses 2707system.l2c.ReadSharedReq_misses::total 792686 # number of ReadSharedReq misses 2708system.l2c.InvalidateReq_misses::cpu0.data 465421 # number of InvalidateReq misses 2709system.l2c.InvalidateReq_misses::cpu1.data 95414 # number of InvalidateReq misses 2710system.l2c.InvalidateReq_misses::total 560835 # number of InvalidateReq misses 2711system.l2c.demand_misses::cpu0.dtb.walker 2056 # number of demand (read+write) misses 2712system.l2c.demand_misses::cpu0.itb.walker 1934 # number of demand (read+write) misses 2713system.l2c.demand_misses::cpu0.inst 66055 # number of demand (read+write) misses 2714system.l2c.demand_misses::cpu0.data 224069 # number of demand (read+write) misses 2715system.l2c.demand_misses::cpu0.l2cache.prefetcher 256484 # number of demand (read+write) misses 2716system.l2c.demand_misses::cpu1.dtb.walker 1908 # number of demand (read+write) misses 2717system.l2c.demand_misses::cpu1.itb.walker 1578 # number of demand (read+write) misses 2718system.l2c.demand_misses::cpu1.inst 52043 # number of demand (read+write) misses 2719system.l2c.demand_misses::cpu1.data 154987 # number of demand (read+write) misses 2720system.l2c.demand_misses::cpu1.l2cache.prefetcher 163476 # number of demand (read+write) misses 2721system.l2c.demand_misses::total 924590 # number of demand (read+write) misses 2722system.l2c.overall_misses::cpu0.dtb.walker 2056 # number of overall misses 2723system.l2c.overall_misses::cpu0.itb.walker 1934 # number of overall misses 2724system.l2c.overall_misses::cpu0.inst 66055 # number of overall misses 2725system.l2c.overall_misses::cpu0.data 224069 # number of overall misses 2726system.l2c.overall_misses::cpu0.l2cache.prefetcher 256484 # number of overall misses 2727system.l2c.overall_misses::cpu1.dtb.walker 1908 # number of overall misses 2728system.l2c.overall_misses::cpu1.itb.walker 1578 # number of overall misses 2729system.l2c.overall_misses::cpu1.inst 52043 # number of overall misses 2730system.l2c.overall_misses::cpu1.data 154987 # number of overall misses 2731system.l2c.overall_misses::cpu1.l2cache.prefetcher 163476 # number of overall misses 2732system.l2c.overall_misses::total 924590 # number of overall misses 2733system.l2c.UpgradeReq_miss_latency::cpu0.data 446027000 # number of UpgradeReq miss cycles 2734system.l2c.UpgradeReq_miss_latency::cpu1.data 423537000 # number of UpgradeReq miss cycles 2735system.l2c.UpgradeReq_miss_latency::total 869564000 # number of UpgradeReq miss cycles 2736system.l2c.SCUpgradeReq_miss_latency::cpu0.data 79642000 # number of SCUpgradeReq miss cycles 2737system.l2c.SCUpgradeReq_miss_latency::cpu1.data 73423000 # number of SCUpgradeReq miss cycles 2738system.l2c.SCUpgradeReq_miss_latency::total 153065000 # number of SCUpgradeReq miss cycles 2739system.l2c.ReadExReq_miss_latency::cpu0.data 7209880999 # number of ReadExReq miss cycles 2740system.l2c.ReadExReq_miss_latency::cpu1.data 4224259500 # number of ReadExReq miss cycles 2741system.l2c.ReadExReq_miss_latency::total 11434140499 # number of ReadExReq miss cycles 2742system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 181168500 # number of ReadSharedReq miss cycles 2743system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 173308500 # number of ReadSharedReq miss cycles 2744system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5614644500 # number of ReadSharedReq miss cycles 2745system.l2c.ReadSharedReq_miss_latency::cpu0.data 12851594000 # number of ReadSharedReq miss cycles 2746system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 32734884574 # number of ReadSharedReq miss cycles 2747system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 174846500 # number of ReadSharedReq miss cycles 2748system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 145724500 # number of ReadSharedReq miss cycles 2749system.l2c.ReadSharedReq_miss_latency::cpu1.inst 4416688500 # number of ReadSharedReq miss cycles 2750system.l2c.ReadSharedReq_miss_latency::cpu1.data 9519600500 # number of ReadSharedReq miss cycles 2751system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 19884865739 # number of ReadSharedReq miss cycles 2752system.l2c.ReadSharedReq_miss_latency::total 85697325813 # number of ReadSharedReq miss cycles 2753system.l2c.InvalidateReq_miss_latency::cpu0.data 65788000 # number of InvalidateReq miss cycles 2754system.l2c.InvalidateReq_miss_latency::cpu1.data 54373000 # number of InvalidateReq miss cycles 2755system.l2c.InvalidateReq_miss_latency::total 120161000 # number of InvalidateReq miss cycles 2756system.l2c.demand_miss_latency::cpu0.dtb.walker 181168500 # number of demand (read+write) miss cycles 2757system.l2c.demand_miss_latency::cpu0.itb.walker 173308500 # number of demand (read+write) miss cycles 2758system.l2c.demand_miss_latency::cpu0.inst 5614644500 # number of demand (read+write) miss cycles 2759system.l2c.demand_miss_latency::cpu0.data 20061474999 # number of demand (read+write) miss cycles 2760system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 32734884574 # number of demand (read+write) miss cycles 2761system.l2c.demand_miss_latency::cpu1.dtb.walker 174846500 # number of demand (read+write) miss cycles 2762system.l2c.demand_miss_latency::cpu1.itb.walker 145724500 # number of demand (read+write) miss cycles 2763system.l2c.demand_miss_latency::cpu1.inst 4416688500 # number of demand (read+write) miss cycles 2764system.l2c.demand_miss_latency::cpu1.data 13743860000 # number of demand (read+write) miss cycles 2765system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 19884865739 # number of demand (read+write) miss cycles 2766system.l2c.demand_miss_latency::total 97131466312 # number of demand (read+write) miss cycles 2767system.l2c.overall_miss_latency::cpu0.dtb.walker 181168500 # number of overall miss cycles 2768system.l2c.overall_miss_latency::cpu0.itb.walker 173308500 # number of overall miss cycles 2769system.l2c.overall_miss_latency::cpu0.inst 5614644500 # number of overall miss cycles 2770system.l2c.overall_miss_latency::cpu0.data 20061474999 # number of overall miss cycles 2771system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 32734884574 # number of overall miss cycles 2772system.l2c.overall_miss_latency::cpu1.dtb.walker 174846500 # number of overall miss cycles 2773system.l2c.overall_miss_latency::cpu1.itb.walker 145724500 # number of overall miss cycles 2774system.l2c.overall_miss_latency::cpu1.inst 4416688500 # number of overall miss cycles 2775system.l2c.overall_miss_latency::cpu1.data 13743860000 # number of overall miss cycles 2776system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 19884865739 # number of overall miss cycles 2777system.l2c.overall_miss_latency::total 97131466312 # number of overall miss cycles 2778system.l2c.WritebackDirty_accesses::writebacks 2747527 # number of WritebackDirty accesses(hits+misses) 2779system.l2c.WritebackDirty_accesses::total 2747527 # number of WritebackDirty accesses(hits+misses) 2780system.l2c.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) 2781system.l2c.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) 2782system.l2c.UpgradeReq_accesses::cpu0.data 234015 # number of UpgradeReq accesses(hits+misses) 2783system.l2c.UpgradeReq_accesses::cpu1.data 192728 # number of UpgradeReq accesses(hits+misses) 2784system.l2c.UpgradeReq_accesses::total 426743 # number of UpgradeReq accesses(hits+misses) 2785system.l2c.SCUpgradeReq_accesses::cpu0.data 54214 # number of SCUpgradeReq accesses(hits+misses) 2786system.l2c.SCUpgradeReq_accesses::cpu1.data 49248 # number of SCUpgradeReq accesses(hits+misses) 2787system.l2c.SCUpgradeReq_accesses::total 103462 # number of SCUpgradeReq accesses(hits+misses) 2788system.l2c.ReadExReq_accesses::cpu0.data 132881 # number of ReadExReq accesses(hits+misses) 2789system.l2c.ReadExReq_accesses::cpu1.data 110166 # number of ReadExReq accesses(hits+misses) 2790system.l2c.ReadExReq_accesses::total 243047 # number of ReadExReq accesses(hits+misses) 2791system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8404 # number of ReadSharedReq accesses(hits+misses) 2792system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5722 # number of ReadSharedReq accesses(hits+misses) 2793system.l2c.ReadSharedReq_accesses::cpu0.inst 724174 # number of ReadSharedReq accesses(hits+misses) 2794system.l2c.ReadSharedReq_accesses::cpu0.data 763603 # number of ReadSharedReq accesses(hits+misses) 2795system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 573178 # number of ReadSharedReq accesses(hits+misses) 2796system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8826 # number of ReadSharedReq accesses(hits+misses) 2797system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6774 # number of ReadSharedReq accesses(hits+misses) 2798system.l2c.ReadSharedReq_accesses::cpu1.inst 672599 # number of ReadSharedReq accesses(hits+misses) 2799system.l2c.ReadSharedReq_accesses::cpu1.data 667396 # number of ReadSharedReq accesses(hits+misses) 2800system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 476092 # number of ReadSharedReq accesses(hits+misses) 2801system.l2c.ReadSharedReq_accesses::total 3906768 # number of ReadSharedReq accesses(hits+misses) 2802system.l2c.InvalidateReq_accesses::cpu0.data 595760 # number of InvalidateReq accesses(hits+misses) 2803system.l2c.InvalidateReq_accesses::cpu1.data 229768 # number of InvalidateReq accesses(hits+misses) 2804system.l2c.InvalidateReq_accesses::total 825528 # number of InvalidateReq accesses(hits+misses) 2805system.l2c.demand_accesses::cpu0.dtb.walker 8404 # number of demand (read+write) accesses 2806system.l2c.demand_accesses::cpu0.itb.walker 5722 # number of demand (read+write) accesses 2807system.l2c.demand_accesses::cpu0.inst 724174 # number of demand (read+write) accesses 2808system.l2c.demand_accesses::cpu0.data 896484 # number of demand (read+write) accesses 2809system.l2c.demand_accesses::cpu0.l2cache.prefetcher 573178 # number of demand (read+write) accesses 2810system.l2c.demand_accesses::cpu1.dtb.walker 8826 # number of demand (read+write) accesses 2811system.l2c.demand_accesses::cpu1.itb.walker 6774 # number of demand (read+write) accesses 2812system.l2c.demand_accesses::cpu1.inst 672599 # number of demand (read+write) accesses 2813system.l2c.demand_accesses::cpu1.data 777562 # number of demand (read+write) accesses 2814system.l2c.demand_accesses::cpu1.l2cache.prefetcher 476092 # number of demand (read+write) accesses 2815system.l2c.demand_accesses::total 4149815 # number of demand (read+write) accesses 2816system.l2c.overall_accesses::cpu0.dtb.walker 8404 # number of overall (read+write) accesses 2817system.l2c.overall_accesses::cpu0.itb.walker 5722 # number of overall (read+write) accesses 2818system.l2c.overall_accesses::cpu0.inst 724174 # number of overall (read+write) accesses 2819system.l2c.overall_accesses::cpu0.data 896484 # number of overall (read+write) accesses 2820system.l2c.overall_accesses::cpu0.l2cache.prefetcher 573178 # number of overall (read+write) accesses 2821system.l2c.overall_accesses::cpu1.dtb.walker 8826 # number of overall (read+write) accesses 2822system.l2c.overall_accesses::cpu1.itb.walker 6774 # number of overall (read+write) accesses 2823system.l2c.overall_accesses::cpu1.inst 672599 # number of overall (read+write) accesses 2824system.l2c.overall_accesses::cpu1.data 777562 # number of overall (read+write) accesses 2825system.l2c.overall_accesses::cpu1.l2cache.prefetcher 476092 # number of overall (read+write) accesses 2826system.l2c.overall_accesses::total 4149815 # number of overall (read+write) accesses 2827system.l2c.UpgradeReq_miss_rate::cpu0.data 0.273042 # miss rate for UpgradeReq accesses 2828system.l2c.UpgradeReq_miss_rate::cpu1.data 0.312881 # miss rate for UpgradeReq accesses 2829system.l2c.UpgradeReq_miss_rate::total 0.291035 # miss rate for UpgradeReq accesses 2830system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.229959 # miss rate for SCUpgradeReq accesses 2831system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.227623 # miss rate for SCUpgradeReq accesses 2832system.l2c.SCUpgradeReq_miss_rate::total 0.228847 # miss rate for SCUpgradeReq accesses 2833system.l2c.ReadExReq_miss_rate::cpu0.data 0.608025 # miss rate for ReadExReq accesses 2834system.l2c.ReadExReq_miss_rate::cpu1.data 0.463927 # miss rate for ReadExReq accesses 2835system.l2c.ReadExReq_miss_rate::total 0.542710 # miss rate for ReadExReq accesses 2836system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.244645 # miss rate for ReadSharedReq accesses 2837system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.337994 # miss rate for ReadSharedReq accesses 2838system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.091214 # miss rate for ReadSharedReq accesses 2839system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.187629 # miss rate for ReadSharedReq accesses 2840system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.447477 # miss rate for ReadSharedReq accesses 2841system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.216179 # miss rate for ReadSharedReq accesses 2842system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.232950 # miss rate for ReadSharedReq accesses 2843system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.077376 # miss rate for ReadSharedReq accesses 2844system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.155647 # miss rate for ReadSharedReq accesses 2845system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.343371 # miss rate for ReadSharedReq accesses 2846system.l2c.ReadSharedReq_miss_rate::total 0.202901 # miss rate for ReadSharedReq accesses 2847system.l2c.InvalidateReq_miss_rate::cpu0.data 0.781222 # miss rate for InvalidateReq accesses 2848system.l2c.InvalidateReq_miss_rate::cpu1.data 0.415262 # miss rate for InvalidateReq accesses 2849system.l2c.InvalidateReq_miss_rate::total 0.679365 # miss rate for InvalidateReq accesses 2850system.l2c.demand_miss_rate::cpu0.dtb.walker 0.244645 # miss rate for demand accesses 2851system.l2c.demand_miss_rate::cpu0.itb.walker 0.337994 # miss rate for demand accesses 2852system.l2c.demand_miss_rate::cpu0.inst 0.091214 # miss rate for demand accesses 2853system.l2c.demand_miss_rate::cpu0.data 0.249942 # miss rate for demand accesses 2854system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.447477 # miss rate for demand accesses 2855system.l2c.demand_miss_rate::cpu1.dtb.walker 0.216179 # miss rate for demand accesses 2856system.l2c.demand_miss_rate::cpu1.itb.walker 0.232950 # miss rate for demand accesses 2857system.l2c.demand_miss_rate::cpu1.inst 0.077376 # miss rate for demand accesses 2858system.l2c.demand_miss_rate::cpu1.data 0.199324 # miss rate for demand accesses 2859system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.343371 # miss rate for demand accesses 2860system.l2c.demand_miss_rate::total 0.222803 # miss rate for demand accesses 2861system.l2c.overall_miss_rate::cpu0.dtb.walker 0.244645 # miss rate for overall accesses 2862system.l2c.overall_miss_rate::cpu0.itb.walker 0.337994 # miss rate for overall accesses 2863system.l2c.overall_miss_rate::cpu0.inst 0.091214 # miss rate for overall accesses 2864system.l2c.overall_miss_rate::cpu0.data 0.249942 # miss rate for overall accesses 2865system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.447477 # miss rate for overall accesses 2866system.l2c.overall_miss_rate::cpu1.dtb.walker 0.216179 # miss rate for overall accesses 2867system.l2c.overall_miss_rate::cpu1.itb.walker 0.232950 # miss rate for overall accesses 2868system.l2c.overall_miss_rate::cpu1.inst 0.077376 # miss rate for overall accesses 2869system.l2c.overall_miss_rate::cpu1.data 0.199324 # miss rate for overall accesses 2870system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.343371 # miss rate for overall accesses 2871system.l2c.overall_miss_rate::total 0.222803 # miss rate for overall accesses 2872system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6980.515212 # average UpgradeReq miss latency 2873system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7023.714366 # average UpgradeReq miss latency 2874system.l2c.UpgradeReq_avg_miss_latency::total 7001.489569 # average UpgradeReq miss latency 2875system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6388.224914 # average SCUpgradeReq miss latency 2876system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6549.776985 # average SCUpgradeReq miss latency 2877system.l2c.SCUpgradeReq_avg_miss_latency::total 6464.712590 # average SCUpgradeReq miss latency 2878system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89236.722557 # average ReadExReq miss latency 2879system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82651.969320 # average ReadExReq miss latency 2880system.l2c.ReadExReq_avg_miss_latency::total 86685.320377 # average ReadExReq miss latency 2881system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 88116.974708 # average ReadSharedReq miss latency 2882system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 89611.427094 # average ReadSharedReq miss latency 2883system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 84999.538264 # average ReadSharedReq miss latency 2884system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 89699.415107 # average ReadSharedReq miss latency 2885system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 127629.343639 # average ReadSharedReq miss latency 2886system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 91638.626834 # average ReadSharedReq miss latency 2887system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 92347.591888 # average ReadSharedReq miss latency 2888system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 84866.139538 # average ReadSharedReq miss latency 2889system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 91642.123453 # average ReadSharedReq miss latency 2890system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 121637.829033 # average ReadSharedReq miss latency 2891system.l2c.ReadSharedReq_avg_miss_latency::total 108110.053430 # average ReadSharedReq miss latency 2892system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 141.351594 # average InvalidateReq miss latency 2893system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 569.863961 # average InvalidateReq miss latency 2894system.l2c.InvalidateReq_avg_miss_latency::total 214.253747 # average InvalidateReq miss latency 2895system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88116.974708 # average overall miss latency 2896system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89611.427094 # average overall miss latency 2897system.l2c.demand_avg_miss_latency::cpu0.inst 84999.538264 # average overall miss latency 2898system.l2c.demand_avg_miss_latency::cpu0.data 89532.577014 # average overall miss latency 2899system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 127629.343639 # average overall miss latency 2900system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 91638.626834 # average overall miss latency 2901system.l2c.demand_avg_miss_latency::cpu1.itb.walker 92347.591888 # average overall miss latency 2902system.l2c.demand_avg_miss_latency::cpu1.inst 84866.139538 # average overall miss latency 2903system.l2c.demand_avg_miss_latency::cpu1.data 88677.501984 # average overall miss latency 2904system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 121637.829033 # average overall miss latency 2905system.l2c.demand_avg_miss_latency::total 105053.554886 # average overall miss latency 2906system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88116.974708 # average overall miss latency 2907system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89611.427094 # average overall miss latency 2908system.l2c.overall_avg_miss_latency::cpu0.inst 84999.538264 # average overall miss latency 2909system.l2c.overall_avg_miss_latency::cpu0.data 89532.577014 # average overall miss latency 2910system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 127629.343639 # average overall miss latency 2911system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 91638.626834 # average overall miss latency 2912system.l2c.overall_avg_miss_latency::cpu1.itb.walker 92347.591888 # average overall miss latency 2913system.l2c.overall_avg_miss_latency::cpu1.inst 84866.139538 # average overall miss latency 2914system.l2c.overall_avg_miss_latency::cpu1.data 88677.501984 # average overall miss latency 2915system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 121637.829033 # average overall miss latency 2916system.l2c.overall_avg_miss_latency::total 105053.554886 # average overall miss latency 2917system.l2c.blocked_cycles::no_mshrs 547 # number of cycles access was blocked |
| 2900system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2918system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2901system.l2c.blocked::no_mshrs 13 # number of cycles access was blocked | 2919system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked |
| 2902system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 2920system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 2903system.l2c.avg_blocked_cycles::no_mshrs 74.692308 # average number of cycles each access was blocked | 2921system.l2c.avg_blocked_cycles::no_mshrs 68.375000 # average number of cycles each access was blocked |
| 2904system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2922system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2905system.l2c.writebacks::writebacks 1075915 # number of writebacks 2906system.l2c.writebacks::total 1075915 # number of writebacks 2907system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 164 # number of ReadSharedReq MSHR hits 2908system.l2c.ReadSharedReq_mshr_hits::cpu0.data 19 # number of ReadSharedReq MSHR hits 2909system.l2c.ReadSharedReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadSharedReq MSHR hits 2910system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 208 # number of ReadSharedReq MSHR hits 2911system.l2c.ReadSharedReq_mshr_hits::cpu1.data 31 # number of ReadSharedReq MSHR hits 2912system.l2c.ReadSharedReq_mshr_hits::total 423 # number of ReadSharedReq MSHR hits 2913system.l2c.demand_mshr_hits::cpu0.inst 164 # number of demand (read+write) MSHR hits 2914system.l2c.demand_mshr_hits::cpu0.data 19 # number of demand (read+write) MSHR hits 2915system.l2c.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 2916system.l2c.demand_mshr_hits::cpu1.inst 208 # number of demand (read+write) MSHR hits 2917system.l2c.demand_mshr_hits::cpu1.data 31 # number of demand (read+write) MSHR hits 2918system.l2c.demand_mshr_hits::total 423 # number of demand (read+write) MSHR hits 2919system.l2c.overall_mshr_hits::cpu0.inst 164 # number of overall MSHR hits 2920system.l2c.overall_mshr_hits::cpu0.data 19 # number of overall MSHR hits 2921system.l2c.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 2922system.l2c.overall_mshr_hits::cpu1.inst 208 # number of overall MSHR hits 2923system.l2c.overall_mshr_hits::cpu1.data 31 # number of overall MSHR hits 2924system.l2c.overall_mshr_hits::total 423 # number of overall MSHR hits 2925system.l2c.CleanEvict_mshr_misses::writebacks 53944 # number of CleanEvict MSHR misses 2926system.l2c.CleanEvict_mshr_misses::total 53944 # number of CleanEvict MSHR misses 2927system.l2c.UpgradeReq_mshr_misses::cpu0.data 63565 # number of UpgradeReq MSHR misses 2928system.l2c.UpgradeReq_mshr_misses::cpu1.data 62220 # number of UpgradeReq MSHR misses 2929system.l2c.UpgradeReq_mshr_misses::total 125785 # number of UpgradeReq MSHR misses 2930system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 13487 # number of SCUpgradeReq MSHR misses 2931system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11849 # number of SCUpgradeReq MSHR misses 2932system.l2c.SCUpgradeReq_mshr_misses::total 25336 # number of SCUpgradeReq MSHR misses 2933system.l2c.ReadExReq_mshr_misses::cpu0.data 80559 # number of ReadExReq MSHR misses 2934system.l2c.ReadExReq_mshr_misses::cpu1.data 50978 # number of ReadExReq MSHR misses 2935system.l2c.ReadExReq_mshr_misses::total 131537 # number of ReadExReq MSHR misses 2936system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 1546 # number of ReadSharedReq MSHR misses 2937system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1402 # number of ReadSharedReq MSHR misses 2938system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 75233 # number of ReadSharedReq MSHR misses 2939system.l2c.ReadSharedReq_mshr_misses::cpu0.data 144852 # number of ReadSharedReq MSHR misses 2940system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 231057 # number of ReadSharedReq MSHR misses 2941system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2350 # number of ReadSharedReq MSHR misses 2942system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1996 # number of ReadSharedReq MSHR misses 2943system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 47551 # number of ReadSharedReq MSHR misses 2944system.l2c.ReadSharedReq_mshr_misses::cpu1.data 100835 # number of ReadSharedReq MSHR misses 2945system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 195589 # number of ReadSharedReq MSHR misses 2946system.l2c.ReadSharedReq_mshr_misses::total 802411 # number of ReadSharedReq MSHR misses 2947system.l2c.InvalidateReq_mshr_misses::cpu0.data 470568 # number of InvalidateReq MSHR misses 2948system.l2c.InvalidateReq_mshr_misses::cpu1.data 95260 # number of InvalidateReq MSHR misses 2949system.l2c.InvalidateReq_mshr_misses::total 565828 # number of InvalidateReq MSHR misses 2950system.l2c.demand_mshr_misses::cpu0.dtb.walker 1546 # number of demand (read+write) MSHR misses 2951system.l2c.demand_mshr_misses::cpu0.itb.walker 1402 # number of demand (read+write) MSHR misses 2952system.l2c.demand_mshr_misses::cpu0.inst 75233 # number of demand (read+write) MSHR misses 2953system.l2c.demand_mshr_misses::cpu0.data 225411 # number of demand (read+write) MSHR misses 2954system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 231057 # number of demand (read+write) MSHR misses 2955system.l2c.demand_mshr_misses::cpu1.dtb.walker 2350 # number of demand (read+write) MSHR misses 2956system.l2c.demand_mshr_misses::cpu1.itb.walker 1996 # number of demand (read+write) MSHR misses 2957system.l2c.demand_mshr_misses::cpu1.inst 47551 # number of demand (read+write) MSHR misses 2958system.l2c.demand_mshr_misses::cpu1.data 151813 # number of demand (read+write) MSHR misses 2959system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 195589 # number of demand (read+write) MSHR misses 2960system.l2c.demand_mshr_misses::total 933948 # number of demand (read+write) MSHR misses 2961system.l2c.overall_mshr_misses::cpu0.dtb.walker 1546 # number of overall MSHR misses 2962system.l2c.overall_mshr_misses::cpu0.itb.walker 1402 # number of overall MSHR misses 2963system.l2c.overall_mshr_misses::cpu0.inst 75233 # number of overall MSHR misses 2964system.l2c.overall_mshr_misses::cpu0.data 225411 # number of overall MSHR misses 2965system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 231057 # number of overall MSHR misses 2966system.l2c.overall_mshr_misses::cpu1.dtb.walker 2350 # number of overall MSHR misses 2967system.l2c.overall_mshr_misses::cpu1.itb.walker 1996 # number of overall MSHR misses 2968system.l2c.overall_mshr_misses::cpu1.inst 47551 # number of overall MSHR misses 2969system.l2c.overall_mshr_misses::cpu1.data 151813 # number of overall MSHR misses 2970system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 195589 # number of overall MSHR misses 2971system.l2c.overall_mshr_misses::total 933948 # number of overall MSHR misses 2972system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52309 # number of ReadReq MSHR uncacheable 2973system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31552 # number of ReadReq MSHR uncacheable | 2923system.l2c.writebacks::writebacks 1075082 # number of writebacks 2924system.l2c.writebacks::total 1075082 # number of writebacks 2925system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 93 # number of ReadSharedReq MSHR hits 2926system.l2c.ReadSharedReq_mshr_hits::cpu0.data 13 # number of ReadSharedReq MSHR hits 2927system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 87 # number of ReadSharedReq MSHR hits 2928system.l2c.ReadSharedReq_mshr_hits::cpu1.data 17 # number of ReadSharedReq MSHR hits 2929system.l2c.ReadSharedReq_mshr_hits::total 210 # number of ReadSharedReq MSHR hits 2930system.l2c.demand_mshr_hits::cpu0.inst 93 # number of demand (read+write) MSHR hits 2931system.l2c.demand_mshr_hits::cpu0.data 13 # number of demand (read+write) MSHR hits 2932system.l2c.demand_mshr_hits::cpu1.inst 87 # number of demand (read+write) MSHR hits 2933system.l2c.demand_mshr_hits::cpu1.data 17 # number of demand (read+write) MSHR hits 2934system.l2c.demand_mshr_hits::total 210 # number of demand (read+write) MSHR hits 2935system.l2c.overall_mshr_hits::cpu0.inst 93 # number of overall MSHR hits 2936system.l2c.overall_mshr_hits::cpu0.data 13 # number of overall MSHR hits 2937system.l2c.overall_mshr_hits::cpu1.inst 87 # number of overall MSHR hits 2938system.l2c.overall_mshr_hits::cpu1.data 17 # number of overall MSHR hits 2939system.l2c.overall_mshr_hits::total 210 # number of overall MSHR hits 2940system.l2c.CleanEvict_mshr_misses::writebacks 54168 # number of CleanEvict MSHR misses 2941system.l2c.CleanEvict_mshr_misses::total 54168 # number of CleanEvict MSHR misses 2942system.l2c.UpgradeReq_mshr_misses::cpu0.data 63896 # number of UpgradeReq MSHR misses 2943system.l2c.UpgradeReq_mshr_misses::cpu1.data 60301 # number of UpgradeReq MSHR misses 2944system.l2c.UpgradeReq_mshr_misses::total 124197 # number of UpgradeReq MSHR misses 2945system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12467 # number of SCUpgradeReq MSHR misses 2946system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11210 # number of SCUpgradeReq MSHR misses 2947system.l2c.SCUpgradeReq_mshr_misses::total 23677 # number of SCUpgradeReq MSHR misses 2948system.l2c.ReadExReq_mshr_misses::cpu0.data 80795 # number of ReadExReq MSHR misses 2949system.l2c.ReadExReq_mshr_misses::cpu1.data 51109 # number of ReadExReq MSHR misses 2950system.l2c.ReadExReq_mshr_misses::total 131904 # number of ReadExReq MSHR misses 2951system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2056 # number of ReadSharedReq MSHR misses 2952system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 1934 # number of ReadSharedReq MSHR misses 2953system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 65962 # number of ReadSharedReq MSHR misses 2954system.l2c.ReadSharedReq_mshr_misses::cpu0.data 143261 # number of ReadSharedReq MSHR misses 2955system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 256484 # number of ReadSharedReq MSHR misses 2956system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1908 # number of ReadSharedReq MSHR misses 2957system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1578 # number of ReadSharedReq MSHR misses 2958system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 51956 # number of ReadSharedReq MSHR misses 2959system.l2c.ReadSharedReq_mshr_misses::cpu1.data 103861 # number of ReadSharedReq MSHR misses 2960system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 163476 # number of ReadSharedReq MSHR misses 2961system.l2c.ReadSharedReq_mshr_misses::total 792476 # number of ReadSharedReq MSHR misses 2962system.l2c.InvalidateReq_mshr_misses::cpu0.data 465421 # number of InvalidateReq MSHR misses 2963system.l2c.InvalidateReq_mshr_misses::cpu1.data 95414 # number of InvalidateReq MSHR misses 2964system.l2c.InvalidateReq_mshr_misses::total 560835 # number of InvalidateReq MSHR misses 2965system.l2c.demand_mshr_misses::cpu0.dtb.walker 2056 # number of demand (read+write) MSHR misses 2966system.l2c.demand_mshr_misses::cpu0.itb.walker 1934 # number of demand (read+write) MSHR misses 2967system.l2c.demand_mshr_misses::cpu0.inst 65962 # number of demand (read+write) MSHR misses 2968system.l2c.demand_mshr_misses::cpu0.data 224056 # number of demand (read+write) MSHR misses 2969system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 256484 # number of demand (read+write) MSHR misses 2970system.l2c.demand_mshr_misses::cpu1.dtb.walker 1908 # number of demand (read+write) MSHR misses 2971system.l2c.demand_mshr_misses::cpu1.itb.walker 1578 # number of demand (read+write) MSHR misses 2972system.l2c.demand_mshr_misses::cpu1.inst 51956 # number of demand (read+write) MSHR misses 2973system.l2c.demand_mshr_misses::cpu1.data 154970 # number of demand (read+write) MSHR misses 2974system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 163476 # number of demand (read+write) MSHR misses 2975system.l2c.demand_mshr_misses::total 924380 # number of demand (read+write) MSHR misses 2976system.l2c.overall_mshr_misses::cpu0.dtb.walker 2056 # number of overall MSHR misses 2977system.l2c.overall_mshr_misses::cpu0.itb.walker 1934 # number of overall MSHR misses 2978system.l2c.overall_mshr_misses::cpu0.inst 65962 # number of overall MSHR misses 2979system.l2c.overall_mshr_misses::cpu0.data 224056 # number of overall MSHR misses 2980system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 256484 # number of overall MSHR misses 2981system.l2c.overall_mshr_misses::cpu1.dtb.walker 1908 # number of overall MSHR misses 2982system.l2c.overall_mshr_misses::cpu1.itb.walker 1578 # number of overall MSHR misses 2983system.l2c.overall_mshr_misses::cpu1.inst 51956 # number of overall MSHR misses 2984system.l2c.overall_mshr_misses::cpu1.data 154970 # number of overall MSHR misses 2985system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 163476 # number of overall MSHR misses 2986system.l2c.overall_mshr_misses::total 924380 # number of overall MSHR misses 2987system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 52299 # number of ReadReq MSHR uncacheable 2988system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31702 # number of ReadReq MSHR uncacheable |
| 2974system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable | 2989system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 93 # number of ReadReq MSHR uncacheable |
| 2975system.l2c.ReadReq_mshr_uncacheable::cpu1.data 7335 # number of ReadReq MSHR uncacheable 2976system.l2c.ReadReq_mshr_uncacheable::total 91289 # number of ReadReq MSHR uncacheable 2977system.l2c.WriteReq_mshr_uncacheable::cpu0.data 31148 # number of WriteReq MSHR uncacheable 2978system.l2c.WriteReq_mshr_uncacheable::cpu1.data 7641 # number of WriteReq MSHR uncacheable 2979system.l2c.WriteReq_mshr_uncacheable::total 38789 # number of WriteReq MSHR uncacheable 2980system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52309 # number of overall MSHR uncacheable misses 2981system.l2c.overall_mshr_uncacheable_misses::cpu0.data 62700 # number of overall MSHR uncacheable misses | 2990system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6939 # number of ReadReq MSHR uncacheable 2991system.l2c.ReadReq_mshr_uncacheable::total 91033 # number of ReadReq MSHR uncacheable 2992system.l2c.WriteReq_mshr_uncacheable::cpu0.data 31225 # number of WriteReq MSHR uncacheable 2993system.l2c.WriteReq_mshr_uncacheable::cpu1.data 7280 # number of WriteReq MSHR uncacheable 2994system.l2c.WriteReq_mshr_uncacheable::total 38505 # number of WriteReq MSHR uncacheable 2995system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 52299 # number of overall MSHR uncacheable misses 2996system.l2c.overall_mshr_uncacheable_misses::cpu0.data 62927 # number of overall MSHR uncacheable misses |
| 2982system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses | 2997system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 93 # number of overall MSHR uncacheable misses |
| 2983system.l2c.overall_mshr_uncacheable_misses::cpu1.data 14976 # number of overall MSHR uncacheable misses 2984system.l2c.overall_mshr_uncacheable_misses::total 130078 # number of overall MSHR uncacheable misses 2985system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4482067996 # number of UpgradeReq MSHR miss cycles 2986system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4401703997 # number of UpgradeReq MSHR miss cycles 2987system.l2c.UpgradeReq_mshr_miss_latency::total 8883771993 # number of UpgradeReq MSHR miss cycles 2988system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 992507998 # number of SCUpgradeReq MSHR miss cycles 2989system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 871605998 # number of SCUpgradeReq MSHR miss cycles 2990system.l2c.SCUpgradeReq_mshr_miss_latency::total 1864113996 # number of SCUpgradeReq MSHR miss cycles 2991system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 10344161682 # number of ReadExReq MSHR miss cycles 2992system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 6287373504 # number of ReadExReq MSHR miss cycles 2993system.l2c.ReadExReq_mshr_miss_latency::total 16631535186 # number of ReadExReq MSHR miss cycles 2994system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 202642005 # number of ReadSharedReq MSHR miss cycles 2995system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 183792005 # number of ReadSharedReq MSHR miss cycles 2996system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 9367711407 # number of ReadSharedReq MSHR miss cycles 2997system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 18771270759 # number of ReadSharedReq MSHR miss cycles 2998system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 38070504234 # number of ReadSharedReq MSHR miss cycles 2999system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 304834024 # number of ReadSharedReq MSHR miss cycles 3000system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 260849021 # number of ReadSharedReq MSHR miss cycles 3001system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5931658488 # 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number of demand (read+write) MSHR miss cycles 3011system.l2c.demand_mshr_miss_latency::cpu0.data 29115432441 # number of demand (read+write) MSHR miss cycles 3012system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 38070504234 # number of demand (read+write) MSHR miss cycles 3013system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 304834024 # number of demand (read+write) MSHR miss cycles 3014system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 260849021 # number of demand (read+write) MSHR miss cycles 3015system.l2c.demand_mshr_miss_latency::cpu1.inst 5931658488 # number of demand (read+write) MSHR miss cycles 3016system.l2c.demand_mshr_miss_latency::cpu1.data 19505265139 # number of demand (read+write) MSHR miss cycles 3017system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 30868571958 # number of demand (read+write) MSHR miss cycles 3018system.l2c.demand_mshr_miss_latency::total 133811260722 # number of demand (read+write) MSHR miss cycles 3019system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 202642005 # number of overall MSHR miss cycles 3020system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 183792005 # number of overall MSHR miss cycles 3021system.l2c.overall_mshr_miss_latency::cpu0.inst 9367711407 # number of overall MSHR miss cycles 3022system.l2c.overall_mshr_miss_latency::cpu0.data 29115432441 # number of overall MSHR miss cycles 3023system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 38070504234 # number of overall MSHR miss cycles 3024system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 304834024 # number of overall MSHR miss cycles 3025system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 260849021 # number of overall MSHR miss cycles 3026system.l2c.overall_mshr_miss_latency::cpu1.inst 5931658488 # number of overall MSHR miss cycles 3027system.l2c.overall_mshr_miss_latency::cpu1.data 19505265139 # number of overall MSHR miss cycles 3028system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 30868571958 # number of overall MSHR miss cycles 3029system.l2c.overall_mshr_miss_latency::total 133811260722 # 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number of overall MSHR miss cycles 3044system.l2c.overall_mshr_miss_latency::total 87871704905 # number of overall MSHR miss cycles 3045system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3320524500 # number of ReadReq MSHR uncacheable cycles 3046system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5312322505 # number of ReadReq MSHR uncacheable cycles 3047system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5752000 # number of ReadReq MSHR uncacheable cycles 3048system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 656593502 # number of ReadReq MSHR uncacheable cycles 3049system.l2c.ReadReq_mshr_uncacheable_latency::total 9295192507 # number of ReadReq MSHR uncacheable cycles 3050system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3320524500 # number of overall MSHR uncacheable cycles 3051system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5312322505 # number of overall MSHR uncacheable cycles 3052system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5752000 # number of overall MSHR uncacheable cycles 3053system.l2c.overall_mshr_uncacheable_latency::cpu1.data 656593502 # number of overall MSHR uncacheable cycles 3054system.l2c.overall_mshr_uncacheable_latency::total 9295192507 # number of overall MSHR uncacheable cycles |
| 3040system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3041system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses | 3055system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3056system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| 3042system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.275862 # mshr miss rate for UpgradeReq accesses 3043system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.306052 # mshr miss rate for UpgradeReq accesses 3044system.l2c.UpgradeReq_mshr_miss_rate::total 0.290013 # mshr miss rate for UpgradeReq accesses 3045system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.237874 # mshr miss rate for SCUpgradeReq accesses 3046system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.225288 # mshr miss rate for SCUpgradeReq accesses 3047system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.231817 # mshr miss rate for SCUpgradeReq accesses 3048system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.604734 # mshr miss rate for ReadExReq accesses 3049system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.454062 # mshr miss rate for ReadExReq accesses 3050system.l2c.ReadExReq_mshr_miss_rate::total 0.535825 # mshr miss rate for ReadExReq accesses 3051system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.194759 # mshr miss rate for ReadSharedReq accesses 3052system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.255466 # mshr miss rate for ReadSharedReq accesses 3053system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.100380 # mshr miss rate for ReadSharedReq accesses 3054system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.189967 # mshr miss rate for ReadSharedReq accesses 3055system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.410594 # mshr miss rate for ReadSharedReq accesses 3056system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.245303 # mshr miss rate for ReadSharedReq accesses 3057system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.273125 # mshr miss rate for ReadSharedReq accesses 3058system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.069794 # mshr miss rate for ReadSharedReq accesses 3059system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.145225 # mshr miss rate for ReadSharedReq accesses 3060system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.371856 # mshr miss rate for ReadSharedReq accesses 3061system.l2c.ReadSharedReq_mshr_miss_rate::total 0.200269 # mshr miss rate for ReadSharedReq accesses 3062system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.779086 # mshr miss rate for InvalidateReq accesses 3063system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.408078 # mshr miss rate for InvalidateReq accesses 3064system.l2c.InvalidateReq_mshr_miss_rate::total 0.675667 # mshr miss rate for InvalidateReq accesses 3065system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.194759 # mshr miss rate for demand accesses 3066system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.255466 # mshr miss rate for demand accesses 3067system.l2c.demand_mshr_miss_rate::cpu0.inst 0.100380 # mshr miss rate for demand accesses 3068system.l2c.demand_mshr_miss_rate::cpu0.data 0.251652 # mshr miss rate for demand accesses 3069system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.410594 # mshr miss rate for demand accesses 3070system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.245303 # mshr miss rate for demand accesses 3071system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.273125 # mshr miss rate for demand accesses 3072system.l2c.demand_mshr_miss_rate::cpu1.inst 0.069794 # mshr miss rate for demand accesses 3073system.l2c.demand_mshr_miss_rate::cpu1.data 0.188212 # mshr miss rate for demand accesses 3074system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.371856 # mshr miss rate for demand accesses 3075system.l2c.demand_mshr_miss_rate::total 0.219641 # mshr miss rate for demand accesses 3076system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.194759 # mshr miss rate for overall accesses 3077system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.255466 # mshr miss rate for overall accesses 3078system.l2c.overall_mshr_miss_rate::cpu0.inst 0.100380 # mshr miss rate for overall accesses 3079system.l2c.overall_mshr_miss_rate::cpu0.data 0.251652 # mshr miss rate for overall accesses 3080system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.410594 # mshr miss rate for overall accesses 3081system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.245303 # mshr miss rate for overall accesses 3082system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.273125 # mshr miss rate for overall accesses 3083system.l2c.overall_mshr_miss_rate::cpu1.inst 0.069794 # mshr miss rate for overall accesses 3084system.l2c.overall_mshr_miss_rate::cpu1.data 0.188212 # mshr miss rate for overall accesses 3085system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.371856 # mshr miss rate for overall accesses 3086system.l2c.overall_mshr_miss_rate::total 0.219641 # mshr miss rate for overall accesses 3087system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70511.570770 # average UpgradeReq mshr miss latency 3088system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70744.197959 # average UpgradeReq mshr miss latency 3089system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70626.640641 # average UpgradeReq mshr miss latency 3090system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73589.975384 # average SCUpgradeReq mshr miss latency 3091system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73559.456325 # average SCUpgradeReq mshr miss latency 3092system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73575.702400 # average SCUpgradeReq mshr miss latency 3093system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128404.792537 # average ReadExReq mshr miss latency 3094system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123335.036761 # average ReadExReq mshr miss latency 3095system.l2c.ReadExReq_avg_mshr_miss_latency::total 126439.976478 # average ReadExReq mshr miss latency 3096system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 131075.035576 # average ReadSharedReq mshr miss latency 3097system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131092.728245 # average ReadSharedReq mshr miss latency 3098system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124515.989087 # average ReadSharedReq mshr miss latency 3099system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 129589.310186 # average ReadSharedReq mshr miss latency 3100system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 164766.720913 # average ReadSharedReq mshr miss latency 3101system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 129716.605957 # average ReadSharedReq mshr miss latency 3102system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 130685.882265 # average ReadSharedReq mshr miss latency 3103system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 124743.086118 # average ReadSharedReq mshr miss latency 3104system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131084.361928 # average ReadSharedReq mshr miss latency 3105system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157823.660625 # average ReadSharedReq mshr miss latency 3106system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 146034.545309 # average ReadSharedReq mshr miss latency 3107system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 69905.751133 # average InvalidateReq mshr miss latency 3108system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69900.131209 # average InvalidateReq mshr miss latency 3109system.l2c.InvalidateReq_avg_mshr_miss_latency::total 69904.804990 # average InvalidateReq mshr miss latency 3110system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 131075.035576 # average overall mshr miss latency 3111system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131092.728245 # average overall mshr miss latency 3112system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124515.989087 # average overall mshr miss latency 3113system.l2c.demand_avg_mshr_miss_latency::cpu0.data 129165.978772 # average overall mshr miss latency 3114system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 164766.720913 # average overall mshr miss latency 3115system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 129716.605957 # average overall mshr miss latency 3116system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130685.882265 # average overall mshr miss latency 3117system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 124743.086118 # average overall mshr miss latency 3118system.l2c.demand_avg_mshr_miss_latency::cpu1.data 128482.179649 # average overall mshr miss latency 3119system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157823.660625 # average overall mshr miss latency 3120system.l2c.demand_avg_mshr_miss_latency::total 143274.851193 # average overall mshr miss latency 3121system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 131075.035576 # average overall mshr miss latency 3122system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131092.728245 # average overall mshr miss latency 3123system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124515.989087 # average overall mshr miss latency 3124system.l2c.overall_avg_mshr_miss_latency::cpu0.data 129165.978772 # average overall mshr miss latency 3125system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 164766.720913 # average overall mshr miss latency 3126system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129716.605957 # average overall mshr miss latency 3127system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130685.882265 # average overall mshr miss latency 3128system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124743.086118 # average overall mshr miss latency 3129system.l2c.overall_avg_mshr_miss_latency::cpu1.data 128482.179649 # average overall mshr miss latency 3130system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157823.660625 # average overall mshr miss latency 3131system.l2c.overall_avg_mshr_miss_latency::total 143274.851193 # average overall mshr miss latency 3132system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency 3133system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165462.983424 # average ReadReq mshr uncacheable latency 3134system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280 # average ReadReq mshr uncacheable latency 3135system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 99350.240900 # average ReadReq mshr uncacheable latency 3136system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 129888.689437 # average ReadReq mshr uncacheable latency 3137system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency 3138system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83264.562249 # average overall mshr uncacheable latency 3139system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280 # average overall mshr uncacheable latency 3140system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 48660.123998 # average overall mshr uncacheable latency 3141system.l2c.overall_avg_mshr_uncacheable_latency::total 91156.141469 # average overall mshr uncacheable latency 3142system.membus.trans_dist::ReadReq 91289 # Transaction distribution 3143system.membus.trans_dist::ReadResp 902614 # Transaction distribution 3144system.membus.trans_dist::WriteReq 38789 # Transaction distribution 3145system.membus.trans_dist::WriteResp 38789 # Transaction distribution 3146system.membus.trans_dist::WritebackDirty 1182866 # Transaction distribution 3147system.membus.trans_dist::CleanEvict 259673 # Transaction distribution 3148system.membus.trans_dist::UpgradeReq 445486 # Transaction distribution 3149system.membus.trans_dist::SCUpgradeReq 315870 # Transaction distribution | 3057system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.273042 # mshr miss rate for UpgradeReq accesses 3058system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.312881 # mshr miss rate for UpgradeReq accesses 3059system.l2c.UpgradeReq_mshr_miss_rate::total 0.291035 # mshr miss rate for UpgradeReq accesses 3060system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.229959 # mshr miss rate for SCUpgradeReq accesses 3061system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.227623 # mshr miss rate for SCUpgradeReq accesses 3062system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.228847 # mshr miss rate for SCUpgradeReq accesses 3063system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.608025 # mshr miss rate for ReadExReq accesses 3064system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.463927 # mshr miss rate for ReadExReq accesses 3065system.l2c.ReadExReq_mshr_miss_rate::total 0.542710 # mshr miss rate for ReadExReq accesses 3066system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.244645 # mshr miss rate for ReadSharedReq accesses 3067system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.337994 # mshr miss rate for ReadSharedReq accesses 3068system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.091086 # mshr miss rate for ReadSharedReq accesses 3069system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.187612 # mshr miss rate for ReadSharedReq accesses 3070system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447477 # mshr miss rate for ReadSharedReq accesses 3071system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.216179 # mshr miss rate for ReadSharedReq accesses 3072system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.232950 # mshr miss rate for ReadSharedReq accesses 3073system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.077247 # mshr miss rate for ReadSharedReq accesses 3074system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.155621 # mshr miss rate for ReadSharedReq accesses 3075system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.343371 # mshr miss rate for ReadSharedReq accesses 3076system.l2c.ReadSharedReq_mshr_miss_rate::total 0.202847 # mshr miss rate for ReadSharedReq accesses 3077system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.781222 # mshr miss rate for InvalidateReq accesses 3078system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.415262 # mshr miss rate for InvalidateReq accesses 3079system.l2c.InvalidateReq_mshr_miss_rate::total 0.679365 # mshr miss rate for InvalidateReq accesses 3080system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.244645 # mshr miss rate for demand accesses 3081system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.337994 # mshr miss rate for demand accesses 3082system.l2c.demand_mshr_miss_rate::cpu0.inst 0.091086 # mshr miss rate for demand accesses 3083system.l2c.demand_mshr_miss_rate::cpu0.data 0.249927 # mshr miss rate for demand accesses 3084system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447477 # mshr miss rate for demand accesses 3085system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.216179 # mshr miss rate for demand accesses 3086system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.232950 # mshr miss rate for demand accesses 3087system.l2c.demand_mshr_miss_rate::cpu1.inst 0.077247 # mshr miss rate for demand accesses 3088system.l2c.demand_mshr_miss_rate::cpu1.data 0.199302 # mshr miss rate for demand accesses 3089system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.343371 # mshr miss rate for demand accesses 3090system.l2c.demand_mshr_miss_rate::total 0.222752 # mshr miss rate for demand accesses 3091system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.244645 # mshr miss rate for overall accesses 3092system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.337994 # mshr miss rate for overall accesses 3093system.l2c.overall_mshr_miss_rate::cpu0.inst 0.091086 # mshr miss rate for overall accesses 3094system.l2c.overall_mshr_miss_rate::cpu0.data 0.249927 # mshr miss rate for overall accesses 3095system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447477 # mshr miss rate for overall accesses 3096system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.216179 # mshr miss rate for overall accesses 3097system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.232950 # mshr miss rate for overall accesses 3098system.l2c.overall_mshr_miss_rate::cpu1.inst 0.077247 # mshr miss rate for overall accesses 3099system.l2c.overall_mshr_miss_rate::cpu1.data 0.199302 # mshr miss rate for overall accesses 3100system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.343371 # mshr miss rate for overall accesses 3101system.l2c.overall_mshr_miss_rate::total 0.222752 # mshr miss rate for overall accesses 3102system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21610.225883 # average UpgradeReq mshr miss latency 3103system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21647.742077 # average UpgradeReq mshr miss latency 3104system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21628.441009 # average UpgradeReq mshr miss latency 3105system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24617.068902 # average SCUpgradeReq mshr miss latency 3106system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24607.448617 # average SCUpgradeReq mshr miss latency 3107system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24612.514128 # average SCUpgradeReq mshr miss latency 3108system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79236.339662 # average ReadExReq mshr miss latency 3109system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72651.227338 # average ReadExReq mshr miss latency 3110system.l2c.ReadExReq_avg_mshr_miss_latency::total 76684.798346 # average ReadExReq mshr miss latency 3111system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average ReadSharedReq mshr miss latency 3112system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average ReadSharedReq mshr miss latency 3113system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average ReadSharedReq mshr miss latency 3114system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79699.783619 # average ReadSharedReq mshr miss latency 3115system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average ReadSharedReq mshr miss latency 3116system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average ReadSharedReq mshr miss latency 3117system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average ReadSharedReq mshr miss latency 3118system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average ReadSharedReq mshr miss latency 3119system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 81643.583511 # average ReadSharedReq mshr miss latency 3120system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average ReadSharedReq mshr miss latency 3121system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 98118.647459 # average ReadSharedReq mshr miss latency 3122system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 20918.654291 # average InvalidateReq mshr miss latency 3123system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20760.842224 # average InvalidateReq mshr miss latency 3124system.l2c.InvalidateReq_avg_mshr_miss_latency::total 20891.805966 # average InvalidateReq mshr miss latency 3125system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average overall mshr miss latency 3126system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average overall mshr miss latency 3127system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average overall mshr miss latency 3128system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79532.664887 # average overall mshr miss latency 3129system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average overall mshr miss latency 3130system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average overall mshr miss latency 3131system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average overall mshr miss latency 3132system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average overall mshr miss latency 3133system.l2c.demand_avg_mshr_miss_latency::cpu1.data 78677.910596 # average overall mshr miss latency 3134system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average overall mshr miss latency 3135system.l2c.demand_avg_mshr_miss_latency::total 95060.153730 # average overall mshr miss latency 3136system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78116.974708 # average overall mshr miss latency 3137system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 79611.427094 # average overall mshr miss latency 3138system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75014.327552 # average overall mshr miss latency 3139system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79532.664887 # average overall mshr miss latency 3140system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117628.629743 # average overall mshr miss latency 3141system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81637.057652 # average overall mshr miss latency 3142system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 82346.643219 # average overall mshr miss latency 3143system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74892.092732 # average overall mshr miss latency 3144system.l2c.overall_avg_mshr_miss_latency::cpu1.data 78677.910596 # average overall mshr miss latency 3145system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 111636.476987 # average overall mshr miss latency 3146system.l2c.overall_avg_mshr_miss_latency::total 95060.153730 # average overall mshr miss latency 3147system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63491.166179 # average ReadReq mshr uncacheable latency 3148system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167570.579301 # average ReadReq mshr uncacheable latency 3149system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61849.462366 # average ReadReq mshr uncacheable latency 3150system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 94623.649229 # average ReadReq mshr uncacheable latency 3151system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 102107.944449 # average ReadReq mshr uncacheable latency 3152system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63491.166179 # average overall mshr uncacheable latency 3153system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 84420.399908 # average overall mshr uncacheable latency 3154system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61849.462366 # average overall mshr uncacheable latency 3155system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 46177.192630 # average overall mshr uncacheable latency 3156system.l2c.overall_avg_mshr_uncacheable_latency::total 71756.492357 # average overall mshr uncacheable latency 3157system.membus.snoop_filter.tot_requests 3789204 # Total number of requests made to the snoop filter. 3158system.membus.snoop_filter.hit_single_requests 2296931 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3159system.membus.snoop_filter.hit_multi_requests 2908 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3160system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3161system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3162system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3163system.membus.trans_dist::ReadReq 91033 # Transaction distribution 3164system.membus.trans_dist::ReadResp 892432 # Transaction distribution 3165system.membus.trans_dist::WriteReq 38505 # Transaction distribution 3166system.membus.trans_dist::WriteResp 38505 # Transaction distribution 3167system.membus.trans_dist::WritebackDirty 1181777 # Transaction distribution 3168system.membus.trans_dist::CleanEvict 252869 # Transaction distribution 3169system.membus.trans_dist::UpgradeReq 437143 # Transaction distribution 3170system.membus.trans_dist::SCUpgradeReq 308404 # Transaction distribution |
| 3150system.membus.trans_dist::UpgradeResp 22 # Transaction distribution 3151system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution | 3171system.membus.trans_dist::UpgradeResp 22 # Transaction distribution 3172system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution |
| 3152system.membus.trans_dist::ReadExReq 143483 # Transaction distribution 3153system.membus.trans_dist::ReadExResp 126149 # Transaction distribution 3154system.membus.trans_dist::ReadSharedReq 811325 # Transaction distribution 3155system.membus.trans_dist::InvalidateReq 668729 # Transaction distribution 3156system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122924 # Packet count per connected master and slave (bytes) | 3173system.membus.trans_dist::ReadExReq 143945 # Transaction distribution 3174system.membus.trans_dist::ReadExResp 126263 # Transaction distribution 3175system.membus.trans_dist::ReadSharedReq 801399 # Transaction distribution 3176system.membus.trans_dist::InvalidateReq 663637 # Transaction distribution 3177system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122598 # Packet count per connected master and slave (bytes) |
| 3157system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) | 3178system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) |
| 3158system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27208 # Packet count per connected master and slave (bytes) 3159system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4633500 # Packet count per connected master and slave (bytes) 3160system.membus.pkt_count_system.l2c.mem_side::total 4783684 # Packet count per connected master and slave (bytes) 3161system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238198 # Packet count per connected master and slave (bytes) 3162system.membus.pkt_count_system.iocache.mem_side::total 238198 # Packet count per connected master and slave (bytes) 3163system.membus.pkt_count::total 5021882 # Packet count per connected master and slave (bytes) 3164system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155939 # Cumulative packet size per connected master and slave (bytes) | 3179system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26474 # Packet count per connected master and slave (bytes) 3180system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4585882 # Packet count per connected master and slave (bytes) 3181system.membus.pkt_count_system.l2c.mem_side::total 4735006 # Packet count per connected master and slave (bytes) 3182system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238206 # Packet count per connected master and slave (bytes) 3183system.membus.pkt_count_system.iocache.mem_side::total 238206 # Packet count per connected master and slave (bytes) 3184system.membus.pkt_count::total 4973212 # Packet count per connected master and slave (bytes) 3185system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155705 # Cumulative packet size per connected master and slave (bytes) |
| 3165system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) | 3186system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) |
| 3166system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54416 # Cumulative packet size per connected master and slave (bytes) 3167system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 131613504 # Cumulative packet size per connected master and slave (bytes) 3168system.membus.pkt_size_system.l2c.mem_side::total 131825183 # Cumulative packet size per connected master and slave (bytes) 3169system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257920 # Cumulative packet size per connected master and slave (bytes) 3170system.membus.pkt_size_system.iocache.mem_side::total 7257920 # Cumulative packet size per connected master and slave (bytes) 3171system.membus.pkt_size::total 139083103 # Cumulative packet size per connected master and slave (bytes) 3172system.membus.snoops 621301 # Total snoops (count) 3173system.membus.snoop_fanout::samples 3957559 # Request fanout histogram 3174system.membus.snoop_fanout::mean 1 # Request fanout histogram 3175system.membus.snoop_fanout::stdev 0 # Request fanout histogram | 3187system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52948 # Cumulative packet size per connected master and slave (bytes) 3188system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 130931136 # Cumulative packet size per connected master and slave (bytes) 3189system.membus.pkt_size_system.l2c.mem_side::total 131141113 # Cumulative packet size per connected master and slave (bytes) 3190system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7272704 # Cumulative packet size per connected master and slave (bytes) 3191system.membus.pkt_size_system.iocache.mem_side::total 7272704 # Cumulative packet size per connected master and slave (bytes) 3192system.membus.pkt_size::total 138413817 # Cumulative packet size per connected master and slave (bytes) 3193system.membus.snoops 608511 # Total snoops (count) 3194system.membus.snoop_fanout::samples 2484071 # Request fanout histogram 3195system.membus.snoop_fanout::mean 0.012278 # Request fanout histogram 3196system.membus.snoop_fanout::stdev 0.110125 # Request fanout histogram |
| 3176system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 3197system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 3177system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3178system.membus.snoop_fanout::1 3957559 100.00% 100.00% # Request fanout histogram | 3198system.membus.snoop_fanout::0 2453571 98.77% 98.77% # Request fanout histogram 3199system.membus.snoop_fanout::1 30500 1.23% 100.00% # Request fanout histogram |
| 3179system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3180system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 3200system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3201system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 3181system.membus.snoop_fanout::min_value 1 # Request fanout histogram | 3202system.membus.snoop_fanout::min_value 0 # Request fanout histogram |
| 3182system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 3203system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 3183system.membus.snoop_fanout::total 3957559 # Request fanout histogram 3184system.membus.reqLayer0.occupancy 105148497 # Layer occupancy (ticks) | 3204system.membus.snoop_fanout::total 2484071 # Request fanout histogram 3205system.membus.reqLayer0.occupancy 105594995 # Layer occupancy (ticks) |
| 3185system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3186system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) 3187system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 3206system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3207system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks) 3208system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 3188system.membus.reqLayer2.occupancy 22946496 # Layer occupancy (ticks) | 3209system.membus.reqLayer2.occupancy 22316500 # Layer occupancy (ticks) |
| 3189system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 3210system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 3190system.membus.reqLayer5.occupancy 8356686345 # Layer occupancy (ticks) | 3211system.membus.reqLayer5.occupancy 8304045809 # Layer occupancy (ticks) |
| 3191system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 3212system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 3192system.membus.respLayer2.occupancy 5285705581 # Layer occupancy (ticks) | 3213system.membus.respLayer2.occupancy 5231778477 # Layer occupancy (ticks) |
| 3193system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 3214system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 3194system.membus.respLayer3.occupancy 45456154 # Layer occupancy (ticks) | 3215system.membus.respLayer3.occupancy 45499333 # Layer occupancy (ticks) |
| 3195system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3196system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3197system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3198system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3199system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3200system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3201system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3202system.realview.ethernet.txBytes 966 # Bytes Transmitted --- 37 unchanged lines hidden (view full) --- 3240system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3241system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3242system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3243system.realview.ethernet.droppedPackets 0 # number of packets dropped 3244system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3245system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3246system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3247system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks | 3216system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3217system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3218system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3219system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3220system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3221system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3222system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3223system.realview.ethernet.txBytes 966 # Bytes Transmitted --- 37 unchanged lines hidden (view full) --- 3261system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3262system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3263system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3264system.realview.ethernet.droppedPackets 0 # number of packets dropped 3265system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3266system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3267system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3268system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks |
| 3248system.toL2Bus.snoop_filter.tot_requests 12610950 # Total number of requests made to the snoop filter. 3249system.toL2Bus.snoop_filter.hit_single_requests 6824430 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3250system.toL2Bus.snoop_filter.hit_multi_requests 2134576 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3251system.toL2Bus.snoop_filter.tot_snoops 142334 # Total number of snoops made to the snoop filter. 3252system.toL2Bus.snoop_filter.hit_single_snoops 128133 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3253system.toL2Bus.snoop_filter.hit_multi_snoops 14201 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3254system.toL2Bus.trans_dist::ReadReq 91291 # Transaction distribution 3255system.toL2Bus.trans_dist::ReadResp 4901304 # Transaction distribution 3256system.toL2Bus.trans_dist::WriteReq 38789 # Transaction distribution 3257system.toL2Bus.trans_dist::WriteResp 38789 # Transaction distribution 3258system.toL2Bus.trans_dist::WritebackDirty 3987141 # Transaction distribution 3259system.toL2Bus.trans_dist::CleanEvict 3034318 # Transaction distribution 3260system.toL2Bus.trans_dist::UpgradeReq 743952 # Transaction distribution 3261system.toL2Bus.trans_dist::SCUpgradeReq 399827 # Transaction distribution 3262system.toL2Bus.trans_dist::UpgradeResp 1143779 # Transaction distribution 3263system.toL2Bus.trans_dist::SCUpgradeFailReq 116 # Transaction distribution 3264system.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution 3265system.toL2Bus.trans_dist::ReadExReq 302895 # Transaction distribution 3266system.toL2Bus.trans_dist::ReadExResp 302895 # Transaction distribution 3267system.toL2Bus.trans_dist::ReadSharedReq 4817262 # Transaction distribution 3268system.toL2Bus.trans_dist::InvalidateReq 944420 # Transaction distribution 3269system.toL2Bus.trans_dist::InvalidateResp 837436 # Transaction distribution 3270system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10209362 # Packet count per connected master and slave (bytes) 3271system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8295779 # Packet count per connected master and slave (bytes) 3272system.toL2Bus.pkt_count::total 18505141 # Packet count per connected master and slave (bytes) 3273system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 250153960 # Cumulative packet size per connected master and slave (bytes) 3274system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 205145975 # Cumulative packet size per connected master and slave (bytes) 3275system.toL2Bus.pkt_size::total 455299935 # Cumulative packet size per connected master and slave (bytes) 3276system.toL2Bus.snoops 3080857 # Total snoops (count) 3277system.toL2Bus.snoop_fanout::samples 8841930 # Request fanout histogram 3278system.toL2Bus.snoop_fanout::mean 0.362342 # Request fanout histogram 3279system.toL2Bus.snoop_fanout::stdev 0.484007 # Request fanout histogram | 3269system.toL2Bus.snoop_filter.tot_requests 12326432 # Total number of requests made to the snoop filter. 3270system.toL2Bus.snoop_filter.hit_single_requests 6670511 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3271system.toL2Bus.snoop_filter.hit_multi_requests 2086069 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3272system.toL2Bus.snoop_filter.tot_snoops 130580 # Total number of snoops made to the snoop filter. 3273system.toL2Bus.snoop_filter.hit_single_snoops 118652 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3274system.toL2Bus.snoop_filter.hit_multi_snoops 11928 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3275system.toL2Bus.trans_dist::ReadReq 91035 # Transaction distribution 3276system.toL2Bus.trans_dist::ReadResp 4782322 # Transaction distribution 3277system.toL2Bus.trans_dist::WriteReq 38505 # Transaction distribution 3278system.toL2Bus.trans_dist::WriteResp 38505 # Transaction distribution 3279system.toL2Bus.trans_dist::WritebackDirty 3822609 # Transaction distribution 3280system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution 3281system.toL2Bus.trans_dist::CleanEvict 2941580 # Transaction distribution 3282system.toL2Bus.trans_dist::UpgradeReq 730122 # Transaction distribution 3283system.toL2Bus.trans_dist::SCUpgradeReq 388189 # Transaction distribution 3284system.toL2Bus.trans_dist::UpgradeResp 1118311 # Transaction distribution 3285system.toL2Bus.trans_dist::SCUpgradeFailReq 111 # Transaction distribution 3286system.toL2Bus.trans_dist::UpgradeFailResp 111 # Transaction distribution 3287system.toL2Bus.trans_dist::ReadExReq 299700 # Transaction distribution 3288system.toL2Bus.trans_dist::ReadExResp 299700 # Transaction distribution 3289system.toL2Bus.trans_dist::ReadSharedReq 4691812 # Transaction distribution 3290system.toL2Bus.trans_dist::InvalidateReq 853093 # Transaction distribution 3291system.toL2Bus.trans_dist::InvalidateResp 825528 # Transaction distribution 3292system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10130133 # Packet count per connected master and slave (bytes) 3293system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7962376 # Packet count per connected master and slave (bytes) 3294system.toL2Bus.pkt_count::total 18092509 # Packet count per connected master and slave (bytes) 3295system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 250257116 # Cumulative packet size per connected master and slave (bytes) 3296system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 194861853 # Cumulative packet size per connected master and slave (bytes) 3297system.toL2Bus.pkt_size::total 445118969 # Cumulative packet size per connected master and slave (bytes) 3298system.toL2Bus.snoops 2830390 # Total snoops (count) 3299system.toL2Bus.snoop_fanout::samples 8463866 # Request fanout histogram 3300system.toL2Bus.snoop_fanout::mean 0.368667 # Request fanout histogram 3301system.toL2Bus.snoop_fanout::stdev 0.485356 # Request fanout histogram |
| 3280system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 3302system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 3281system.toL2Bus.snoop_fanout::0 5652330 63.93% 63.93% # Request fanout histogram 3282system.toL2Bus.snoop_fanout::1 3175399 35.91% 99.84% # Request fanout histogram 3283system.toL2Bus.snoop_fanout::2 14201 0.16% 100.00% # Request fanout histogram | 3303system.toL2Bus.snoop_fanout::0 5355444 63.27% 63.27% # Request fanout histogram 3304system.toL2Bus.snoop_fanout::1 3096494 36.58% 99.86% # Request fanout histogram 3305system.toL2Bus.snoop_fanout::2 11928 0.14% 100.00% # Request fanout histogram |
| 3284system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3285system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3286system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 3306system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3307system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3308system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 3287system.toL2Bus.snoop_fanout::total 8841930 # Request fanout histogram 3288system.toL2Bus.reqLayer0.occupancy 9598709952 # Layer occupancy (ticks) | 3309system.toL2Bus.snoop_fanout::total 8463866 # Request fanout histogram 3310system.toL2Bus.reqLayer0.occupancy 9400124055 # Layer occupancy (ticks) |
| 3289system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 3311system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 3290system.toL2Bus.snoopLayer0.occupancy 2569910 # Layer occupancy (ticks) | 3312system.toL2Bus.snoopLayer0.occupancy 2566916 # Layer occupancy (ticks) |
| 3291system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 3313system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 3292system.toL2Bus.respLayer0.occupancy 4696248682 # Layer occupancy (ticks) | 3314system.toL2Bus.respLayer0.occupancy 4651836575 # Layer occupancy (ticks) |
| 3293system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 3315system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 3294system.toL2Bus.respLayer1.occupancy 4118726891 # Layer occupancy (ticks) | 3316system.toL2Bus.respLayer1.occupancy 3960751843 # Layer occupancy (ticks) |
| 3295system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3296 3297---------- End Simulation Statistics ---------- | 3317system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3318 3319---------- End Simulation Statistics ---------- |