| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.535940 # Number of seconds simulated 4sim_ticks 47535940136000 # Number of ticks simulated 5final_tick 47535940136000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.535940 # Number of seconds simulated 4sim_ticks 47535940136000 # Number of ticks simulated 5final_tick 47535940136000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 225035 # Simulator instruction rate (inst/s) 8host_op_rate 264677 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 11911388135 # Simulator tick rate (ticks/s) 10host_mem_usage 769700 # Number of bytes of host memory used 11host_seconds 3990.80 # Real time elapsed on the host | 7host_inst_rate 200561 # Simulator instruction rate (inst/s) 8host_op_rate 235891 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 10615931561 # Simulator tick rate (ticks/s) 10host_mem_usage 769436 # Number of bytes of host memory used 11host_seconds 4477.79 # Real time elapsed on the host |
| 12sim_insts 898069628 # Number of instructions simulated 13sim_ops 1056270581 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 98944 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 89728 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 8161024 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 14243656 # Number of bytes read from this memory --- 622 unchanged lines hidden (view full) --- 642system.cpu0.dcache.SoftPFReq_hits::cpu0.data 305030 # number of SoftPFReq hits 643system.cpu0.dcache.SoftPFReq_hits::total 305030 # number of SoftPFReq hits 644system.cpu0.dcache.WriteLineReq_hits::cpu0.data 287060 # number of WriteLineReq hits 645system.cpu0.dcache.WriteLineReq_hits::total 287060 # number of WriteLineReq hits 646system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1877481 # number of LoadLockedReq hits 647system.cpu0.dcache.LoadLockedReq_hits::total 1877481 # number of LoadLockedReq hits 648system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1849167 # number of StoreCondReq hits 649system.cpu0.dcache.StoreCondReq_hits::total 1849167 # number of StoreCondReq hits | 12sim_insts 898069628 # Number of instructions simulated 13sim_ops 1056270581 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 98944 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 89728 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 8161024 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 14243656 # Number of bytes read from this memory --- 622 unchanged lines hidden (view full) --- 642system.cpu0.dcache.SoftPFReq_hits::cpu0.data 305030 # number of SoftPFReq hits 643system.cpu0.dcache.SoftPFReq_hits::total 305030 # number of SoftPFReq hits 644system.cpu0.dcache.WriteLineReq_hits::cpu0.data 287060 # number of WriteLineReq hits 645system.cpu0.dcache.WriteLineReq_hits::total 287060 # number of WriteLineReq hits 646system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1877481 # number of LoadLockedReq hits 647system.cpu0.dcache.LoadLockedReq_hits::total 1877481 # number of LoadLockedReq hits 648system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1849167 # number of StoreCondReq hits 649system.cpu0.dcache.StoreCondReq_hits::total 1849167 # number of StoreCondReq hits |
| 650system.cpu0.dcache.demand_hits::cpu0.data 164286110 # number of demand (read+write) hits 651system.cpu0.dcache.demand_hits::total 164286110 # number of demand (read+write) hits 652system.cpu0.dcache.overall_hits::cpu0.data 164591140 # number of overall hits 653system.cpu0.dcache.overall_hits::total 164591140 # number of overall hits | 650system.cpu0.dcache.demand_hits::cpu0.data 164573170 # number of demand (read+write) hits 651system.cpu0.dcache.demand_hits::total 164573170 # number of demand (read+write) hits 652system.cpu0.dcache.overall_hits::cpu0.data 164878200 # number of overall hits 653system.cpu0.dcache.overall_hits::total 164878200 # number of overall hits |
| 654system.cpu0.dcache.ReadReq_misses::cpu0.data 3693348 # number of ReadReq misses 655system.cpu0.dcache.ReadReq_misses::total 3693348 # number of ReadReq misses 656system.cpu0.dcache.WriteReq_misses::cpu0.data 2460225 # number of WriteReq misses 657system.cpu0.dcache.WriteReq_misses::total 2460225 # number of WriteReq misses 658system.cpu0.dcache.SoftPFReq_misses::cpu0.data 661742 # number of SoftPFReq misses 659system.cpu0.dcache.SoftPFReq_misses::total 661742 # number of SoftPFReq misses 660system.cpu0.dcache.WriteLineReq_misses::cpu0.data 847892 # number of WriteLineReq misses 661system.cpu0.dcache.WriteLineReq_misses::total 847892 # number of WriteLineReq misses 662system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173543 # number of LoadLockedReq misses 663system.cpu0.dcache.LoadLockedReq_misses::total 173543 # number of LoadLockedReq misses 664system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200600 # number of StoreCondReq misses 665system.cpu0.dcache.StoreCondReq_misses::total 200600 # number of StoreCondReq misses | 654system.cpu0.dcache.ReadReq_misses::cpu0.data 3693348 # number of ReadReq misses 655system.cpu0.dcache.ReadReq_misses::total 3693348 # number of ReadReq misses 656system.cpu0.dcache.WriteReq_misses::cpu0.data 2460225 # number of WriteReq misses 657system.cpu0.dcache.WriteReq_misses::total 2460225 # number of WriteReq misses 658system.cpu0.dcache.SoftPFReq_misses::cpu0.data 661742 # number of SoftPFReq misses 659system.cpu0.dcache.SoftPFReq_misses::total 661742 # number of SoftPFReq misses 660system.cpu0.dcache.WriteLineReq_misses::cpu0.data 847892 # number of WriteLineReq misses 661system.cpu0.dcache.WriteLineReq_misses::total 847892 # number of WriteLineReq misses 662system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 173543 # number of LoadLockedReq misses 663system.cpu0.dcache.LoadLockedReq_misses::total 173543 # number of LoadLockedReq misses 664system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200600 # number of StoreCondReq misses 665system.cpu0.dcache.StoreCondReq_misses::total 200600 # number of StoreCondReq misses |
| 666system.cpu0.dcache.demand_misses::cpu0.data 6153573 # number of demand (read+write) misses 667system.cpu0.dcache.demand_misses::total 6153573 # number of demand (read+write) misses 668system.cpu0.dcache.overall_misses::cpu0.data 6815315 # number of overall misses 669system.cpu0.dcache.overall_misses::total 6815315 # number of overall misses | 666system.cpu0.dcache.demand_misses::cpu0.data 7001465 # number of demand (read+write) misses 667system.cpu0.dcache.demand_misses::total 7001465 # number of demand (read+write) misses 668system.cpu0.dcache.overall_misses::cpu0.data 7663207 # number of overall misses 669system.cpu0.dcache.overall_misses::total 7663207 # number of overall misses |
| 670system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 64125292500 # number of ReadReq miss cycles 671system.cpu0.dcache.ReadReq_miss_latency::total 64125292500 # number of ReadReq miss cycles 672system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 62047058000 # number of WriteReq miss cycles 673system.cpu0.dcache.WriteReq_miss_latency::total 62047058000 # number of WriteReq miss cycles 674system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 51167444000 # number of WriteLineReq miss cycles 675system.cpu0.dcache.WriteLineReq_miss_latency::total 51167444000 # number of WriteLineReq miss cycles 676system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2860725000 # number of LoadLockedReq miss cycles 677system.cpu0.dcache.LoadLockedReq_miss_latency::total 2860725000 # number of LoadLockedReq miss cycles 678system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5699610500 # number of StoreCondReq miss cycles 679system.cpu0.dcache.StoreCondReq_miss_latency::total 5699610500 # number of StoreCondReq miss cycles 680system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5746000 # number of StoreCondFailReq miss cycles 681system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5746000 # number of StoreCondFailReq miss cycles | 670system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 64125292500 # number of ReadReq miss cycles 671system.cpu0.dcache.ReadReq_miss_latency::total 64125292500 # number of ReadReq miss cycles 672system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 62047058000 # number of WriteReq miss cycles 673system.cpu0.dcache.WriteReq_miss_latency::total 62047058000 # number of WriteReq miss cycles 674system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 51167444000 # number of WriteLineReq miss cycles 675system.cpu0.dcache.WriteLineReq_miss_latency::total 51167444000 # number of WriteLineReq miss cycles 676system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2860725000 # number of LoadLockedReq miss cycles 677system.cpu0.dcache.LoadLockedReq_miss_latency::total 2860725000 # number of LoadLockedReq miss cycles 678system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5699610500 # number of StoreCondReq miss cycles 679system.cpu0.dcache.StoreCondReq_miss_latency::total 5699610500 # number of StoreCondReq miss cycles 680system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5746000 # number of StoreCondFailReq miss cycles 681system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5746000 # number of StoreCondFailReq miss cycles |
| 682system.cpu0.dcache.demand_miss_latency::cpu0.data 126172350500 # number of demand (read+write) miss cycles 683system.cpu0.dcache.demand_miss_latency::total 126172350500 # number of demand (read+write) miss cycles 684system.cpu0.dcache.overall_miss_latency::cpu0.data 126172350500 # number of overall miss cycles 685system.cpu0.dcache.overall_miss_latency::total 126172350500 # number of overall miss cycles | 682system.cpu0.dcache.demand_miss_latency::cpu0.data 177339794500 # number of demand (read+write) miss cycles 683system.cpu0.dcache.demand_miss_latency::total 177339794500 # number of demand (read+write) miss cycles 684system.cpu0.dcache.overall_miss_latency::cpu0.data 177339794500 # number of overall miss cycles 685system.cpu0.dcache.overall_miss_latency::total 177339794500 # number of overall miss cycles |
| 686system.cpu0.dcache.ReadReq_accesses::cpu0.data 90736709 # number of ReadReq accesses(hits+misses) 687system.cpu0.dcache.ReadReq_accesses::total 90736709 # number of ReadReq accesses(hits+misses) 688system.cpu0.dcache.WriteReq_accesses::cpu0.data 79702974 # number of WriteReq accesses(hits+misses) 689system.cpu0.dcache.WriteReq_accesses::total 79702974 # number of WriteReq accesses(hits+misses) 690system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 966772 # number of SoftPFReq accesses(hits+misses) 691system.cpu0.dcache.SoftPFReq_accesses::total 966772 # number of SoftPFReq accesses(hits+misses) 692system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1134952 # number of WriteLineReq accesses(hits+misses) 693system.cpu0.dcache.WriteLineReq_accesses::total 1134952 # number of WriteLineReq accesses(hits+misses) 694system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2051024 # number of LoadLockedReq accesses(hits+misses) 695system.cpu0.dcache.LoadLockedReq_accesses::total 2051024 # number of LoadLockedReq accesses(hits+misses) 696system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2049767 # number of StoreCondReq accesses(hits+misses) 697system.cpu0.dcache.StoreCondReq_accesses::total 2049767 # number of StoreCondReq accesses(hits+misses) | 686system.cpu0.dcache.ReadReq_accesses::cpu0.data 90736709 # number of ReadReq accesses(hits+misses) 687system.cpu0.dcache.ReadReq_accesses::total 90736709 # number of ReadReq accesses(hits+misses) 688system.cpu0.dcache.WriteReq_accesses::cpu0.data 79702974 # number of WriteReq accesses(hits+misses) 689system.cpu0.dcache.WriteReq_accesses::total 79702974 # number of WriteReq accesses(hits+misses) 690system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 966772 # number of SoftPFReq accesses(hits+misses) 691system.cpu0.dcache.SoftPFReq_accesses::total 966772 # number of SoftPFReq accesses(hits+misses) 692system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1134952 # number of WriteLineReq accesses(hits+misses) 693system.cpu0.dcache.WriteLineReq_accesses::total 1134952 # number of WriteLineReq accesses(hits+misses) 694system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2051024 # number of LoadLockedReq accesses(hits+misses) 695system.cpu0.dcache.LoadLockedReq_accesses::total 2051024 # number of LoadLockedReq accesses(hits+misses) 696system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2049767 # number of StoreCondReq accesses(hits+misses) 697system.cpu0.dcache.StoreCondReq_accesses::total 2049767 # number of StoreCondReq accesses(hits+misses) |
| 698system.cpu0.dcache.demand_accesses::cpu0.data 170439683 # number of demand (read+write) accesses 699system.cpu0.dcache.demand_accesses::total 170439683 # number of demand (read+write) accesses 700system.cpu0.dcache.overall_accesses::cpu0.data 171406455 # number of overall (read+write) accesses 701system.cpu0.dcache.overall_accesses::total 171406455 # number of overall (read+write) accesses | 698system.cpu0.dcache.demand_accesses::cpu0.data 171574635 # number of demand (read+write) accesses 699system.cpu0.dcache.demand_accesses::total 171574635 # number of demand (read+write) accesses 700system.cpu0.dcache.overall_accesses::cpu0.data 172541407 # number of overall (read+write) accesses 701system.cpu0.dcache.overall_accesses::total 172541407 # number of overall (read+write) accesses |
| 702system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040704 # miss rate for ReadReq accesses 703system.cpu0.dcache.ReadReq_miss_rate::total 0.040704 # miss rate for ReadReq accesses 704system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030867 # miss rate for WriteReq accesses 705system.cpu0.dcache.WriteReq_miss_rate::total 0.030867 # miss rate for WriteReq accesses 706system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.684486 # miss rate for SoftPFReq accesses 707system.cpu0.dcache.SoftPFReq_miss_rate::total 0.684486 # miss rate for SoftPFReq accesses 708system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.747073 # miss rate for WriteLineReq accesses 709system.cpu0.dcache.WriteLineReq_miss_rate::total 0.747073 # miss rate for WriteLineReq accesses 710system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084613 # miss rate for LoadLockedReq accesses 711system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084613 # miss rate for LoadLockedReq accesses 712system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097865 # miss rate for StoreCondReq accesses 713system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097865 # miss rate for StoreCondReq accesses | 702system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040704 # miss rate for ReadReq accesses 703system.cpu0.dcache.ReadReq_miss_rate::total 0.040704 # miss rate for ReadReq accesses 704system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030867 # miss rate for WriteReq accesses 705system.cpu0.dcache.WriteReq_miss_rate::total 0.030867 # miss rate for WriteReq accesses 706system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.684486 # miss rate for SoftPFReq accesses 707system.cpu0.dcache.SoftPFReq_miss_rate::total 0.684486 # miss rate for SoftPFReq accesses 708system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.747073 # miss rate for WriteLineReq accesses 709system.cpu0.dcache.WriteLineReq_miss_rate::total 0.747073 # miss rate for WriteLineReq accesses 710system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.084613 # miss rate for LoadLockedReq accesses 711system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.084613 # miss rate for LoadLockedReq accesses 712system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097865 # miss rate for StoreCondReq accesses 713system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097865 # miss rate for StoreCondReq accesses |
| 714system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036104 # miss rate for demand accesses 715system.cpu0.dcache.demand_miss_rate::total 0.036104 # miss rate for demand accesses 716system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039761 # miss rate for overall accesses 717system.cpu0.dcache.overall_miss_rate::total 0.039761 # miss rate for overall accesses | 714system.cpu0.dcache.demand_miss_rate::cpu0.data 0.040807 # miss rate for demand accesses 715system.cpu0.dcache.demand_miss_rate::total 0.040807 # miss rate for demand accesses 716system.cpu0.dcache.overall_miss_rate::cpu0.data 0.044414 # miss rate for overall accesses 717system.cpu0.dcache.overall_miss_rate::total 0.044414 # miss rate for overall accesses |
| 718system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17362.374870 # average ReadReq miss latency 719system.cpu0.dcache.ReadReq_avg_miss_latency::total 17362.374870 # average ReadReq miss latency 720system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25220.074587 # average WriteReq miss latency 721system.cpu0.dcache.WriteReq_avg_miss_latency::total 25220.074587 # average WriteReq miss latency 722system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 60346.652640 # average WriteLineReq miss latency 723system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 60346.652640 # average WriteLineReq miss latency 724system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16484.243098 # average LoadLockedReq miss latency 725system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16484.243098 # average LoadLockedReq miss latency 726system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28412.814058 # average StoreCondReq miss latency 727system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28412.814058 # average StoreCondReq miss latency 728system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 729system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 718system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17362.374870 # average ReadReq miss latency 719system.cpu0.dcache.ReadReq_avg_miss_latency::total 17362.374870 # average ReadReq miss latency 720system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 25220.074587 # average WriteReq miss latency 721system.cpu0.dcache.WriteReq_avg_miss_latency::total 25220.074587 # average WriteReq miss latency 722system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 60346.652640 # average WriteLineReq miss latency 723system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 60346.652640 # average WriteLineReq miss latency 724system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16484.243098 # average LoadLockedReq miss latency 725system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16484.243098 # average LoadLockedReq miss latency 726system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28412.814058 # average StoreCondReq miss latency 727system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28412.814058 # average StoreCondReq miss latency 728system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 729system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 730system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20503.917074 # average overall miss latency 731system.cpu0.dcache.demand_avg_miss_latency::total 20503.917074 # average overall miss latency 732system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18513.062199 # average overall miss latency 733system.cpu0.dcache.overall_avg_miss_latency::total 18513.062199 # average overall miss latency | 730system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25328.955369 # average overall miss latency 731system.cpu0.dcache.demand_avg_miss_latency::total 25328.955369 # average overall miss latency 732system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23141.720496 # average overall miss latency 733system.cpu0.dcache.overall_avg_miss_latency::total 23141.720496 # average overall miss latency |
| 734system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 735system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 736system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 737system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 738system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 739system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 734system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 735system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 736system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 737system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 738system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 739system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 740system.cpu0.dcache.fast_writes 0 # number of fast writes performed 741system.cpu0.dcache.cache_copies 0 # number of cache copies performed | |
| 742system.cpu0.dcache.writebacks::writebacks 5972043 # number of writebacks 743system.cpu0.dcache.writebacks::total 5972043 # number of writebacks 744system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 444932 # number of ReadReq MSHR hits 745system.cpu0.dcache.ReadReq_mshr_hits::total 444932 # number of ReadReq MSHR hits 746system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1012331 # number of WriteReq MSHR hits 747system.cpu0.dcache.WriteReq_mshr_hits::total 1012331 # number of WriteReq MSHR hits 748system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 90 # number of WriteLineReq MSHR hits 749system.cpu0.dcache.WriteLineReq_mshr_hits::total 90 # number of WriteLineReq MSHR hits 750system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 46565 # number of LoadLockedReq MSHR hits 751system.cpu0.dcache.LoadLockedReq_mshr_hits::total 46565 # number of LoadLockedReq MSHR hits 752system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 65 # number of StoreCondReq MSHR hits 753system.cpu0.dcache.StoreCondReq_mshr_hits::total 65 # number of StoreCondReq MSHR hits | 740system.cpu0.dcache.writebacks::writebacks 5972043 # number of writebacks 741system.cpu0.dcache.writebacks::total 5972043 # number of writebacks 742system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 444932 # number of ReadReq MSHR hits 743system.cpu0.dcache.ReadReq_mshr_hits::total 444932 # number of ReadReq MSHR hits 744system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1012331 # number of WriteReq MSHR hits 745system.cpu0.dcache.WriteReq_mshr_hits::total 1012331 # number of WriteReq MSHR hits 746system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 90 # number of WriteLineReq MSHR hits 747system.cpu0.dcache.WriteLineReq_mshr_hits::total 90 # number of WriteLineReq MSHR hits 748system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 46565 # number of LoadLockedReq MSHR hits 749system.cpu0.dcache.LoadLockedReq_mshr_hits::total 46565 # number of LoadLockedReq MSHR hits 750system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 65 # number of StoreCondReq MSHR hits 751system.cpu0.dcache.StoreCondReq_mshr_hits::total 65 # number of StoreCondReq MSHR hits |
| 754system.cpu0.dcache.demand_mshr_hits::cpu0.data 1457263 # number of demand (read+write) MSHR hits 755system.cpu0.dcache.demand_mshr_hits::total 1457263 # number of demand (read+write) MSHR hits 756system.cpu0.dcache.overall_mshr_hits::cpu0.data 1457263 # number of overall MSHR hits 757system.cpu0.dcache.overall_mshr_hits::total 1457263 # number of overall MSHR hits | 752system.cpu0.dcache.demand_mshr_hits::cpu0.data 1457353 # number of demand (read+write) MSHR hits 753system.cpu0.dcache.demand_mshr_hits::total 1457353 # number of demand (read+write) MSHR hits 754system.cpu0.dcache.overall_mshr_hits::cpu0.data 1457353 # number of overall MSHR hits 755system.cpu0.dcache.overall_mshr_hits::total 1457353 # number of overall MSHR hits |
| 758system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3248416 # number of ReadReq MSHR misses 759system.cpu0.dcache.ReadReq_mshr_misses::total 3248416 # number of ReadReq MSHR misses 760system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1447894 # number of WriteReq MSHR misses 761system.cpu0.dcache.WriteReq_mshr_misses::total 1447894 # number of WriteReq MSHR misses 762system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 660170 # number of SoftPFReq MSHR misses 763system.cpu0.dcache.SoftPFReq_mshr_misses::total 660170 # number of SoftPFReq MSHR misses 764system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 847802 # number of WriteLineReq MSHR misses 765system.cpu0.dcache.WriteLineReq_mshr_misses::total 847802 # number of WriteLineReq MSHR misses 766system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 126978 # number of LoadLockedReq MSHR misses 767system.cpu0.dcache.LoadLockedReq_mshr_misses::total 126978 # number of LoadLockedReq MSHR misses 768system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200535 # number of StoreCondReq MSHR misses 769system.cpu0.dcache.StoreCondReq_mshr_misses::total 200535 # number of StoreCondReq MSHR misses | 756system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3248416 # number of ReadReq MSHR misses 757system.cpu0.dcache.ReadReq_mshr_misses::total 3248416 # number of ReadReq MSHR misses 758system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1447894 # number of WriteReq MSHR misses 759system.cpu0.dcache.WriteReq_mshr_misses::total 1447894 # number of WriteReq MSHR misses 760system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 660170 # number of SoftPFReq MSHR misses 761system.cpu0.dcache.SoftPFReq_mshr_misses::total 660170 # number of SoftPFReq MSHR misses 762system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 847802 # number of WriteLineReq MSHR misses 763system.cpu0.dcache.WriteLineReq_mshr_misses::total 847802 # number of WriteLineReq MSHR misses 764system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 126978 # number of LoadLockedReq MSHR misses 765system.cpu0.dcache.LoadLockedReq_mshr_misses::total 126978 # number of LoadLockedReq MSHR misses 766system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200535 # number of StoreCondReq MSHR misses 767system.cpu0.dcache.StoreCondReq_mshr_misses::total 200535 # number of StoreCondReq MSHR misses |
| 770system.cpu0.dcache.demand_mshr_misses::cpu0.data 4696310 # number of demand (read+write) MSHR misses 771system.cpu0.dcache.demand_mshr_misses::total 4696310 # number of demand (read+write) MSHR misses 772system.cpu0.dcache.overall_mshr_misses::cpu0.data 5356480 # number of overall MSHR misses 773system.cpu0.dcache.overall_mshr_misses::total 5356480 # number of overall MSHR misses | 768system.cpu0.dcache.demand_mshr_misses::cpu0.data 5544112 # number of demand (read+write) MSHR misses 769system.cpu0.dcache.demand_mshr_misses::total 5544112 # number of demand (read+write) MSHR misses 770system.cpu0.dcache.overall_mshr_misses::cpu0.data 6204282 # number of overall MSHR misses 771system.cpu0.dcache.overall_mshr_misses::total 6204282 # number of overall MSHR misses |
| 774system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31552 # number of ReadReq MSHR uncacheable 775system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31552 # number of ReadReq MSHR uncacheable 776system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31148 # number of WriteReq MSHR uncacheable 777system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31148 # number of WriteReq MSHR uncacheable 778system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62700 # number of overall MSHR uncacheable misses 779system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62700 # number of overall MSHR uncacheable misses 780system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50756784000 # number of ReadReq MSHR miss cycles 781system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50756784000 # number of ReadReq MSHR miss cycles --- 4 unchanged lines hidden (view full) --- 786system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 50311370000 # number of WriteLineReq MSHR miss cycles 787system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 50311370000 # number of WriteLineReq MSHR miss cycles 788system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1783759500 # number of LoadLockedReq MSHR miss cycles 789system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1783759500 # number of LoadLockedReq MSHR miss cycles 790system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5494928000 # number of StoreCondReq MSHR miss cycles 791system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5494928000 # number of StoreCondReq MSHR miss cycles 792system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5416500 # number of StoreCondFailReq MSHR miss cycles 793system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5416500 # number of StoreCondFailReq MSHR miss cycles | 772system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31552 # number of ReadReq MSHR uncacheable 773system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31552 # number of ReadReq MSHR uncacheable 774system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31148 # number of WriteReq MSHR uncacheable 775system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31148 # number of WriteReq MSHR uncacheable 776system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 62700 # number of overall MSHR uncacheable misses 777system.cpu0.dcache.overall_mshr_uncacheable_misses::total 62700 # number of overall MSHR uncacheable misses 778system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 50756784000 # number of ReadReq MSHR miss cycles 779system.cpu0.dcache.ReadReq_mshr_miss_latency::total 50756784000 # number of ReadReq MSHR miss cycles --- 4 unchanged lines hidden (view full) --- 784system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 50311370000 # number of WriteLineReq MSHR miss cycles 785system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 50311370000 # number of WriteLineReq MSHR miss cycles 786system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1783759500 # number of LoadLockedReq MSHR miss cycles 787system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1783759500 # number of LoadLockedReq MSHR miss cycles 788system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5494928000 # number of StoreCondReq MSHR miss cycles 789system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5494928000 # number of StoreCondReq MSHR miss cycles 790system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5416500 # number of StoreCondFailReq MSHR miss cycles 791system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5416500 # number of StoreCondFailReq MSHR miss cycles |
| 794system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 87107602500 # number of demand (read+write) MSHR miss cycles 795system.cpu0.dcache.demand_mshr_miss_latency::total 87107602500 # number of demand (read+write) MSHR miss cycles 796system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103687036000 # number of overall MSHR miss cycles 797system.cpu0.dcache.overall_mshr_miss_latency::total 103687036000 # number of overall MSHR miss cycles | 792system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 137418972500 # number of demand (read+write) MSHR miss cycles 793system.cpu0.dcache.demand_mshr_miss_latency::total 137418972500 # number of demand (read+write) MSHR miss cycles 794system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 153998406000 # number of overall MSHR miss cycles 795system.cpu0.dcache.overall_mshr_miss_latency::total 153998406000 # number of overall MSHR miss cycles |
| 798system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6041391000 # number of ReadReq MSHR uncacheable cycles 799system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6041391000 # number of ReadReq MSHR uncacheable cycles | 796system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6041391000 # number of ReadReq MSHR uncacheable cycles 797system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6041391000 # number of ReadReq MSHR uncacheable cycles |
| 800system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5837295500 # number of WriteReq MSHR uncacheable cycles 801system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5837295500 # number of WriteReq MSHR uncacheable cycles 802system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11878686500 # number of overall MSHR uncacheable cycles 803system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11878686500 # number of overall MSHR uncacheable cycles | 798system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6041391000 # number of overall MSHR uncacheable cycles 799system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6041391000 # number of overall MSHR uncacheable cycles |
| 804system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035800 # mshr miss rate for ReadReq accesses 805system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035800 # mshr miss rate for ReadReq accesses 806system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018166 # mshr miss rate for WriteReq accesses 807system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018166 # mshr miss rate for WriteReq accesses 808system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.682860 # mshr miss rate for SoftPFReq accesses 809system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.682860 # mshr miss rate for SoftPFReq accesses 810system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746994 # mshr miss rate for WriteLineReq accesses 811system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746994 # mshr miss rate for WriteLineReq accesses 812system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061910 # mshr miss rate for LoadLockedReq accesses 813system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061910 # mshr miss rate for LoadLockedReq accesses 814system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097833 # mshr miss rate for StoreCondReq accesses 815system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097833 # mshr miss rate for StoreCondReq accesses | 800system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035800 # mshr miss rate for ReadReq accesses 801system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035800 # mshr miss rate for ReadReq accesses 802system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018166 # mshr miss rate for WriteReq accesses 803system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018166 # mshr miss rate for WriteReq accesses 804system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.682860 # mshr miss rate for SoftPFReq accesses 805system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.682860 # mshr miss rate for SoftPFReq accesses 806system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.746994 # mshr miss rate for WriteLineReq accesses 807system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.746994 # mshr miss rate for WriteLineReq accesses 808system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061910 # mshr miss rate for LoadLockedReq accesses 809system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061910 # mshr miss rate for LoadLockedReq accesses 810system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097833 # mshr miss rate for StoreCondReq accesses 811system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097833 # mshr miss rate for StoreCondReq accesses |
| 816system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027554 # mshr miss rate for demand accesses 817system.cpu0.dcache.demand_mshr_miss_rate::total 0.027554 # mshr miss rate for demand accesses 818system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031250 # mshr miss rate for overall accesses 819system.cpu0.dcache.overall_mshr_miss_rate::total 0.031250 # mshr miss rate for overall accesses | 812system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032313 # mshr miss rate for demand accesses 813system.cpu0.dcache.demand_mshr_miss_rate::total 0.032313 # mshr miss rate for demand accesses 814system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.035958 # mshr miss rate for overall accesses 815system.cpu0.dcache.overall_mshr_miss_rate::total 0.035958 # mshr miss rate for overall accesses |
| 820system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15625.087427 # average ReadReq mshr miss latency 821system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15625.087427 # average ReadReq mshr miss latency 822system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25105.994292 # average WriteReq mshr miss latency 823system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25105.994292 # average WriteReq mshr miss latency 824system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25113.885060 # average SoftPFReq mshr miss latency 825system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25113.885060 # average SoftPFReq mshr miss latency 826system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 59343.301856 # average WriteLineReq mshr miss latency 827system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 59343.301856 # average WriteLineReq mshr miss latency 828system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14047.783868 # average LoadLockedReq mshr miss latency 829system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14047.783868 # average LoadLockedReq mshr miss latency 830system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27401.341412 # average StoreCondReq mshr miss latency 831system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27401.341412 # average StoreCondReq mshr miss latency 832system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 833system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 816system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15625.087427 # average ReadReq mshr miss latency 817system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15625.087427 # average ReadReq mshr miss latency 818system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25105.994292 # average WriteReq mshr miss latency 819system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25105.994292 # average WriteReq mshr miss latency 820system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25113.885060 # average SoftPFReq mshr miss latency 821system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25113.885060 # average SoftPFReq mshr miss latency 822system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 59343.301856 # average WriteLineReq mshr miss latency 823system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 59343.301856 # average WriteLineReq mshr miss latency 824system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14047.783868 # average LoadLockedReq mshr miss latency 825system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14047.783868 # average LoadLockedReq mshr miss latency 826system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27401.341412 # average StoreCondReq mshr miss latency 827system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27401.341412 # average StoreCondReq mshr miss latency 828system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 829system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 834system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18548.094674 # average overall mshr miss latency 835system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18548.094674 # average overall mshr miss latency 836system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19357.308531 # average overall mshr miss latency 837system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19357.308531 # average overall mshr miss latency | 830system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24786.471215 # average overall mshr miss latency 831system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24786.471215 # average overall mshr miss latency 832system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24821.309863 # average overall mshr miss latency 833system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24821.309863 # average overall mshr miss latency |
| 838system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191474.106237 # average ReadReq mshr uncacheable latency 839system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191474.106237 # average ReadReq mshr uncacheable latency | 834system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191474.106237 # average ReadReq mshr uncacheable latency 835system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191474.106237 # average ReadReq mshr uncacheable latency |
| 840system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187405.146398 # average WriteReq mshr uncacheable latency 841system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187405.146398 # average WriteReq mshr uncacheable latency 842system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189452.735247 # average overall mshr uncacheable latency 843system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 189452.735247 # average overall mshr uncacheable latency 844system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 836system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96353.923445 # average overall mshr uncacheable latency 837system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96353.923445 # average overall mshr uncacheable latency |
| 845system.cpu0.icache.tags.replacements 10516028 # number of replacements 846system.cpu0.icache.tags.tagsinuse 511.897153 # Cycle average of tags in use 847system.cpu0.icache.tags.total_refs 249911266 # Total number of references to valid blocks. 848system.cpu0.icache.tags.sampled_refs 10516540 # Sample count of references to valid blocks. 849system.cpu0.icache.tags.avg_refs 23.763640 # Average number of references to valid blocks. 850system.cpu0.icache.tags.warmup_cycle 33054279000 # Cycle when the warmup percentage was hit. 851system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.897153 # Average occupied blocks per requestor 852system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999799 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 895system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10410.384965 # average overall miss latency 896system.cpu0.icache.overall_avg_miss_latency::total 10410.384965 # average overall miss latency 897system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 898system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 899system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 900system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 901system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 902system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 838system.cpu0.icache.tags.replacements 10516028 # number of replacements 839system.cpu0.icache.tags.tagsinuse 511.897153 # Cycle average of tags in use 840system.cpu0.icache.tags.total_refs 249911266 # Total number of references to valid blocks. 841system.cpu0.icache.tags.sampled_refs 10516540 # Sample count of references to valid blocks. 842system.cpu0.icache.tags.avg_refs 23.763640 # Average number of references to valid blocks. 843system.cpu0.icache.tags.warmup_cycle 33054279000 # Cycle when the warmup percentage was hit. 844system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.897153 # Average occupied blocks per requestor 845system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999799 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 888system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10410.384965 # average overall miss latency 889system.cpu0.icache.overall_avg_miss_latency::total 10410.384965 # average overall miss latency 890system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 891system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 892system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 893system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 894system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 895system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 903system.cpu0.icache.fast_writes 0 # number of fast writes performed 904system.cpu0.icache.cache_copies 0 # number of cache copies performed | |
| 905system.cpu0.icache.writebacks::writebacks 10516028 # number of writebacks 906system.cpu0.icache.writebacks::total 10516028 # number of writebacks 907system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10516550 # number of ReadReq MSHR misses 908system.cpu0.icache.ReadReq_mshr_misses::total 10516550 # number of ReadReq MSHR misses 909system.cpu0.icache.demand_mshr_misses::cpu0.inst 10516550 # number of demand (read+write) MSHR misses 910system.cpu0.icache.demand_mshr_misses::total 10516550 # number of demand (read+write) MSHR misses 911system.cpu0.icache.overall_mshr_misses::cpu0.inst 10516550 # number of overall MSHR misses 912system.cpu0.icache.overall_mshr_misses::total 10516550 # number of overall MSHR misses --- 22 unchanged lines hidden (view full) --- 935system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9910.385012 # average overall mshr miss latency 936system.cpu0.icache.demand_avg_mshr_miss_latency::total 9910.385012 # average overall mshr miss latency 937system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9910.385012 # average overall mshr miss latency 938system.cpu0.icache.overall_avg_mshr_miss_latency::total 9910.385012 # average overall mshr miss latency 939system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency 940system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency 941system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency 942system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency | 896system.cpu0.icache.writebacks::writebacks 10516028 # number of writebacks 897system.cpu0.icache.writebacks::total 10516028 # number of writebacks 898system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10516550 # number of ReadReq MSHR misses 899system.cpu0.icache.ReadReq_mshr_misses::total 10516550 # number of ReadReq MSHR misses 900system.cpu0.icache.demand_mshr_misses::cpu0.inst 10516550 # number of demand (read+write) MSHR misses 901system.cpu0.icache.demand_mshr_misses::total 10516550 # number of demand (read+write) MSHR misses 902system.cpu0.icache.overall_mshr_misses::cpu0.inst 10516550 # number of overall MSHR misses 903system.cpu0.icache.overall_mshr_misses::total 10516550 # number of overall MSHR misses --- 22 unchanged lines hidden (view full) --- 926system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9910.385012 # average overall mshr miss latency 927system.cpu0.icache.demand_avg_mshr_miss_latency::total 9910.385012 # average overall mshr miss latency 928system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9910.385012 # average overall mshr miss latency 929system.cpu0.icache.overall_avg_mshr_miss_latency::total 9910.385012 # average overall mshr miss latency 930system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average ReadReq mshr uncacheable latency 931system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 141746.678392 # average ReadReq mshr uncacheable latency 932system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141746.678392 # average overall mshr uncacheable latency 933system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141746.678392 # average overall mshr uncacheable latency |
| 943system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 944system.cpu0.l2cache.prefetcher.num_hwpf_issued 8036343 # number of hwpf issued 945system.cpu0.l2cache.prefetcher.pfIdentified 8037705 # number of prefetch candidates identified 946system.cpu0.l2cache.prefetcher.pfBufferHit 1205 # number of redundant prefetches already in prefetch queue 947system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 948system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 949system.cpu0.l2cache.prefetcher.pfSpanPage 1038823 # number of prefetches not generated due to page crossing 950system.cpu0.l2cache.tags.replacements 2850300 # number of replacements 951system.cpu0.l2cache.tags.tagsinuse 16126.746563 # Cycle average of tags in use --- 201 unchanged lines hidden (view full) --- 1153system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 47360.581612 # average overall miss latency 1154system.cpu0.l2cache.overall_avg_miss_latency::total 44387.760222 # average overall miss latency 1155system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1156system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1157system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1158system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1159system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1160system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 934system.cpu0.l2cache.prefetcher.num_hwpf_issued 8036343 # number of hwpf issued 935system.cpu0.l2cache.prefetcher.pfIdentified 8037705 # number of prefetch candidates identified 936system.cpu0.l2cache.prefetcher.pfBufferHit 1205 # number of redundant prefetches already in prefetch queue 937system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 938system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 939system.cpu0.l2cache.prefetcher.pfSpanPage 1038823 # number of prefetches not generated due to page crossing 940system.cpu0.l2cache.tags.replacements 2850300 # number of replacements 941system.cpu0.l2cache.tags.tagsinuse 16126.746563 # Cycle average of tags in use --- 201 unchanged lines hidden (view full) --- 1143system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 47360.581612 # average overall miss latency 1144system.cpu0.l2cache.overall_avg_miss_latency::total 44387.760222 # average overall miss latency 1145system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1146system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1147system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1148system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1149system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1150system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1161system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1162system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | |
| 1163system.cpu0.l2cache.unused_prefetches 49728 # number of HardPF blocks evicted w/o reference 1164system.cpu0.l2cache.writebacks::writebacks 1630983 # number of writebacks 1165system.cpu0.l2cache.writebacks::total 1630983 # number of writebacks 1166system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 1167system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 2 # number of ReadReq MSHR hits 1168system.cpu0.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 1169system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9619 # number of ReadExReq MSHR hits 1170system.cpu0.l2cache.ReadExReq_mshr_hits::total 9619 # number of ReadExReq MSHR hits --- 79 unchanged lines hidden (view full) --- 1250system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 317581000 # number of overall MSHR miss cycles 1251system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 24933652500 # number of overall MSHR miss cycles 1252system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 52594206483 # number of overall MSHR miss cycles 1253system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 46297805758 # number of overall MSHR miss cycles 1254system.cpu0.l2cache.overall_mshr_miss_latency::total 124548471241 # number of overall MSHR miss cycles 1255system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of ReadReq MSHR uncacheable cycles 1256system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5788797000 # number of ReadReq MSHR uncacheable cycles 1257system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 12784952000 # number of ReadReq MSHR uncacheable cycles | 1151system.cpu0.l2cache.unused_prefetches 49728 # number of HardPF blocks evicted w/o reference 1152system.cpu0.l2cache.writebacks::writebacks 1630983 # number of writebacks 1153system.cpu0.l2cache.writebacks::total 1630983 # number of writebacks 1154system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 1155system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 2 # number of ReadReq MSHR hits 1156system.cpu0.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 1157system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9619 # number of ReadExReq MSHR hits 1158system.cpu0.l2cache.ReadExReq_mshr_hits::total 9619 # number of ReadExReq MSHR hits --- 79 unchanged lines hidden (view full) --- 1238system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 317581000 # number of overall MSHR miss cycles 1239system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 24933652500 # number of overall MSHR miss cycles 1240system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 52594206483 # number of overall MSHR miss cycles 1241system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 46297805758 # number of overall MSHR miss cycles 1242system.cpu0.l2cache.overall_mshr_miss_latency::total 124548471241 # number of overall MSHR miss cycles 1243system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of ReadReq MSHR uncacheable cycles 1244system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5788797000 # number of ReadReq MSHR uncacheable cycles 1245system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 12784952000 # number of ReadReq MSHR uncacheable cycles |
| 1258system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5603650500 # number of WriteReq MSHR uncacheable cycles 1259system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5603650500 # number of WriteReq MSHR uncacheable cycles | |
| 1260system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles | 1246system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6996155000 # number of overall MSHR uncacheable cycles |
| 1261system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11392447500 # number of overall MSHR uncacheable cycles 1262system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 18388602500 # number of overall MSHR uncacheable cycles | 1247system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5788797000 # number of overall MSHR uncacheable cycles 1248system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12784952000 # number of overall MSHR uncacheable cycles |
| 1263system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020389 # mshr miss rate for ReadReq accesses 1264system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045776 # mshr miss rate for ReadReq accesses 1265system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.026408 # mshr miss rate for ReadReq accesses 1266system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 1267system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses 1268system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1269system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1270system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998585 # mshr miss rate for UpgradeReq accesses --- 49 unchanged lines hidden (view full) --- 1320system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average overall mshr miss latency 1321system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average overall mshr miss latency 1322system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40568.708271 # average overall mshr miss latency 1323system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56710.263890 # average overall mshr miss latency 1324system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43209.493938 # average overall mshr miss latency 1325system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency 1326system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183468.464757 # average ReadReq mshr uncacheable latency 1327system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152454.084735 # average ReadReq mshr uncacheable latency | 1249system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020389 # mshr miss rate for ReadReq accesses 1250system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045776 # mshr miss rate for ReadReq accesses 1251system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.026408 # mshr miss rate for ReadReq accesses 1252system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 1253system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses 1254system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1255system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1256system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.998585 # mshr miss rate for UpgradeReq accesses --- 49 unchanged lines hidden (view full) --- 1306system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 38383.007010 # average overall mshr miss latency 1307system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33267.758218 # average overall mshr miss latency 1308system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 40568.708271 # average overall mshr miss latency 1309system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56710.263890 # average overall mshr miss latency 1310system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 43209.493938 # average overall mshr miss latency 1311system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average ReadReq mshr uncacheable latency 1312system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183468.464757 # average ReadReq mshr uncacheable latency 1313system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 152454.084735 # average ReadReq mshr uncacheable latency |
| 1328system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179904.022730 # average WriteReq mshr uncacheable latency 1329system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 179904.022730 # average WriteReq mshr uncacheable latency | |
| 1330system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency | 1314system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133746.678392 # average overall mshr uncacheable latency |
| 1331system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181697.727273 # average overall mshr uncacheable latency 1332system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 159888.378301 # average overall mshr uncacheable latency 1333system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1315system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92325.311005 # average overall mshr uncacheable latency 1316system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 111164.795799 # average overall mshr uncacheable latency |
| 1334system.cpu0.toL2Bus.snoop_filter.tot_requests 33857668 # Total number of requests made to the snoop filter. 1335system.cpu0.toL2Bus.snoop_filter.hit_single_requests 17264460 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1336system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3128 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1337system.cpu0.toL2Bus.snoop_filter.tot_snoops 2263959 # Total number of snoops made to the snoop filter. 1338system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2263472 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1339system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 487 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1340system.cpu0.toL2Bus.trans_dist::ReadReq 924227 # Transaction distribution 1341system.cpu0.toL2Bus.trans_dist::ReadResp 15578589 # Transaction distribution --- 306 unchanged lines hidden (view full) --- 1648system.cpu1.dcache.SoftPFReq_hits::cpu1.data 200864 # number of SoftPFReq hits 1649system.cpu1.dcache.SoftPFReq_hits::total 200864 # number of SoftPFReq hits 1650system.cpu1.dcache.WriteLineReq_hits::cpu1.data 33950 # number of WriteLineReq hits 1651system.cpu1.dcache.WriteLineReq_hits::total 33950 # number of WriteLineReq hits 1652system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1678906 # number of LoadLockedReq hits 1653system.cpu1.dcache.LoadLockedReq_hits::total 1678906 # number of LoadLockedReq hits 1654system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1638259 # number of StoreCondReq hits 1655system.cpu1.dcache.StoreCondReq_hits::total 1638259 # number of StoreCondReq hits | 1317system.cpu0.toL2Bus.snoop_filter.tot_requests 33857668 # Total number of requests made to the snoop filter. 1318system.cpu0.toL2Bus.snoop_filter.hit_single_requests 17264460 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1319system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 3128 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1320system.cpu0.toL2Bus.snoop_filter.tot_snoops 2263959 # Total number of snoops made to the snoop filter. 1321system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2263472 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1322system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 487 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1323system.cpu0.toL2Bus.trans_dist::ReadReq 924227 # Transaction distribution 1324system.cpu0.toL2Bus.trans_dist::ReadResp 15578589 # Transaction distribution --- 306 unchanged lines hidden (view full) --- 1631system.cpu1.dcache.SoftPFReq_hits::cpu1.data 200864 # number of SoftPFReq hits 1632system.cpu1.dcache.SoftPFReq_hits::total 200864 # number of SoftPFReq hits 1633system.cpu1.dcache.WriteLineReq_hits::cpu1.data 33950 # number of WriteLineReq hits 1634system.cpu1.dcache.WriteLineReq_hits::total 33950 # number of WriteLineReq hits 1635system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1678906 # number of LoadLockedReq hits 1636system.cpu1.dcache.LoadLockedReq_hits::total 1678906 # number of LoadLockedReq hits 1637system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1638259 # number of StoreCondReq hits 1638system.cpu1.dcache.StoreCondReq_hits::total 1638259 # number of StoreCondReq hits |
| 1656system.cpu1.dcache.demand_hits::cpu1.data 139703423 # number of demand (read+write) hits 1657system.cpu1.dcache.demand_hits::total 139703423 # number of demand (read+write) hits 1658system.cpu1.dcache.overall_hits::cpu1.data 139904287 # number of overall hits 1659system.cpu1.dcache.overall_hits::total 139904287 # number of overall hits | 1639system.cpu1.dcache.demand_hits::cpu1.data 139737373 # number of demand (read+write) hits 1640system.cpu1.dcache.demand_hits::total 139737373 # number of demand (read+write) hits 1641system.cpu1.dcache.overall_hits::cpu1.data 139938237 # number of overall hits 1642system.cpu1.dcache.overall_hits::total 139938237 # number of overall hits |
| 1660system.cpu1.dcache.ReadReq_misses::cpu1.data 3193197 # number of ReadReq misses 1661system.cpu1.dcache.ReadReq_misses::total 3193197 # number of ReadReq misses 1662system.cpu1.dcache.WriteReq_misses::cpu1.data 2277873 # number of WriteReq misses 1663system.cpu1.dcache.WriteReq_misses::total 2277873 # number of WriteReq misses 1664system.cpu1.dcache.SoftPFReq_misses::cpu1.data 648992 # number of SoftPFReq misses 1665system.cpu1.dcache.SoftPFReq_misses::total 648992 # number of SoftPFReq misses 1666system.cpu1.dcache.WriteLineReq_misses::cpu1.data 409957 # number of WriteLineReq misses 1667system.cpu1.dcache.WriteLineReq_misses::total 409957 # number of WriteLineReq misses 1668system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 159945 # number of LoadLockedReq misses 1669system.cpu1.dcache.LoadLockedReq_misses::total 159945 # number of LoadLockedReq misses 1670system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199493 # number of StoreCondReq misses 1671system.cpu1.dcache.StoreCondReq_misses::total 199493 # number of StoreCondReq misses | 1643system.cpu1.dcache.ReadReq_misses::cpu1.data 3193197 # number of ReadReq misses 1644system.cpu1.dcache.ReadReq_misses::total 3193197 # number of ReadReq misses 1645system.cpu1.dcache.WriteReq_misses::cpu1.data 2277873 # number of WriteReq misses 1646system.cpu1.dcache.WriteReq_misses::total 2277873 # number of WriteReq misses 1647system.cpu1.dcache.SoftPFReq_misses::cpu1.data 648992 # number of SoftPFReq misses 1648system.cpu1.dcache.SoftPFReq_misses::total 648992 # number of SoftPFReq misses 1649system.cpu1.dcache.WriteLineReq_misses::cpu1.data 409957 # number of WriteLineReq misses 1650system.cpu1.dcache.WriteLineReq_misses::total 409957 # number of WriteLineReq misses 1651system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 159945 # number of LoadLockedReq misses 1652system.cpu1.dcache.LoadLockedReq_misses::total 159945 # number of LoadLockedReq misses 1653system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199493 # number of StoreCondReq misses 1654system.cpu1.dcache.StoreCondReq_misses::total 199493 # number of StoreCondReq misses |
| 1672system.cpu1.dcache.demand_misses::cpu1.data 5471070 # number of demand (read+write) misses 1673system.cpu1.dcache.demand_misses::total 5471070 # number of demand (read+write) misses 1674system.cpu1.dcache.overall_misses::cpu1.data 6120062 # number of overall misses 1675system.cpu1.dcache.overall_misses::total 6120062 # number of overall misses | 1655system.cpu1.dcache.demand_misses::cpu1.data 5881027 # number of demand (read+write) misses 1656system.cpu1.dcache.demand_misses::total 5881027 # number of demand (read+write) misses 1657system.cpu1.dcache.overall_misses::cpu1.data 6530019 # number of overall misses 1658system.cpu1.dcache.overall_misses::total 6530019 # number of overall misses |
| 1676system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 52208022500 # number of ReadReq miss cycles 1677system.cpu1.dcache.ReadReq_miss_latency::total 52208022500 # number of ReadReq miss cycles 1678system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 51224639500 # number of WriteReq miss cycles 1679system.cpu1.dcache.WriteReq_miss_latency::total 51224639500 # number of WriteReq miss cycles 1680system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 14899741000 # number of WriteLineReq miss cycles 1681system.cpu1.dcache.WriteLineReq_miss_latency::total 14899741000 # number of WriteLineReq miss cycles 1682system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2555092000 # number of LoadLockedReq miss cycles 1683system.cpu1.dcache.LoadLockedReq_miss_latency::total 2555092000 # number of LoadLockedReq miss cycles 1684system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5532212500 # number of StoreCondReq miss cycles 1685system.cpu1.dcache.StoreCondReq_miss_latency::total 5532212500 # number of StoreCondReq miss cycles 1686system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5344000 # number of StoreCondFailReq miss cycles 1687system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5344000 # number of StoreCondFailReq miss cycles | 1659system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 52208022500 # number of ReadReq miss cycles 1660system.cpu1.dcache.ReadReq_miss_latency::total 52208022500 # number of ReadReq miss cycles 1661system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 51224639500 # number of WriteReq miss cycles 1662system.cpu1.dcache.WriteReq_miss_latency::total 51224639500 # number of WriteReq miss cycles 1663system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 14899741000 # number of WriteLineReq miss cycles 1664system.cpu1.dcache.WriteLineReq_miss_latency::total 14899741000 # number of WriteLineReq miss cycles 1665system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2555092000 # number of LoadLockedReq miss cycles 1666system.cpu1.dcache.LoadLockedReq_miss_latency::total 2555092000 # number of LoadLockedReq miss cycles 1667system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5532212500 # number of StoreCondReq miss cycles 1668system.cpu1.dcache.StoreCondReq_miss_latency::total 5532212500 # number of StoreCondReq miss cycles 1669system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5344000 # number of StoreCondFailReq miss cycles 1670system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5344000 # number of StoreCondFailReq miss cycles |
| 1688system.cpu1.dcache.demand_miss_latency::cpu1.data 103432662000 # number of demand (read+write) miss cycles 1689system.cpu1.dcache.demand_miss_latency::total 103432662000 # number of demand (read+write) miss cycles 1690system.cpu1.dcache.overall_miss_latency::cpu1.data 103432662000 # number of overall miss cycles 1691system.cpu1.dcache.overall_miss_latency::total 103432662000 # number of overall miss cycles | 1671system.cpu1.dcache.demand_miss_latency::cpu1.data 118332403000 # number of demand (read+write) miss cycles 1672system.cpu1.dcache.demand_miss_latency::total 118332403000 # number of demand (read+write) miss cycles 1673system.cpu1.dcache.overall_miss_latency::cpu1.data 118332403000 # number of overall miss cycles 1674system.cpu1.dcache.overall_miss_latency::total 118332403000 # number of overall miss cycles |
| 1692system.cpu1.dcache.ReadReq_accesses::cpu1.data 76856004 # number of ReadReq accesses(hits+misses) 1693system.cpu1.dcache.ReadReq_accesses::total 76856004 # number of ReadReq accesses(hits+misses) 1694system.cpu1.dcache.WriteReq_accesses::cpu1.data 68318489 # number of WriteReq accesses(hits+misses) 1695system.cpu1.dcache.WriteReq_accesses::total 68318489 # number of WriteReq accesses(hits+misses) 1696system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 849856 # number of SoftPFReq accesses(hits+misses) 1697system.cpu1.dcache.SoftPFReq_accesses::total 849856 # number of SoftPFReq accesses(hits+misses) 1698system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 443907 # number of WriteLineReq accesses(hits+misses) 1699system.cpu1.dcache.WriteLineReq_accesses::total 443907 # number of WriteLineReq accesses(hits+misses) 1700system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1838851 # number of LoadLockedReq accesses(hits+misses) 1701system.cpu1.dcache.LoadLockedReq_accesses::total 1838851 # number of LoadLockedReq accesses(hits+misses) 1702system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1837752 # number of StoreCondReq accesses(hits+misses) 1703system.cpu1.dcache.StoreCondReq_accesses::total 1837752 # number of StoreCondReq accesses(hits+misses) | 1675system.cpu1.dcache.ReadReq_accesses::cpu1.data 76856004 # number of ReadReq accesses(hits+misses) 1676system.cpu1.dcache.ReadReq_accesses::total 76856004 # number of ReadReq accesses(hits+misses) 1677system.cpu1.dcache.WriteReq_accesses::cpu1.data 68318489 # number of WriteReq accesses(hits+misses) 1678system.cpu1.dcache.WriteReq_accesses::total 68318489 # number of WriteReq accesses(hits+misses) 1679system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 849856 # number of SoftPFReq accesses(hits+misses) 1680system.cpu1.dcache.SoftPFReq_accesses::total 849856 # number of SoftPFReq accesses(hits+misses) 1681system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 443907 # number of WriteLineReq accesses(hits+misses) 1682system.cpu1.dcache.WriteLineReq_accesses::total 443907 # number of WriteLineReq accesses(hits+misses) 1683system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1838851 # number of LoadLockedReq accesses(hits+misses) 1684system.cpu1.dcache.LoadLockedReq_accesses::total 1838851 # number of LoadLockedReq accesses(hits+misses) 1685system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1837752 # number of StoreCondReq accesses(hits+misses) 1686system.cpu1.dcache.StoreCondReq_accesses::total 1837752 # number of StoreCondReq accesses(hits+misses) |
| 1704system.cpu1.dcache.demand_accesses::cpu1.data 145174493 # number of demand (read+write) accesses 1705system.cpu1.dcache.demand_accesses::total 145174493 # number of demand (read+write) accesses 1706system.cpu1.dcache.overall_accesses::cpu1.data 146024349 # number of overall (read+write) accesses 1707system.cpu1.dcache.overall_accesses::total 146024349 # number of overall (read+write) accesses | 1687system.cpu1.dcache.demand_accesses::cpu1.data 145618400 # number of demand (read+write) accesses 1688system.cpu1.dcache.demand_accesses::total 145618400 # number of demand (read+write) accesses 1689system.cpu1.dcache.overall_accesses::cpu1.data 146468256 # number of overall (read+write) accesses 1690system.cpu1.dcache.overall_accesses::total 146468256 # number of overall (read+write) accesses |
| 1708system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041548 # miss rate for ReadReq accesses 1709system.cpu1.dcache.ReadReq_miss_rate::total 0.041548 # miss rate for ReadReq accesses 1710system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.033342 # miss rate for WriteReq accesses 1711system.cpu1.dcache.WriteReq_miss_rate::total 0.033342 # miss rate for WriteReq accesses 1712system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.763649 # miss rate for SoftPFReq accesses 1713system.cpu1.dcache.SoftPFReq_miss_rate::total 0.763649 # miss rate for SoftPFReq accesses 1714system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.923520 # miss rate for WriteLineReq accesses 1715system.cpu1.dcache.WriteLineReq_miss_rate::total 0.923520 # miss rate for WriteLineReq accesses 1716system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086981 # miss rate for LoadLockedReq accesses 1717system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086981 # miss rate for LoadLockedReq accesses 1718system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108553 # miss rate for StoreCondReq accesses 1719system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108553 # miss rate for StoreCondReq accesses | 1691system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041548 # miss rate for ReadReq accesses 1692system.cpu1.dcache.ReadReq_miss_rate::total 0.041548 # miss rate for ReadReq accesses 1693system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.033342 # miss rate for WriteReq accesses 1694system.cpu1.dcache.WriteReq_miss_rate::total 0.033342 # miss rate for WriteReq accesses 1695system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.763649 # miss rate for SoftPFReq accesses 1696system.cpu1.dcache.SoftPFReq_miss_rate::total 0.763649 # miss rate for SoftPFReq accesses 1697system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.923520 # miss rate for WriteLineReq accesses 1698system.cpu1.dcache.WriteLineReq_miss_rate::total 0.923520 # miss rate for WriteLineReq accesses 1699system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086981 # miss rate for LoadLockedReq accesses 1700system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086981 # miss rate for LoadLockedReq accesses 1701system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108553 # miss rate for StoreCondReq accesses 1702system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108553 # miss rate for StoreCondReq accesses |
| 1720system.cpu1.dcache.demand_miss_rate::cpu1.data 0.037686 # miss rate for demand accesses 1721system.cpu1.dcache.demand_miss_rate::total 0.037686 # miss rate for demand accesses 1722system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041911 # miss rate for overall accesses 1723system.cpu1.dcache.overall_miss_rate::total 0.041911 # miss rate for overall accesses | 1703system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040387 # miss rate for demand accesses 1704system.cpu1.dcache.demand_miss_rate::total 0.040387 # miss rate for demand accesses 1705system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044583 # miss rate for overall accesses 1706system.cpu1.dcache.overall_miss_rate::total 0.044583 # miss rate for overall accesses |
| 1724system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16349.765611 # average ReadReq miss latency 1725system.cpu1.dcache.ReadReq_avg_miss_latency::total 16349.765611 # average ReadReq miss latency 1726system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22487.926017 # average WriteReq miss latency 1727system.cpu1.dcache.WriteReq_avg_miss_latency::total 22487.926017 # average WriteReq miss latency 1728system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 36344.643463 # average WriteLineReq miss latency 1729system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 36344.643463 # average WriteLineReq miss latency 1730system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15974.816343 # average LoadLockedReq miss latency 1731system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15974.816343 # average LoadLockedReq miss latency 1732system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27731.361501 # average StoreCondReq miss latency 1733system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27731.361501 # average StoreCondReq miss latency 1734system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1735system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 1707system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16349.765611 # average ReadReq miss latency 1708system.cpu1.dcache.ReadReq_avg_miss_latency::total 16349.765611 # average ReadReq miss latency 1709system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22487.926017 # average WriteReq miss latency 1710system.cpu1.dcache.WriteReq_avg_miss_latency::total 22487.926017 # average WriteReq miss latency 1711system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 36344.643463 # average WriteLineReq miss latency 1712system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 36344.643463 # average WriteLineReq miss latency 1713system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15974.816343 # average LoadLockedReq miss latency 1714system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15974.816343 # average LoadLockedReq miss latency 1715system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27731.361501 # average StoreCondReq miss latency 1716system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27731.361501 # average StoreCondReq miss latency 1717system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1718system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 1736system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18905.380849 # average overall miss latency 1737system.cpu1.dcache.demand_avg_miss_latency::total 18905.380849 # average overall miss latency 1738system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16900.590550 # average overall miss latency 1739system.cpu1.dcache.overall_avg_miss_latency::total 16900.590550 # average overall miss latency | 1719system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20121.043995 # average overall miss latency 1720system.cpu1.dcache.demand_avg_miss_latency::total 20121.043995 # average overall miss latency 1721system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18121.295359 # average overall miss latency 1722system.cpu1.dcache.overall_avg_miss_latency::total 18121.295359 # average overall miss latency |
| 1740system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1741system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1742system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1743system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1744system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1745system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1723system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1724system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1725system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1726system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1727system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1728system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1746system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1747system.cpu1.dcache.cache_copies 0 # number of cache copies performed | |
| 1748system.cpu1.dcache.writebacks::writebacks 5011891 # number of writebacks 1749system.cpu1.dcache.writebacks::total 5011891 # number of writebacks 1750system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 367321 # number of ReadReq MSHR hits 1751system.cpu1.dcache.ReadReq_mshr_hits::total 367321 # number of ReadReq MSHR hits 1752system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 943211 # number of WriteReq MSHR hits 1753system.cpu1.dcache.WriteReq_mshr_hits::total 943211 # number of WriteReq MSHR hits 1754system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits 1755system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits 1756system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 40165 # number of LoadLockedReq MSHR hits 1757system.cpu1.dcache.LoadLockedReq_mshr_hits::total 40165 # number of LoadLockedReq MSHR hits 1758system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 85 # number of StoreCondReq MSHR hits 1759system.cpu1.dcache.StoreCondReq_mshr_hits::total 85 # number of StoreCondReq MSHR hits | 1729system.cpu1.dcache.writebacks::writebacks 5011891 # number of writebacks 1730system.cpu1.dcache.writebacks::total 5011891 # number of writebacks 1731system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 367321 # number of ReadReq MSHR hits 1732system.cpu1.dcache.ReadReq_mshr_hits::total 367321 # number of ReadReq MSHR hits 1733system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 943211 # number of WriteReq MSHR hits 1734system.cpu1.dcache.WriteReq_mshr_hits::total 943211 # number of WriteReq MSHR hits 1735system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 58 # number of WriteLineReq MSHR hits 1736system.cpu1.dcache.WriteLineReq_mshr_hits::total 58 # number of WriteLineReq MSHR hits 1737system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 40165 # number of LoadLockedReq MSHR hits 1738system.cpu1.dcache.LoadLockedReq_mshr_hits::total 40165 # number of LoadLockedReq MSHR hits 1739system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 85 # number of StoreCondReq MSHR hits 1740system.cpu1.dcache.StoreCondReq_mshr_hits::total 85 # number of StoreCondReq MSHR hits |
| 1760system.cpu1.dcache.demand_mshr_hits::cpu1.data 1310532 # number of demand (read+write) MSHR hits 1761system.cpu1.dcache.demand_mshr_hits::total 1310532 # number of demand (read+write) MSHR hits 1762system.cpu1.dcache.overall_mshr_hits::cpu1.data 1310532 # number of overall MSHR hits 1763system.cpu1.dcache.overall_mshr_hits::total 1310532 # number of overall MSHR hits | 1741system.cpu1.dcache.demand_mshr_hits::cpu1.data 1310590 # number of demand (read+write) MSHR hits 1742system.cpu1.dcache.demand_mshr_hits::total 1310590 # number of demand (read+write) MSHR hits 1743system.cpu1.dcache.overall_mshr_hits::cpu1.data 1310590 # number of overall MSHR hits 1744system.cpu1.dcache.overall_mshr_hits::total 1310590 # number of overall MSHR hits |
| 1764system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2825876 # number of ReadReq MSHR misses 1765system.cpu1.dcache.ReadReq_mshr_misses::total 2825876 # number of ReadReq MSHR misses 1766system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1334662 # number of WriteReq MSHR misses 1767system.cpu1.dcache.WriteReq_mshr_misses::total 1334662 # number of WriteReq MSHR misses 1768system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 648629 # number of SoftPFReq MSHR misses 1769system.cpu1.dcache.SoftPFReq_mshr_misses::total 648629 # number of SoftPFReq MSHR misses 1770system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 409899 # number of WriteLineReq MSHR misses 1771system.cpu1.dcache.WriteLineReq_mshr_misses::total 409899 # number of WriteLineReq MSHR misses 1772system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 119780 # number of LoadLockedReq MSHR misses 1773system.cpu1.dcache.LoadLockedReq_mshr_misses::total 119780 # number of LoadLockedReq MSHR misses 1774system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199408 # number of StoreCondReq MSHR misses 1775system.cpu1.dcache.StoreCondReq_mshr_misses::total 199408 # number of StoreCondReq MSHR misses | 1745system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2825876 # number of ReadReq MSHR misses 1746system.cpu1.dcache.ReadReq_mshr_misses::total 2825876 # number of ReadReq MSHR misses 1747system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1334662 # number of WriteReq MSHR misses 1748system.cpu1.dcache.WriteReq_mshr_misses::total 1334662 # number of WriteReq MSHR misses 1749system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 648629 # number of SoftPFReq MSHR misses 1750system.cpu1.dcache.SoftPFReq_mshr_misses::total 648629 # number of SoftPFReq MSHR misses 1751system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 409899 # number of WriteLineReq MSHR misses 1752system.cpu1.dcache.WriteLineReq_mshr_misses::total 409899 # number of WriteLineReq MSHR misses 1753system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 119780 # number of LoadLockedReq MSHR misses 1754system.cpu1.dcache.LoadLockedReq_mshr_misses::total 119780 # number of LoadLockedReq MSHR misses 1755system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199408 # number of StoreCondReq MSHR misses 1756system.cpu1.dcache.StoreCondReq_mshr_misses::total 199408 # number of StoreCondReq MSHR misses |
| 1776system.cpu1.dcache.demand_mshr_misses::cpu1.data 4160538 # number of demand (read+write) MSHR misses 1777system.cpu1.dcache.demand_mshr_misses::total 4160538 # number of demand (read+write) MSHR misses 1778system.cpu1.dcache.overall_mshr_misses::cpu1.data 4809167 # number of overall MSHR misses 1779system.cpu1.dcache.overall_mshr_misses::total 4809167 # number of overall MSHR misses | 1757system.cpu1.dcache.demand_mshr_misses::cpu1.data 4570437 # number of demand (read+write) MSHR misses 1758system.cpu1.dcache.demand_mshr_misses::total 4570437 # number of demand (read+write) MSHR misses 1759system.cpu1.dcache.overall_mshr_misses::cpu1.data 5219066 # number of overall MSHR misses 1760system.cpu1.dcache.overall_mshr_misses::total 5219066 # number of overall MSHR misses |
| 1780system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7337 # number of ReadReq MSHR uncacheable 1781system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7337 # number of ReadReq MSHR uncacheable 1782system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7641 # number of WriteReq MSHR uncacheable 1783system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7641 # number of WriteReq MSHR uncacheable 1784system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14978 # number of overall MSHR uncacheable misses 1785system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14978 # number of overall MSHR uncacheable misses 1786system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41329046000 # number of ReadReq MSHR miss cycles 1787system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41329046000 # number of ReadReq MSHR miss cycles --- 4 unchanged lines hidden (view full) --- 1792system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 14484285500 # number of WriteLineReq MSHR miss cycles 1793system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 14484285500 # number of WriteLineReq MSHR miss cycles 1794system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1714801500 # number of LoadLockedReq MSHR miss cycles 1795system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1714801500 # number of LoadLockedReq MSHR miss cycles 1796system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5327664500 # number of StoreCondReq MSHR miss cycles 1797system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5327664500 # number of StoreCondReq MSHR miss cycles 1798system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4914500 # number of StoreCondFailReq MSHR miss cycles 1799system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4914500 # number of StoreCondFailReq MSHR miss cycles | 1761system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7337 # number of ReadReq MSHR uncacheable 1762system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7337 # number of ReadReq MSHR uncacheable 1763system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7641 # number of WriteReq MSHR uncacheable 1764system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7641 # number of WriteReq MSHR uncacheable 1765system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14978 # number of overall MSHR uncacheable misses 1766system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14978 # number of overall MSHR uncacheable misses 1767system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41329046000 # number of ReadReq MSHR miss cycles 1768system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41329046000 # number of ReadReq MSHR miss cycles --- 4 unchanged lines hidden (view full) --- 1773system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 14484285500 # number of WriteLineReq MSHR miss cycles 1774system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 14484285500 # number of WriteLineReq MSHR miss cycles 1775system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1714801500 # number of LoadLockedReq MSHR miss cycles 1776system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1714801500 # number of LoadLockedReq MSHR miss cycles 1777system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5327664500 # number of StoreCondReq MSHR miss cycles 1778system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5327664500 # number of StoreCondReq MSHR miss cycles 1779system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4914500 # number of StoreCondFailReq MSHR miss cycles 1780system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4914500 # number of StoreCondFailReq MSHR miss cycles |
| 1800system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 71363385000 # number of demand (read+write) MSHR miss cycles 1801system.cpu1.dcache.demand_mshr_miss_latency::total 71363385000 # number of demand (read+write) MSHR miss cycles 1802system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87278174000 # number of overall MSHR miss cycles 1803system.cpu1.dcache.overall_mshr_miss_latency::total 87278174000 # number of overall MSHR miss cycles | 1781system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 85847670500 # number of demand (read+write) MSHR miss cycles 1782system.cpu1.dcache.demand_mshr_miss_latency::total 85847670500 # number of demand (read+write) MSHR miss cycles 1783system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101762459500 # number of overall MSHR miss cycles 1784system.cpu1.dcache.overall_mshr_miss_latency::total 101762459500 # number of overall MSHR miss cycles |
| 1804system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 919733500 # number of ReadReq MSHR uncacheable cycles 1805system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 919733500 # number of ReadReq MSHR uncacheable cycles | 1785system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 919733500 # number of ReadReq MSHR uncacheable cycles 1786system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 919733500 # number of ReadReq MSHR uncacheable cycles |
| 1806system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1094820000 # number of WriteReq MSHR uncacheable cycles 1807system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1094820000 # number of WriteReq MSHR uncacheable cycles 1808system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2014553500 # number of overall MSHR uncacheable cycles 1809system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2014553500 # number of overall MSHR uncacheable cycles | 1787system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 919733500 # number of overall MSHR uncacheable cycles 1788system.cpu1.dcache.overall_mshr_uncacheable_latency::total 919733500 # number of overall MSHR uncacheable cycles |
| 1810system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036768 # mshr miss rate for ReadReq accesses 1811system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036768 # mshr miss rate for ReadReq accesses 1812system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019536 # mshr miss rate for WriteReq accesses 1813system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019536 # mshr miss rate for WriteReq accesses 1814system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.763222 # mshr miss rate for SoftPFReq accesses 1815system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.763222 # mshr miss rate for SoftPFReq accesses 1816system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.923389 # mshr miss rate for WriteLineReq accesses 1817system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.923389 # mshr miss rate for WriteLineReq accesses 1818system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065139 # mshr miss rate for LoadLockedReq accesses 1819system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065139 # mshr miss rate for LoadLockedReq accesses 1820system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108506 # mshr miss rate for StoreCondReq accesses 1821system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108506 # mshr miss rate for StoreCondReq accesses | 1789system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036768 # mshr miss rate for ReadReq accesses 1790system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036768 # mshr miss rate for ReadReq accesses 1791system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.019536 # mshr miss rate for WriteReq accesses 1792system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.019536 # mshr miss rate for WriteReq accesses 1793system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.763222 # mshr miss rate for SoftPFReq accesses 1794system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.763222 # mshr miss rate for SoftPFReq accesses 1795system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.923389 # mshr miss rate for WriteLineReq accesses 1796system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.923389 # mshr miss rate for WriteLineReq accesses 1797system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065139 # mshr miss rate for LoadLockedReq accesses 1798system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065139 # mshr miss rate for LoadLockedReq accesses 1799system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108506 # mshr miss rate for StoreCondReq accesses 1800system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108506 # mshr miss rate for StoreCondReq accesses |
| 1822system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028659 # mshr miss rate for demand accesses 1823system.cpu1.dcache.demand_mshr_miss_rate::total 0.028659 # mshr miss rate for demand accesses 1824system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032934 # mshr miss rate for overall accesses 1825system.cpu1.dcache.overall_mshr_miss_rate::total 0.032934 # mshr miss rate for overall accesses | 1801system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031386 # mshr miss rate for demand accesses 1802system.cpu1.dcache.demand_mshr_miss_rate::total 0.031386 # mshr miss rate for demand accesses 1803system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035633 # mshr miss rate for overall accesses 1804system.cpu1.dcache.overall_mshr_miss_rate::total 0.035633 # mshr miss rate for overall accesses |
| 1826system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14625.215685 # average ReadReq mshr miss latency 1827system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14625.215685 # average ReadReq mshr miss latency 1828system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22503.329682 # average WriteReq mshr miss latency 1829system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22503.329682 # average WriteReq mshr miss latency 1830system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24536.042946 # average SoftPFReq mshr miss latency 1831system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24536.042946 # average SoftPFReq mshr miss latency 1832system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 35336.230388 # average WriteLineReq mshr miss latency 1833system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 35336.230388 # average WriteLineReq mshr miss latency 1834system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14316.258975 # average LoadLockedReq mshr miss latency 1835system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14316.258975 # average LoadLockedReq mshr miss latency 1836system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26717.406022 # average StoreCondReq mshr miss latency 1837system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26717.406022 # average StoreCondReq mshr miss latency 1838system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1839system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1805system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14625.215685 # average ReadReq mshr miss latency 1806system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14625.215685 # average ReadReq mshr miss latency 1807system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22503.329682 # average WriteReq mshr miss latency 1808system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22503.329682 # average WriteReq mshr miss latency 1809system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24536.042946 # average SoftPFReq mshr miss latency 1810system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24536.042946 # average SoftPFReq mshr miss latency 1811system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 35336.230388 # average WriteLineReq mshr miss latency 1812system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 35336.230388 # average WriteLineReq mshr miss latency 1813system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14316.258975 # average LoadLockedReq mshr miss latency 1814system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14316.258975 # average LoadLockedReq mshr miss latency 1815system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26717.406022 # average StoreCondReq mshr miss latency 1816system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26717.406022 # average StoreCondReq mshr miss latency 1817system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1818system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1840system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17152.441583 # average overall mshr miss latency 1841system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17152.441583 # average overall mshr miss latency 1842system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18148.293457 # average overall mshr miss latency 1843system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18148.293457 # average overall mshr miss latency | 1819system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18783.252127 # average overall mshr miss latency 1820system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18783.252127 # average overall mshr miss latency 1821system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19498.212803 # average overall mshr miss latency 1822system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19498.212803 # average overall mshr miss latency |
| 1844system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125355.526782 # average ReadReq mshr uncacheable latency 1845system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 125355.526782 # average ReadReq mshr uncacheable latency | 1823system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 125355.526782 # average ReadReq mshr uncacheable latency 1824system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 125355.526782 # average ReadReq mshr uncacheable latency |
| 1846system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143282.292894 # average WriteReq mshr uncacheable latency 1847system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 143282.292894 # average WriteReq mshr uncacheable latency 1848system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134500.834557 # average overall mshr uncacheable latency 1849system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134500.834557 # average overall mshr uncacheable latency 1850system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1825system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 61405.628255 # average overall mshr uncacheable latency 1826system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 61405.628255 # average overall mshr uncacheable latency |
| 1851system.cpu1.icache.tags.replacements 8449872 # number of replacements 1852system.cpu1.icache.tags.tagsinuse 506.781387 # Cycle average of tags in use 1853system.cpu1.icache.tags.total_refs 217357255 # Total number of references to valid blocks. 1854system.cpu1.icache.tags.sampled_refs 8450384 # Sample count of references to valid blocks. 1855system.cpu1.icache.tags.avg_refs 25.721583 # Average number of references to valid blocks. 1856system.cpu1.icache.tags.warmup_cycle 8379180185000 # Cycle when the warmup percentage was hit. 1857system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.781387 # Average occupied blocks per requestor 1858system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989807 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 1901system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10439.359501 # average overall miss latency 1902system.cpu1.icache.overall_avg_miss_latency::total 10439.359501 # average overall miss latency 1903system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1904system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1905system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1906system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1907system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1908system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1827system.cpu1.icache.tags.replacements 8449872 # number of replacements 1828system.cpu1.icache.tags.tagsinuse 506.781387 # Cycle average of tags in use 1829system.cpu1.icache.tags.total_refs 217357255 # Total number of references to valid blocks. 1830system.cpu1.icache.tags.sampled_refs 8450384 # Sample count of references to valid blocks. 1831system.cpu1.icache.tags.avg_refs 25.721583 # Average number of references to valid blocks. 1832system.cpu1.icache.tags.warmup_cycle 8379180185000 # Cycle when the warmup percentage was hit. 1833system.cpu1.icache.tags.occ_blocks::cpu1.inst 506.781387 # Average occupied blocks per requestor 1834system.cpu1.icache.tags.occ_percent::cpu1.inst 0.989807 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 1877system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10439.359501 # average overall miss latency 1878system.cpu1.icache.overall_avg_miss_latency::total 10439.359501 # average overall miss latency 1879system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1880system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1881system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1882system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1883system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1884system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1909system.cpu1.icache.fast_writes 0 # number of fast writes performed 1910system.cpu1.icache.cache_copies 0 # number of cache copies performed | |
| 1911system.cpu1.icache.writebacks::writebacks 8449872 # number of writebacks 1912system.cpu1.icache.writebacks::total 8449872 # number of writebacks 1913system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8450384 # number of ReadReq MSHR misses 1914system.cpu1.icache.ReadReq_mshr_misses::total 8450384 # number of ReadReq MSHR misses 1915system.cpu1.icache.demand_mshr_misses::cpu1.inst 8450384 # number of demand (read+write) MSHR misses 1916system.cpu1.icache.demand_mshr_misses::total 8450384 # number of demand (read+write) MSHR misses 1917system.cpu1.icache.overall_mshr_misses::cpu1.inst 8450384 # number of overall MSHR misses 1918system.cpu1.icache.overall_mshr_misses::total 8450384 # number of overall MSHR misses --- 22 unchanged lines hidden (view full) --- 1941system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9939.359501 # average overall mshr miss latency 1942system.cpu1.icache.demand_avg_mshr_miss_latency::total 9939.359501 # average overall mshr miss latency 1943system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9939.359501 # average overall mshr miss latency 1944system.cpu1.icache.overall_avg_mshr_miss_latency::total 9939.359501 # average overall mshr miss latency 1945system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 139978.494624 # average ReadReq mshr uncacheable latency 1946system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 139978.494624 # average ReadReq mshr uncacheable latency 1947system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 139978.494624 # average overall mshr uncacheable latency 1948system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 139978.494624 # average overall mshr uncacheable latency | 1885system.cpu1.icache.writebacks::writebacks 8449872 # number of writebacks 1886system.cpu1.icache.writebacks::total 8449872 # number of writebacks 1887system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8450384 # number of ReadReq MSHR misses 1888system.cpu1.icache.ReadReq_mshr_misses::total 8450384 # number of ReadReq MSHR misses 1889system.cpu1.icache.demand_mshr_misses::cpu1.inst 8450384 # number of demand (read+write) MSHR misses 1890system.cpu1.icache.demand_mshr_misses::total 8450384 # number of demand (read+write) MSHR misses 1891system.cpu1.icache.overall_mshr_misses::cpu1.inst 8450384 # number of overall MSHR misses 1892system.cpu1.icache.overall_mshr_misses::total 8450384 # number of overall MSHR misses --- 22 unchanged lines hidden (view full) --- 1915system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9939.359501 # average overall mshr miss latency 1916system.cpu1.icache.demand_avg_mshr_miss_latency::total 9939.359501 # average overall mshr miss latency 1917system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9939.359501 # average overall mshr miss latency 1918system.cpu1.icache.overall_avg_mshr_miss_latency::total 9939.359501 # average overall mshr miss latency 1919system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 139978.494624 # average ReadReq mshr uncacheable latency 1920system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 139978.494624 # average ReadReq mshr uncacheable latency 1921system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 139978.494624 # average overall mshr uncacheable latency 1922system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 139978.494624 # average overall mshr uncacheable latency |
| 1949system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1950system.cpu1.l2cache.prefetcher.num_hwpf_issued 7137751 # number of hwpf issued 1951system.cpu1.l2cache.prefetcher.pfIdentified 7137894 # number of prefetch candidates identified 1952system.cpu1.l2cache.prefetcher.pfBufferHit 127 # number of redundant prefetches already in prefetch queue 1953system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1954system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1955system.cpu1.l2cache.prefetcher.pfSpanPage 851890 # number of prefetches not generated due to page crossing 1956system.cpu1.l2cache.tags.replacements 2314380 # number of replacements 1957system.cpu1.l2cache.tags.tagsinuse 13359.571881 # Cycle average of tags in use --- 199 unchanged lines hidden (view full) --- 2157system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40773.813811 # average overall miss latency 2158system.cpu1.l2cache.overall_avg_miss_latency::total 39126.172242 # average overall miss latency 2159system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2160system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2161system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2162system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2163system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2164system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1923system.cpu1.l2cache.prefetcher.num_hwpf_issued 7137751 # number of hwpf issued 1924system.cpu1.l2cache.prefetcher.pfIdentified 7137894 # number of prefetch candidates identified 1925system.cpu1.l2cache.prefetcher.pfBufferHit 127 # number of redundant prefetches already in prefetch queue 1926system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1927system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1928system.cpu1.l2cache.prefetcher.pfSpanPage 851890 # number of prefetches not generated due to page crossing 1929system.cpu1.l2cache.tags.replacements 2314380 # number of replacements 1930system.cpu1.l2cache.tags.tagsinuse 13359.571881 # Cycle average of tags in use --- 199 unchanged lines hidden (view full) --- 2130system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40773.813811 # average overall miss latency 2131system.cpu1.l2cache.overall_avg_miss_latency::total 39126.172242 # average overall miss latency 2132system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2133system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2134system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2135system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2136system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2137system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2165system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2166system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | |
| 2167system.cpu1.l2cache.unused_prefetches 46108 # number of HardPF blocks evicted w/o reference 2168system.cpu1.l2cache.writebacks::writebacks 1173247 # number of writebacks 2169system.cpu1.l2cache.writebacks::total 1173247 # number of writebacks 2170system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 3 # number of ReadReq MSHR hits 2171system.cpu1.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 2172system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6478 # number of ReadExReq MSHR hits 2173system.cpu1.l2cache.ReadExReq_mshr_hits::total 6478 # number of ReadExReq MSHR hits 2174system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits --- 76 unchanged lines hidden (view full) --- 2251system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 414677500 # number of overall MSHR miss cycles 2252system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20322130500 # number of overall MSHR miss cycles 2253system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 41898612489 # number of overall MSHR miss cycles 2254system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 38779162359 # number of overall MSHR miss cycles 2255system.cpu1.l2cache.overall_mshr_miss_latency::total 101937567348 # number of overall MSHR miss cycles 2256system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12274000 # number of ReadReq MSHR uncacheable cycles 2257system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 860931500 # number of ReadReq MSHR uncacheable cycles 2258system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 873205500 # number of ReadReq MSHR uncacheable cycles | 2138system.cpu1.l2cache.unused_prefetches 46108 # number of HardPF blocks evicted w/o reference 2139system.cpu1.l2cache.writebacks::writebacks 1173247 # number of writebacks 2140system.cpu1.l2cache.writebacks::total 1173247 # number of writebacks 2141system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 3 # number of ReadReq MSHR hits 2142system.cpu1.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 2143system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 6478 # number of ReadExReq MSHR hits 2144system.cpu1.l2cache.ReadExReq_mshr_hits::total 6478 # number of ReadExReq MSHR hits 2145system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits --- 76 unchanged lines hidden (view full) --- 2222system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 414677500 # number of overall MSHR miss cycles 2223system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 20322130500 # number of overall MSHR miss cycles 2224system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 41898612489 # number of overall MSHR miss cycles 2225system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 38779162359 # number of overall MSHR miss cycles 2226system.cpu1.l2cache.overall_mshr_miss_latency::total 101937567348 # number of overall MSHR miss cycles 2227system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12274000 # number of ReadReq MSHR uncacheable cycles 2228system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 860931500 # number of ReadReq MSHR uncacheable cycles 2229system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 873205500 # number of ReadReq MSHR uncacheable cycles |
| 2259system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1037437000 # number of WriteReq MSHR uncacheable cycles 2260system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1037437000 # number of WriteReq MSHR uncacheable cycles | |
| 2261system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12274000 # number of overall MSHR uncacheable cycles | 2230system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12274000 # number of overall MSHR uncacheable cycles |
| 2262system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1898368500 # number of overall MSHR uncacheable cycles 2263system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1910642500 # number of overall MSHR uncacheable cycles | 2231system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 860931500 # number of overall MSHR uncacheable cycles 2232system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 873205500 # number of overall MSHR uncacheable cycles |
| 2264system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024289 # mshr miss rate for ReadReq accesses 2265system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.052372 # mshr miss rate for ReadReq accesses 2266system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.031430 # mshr miss rate for ReadReq accesses 2267system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2268system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2269system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997472 # mshr miss rate for UpgradeReq accesses 2270system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997472 # mshr miss rate for UpgradeReq accesses 2271system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses --- 47 unchanged lines hidden (view full) --- 2319system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average overall mshr miss latency 2320system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average overall mshr miss latency 2321system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34176.305402 # average overall mshr miss latency 2322system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50482.920781 # average overall mshr miss latency 2323system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37793.329747 # average overall mshr miss latency 2324system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average ReadReq mshr uncacheable latency 2325system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117341.079460 # average ReadReq mshr uncacheable latency 2326system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117524.293405 # average ReadReq mshr uncacheable latency | 2233system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024289 # mshr miss rate for ReadReq accesses 2234system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.052372 # mshr miss rate for ReadReq accesses 2235system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.031430 # mshr miss rate for ReadReq accesses 2236system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2237system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2238system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997472 # mshr miss rate for UpgradeReq accesses 2239system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997472 # mshr miss rate for UpgradeReq accesses 2240system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses --- 47 unchanged lines hidden (view full) --- 2288system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 44859.097793 # average overall mshr miss latency 2289system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29828.373467 # average overall mshr miss latency 2290system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34176.305402 # average overall mshr miss latency 2291system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50482.920781 # average overall mshr miss latency 2292system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 37793.329747 # average overall mshr miss latency 2293system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average ReadReq mshr uncacheable latency 2294system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117341.079460 # average ReadReq mshr uncacheable latency 2295system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117524.293405 # average ReadReq mshr uncacheable latency |
| 2327system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 135772.411988 # average WriteReq mshr uncacheable latency 2328system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 135772.411988 # average WriteReq mshr uncacheable latency | |
| 2329system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average overall mshr uncacheable latency | 2296system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 131978.494624 # average overall mshr uncacheable latency |
| 2330system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126743.790893 # average overall mshr uncacheable latency 2331system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126776.093159 # average overall mshr uncacheable latency 2332system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 2297system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 57479.736948 # average overall mshr uncacheable latency 2298system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 57939.453255 # average overall mshr uncacheable latency |
| 2333system.cpu1.toL2Bus.snoop_filter.tot_requests 27757324 # Total number of requests made to the snoop filter. 2334system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14199775 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2335system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1809 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2336system.cpu1.toL2Bus.snoop_filter.tot_snoops 2096264 # Total number of snoops made to the snoop filter. 2337system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2095922 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2338system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 342 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2339system.cpu1.toL2Bus.trans_dist::ReadReq 778911 # Transaction distribution 2340system.cpu1.toL2Bus.trans_dist::ReadResp 12918528 # Transaction distribution --- 145 unchanged lines hidden (view full) --- 2486system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2487system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses 2488system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses 2489system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2490system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2491system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses 2492system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses 2493system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses | 2299system.cpu1.toL2Bus.snoop_filter.tot_requests 27757324 # Total number of requests made to the snoop filter. 2300system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14199775 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2301system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1809 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2302system.cpu1.toL2Bus.snoop_filter.tot_snoops 2096264 # Total number of snoops made to the snoop filter. 2303system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2095922 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2304system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 342 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2305system.cpu1.toL2Bus.trans_dist::ReadReq 778911 # Transaction distribution 2306system.cpu1.toL2Bus.trans_dist::ReadResp 12918528 # Transaction distribution --- 145 unchanged lines hidden (view full) --- 2452system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2453system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses 2454system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses 2455system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2456system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2457system.iocache.WriteLineReq_misses::realview.ide 106984 # number of WriteLineReq misses 2458system.iocache.WriteLineReq_misses::total 106984 # number of WriteLineReq misses 2459system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses |
| 2494system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses 2495system.iocache.demand_misses::total 8917 # number of demand (read+write) misses | 2460system.iocache.demand_misses::realview.ide 115861 # number of demand (read+write) misses 2461system.iocache.demand_misses::total 115901 # number of demand (read+write) misses |
| 2496system.iocache.overall_misses::realview.ethernet 40 # number of overall misses | 2462system.iocache.overall_misses::realview.ethernet 40 # number of overall misses |
| 2497system.iocache.overall_misses::realview.ide 8877 # number of overall misses 2498system.iocache.overall_misses::total 8917 # number of overall misses | 2463system.iocache.overall_misses::realview.ide 115861 # number of overall misses 2464system.iocache.overall_misses::total 115901 # number of overall misses |
| 2499system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles 2500system.iocache.ReadReq_miss_latency::realview.ide 1651659585 # number of ReadReq miss cycles 2501system.iocache.ReadReq_miss_latency::total 1656859085 # number of ReadReq miss cycles 2502system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2503system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2504system.iocache.WriteLineReq_miss_latency::realview.ide 13563940301 # number of WriteLineReq miss cycles 2505system.iocache.WriteLineReq_miss_latency::total 13563940301 # number of WriteLineReq miss cycles 2506system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles | 2465system.iocache.ReadReq_miss_latency::realview.ethernet 5199500 # number of ReadReq miss cycles 2466system.iocache.ReadReq_miss_latency::realview.ide 1651659585 # number of ReadReq miss cycles 2467system.iocache.ReadReq_miss_latency::total 1656859085 # number of ReadReq miss cycles 2468system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2469system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2470system.iocache.WriteLineReq_miss_latency::realview.ide 13563940301 # number of WriteLineReq miss cycles 2471system.iocache.WriteLineReq_miss_latency::total 13563940301 # number of WriteLineReq miss cycles 2472system.iocache.demand_miss_latency::realview.ethernet 5568500 # number of demand (read+write) miss cycles |
| 2507system.iocache.demand_miss_latency::realview.ide 1651659585 # number of demand (read+write) miss cycles 2508system.iocache.demand_miss_latency::total 1657228085 # number of demand (read+write) miss cycles | 2473system.iocache.demand_miss_latency::realview.ide 15215599886 # number of demand (read+write) miss cycles 2474system.iocache.demand_miss_latency::total 15221168386 # number of demand (read+write) miss cycles |
| 2509system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles | 2475system.iocache.overall_miss_latency::realview.ethernet 5568500 # number of overall miss cycles |
| 2510system.iocache.overall_miss_latency::realview.ide 1651659585 # number of overall miss cycles 2511system.iocache.overall_miss_latency::total 1657228085 # number of overall miss cycles | 2476system.iocache.overall_miss_latency::realview.ide 15215599886 # number of overall miss cycles 2477system.iocache.overall_miss_latency::total 15221168386 # number of overall miss cycles |
| 2512system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2513system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses) 2514system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses) 2515system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2516system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2517system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) 2518system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) 2519system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses | 2478system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2479system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses) 2480system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses) 2481system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2482system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2483system.iocache.WriteLineReq_accesses::realview.ide 106984 # number of WriteLineReq accesses(hits+misses) 2484system.iocache.WriteLineReq_accesses::total 106984 # number of WriteLineReq accesses(hits+misses) 2485system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses |
| 2520system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses 2521system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses | 2486system.iocache.demand_accesses::realview.ide 115861 # number of demand (read+write) accesses 2487system.iocache.demand_accesses::total 115901 # number of demand (read+write) accesses |
| 2522system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses | 2488system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses |
| 2523system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses 2524system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses | 2489system.iocache.overall_accesses::realview.ide 115861 # number of overall (read+write) accesses 2490system.iocache.overall_accesses::total 115901 # number of overall (read+write) accesses |
| 2525system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2526system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2527system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2528system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2529system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2530system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2531system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2532system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses --- 5 unchanged lines hidden (view full) --- 2538system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency 2539system.iocache.ReadReq_avg_miss_latency::realview.ide 186060.559311 # average ReadReq miss latency 2540system.iocache.ReadReq_avg_miss_latency::total 185871.559906 # average ReadReq miss latency 2541system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2542system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2543system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126784.755674 # average WriteLineReq miss latency 2544system.iocache.WriteLineReq_avg_miss_latency::total 126784.755674 # average WriteLineReq miss latency 2545system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency | 2491system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2492system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2493system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2494system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2495system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2496system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2497system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2498system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses --- 5 unchanged lines hidden (view full) --- 2504system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140527.027027 # average ReadReq miss latency 2505system.iocache.ReadReq_avg_miss_latency::realview.ide 186060.559311 # average ReadReq miss latency 2506system.iocache.ReadReq_avg_miss_latency::total 185871.559906 # average ReadReq miss latency 2507system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2508system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2509system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126784.755674 # average WriteLineReq miss latency 2510system.iocache.WriteLineReq_avg_miss_latency::total 126784.755674 # average WriteLineReq miss latency 2511system.iocache.demand_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency |
| 2546system.iocache.demand_avg_miss_latency::realview.ide 186060.559311 # average overall miss latency 2547system.iocache.demand_avg_miss_latency::total 185850.407648 # average overall miss latency | 2512system.iocache.demand_avg_miss_latency::realview.ide 131326.329705 # average overall miss latency 2513system.iocache.demand_avg_miss_latency::total 131329.051397 # average overall miss latency |
| 2548system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency | 2514system.iocache.overall_avg_miss_latency::realview.ethernet 139212.500000 # average overall miss latency |
| 2549system.iocache.overall_avg_miss_latency::realview.ide 186060.559311 # average overall miss latency 2550system.iocache.overall_avg_miss_latency::total 185850.407648 # average overall miss latency | 2515system.iocache.overall_avg_miss_latency::realview.ide 131326.329705 # average overall miss latency 2516system.iocache.overall_avg_miss_latency::total 131329.051397 # average overall miss latency |
| 2551system.iocache.blocked_cycles::no_mshrs 32764 # number of cycles access was blocked 2552system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2553system.iocache.blocked::no_mshrs 3385 # number of cycles access was blocked 2554system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2555system.iocache.avg_blocked_cycles::no_mshrs 9.679173 # average number of cycles each access was blocked 2556system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2517system.iocache.blocked_cycles::no_mshrs 32764 # number of cycles access was blocked 2518system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2519system.iocache.blocked::no_mshrs 3385 # number of cycles access was blocked 2520system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2521system.iocache.avg_blocked_cycles::no_mshrs 9.679173 # average number of cycles each access was blocked 2522system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2557system.iocache.fast_writes 0 # number of fast writes performed 2558system.iocache.cache_copies 0 # number of cache copies performed | |
| 2559system.iocache.writebacks::writebacks 106951 # number of writebacks 2560system.iocache.writebacks::total 106951 # number of writebacks 2561system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2562system.iocache.ReadReq_mshr_misses::realview.ide 8877 # number of ReadReq MSHR misses 2563system.iocache.ReadReq_mshr_misses::total 8914 # number of ReadReq MSHR misses 2564system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2565system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2566system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses 2567system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses 2568system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses | 2523system.iocache.writebacks::writebacks 106951 # number of writebacks 2524system.iocache.writebacks::total 106951 # number of writebacks 2525system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2526system.iocache.ReadReq_mshr_misses::realview.ide 8877 # number of ReadReq MSHR misses 2527system.iocache.ReadReq_mshr_misses::total 8914 # number of ReadReq MSHR misses 2528system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2529system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2530system.iocache.WriteLineReq_mshr_misses::realview.ide 106984 # number of WriteLineReq MSHR misses 2531system.iocache.WriteLineReq_mshr_misses::total 106984 # number of WriteLineReq MSHR misses 2532system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses |
| 2569system.iocache.demand_mshr_misses::realview.ide 8877 # number of demand (read+write) MSHR misses 2570system.iocache.demand_mshr_misses::total 8917 # number of demand (read+write) MSHR misses | 2533system.iocache.demand_mshr_misses::realview.ide 115861 # number of demand (read+write) MSHR misses 2534system.iocache.demand_mshr_misses::total 115901 # number of demand (read+write) MSHR misses |
| 2571system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses | 2535system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses |
| 2572system.iocache.overall_mshr_misses::realview.ide 8877 # number of overall MSHR misses 2573system.iocache.overall_mshr_misses::total 8917 # number of overall MSHR misses | 2536system.iocache.overall_mshr_misses::realview.ide 115861 # number of overall MSHR misses 2537system.iocache.overall_mshr_misses::total 115901 # number of overall MSHR misses |
| 2574system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles 2575system.iocache.ReadReq_mshr_miss_latency::realview.ide 1207809585 # number of ReadReq MSHR miss cycles 2576system.iocache.ReadReq_mshr_miss_latency::total 1211159085 # number of ReadReq MSHR miss cycles 2577system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2578system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2579system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8208491858 # number of WriteLineReq MSHR miss cycles 2580system.iocache.WriteLineReq_mshr_miss_latency::total 8208491858 # number of WriteLineReq MSHR miss cycles 2581system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles | 2538system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349500 # number of ReadReq MSHR miss cycles 2539system.iocache.ReadReq_mshr_miss_latency::realview.ide 1207809585 # number of ReadReq MSHR miss cycles 2540system.iocache.ReadReq_mshr_miss_latency::total 1211159085 # number of ReadReq MSHR miss cycles 2541system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2542system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2543system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8208491858 # number of WriteLineReq MSHR miss cycles 2544system.iocache.WriteLineReq_mshr_miss_latency::total 8208491858 # number of WriteLineReq MSHR miss cycles 2545system.iocache.demand_mshr_miss_latency::realview.ethernet 3568500 # number of demand (read+write) MSHR miss cycles |
| 2582system.iocache.demand_mshr_miss_latency::realview.ide 1207809585 # number of demand (read+write) MSHR miss cycles 2583system.iocache.demand_mshr_miss_latency::total 1211378085 # number of demand (read+write) MSHR miss cycles | 2546system.iocache.demand_mshr_miss_latency::realview.ide 9416301443 # number of demand (read+write) MSHR miss cycles 2547system.iocache.demand_mshr_miss_latency::total 9419869943 # number of demand (read+write) MSHR miss cycles |
| 2584system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles | 2548system.iocache.overall_mshr_miss_latency::realview.ethernet 3568500 # number of overall MSHR miss cycles |
| 2585system.iocache.overall_mshr_miss_latency::realview.ide 1207809585 # number of overall MSHR miss cycles 2586system.iocache.overall_mshr_miss_latency::total 1211378085 # number of overall MSHR miss cycles | 2549system.iocache.overall_mshr_miss_latency::realview.ide 9416301443 # number of overall MSHR miss cycles 2550system.iocache.overall_mshr_miss_latency::total 9419869943 # number of overall MSHR miss cycles |
| 2587system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2588system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2589system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2590system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2591system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2592system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2593system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2594system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses --- 5 unchanged lines hidden (view full) --- 2600system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency 2601system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136060.559311 # average ReadReq mshr miss latency 2602system.iocache.ReadReq_avg_mshr_miss_latency::total 135871.559906 # average ReadReq mshr miss latency 2603system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2604system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2605system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76726.350277 # average WriteLineReq mshr miss latency 2606system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76726.350277 # average WriteLineReq mshr miss latency 2607system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency | 2551system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2552system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2553system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2554system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2555system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2556system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2557system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2558system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses --- 5 unchanged lines hidden (view full) --- 2564system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90527.027027 # average ReadReq mshr miss latency 2565system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136060.559311 # average ReadReq mshr miss latency 2566system.iocache.ReadReq_avg_mshr_miss_latency::total 135871.559906 # average ReadReq mshr miss latency 2567system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2568system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2569system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76726.350277 # average WriteLineReq mshr miss latency 2570system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76726.350277 # average WriteLineReq mshr miss latency 2571system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency |
| 2608system.iocache.demand_avg_mshr_miss_latency::realview.ide 136060.559311 # average overall mshr miss latency 2609system.iocache.demand_avg_mshr_miss_latency::total 135850.407648 # average overall mshr miss latency | 2572system.iocache.demand_avg_mshr_miss_latency::realview.ide 81272.399194 # average overall mshr miss latency 2573system.iocache.demand_avg_mshr_miss_latency::total 81275.139498 # average overall mshr miss latency |
| 2610system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency | 2574system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89212.500000 # average overall mshr miss latency |
| 2611system.iocache.overall_avg_mshr_miss_latency::realview.ide 136060.559311 # average overall mshr miss latency 2612system.iocache.overall_avg_mshr_miss_latency::total 135850.407648 # average overall mshr miss latency 2613system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 2575system.iocache.overall_avg_mshr_miss_latency::realview.ide 81272.399194 # average overall mshr miss latency 2576system.iocache.overall_avg_mshr_miss_latency::total 81275.139498 # average overall mshr miss latency |
| 2614system.l2c.tags.replacements 1387428 # number of replacements 2615system.l2c.tags.tagsinuse 63551.257518 # Cycle average of tags in use 2616system.l2c.tags.total_refs 6641936 # Total number of references to valid blocks. 2617system.l2c.tags.sampled_refs 1448331 # Sample count of references to valid blocks. 2618system.l2c.tags.avg_refs 4.585924 # Average number of references to valid blocks. 2619system.l2c.tags.warmup_cycle 13283135500 # Cycle when the warmup percentage was hit. 2620system.l2c.tags.occ_blocks::writebacks 22018.288167 # Average occupied blocks per requestor 2621system.l2c.tags.occ_blocks::cpu0.dtb.walker 94.707462 # Average occupied blocks per requestor --- 312 unchanged lines hidden (view full) --- 2934system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 167833.163833 # average overall miss latency 2935system.l2c.overall_avg_miss_latency::total 153262.747812 # average overall miss latency 2936system.l2c.blocked_cycles::no_mshrs 971 # number of cycles access was blocked 2937system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2938system.l2c.blocked::no_mshrs 13 # number of cycles access was blocked 2939system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2940system.l2c.avg_blocked_cycles::no_mshrs 74.692308 # average number of cycles each access was blocked 2941system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 2577system.l2c.tags.replacements 1387428 # number of replacements 2578system.l2c.tags.tagsinuse 63551.257518 # Cycle average of tags in use 2579system.l2c.tags.total_refs 6641936 # Total number of references to valid blocks. 2580system.l2c.tags.sampled_refs 1448331 # Sample count of references to valid blocks. 2581system.l2c.tags.avg_refs 4.585924 # Average number of references to valid blocks. 2582system.l2c.tags.warmup_cycle 13283135500 # Cycle when the warmup percentage was hit. 2583system.l2c.tags.occ_blocks::writebacks 22018.288167 # Average occupied blocks per requestor 2584system.l2c.tags.occ_blocks::cpu0.dtb.walker 94.707462 # Average occupied blocks per requestor --- 312 unchanged lines hidden (view full) --- 2897system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 167833.163833 # average overall miss latency 2898system.l2c.overall_avg_miss_latency::total 153262.747812 # average overall miss latency 2899system.l2c.blocked_cycles::no_mshrs 971 # number of cycles access was blocked 2900system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2901system.l2c.blocked::no_mshrs 13 # number of cycles access was blocked 2902system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2903system.l2c.avg_blocked_cycles::no_mshrs 74.692308 # average number of cycles each access was blocked 2904system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 2942system.l2c.fast_writes 0 # number of fast writes performed 2943system.l2c.cache_copies 0 # number of cache copies performed | |
| 2944system.l2c.writebacks::writebacks 1075915 # number of writebacks 2945system.l2c.writebacks::total 1075915 # number of writebacks 2946system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 164 # number of ReadSharedReq MSHR hits 2947system.l2c.ReadSharedReq_mshr_hits::cpu0.data 19 # number of ReadSharedReq MSHR hits 2948system.l2c.ReadSharedReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadSharedReq MSHR hits 2949system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 208 # number of ReadSharedReq MSHR hits 2950system.l2c.ReadSharedReq_mshr_hits::cpu1.data 31 # number of ReadSharedReq MSHR hits 2951system.l2c.ReadSharedReq_mshr_hits::total 423 # number of ReadSharedReq MSHR hits --- 114 unchanged lines hidden (view full) --- 3066system.l2c.overall_mshr_miss_latency::cpu1.data 19505265139 # number of overall MSHR miss cycles 3067system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 30868571958 # number of overall MSHR miss cycles 3068system.l2c.overall_mshr_miss_latency::total 133811260722 # number of overall MSHR miss cycles 3069system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5897666000 # number of ReadReq MSHR uncacheable cycles 3070system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5220688053 # number of ReadReq MSHR uncacheable cycles 3071system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10320500 # number of ReadReq MSHR uncacheable cycles 3072system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 728734017 # number of ReadReq MSHR uncacheable cycles 3073system.l2c.ReadReq_mshr_uncacheable_latency::total 11857408570 # number of ReadReq MSHR uncacheable cycles | 2905system.l2c.writebacks::writebacks 1075915 # number of writebacks 2906system.l2c.writebacks::total 1075915 # number of writebacks 2907system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 164 # number of ReadSharedReq MSHR hits 2908system.l2c.ReadSharedReq_mshr_hits::cpu0.data 19 # number of ReadSharedReq MSHR hits 2909system.l2c.ReadSharedReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadSharedReq MSHR hits 2910system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 208 # number of ReadSharedReq MSHR hits 2911system.l2c.ReadSharedReq_mshr_hits::cpu1.data 31 # number of ReadSharedReq MSHR hits 2912system.l2c.ReadSharedReq_mshr_hits::total 423 # number of ReadSharedReq MSHR hits --- 114 unchanged lines hidden (view full) --- 3027system.l2c.overall_mshr_miss_latency::cpu1.data 19505265139 # number of overall MSHR miss cycles 3028system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 30868571958 # number of overall MSHR miss cycles 3029system.l2c.overall_mshr_miss_latency::total 133811260722 # number of overall MSHR miss cycles 3030system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5897666000 # number of ReadReq MSHR uncacheable cycles 3031system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5220688053 # number of ReadReq MSHR uncacheable cycles 3032system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10320500 # number of ReadReq MSHR uncacheable cycles 3033system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 728734017 # number of ReadReq MSHR uncacheable cycles 3034system.l2c.ReadReq_mshr_uncacheable_latency::total 11857408570 # number of ReadReq MSHR uncacheable cycles |
| 3074system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 5073884538 # number of WriteReq MSHR uncacheable cycles 3075system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 907395547 # number of WriteReq MSHR uncacheable cycles 3076system.l2c.WriteReq_mshr_uncacheable_latency::total 5981280085 # number of WriteReq MSHR uncacheable cycles | |
| 3077system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5897666000 # number of overall MSHR uncacheable cycles | 3035system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5897666000 # number of overall MSHR uncacheable cycles |
| 3078system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10294572591 # number of overall MSHR uncacheable cycles | 3036system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5220688053 # number of overall MSHR uncacheable cycles |
| 3079system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10320500 # number of overall MSHR uncacheable cycles | 3037system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10320500 # number of overall MSHR uncacheable cycles |
| 3080system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1636129564 # number of overall MSHR uncacheable cycles 3081system.l2c.overall_mshr_uncacheable_latency::total 17838688655 # number of overall MSHR uncacheable cycles | 3038system.l2c.overall_mshr_uncacheable_latency::cpu1.data 728734017 # number of overall MSHR uncacheable cycles 3039system.l2c.overall_mshr_uncacheable_latency::total 11857408570 # number of overall MSHR uncacheable cycles |
| 3082system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3083system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3084system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.275862 # mshr miss rate for UpgradeReq accesses 3085system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.306052 # mshr miss rate for UpgradeReq accesses 3086system.l2c.UpgradeReq_mshr_miss_rate::total 0.290013 # mshr miss rate for UpgradeReq accesses 3087system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.237874 # mshr miss rate for SCUpgradeReq accesses 3088system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.225288 # mshr miss rate for SCUpgradeReq accesses 3089system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.231817 # mshr miss rate for SCUpgradeReq accesses --- 81 unchanged lines hidden (view full) --- 3171system.l2c.overall_avg_mshr_miss_latency::cpu1.data 128482.179649 # average overall mshr miss latency 3172system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157823.660625 # average overall mshr miss latency 3173system.l2c.overall_avg_mshr_miss_latency::total 143274.851193 # average overall mshr miss latency 3174system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency 3175system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165462.983424 # average ReadReq mshr uncacheable latency 3176system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280 # average ReadReq mshr uncacheable latency 3177system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 99350.240900 # average ReadReq mshr uncacheable latency 3178system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 129888.689437 # average ReadReq mshr uncacheable latency | 3040system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3041system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3042system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.275862 # mshr miss rate for UpgradeReq accesses 3043system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.306052 # mshr miss rate for UpgradeReq accesses 3044system.l2c.UpgradeReq_mshr_miss_rate::total 0.290013 # mshr miss rate for UpgradeReq accesses 3045system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.237874 # mshr miss rate for SCUpgradeReq accesses 3046system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.225288 # mshr miss rate for SCUpgradeReq accesses 3047system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.231817 # mshr miss rate for SCUpgradeReq accesses --- 81 unchanged lines hidden (view full) --- 3129system.l2c.overall_avg_mshr_miss_latency::cpu1.data 128482.179649 # average overall mshr miss latency 3130system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 157823.660625 # average overall mshr miss latency 3131system.l2c.overall_avg_mshr_miss_latency::total 143274.851193 # average overall mshr miss latency 3132system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average ReadReq mshr uncacheable latency 3133system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165462.983424 # average ReadReq mshr uncacheable latency 3134system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280 # average ReadReq mshr uncacheable latency 3135system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 99350.240900 # average ReadReq mshr uncacheable latency 3136system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 129888.689437 # average ReadReq mshr uncacheable latency |
| 3179system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162895.997753 # average WriteReq mshr uncacheable latency 3180system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 118753.507002 # average WriteReq mshr uncacheable latency 3181system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154200.419836 # average WriteReq mshr uncacheable latency | |
| 3182system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency | 3137system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112746.678392 # average overall mshr uncacheable latency |
| 3183system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164187.760622 # average overall mshr uncacheable latency | 3138system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83264.562249 # average overall mshr uncacheable latency |
| 3184system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280 # average overall mshr uncacheable latency | 3139system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 110973.118280 # average overall mshr uncacheable latency |
| 3185system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109250.104434 # average overall mshr uncacheable latency 3186system.l2c.overall_avg_mshr_uncacheable_latency::total 137138.398922 # average overall mshr uncacheable latency 3187system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 3140system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 48660.123998 # average overall mshr uncacheable latency 3141system.l2c.overall_avg_mshr_uncacheable_latency::total 91156.141469 # average overall mshr uncacheable latency |
| 3188system.membus.trans_dist::ReadReq 91289 # Transaction distribution 3189system.membus.trans_dist::ReadResp 902614 # Transaction distribution 3190system.membus.trans_dist::WriteReq 38789 # Transaction distribution 3191system.membus.trans_dist::WriteResp 38789 # Transaction distribution 3192system.membus.trans_dist::WritebackDirty 1182866 # Transaction distribution 3193system.membus.trans_dist::CleanEvict 259673 # Transaction distribution 3194system.membus.trans_dist::UpgradeReq 445486 # Transaction distribution 3195system.membus.trans_dist::SCUpgradeReq 315870 # Transaction distribution --- 148 unchanged lines hidden --- | 3142system.membus.trans_dist::ReadReq 91289 # Transaction distribution 3143system.membus.trans_dist::ReadResp 902614 # Transaction distribution 3144system.membus.trans_dist::WriteReq 38789 # Transaction distribution 3145system.membus.trans_dist::WriteResp 38789 # Transaction distribution 3146system.membus.trans_dist::WritebackDirty 1182866 # Transaction distribution 3147system.membus.trans_dist::CleanEvict 259673 # Transaction distribution 3148system.membus.trans_dist::UpgradeReq 445486 # Transaction distribution 3149system.membus.trans_dist::SCUpgradeReq 315870 # Transaction distribution --- 148 unchanged lines hidden --- |