| stats.txt (10765:ee0e03afd9da) | stats.txt (10827:7f5467f2f8b8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 47.443139 # Number of seconds simulated 4sim_ticks 47443139283500 # Number of ticks simulated 5final_tick 47443139283500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 47.365947 # Number of seconds simulated 4sim_ticks 47365946685500 # Number of ticks simulated 5final_tick 47365946685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 174986 # Simulator instruction rate (inst/s) 8host_op_rate 205797 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9320406551 # Simulator tick rate (ticks/s) 10host_mem_usage 765676 # Number of bytes of host memory used 11host_seconds 5090.24 # Real time elapsed on the host 12sim_insts 890723033 # Number of instructions simulated 13sim_ops 1047557701 # Number of ops (including micro ops) simulated | 7host_inst_rate 174192 # Simulator instruction rate (inst/s) 8host_op_rate 204861 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 9672451523 # Simulator tick rate (ticks/s) 10host_mem_usage 763596 # Number of bytes of host memory used 11host_seconds 4897.00 # Real time elapsed on the host 12sim_insts 853019792 # Number of instructions simulated 13sim_ops 1003201701 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu0.dtb.walker 111744 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 91648 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 7668224 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 13156952 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 13340800 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 149248 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 146240 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 3865344 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 11856672 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 13765376 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 430976 # Number of bytes read from this memory 27system.physmem.bytes_read::total 64583224 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 7668224 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 3865344 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 11533568 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 75782720 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory | 16system.physmem.bytes_read::cpu0.dtb.walker 65472 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 64384 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 7833792 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 12003144 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 10766848 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 71104 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 69248 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 2839488 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 7678416 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 7994432 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 439552 # Number of bytes read from this memory 27system.physmem.bytes_read::total 49825880 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 7833792 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 2839488 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 10673280 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 62800512 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory |
| 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory | 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory |
| 34system.physmem.bytes_written::total 75803536 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 1746 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1432 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 119816 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 205599 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 208450 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 2332 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 2285 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 60396 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 185275 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 215084 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6734 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 1009149 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1184105 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory | 34system.physmem.bytes_written::total 62821096 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 1023 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1006 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 122403 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 187562 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 168232 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 1111 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 1082 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 44367 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 119988 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 124913 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6868 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 778555 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 981258 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory |
| 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory | 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory |
| 50system.physmem.num_writes::total 1186708 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 2355 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 1932 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 161630 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 277320 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 281196 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 3146 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 3082 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 81473 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 249913 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 290145 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9084 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1361276 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 161630 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 81473 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 243103 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1597338 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) | 50system.physmem.num_writes::total 983832 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 1382 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 1359 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 165389 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 253413 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 227312 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 1501 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 1462 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 59948 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 162108 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 168780 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9280 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1051935 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 165389 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 59948 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 225337 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1325858 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) |
| 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) | 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) |
| 69system.physmem.bw_write::total 1597777 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1597338 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 2355 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 1932 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 161630 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 277759 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 281196 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 3146 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 3082 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 81473 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 249913 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 290145 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9084 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 2959053 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 1009149 # Number of read requests accepted 84system.physmem.writeReqs 1850399 # Number of write requests accepted 85system.physmem.readBursts 1009149 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1850399 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 64564224 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 21312 # Total number of bytes read from write queue 89system.physmem.bytesWritten 115242304 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 64583224 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 118279760 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 333 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 49721 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 115106 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 57845 # Per bank write bursts 96system.physmem.perBankRdBursts::1 61929 # Per bank write bursts 97system.physmem.perBankRdBursts::2 56818 # Per bank write bursts 98system.physmem.perBankRdBursts::3 63723 # Per bank write bursts 99system.physmem.perBankRdBursts::4 61880 # Per bank write bursts 100system.physmem.perBankRdBursts::5 68171 # Per bank write bursts 101system.physmem.perBankRdBursts::6 59739 # Per bank write bursts 102system.physmem.perBankRdBursts::7 60869 # Per bank write bursts 103system.physmem.perBankRdBursts::8 54876 # Per bank write bursts 104system.physmem.perBankRdBursts::9 108415 # Per bank write bursts 105system.physmem.perBankRdBursts::10 50407 # Per bank write bursts 106system.physmem.perBankRdBursts::11 61358 # Per bank write bursts 107system.physmem.perBankRdBursts::12 58228 # Per bank write bursts 108system.physmem.perBankRdBursts::13 64090 # Per bank write bursts 109system.physmem.perBankRdBursts::14 57873 # Per bank write bursts 110system.physmem.perBankRdBursts::15 62595 # Per bank write bursts 111system.physmem.perBankWrBursts::0 107469 # Per bank write bursts 112system.physmem.perBankWrBursts::1 113594 # Per bank write bursts 113system.physmem.perBankWrBursts::2 115011 # Per bank write bursts 114system.physmem.perBankWrBursts::3 118413 # Per bank write bursts 115system.physmem.perBankWrBursts::4 118243 # Per bank write bursts 116system.physmem.perBankWrBursts::5 118449 # Per bank write bursts 117system.physmem.perBankWrBursts::6 111339 # Per bank write bursts 118system.physmem.perBankWrBursts::7 115322 # Per bank write bursts 119system.physmem.perBankWrBursts::8 110047 # Per bank write bursts 120system.physmem.perBankWrBursts::9 111027 # Per bank write bursts 121system.physmem.perBankWrBursts::10 102767 # Per bank write bursts 122system.physmem.perBankWrBursts::11 112058 # Per bank write bursts 123system.physmem.perBankWrBursts::12 108184 # Per bank write bursts 124system.physmem.perBankWrBursts::13 112341 # Per bank write bursts 125system.physmem.perBankWrBursts::14 110504 # Per bank write bursts 126system.physmem.perBankWrBursts::15 115893 # Per bank write bursts | 69system.physmem.bw_write::total 1326292 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1325858 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 1382 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 1359 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 165389 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 253847 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 227312 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 1501 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 1462 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 59948 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 162108 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 168780 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9280 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 2378227 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 778555 # Number of read requests accepted 84system.physmem.writeReqs 1622091 # Number of write requests accepted 85system.physmem.readBursts 778555 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1622091 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 49803520 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 24000 # Total number of bytes read from write queue 89system.physmem.bytesWritten 100652928 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 49825880 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 103669672 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 375 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 49366 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 111816 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 42060 # Per bank write bursts 96system.physmem.perBankRdBursts::1 53156 # Per bank write bursts 97system.physmem.perBankRdBursts::2 42442 # Per bank write bursts 98system.physmem.perBankRdBursts::3 47567 # Per bank write bursts 99system.physmem.perBankRdBursts::4 45723 # Per bank write bursts 100system.physmem.perBankRdBursts::5 54413 # Per bank write bursts 101system.physmem.perBankRdBursts::6 50594 # Per bank write bursts 102system.physmem.perBankRdBursts::7 44772 # Per bank write bursts 103system.physmem.perBankRdBursts::8 41306 # Per bank write bursts 104system.physmem.perBankRdBursts::9 93457 # Per bank write bursts 105system.physmem.perBankRdBursts::10 34541 # Per bank write bursts 106system.physmem.perBankRdBursts::11 47870 # Per bank write bursts 107system.physmem.perBankRdBursts::12 47765 # Per bank write bursts 108system.physmem.perBankRdBursts::13 46143 # Per bank write bursts 109system.physmem.perBankRdBursts::14 39677 # Per bank write bursts 110system.physmem.perBankRdBursts::15 46694 # Per bank write bursts 111system.physmem.perBankWrBursts::0 94318 # Per bank write bursts 112system.physmem.perBankWrBursts::1 104450 # Per bank write bursts 113system.physmem.perBankWrBursts::2 99318 # Per bank write bursts 114system.physmem.perBankWrBursts::3 101345 # Per bank write bursts 115system.physmem.perBankWrBursts::4 99792 # Per bank write bursts 116system.physmem.perBankWrBursts::5 104837 # Per bank write bursts 117system.physmem.perBankWrBursts::6 100210 # Per bank write bursts 118system.physmem.perBankWrBursts::7 98464 # Per bank write bursts 119system.physmem.perBankWrBursts::8 93421 # Per bank write bursts 120system.physmem.perBankWrBursts::9 95649 # Per bank write bursts 121system.physmem.perBankWrBursts::10 88541 # Per bank write bursts 122system.physmem.perBankWrBursts::11 99820 # Per bank write bursts 123system.physmem.perBankWrBursts::12 96824 # Per bank write bursts 124system.physmem.perBankWrBursts::13 96750 # Per bank write bursts 125system.physmem.perBankWrBursts::14 94484 # Per bank write bursts 126system.physmem.perBankWrBursts::15 104479 # Per bank write bursts |
| 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 128system.physmem.numWrRetry 251 # Number of times write queue was full causing retry 129system.physmem.totGap 47443137361000 # Total gap between requests | 128system.physmem.numWrRetry 276 # Number of times write queue was full causing retry 129system.physmem.totGap 47365944763000 # Total gap between requests |
| 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) | 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) |
| 133system.physmem.readPktSize::3 37 # Read request sizes (log2) | 133system.physmem.readPktSize::3 25 # Read request sizes (log2) |
| 134system.physmem.readPktSize::4 5 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) | 134system.physmem.readPktSize::4 5 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 136system.physmem.readPktSize::6 1009107 # Read request sizes (log2) | 136system.physmem.readPktSize::6 778525 # Read request sizes (log2) |
| 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) | 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) |
| 140system.physmem.writePktSize::3 2601 # Write request sizes (log2) | 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) |
| 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) | 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 143system.physmem.writePktSize::6 1847796 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 676531 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 118770 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 46489 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 34633 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 29357 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 26883 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 24732 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 22204 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 18862 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 5388 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 1444 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 966 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 795 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 574 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 312 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 275 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 235 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 205 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 85 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 73 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see | 143system.physmem.writePktSize::6 1619517 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 550292 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 82276 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 30517 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 23784 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 20492 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 18686 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 17057 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 15108 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 12648 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 3935 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 960 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 693 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 556 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 402 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 182 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 158 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 141 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 135 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 64 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see |
| 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see --- 8 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see --- 8 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 191system.physmem.wrQLenPdf::15 43843 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 64070 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 91575 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 102673 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 109951 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 108175 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 103872 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 98771 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 95896 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 92750 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 92610 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 110859 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 98695 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 94070 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 109570 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 97266 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 90790 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 87057 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 7476 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 6313 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 6611 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 8079 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 7980 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 6674 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 6184 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 7891 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 6061 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 5542 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 5221 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 5534 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 4360 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 3749 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 3800 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 3055 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 2430 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 1409 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 1466 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 1135 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 1034 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 856 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 876 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 759 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 668 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 573 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 497 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 432 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 361 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 312 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 832 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 1017757 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 176.667963 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 107.708761 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 246.723752 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 648817 63.75% 63.75% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 197916 19.45% 83.20% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 48918 4.81% 88.00% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 23519 2.31% 90.31% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 17229 1.69% 92.01% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 11413 1.12% 93.13% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 8164 0.80% 93.93% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 7432 0.73% 94.66% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 54349 5.34% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 1017757 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 78960 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 12.776165 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 140.389446 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-1023 78957 100.00% 100.00% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes | 191system.physmem.wrQLenPdf::15 40446 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 59954 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 84735 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 94224 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 98939 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 95817 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 91113 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 85467 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 82456 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 78613 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 78193 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 94725 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 83224 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 77979 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 91163 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 80486 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 75147 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 72304 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 7065 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 6188 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 6251 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 7364 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 8039 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 6897 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 6691 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 7373 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 5850 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 5415 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 5159 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 5392 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 4452 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 3922 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 3792 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 3304 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 2703 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 1783 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 1523 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 1082 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 1091 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 770 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 913 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 777 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 665 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 582 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 501 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 501 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 424 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 383 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 873 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 836953 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 179.765373 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 108.063876 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 253.948875 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 534704 63.89% 63.89% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 162086 19.37% 83.25% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 38261 4.57% 87.82% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 18116 2.16% 89.99% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 12763 1.52% 91.51% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 8799 1.05% 92.57% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 6603 0.79% 93.35% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 6067 0.72% 94.08% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 49554 5.92% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 836953 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 65558 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 11.869901 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 153.975731 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-1023 65556 100.00% 100.00% # Reads before turning the bus around for writes |
| 259system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes | 258system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes |
| 261system.physmem.rdPerTurnAround::total 78960 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 78960 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 22.804724 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 20.151306 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 21.211366 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-31 71201 90.17% 90.17% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::32-47 3689 4.67% 94.85% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::48-63 1610 2.04% 96.88% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::64-79 798 1.01% 97.90% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::80-95 435 0.55% 98.45% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::96-111 299 0.38% 98.82% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::112-127 436 0.55% 99.38% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::128-143 198 0.25% 99.63% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::144-159 63 0.08% 99.71% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::160-175 19 0.02% 99.73% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::176-191 61 0.08% 99.81% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::192-207 31 0.04% 99.85% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::208-223 15 0.02% 99.87% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::224-239 6 0.01% 99.87% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::240-255 4 0.01% 99.88% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::256-271 5 0.01% 99.89% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::272-287 7 0.01% 99.89% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::288-303 4 0.01% 99.90% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::304-319 9 0.01% 99.91% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::320-335 8 0.01% 99.92% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::336-351 9 0.01% 99.93% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::352-367 14 0.02% 99.95% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::368-383 2 0.00% 99.95% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::384-399 5 0.01% 99.96% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::400-415 4 0.01% 99.96% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::416-431 1 0.00% 99.97% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::432-447 4 0.01% 99.97% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::464-479 1 0.00% 99.97% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::480-495 3 0.00% 99.98% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::512-527 5 0.01% 99.99% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::528-543 3 0.00% 99.99% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::544-559 3 0.00% 99.99% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::560-575 1 0.00% 99.99% # Writes before turning the bus around for reads | 260system.physmem.rdPerTurnAround::total 65558 # Reads before turning the bus around for writes 261system.physmem.wrPerTurnAround::samples 65558 # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::mean 23.989475 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::gmean 20.876910 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::stdev 23.036255 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::16-31 57911 88.34% 88.34% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::32-47 3625 5.53% 93.86% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::48-63 1537 2.34% 96.21% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::64-79 756 1.15% 97.36% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::80-95 457 0.70% 98.06% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::96-111 339 0.52% 98.58% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::112-127 446 0.68% 99.26% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::128-143 180 0.27% 99.53% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::144-159 59 0.09% 99.62% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::160-175 25 0.04% 99.66% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::176-191 57 0.09% 99.75% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::192-207 41 0.06% 99.81% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::208-223 16 0.02% 99.83% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::224-239 6 0.01% 99.84% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::240-255 2 0.00% 99.85% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::256-271 7 0.01% 99.86% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::272-287 6 0.01% 99.87% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::288-303 4 0.01% 99.87% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::304-319 12 0.02% 99.89% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::320-335 9 0.01% 99.90% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::336-351 13 0.02% 99.92% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::352-367 20 0.03% 99.95% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::368-383 3 0.00% 99.96% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::384-399 1 0.00% 99.96% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::400-415 2 0.00% 99.96% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::432-447 2 0.00% 99.97% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::448-463 1 0.00% 99.97% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::480-495 4 0.01% 99.98% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::496-511 4 0.01% 99.98% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::512-527 4 0.01% 99.99% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::528-543 2 0.00% 99.99% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads |
| 300system.physmem.wrPerTurnAround::576-591 1 0.00% 100.00% # Writes before turning the bus around for reads | 298system.physmem.wrPerTurnAround::576-591 1 0.00% 100.00% # Writes before turning the bus around for reads |
| 301system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::736-751 1 0.00% 100.00% # Writes before turning the bus around for reads | 299system.physmem.wrPerTurnAround::672-687 1 0.00% 100.00% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads |
| 303system.physmem.wrPerTurnAround::848-863 1 0.00% 100.00% # Writes before turning the bus around for reads | 301system.physmem.wrPerTurnAround::848-863 1 0.00% 100.00% # Writes before turning the bus around for reads |
| 304system.physmem.wrPerTurnAround::total 78960 # Writes before turning the bus around for reads 305system.physmem.totQLat 36416381887 # Total ticks spent queuing 306system.physmem.totMemAccLat 55331681887 # Total ticks spent from burst creation until serviced by the DRAM 307system.physmem.totBusLat 5044080000 # Total ticks spent in databus transfers 308system.physmem.avgQLat 36098.14 # Average queueing delay per DRAM burst | 302system.physmem.wrPerTurnAround::total 65558 # Writes before turning the bus around for reads 303system.physmem.totQLat 24526926504 # Total ticks spent queuing 304system.physmem.totMemAccLat 39117801504 # Total ticks spent from burst creation until serviced by the DRAM 305system.physmem.totBusLat 3890900000 # Total ticks spent in databus transfers 306system.physmem.avgQLat 31518.32 # Average queueing delay per DRAM burst |
| 309system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 307system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 310system.physmem.avgMemAccLat 54848.14 # Average memory access latency per DRAM burst 311system.physmem.avgRdBW 1.36 # Average DRAM read bandwidth in MiByte/s 312system.physmem.avgWrBW 2.43 # Average achieved write bandwidth in MiByte/s 313system.physmem.avgRdBWSys 1.36 # Average system read bandwidth in MiByte/s 314system.physmem.avgWrBWSys 2.49 # Average system write bandwidth in MiByte/s | 308system.physmem.avgMemAccLat 50268.32 # Average memory access latency per DRAM burst 309system.physmem.avgRdBW 1.05 # Average DRAM read bandwidth in MiByte/s 310system.physmem.avgWrBW 2.13 # Average achieved write bandwidth in MiByte/s 311system.physmem.avgRdBWSys 1.05 # Average system read bandwidth in MiByte/s 312system.physmem.avgWrBWSys 2.19 # Average system write bandwidth in MiByte/s |
| 315system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 313system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 316system.physmem.busUtil 0.03 # Data bus utilization in percentage | 314system.physmem.busUtil 0.02 # Data bus utilization in percentage |
| 317system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 318system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes | 315system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 316system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes |
| 319system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing 320system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing 321system.physmem.readRowHits 756126 # Number of row buffer hits during reads 322system.physmem.writeRowHits 1035585 # Number of row buffer hits during writes 323system.physmem.readRowHitRate 74.95 # Row buffer hit rate for reads 324system.physmem.writeRowHitRate 57.51 # Row buffer hit rate for writes 325system.physmem.avgGap 16591131.66 # Average gap between requests 326system.physmem.pageHitRate 63.77 # Row buffer hit rate, read and write combined 327system.physmem_0.actEnergy 3944550960 # Energy for activate commands per rank (pJ) 328system.physmem_0.preEnergy 2152284750 # Energy for precharge commands per rank (pJ) 329system.physmem_0.readEnergy 3829511400 # Energy for read commands per rank (pJ) 330system.physmem_0.writeEnergy 5947512480 # Energy for write commands per rank (pJ) 331system.physmem_0.refreshEnergy 3098754740640 # Energy for refresh commands per rank (pJ) 332system.physmem_0.actBackEnergy 1192681206900 # Energy for active background per rank (pJ) 333system.physmem_0.preBackEnergy 27419667632250 # Energy for precharge background per rank (pJ) 334system.physmem_0.totalEnergy 31726977439380 # Total energy per rank (pJ) 335system.physmem_0.averagePower 668.736993 # Core power per rank (mW) 336system.physmem_0.memoryStateTime::IDLE 45614623336779 # Time in different power states 337system.physmem_0.memoryStateTime::REF 1584230440000 # Time in different power states | 317system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 318system.physmem.avgWrQLen 26.72 # Average write queue length when enqueuing 319system.physmem.readRowHits 582169 # Number of row buffer hits during reads 320system.physmem.writeRowHits 931750 # Number of row buffer hits during writes 321system.physmem.readRowHitRate 74.81 # Row buffer hit rate for reads 322system.physmem.writeRowHitRate 59.24 # Row buffer hit rate for writes 323system.physmem.avgGap 19730499.53 # Average gap between requests 324system.physmem.pageHitRate 64.40 # Row buffer hit rate, read and write combined 325system.physmem_0.actEnergy 3287730600 # Energy for activate commands per rank (pJ) 326system.physmem_0.preEnergy 1793900625 # Energy for precharge commands per rank (pJ) 327system.physmem_0.readEnergy 2969101200 # Energy for read commands per rank (pJ) 328system.physmem_0.writeEnergy 5201632080 # Energy for write commands per rank (pJ) 329system.physmem_0.refreshEnergy 3093712876800 # Energy for refresh commands per rank (pJ) 330system.physmem_0.actBackEnergy 1175633111385 # Energy for active background per rank (pJ) 331system.physmem_0.preBackEnergy 27388306372500 # Energy for precharge background per rank (pJ) 332system.physmem_0.totalEnergy 31670904725190 # Total energy per rank (pJ) 333system.physmem_0.averagePower 668.643023 # Core power per rank (mW) 334system.physmem_0.memoryStateTime::IDLE 45562569995604 # Time in different power states 335system.physmem_0.memoryStateTime::REF 1581652800000 # Time in different power states |
| 338system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 336system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 339system.physmem_0.memoryStateTime::ACT 244280410221 # Time in different power states | 337system.physmem_0.memoryStateTime::ACT 221716854896 # Time in different power states |
| 340system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 338system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 341system.physmem_1.actEnergy 3749639040 # Energy for activate commands per rank (pJ) 342system.physmem_1.preEnergy 2045934000 # Energy for precharge commands per rank (pJ) 343system.physmem_1.readEnergy 4039144200 # Energy for read commands per rank (pJ) 344system.physmem_1.writeEnergy 5720654160 # Energy for write commands per rank (pJ) 345system.physmem_1.refreshEnergy 3098754740640 # Energy for refresh commands per rank (pJ) 346system.physmem_1.actBackEnergy 1188668792790 # Energy for active background per rank (pJ) 347system.physmem_1.preBackEnergy 27423187293750 # Energy for precharge background per rank (pJ) 348system.physmem_1.totalEnergy 31726166198580 # Total energy per rank (pJ) 349system.physmem_1.averagePower 668.719894 # Core power per rank (mW) 350system.physmem_1.memoryStateTime::IDLE 45620445429017 # Time in different power states 351system.physmem_1.memoryStateTime::REF 1584230440000 # Time in different power states | 339system.physmem_1.actEnergy 3039558480 # Energy for activate commands per rank (pJ) 340system.physmem_1.preEnergy 1658489250 # Energy for precharge commands per rank (pJ) 341system.physmem_1.readEnergy 3100125600 # Energy for read commands per rank (pJ) 342system.physmem_1.writeEnergy 4989373200 # Energy for write commands per rank (pJ) 343system.physmem_1.refreshEnergy 3093712876800 # Energy for refresh commands per rank (pJ) 344system.physmem_1.actBackEnergy 1167524389710 # Energy for active background per rank (pJ) 345system.physmem_1.preBackEnergy 27395419294500 # Energy for precharge background per rank (pJ) 346system.physmem_1.totalEnergy 31669444107540 # Total energy per rank (pJ) 347system.physmem_1.averagePower 668.612186 # Core power per rank (mW) 348system.physmem_1.memoryStateTime::IDLE 45574402608448 # Time in different power states 349system.physmem_1.memoryStateTime::REF 1581652800000 # Time in different power states |
| 352system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 350system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 353system.physmem_1.memoryStateTime::ACT 238458431983 # Time in different power states | 351system.physmem_1.memoryStateTime::ACT 209885438552 # Time in different power states |
| 354system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 355system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 356system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 357system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 358system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 359system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 360system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 361system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory --- 17 unchanged lines hidden (view full) --- 379system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 380system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 381system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 382system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 383system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 384system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. 385system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. 386system.cf0.dma_write_txs 1674 # Number of DMA write transactions. | 352system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 353system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory 354system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 355system.realview.nvmem.bytes_read::cpu1.inst 576 # Number of bytes read from this memory 356system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 357system.realview.nvmem.bytes_read::total 1324 # Number of bytes read from this memory 358system.realview.nvmem.bytes_inst_read::cpu0.inst 704 # Number of instructions bytes read from this memory 359system.realview.nvmem.bytes_inst_read::cpu1.inst 576 # Number of instructions bytes read from this memory --- 17 unchanged lines hidden (view full) --- 377system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 378system.realview.nvmem.bw_total::total 28 # Total bandwidth to/from this memory (bytes/s) 379system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 380system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 381system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 382system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes. 383system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes. 384system.cf0.dma_write_txs 1674 # Number of DMA write transactions. |
| 387system.cpu0.branchPred.lookups 130059643 # Number of BP lookups 388system.cpu0.branchPred.condPredicted 92054393 # Number of conditional branches predicted 389system.cpu0.branchPred.condIncorrect 5970282 # Number of conditional branches incorrect 390system.cpu0.branchPred.BTBLookups 98035548 # Number of BTB lookups 391system.cpu0.branchPred.BTBHits 70777475 # Number of BTB hits | 385system.cpu0.branchPred.lookups 133649210 # Number of BP lookups 386system.cpu0.branchPred.condPredicted 93568356 # Number of conditional branches predicted 387system.cpu0.branchPred.condIncorrect 6412350 # Number of conditional branches incorrect 388system.cpu0.branchPred.BTBLookups 100434532 # Number of BTB lookups 389system.cpu0.branchPred.BTBHits 71867706 # Number of BTB hits |
| 392system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 390system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 393system.cpu0.branchPred.BTBHitPct 72.195725 # BTB Hit Percentage 394system.cpu0.branchPred.usedRAS 15296635 # Number of times the RAS was used to get a target. 395system.cpu0.branchPred.RASInCorrect 1065115 # Number of incorrect RAS predictions. | 391system.cpu0.branchPred.BTBHitPct 71.556769 # BTB Hit Percentage 392system.cpu0.branchPred.usedRAS 16148203 # Number of times the RAS was used to get a target. 393system.cpu0.branchPred.RASInCorrect 1115497 # Number of incorrect RAS predictions. |
| 396system.cpu_clk_domain.clock 500 # Clock period in ticks 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 401system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 402system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 403system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 418system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 419system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 420system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 421system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 422system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 423system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 424system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 425system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 394system.cpu_clk_domain.clock 500 # Clock period in ticks 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 400system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 401system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 416system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 417system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 418system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 419system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 420system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 421system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 422system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 423system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 426system.cpu0.dtb.walker.walks 268213 # Table walker walks requested 427system.cpu0.dtb.walker.walksLong 268213 # Table walker walks initiated with long descriptors 428system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8180 # Level at which table walker walks with long descriptors terminate 429system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 73055 # Level at which table walker walks with long descriptors terminate 430system.cpu0.dtb.walker.walkWaitTime::samples 268213 # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkWaitTime::0 268213 100.00% 100.00% # Table walker wait (enqueue to first request) latency 432system.cpu0.dtb.walker.walkWaitTime::total 268213 # Table walker wait (enqueue to first request) latency 433system.cpu0.dtb.walker.walkCompletionTime::samples 81235 # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::mean 18802.895870 # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::gmean 17058.372218 # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::stdev 13418.609606 # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::0-65535 80487 99.08% 99.08% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::65536-131071 639 0.79% 99.87% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::131072-196607 31 0.04% 99.90% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::196608-262143 33 0.04% 99.94% # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::262144-327679 28 0.03% 99.98% # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.99% # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::total 81235 # Table walker service (enqueue to completion) latency | 424system.cpu0.dtb.walker.walks 281840 # Table walker walks requested 425system.cpu0.dtb.walker.walksLong 281840 # Table walker walks initiated with long descriptors 426system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8577 # Level at which table walker walks with long descriptors terminate 427system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76588 # Level at which table walker walks with long descriptors terminate 428system.cpu0.dtb.walker.walkWaitTime::samples 281840 # Table walker wait (enqueue to first request) latency 429system.cpu0.dtb.walker.walkWaitTime::0 281840 100.00% 100.00% # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkWaitTime::total 281840 # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkCompletionTime::samples 85165 # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::mean 18850.134868 # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::gmean 17191.967454 # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::stdev 12262.040349 # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::0-32767 80924 95.02% 95.02% # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3552 4.17% 99.19% # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::65536-98303 385 0.45% 99.64% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::98304-131071 201 0.24% 99.88% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::131072-163839 20 0.02% 99.90% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::163840-196607 10 0.01% 99.91% # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::196608-229375 25 0.03% 99.94% # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::229376-262143 15 0.02% 99.96% # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::262144-294911 9 0.01% 99.97% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::294912-327679 16 0.02% 99.99% # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::total 85165 # Table walker service (enqueue to completion) latency |
| 447system.cpu0.dtb.walker.walksPending::samples 788586204 # Table walker pending requests distribution 448system.cpu0.dtb.walker.walksPending::0 788586204 100.00% 100.00% # Table walker pending requests distribution 449system.cpu0.dtb.walker.walksPending::total 788586204 # Table walker pending requests distribution | 451system.cpu0.dtb.walker.walksPending::samples 788586204 # Table walker pending requests distribution 452system.cpu0.dtb.walker.walksPending::0 788586204 100.00% 100.00% # Table walker pending requests distribution 453system.cpu0.dtb.walker.walksPending::total 788586204 # Table walker pending requests distribution |
| 450system.cpu0.dtb.walker.walkPageSizes::4K 73055 89.93% 89.93% # Table walker page sizes translated 451system.cpu0.dtb.walker.walkPageSizes::2M 8180 10.07% 100.00% # Table walker page sizes translated 452system.cpu0.dtb.walker.walkPageSizes::total 81235 # Table walker page sizes translated 453system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 268213 # Table walker requests started/completed, data/inst | 454system.cpu0.dtb.walker.walkPageSizes::4K 76588 89.93% 89.93% # Table walker page sizes translated 455system.cpu0.dtb.walker.walkPageSizes::2M 8577 10.07% 100.00% # Table walker page sizes translated 456system.cpu0.dtb.walker.walkPageSizes::total 85165 # Table walker page sizes translated 457system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 281840 # Table walker requests started/completed, data/inst |
| 454system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 458system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 455system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 268213 # Table walker requests started/completed, data/inst 456system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 81235 # Table walker requests started/completed, data/inst | 459system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 281840 # Table walker requests started/completed, data/inst 460system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85165 # Table walker requests started/completed, data/inst |
| 457system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 461system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 458system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 81235 # Table walker requests started/completed, data/inst 459system.cpu0.dtb.walker.walkRequestOrigin::total 349448 # Table walker requests started/completed, data/inst | 462system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85165 # Table walker requests started/completed, data/inst 463system.cpu0.dtb.walker.walkRequestOrigin::total 367005 # Table walker requests started/completed, data/inst |
| 460system.cpu0.dtb.inst_hits 0 # ITB inst hits 461system.cpu0.dtb.inst_misses 0 # ITB inst misses | 464system.cpu0.dtb.inst_hits 0 # ITB inst hits 465system.cpu0.dtb.inst_misses 0 # ITB inst misses |
| 462system.cpu0.dtb.read_hits 82876233 # DTB read hits 463system.cpu0.dtb.read_misses 221834 # DTB read misses 464system.cpu0.dtb.write_hits 73950839 # DTB write hits 465system.cpu0.dtb.write_misses 46379 # DTB write misses | 466system.cpu0.dtb.read_hits 86621651 # DTB read hits 467system.cpu0.dtb.read_misses 235326 # DTB read misses 468system.cpu0.dtb.write_hits 77269391 # DTB write hits 469system.cpu0.dtb.write_misses 46514 # DTB write misses |
| 466system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 467system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 470system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 471system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 468system.cpu0.dtb.flush_tlb_mva_asid 41692 # Number of times TLB was flushed by MVA & ASID 469system.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID 470system.cpu0.dtb.flush_entries 33850 # Number of entries that have been flushed from TLB 471system.cpu0.dtb.align_faults 2174 # Number of TLB faults due to alignment restrictions 472system.cpu0.dtb.prefetch_faults 9634 # Number of TLB faults due to prefetch | 472system.cpu0.dtb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID 473system.cpu0.dtb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID 474system.cpu0.dtb.flush_entries 36825 # Number of entries that have been flushed from TLB 475system.cpu0.dtb.align_faults 2231 # Number of TLB faults due to alignment restrictions 476system.cpu0.dtb.prefetch_faults 9213 # Number of TLB faults due to prefetch |
| 473system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 477system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 474system.cpu0.dtb.perms_faults 10897 # Number of TLB faults due to permissions restrictions 475system.cpu0.dtb.read_accesses 83098067 # DTB read accesses 476system.cpu0.dtb.write_accesses 73997218 # DTB write accesses | 478system.cpu0.dtb.perms_faults 11443 # Number of TLB faults due to permissions restrictions 479system.cpu0.dtb.read_accesses 86856977 # DTB read accesses 480system.cpu0.dtb.write_accesses 77315905 # DTB write accesses |
| 477system.cpu0.dtb.inst_accesses 0 # ITB inst accesses | 481system.cpu0.dtb.inst_accesses 0 # ITB inst accesses |
| 478system.cpu0.dtb.hits 156827072 # DTB hits 479system.cpu0.dtb.misses 268213 # DTB misses 480system.cpu0.dtb.accesses 157095285 # DTB accesses | 482system.cpu0.dtb.hits 163891042 # DTB hits 483system.cpu0.dtb.misses 281840 # DTB misses 484system.cpu0.dtb.accesses 164172882 # DTB accesses |
| 481system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 502system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 503system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 504system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 505system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 506system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 507system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 508system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 509system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 485system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 488system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 489system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 490system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 491system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 492system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 506system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 507system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 508system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 509system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 510system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 511system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 512system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 513system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 510system.cpu0.itb.walker.walks 59559 # Table walker walks requested 511system.cpu0.itb.walker.walksLong 59559 # Table walker walks initiated with long descriptors 512system.cpu0.itb.walker.walksLongTerminationLevel::Level2 562 # Level at which table walker walks with long descriptors terminate 513system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52025 # Level at which table walker walks with long descriptors terminate 514system.cpu0.itb.walker.walkWaitTime::samples 59559 # Table walker wait (enqueue to first request) latency 515system.cpu0.itb.walker.walkWaitTime::0 59559 100.00% 100.00% # Table walker wait (enqueue to first request) latency 516system.cpu0.itb.walker.walkWaitTime::total 59559 # Table walker wait (enqueue to first request) latency 517system.cpu0.itb.walker.walkCompletionTime::samples 52587 # Table walker service (enqueue to completion) latency 518system.cpu0.itb.walker.walkCompletionTime::mean 21528.762508 # Table walker service (enqueue to completion) latency 519system.cpu0.itb.walker.walkCompletionTime::gmean 19318.036298 # Table walker service (enqueue to completion) latency 520system.cpu0.itb.walker.walkCompletionTime::stdev 15879.557576 # Table walker service (enqueue to completion) latency 521system.cpu0.itb.walker.walkCompletionTime::0-32767 47969 91.22% 91.22% # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walkCompletionTime::32768-65535 3703 7.04% 98.26% # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walkCompletionTime::65536-98303 280 0.53% 98.79% # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walkCompletionTime::98304-131071 523 0.99% 99.79% # Table walker service (enqueue to completion) latency 525system.cpu0.itb.walker.walkCompletionTime::131072-163839 24 0.05% 99.83% # Table walker service (enqueue to completion) latency 526system.cpu0.itb.walker.walkCompletionTime::163840-196607 24 0.05% 99.88% # Table walker service (enqueue to completion) latency 527system.cpu0.itb.walker.walkCompletionTime::196608-229375 27 0.05% 99.93% # Table walker service (enqueue to completion) latency 528system.cpu0.itb.walker.walkCompletionTime::229376-262143 16 0.03% 99.96% # Table walker service (enqueue to completion) latency 529system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.97% # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.98% # Table walker service (enqueue to completion) latency 531system.cpu0.itb.walker.walkCompletionTime::327680-360447 8 0.02% 99.99% # Table walker service (enqueue to completion) latency 532system.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.01% 100.00% # Table walker service (enqueue to completion) latency | 514system.cpu0.itb.walker.walks 66347 # Table walker walks requested 515system.cpu0.itb.walker.walksLong 66347 # Table walker walks initiated with long descriptors 516system.cpu0.itb.walker.walksLongTerminationLevel::Level2 679 # Level at which table walker walks with long descriptors terminate 517system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58898 # Level at which table walker walks with long descriptors terminate 518system.cpu0.itb.walker.walkWaitTime::samples 66347 # Table walker wait (enqueue to first request) latency 519system.cpu0.itb.walker.walkWaitTime::0 66347 100.00% 100.00% # Table walker wait (enqueue to first request) latency 520system.cpu0.itb.walker.walkWaitTime::total 66347 # Table walker wait (enqueue to first request) latency 521system.cpu0.itb.walker.walkCompletionTime::samples 59577 # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walkCompletionTime::mean 21233.631049 # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walkCompletionTime::gmean 19420.255520 # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walkCompletionTime::stdev 13392.583355 # Table walker service (enqueue to completion) latency 525system.cpu0.itb.walker.walkCompletionTime::0-32767 54894 92.14% 92.14% # Table walker service (enqueue to completion) latency 526system.cpu0.itb.walker.walkCompletionTime::32768-65535 3878 6.51% 98.65% # Table walker service (enqueue to completion) latency 527system.cpu0.itb.walker.walkCompletionTime::65536-98303 278 0.47% 99.12% # Table walker service (enqueue to completion) latency 528system.cpu0.itb.walker.walkCompletionTime::98304-131071 464 0.78% 99.89% # Table walker service (enqueue to completion) latency 529system.cpu0.itb.walker.walkCompletionTime::131072-163839 13 0.02% 99.92% # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walkCompletionTime::163840-196607 10 0.02% 99.93% # Table walker service (enqueue to completion) latency 531system.cpu0.itb.walker.walkCompletionTime::196608-229375 21 0.04% 99.97% # Table walker service (enqueue to completion) latency 532system.cpu0.itb.walker.walkCompletionTime::229376-262143 10 0.02% 99.98% # Table walker service (enqueue to completion) latency 533system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.99% # Table walker service (enqueue to completion) latency 534system.cpu0.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.99% # Table walker service (enqueue to completion) latency 535system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 536system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency |
| 533system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency | 537system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency |
| 534system.cpu0.itb.walker.walkCompletionTime::total 52587 # Table walker service (enqueue to completion) latency | 538system.cpu0.itb.walker.walkCompletionTime::total 59577 # Table walker service (enqueue to completion) latency |
| 535system.cpu0.itb.walker.walksPending::samples 787865704 # Table walker pending requests distribution 536system.cpu0.itb.walker.walksPending::0 787865704 100.00% 100.00% # Table walker pending requests distribution 537system.cpu0.itb.walker.walksPending::total 787865704 # Table walker pending requests distribution | 539system.cpu0.itb.walker.walksPending::samples 787865704 # Table walker pending requests distribution 540system.cpu0.itb.walker.walksPending::0 787865704 100.00% 100.00% # Table walker pending requests distribution 541system.cpu0.itb.walker.walksPending::total 787865704 # Table walker pending requests distribution |
| 538system.cpu0.itb.walker.walkPageSizes::4K 52025 98.93% 98.93% # Table walker page sizes translated 539system.cpu0.itb.walker.walkPageSizes::2M 562 1.07% 100.00% # Table walker page sizes translated 540system.cpu0.itb.walker.walkPageSizes::total 52587 # Table walker page sizes translated | 542system.cpu0.itb.walker.walkPageSizes::4K 58898 98.86% 98.86% # Table walker page sizes translated 543system.cpu0.itb.walker.walkPageSizes::2M 679 1.14% 100.00% # Table walker page sizes translated 544system.cpu0.itb.walker.walkPageSizes::total 59577 # Table walker page sizes translated |
| 541system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 545system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 542system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 59559 # Table walker requests started/completed, data/inst 543system.cpu0.itb.walker.walkRequestOrigin_Requested::total 59559 # Table walker requests started/completed, data/inst | 546system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66347 # Table walker requests started/completed, data/inst 547system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66347 # Table walker requests started/completed, data/inst |
| 544system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 548system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 545system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52587 # Table walker requests started/completed, data/inst 546system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52587 # Table walker requests started/completed, data/inst 547system.cpu0.itb.walker.walkRequestOrigin::total 112146 # Table walker requests started/completed, data/inst 548system.cpu0.itb.inst_hits 232580630 # ITB inst hits 549system.cpu0.itb.inst_misses 59559 # ITB inst misses | 549system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59577 # Table walker requests started/completed, data/inst 550system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59577 # Table walker requests started/completed, data/inst 551system.cpu0.itb.walker.walkRequestOrigin::total 125924 # Table walker requests started/completed, data/inst 552system.cpu0.itb.inst_hits 239632917 # ITB inst hits 553system.cpu0.itb.inst_misses 66347 # ITB inst misses |
| 550system.cpu0.itb.read_hits 0 # DTB read hits 551system.cpu0.itb.read_misses 0 # DTB read misses 552system.cpu0.itb.write_hits 0 # DTB write hits 553system.cpu0.itb.write_misses 0 # DTB write misses 554system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 555system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 554system.cpu0.itb.read_hits 0 # DTB read hits 555system.cpu0.itb.read_misses 0 # DTB read misses 556system.cpu0.itb.write_hits 0 # DTB write hits 557system.cpu0.itb.write_misses 0 # DTB write misses 558system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 559system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 556system.cpu0.itb.flush_tlb_mva_asid 41692 # Number of times TLB was flushed by MVA & ASID 557system.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID 558system.cpu0.itb.flush_entries 23871 # Number of entries that have been flushed from TLB | 560system.cpu0.itb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID 561system.cpu0.itb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID 562system.cpu0.itb.flush_entries 26379 # Number of entries that have been flushed from TLB |
| 559system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 560system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 561system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 563system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 564system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 565system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 562system.cpu0.itb.perms_faults 192056 # Number of TLB faults due to permissions restrictions | 566system.cpu0.itb.perms_faults 196328 # Number of TLB faults due to permissions restrictions |
| 563system.cpu0.itb.read_accesses 0 # DTB read accesses 564system.cpu0.itb.write_accesses 0 # DTB write accesses | 567system.cpu0.itb.read_accesses 0 # DTB read accesses 568system.cpu0.itb.write_accesses 0 # DTB write accesses |
| 565system.cpu0.itb.inst_accesses 232640189 # ITB inst accesses 566system.cpu0.itb.hits 232580630 # DTB hits 567system.cpu0.itb.misses 59559 # DTB misses 568system.cpu0.itb.accesses 232640189 # DTB accesses 569system.cpu0.numCycles 928928804 # number of cpu cycles simulated | 569system.cpu0.itb.inst_accesses 239699264 # ITB inst accesses 570system.cpu0.itb.hits 239632917 # DTB hits 571system.cpu0.itb.misses 66347 # DTB misses 572system.cpu0.itb.accesses 239699264 # DTB accesses 573system.cpu0.numCycles 955623985 # number of cpu cycles simulated |
| 570system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 571system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed | 574system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 575system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 572system.cpu0.committedInsts 429144762 # Number of instructions committed 573system.cpu0.committedOps 504441860 # Number of ops (including micro ops) committed 574system.cpu0.discardedOps 43734034 # Number of ops (including micro ops) which were discarded before commit 575system.cpu0.numFetchSuspends 3788 # Number of times Execute suspended instruction fetching 576system.cpu0.quiesceCycles 93957994041 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 577system.cpu0.cpi 2.164605 # CPI: cycles per instruction 578system.cpu0.ipc 0.461978 # IPC: instructions per cycle | 576system.cpu0.committedInsts 445844997 # Number of instructions committed 577system.cpu0.committedOps 524389125 # Number of ops (including micro ops) committed 578system.cpu0.discardedOps 43457031 # Number of ops (including micro ops) which were discarded before commit 579system.cpu0.numFetchSuspends 4220 # Number of times Execute suspended instruction fetching 580system.cpu0.quiesceCycles 93776986984 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 581system.cpu0.cpi 2.143400 # CPI: cycles per instruction 582system.cpu0.ipc 0.466549 # IPC: instructions per cycle |
| 579system.cpu0.kern.inst.arm 0 # number of arm instructions executed | 583system.cpu0.kern.inst.arm 0 # number of arm instructions executed |
| 580system.cpu0.kern.inst.quiesce 12678 # number of quiesce instructions executed 581system.cpu0.tickCycles 694752800 # Number of cycles that the object actually ticked 582system.cpu0.idleCycles 234176004 # Total number of cycles that the object has spent stopped 583system.cpu0.dcache.tags.replacements 5394073 # number of replacements 584system.cpu0.dcache.tags.tagsinuse 480.331401 # Cycle average of tags in use 585system.cpu0.dcache.tags.total_refs 148625740 # Total number of references to valid blocks. 586system.cpu0.dcache.tags.sampled_refs 5394584 # Sample count of references to valid blocks. 587system.cpu0.dcache.tags.avg_refs 27.550918 # Average number of references to valid blocks. 588system.cpu0.dcache.tags.warmup_cycle 5096417500 # Cycle when the warmup percentage was hit. 589system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.331401 # Average occupied blocks per requestor 590system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938147 # Average percentage of cache occupancy 591system.cpu0.dcache.tags.occ_percent::total 0.938147 # Average percentage of cache occupancy | 584system.cpu0.kern.inst.quiesce 13187 # number of quiesce instructions executed 585system.cpu0.tickCycles 717454138 # Number of cycles that the object actually ticked 586system.cpu0.idleCycles 238169847 # Total number of cycles that the object has spent stopped 587system.cpu0.dcache.tags.replacements 5506052 # number of replacements 588system.cpu0.dcache.tags.tagsinuse 502.001203 # Cycle average of tags in use 589system.cpu0.dcache.tags.total_refs 155497940 # Total number of references to valid blocks. 590system.cpu0.dcache.tags.sampled_refs 5506563 # Sample count of references to valid blocks. 591system.cpu0.dcache.tags.avg_refs 28.238656 # Average number of references to valid blocks. 592system.cpu0.dcache.tags.warmup_cycle 5093256500 # Cycle when the warmup percentage was hit. 593system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.001203 # Average occupied blocks per requestor 594system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980471 # Average percentage of cache occupancy 595system.cpu0.dcache.tags.occ_percent::total 0.980471 # Average percentage of cache occupancy |
| 592system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id | 596system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id |
| 593system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 594system.cpu0.dcache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id 595system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id | 597system.cpu0.dcache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id 598system.cpu0.dcache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id 599system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id |
| 596system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id | 600system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id |
| 597system.cpu0.dcache.tags.tag_accesses 316412315 # Number of tag accesses 598system.cpu0.dcache.tags.data_accesses 316412315 # Number of data accesses 599system.cpu0.dcache.ReadReq_hits::cpu0.data 75879605 # number of ReadReq hits 600system.cpu0.dcache.ReadReq_hits::total 75879605 # number of ReadReq hits 601system.cpu0.dcache.WriteReq_hits::cpu0.data 68405292 # number of WriteReq hits 602system.cpu0.dcache.WriteReq_hits::total 68405292 # number of WriteReq hits 603system.cpu0.dcache.SoftPFReq_hits::cpu0.data 266627 # number of SoftPFReq hits 604system.cpu0.dcache.SoftPFReq_hits::total 266627 # number of SoftPFReq hits 605system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 249000 # number of WriteInvalidateReq hits 606system.cpu0.dcache.WriteInvalidateReq_hits::total 249000 # number of WriteInvalidateReq hits 607system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1685353 # number of LoadLockedReq hits 608system.cpu0.dcache.LoadLockedReq_hits::total 1685353 # number of LoadLockedReq hits 609system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1648257 # number of StoreCondReq hits 610system.cpu0.dcache.StoreCondReq_hits::total 1648257 # number of StoreCondReq hits 611system.cpu0.dcache.demand_hits::cpu0.data 144284897 # number of demand (read+write) hits 612system.cpu0.dcache.demand_hits::total 144284897 # number of demand (read+write) hits 613system.cpu0.dcache.overall_hits::cpu0.data 144551524 # number of overall hits 614system.cpu0.dcache.overall_hits::total 144551524 # number of overall hits 615system.cpu0.dcache.ReadReq_misses::cpu0.data 3254530 # number of ReadReq misses 616system.cpu0.dcache.ReadReq_misses::total 3254530 # number of ReadReq misses 617system.cpu0.dcache.WriteReq_misses::cpu0.data 2315784 # number of WriteReq misses 618system.cpu0.dcache.WriteReq_misses::total 2315784 # number of WriteReq misses 619system.cpu0.dcache.SoftPFReq_misses::cpu0.data 640707 # number of SoftPFReq misses 620system.cpu0.dcache.SoftPFReq_misses::total 640707 # number of SoftPFReq misses 621system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 788472 # number of WriteInvalidateReq misses 622system.cpu0.dcache.WriteInvalidateReq_misses::total 788472 # number of WriteInvalidateReq misses 623system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 144645 # number of LoadLockedReq misses 624system.cpu0.dcache.LoadLockedReq_misses::total 144645 # number of LoadLockedReq misses 625system.cpu0.dcache.StoreCondReq_misses::cpu0.data 180684 # number of StoreCondReq misses 626system.cpu0.dcache.StoreCondReq_misses::total 180684 # number of StoreCondReq misses 627system.cpu0.dcache.demand_misses::cpu0.data 5570314 # number of demand (read+write) misses 628system.cpu0.dcache.demand_misses::total 5570314 # number of demand (read+write) misses 629system.cpu0.dcache.overall_misses::cpu0.data 6211021 # number of overall misses 630system.cpu0.dcache.overall_misses::total 6211021 # number of overall misses 631system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 49481056746 # number of ReadReq miss cycles 632system.cpu0.dcache.ReadReq_miss_latency::total 49481056746 # number of ReadReq miss cycles 633system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 45032988844 # number of WriteReq miss cycles 634system.cpu0.dcache.WriteReq_miss_latency::total 45032988844 # number of WriteReq miss cycles 635system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 32697185728 # number of WriteInvalidateReq miss cycles 636system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 32697185728 # number of WriteInvalidateReq miss cycles 637system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2134918217 # number of LoadLockedReq miss cycles 638system.cpu0.dcache.LoadLockedReq_miss_latency::total 2134918217 # number of LoadLockedReq miss cycles 639system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3848217698 # number of StoreCondReq miss cycles 640system.cpu0.dcache.StoreCondReq_miss_latency::total 3848217698 # number of StoreCondReq miss cycles 641system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3587000 # number of StoreCondFailReq miss cycles 642system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3587000 # number of StoreCondFailReq miss cycles 643system.cpu0.dcache.demand_miss_latency::cpu0.data 94514045590 # number of demand (read+write) miss cycles 644system.cpu0.dcache.demand_miss_latency::total 94514045590 # number of demand (read+write) miss cycles 645system.cpu0.dcache.overall_miss_latency::cpu0.data 94514045590 # number of overall miss cycles 646system.cpu0.dcache.overall_miss_latency::total 94514045590 # number of overall miss cycles 647system.cpu0.dcache.ReadReq_accesses::cpu0.data 79134135 # number of ReadReq accesses(hits+misses) 648system.cpu0.dcache.ReadReq_accesses::total 79134135 # number of ReadReq accesses(hits+misses) 649system.cpu0.dcache.WriteReq_accesses::cpu0.data 70721076 # number of WriteReq accesses(hits+misses) 650system.cpu0.dcache.WriteReq_accesses::total 70721076 # number of WriteReq accesses(hits+misses) 651system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 907334 # number of SoftPFReq accesses(hits+misses) 652system.cpu0.dcache.SoftPFReq_accesses::total 907334 # number of SoftPFReq accesses(hits+misses) 653system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1037472 # number of WriteInvalidateReq accesses(hits+misses) 654system.cpu0.dcache.WriteInvalidateReq_accesses::total 1037472 # number of WriteInvalidateReq accesses(hits+misses) 655system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1829998 # number of LoadLockedReq accesses(hits+misses) 656system.cpu0.dcache.LoadLockedReq_accesses::total 1829998 # number of LoadLockedReq accesses(hits+misses) 657system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1828941 # number of StoreCondReq accesses(hits+misses) 658system.cpu0.dcache.StoreCondReq_accesses::total 1828941 # number of StoreCondReq accesses(hits+misses) 659system.cpu0.dcache.demand_accesses::cpu0.data 149855211 # number of demand (read+write) accesses 660system.cpu0.dcache.demand_accesses::total 149855211 # number of demand (read+write) accesses 661system.cpu0.dcache.overall_accesses::cpu0.data 150762545 # number of overall (read+write) accesses 662system.cpu0.dcache.overall_accesses::total 150762545 # number of overall (read+write) accesses 663system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.041127 # miss rate for ReadReq accesses 664system.cpu0.dcache.ReadReq_miss_rate::total 0.041127 # miss rate for ReadReq accesses 665system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032745 # miss rate for WriteReq accesses 666system.cpu0.dcache.WriteReq_miss_rate::total 0.032745 # miss rate for WriteReq accesses 667system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.706142 # miss rate for SoftPFReq accesses 668system.cpu0.dcache.SoftPFReq_miss_rate::total 0.706142 # miss rate for SoftPFReq accesses 669system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.759994 # miss rate for WriteInvalidateReq accesses 670system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.759994 # miss rate for WriteInvalidateReq accesses 671system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.079041 # miss rate for LoadLockedReq accesses 672system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.079041 # miss rate for LoadLockedReq accesses 673system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098792 # miss rate for StoreCondReq accesses 674system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098792 # miss rate for StoreCondReq accesses 675system.cpu0.dcache.demand_miss_rate::cpu0.data 0.037171 # miss rate for demand accesses 676system.cpu0.dcache.demand_miss_rate::total 0.037171 # miss rate for demand accesses 677system.cpu0.dcache.overall_miss_rate::cpu0.data 0.041197 # miss rate for overall accesses 678system.cpu0.dcache.overall_miss_rate::total 0.041197 # miss rate for overall accesses 679system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15203.748850 # average ReadReq miss latency 680system.cpu0.dcache.ReadReq_avg_miss_latency::total 15203.748850 # average ReadReq miss latency 681system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19446.109328 # average WriteReq miss latency 682system.cpu0.dcache.WriteReq_avg_miss_latency::total 19446.109328 # average WriteReq miss latency 683system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41469.051188 # average WriteInvalidateReq miss latency 684system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41469.051188 # average WriteInvalidateReq miss latency 685system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14759.709751 # average LoadLockedReq miss latency 686system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14759.709751 # average LoadLockedReq miss latency 687system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21298.054604 # average StoreCondReq miss latency 688system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21298.054604 # average StoreCondReq miss latency | 601system.cpu0.dcache.tags.tag_accesses 330491760 # Number of tag accesses 602system.cpu0.dcache.tags.data_accesses 330491760 # Number of data accesses 603system.cpu0.dcache.ReadReq_hits::cpu0.data 79543100 # number of ReadReq hits 604system.cpu0.dcache.ReadReq_hits::total 79543100 # number of ReadReq hits 605system.cpu0.dcache.WriteReq_hits::cpu0.data 71719508 # number of WriteReq hits 606system.cpu0.dcache.WriteReq_hits::total 71719508 # number of WriteReq hits 607system.cpu0.dcache.SoftPFReq_hits::cpu0.data 278613 # number of SoftPFReq hits 608system.cpu0.dcache.SoftPFReq_hits::total 278613 # number of SoftPFReq hits 609system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 256505 # number of WriteInvalidateReq hits 610system.cpu0.dcache.WriteInvalidateReq_hits::total 256505 # number of WriteInvalidateReq hits 611system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1617523 # number of LoadLockedReq hits 612system.cpu0.dcache.LoadLockedReq_hits::total 1617523 # number of LoadLockedReq hits 613system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1589938 # number of StoreCondReq hits 614system.cpu0.dcache.StoreCondReq_hits::total 1589938 # number of StoreCondReq hits 615system.cpu0.dcache.demand_hits::cpu0.data 151262608 # number of demand (read+write) hits 616system.cpu0.dcache.demand_hits::total 151262608 # number of demand (read+write) hits 617system.cpu0.dcache.overall_hits::cpu0.data 151541221 # number of overall hits 618system.cpu0.dcache.overall_hits::total 151541221 # number of overall hits 619system.cpu0.dcache.ReadReq_misses::cpu0.data 3339841 # number of ReadReq misses 620system.cpu0.dcache.ReadReq_misses::total 3339841 # number of ReadReq misses 621system.cpu0.dcache.WriteReq_misses::cpu0.data 2311852 # number of WriteReq misses 622system.cpu0.dcache.WriteReq_misses::total 2311852 # number of WriteReq misses 623system.cpu0.dcache.SoftPFReq_misses::cpu0.data 620748 # number of SoftPFReq misses 624system.cpu0.dcache.SoftPFReq_misses::total 620748 # number of SoftPFReq misses 625system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 822680 # number of WriteInvalidateReq misses 626system.cpu0.dcache.WriteInvalidateReq_misses::total 822680 # number of WriteInvalidateReq misses 627system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 157499 # number of LoadLockedReq misses 628system.cpu0.dcache.LoadLockedReq_misses::total 157499 # number of LoadLockedReq misses 629system.cpu0.dcache.StoreCondReq_misses::cpu0.data 183638 # number of StoreCondReq misses 630system.cpu0.dcache.StoreCondReq_misses::total 183638 # number of StoreCondReq misses 631system.cpu0.dcache.demand_misses::cpu0.data 5651693 # number of demand (read+write) misses 632system.cpu0.dcache.demand_misses::total 5651693 # number of demand (read+write) misses 633system.cpu0.dcache.overall_misses::cpu0.data 6272441 # number of overall misses 634system.cpu0.dcache.overall_misses::total 6272441 # number of overall misses 635system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 49670372012 # number of ReadReq miss cycles 636system.cpu0.dcache.ReadReq_miss_latency::total 49670372012 # number of ReadReq miss cycles 637system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 43497452544 # number of WriteReq miss cycles 638system.cpu0.dcache.WriteReq_miss_latency::total 43497452544 # number of WriteReq miss cycles 639system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 32835554230 # number of WriteInvalidateReq miss cycles 640system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 32835554230 # number of WriteInvalidateReq miss cycles 641system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2312206455 # number of LoadLockedReq miss cycles 642system.cpu0.dcache.LoadLockedReq_miss_latency::total 2312206455 # number of LoadLockedReq miss cycles 643system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3898320876 # number of StoreCondReq miss cycles 644system.cpu0.dcache.StoreCondReq_miss_latency::total 3898320876 # number of StoreCondReq miss cycles 645system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3663000 # number of StoreCondFailReq miss cycles 646system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3663000 # number of StoreCondFailReq miss cycles 647system.cpu0.dcache.demand_miss_latency::cpu0.data 93167824556 # number of demand (read+write) miss cycles 648system.cpu0.dcache.demand_miss_latency::total 93167824556 # number of demand (read+write) miss cycles 649system.cpu0.dcache.overall_miss_latency::cpu0.data 93167824556 # number of overall miss cycles 650system.cpu0.dcache.overall_miss_latency::total 93167824556 # number of overall miss cycles 651system.cpu0.dcache.ReadReq_accesses::cpu0.data 82882941 # number of ReadReq accesses(hits+misses) 652system.cpu0.dcache.ReadReq_accesses::total 82882941 # number of ReadReq accesses(hits+misses) 653system.cpu0.dcache.WriteReq_accesses::cpu0.data 74031360 # number of WriteReq accesses(hits+misses) 654system.cpu0.dcache.WriteReq_accesses::total 74031360 # number of WriteReq accesses(hits+misses) 655system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 899361 # number of SoftPFReq accesses(hits+misses) 656system.cpu0.dcache.SoftPFReq_accesses::total 899361 # number of SoftPFReq accesses(hits+misses) 657system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1079185 # number of WriteInvalidateReq accesses(hits+misses) 658system.cpu0.dcache.WriteInvalidateReq_accesses::total 1079185 # number of WriteInvalidateReq accesses(hits+misses) 659system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1775022 # number of LoadLockedReq accesses(hits+misses) 660system.cpu0.dcache.LoadLockedReq_accesses::total 1775022 # number of LoadLockedReq accesses(hits+misses) 661system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1773576 # number of StoreCondReq accesses(hits+misses) 662system.cpu0.dcache.StoreCondReq_accesses::total 1773576 # number of StoreCondReq accesses(hits+misses) 663system.cpu0.dcache.demand_accesses::cpu0.data 156914301 # number of demand (read+write) accesses 664system.cpu0.dcache.demand_accesses::total 156914301 # number of demand (read+write) accesses 665system.cpu0.dcache.overall_accesses::cpu0.data 157813662 # number of overall (read+write) accesses 666system.cpu0.dcache.overall_accesses::total 157813662 # number of overall (read+write) accesses 667system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.040296 # miss rate for ReadReq accesses 668system.cpu0.dcache.ReadReq_miss_rate::total 0.040296 # miss rate for ReadReq accesses 669system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031228 # miss rate for WriteReq accesses 670system.cpu0.dcache.WriteReq_miss_rate::total 0.031228 # miss rate for WriteReq accesses 671system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.690210 # miss rate for SoftPFReq accesses 672system.cpu0.dcache.SoftPFReq_miss_rate::total 0.690210 # miss rate for SoftPFReq accesses 673system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.762316 # miss rate for WriteInvalidateReq accesses 674system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.762316 # miss rate for WriteInvalidateReq accesses 675system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088731 # miss rate for LoadLockedReq accesses 676system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088731 # miss rate for LoadLockedReq accesses 677system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.103541 # miss rate for StoreCondReq accesses 678system.cpu0.dcache.StoreCondReq_miss_rate::total 0.103541 # miss rate for StoreCondReq accesses 679system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036018 # miss rate for demand accesses 680system.cpu0.dcache.demand_miss_rate::total 0.036018 # miss rate for demand accesses 681system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039746 # miss rate for overall accesses 682system.cpu0.dcache.overall_miss_rate::total 0.039746 # miss rate for overall accesses 683system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14872.076848 # average ReadReq miss latency 684system.cpu0.dcache.ReadReq_avg_miss_latency::total 14872.076848 # average ReadReq miss latency 685system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18814.981471 # average WriteReq miss latency 686system.cpu0.dcache.WriteReq_avg_miss_latency::total 18814.981471 # average WriteReq miss latency 687system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 39912.911740 # average WriteInvalidateReq miss latency 688system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 39912.911740 # average WriteInvalidateReq miss latency 689system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14680.769116 # average LoadLockedReq miss latency 690system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14680.769116 # average LoadLockedReq miss latency 691system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21228.290855 # average StoreCondReq miss latency 692system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21228.290855 # average StoreCondReq miss latency |
| 689system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 690system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 693system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 694system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 691system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16967.453826 # average overall miss latency 692system.cpu0.dcache.demand_avg_miss_latency::total 16967.453826 # average overall miss latency 693system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15217.151188 # average overall miss latency 694system.cpu0.dcache.overall_avg_miss_latency::total 15217.151188 # average overall miss latency | 695system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16484.940806 # average overall miss latency 696system.cpu0.dcache.demand_avg_miss_latency::total 16484.940806 # average overall miss latency 697system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14853.519476 # average overall miss latency 698system.cpu0.dcache.overall_avg_miss_latency::total 14853.519476 # average overall miss latency |
| 695system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 696system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 697system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 698system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 699system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 700system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 701system.cpu0.dcache.fast_writes 0 # number of fast writes performed 702system.cpu0.dcache.cache_copies 0 # number of cache copies performed | 699system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 700system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 701system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 702system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 703system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 704system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 705system.cpu0.dcache.fast_writes 0 # number of fast writes performed 706system.cpu0.dcache.cache_copies 0 # number of cache copies performed |
| 703system.cpu0.dcache.writebacks::writebacks 3714069 # number of writebacks 704system.cpu0.dcache.writebacks::total 3714069 # number of writebacks 705system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 414551 # number of ReadReq MSHR hits 706system.cpu0.dcache.ReadReq_mshr_hits::total 414551 # number of ReadReq MSHR hits 707system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 973091 # number of WriteReq MSHR hits 708system.cpu0.dcache.WriteReq_mshr_hits::total 973091 # number of WriteReq MSHR hits 709system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 89 # number of WriteInvalidateReq MSHR hits 710system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 89 # number of WriteInvalidateReq MSHR hits 711system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 40213 # number of LoadLockedReq MSHR hits 712system.cpu0.dcache.LoadLockedReq_mshr_hits::total 40213 # number of LoadLockedReq MSHR hits 713system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 42 # number of StoreCondReq MSHR hits 714system.cpu0.dcache.StoreCondReq_mshr_hits::total 42 # number of StoreCondReq MSHR hits 715system.cpu0.dcache.demand_mshr_hits::cpu0.data 1387642 # number of demand (read+write) MSHR hits 716system.cpu0.dcache.demand_mshr_hits::total 1387642 # number of demand (read+write) MSHR hits 717system.cpu0.dcache.overall_mshr_hits::cpu0.data 1387642 # number of overall MSHR hits 718system.cpu0.dcache.overall_mshr_hits::total 1387642 # number of overall MSHR hits 719system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2839979 # number of ReadReq MSHR misses 720system.cpu0.dcache.ReadReq_mshr_misses::total 2839979 # number of ReadReq MSHR misses 721system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1342693 # number of WriteReq MSHR misses 722system.cpu0.dcache.WriteReq_mshr_misses::total 1342693 # number of WriteReq MSHR misses 723system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 635024 # number of SoftPFReq MSHR misses 724system.cpu0.dcache.SoftPFReq_mshr_misses::total 635024 # number of SoftPFReq MSHR misses 725system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 788383 # number of WriteInvalidateReq MSHR misses 726system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 788383 # number of WriteInvalidateReq MSHR misses 727system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104432 # number of LoadLockedReq MSHR misses 728system.cpu0.dcache.LoadLockedReq_mshr_misses::total 104432 # number of LoadLockedReq MSHR misses 729system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 180642 # number of StoreCondReq MSHR misses 730system.cpu0.dcache.StoreCondReq_mshr_misses::total 180642 # number of StoreCondReq MSHR misses 731system.cpu0.dcache.demand_mshr_misses::cpu0.data 4182672 # number of demand (read+write) MSHR misses 732system.cpu0.dcache.demand_mshr_misses::total 4182672 # number of demand (read+write) MSHR misses 733system.cpu0.dcache.overall_mshr_misses::cpu0.data 4817696 # number of overall MSHR misses 734system.cpu0.dcache.overall_mshr_misses::total 4817696 # number of overall MSHR misses 735system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37224821633 # number of ReadReq MSHR miss cycles 736system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37224821633 # number of ReadReq MSHR miss cycles 737system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 24320285408 # number of WriteReq MSHR miss cycles 738system.cpu0.dcache.WriteReq_mshr_miss_latency::total 24320285408 # number of WriteReq MSHR miss cycles 739system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14430000107 # number of SoftPFReq MSHR miss cycles 740system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14430000107 # number of SoftPFReq MSHR miss cycles 741system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 31505168022 # number of WriteInvalidateReq MSHR miss cycles 742system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 31505168022 # number of WriteInvalidateReq MSHR miss cycles 743system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1352929391 # number of LoadLockedReq MSHR miss cycles 744system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1352929391 # number of LoadLockedReq MSHR miss cycles 745system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3566593771 # number of StoreCondReq MSHR miss cycles 746system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3566593771 # number of StoreCondReq MSHR miss cycles 747system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3248500 # number of StoreCondFailReq MSHR miss cycles 748system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3248500 # number of StoreCondFailReq MSHR miss cycles 749system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61545107041 # number of demand (read+write) MSHR miss cycles 750system.cpu0.dcache.demand_mshr_miss_latency::total 61545107041 # number of demand (read+write) MSHR miss cycles 751system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 75975107148 # number of overall MSHR miss cycles 752system.cpu0.dcache.overall_mshr_miss_latency::total 75975107148 # number of overall MSHR miss cycles 753system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5918601247 # number of ReadReq MSHR uncacheable cycles 754system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5918601247 # number of ReadReq MSHR uncacheable cycles 755system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5692373000 # number of WriteReq MSHR uncacheable cycles 756system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5692373000 # number of WriteReq MSHR uncacheable cycles 757system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11610974247 # number of overall MSHR uncacheable cycles 758system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11610974247 # number of overall MSHR uncacheable cycles 759system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035888 # mshr miss rate for ReadReq accesses 760system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035888 # mshr miss rate for ReadReq accesses 761system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018986 # mshr miss rate for WriteReq accesses 762system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018986 # mshr miss rate for WriteReq accesses 763system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.699879 # mshr miss rate for SoftPFReq accesses 764system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.699879 # mshr miss rate for SoftPFReq accesses 765system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.759908 # mshr miss rate for WriteInvalidateReq accesses 766system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.759908 # mshr miss rate for WriteInvalidateReq accesses 767system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057067 # mshr miss rate for LoadLockedReq accesses 768system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057067 # mshr miss rate for LoadLockedReq accesses 769system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098769 # mshr miss rate for StoreCondReq accesses 770system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098769 # mshr miss rate for StoreCondReq accesses 771system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027911 # mshr miss rate for demand accesses 772system.cpu0.dcache.demand_mshr_miss_rate::total 0.027911 # mshr miss rate for demand accesses 773system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031956 # mshr miss rate for overall accesses 774system.cpu0.dcache.overall_mshr_miss_rate::total 0.031956 # mshr miss rate for overall accesses 775system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13107.428482 # average ReadReq mshr miss latency 776system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13107.428482 # average ReadReq mshr miss latency 777system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18113.064869 # average WriteReq mshr miss latency 778system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18113.064869 # average WriteReq mshr miss latency 779system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22723.550774 # average SoftPFReq mshr miss latency 780system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22723.550774 # average SoftPFReq mshr miss latency 781system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39961.754657 # average WriteInvalidateReq mshr miss latency 782system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39961.754657 # average WriteInvalidateReq mshr miss latency 783system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12955.122865 # average LoadLockedReq mshr miss latency 784system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12955.122865 # average LoadLockedReq mshr miss latency 785system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19743.989609 # average StoreCondReq mshr miss latency 786system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19743.989609 # average StoreCondReq mshr miss latency | 707system.cpu0.dcache.writebacks::writebacks 3760610 # number of writebacks 708system.cpu0.dcache.writebacks::total 3760610 # number of writebacks 709system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 413115 # number of ReadReq MSHR hits 710system.cpu0.dcache.ReadReq_mshr_hits::total 413115 # number of ReadReq MSHR hits 711system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 966709 # number of WriteReq MSHR hits 712system.cpu0.dcache.WriteReq_mshr_hits::total 966709 # number of WriteReq MSHR hits 713system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 96 # number of WriteInvalidateReq MSHR hits 714system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 96 # number of WriteInvalidateReq MSHR hits 715system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 42490 # number of LoadLockedReq MSHR hits 716system.cpu0.dcache.LoadLockedReq_mshr_hits::total 42490 # number of LoadLockedReq MSHR hits 717system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 52 # number of StoreCondReq MSHR hits 718system.cpu0.dcache.StoreCondReq_mshr_hits::total 52 # number of StoreCondReq MSHR hits 719system.cpu0.dcache.demand_mshr_hits::cpu0.data 1379824 # number of demand (read+write) MSHR hits 720system.cpu0.dcache.demand_mshr_hits::total 1379824 # number of demand (read+write) MSHR hits 721system.cpu0.dcache.overall_mshr_hits::cpu0.data 1379824 # number of overall MSHR hits 722system.cpu0.dcache.overall_mshr_hits::total 1379824 # number of overall MSHR hits 723system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2926726 # number of ReadReq MSHR misses 724system.cpu0.dcache.ReadReq_mshr_misses::total 2926726 # number of ReadReq MSHR misses 725system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1345143 # number of WriteReq MSHR misses 726system.cpu0.dcache.WriteReq_mshr_misses::total 1345143 # number of WriteReq MSHR misses 727system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 614981 # number of SoftPFReq MSHR misses 728system.cpu0.dcache.SoftPFReq_mshr_misses::total 614981 # number of SoftPFReq MSHR misses 729system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 822584 # number of WriteInvalidateReq MSHR misses 730system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 822584 # number of WriteInvalidateReq MSHR misses 731system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 115009 # number of LoadLockedReq MSHR misses 732system.cpu0.dcache.LoadLockedReq_mshr_misses::total 115009 # number of LoadLockedReq MSHR misses 733system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 183586 # number of StoreCondReq MSHR misses 734system.cpu0.dcache.StoreCondReq_mshr_misses::total 183586 # number of StoreCondReq MSHR misses 735system.cpu0.dcache.demand_mshr_misses::cpu0.data 4271869 # number of demand (read+write) MSHR misses 736system.cpu0.dcache.demand_mshr_misses::total 4271869 # number of demand (read+write) MSHR misses 737system.cpu0.dcache.overall_mshr_misses::cpu0.data 4886850 # number of overall MSHR misses 738system.cpu0.dcache.overall_mshr_misses::total 4886850 # number of overall MSHR misses 739system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 33259 # number of ReadReq MSHR uncacheable 740system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33259 # number of ReadReq MSHR uncacheable 741system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 33163 # number of WriteReq MSHR uncacheable 742system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33163 # number of WriteReq MSHR uncacheable 743system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 66422 # number of overall MSHR uncacheable misses 744system.cpu0.dcache.overall_mshr_uncacheable_misses::total 66422 # number of overall MSHR uncacheable misses 745system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37662767131 # number of ReadReq MSHR miss cycles 746system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37662767131 # number of ReadReq MSHR miss cycles 747system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 23537156289 # number of WriteReq MSHR miss cycles 748system.cpu0.dcache.WriteReq_mshr_miss_latency::total 23537156289 # number of WriteReq MSHR miss cycles 749system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13208319439 # number of SoftPFReq MSHR miss cycles 750system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13208319439 # number of SoftPFReq MSHR miss cycles 751system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 31592370271 # number of WriteInvalidateReq MSHR miss cycles 752system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 31592370271 # number of WriteInvalidateReq MSHR miss cycles 753system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1454810141 # number of LoadLockedReq MSHR miss cycles 754system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1454810141 # number of LoadLockedReq MSHR miss cycles 755system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3611856094 # number of StoreCondReq MSHR miss cycles 756system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3611856094 # number of StoreCondReq MSHR miss cycles 757system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3160000 # number of StoreCondFailReq MSHR miss cycles 758system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3160000 # number of StoreCondFailReq MSHR miss cycles 759system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61199923420 # number of demand (read+write) MSHR miss cycles 760system.cpu0.dcache.demand_mshr_miss_latency::total 61199923420 # number of demand (read+write) MSHR miss cycles 761system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 74408242859 # number of overall MSHR miss cycles 762system.cpu0.dcache.overall_mshr_miss_latency::total 74408242859 # number of overall MSHR miss cycles 763system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5916157251 # number of ReadReq MSHR uncacheable cycles 764system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5916157251 # number of ReadReq MSHR uncacheable cycles 765system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5692664250 # number of WriteReq MSHR uncacheable cycles 766system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5692664250 # number of WriteReq MSHR uncacheable cycles 767system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11608821501 # number of overall MSHR uncacheable cycles 768system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11608821501 # number of overall MSHR uncacheable cycles 769system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035312 # mshr miss rate for ReadReq accesses 770system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035312 # mshr miss rate for ReadReq accesses 771system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018170 # mshr miss rate for WriteReq accesses 772system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018170 # mshr miss rate for WriteReq accesses 773system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.683798 # mshr miss rate for SoftPFReq accesses 774system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.683798 # mshr miss rate for SoftPFReq accesses 775system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.762227 # mshr miss rate for WriteInvalidateReq accesses 776system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.762227 # mshr miss rate for WriteInvalidateReq accesses 777system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064793 # mshr miss rate for LoadLockedReq accesses 778system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064793 # mshr miss rate for LoadLockedReq accesses 779system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.103512 # mshr miss rate for StoreCondReq accesses 780system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.103512 # mshr miss rate for StoreCondReq accesses 781system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027224 # mshr miss rate for demand accesses 782system.cpu0.dcache.demand_mshr_miss_rate::total 0.027224 # mshr miss rate for demand accesses 783system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030966 # mshr miss rate for overall accesses 784system.cpu0.dcache.overall_mshr_miss_rate::total 0.030966 # mshr miss rate for overall accesses 785system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12868.566149 # average ReadReq mshr miss latency 786system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12868.566149 # average ReadReq mshr miss latency 787system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17497.884083 # average WriteReq mshr miss latency 788system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17497.884083 # average WriteReq mshr miss latency 789system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21477.605713 # average SoftPFReq mshr miss latency 790system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21477.605713 # average SoftPFReq mshr miss latency 791system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 38406.254280 # average WriteInvalidateReq mshr miss latency 792system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 38406.254280 # average WriteInvalidateReq mshr miss latency 793system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12649.533002 # average LoadLockedReq mshr miss latency 794system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12649.533002 # average LoadLockedReq mshr miss latency 795system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19673.919003 # average StoreCondReq mshr miss latency 796system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19673.919003 # average StoreCondReq mshr miss latency |
| 787system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 788system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 797system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 798system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 789system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14714.303928 # average overall mshr miss latency 790system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14714.303928 # average overall mshr miss latency 791system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15770.008558 # average overall mshr miss latency 792system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15770.008558 # average overall mshr miss latency 793system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 794system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 795system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 796system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 797system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 798system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 799system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14326.264083 # average overall mshr miss latency 800system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14326.264083 # average overall mshr miss latency 801system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15226.217882 # average overall mshr miss latency 802system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15226.217882 # average overall mshr miss latency 803system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177881.393036 # average ReadReq mshr uncacheable latency 804system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 177881.393036 # average ReadReq mshr uncacheable latency 805system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171657.095257 # average WriteReq mshr uncacheable latency 806system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171657.095257 # average WriteReq mshr uncacheable latency 807system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 174773.742149 # average overall mshr uncacheable latency 808system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174773.742149 # average overall mshr uncacheable latency |
| 799system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 809system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 800system.cpu0.icache.tags.replacements 9298569 # number of replacements 801system.cpu0.icache.tags.tagsinuse 511.930207 # Cycle average of tags in use 802system.cpu0.icache.tags.total_refs 223083541 # Total number of references to valid blocks. 803system.cpu0.icache.tags.sampled_refs 9299081 # Sample count of references to valid blocks. 804system.cpu0.icache.tags.avg_refs 23.989848 # Average number of references to valid blocks. 805system.cpu0.icache.tags.warmup_cycle 24039613250 # Cycle when the warmup percentage was hit. 806system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930207 # Average occupied blocks per requestor 807system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999864 # Average percentage of cache occupancy 808system.cpu0.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy | 810system.cpu0.icache.tags.replacements 9994306 # number of replacements 811system.cpu0.icache.tags.tagsinuse 511.930109 # Cycle average of tags in use 812system.cpu0.icache.tags.total_refs 229434949 # Total number of references to valid blocks. 813system.cpu0.icache.tags.sampled_refs 9994818 # Sample count of references to valid blocks. 814system.cpu0.icache.tags.avg_refs 22.955390 # Average number of references to valid blocks. 815system.cpu0.icache.tags.warmup_cycle 24035147250 # Cycle when the warmup percentage was hit. 816system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930109 # Average occupied blocks per requestor 817system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999863 # Average percentage of cache occupancy 818system.cpu0.icache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy |
| 809system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 819system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 810system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 811system.cpu0.icache.tags.age_task_id_blocks_1024::1 423 # Occupied blocks per task id 812system.cpu0.icache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id | 820system.cpu0.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 821system.cpu0.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id 822system.cpu0.icache.tags.age_task_id_blocks_1024::2 254 # Occupied blocks per task id |
| 813system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 823system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 814system.cpu0.icache.tags.tag_accesses 474064354 # Number of tag accesses 815system.cpu0.icache.tags.data_accesses 474064354 # Number of data accesses 816system.cpu0.icache.ReadReq_hits::cpu0.inst 223083541 # number of ReadReq hits 817system.cpu0.icache.ReadReq_hits::total 223083541 # number of ReadReq hits 818system.cpu0.icache.demand_hits::cpu0.inst 223083541 # number of demand (read+write) hits 819system.cpu0.icache.demand_hits::total 223083541 # number of demand (read+write) hits 820system.cpu0.icache.overall_hits::cpu0.inst 223083541 # number of overall hits 821system.cpu0.icache.overall_hits::total 223083541 # number of overall hits 822system.cpu0.icache.ReadReq_misses::cpu0.inst 9299091 # number of ReadReq misses 823system.cpu0.icache.ReadReq_misses::total 9299091 # number of ReadReq misses 824system.cpu0.icache.demand_misses::cpu0.inst 9299091 # number of demand (read+write) misses 825system.cpu0.icache.demand_misses::total 9299091 # number of demand (read+write) misses 826system.cpu0.icache.overall_misses::cpu0.inst 9299091 # number of overall misses 827system.cpu0.icache.overall_misses::total 9299091 # number of overall misses 828system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 92099739258 # number of ReadReq miss cycles 829system.cpu0.icache.ReadReq_miss_latency::total 92099739258 # number of ReadReq miss cycles 830system.cpu0.icache.demand_miss_latency::cpu0.inst 92099739258 # number of demand (read+write) miss cycles 831system.cpu0.icache.demand_miss_latency::total 92099739258 # number of demand (read+write) miss cycles 832system.cpu0.icache.overall_miss_latency::cpu0.inst 92099739258 # number of overall miss cycles 833system.cpu0.icache.overall_miss_latency::total 92099739258 # number of overall miss cycles 834system.cpu0.icache.ReadReq_accesses::cpu0.inst 232382632 # number of ReadReq accesses(hits+misses) 835system.cpu0.icache.ReadReq_accesses::total 232382632 # number of ReadReq accesses(hits+misses) 836system.cpu0.icache.demand_accesses::cpu0.inst 232382632 # number of demand (read+write) accesses 837system.cpu0.icache.demand_accesses::total 232382632 # number of demand (read+write) accesses 838system.cpu0.icache.overall_accesses::cpu0.inst 232382632 # number of overall (read+write) accesses 839system.cpu0.icache.overall_accesses::total 232382632 # number of overall (read+write) accesses 840system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.040016 # miss rate for ReadReq accesses 841system.cpu0.icache.ReadReq_miss_rate::total 0.040016 # miss rate for ReadReq accesses 842system.cpu0.icache.demand_miss_rate::cpu0.inst 0.040016 # miss rate for demand accesses 843system.cpu0.icache.demand_miss_rate::total 0.040016 # miss rate for demand accesses 844system.cpu0.icache.overall_miss_rate::cpu0.inst 0.040016 # miss rate for overall accesses 845system.cpu0.icache.overall_miss_rate::total 0.040016 # miss rate for overall accesses 846system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9904.165822 # average ReadReq miss latency 847system.cpu0.icache.ReadReq_avg_miss_latency::total 9904.165822 # average ReadReq miss latency 848system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9904.165822 # average overall miss latency 849system.cpu0.icache.demand_avg_miss_latency::total 9904.165822 # average overall miss latency 850system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9904.165822 # average overall miss latency 851system.cpu0.icache.overall_avg_miss_latency::total 9904.165822 # average overall miss latency | 824system.cpu0.icache.tags.tag_accesses 488854379 # Number of tag accesses 825system.cpu0.icache.tags.data_accesses 488854379 # Number of data accesses 826system.cpu0.icache.ReadReq_hits::cpu0.inst 229434949 # number of ReadReq hits 827system.cpu0.icache.ReadReq_hits::total 229434949 # number of ReadReq hits 828system.cpu0.icache.demand_hits::cpu0.inst 229434949 # number of demand (read+write) hits 829system.cpu0.icache.demand_hits::total 229434949 # number of demand (read+write) hits 830system.cpu0.icache.overall_hits::cpu0.inst 229434949 # number of overall hits 831system.cpu0.icache.overall_hits::total 229434949 # number of overall hits 832system.cpu0.icache.ReadReq_misses::cpu0.inst 9994827 # number of ReadReq misses 833system.cpu0.icache.ReadReq_misses::total 9994827 # number of ReadReq misses 834system.cpu0.icache.demand_misses::cpu0.inst 9994827 # number of demand (read+write) misses 835system.cpu0.icache.demand_misses::total 9994827 # number of demand (read+write) misses 836system.cpu0.icache.overall_misses::cpu0.inst 9994827 # number of overall misses 837system.cpu0.icache.overall_misses::total 9994827 # number of overall misses 838system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 98560798487 # number of ReadReq miss cycles 839system.cpu0.icache.ReadReq_miss_latency::total 98560798487 # number of ReadReq miss cycles 840system.cpu0.icache.demand_miss_latency::cpu0.inst 98560798487 # number of demand (read+write) miss cycles 841system.cpu0.icache.demand_miss_latency::total 98560798487 # number of demand (read+write) miss cycles 842system.cpu0.icache.overall_miss_latency::cpu0.inst 98560798487 # number of overall miss cycles 843system.cpu0.icache.overall_miss_latency::total 98560798487 # number of overall miss cycles 844system.cpu0.icache.ReadReq_accesses::cpu0.inst 239429776 # number of ReadReq accesses(hits+misses) 845system.cpu0.icache.ReadReq_accesses::total 239429776 # number of ReadReq accesses(hits+misses) 846system.cpu0.icache.demand_accesses::cpu0.inst 239429776 # number of demand (read+write) accesses 847system.cpu0.icache.demand_accesses::total 239429776 # number of demand (read+write) accesses 848system.cpu0.icache.overall_accesses::cpu0.inst 239429776 # number of overall (read+write) accesses 849system.cpu0.icache.overall_accesses::total 239429776 # number of overall (read+write) accesses 850system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.041744 # miss rate for ReadReq accesses 851system.cpu0.icache.ReadReq_miss_rate::total 0.041744 # miss rate for ReadReq accesses 852system.cpu0.icache.demand_miss_rate::cpu0.inst 0.041744 # miss rate for demand accesses 853system.cpu0.icache.demand_miss_rate::total 0.041744 # miss rate for demand accesses 854system.cpu0.icache.overall_miss_rate::cpu0.inst 0.041744 # miss rate for overall accesses 855system.cpu0.icache.overall_miss_rate::total 0.041744 # miss rate for overall accesses 856system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9861.181038 # average ReadReq miss latency 857system.cpu0.icache.ReadReq_avg_miss_latency::total 9861.181038 # average ReadReq miss latency 858system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9861.181038 # average overall miss latency 859system.cpu0.icache.demand_avg_miss_latency::total 9861.181038 # average overall miss latency 860system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9861.181038 # average overall miss latency 861system.cpu0.icache.overall_avg_miss_latency::total 9861.181038 # average overall miss latency |
| 852system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 853system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 854system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 855system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 856system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 857system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 858system.cpu0.icache.fast_writes 0 # number of fast writes performed 859system.cpu0.icache.cache_copies 0 # number of cache copies performed | 862system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 863system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 864system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 865system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 866system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 867system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 868system.cpu0.icache.fast_writes 0 # number of fast writes performed 869system.cpu0.icache.cache_copies 0 # number of cache copies performed |
| 860system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9299091 # number of ReadReq MSHR misses 861system.cpu0.icache.ReadReq_mshr_misses::total 9299091 # number of ReadReq MSHR misses 862system.cpu0.icache.demand_mshr_misses::cpu0.inst 9299091 # number of demand (read+write) MSHR misses 863system.cpu0.icache.demand_mshr_misses::total 9299091 # number of demand (read+write) MSHR misses 864system.cpu0.icache.overall_mshr_misses::cpu0.inst 9299091 # number of overall MSHR misses 865system.cpu0.icache.overall_mshr_misses::total 9299091 # number of overall MSHR misses 866system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 82773169690 # number of ReadReq MSHR miss cycles 867system.cpu0.icache.ReadReq_mshr_miss_latency::total 82773169690 # number of ReadReq MSHR miss cycles 868system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 82773169690 # number of demand (read+write) MSHR miss cycles 869system.cpu0.icache.demand_mshr_miss_latency::total 82773169690 # number of demand (read+write) MSHR miss cycles 870system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 82773169690 # number of overall MSHR miss cycles 871system.cpu0.icache.overall_mshr_miss_latency::total 82773169690 # number of overall MSHR miss cycles | 870system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9994827 # number of ReadReq MSHR misses 871system.cpu0.icache.ReadReq_mshr_misses::total 9994827 # number of ReadReq MSHR misses 872system.cpu0.icache.demand_mshr_misses::cpu0.inst 9994827 # number of demand (read+write) MSHR misses 873system.cpu0.icache.demand_mshr_misses::total 9994827 # number of demand (read+write) MSHR misses 874system.cpu0.icache.overall_mshr_misses::cpu0.inst 9994827 # number of overall MSHR misses 875system.cpu0.icache.overall_mshr_misses::total 9994827 # number of overall MSHR misses 876system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 52307 # number of ReadReq MSHR uncacheable 877system.cpu0.icache.ReadReq_mshr_uncacheable::total 52307 # number of ReadReq MSHR uncacheable 878system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 52307 # number of overall MSHR uncacheable misses 879system.cpu0.icache.overall_mshr_uncacheable_misses::total 52307 # number of overall MSHR uncacheable misses 880system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 88537189453 # number of ReadReq MSHR miss cycles 881system.cpu0.icache.ReadReq_mshr_miss_latency::total 88537189453 # number of ReadReq MSHR miss cycles 882system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 88537189453 # number of demand (read+write) MSHR miss cycles 883system.cpu0.icache.demand_mshr_miss_latency::total 88537189453 # number of demand (read+write) MSHR miss cycles 884system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 88537189453 # number of overall MSHR miss cycles 885system.cpu0.icache.overall_mshr_miss_latency::total 88537189453 # number of overall MSHR miss cycles |
| 872system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of ReadReq MSHR uncacheable cycles 873system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4833897250 # number of ReadReq MSHR uncacheable cycles 874system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of overall MSHR uncacheable cycles 875system.cpu0.icache.overall_mshr_uncacheable_latency::total 4833897250 # number of overall MSHR uncacheable cycles | 886system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of ReadReq MSHR uncacheable cycles 887system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4833897250 # number of ReadReq MSHR uncacheable cycles 888system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of overall MSHR uncacheable cycles 889system.cpu0.icache.overall_mshr_uncacheable_latency::total 4833897250 # number of overall MSHR uncacheable cycles |
| 876system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.040016 # mshr miss rate for ReadReq accesses 877system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.040016 # mshr miss rate for ReadReq accesses 878system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.040016 # mshr miss rate for demand accesses 879system.cpu0.icache.demand_mshr_miss_rate::total 0.040016 # mshr miss rate for demand accesses 880system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.040016 # mshr miss rate for overall accesses 881system.cpu0.icache.overall_mshr_miss_rate::total 0.040016 # mshr miss rate for overall accesses 882system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8901.210848 # average ReadReq mshr miss latency 883system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8901.210848 # average ReadReq mshr miss latency 884system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8901.210848 # average overall mshr miss latency 885system.cpu0.icache.demand_avg_mshr_miss_latency::total 8901.210848 # average overall mshr miss latency 886system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8901.210848 # average overall mshr miss latency 887system.cpu0.icache.overall_avg_mshr_miss_latency::total 8901.210848 # average overall mshr miss latency 888system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 889system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 890system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 891system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 890system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.041744 # mshr miss rate for ReadReq accesses 891system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.041744 # mshr miss rate for ReadReq accesses 892system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.041744 # mshr miss rate for demand accesses 893system.cpu0.icache.demand_mshr_miss_rate::total 0.041744 # mshr miss rate for demand accesses 894system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.041744 # mshr miss rate for overall accesses 895system.cpu0.icache.overall_mshr_miss_rate::total 0.041744 # mshr miss rate for overall accesses 896system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8858.301345 # average ReadReq mshr miss latency 897system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8858.301345 # average ReadReq mshr miss latency 898system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8858.301345 # average overall mshr miss latency 899system.cpu0.icache.demand_avg_mshr_miss_latency::total 8858.301345 # average overall mshr miss latency 900system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8858.301345 # average overall mshr miss latency 901system.cpu0.icache.overall_avg_mshr_miss_latency::total 8858.301345 # average overall mshr miss latency 902system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 92413.964670 # average ReadReq mshr uncacheable latency 903system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 92413.964670 # average ReadReq mshr uncacheable latency 904system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 92413.964670 # average overall mshr uncacheable latency 905system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92413.964670 # average overall mshr uncacheable latency |
| 892system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 906system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 893system.cpu0.l2cache.prefetcher.num_hwpf_issued 7190203 # number of hwpf issued 894system.cpu0.l2cache.prefetcher.pfIdentified 7193896 # number of prefetch candidates identified 895system.cpu0.l2cache.prefetcher.pfBufferHit 3174 # number of redundant prefetches already in prefetch queue | 907system.cpu0.l2cache.prefetcher.num_hwpf_issued 7230073 # number of hwpf issued 908system.cpu0.l2cache.prefetcher.pfIdentified 7233896 # number of prefetch candidates identified 909system.cpu0.l2cache.prefetcher.pfBufferHit 3309 # number of redundant prefetches already in prefetch queue |
| 896system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 897system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 910system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 911system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 898system.cpu0.l2cache.prefetcher.pfSpanPage 922256 # number of prefetches not generated due to page crossing 899system.cpu0.l2cache.tags.replacements 2625541 # number of replacements 900system.cpu0.l2cache.tags.tagsinuse 15991.413435 # Cycle average of tags in use 901system.cpu0.l2cache.tags.total_refs 14807300 # Total number of references to valid blocks. 902system.cpu0.l2cache.tags.sampled_refs 2641343 # Sample count of references to valid blocks. 903system.cpu0.l2cache.tags.avg_refs 5.605974 # Average number of references to valid blocks. 904system.cpu0.l2cache.tags.warmup_cycle 5822698500 # Cycle when the warmup percentage was hit. 905system.cpu0.l2cache.tags.occ_blocks::writebacks 4879.764539 # Average occupied blocks per requestor 906system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 24.400359 # Average occupied blocks per requestor 907system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 12.549912 # Average occupied blocks per requestor 908system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 6476.155414 # Average occupied blocks per requestor 909system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3443.547426 # Average occupied blocks per requestor 910system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1154.995785 # Average occupied blocks per requestor 911system.cpu0.l2cache.tags.occ_percent::writebacks 0.297837 # Average percentage of cache occupancy 912system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001489 # Average percentage of cache occupancy 913system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000766 # Average percentage of cache occupancy 914system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.395273 # Average percentage of cache occupancy 915system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.210177 # Average percentage of cache occupancy 916system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.070495 # Average percentage of cache occupancy 917system.cpu0.l2cache.tags.occ_percent::total 0.976038 # Average percentage of cache occupancy 918system.cpu0.l2cache.tags.occ_task_id_blocks::1022 899 # Occupied blocks per task id 919system.cpu0.l2cache.tags.occ_task_id_blocks::1023 100 # Occupied blocks per task id 920system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14803 # Occupied blocks per task id 921system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 9 # Occupied blocks per task id 922system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 131 # Occupied blocks per task id 923system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 286 # Occupied blocks per task id 924system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 212 # Occupied blocks per task id 925system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 261 # Occupied blocks per task id 926system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 927system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id 928system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 49 # Occupied blocks per task id 929system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 930system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 931system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 584 # Occupied blocks per task id 932system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3987 # Occupied blocks per task id 933system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7940 # Occupied blocks per task id 934system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2205 # Occupied blocks per task id 935system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.054871 # Percentage of cache occupancy per task id 936system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006104 # Percentage of cache occupancy per task id 937system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.903503 # Percentage of cache occupancy per task id 938system.cpu0.l2cache.tags.tag_accesses 317363753 # Number of tag accesses 939system.cpu0.l2cache.tags.data_accesses 317363753 # Number of data accesses 940system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 462963 # number of ReadReq hits 941system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 140724 # number of ReadReq hits 942system.cpu0.l2cache.ReadReq_hits::cpu0.inst 8558678 # number of ReadReq hits 943system.cpu0.l2cache.ReadReq_hits::cpu0.data 2632719 # number of ReadReq hits 944system.cpu0.l2cache.ReadReq_hits::total 11795084 # number of ReadReq hits 945system.cpu0.l2cache.Writeback_hits::writebacks 3714063 # number of Writeback hits 946system.cpu0.l2cache.Writeback_hits::total 3714063 # number of Writeback hits 947system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 203687 # number of WriteInvalidateReq hits 948system.cpu0.l2cache.WriteInvalidateReq_hits::total 203687 # number of WriteInvalidateReq hits 949system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 102333 # number of UpgradeReq hits 950system.cpu0.l2cache.UpgradeReq_hits::total 102333 # number of UpgradeReq hits 951system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 31948 # number of SCUpgradeReq hits 952system.cpu0.l2cache.SCUpgradeReq_hits::total 31948 # number of SCUpgradeReq hits 953system.cpu0.l2cache.ReadExReq_hits::cpu0.data 859061 # number of ReadExReq hits 954system.cpu0.l2cache.ReadExReq_hits::total 859061 # number of ReadExReq hits 955system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 462963 # number of demand (read+write) hits 956system.cpu0.l2cache.demand_hits::cpu0.itb.walker 140724 # number of demand (read+write) hits 957system.cpu0.l2cache.demand_hits::cpu0.inst 8558678 # number of demand (read+write) hits 958system.cpu0.l2cache.demand_hits::cpu0.data 3491780 # number of demand (read+write) hits 959system.cpu0.l2cache.demand_hits::total 12654145 # number of demand (read+write) hits 960system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 462963 # number of overall hits 961system.cpu0.l2cache.overall_hits::cpu0.itb.walker 140724 # number of overall hits 962system.cpu0.l2cache.overall_hits::cpu0.inst 8558678 # number of overall hits 963system.cpu0.l2cache.overall_hits::cpu0.data 3491780 # number of overall hits 964system.cpu0.l2cache.overall_hits::total 12654145 # number of overall hits 965system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10993 # number of ReadReq misses 966system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8048 # number of ReadReq misses 967system.cpu0.l2cache.ReadReq_misses::cpu0.inst 740412 # number of ReadReq misses 968system.cpu0.l2cache.ReadReq_misses::cpu0.data 946440 # number of ReadReq misses 969system.cpu0.l2cache.ReadReq_misses::total 1705893 # number of ReadReq misses 970system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses 971system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses 972system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 583142 # number of WriteInvalidateReq misses 973system.cpu0.l2cache.WriteInvalidateReq_misses::total 583142 # number of WriteInvalidateReq misses 974system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 124112 # number of UpgradeReq misses 975system.cpu0.l2cache.UpgradeReq_misses::total 124112 # number of UpgradeReq misses 976system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 148691 # number of SCUpgradeReq misses 977system.cpu0.l2cache.SCUpgradeReq_misses::total 148691 # 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number of overall misses 989system.cpu0.l2cache.overall_misses::cpu0.inst 740412 # number of overall misses 990system.cpu0.l2cache.overall_misses::cpu0.data 1215712 # number of overall misses 991system.cpu0.l2cache.overall_misses::total 1975165 # number of overall misses 992system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 390640720 # number of ReadReq miss cycles 993system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 300789761 # number of ReadReq miss cycles 994system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 22448225702 # number of ReadReq miss cycles 995system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 32185912694 # number of ReadReq miss cycles 996system.cpu0.l2cache.ReadReq_miss_latency::total 55325568877 # number of ReadReq miss cycles 997system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 214128828 # number of WriteInvalidateReq miss cycles 998system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 214128828 # number of WriteInvalidateReq miss cycles 999system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2731788344 # number of UpgradeReq miss cycles 1000system.cpu0.l2cache.UpgradeReq_miss_latency::total 2731788344 # number of UpgradeReq miss cycles 1001system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3090531448 # number of SCUpgradeReq miss cycles 1002system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3090531448 # number of SCUpgradeReq miss cycles 1003system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3176498 # number of SCUpgradeFailReq miss cycles 1004system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3176498 # number of SCUpgradeFailReq miss cycles 1005system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 13196588662 # number of ReadExReq miss cycles 1006system.cpu0.l2cache.ReadExReq_miss_latency::total 13196588662 # number of ReadExReq miss cycles 1007system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 390640720 # number of demand (read+write) miss cycles 1008system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 300789761 # number of demand (read+write) miss cycles 1009system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22448225702 # number of demand (read+write) miss cycles 1010system.cpu0.l2cache.demand_miss_latency::cpu0.data 45382501356 # number of demand (read+write) miss cycles 1011system.cpu0.l2cache.demand_miss_latency::total 68522157539 # number of demand (read+write) miss cycles 1012system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 390640720 # number of overall miss cycles 1013system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 300789761 # number of overall miss cycles 1014system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22448225702 # number of overall miss cycles 1015system.cpu0.l2cache.overall_miss_latency::cpu0.data 45382501356 # number of overall miss cycles 1016system.cpu0.l2cache.overall_miss_latency::total 68522157539 # number of overall miss cycles 1017system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 473956 # number of ReadReq accesses(hits+misses) 1018system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 148772 # number of ReadReq accesses(hits+misses) 1019system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 9299090 # number of ReadReq accesses(hits+misses) 1020system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3579159 # number of ReadReq accesses(hits+misses) 1021system.cpu0.l2cache.ReadReq_accesses::total 13500977 # number of ReadReq accesses(hits+misses) 1022system.cpu0.l2cache.Writeback_accesses::writebacks 3714064 # number of Writeback accesses(hits+misses) 1023system.cpu0.l2cache.Writeback_accesses::total 3714064 # number of Writeback accesses(hits+misses) 1024system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 786829 # number of WriteInvalidateReq accesses(hits+misses) 1025system.cpu0.l2cache.WriteInvalidateReq_accesses::total 786829 # number of WriteInvalidateReq accesses(hits+misses) 1026system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 226445 # number of UpgradeReq accesses(hits+misses) 1027system.cpu0.l2cache.UpgradeReq_accesses::total 226445 # number of UpgradeReq accesses(hits+misses) 1028system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 180639 # number of SCUpgradeReq accesses(hits+misses) 1029system.cpu0.l2cache.SCUpgradeReq_accesses::total 180639 # number of SCUpgradeReq accesses(hits+misses) 1030system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 1031system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 1032system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1128333 # number of ReadExReq accesses(hits+misses) 1033system.cpu0.l2cache.ReadExReq_accesses::total 1128333 # number of ReadExReq accesses(hits+misses) 1034system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 473956 # number of demand (read+write) accesses 1035system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 148772 # number of demand (read+write) accesses 1036system.cpu0.l2cache.demand_accesses::cpu0.inst 9299090 # number of demand (read+write) accesses 1037system.cpu0.l2cache.demand_accesses::cpu0.data 4707492 # number of demand (read+write) accesses 1038system.cpu0.l2cache.demand_accesses::total 14629310 # number of demand (read+write) accesses 1039system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 473956 # number of overall (read+write) accesses 1040system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 148772 # number of overall (read+write) accesses 1041system.cpu0.l2cache.overall_accesses::cpu0.inst 9299090 # number of overall (read+write) accesses 1042system.cpu0.l2cache.overall_accesses::cpu0.data 4707492 # number of overall (read+write) accesses 1043system.cpu0.l2cache.overall_accesses::total 14629310 # number of overall (read+write) accesses 1044system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.023194 # miss rate for ReadReq accesses 1045system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.054096 # miss rate for ReadReq accesses 1046system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.079622 # miss rate for ReadReq accesses 1047system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.264431 # miss rate for ReadReq accesses 1048system.cpu0.l2cache.ReadReq_miss_rate::total 0.126353 # miss rate for ReadReq accesses 1049system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses 1050system.cpu0.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses 1051system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.741129 # miss rate for WriteInvalidateReq accesses 1052system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.741129 # miss rate for WriteInvalidateReq accesses 1053system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.548089 # miss rate for UpgradeReq accesses 1054system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.548089 # miss rate for UpgradeReq accesses 1055system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.823139 # miss rate for SCUpgradeReq accesses 1056system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.823139 # miss rate for SCUpgradeReq accesses | 912system.cpu0.l2cache.prefetcher.pfSpanPage 950560 # number of prefetches not generated due to page crossing 913system.cpu0.l2cache.tags.replacements 2661651 # number of replacements 914system.cpu0.l2cache.tags.tagsinuse 16101.576152 # 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Occupied blocks per task id 936system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 263 # Occupied blocks per task id 937system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 985 # Occupied blocks per task id 938system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 51 # Occupied blocks per task id 939system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id 940system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 56 # Occupied blocks per task id 941system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 31 # Occupied blocks per task id 942system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 943system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id 944system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 705 # Occupied blocks per task id 945system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5210 # Occupied blocks per task id 946system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7781 # Occupied blocks per task id 947system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 446 # Occupied blocks per task id 948system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.082458 # Percentage of cache occupancy per task id 949system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id 950system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.870667 # Percentage of cache occupancy per task id 951system.cpu0.l2cache.tags.tag_accesses 331999507 # Number of tag accesses 952system.cpu0.l2cache.tags.data_accesses 331999507 # Number of data accesses 953system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 494334 # number of ReadReq hits 954system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 160804 # number of ReadReq hits 955system.cpu0.l2cache.ReadReq_hits::cpu0.inst 9208783 # number of ReadReq hits 956system.cpu0.l2cache.ReadReq_hits::cpu0.data 2710357 # number of ReadReq hits 957system.cpu0.l2cache.ReadReq_hits::total 12574278 # number of ReadReq hits 958system.cpu0.l2cache.Writeback_hits::writebacks 3760607 # number of Writeback hits 959system.cpu0.l2cache.Writeback_hits::total 3760607 # number of Writeback hits 960system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 232072 # number of WriteInvalidateReq hits 961system.cpu0.l2cache.WriteInvalidateReq_hits::total 232072 # number of WriteInvalidateReq hits 962system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 101378 # number of UpgradeReq hits 963system.cpu0.l2cache.UpgradeReq_hits::total 101378 # number of UpgradeReq hits 964system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 33994 # number of SCUpgradeReq hits 965system.cpu0.l2cache.SCUpgradeReq_hits::total 33994 # number of SCUpgradeReq hits 966system.cpu0.l2cache.ReadExReq_hits::cpu0.data 863447 # number of ReadExReq hits 967system.cpu0.l2cache.ReadExReq_hits::total 863447 # number of ReadExReq hits 968system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 494334 # number of demand (read+write) hits 969system.cpu0.l2cache.demand_hits::cpu0.itb.walker 160804 # number of demand (read+write) hits 970system.cpu0.l2cache.demand_hits::cpu0.inst 9208783 # number of demand (read+write) hits 971system.cpu0.l2cache.demand_hits::cpu0.data 3573804 # number of demand (read+write) hits 972system.cpu0.l2cache.demand_hits::total 13437725 # number of demand (read+write) hits 973system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 494334 # number of overall hits 974system.cpu0.l2cache.overall_hits::cpu0.itb.walker 160804 # number of overall hits 975system.cpu0.l2cache.overall_hits::cpu0.inst 9208783 # number of overall hits 976system.cpu0.l2cache.overall_hits::cpu0.data 3573804 # number of overall hits 977system.cpu0.l2cache.overall_hits::total 13437725 # number of overall hits 978system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10659 # number of ReadReq misses 979system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 7834 # number of ReadReq misses 980system.cpu0.l2cache.ReadReq_misses::cpu0.inst 786043 # number of ReadReq misses 981system.cpu0.l2cache.ReadReq_misses::cpu0.data 946030 # number of ReadReq misses 982system.cpu0.l2cache.ReadReq_misses::total 1750566 # number of ReadReq misses 983system.cpu0.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses 984system.cpu0.l2cache.Writeback_misses::total 2 # number of Writeback misses 985system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 588987 # number of WriteInvalidateReq misses 986system.cpu0.l2cache.WriteInvalidateReq_misses::total 588987 # number of WriteInvalidateReq misses 987system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 124560 # number of UpgradeReq misses 988system.cpu0.l2cache.UpgradeReq_misses::total 124560 # number of UpgradeReq misses 989system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 149586 # number of SCUpgradeReq misses 990system.cpu0.l2cache.SCUpgradeReq_misses::total 149586 # number of SCUpgradeReq misses 991system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses 992system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 993system.cpu0.l2cache.ReadExReq_misses::cpu0.data 267892 # number of ReadExReq misses 994system.cpu0.l2cache.ReadExReq_misses::total 267892 # number of ReadExReq misses 995system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10659 # 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number of ReadReq miss cycles 1007system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 23635812248 # number of ReadReq miss cycles 1008system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 30920172081 # number of ReadReq miss cycles 1009system.cpu0.l2cache.ReadReq_miss_latency::total 55128304577 # number of ReadReq miss cycles 1010system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 210558524 # number of WriteInvalidateReq miss cycles 1011system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 210558524 # number of WriteInvalidateReq miss cycles 1012system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2759900095 # number of UpgradeReq miss cycles 1013system.cpu0.l2cache.UpgradeReq_miss_latency::total 2759900095 # number of UpgradeReq miss cycles 1014system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3121911280 # number of SCUpgradeReq miss cycles 1015system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3121911280 # number of SCUpgradeReq miss cycles 1016system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3089998 # number of SCUpgradeFailReq miss cycles 1017system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3089998 # number of SCUpgradeFailReq miss cycles 1018system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12386704821 # number of ReadExReq miss cycles 1019system.cpu0.l2cache.ReadExReq_miss_latency::total 12386704821 # number of ReadExReq miss cycles 1020system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 318928487 # number of demand (read+write) miss cycles 1021system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 253391761 # number of demand (read+write) miss cycles 1022system.cpu0.l2cache.demand_miss_latency::cpu0.inst 23635812248 # number of demand (read+write) miss cycles 1023system.cpu0.l2cache.demand_miss_latency::cpu0.data 43306876902 # number of demand (read+write) miss cycles 1024system.cpu0.l2cache.demand_miss_latency::total 67515009398 # number of demand (read+write) miss cycles 1025system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 318928487 # number of overall miss cycles 1026system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 253391761 # number of overall miss cycles 1027system.cpu0.l2cache.overall_miss_latency::cpu0.inst 23635812248 # number of overall miss cycles 1028system.cpu0.l2cache.overall_miss_latency::cpu0.data 43306876902 # number of overall miss cycles 1029system.cpu0.l2cache.overall_miss_latency::total 67515009398 # number of overall miss cycles 1030system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 504993 # number of ReadReq accesses(hits+misses) 1031system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 168638 # number of ReadReq accesses(hits+misses) 1032system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 9994826 # number of ReadReq accesses(hits+misses) 1033system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3656387 # number of ReadReq accesses(hits+misses) 1034system.cpu0.l2cache.ReadReq_accesses::total 14324844 # number of ReadReq accesses(hits+misses) 1035system.cpu0.l2cache.Writeback_accesses::writebacks 3760609 # number of Writeback accesses(hits+misses) 1036system.cpu0.l2cache.Writeback_accesses::total 3760609 # number of Writeback accesses(hits+misses) 1037system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 821059 # number of WriteInvalidateReq accesses(hits+misses) 1038system.cpu0.l2cache.WriteInvalidateReq_accesses::total 821059 # number of WriteInvalidateReq accesses(hits+misses) 1039system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 225938 # number of UpgradeReq accesses(hits+misses) 1040system.cpu0.l2cache.UpgradeReq_accesses::total 225938 # number of UpgradeReq accesses(hits+misses) 1041system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 183580 # number of SCUpgradeReq accesses(hits+misses) 1042system.cpu0.l2cache.SCUpgradeReq_accesses::total 183580 # number of SCUpgradeReq accesses(hits+misses) 1043system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 6 # number of SCUpgradeFailReq accesses(hits+misses) 1044system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) 1045system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1131339 # number of ReadExReq accesses(hits+misses) 1046system.cpu0.l2cache.ReadExReq_accesses::total 1131339 # number of ReadExReq accesses(hits+misses) 1047system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 504993 # number of demand (read+write) accesses 1048system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 168638 # number of demand (read+write) accesses 1049system.cpu0.l2cache.demand_accesses::cpu0.inst 9994826 # number of demand (read+write) accesses 1050system.cpu0.l2cache.demand_accesses::cpu0.data 4787726 # number of demand (read+write) accesses 1051system.cpu0.l2cache.demand_accesses::total 15456183 # number of demand (read+write) accesses 1052system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 504993 # number of overall (read+write) accesses 1053system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 168638 # number of overall (read+write) accesses 1054system.cpu0.l2cache.overall_accesses::cpu0.inst 9994826 # number of overall (read+write) accesses 1055system.cpu0.l2cache.overall_accesses::cpu0.data 4787726 # number of overall (read+write) accesses 1056system.cpu0.l2cache.overall_accesses::total 15456183 # number of overall (read+write) accesses 1057system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021107 # miss rate for ReadReq accesses 1058system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.046455 # miss rate for ReadReq accesses 1059system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.078645 # miss rate for ReadReq accesses 1060system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.258734 # miss rate for ReadReq accesses 1061system.cpu0.l2cache.ReadReq_miss_rate::total 0.122205 # miss rate for ReadReq accesses 1062system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000001 # miss rate for Writeback accesses 1063system.cpu0.l2cache.Writeback_miss_rate::total 0.000001 # miss rate for Writeback accesses 1064system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.717350 # miss rate for WriteInvalidateReq accesses 1065system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.717350 # miss rate for WriteInvalidateReq accesses 1066system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.551302 # miss rate for UpgradeReq accesses 1067system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.551302 # miss rate for UpgradeReq accesses 1068system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.814827 # miss rate for SCUpgradeReq accesses 1069system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.814827 # miss rate for SCUpgradeReq accesses |
| 1057system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1058system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 1070system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1071system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 1059system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.238646 # miss rate for ReadExReq accesses 1060system.cpu0.l2cache.ReadExReq_miss_rate::total 0.238646 # miss rate for ReadExReq accesses 1061system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.023194 # miss rate for demand accesses 1062system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.054096 # miss rate for demand accesses 1063system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.079622 # miss rate for demand accesses 1064system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.258250 # miss rate for demand accesses 1065system.cpu0.l2cache.demand_miss_rate::total 0.135014 # miss rate for demand accesses 1066system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.023194 # miss rate for overall accesses 1067system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.054096 # miss rate for overall accesses 1068system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.079622 # miss rate for overall accesses 1069system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.258250 # miss rate for overall accesses 1070system.cpu0.l2cache.overall_miss_rate::total 0.135014 # miss rate for overall accesses 1071system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35535.406168 # average ReadReq miss latency 1072system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 37374.473285 # average ReadReq miss latency 1073system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30318.560075 # average ReadReq miss latency 1074system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 34007.346154 # average ReadReq miss latency 1075system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32432.027611 # average ReadReq miss latency 1076system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 367.198432 # average WriteInvalidateReq miss latency 1077system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 367.198432 # average WriteInvalidateReq miss latency 1078system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22010.670556 # average UpgradeReq miss latency 1079system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22010.670556 # average UpgradeReq miss latency 1080system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20784.926109 # average SCUpgradeReq miss latency 1081system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20784.926109 # average SCUpgradeReq miss latency 1082system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 1058832.666667 # average SCUpgradeFailReq miss latency 1083system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1058832.666667 # average SCUpgradeFailReq miss latency 1084system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49008.395459 # average ReadExReq miss latency 1085system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49008.395459 # average ReadExReq miss latency 1086system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35535.406168 # average overall miss latency 1087system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 37374.473285 # average overall miss latency 1088system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30318.560075 # average overall miss latency 1089system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37329.977294 # average overall miss latency 1090system.cpu0.l2cache.demand_avg_miss_latency::total 34691.865003 # average overall miss latency 1091system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35535.406168 # average overall miss latency 1092system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 37374.473285 # average overall miss latency 1093system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30318.560075 # average overall miss latency 1094system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37329.977294 # average overall miss latency 1095system.cpu0.l2cache.overall_avg_miss_latency::total 34691.865003 # average overall miss latency 1096system.cpu0.l2cache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked | 1072system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.236792 # miss rate for ReadExReq accesses 1073system.cpu0.l2cache.ReadExReq_miss_rate::total 0.236792 # miss rate for ReadExReq accesses 1074system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021107 # miss rate for demand accesses 1075system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.046455 # miss rate for demand accesses 1076system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.078645 # miss rate for demand accesses 1077system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.253549 # miss rate for demand accesses 1078system.cpu0.l2cache.demand_miss_rate::total 0.130592 # miss rate for demand accesses 1079system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021107 # miss rate for overall accesses 1080system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.046455 # miss rate for overall accesses 1081system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.078645 # miss rate for overall accesses 1082system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.253549 # miss rate for overall accesses 1083system.cpu0.l2cache.overall_miss_rate::total 0.130592 # miss rate for overall accesses 1084system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 29921.051412 # average ReadReq miss latency 1085system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 32345.131606 # average ReadReq miss latency 1086system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30069.362933 # average ReadReq miss latency 1087system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 32684.134838 # average ReadReq miss latency 1088system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31491.703013 # average ReadReq miss latency 1089system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 357.492651 # average WriteInvalidateReq miss latency 1090system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 357.492651 # average WriteInvalidateReq miss latency 1091system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22157.194083 # average UpgradeReq miss latency 1092system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22157.194083 # average UpgradeReq miss latency 1093system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20870.344016 # average SCUpgradeReq miss latency 1094system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20870.344016 # average SCUpgradeReq miss latency 1095system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 514999.666667 # average SCUpgradeFailReq miss latency 1096system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 514999.666667 # average SCUpgradeFailReq miss latency 1097system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 46237.680935 # average ReadExReq miss latency 1098system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 46237.680935 # average ReadExReq miss latency 1099system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 29921.051412 # average overall miss latency 1100system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 32345.131606 # average overall miss latency 1101system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30069.362933 # average overall miss latency 1102system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35675.172624 # average overall miss latency 1103system.cpu0.l2cache.demand_avg_miss_latency::total 33448.805671 # average overall miss latency 1104system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 29921.051412 # average overall miss latency 1105system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 32345.131606 # average overall miss latency 1106system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30069.362933 # average overall miss latency 1107system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35675.172624 # average overall miss latency 1108system.cpu0.l2cache.overall_avg_miss_latency::total 33448.805671 # average overall miss latency 1109system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 1097system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1110system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1098system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked | 1111system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 1099system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1112system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1100system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 99 # average number of cycles each access was blocked | 1113system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 1101system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1102system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1103system.cpu0.l2cache.cache_copies 0 # number of cache copies performed | 1114system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1115system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1116system.cpu0.l2cache.cache_copies 0 # number of cache copies performed |
| 1104system.cpu0.l2cache.writebacks::writebacks 1355884 # number of writebacks 1105system.cpu0.l2cache.writebacks::total 1355884 # number of writebacks 1106system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits 1107system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits | 1117system.cpu0.l2cache.writebacks::writebacks 1339072 # number of writebacks 1118system.cpu0.l2cache.writebacks::total 1339072 # number of writebacks |
| 1108system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 6 # number of ReadReq MSHR hits | 1119system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 6 # number of ReadReq MSHR hits |
| 1109system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 800 # number of ReadReq MSHR hits 1110system.cpu0.l2cache.ReadReq_mshr_hits::total 808 # number of ReadReq MSHR hits 1111system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 23 # number of WriteInvalidateReq MSHR hits 1112system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 23 # number of WriteInvalidateReq MSHR hits 1113system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 7927 # number of ReadExReq MSHR hits 1114system.cpu0.l2cache.ReadExReq_mshr_hits::total 7927 # number of ReadExReq MSHR hits 1115system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits 1116system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits | 1120system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 981 # number of ReadReq MSHR hits 1121system.cpu0.l2cache.ReadReq_mshr_hits::total 987 # number of ReadReq MSHR hits 1122system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 31 # number of WriteInvalidateReq MSHR hits 1123system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 31 # number of WriteInvalidateReq MSHR hits 1124system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6237 # number of ReadExReq MSHR hits 1125system.cpu0.l2cache.ReadExReq_mshr_hits::total 6237 # number of ReadExReq MSHR hits |
| 1117system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits | 1126system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits |
| 1118system.cpu0.l2cache.demand_mshr_hits::cpu0.data 8727 # number of demand (read+write) MSHR hits 1119system.cpu0.l2cache.demand_mshr_hits::total 8735 # number of demand (read+write) MSHR hits 1120system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits 1121system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits | 1127system.cpu0.l2cache.demand_mshr_hits::cpu0.data 7218 # number of demand (read+write) MSHR hits 1128system.cpu0.l2cache.demand_mshr_hits::total 7224 # number of demand (read+write) MSHR hits |
| 1122system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits | 1129system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits |
| 1123system.cpu0.l2cache.overall_mshr_hits::cpu0.data 8727 # number of overall MSHR hits 1124system.cpu0.l2cache.overall_mshr_hits::total 8735 # number of overall MSHR hits 1125system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10992 # number of ReadReq MSHR misses 1126system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8047 # number of ReadReq MSHR misses 1127system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 740406 # number of ReadReq MSHR misses 1128system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 945640 # number of ReadReq MSHR misses 1129system.cpu0.l2cache.ReadReq_mshr_misses::total 1705085 # number of ReadReq MSHR misses 1130system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses 1131system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses 1132system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 695861 # number of HardPFReq MSHR misses 1133system.cpu0.l2cache.HardPFReq_mshr_misses::total 695861 # number of HardPFReq MSHR misses 1134system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 583119 # number of WriteInvalidateReq MSHR misses 1135system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 583119 # number of WriteInvalidateReq MSHR misses 1136system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 124112 # number of UpgradeReq MSHR misses 1137system.cpu0.l2cache.UpgradeReq_mshr_misses::total 124112 # number of UpgradeReq MSHR misses 1138system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 148691 # number of SCUpgradeReq MSHR misses 1139system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 148691 # number of SCUpgradeReq MSHR misses 1140system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses 1141system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 1142system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 261345 # number of ReadExReq MSHR misses 1143system.cpu0.l2cache.ReadExReq_mshr_misses::total 261345 # number of ReadExReq MSHR misses 1144system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10992 # number of demand (read+write) MSHR misses 1145system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8047 # number of demand (read+write) MSHR misses 1146system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 740406 # number of demand (read+write) MSHR misses 1147system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1206985 # number of demand (read+write) MSHR misses 1148system.cpu0.l2cache.demand_mshr_misses::total 1966430 # number of demand (read+write) MSHR misses 1149system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10992 # number of overall MSHR misses 1150system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8047 # number of overall MSHR misses 1151system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 740406 # number of overall MSHR misses 1152system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1206985 # number of overall MSHR misses 1153system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 695861 # number of overall MSHR misses 1154system.cpu0.l2cache.overall_mshr_misses::total 2662291 # number of overall MSHR misses 1155system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 318665266 # number of ReadReq MSHR miss cycles 1156system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 248030007 # number of ReadReq MSHR miss cycles 1157system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 17610392548 # number of ReadReq MSHR miss cycles 1158system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 25914267732 # number of ReadReq MSHR miss cycles 1159system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 44091355553 # number of ReadReq MSHR miss cycles 1160system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 32596842182 # number of HardPFReq MSHR miss cycles 1161system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 32596842182 # number of HardPFReq MSHR miss cycles 1162system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 25478427229 # number of WriteInvalidateReq MSHR miss cycles 1163system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 25478427229 # number of WriteInvalidateReq MSHR miss cycles 1164system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2526518712 # number of UpgradeReq MSHR miss cycles 1165system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2526518712 # number of UpgradeReq MSHR miss cycles 1166system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2211223584 # number of SCUpgradeReq MSHR miss cycles 1167system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2211223584 # number of SCUpgradeReq MSHR miss cycles 1168system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2721498 # number of SCUpgradeFailReq MSHR miss cycles 1169system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2721498 # number of SCUpgradeFailReq MSHR miss cycles 1170system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10434978340 # number of ReadExReq MSHR miss cycles 1171system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10434978340 # number of ReadExReq MSHR miss cycles 1172system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 318665266 # number of demand (read+write) MSHR miss cycles 1173system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 248030007 # number of demand (read+write) MSHR miss cycles 1174system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 17610392548 # number of demand (read+write) MSHR miss cycles 1175system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 36349246072 # number of demand (read+write) MSHR miss cycles 1176system.cpu0.l2cache.demand_mshr_miss_latency::total 54526333893 # number of demand (read+write) MSHR miss cycles 1177system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 318665266 # number of overall MSHR miss cycles 1178system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 248030007 # number of overall MSHR miss cycles 1179system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 17610392548 # number of overall MSHR miss cycles 1180system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 36349246072 # number of overall MSHR miss cycles 1181system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 32596842182 # number of overall MSHR miss cycles 1182system.cpu0.l2cache.overall_mshr_miss_latency::total 87123176075 # number of overall MSHR miss cycles | 1130system.cpu0.l2cache.overall_mshr_hits::cpu0.data 7218 # number of overall MSHR hits 1131system.cpu0.l2cache.overall_mshr_hits::total 7224 # number of overall MSHR hits 1132system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10659 # number of ReadReq MSHR misses 1133system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 7834 # number of ReadReq MSHR misses 1134system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 786037 # number of ReadReq MSHR misses 1135system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 945049 # number of ReadReq MSHR misses 1136system.cpu0.l2cache.ReadReq_mshr_misses::total 1749579 # number of ReadReq MSHR misses 1137system.cpu0.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses 1138system.cpu0.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses 1139system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 685342 # number of HardPFReq MSHR misses 1140system.cpu0.l2cache.HardPFReq_mshr_misses::total 685342 # number of HardPFReq MSHR misses 1141system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 588956 # number of WriteInvalidateReq MSHR misses 1142system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 588956 # number of WriteInvalidateReq MSHR misses 1143system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 124560 # number of UpgradeReq MSHR misses 1144system.cpu0.l2cache.UpgradeReq_mshr_misses::total 124560 # number of UpgradeReq MSHR misses 1145system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 149586 # number of SCUpgradeReq MSHR misses 1146system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 149586 # number of SCUpgradeReq MSHR misses 1147system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses 1148system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses 1149system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 261655 # number of ReadExReq MSHR misses 1150system.cpu0.l2cache.ReadExReq_mshr_misses::total 261655 # number of ReadExReq MSHR misses 1151system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10659 # number of demand (read+write) MSHR misses 1152system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 7834 # number of demand (read+write) MSHR misses 1153system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 786037 # number of demand (read+write) MSHR misses 1154system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1206704 # number of demand (read+write) MSHR misses 1155system.cpu0.l2cache.demand_mshr_misses::total 2011234 # number of demand (read+write) MSHR misses 1156system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10659 # number of overall MSHR misses 1157system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 7834 # number of overall MSHR misses 1158system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 786037 # number of overall MSHR misses 1159system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1206704 # number of overall MSHR misses 1160system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 685342 # number of overall MSHR misses 1161system.cpu0.l2cache.overall_mshr_misses::total 2696576 # number of overall MSHR misses 1162system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 52307 # number of ReadReq MSHR uncacheable 1163system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 33259 # number of ReadReq MSHR uncacheable 1164system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 85566 # number of ReadReq MSHR uncacheable 1165system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 33163 # number of WriteReq MSHR uncacheable 1166system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 33163 # number of WriteReq MSHR uncacheable 1167system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 52307 # number of overall MSHR uncacheable misses 1168system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 66422 # number of overall MSHR uncacheable misses 1169system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 118729 # number of overall MSHR uncacheable misses 1170system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 249336497 # number of ReadReq MSHR miss cycles 1171system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 202183759 # number of ReadReq MSHR miss cycles 1172system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 18500486252 # number of ReadReq MSHR miss cycles 1173system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 24637742155 # number of ReadReq MSHR miss cycles 1174system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 43589748663 # number of ReadReq MSHR miss cycles 1175system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 26923200622 # number of HardPFReq MSHR miss cycles 1176system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 26923200622 # number of HardPFReq MSHR miss cycles 1177system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 25292544478 # number of WriteInvalidateReq MSHR miss cycles 1178system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 25292544478 # number of WriteInvalidateReq MSHR miss cycles 1179system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2524783016 # number of UpgradeReq MSHR miss cycles 1180system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2524783016 # number of UpgradeReq MSHR miss cycles 1181system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2234342769 # number of SCUpgradeReq MSHR miss cycles 1182system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2234342769 # number of SCUpgradeReq MSHR miss cycles 1183system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2647998 # number of SCUpgradeFailReq MSHR miss cycles 1184system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2647998 # number of SCUpgradeFailReq MSHR miss cycles 1185system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 9878225571 # number of ReadExReq MSHR miss cycles 1186system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9878225571 # number of ReadExReq MSHR miss cycles 1187system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 249336497 # number of demand (read+write) MSHR miss cycles 1188system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 202183759 # number of demand (read+write) MSHR miss cycles 1189system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 18500486252 # number of demand (read+write) MSHR miss cycles 1190system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 34515967726 # number of demand (read+write) MSHR miss cycles 1191system.cpu0.l2cache.demand_mshr_miss_latency::total 53467974234 # number of demand (read+write) MSHR miss cycles 1192system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 249336497 # number of overall MSHR miss cycles 1193system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 202183759 # number of overall MSHR miss cycles 1194system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 18500486252 # number of overall MSHR miss cycles 1195system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 34515967726 # number of overall MSHR miss cycles 1196system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 26923200622 # number of overall MSHR miss cycles 1197system.cpu0.l2cache.overall_mshr_miss_latency::total 80391174856 # number of overall MSHR miss cycles |
| 1183system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of ReadReq MSHR uncacheable cycles | 1198system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of ReadReq MSHR uncacheable cycles |
| 1184system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5652021253 # number of ReadReq MSHR uncacheable cycles 1185system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10043092003 # number of ReadReq MSHR uncacheable cycles 1186system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5443565000 # number of WriteReq MSHR uncacheable cycles 1187system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5443565000 # number of WriteReq MSHR uncacheable cycles | 1199system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5650020250 # number of ReadReq MSHR uncacheable cycles 1200system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10041091000 # number of ReadReq MSHR uncacheable cycles 1201system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5443925500 # number of WriteReq MSHR uncacheable cycles 1202system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5443925500 # number of WriteReq MSHR uncacheable cycles |
| 1188system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of overall MSHR uncacheable cycles | 1203system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of overall MSHR uncacheable cycles |
| 1189system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11095586253 # number of overall MSHR uncacheable cycles 1190system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15486657003 # number of overall MSHR uncacheable cycles 1191system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.023192 # mshr miss rate for ReadReq accesses 1192system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.054089 # mshr miss rate for ReadReq accesses 1193system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.079621 # mshr miss rate for ReadReq accesses 1194system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.264207 # mshr miss rate for ReadReq accesses 1195system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.126293 # mshr miss rate for ReadReq accesses 1196system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses 1197system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses | 1204system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11093945750 # number of overall MSHR uncacheable cycles 1205system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15485016500 # number of overall MSHR uncacheable cycles 1206system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021107 # mshr miss rate for ReadReq accesses 1207system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.046455 # mshr miss rate for ReadReq accesses 1208system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.078644 # mshr miss rate for ReadReq accesses 1209system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.258465 # mshr miss rate for ReadReq accesses 1210system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.122136 # mshr miss rate for ReadReq accesses 1211system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for Writeback accesses 1212system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000001 # mshr miss rate for Writeback accesses |
| 1198system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1199system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1213system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1214system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 1200system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.741100 # mshr miss rate for WriteInvalidateReq accesses 1201system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.741100 # mshr miss rate for WriteInvalidateReq accesses 1202system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.548089 # mshr miss rate for UpgradeReq accesses 1203system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.548089 # mshr miss rate for UpgradeReq accesses 1204system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.823139 # mshr miss rate for SCUpgradeReq accesses 1205system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.823139 # mshr miss rate for SCUpgradeReq accesses | 1215system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.717313 # mshr miss rate for WriteInvalidateReq accesses 1216system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.717313 # mshr miss rate for WriteInvalidateReq accesses 1217system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.551302 # mshr miss rate for UpgradeReq accesses 1218system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.551302 # mshr miss rate for UpgradeReq accesses 1219system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.814827 # mshr miss rate for SCUpgradeReq accesses 1220system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.814827 # mshr miss rate for SCUpgradeReq accesses |
| 1206system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1207system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 1221system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1222system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 1208system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.231620 # mshr miss rate for ReadExReq accesses 1209system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231620 # mshr miss rate for ReadExReq accesses 1210system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.023192 # mshr miss rate for demand accesses 1211system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.054089 # mshr miss rate for demand accesses 1212system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.079621 # mshr miss rate for demand accesses 1213system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256397 # mshr miss rate for demand accesses 1214system.cpu0.l2cache.demand_mshr_miss_rate::total 0.134417 # mshr miss rate for demand accesses 1215system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.023192 # mshr miss rate for overall accesses 1216system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.054089 # mshr miss rate for overall accesses 1217system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079621 # mshr miss rate for overall accesses 1218system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256397 # mshr miss rate for overall accesses | 1223system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.231279 # mshr miss rate for ReadExReq accesses 1224system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231279 # mshr miss rate for ReadExReq accesses 1225system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021107 # mshr miss rate for demand accesses 1226system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046455 # mshr miss rate for demand accesses 1227system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.078644 # mshr miss rate for demand accesses 1228system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.252041 # mshr miss rate for demand accesses 1229system.cpu0.l2cache.demand_mshr_miss_rate::total 0.130125 # mshr miss rate for demand accesses 1230system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021107 # mshr miss rate for overall accesses 1231system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046455 # mshr miss rate for overall accesses 1232system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078644 # mshr miss rate for overall accesses 1233system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.252041 # mshr miss rate for overall accesses |
| 1219system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1234system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1220system.cpu0.l2cache.overall_mshr_miss_rate::total 0.181983 # mshr miss rate for overall accesses 1221system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28990.653748 # average ReadReq mshr miss latency 1222system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 30822.667702 # average ReadReq mshr miss latency 1223system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23784.778281 # average ReadReq mshr miss latency 1224system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27403.946250 # average ReadReq mshr miss latency 1225system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25858.743437 # average ReadReq mshr miss latency 1226system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46843.898684 # average HardPFReq mshr miss latency 1227system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46843.898684 # average HardPFReq mshr miss latency 1228system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43693.358009 # average WriteInvalidateReq mshr miss latency 1229system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43693.358009 # average WriteInvalidateReq mshr miss latency 1230system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20356.764149 # average UpgradeReq mshr miss latency 1231system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20356.764149 # average UpgradeReq mshr miss latency 1232system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14871.267151 # average SCUpgradeReq mshr miss latency 1233system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14871.267151 # average SCUpgradeReq mshr miss latency 1234system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 907166 # average SCUpgradeFailReq mshr miss latency 1235system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 907166 # average SCUpgradeFailReq mshr miss latency 1236system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39927.981557 # average ReadExReq mshr miss latency 1237system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39927.981557 # average ReadExReq mshr miss latency 1238system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28990.653748 # average overall mshr miss latency 1239system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 30822.667702 # average overall mshr miss latency 1240system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23784.778281 # average overall mshr miss latency 1241system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30115.739692 # average overall mshr miss latency 1242system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27728.591352 # average overall mshr miss latency 1243system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28990.653748 # average overall mshr miss latency 1244system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 30822.667702 # average overall mshr miss latency 1245system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23784.778281 # average overall mshr miss latency 1246system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30115.739692 # average overall mshr miss latency 1247system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46843.898684 # average overall mshr miss latency 1248system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 32724.888480 # average overall mshr miss latency 1249system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 1250system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 1251system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1252system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 1253system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1254system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 1255system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 1256system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1235system.cpu0.l2cache.overall_mshr_miss_rate::total 0.174466 # mshr miss rate for overall accesses 1236system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 23392.109673 # average ReadReq mshr miss latency 1237system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 25808.496171 # average ReadReq mshr miss latency 1238system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23536.406368 # average ReadReq mshr miss latency 1239system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26070.333025 # average ReadReq mshr miss latency 1240system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24914.421505 # average ReadReq mshr miss latency 1241system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39284.329024 # average HardPFReq mshr miss latency 1242system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 39284.329024 # average HardPFReq mshr miss latency 1243system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 42944.709754 # average WriteInvalidateReq mshr miss latency 1244system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 42944.709754 # average WriteInvalidateReq mshr miss latency 1245system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20269.613166 # average UpgradeReq mshr miss latency 1246system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20269.613166 # average UpgradeReq mshr miss latency 1247system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14936.844150 # average SCUpgradeReq mshr miss latency 1248system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14936.844150 # average SCUpgradeReq mshr miss latency 1249system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 441333 # average SCUpgradeFailReq mshr miss latency 1250system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 441333 # average SCUpgradeFailReq mshr miss latency 1251system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 37752.863775 # average ReadExReq mshr miss latency 1252system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 37752.863775 # average ReadExReq mshr miss latency 1253system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23392.109673 # average overall mshr miss latency 1254system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 25808.496171 # average overall mshr miss latency 1255system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23536.406368 # average overall mshr miss latency 1256system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28603.508173 # average overall mshr miss latency 1257system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26584.661076 # average overall mshr miss latency 1258system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23392.109673 # average overall mshr miss latency 1259system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 25808.496171 # average overall mshr miss latency 1260system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23536.406368 # average overall mshr miss latency 1261system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28603.508173 # average overall mshr miss latency 1262system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39284.329024 # average overall mshr miss latency 1263system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 29812.315639 # average overall mshr miss latency 1264system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886 # average ReadReq mshr uncacheable latency 1265system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169879.438648 # average ReadReq mshr uncacheable latency 1266system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117349.075567 # average ReadReq mshr uncacheable latency 1267system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164156.605253 # average WriteReq mshr uncacheable latency 1268system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164156.605253 # average WriteReq mshr uncacheable latency 1269system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886 # average overall mshr uncacheable latency 1270system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 167022.157568 # average overall mshr uncacheable latency 1271system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 130423.203261 # average overall mshr uncacheable latency |
| 1257system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1272system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1258system.cpu0.toL2Bus.trans_dist::ReadReq 16236238 # Transaction distribution 1259system.cpu0.toL2Bus.trans_dist::ReadResp 13810704 # Transaction distribution 1260system.cpu0.toL2Bus.trans_dist::WriteReq 33172 # Transaction distribution 1261system.cpu0.toL2Bus.trans_dist::WriteResp 33172 # Transaction distribution 1262system.cpu0.toL2Bus.trans_dist::Writeback 3714064 # Transaction distribution 1263system.cpu0.toL2Bus.trans_dist::HardPFReq 1025800 # Transaction distribution 1264system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1145042 # Transaction distribution 1265system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 786829 # Transaction distribution 1266system.cpu0.toL2Bus.trans_dist::UpgradeReq 475552 # Transaction distribution 1267system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 336189 # Transaction distribution 1268system.cpu0.toL2Bus.trans_dist::UpgradeResp 478151 # Transaction distribution 1269system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 52 # Transaction distribution 1270system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 119 # Transaction distribution 1271system.cpu0.toL2Bus.trans_dist::ReadExReq 1267323 # Transaction distribution 1272system.cpu0.toL2Bus.trans_dist::ReadExResp 1138296 # Transaction distribution 1273system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18702794 # Packet count per connected master and slave (bytes) 1274system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15835764 # Packet count per connected master and slave (bytes) 1275system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 326673 # Packet count per connected master and slave (bytes) 1276system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1038123 # Packet count per connected master and slave (bytes) 1277system.cpu0.toL2Bus.pkt_count::total 35903354 # Packet count per connected master and slave (bytes) 1278system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 598489344 # Cumulative packet size per connected master and slave (bytes) 1279system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 596885449 # Cumulative packet size per connected master and slave (bytes) 1280system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1190176 # Cumulative packet size per connected master and slave (bytes) 1281system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3791640 # Cumulative packet size per connected master and slave (bytes) 1282system.cpu0.toL2Bus.pkt_size::total 1200356609 # Cumulative packet size per connected master and slave (bytes) 1283system.cpu0.toL2Bus.snoops 4763261 # Total snoops (count) 1284system.cpu0.toL2Bus.snoop_fanout::samples 24114639 # Request fanout histogram 1285system.cpu0.toL2Bus.snoop_fanout::mean 3.184867 # Request fanout histogram 1286system.cpu0.toL2Bus.snoop_fanout::stdev 0.388190 # Request fanout histogram | 1273system.cpu0.toL2Bus.trans_dist::ReadReq 16764997 # Transaction distribution 1274system.cpu0.toL2Bus.trans_dist::ReadResp 14635279 # Transaction distribution 1275system.cpu0.toL2Bus.trans_dist::WriteReq 38250 # Transaction distribution 1276system.cpu0.toL2Bus.trans_dist::WriteResp 33163 # Transaction distribution 1277system.cpu0.toL2Bus.trans_dist::Writeback 3760609 # Transaction distribution 1278system.cpu0.toL2Bus.trans_dist::HardPFReq 997781 # Transaction distribution 1279system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1159753 # Transaction distribution 1280system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 821059 # Transaction distribution 1281system.cpu0.toL2Bus.trans_dist::UpgradeReq 475624 # Transaction distribution 1282system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 336764 # Transaction distribution 1283system.cpu0.toL2Bus.trans_dist::UpgradeResp 482191 # Transaction distribution 1284system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution 1285system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution 1286system.cpu0.toL2Bus.trans_dist::ReadExReq 1257493 # Transaction distribution 1287system.cpu0.toL2Bus.trans_dist::ReadExResp 1141567 # Transaction distribution 1288system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20094267 # Packet count per connected master and slave (bytes) 1289system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16118866 # Packet count per connected master and slave (bytes) 1290system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366766 # Packet count per connected master and slave (bytes) 1291system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1099589 # Packet count per connected master and slave (bytes) 1292system.cpu0.toL2Bus.pkt_count::total 37679488 # Packet count per connected master and slave (bytes) 1293system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 643016512 # Cumulative packet size per connected master and slave (bytes) 1294system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 607271415 # Cumulative packet size per connected master and slave (bytes) 1295system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1349104 # Cumulative packet size per connected master and slave (bytes) 1296system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4039944 # Cumulative packet size per connected master and slave (bytes) 1297system.cpu0.toL2Bus.pkt_size::total 1255676975 # Cumulative packet size per connected master and slave (bytes) 1298system.cpu0.toL2Bus.snoops 4414025 # Total snoops (count) 1299system.cpu0.toL2Bus.snoop_fanout::samples 24791334 # Request fanout histogram 1300system.cpu0.toL2Bus.snoop_fanout::mean 1.197604 # Request fanout histogram 1301system.cpu0.toL2Bus.snoop_fanout::stdev 0.398192 # Request fanout histogram |
| 1287system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1288system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1302system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1303system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1289system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1290system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1291system.cpu0.toL2Bus.snoop_fanout::3 19656632 81.51% 81.51% # Request fanout histogram 1292system.cpu0.toL2Bus.snoop_fanout::4 4458007 18.49% 100.00% # Request fanout histogram | 1304system.cpu0.toL2Bus.snoop_fanout::1 19892474 80.24% 80.24% # Request fanout histogram 1305system.cpu0.toL2Bus.snoop_fanout::2 4898860 19.76% 100.00% # Request fanout histogram |
| 1293system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1306system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1294system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1295system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1296system.cpu0.toL2Bus.snoop_fanout::total 24114639 # Request fanout histogram 1297system.cpu0.toL2Bus.reqLayer0.occupancy 14405309409 # Layer occupancy (ticks) | 1307system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1308system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1309system.cpu0.toL2Bus.snoop_fanout::total 24791334 # Request fanout histogram 1310system.cpu0.toL2Bus.reqLayer0.occupancy 14940946397 # Layer occupancy (ticks) |
| 1298system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1311system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1299system.cpu0.toL2Bus.snoopLayer0.occupancy 207723992 # Layer occupancy (ticks) | 1312system.cpu0.toL2Bus.snoopLayer0.occupancy 210442490 # Layer occupancy (ticks) |
| 1300system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1313system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1301system.cpu0.toL2Bus.respLayer0.occupancy 14053020534 # Layer occupancy (ticks) | 1314system.cpu0.toL2Bus.respLayer0.occupancy 15097277267 # Layer occupancy (ticks) |
| 1302system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1315system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1303system.cpu0.toL2Bus.respLayer1.occupancy 7776245419 # Layer occupancy (ticks) | 1316system.cpu0.toL2Bus.respLayer1.occupancy 7911607131 # Layer occupancy (ticks) |
| 1304system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 1317system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1305system.cpu0.toL2Bus.respLayer2.occupancy 178137962 # Layer occupancy (ticks) | 1318system.cpu0.toL2Bus.respLayer2.occupancy 198319454 # Layer occupancy (ticks) |
| 1306system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1319system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1307system.cpu0.toL2Bus.respLayer3.occupancy 564500428 # Layer occupancy (ticks) | 1320system.cpu0.toL2Bus.respLayer3.occupancy 594828175 # Layer occupancy (ticks) |
| 1308system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1321system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1309system.cpu1.branchPred.lookups 140284857 # Number of BP lookups 1310system.cpu1.branchPred.condPredicted 99939687 # Number of conditional branches predicted 1311system.cpu1.branchPred.condIncorrect 6358953 # Number of conditional branches incorrect 1312system.cpu1.branchPred.BTBLookups 105820632 # Number of BTB lookups 1313system.cpu1.branchPred.BTBHits 77032296 # Number of BTB hits | 1322system.cpu1.branchPred.lookups 123549187 # Number of BP lookups 1323system.cpu1.branchPred.condPredicted 87841692 # Number of conditional branches predicted 1324system.cpu1.branchPred.condIncorrect 5708078 # Number of conditional branches incorrect 1325system.cpu1.branchPred.BTBLookups 93157119 # Number of BTB lookups 1326system.cpu1.branchPred.BTBHits 67436708 # Number of BTB hits |
| 1314system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 1327system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 1315system.cpu1.branchPred.BTBHitPct 72.795158 # BTB Hit Percentage 1316system.cpu1.branchPred.usedRAS 16359380 # Number of times the RAS was used to get a target. 1317system.cpu1.branchPred.RASInCorrect 1035022 # Number of incorrect RAS predictions. | 1328system.cpu1.branchPred.BTBHitPct 72.390289 # BTB Hit Percentage 1329system.cpu1.branchPred.usedRAS 14460012 # Number of times the RAS was used to get a target. 1330system.cpu1.branchPred.RASInCorrect 934859 # Number of incorrect RAS predictions. |
| 1318system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1319system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1320system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1321system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1322system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1323system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1324system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1325system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1339system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1340system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1341system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1342system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1343system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1344system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1345system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1346system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1331system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1332system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1333system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1334system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1335system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1336system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1337system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1338system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1352system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1353system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1354system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1355system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1356system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1357system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1358system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1359system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1347system.cpu1.dtb.walker.walks 298079 # Table walker walks requested 1348system.cpu1.dtb.walker.walksLong 298079 # Table walker walks initiated with long descriptors 1349system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11270 # Level at which table walker walks with long descriptors terminate 1350system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 91179 # Level at which table walker walks with long descriptors terminate 1351system.cpu1.dtb.walker.walkWaitTime::samples 298079 # Table walker wait (enqueue to first request) latency 1352system.cpu1.dtb.walker.walkWaitTime::0 298079 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1353system.cpu1.dtb.walker.walkWaitTime::total 298079 # Table walker wait (enqueue to first request) latency 1354system.cpu1.dtb.walker.walkCompletionTime::samples 102449 # Table walker service (enqueue to completion) latency 1355system.cpu1.dtb.walker.walkCompletionTime::mean 19055.295776 # Table walker service (enqueue to completion) latency 1356system.cpu1.dtb.walker.walkCompletionTime::gmean 17104.036055 # Table walker service (enqueue to completion) latency 1357system.cpu1.dtb.walker.walkCompletionTime::stdev 15328.339502 # Table walker service (enqueue to completion) latency 1358system.cpu1.dtb.walker.walkCompletionTime::0-65535 101103 98.69% 98.69% # Table walker service (enqueue to completion) latency 1359system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1144 1.12% 99.80% # Table walker service (enqueue to completion) latency 1360system.cpu1.dtb.walker.walkCompletionTime::131072-196607 36 0.04% 99.84% # Table walker service (enqueue to completion) latency 1361system.cpu1.dtb.walker.walkCompletionTime::196608-262143 71 0.07% 99.91% # Table walker service (enqueue to completion) latency 1362system.cpu1.dtb.walker.walkCompletionTime::262144-327679 73 0.07% 99.98% # Table walker service (enqueue to completion) latency 1363system.cpu1.dtb.walker.walkCompletionTime::327680-393215 15 0.01% 99.99% # Table walker service (enqueue to completion) latency 1364system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 1365system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1366system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1367system.cpu1.dtb.walker.walkCompletionTime::total 102449 # Table walker service (enqueue to completion) latency 1368system.cpu1.dtb.walker.walksPending::samples 1267166444 # Table walker pending requests distribution 1369system.cpu1.dtb.walker.walksPending::0 1267166444 100.00% 100.00% # Table walker pending requests distribution 1370system.cpu1.dtb.walker.walksPending::total 1267166444 # Table walker pending requests distribution 1371system.cpu1.dtb.walker.walkPageSizes::4K 91179 89.00% 89.00% # Table walker page sizes translated 1372system.cpu1.dtb.walker.walkPageSizes::2M 11270 11.00% 100.00% # Table walker page sizes translated 1373system.cpu1.dtb.walker.walkPageSizes::total 102449 # Table walker page sizes translated 1374system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 298079 # Table walker requests started/completed, data/inst | 1360system.cpu1.dtb.walker.walks 259362 # Table walker walks requested 1361system.cpu1.dtb.walker.walksLong 259362 # Table walker walks initiated with long descriptors 1362system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8416 # Level at which table walker walks with long descriptors terminate 1363system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76621 # Level at which table walker walks with long descriptors terminate 1364system.cpu1.dtb.walker.walkWaitTime::samples 259362 # Table walker wait (enqueue to first request) latency 1365system.cpu1.dtb.walker.walkWaitTime::0 259362 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1366system.cpu1.dtb.walker.walkWaitTime::total 259362 # Table walker wait (enqueue to first request) latency 1367system.cpu1.dtb.walker.walkCompletionTime::samples 85037 # Table walker service (enqueue to completion) latency 1368system.cpu1.dtb.walker.walkCompletionTime::mean 18225.042946 # Table walker service (enqueue to completion) latency 1369system.cpu1.dtb.walker.walkCompletionTime::gmean 16628.571422 # Table walker service (enqueue to completion) latency 1370system.cpu1.dtb.walker.walkCompletionTime::stdev 11774.469557 # Table walker service (enqueue to completion) latency 1371system.cpu1.dtb.walker.walkCompletionTime::0-32767 81545 95.89% 95.89% # Table walker service (enqueue to completion) latency 1372system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2790 3.28% 99.17% # Table walker service (enqueue to completion) latency 1373system.cpu1.dtb.walker.walkCompletionTime::65536-98303 403 0.47% 99.65% # Table walker service (enqueue to completion) latency 1374system.cpu1.dtb.walker.walkCompletionTime::98304-131071 201 0.24% 99.88% # Table walker service (enqueue to completion) latency 1375system.cpu1.dtb.walker.walkCompletionTime::131072-163839 25 0.03% 99.91% # Table walker service (enqueue to completion) latency 1376system.cpu1.dtb.walker.walkCompletionTime::163840-196607 11 0.01% 99.93% # Table walker service (enqueue to completion) latency 1377system.cpu1.dtb.walker.walkCompletionTime::196608-229375 23 0.03% 99.95% # Table walker service (enqueue to completion) latency 1378system.cpu1.dtb.walker.walkCompletionTime::229376-262143 9 0.01% 99.96% # Table walker service (enqueue to completion) latency 1379system.cpu1.dtb.walker.walkCompletionTime::262144-294911 14 0.02% 99.98% # Table walker service (enqueue to completion) latency 1380system.cpu1.dtb.walker.walkCompletionTime::294912-327679 11 0.01% 99.99% # Table walker service (enqueue to completion) latency 1381system.cpu1.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1382system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1383system.cpu1.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1384system.cpu1.dtb.walker.walkCompletionTime::total 85037 # Table walker service (enqueue to completion) latency 1385system.cpu1.dtb.walker.walksPending::samples 1261494444 # Table walker pending requests distribution 1386system.cpu1.dtb.walker.walksPending::0 1261494444 100.00% 100.00% # Table walker pending requests distribution 1387system.cpu1.dtb.walker.walksPending::total 1261494444 # Table walker pending requests distribution 1388system.cpu1.dtb.walker.walkPageSizes::4K 76621 90.10% 90.10% # Table walker page sizes translated 1389system.cpu1.dtb.walker.walkPageSizes::2M 8416 9.90% 100.00% # Table walker page sizes translated 1390system.cpu1.dtb.walker.walkPageSizes::total 85037 # Table walker page sizes translated 1391system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 259362 # Table walker requests started/completed, data/inst |
| 1375system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst | 1392system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| 1376system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 298079 # Table walker requests started/completed, data/inst 1377system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 102449 # Table walker requests started/completed, data/inst | 1393system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 259362 # Table walker requests started/completed, data/inst 1394system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 85037 # Table walker requests started/completed, data/inst |
| 1378system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst | 1395system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| 1379system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 102449 # Table walker requests started/completed, data/inst 1380system.cpu1.dtb.walker.walkRequestOrigin::total 400528 # Table walker requests started/completed, data/inst | 1396system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 85037 # Table walker requests started/completed, data/inst 1397system.cpu1.dtb.walker.walkRequestOrigin::total 344399 # Table walker requests started/completed, data/inst |
| 1381system.cpu1.dtb.inst_hits 0 # ITB inst hits 1382system.cpu1.dtb.inst_misses 0 # ITB inst misses | 1398system.cpu1.dtb.inst_hits 0 # ITB inst hits 1399system.cpu1.dtb.inst_misses 0 # ITB inst misses |
| 1383system.cpu1.dtb.read_hits 91176680 # DTB read hits 1384system.cpu1.dtb.read_misses 248433 # DTB read misses 1385system.cpu1.dtb.write_hits 79002879 # DTB write hits 1386system.cpu1.dtb.write_misses 49646 # DTB write misses | 1400system.cpu1.dtb.read_hits 80542266 # DTB read hits 1401system.cpu1.dtb.read_misses 214982 # DTB read misses 1402system.cpu1.dtb.write_hits 69249357 # DTB write hits 1403system.cpu1.dtb.write_misses 44380 # DTB write misses |
| 1387system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1388system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 1404system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1405system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 1389system.cpu1.dtb.flush_tlb_mva_asid 41692 # Number of times TLB was flushed by MVA & ASID 1390system.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID 1391system.cpu1.dtb.flush_entries 41482 # Number of entries that have been flushed from TLB 1392system.cpu1.dtb.align_faults 884 # Number of TLB faults due to alignment restrictions 1393system.cpu1.dtb.prefetch_faults 7879 # Number of TLB faults due to prefetch | 1406system.cpu1.dtb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID 1407system.cpu1.dtb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID 1408system.cpu1.dtb.flush_entries 35601 # Number of entries that have been flushed from TLB 1409system.cpu1.dtb.align_faults 736 # Number of TLB faults due to alignment restrictions 1410system.cpu1.dtb.prefetch_faults 6438 # Number of TLB faults due to prefetch |
| 1394system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1411system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1395system.cpu1.dtb.perms_faults 11586 # Number of TLB faults due to permissions restrictions 1396system.cpu1.dtb.read_accesses 91425113 # DTB read accesses 1397system.cpu1.dtb.write_accesses 79052525 # DTB write accesses | 1412system.cpu1.dtb.perms_faults 9960 # Number of TLB faults due to permissions restrictions 1413system.cpu1.dtb.read_accesses 80757248 # DTB read accesses 1414system.cpu1.dtb.write_accesses 69293737 # DTB write accesses |
| 1398system.cpu1.dtb.inst_accesses 0 # ITB inst accesses | 1415system.cpu1.dtb.inst_accesses 0 # ITB inst accesses |
| 1399system.cpu1.dtb.hits 170179559 # DTB hits 1400system.cpu1.dtb.misses 298079 # DTB misses 1401system.cpu1.dtb.accesses 170477638 # DTB accesses | 1416system.cpu1.dtb.hits 149791623 # DTB hits 1417system.cpu1.dtb.misses 259362 # DTB misses 1418system.cpu1.dtb.accesses 150050985 # DTB accesses |
| 1402system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1403system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1404system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1405system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1406system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1407system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1408system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1409system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1423system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1424system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1425system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1426system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1427system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1428system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1429system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1430system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 1419system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1420system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1421system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1422system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1423system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1424system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1425system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1426system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 1440system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1441system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1442system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1443system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1444system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1445system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1446system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1447system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 1431system.cpu1.itb.walker.walks 68407 # Table walker walks requested 1432system.cpu1.itb.walker.walksLong 68407 # Table walker walks initiated with long descriptors 1433system.cpu1.itb.walker.walksLongTerminationLevel::Level2 609 # Level at which table walker walks with long descriptors terminate 1434system.cpu1.itb.walker.walksLongTerminationLevel::Level3 58709 # Level at which table walker walks with long descriptors terminate 1435system.cpu1.itb.walker.walkWaitTime::samples 68407 # Table walker wait (enqueue to first request) latency 1436system.cpu1.itb.walker.walkWaitTime::0 68407 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1437system.cpu1.itb.walker.walkWaitTime::total 68407 # Table walker wait (enqueue to first request) latency 1438system.cpu1.itb.walker.walkCompletionTime::samples 59318 # Table walker service (enqueue to completion) latency 1439system.cpu1.itb.walker.walkCompletionTime::mean 21639.401767 # Table walker service (enqueue to completion) latency 1440system.cpu1.itb.walker.walkCompletionTime::gmean 18915.934077 # Table walker service (enqueue to completion) latency 1441system.cpu1.itb.walker.walkCompletionTime::stdev 18524.659910 # Table walker service (enqueue to completion) latency 1442system.cpu1.itb.walker.walkCompletionTime::0-32767 54668 92.16% 92.16% # Table walker service (enqueue to completion) latency 1443system.cpu1.itb.walker.walkCompletionTime::32768-65535 3100 5.23% 97.39% # Table walker service (enqueue to completion) latency 1444system.cpu1.itb.walker.walkCompletionTime::65536-98303 594 1.00% 98.39% # Table walker service (enqueue to completion) latency 1445system.cpu1.itb.walker.walkCompletionTime::98304-131071 801 1.35% 99.74% # Table walker service (enqueue to completion) latency 1446system.cpu1.itb.walker.walkCompletionTime::131072-163839 32 0.05% 99.79% # Table walker service (enqueue to completion) latency 1447system.cpu1.itb.walker.walkCompletionTime::163840-196607 14 0.02% 99.82% # Table walker service (enqueue to completion) latency 1448system.cpu1.itb.walker.walkCompletionTime::196608-229375 58 0.10% 99.91% # Table walker service (enqueue to completion) latency 1449system.cpu1.itb.walker.walkCompletionTime::229376-262143 21 0.04% 99.95% # Table walker service (enqueue to completion) latency 1450system.cpu1.itb.walker.walkCompletionTime::262144-294911 5 0.01% 99.96% # Table walker service (enqueue to completion) latency 1451system.cpu1.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.96% # Table walker service (enqueue to completion) latency 1452system.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.98% # Table walker service (enqueue to completion) latency 1453system.cpu1.itb.walker.walkCompletionTime::360448-393215 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 1454system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency 1455system.cpu1.itb.walker.walkCompletionTime::425984-458751 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 1456system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency | 1448system.cpu1.itb.walker.walks 60478 # Table walker walks requested 1449system.cpu1.itb.walker.walksLong 60478 # Table walker walks initiated with long descriptors 1450system.cpu1.itb.walker.walksLongTerminationLevel::Level2 478 # Level at which table walker walks with long descriptors terminate 1451system.cpu1.itb.walker.walksLongTerminationLevel::Level3 50972 # Level at which table walker walks with long descriptors terminate 1452system.cpu1.itb.walker.walkWaitTime::samples 60478 # Table walker wait (enqueue to first request) latency 1453system.cpu1.itb.walker.walkWaitTime::0 60478 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1454system.cpu1.itb.walker.walkWaitTime::total 60478 # Table walker wait (enqueue to first request) latency 1455system.cpu1.itb.walker.walkCompletionTime::samples 51450 # Table walker service (enqueue to completion) latency 1456system.cpu1.itb.walker.walkCompletionTime::mean 20568.513975 # Table walker service (enqueue to completion) latency 1457system.cpu1.itb.walker.walkCompletionTime::gmean 18499.951285 # Table walker service (enqueue to completion) latency 1458system.cpu1.itb.walker.walkCompletionTime::stdev 14805.800668 # Table walker service (enqueue to completion) latency 1459system.cpu1.itb.walker.walkCompletionTime::0-32767 47723 92.76% 92.76% # Table walker service (enqueue to completion) latency 1460system.cpu1.itb.walker.walkCompletionTime::32768-65535 2940 5.71% 98.47% # Table walker service (enqueue to completion) latency 1461system.cpu1.itb.walker.walkCompletionTime::65536-98303 278 0.54% 99.01% # Table walker service (enqueue to completion) latency 1462system.cpu1.itb.walker.walkCompletionTime::98304-131071 425 0.83% 99.84% # Table walker service (enqueue to completion) latency 1463system.cpu1.itb.walker.walkCompletionTime::131072-163839 16 0.03% 99.87% # Table walker service (enqueue to completion) latency 1464system.cpu1.itb.walker.walkCompletionTime::163840-196607 10 0.02% 99.89% # Table walker service (enqueue to completion) latency 1465system.cpu1.itb.walker.walkCompletionTime::196608-229375 27 0.05% 99.94% # Table walker service (enqueue to completion) latency 1466system.cpu1.itb.walker.walkCompletionTime::229376-262143 13 0.03% 99.97% # Table walker service (enqueue to completion) latency 1467system.cpu1.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.98% # Table walker service (enqueue to completion) latency 1468system.cpu1.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 1469system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 1470system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.00% 100.00% # Table walker service (enqueue to completion) latency |
| 1457system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency | 1471system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency |
| 1458system.cpu1.itb.walker.walkCompletionTime::total 59318 # Table walker service (enqueue to completion) latency 1459system.cpu1.itb.walker.walksPending::samples 1266435944 # Table walker pending requests distribution 1460system.cpu1.itb.walker.walksPending::0 1266435944 100.00% 100.00% # Table walker pending requests distribution 1461system.cpu1.itb.walker.walksPending::total 1266435944 # Table walker pending requests distribution 1462system.cpu1.itb.walker.walkPageSizes::4K 58709 98.97% 98.97% # Table walker page sizes translated 1463system.cpu1.itb.walker.walkPageSizes::2M 609 1.03% 100.00% # Table walker page sizes translated 1464system.cpu1.itb.walker.walkPageSizes::total 59318 # Table walker page sizes translated | 1472system.cpu1.itb.walker.walkCompletionTime::total 51450 # Table walker service (enqueue to completion) latency 1473system.cpu1.itb.walker.walksPending::samples 1260837944 # Table walker pending requests distribution 1474system.cpu1.itb.walker.walksPending::0 1260837944 100.00% 100.00% # Table walker pending requests distribution 1475system.cpu1.itb.walker.walksPending::total 1260837944 # Table walker pending requests distribution 1476system.cpu1.itb.walker.walkPageSizes::4K 50972 99.07% 99.07% # Table walker page sizes translated 1477system.cpu1.itb.walker.walkPageSizes::2M 478 0.93% 100.00% # Table walker page sizes translated 1478system.cpu1.itb.walker.walkPageSizes::total 51450 # Table walker page sizes translated |
| 1465system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst | 1479system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| 1466system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 68407 # Table walker requests started/completed, data/inst 1467system.cpu1.itb.walker.walkRequestOrigin_Requested::total 68407 # Table walker requests started/completed, data/inst | 1480system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60478 # Table walker requests started/completed, data/inst 1481system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60478 # Table walker requests started/completed, data/inst |
| 1468system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst | 1482system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| 1469system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 59318 # Table walker requests started/completed, data/inst 1470system.cpu1.itb.walker.walkRequestOrigin_Completed::total 59318 # Table walker requests started/completed, data/inst 1471system.cpu1.itb.walker.walkRequestOrigin::total 127725 # Table walker requests started/completed, data/inst 1472system.cpu1.itb.inst_hits 251160195 # ITB inst hits 1473system.cpu1.itb.inst_misses 68407 # ITB inst misses | 1483system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 51450 # Table walker requests started/completed, data/inst 1484system.cpu1.itb.walker.walkRequestOrigin_Completed::total 51450 # Table walker requests started/completed, data/inst 1485system.cpu1.itb.walker.walkRequestOrigin::total 111928 # Table walker requests started/completed, data/inst 1486system.cpu1.itb.inst_hits 220701471 # ITB inst hits 1487system.cpu1.itb.inst_misses 60478 # ITB inst misses |
| 1474system.cpu1.itb.read_hits 0 # DTB read hits 1475system.cpu1.itb.read_misses 0 # DTB read misses 1476system.cpu1.itb.write_hits 0 # DTB write hits 1477system.cpu1.itb.write_misses 0 # DTB write misses 1478system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1479system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA | 1488system.cpu1.itb.read_hits 0 # DTB read hits 1489system.cpu1.itb.read_misses 0 # DTB read misses 1490system.cpu1.itb.write_hits 0 # DTB write hits 1491system.cpu1.itb.write_misses 0 # DTB write misses 1492system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1493system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| 1480system.cpu1.itb.flush_tlb_mva_asid 41692 # Number of times TLB was flushed by MVA & ASID 1481system.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID 1482system.cpu1.itb.flush_entries 30244 # Number of entries that have been flushed from TLB | 1494system.cpu1.itb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID 1495system.cpu1.itb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID 1496system.cpu1.itb.flush_entries 25765 # Number of entries that have been flushed from TLB |
| 1483system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1484system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1485system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions | 1497system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1498system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1499system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| 1486system.cpu1.itb.perms_faults 224879 # Number of TLB faults due to permissions restrictions | 1500system.cpu1.itb.perms_faults 203408 # Number of TLB faults due to permissions restrictions |
| 1487system.cpu1.itb.read_accesses 0 # DTB read accesses 1488system.cpu1.itb.write_accesses 0 # DTB write accesses | 1501system.cpu1.itb.read_accesses 0 # DTB read accesses 1502system.cpu1.itb.write_accesses 0 # DTB write accesses |
| 1489system.cpu1.itb.inst_accesses 251228602 # ITB inst accesses 1490system.cpu1.itb.hits 251160195 # DTB hits 1491system.cpu1.itb.misses 68407 # DTB misses 1492system.cpu1.itb.accesses 251228602 # DTB accesses 1493system.cpu1.numCycles 937856787 # number of cpu cycles simulated | 1503system.cpu1.itb.inst_accesses 220761949 # ITB inst accesses 1504system.cpu1.itb.hits 220701471 # DTB hits 1505system.cpu1.itb.misses 60478 # DTB misses 1506system.cpu1.itb.accesses 220761949 # DTB accesses 1507system.cpu1.numCycles 819495419 # number of cpu cycles simulated |
| 1494system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1495system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed | 1508system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1509system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 1496system.cpu1.committedInsts 461578271 # Number of instructions committed 1497system.cpu1.committedOps 543115841 # Number of ops (including micro ops) committed 1498system.cpu1.discardedOps 48137471 # Number of ops (including micro ops) which were discarded before commit 1499system.cpu1.numFetchSuspends 5811 # Number of times Execute suspended instruction fetching 1500system.cpu1.quiesceCycles 93949323576 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1501system.cpu1.cpi 2.031848 # CPI: cycles per instruction 1502system.cpu1.ipc 0.492163 # IPC: instructions per cycle | 1510system.cpu1.committedInsts 407174795 # Number of instructions committed 1511system.cpu1.committedOps 478812576 # Number of ops (including micro ops) committed 1512system.cpu1.discardedOps 42038613 # Number of ops (including micro ops) which were discarded before commit 1513system.cpu1.numFetchSuspends 5231 # Number of times Execute suspended instruction fetching 1514system.cpu1.quiesceCycles 93913157476 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 1515system.cpu1.cpi 2.012638 # CPI: cycles per instruction 1516system.cpu1.ipc 0.496860 # IPC: instructions per cycle |
| 1503system.cpu1.kern.inst.arm 0 # number of arm instructions executed | 1517system.cpu1.kern.inst.arm 0 # number of arm instructions executed |
| 1504system.cpu1.kern.inst.quiesce 5892 # number of quiesce instructions executed 1505system.cpu1.tickCycles 744774671 # Number of cycles that the object actually ticked 1506system.cpu1.idleCycles 193082116 # Total number of cycles that the object has spent stopped 1507system.cpu1.dcache.tags.replacements 5501509 # number of replacements 1508system.cpu1.dcache.tags.tagsinuse 462.401458 # Cycle average of tags in use 1509system.cpu1.dcache.tags.total_refs 161882040 # Total number of references to valid blocks. 1510system.cpu1.dcache.tags.sampled_refs 5502021 # Sample count of references to valid blocks. 1511system.cpu1.dcache.tags.avg_refs 29.422287 # Average number of references to valid blocks. 1512system.cpu1.dcache.tags.warmup_cycle 8380046591500 # Cycle when the warmup percentage was hit. 1513system.cpu1.dcache.tags.occ_blocks::cpu1.data 462.401458 # Average occupied blocks per requestor 1514system.cpu1.dcache.tags.occ_percent::cpu1.data 0.903128 # Average percentage of cache occupancy 1515system.cpu1.dcache.tags.occ_percent::total 0.903128 # Average percentage of cache occupancy | 1518system.cpu1.kern.inst.quiesce 5271 # number of quiesce instructions executed 1519system.cpu1.tickCycles 656184177 # Number of cycles that the object actually ticked 1520system.cpu1.idleCycles 163311242 # Total number of cycles that the object has spent stopped 1521system.cpu1.dcache.tags.replacements 4776829 # number of replacements 1522system.cpu1.dcache.tags.tagsinuse 427.655512 # Cycle average of tags in use 1523system.cpu1.dcache.tags.total_refs 142582647 # Total number of references to valid blocks. 1524system.cpu1.dcache.tags.sampled_refs 4777341 # Sample count of references to valid blocks. 1525system.cpu1.dcache.tags.avg_refs 29.845608 # Average number of references to valid blocks. 1526system.cpu1.dcache.tags.warmup_cycle 8380053198500 # Cycle when the warmup percentage was hit. 1527system.cpu1.dcache.tags.occ_blocks::cpu1.data 427.655512 # Average occupied blocks per requestor 1528system.cpu1.dcache.tags.occ_percent::cpu1.data 0.835265 # Average percentage of cache occupancy 1529system.cpu1.dcache.tags.occ_percent::total 0.835265 # Average percentage of cache occupancy |
| 1516system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1530system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1517system.cpu1.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id 1518system.cpu1.dcache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id 1519system.cpu1.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id | 1531system.cpu1.dcache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 1532system.cpu1.dcache.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id 1533system.cpu1.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id |
| 1520system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1534system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1521system.cpu1.dcache.tags.tag_accesses 343173973 # Number of tag accesses 1522system.cpu1.dcache.tags.data_accesses 343173973 # Number of data accesses 1523system.cpu1.dcache.ReadReq_hits::cpu1.data 83605080 # number of ReadReq hits 1524system.cpu1.dcache.ReadReq_hits::total 83605080 # number of ReadReq hits 1525system.cpu1.dcache.WriteReq_hits::cpu1.data 73820570 # number of WriteReq hits 1526system.cpu1.dcache.WriteReq_hits::total 73820570 # number of WriteReq hits 1527system.cpu1.dcache.SoftPFReq_hits::cpu1.data 234480 # number of SoftPFReq hits 1528system.cpu1.dcache.SoftPFReq_hits::total 234480 # number of SoftPFReq hits 1529system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 75463 # number of WriteInvalidateReq hits 1530system.cpu1.dcache.WriteInvalidateReq_hits::total 75463 # number of WriteInvalidateReq hits 1531system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1844270 # number of LoadLockedReq hits 1532system.cpu1.dcache.LoadLockedReq_hits::total 1844270 # number of LoadLockedReq hits 1533system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1832447 # number of StoreCondReq hits 1534system.cpu1.dcache.StoreCondReq_hits::total 1832447 # number of StoreCondReq hits 1535system.cpu1.dcache.demand_hits::cpu1.data 157425650 # number of demand (read+write) hits 1536system.cpu1.dcache.demand_hits::total 157425650 # number of demand (read+write) hits 1537system.cpu1.dcache.overall_hits::cpu1.data 157660130 # number of overall hits 1538system.cpu1.dcache.overall_hits::total 157660130 # number of overall hits 1539system.cpu1.dcache.ReadReq_misses::cpu1.data 3592418 # number of ReadReq misses 1540system.cpu1.dcache.ReadReq_misses::total 3592418 # number of ReadReq misses 1541system.cpu1.dcache.WriteReq_misses::cpu1.data 2291328 # number of WriteReq misses 1542system.cpu1.dcache.WriteReq_misses::total 2291328 # number of WriteReq misses 1543system.cpu1.dcache.SoftPFReq_misses::cpu1.data 658469 # number of SoftPFReq misses 1544system.cpu1.dcache.SoftPFReq_misses::total 658469 # number of SoftPFReq misses 1545system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 456956 # number of WriteInvalidateReq misses 1546system.cpu1.dcache.WriteInvalidateReq_misses::total 456956 # number of WriteInvalidateReq misses 1547system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 185722 # number of LoadLockedReq misses 1548system.cpu1.dcache.LoadLockedReq_misses::total 185722 # number of LoadLockedReq misses 1549system.cpu1.dcache.StoreCondReq_misses::cpu1.data 196000 # number of StoreCondReq misses 1550system.cpu1.dcache.StoreCondReq_misses::total 196000 # number of StoreCondReq misses 1551system.cpu1.dcache.demand_misses::cpu1.data 5883746 # number of demand (read+write) misses 1552system.cpu1.dcache.demand_misses::total 5883746 # number of demand (read+write) misses 1553system.cpu1.dcache.overall_misses::cpu1.data 6542215 # number of overall misses 1554system.cpu1.dcache.overall_misses::total 6542215 # number of overall misses 1555system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 54049590884 # number of ReadReq miss cycles 1556system.cpu1.dcache.ReadReq_miss_latency::total 54049590884 # number of ReadReq miss cycles 1557system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 39638005604 # number of WriteReq miss cycles 1558system.cpu1.dcache.WriteReq_miss_latency::total 39638005604 # number of WriteReq miss cycles 1559system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 12577649145 # number of WriteInvalidateReq miss cycles 1560system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 12577649145 # number of WriteInvalidateReq miss cycles 1561system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2799761413 # number of LoadLockedReq miss cycles 1562system.cpu1.dcache.LoadLockedReq_miss_latency::total 2799761413 # number of LoadLockedReq miss cycles 1563system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4076020251 # number of StoreCondReq miss cycles 1564system.cpu1.dcache.StoreCondReq_miss_latency::total 4076020251 # number of StoreCondReq miss cycles 1565system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2567000 # number of StoreCondFailReq miss cycles 1566system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2567000 # number of StoreCondFailReq miss cycles 1567system.cpu1.dcache.demand_miss_latency::cpu1.data 93687596488 # number of demand (read+write) miss cycles 1568system.cpu1.dcache.demand_miss_latency::total 93687596488 # number of demand (read+write) miss cycles 1569system.cpu1.dcache.overall_miss_latency::cpu1.data 93687596488 # number of overall miss cycles 1570system.cpu1.dcache.overall_miss_latency::total 93687596488 # number of overall miss cycles 1571system.cpu1.dcache.ReadReq_accesses::cpu1.data 87197498 # number of ReadReq accesses(hits+misses) 1572system.cpu1.dcache.ReadReq_accesses::total 87197498 # number of ReadReq accesses(hits+misses) 1573system.cpu1.dcache.WriteReq_accesses::cpu1.data 76111898 # number of WriteReq accesses(hits+misses) 1574system.cpu1.dcache.WriteReq_accesses::total 76111898 # number of WriteReq accesses(hits+misses) 1575system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 892949 # number of SoftPFReq accesses(hits+misses) 1576system.cpu1.dcache.SoftPFReq_accesses::total 892949 # number of SoftPFReq accesses(hits+misses) 1577system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 532419 # number of WriteInvalidateReq accesses(hits+misses) 1578system.cpu1.dcache.WriteInvalidateReq_accesses::total 532419 # number of WriteInvalidateReq accesses(hits+misses) 1579system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2029992 # number of LoadLockedReq accesses(hits+misses) 1580system.cpu1.dcache.LoadLockedReq_accesses::total 2029992 # number of LoadLockedReq accesses(hits+misses) 1581system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2028447 # number of StoreCondReq accesses(hits+misses) 1582system.cpu1.dcache.StoreCondReq_accesses::total 2028447 # number of StoreCondReq accesses(hits+misses) 1583system.cpu1.dcache.demand_accesses::cpu1.data 163309396 # number of demand (read+write) accesses 1584system.cpu1.dcache.demand_accesses::total 163309396 # number of demand (read+write) accesses 1585system.cpu1.dcache.overall_accesses::cpu1.data 164202345 # number of overall (read+write) accesses 1586system.cpu1.dcache.overall_accesses::total 164202345 # number of overall (read+write) accesses 1587system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.041199 # miss rate for ReadReq accesses 1588system.cpu1.dcache.ReadReq_miss_rate::total 0.041199 # miss rate for ReadReq accesses 1589system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030105 # miss rate for WriteReq accesses 1590system.cpu1.dcache.WriteReq_miss_rate::total 0.030105 # miss rate for WriteReq accesses 1591system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.737409 # miss rate for SoftPFReq accesses 1592system.cpu1.dcache.SoftPFReq_miss_rate::total 0.737409 # miss rate for SoftPFReq accesses 1593system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.858264 # miss rate for WriteInvalidateReq accesses 1594system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.858264 # miss rate for WriteInvalidateReq accesses 1595system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091489 # miss rate for LoadLockedReq accesses 1596system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091489 # miss rate for LoadLockedReq accesses 1597system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.096626 # miss rate for StoreCondReq accesses 1598system.cpu1.dcache.StoreCondReq_miss_rate::total 0.096626 # miss rate for StoreCondReq accesses 1599system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036028 # miss rate for demand accesses 1600system.cpu1.dcache.demand_miss_rate::total 0.036028 # miss rate for demand accesses 1601system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039842 # miss rate for overall accesses 1602system.cpu1.dcache.overall_miss_rate::total 0.039842 # miss rate for overall accesses 1603system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15045.462662 # average ReadReq miss latency 1604system.cpu1.dcache.ReadReq_avg_miss_latency::total 15045.462662 # average ReadReq miss latency 1605system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17299.140762 # average WriteReq miss latency 1606system.cpu1.dcache.WriteReq_avg_miss_latency::total 17299.140762 # average WriteReq miss latency 1607system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27524.858291 # average WriteInvalidateReq miss latency 1608system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27524.858291 # average WriteInvalidateReq miss latency 1609system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15075.012185 # average LoadLockedReq miss latency 1610system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15075.012185 # average LoadLockedReq miss latency 1611system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20796.021689 # average StoreCondReq miss latency 1612system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20796.021689 # average StoreCondReq miss latency | 1535system.cpu1.dcache.tags.tag_accesses 302037341 # Number of tag accesses 1536system.cpu1.dcache.tags.data_accesses 302037341 # Number of data accesses 1537system.cpu1.dcache.ReadReq_hits::cpu1.data 73896099 # number of ReadReq hits 1538system.cpu1.dcache.ReadReq_hits::total 73896099 # number of ReadReq hits 1539system.cpu1.dcache.WriteReq_hits::cpu1.data 64629380 # number of WriteReq hits 1540system.cpu1.dcache.WriteReq_hits::total 64629380 # number of WriteReq hits 1541system.cpu1.dcache.SoftPFReq_hits::cpu1.data 204586 # number of SoftPFReq hits 1542system.cpu1.dcache.SoftPFReq_hits::total 204586 # number of SoftPFReq hits 1543system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 67650 # number of WriteInvalidateReq hits 1544system.cpu1.dcache.WriteInvalidateReq_hits::total 67650 # number of WriteInvalidateReq hits 1545system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1684264 # number of LoadLockedReq hits 1546system.cpu1.dcache.LoadLockedReq_hits::total 1684264 # number of LoadLockedReq hits 1547system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1653940 # number of StoreCondReq hits 1548system.cpu1.dcache.StoreCondReq_hits::total 1653940 # number of StoreCondReq hits 1549system.cpu1.dcache.demand_hits::cpu1.data 138525479 # number of demand (read+write) hits 1550system.cpu1.dcache.demand_hits::total 138525479 # number of demand (read+write) hits 1551system.cpu1.dcache.overall_hits::cpu1.data 138730065 # number of overall hits 1552system.cpu1.dcache.overall_hits::total 138730065 # number of overall hits 1553system.cpu1.dcache.ReadReq_misses::cpu1.data 3123049 # number of ReadReq misses 1554system.cpu1.dcache.ReadReq_misses::total 3123049 # number of ReadReq misses 1555system.cpu1.dcache.WriteReq_misses::cpu1.data 2001792 # number of WriteReq misses 1556system.cpu1.dcache.WriteReq_misses::total 2001792 # number of WriteReq misses 1557system.cpu1.dcache.SoftPFReq_misses::cpu1.data 560125 # number of SoftPFReq misses 1558system.cpu1.dcache.SoftPFReq_misses::total 560125 # number of SoftPFReq misses 1559system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 418714 # number of WriteInvalidateReq misses 1560system.cpu1.dcache.WriteInvalidateReq_misses::total 418714 # number of WriteInvalidateReq misses 1561system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158898 # number of LoadLockedReq misses 1562system.cpu1.dcache.LoadLockedReq_misses::total 158898 # number of LoadLockedReq misses 1563system.cpu1.dcache.StoreCondReq_misses::cpu1.data 187849 # number of StoreCondReq misses 1564system.cpu1.dcache.StoreCondReq_misses::total 187849 # number of StoreCondReq misses 1565system.cpu1.dcache.demand_misses::cpu1.data 5124841 # number of demand (read+write) misses 1566system.cpu1.dcache.demand_misses::total 5124841 # number of demand (read+write) misses 1567system.cpu1.dcache.overall_misses::cpu1.data 5684966 # number of overall misses 1568system.cpu1.dcache.overall_misses::total 5684966 # number of overall misses 1569system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43997999443 # number of ReadReq miss cycles 1570system.cpu1.dcache.ReadReq_miss_latency::total 43997999443 # number of ReadReq miss cycles 1571system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 34323796172 # number of WriteReq miss cycles 1572system.cpu1.dcache.WriteReq_miss_latency::total 34323796172 # number of WriteReq miss cycles 1573system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11321642584 # number of WriteInvalidateReq miss cycles 1574system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11321642584 # number of WriteInvalidateReq miss cycles 1575system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2327905715 # number of LoadLockedReq miss cycles 1576system.cpu1.dcache.LoadLockedReq_miss_latency::total 2327905715 # number of LoadLockedReq miss cycles 1577system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3931505754 # number of StoreCondReq miss cycles 1578system.cpu1.dcache.StoreCondReq_miss_latency::total 3931505754 # number of StoreCondReq miss cycles 1579system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3098000 # number of StoreCondFailReq miss cycles 1580system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3098000 # number of StoreCondFailReq miss cycles 1581system.cpu1.dcache.demand_miss_latency::cpu1.data 78321795615 # number of demand (read+write) miss cycles 1582system.cpu1.dcache.demand_miss_latency::total 78321795615 # number of demand (read+write) miss cycles 1583system.cpu1.dcache.overall_miss_latency::cpu1.data 78321795615 # number of overall miss cycles 1584system.cpu1.dcache.overall_miss_latency::total 78321795615 # number of overall miss cycles 1585system.cpu1.dcache.ReadReq_accesses::cpu1.data 77019148 # number of ReadReq accesses(hits+misses) 1586system.cpu1.dcache.ReadReq_accesses::total 77019148 # number of ReadReq accesses(hits+misses) 1587system.cpu1.dcache.WriteReq_accesses::cpu1.data 66631172 # number of WriteReq accesses(hits+misses) 1588system.cpu1.dcache.WriteReq_accesses::total 66631172 # number of WriteReq accesses(hits+misses) 1589system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 764711 # number of SoftPFReq accesses(hits+misses) 1590system.cpu1.dcache.SoftPFReq_accesses::total 764711 # number of SoftPFReq accesses(hits+misses) 1591system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 486364 # number of WriteInvalidateReq accesses(hits+misses) 1592system.cpu1.dcache.WriteInvalidateReq_accesses::total 486364 # number of WriteInvalidateReq accesses(hits+misses) 1593system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1843162 # number of LoadLockedReq accesses(hits+misses) 1594system.cpu1.dcache.LoadLockedReq_accesses::total 1843162 # number of LoadLockedReq accesses(hits+misses) 1595system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1841789 # number of StoreCondReq accesses(hits+misses) 1596system.cpu1.dcache.StoreCondReq_accesses::total 1841789 # number of StoreCondReq accesses(hits+misses) 1597system.cpu1.dcache.demand_accesses::cpu1.data 143650320 # number of demand (read+write) accesses 1598system.cpu1.dcache.demand_accesses::total 143650320 # number of demand (read+write) accesses 1599system.cpu1.dcache.overall_accesses::cpu1.data 144415031 # number of overall (read+write) accesses 1600system.cpu1.dcache.overall_accesses::total 144415031 # number of overall (read+write) accesses 1601system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040549 # miss rate for ReadReq accesses 1602system.cpu1.dcache.ReadReq_miss_rate::total 0.040549 # miss rate for ReadReq accesses 1603system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030043 # miss rate for WriteReq accesses 1604system.cpu1.dcache.WriteReq_miss_rate::total 0.030043 # miss rate for WriteReq accesses 1605system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.732466 # miss rate for SoftPFReq accesses 1606system.cpu1.dcache.SoftPFReq_miss_rate::total 0.732466 # miss rate for SoftPFReq accesses 1607system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.860907 # miss rate for WriteInvalidateReq accesses 1608system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.860907 # miss rate for WriteInvalidateReq accesses 1609system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086209 # miss rate for LoadLockedReq accesses 1610system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086209 # miss rate for LoadLockedReq accesses 1611system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.101993 # miss rate for StoreCondReq accesses 1612system.cpu1.dcache.StoreCondReq_miss_rate::total 0.101993 # miss rate for StoreCondReq accesses 1613system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035676 # miss rate for demand accesses 1614system.cpu1.dcache.demand_miss_rate::total 0.035676 # miss rate for demand accesses 1615system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039365 # miss rate for overall accesses 1616system.cpu1.dcache.overall_miss_rate::total 0.039365 # miss rate for overall accesses 1617system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14088.155339 # average ReadReq miss latency 1618system.cpu1.dcache.ReadReq_avg_miss_latency::total 14088.155339 # average ReadReq miss latency 1619system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17146.534791 # average WriteReq miss latency 1620system.cpu1.dcache.WriteReq_avg_miss_latency::total 17146.534791 # average WriteReq miss latency 1621system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27039.082964 # average WriteInvalidateReq miss latency 1622system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27039.082964 # average WriteInvalidateReq miss latency 1623system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14650.314762 # average LoadLockedReq miss latency 1624system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14650.314762 # average LoadLockedReq miss latency 1625system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20929.074704 # average StoreCondReq miss latency 1626system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20929.074704 # average StoreCondReq miss latency |
| 1613system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1614system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency | 1627system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1628system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency |
| 1615system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15923.120490 # average overall miss latency 1616system.cpu1.dcache.demand_avg_miss_latency::total 15923.120490 # average overall miss latency 1617system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14320.470435 # average overall miss latency 1618system.cpu1.dcache.overall_avg_miss_latency::total 14320.470435 # average overall miss latency | 1629system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15282.775722 # average overall miss latency 1630system.cpu1.dcache.demand_avg_miss_latency::total 15282.775722 # average overall miss latency 1631system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13777.003348 # average overall miss latency 1632system.cpu1.dcache.overall_avg_miss_latency::total 13777.003348 # average overall miss latency |
| 1619system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1620system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1621system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1622system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1623system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1624system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1625system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1626system.cpu1.dcache.cache_copies 0 # number of cache copies performed | 1633system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1634system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1635system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1636system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1637system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1638system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1639system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1640system.cpu1.dcache.cache_copies 0 # number of cache copies performed |
| 1627system.cpu1.dcache.writebacks::writebacks 3514313 # number of writebacks 1628system.cpu1.dcache.writebacks::total 3514313 # number of writebacks 1629system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 402319 # number of ReadReq MSHR hits 1630system.cpu1.dcache.ReadReq_mshr_hits::total 402319 # number of ReadReq MSHR hits 1631system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 938195 # number of WriteReq MSHR hits 1632system.cpu1.dcache.WriteReq_mshr_hits::total 938195 # number of WriteReq MSHR hits 1633system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 62 # number of WriteInvalidateReq MSHR hits 1634system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 62 # number of WriteInvalidateReq MSHR hits 1635system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44601 # number of LoadLockedReq MSHR hits 1636system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44601 # number of LoadLockedReq MSHR hits 1637system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 41 # number of StoreCondReq MSHR hits 1638system.cpu1.dcache.StoreCondReq_mshr_hits::total 41 # number of StoreCondReq MSHR hits 1639system.cpu1.dcache.demand_mshr_hits::cpu1.data 1340514 # number of demand (read+write) MSHR hits 1640system.cpu1.dcache.demand_mshr_hits::total 1340514 # number of demand (read+write) MSHR hits 1641system.cpu1.dcache.overall_mshr_hits::cpu1.data 1340514 # number of overall MSHR hits 1642system.cpu1.dcache.overall_mshr_hits::total 1340514 # number of overall MSHR hits 1643system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3190099 # number of ReadReq MSHR misses 1644system.cpu1.dcache.ReadReq_mshr_misses::total 3190099 # number of ReadReq MSHR misses 1645system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1353133 # number of WriteReq MSHR misses 1646system.cpu1.dcache.WriteReq_mshr_misses::total 1353133 # number of WriteReq MSHR misses 1647system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 658162 # number of SoftPFReq MSHR misses 1648system.cpu1.dcache.SoftPFReq_mshr_misses::total 658162 # number of SoftPFReq MSHR misses 1649system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 456894 # number of WriteInvalidateReq MSHR misses 1650system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 456894 # number of WriteInvalidateReq MSHR misses 1651system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 141121 # number of LoadLockedReq MSHR misses 1652system.cpu1.dcache.LoadLockedReq_mshr_misses::total 141121 # number of LoadLockedReq MSHR misses 1653system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195959 # number of StoreCondReq MSHR misses 1654system.cpu1.dcache.StoreCondReq_mshr_misses::total 195959 # number of StoreCondReq MSHR misses 1655system.cpu1.dcache.demand_mshr_misses::cpu1.data 4543232 # number of demand (read+write) MSHR misses 1656system.cpu1.dcache.demand_mshr_misses::total 4543232 # number of demand (read+write) MSHR misses 1657system.cpu1.dcache.overall_mshr_misses::cpu1.data 5201394 # number of overall MSHR misses 1658system.cpu1.dcache.overall_mshr_misses::total 5201394 # number of overall MSHR misses 1659system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 41952700254 # number of ReadReq MSHR miss cycles 1660system.cpu1.dcache.ReadReq_mshr_miss_latency::total 41952700254 # number of ReadReq MSHR miss cycles 1661system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21819340170 # number of WriteReq MSHR miss cycles 1662system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21819340170 # number of WriteReq MSHR miss cycles 1663system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13178817169 # number of SoftPFReq MSHR miss cycles 1664system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13178817169 # number of SoftPFReq MSHR miss cycles 1665system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11885329605 # number of WriteInvalidateReq MSHR miss cycles 1666system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11885329605 # number of WriteInvalidateReq MSHR miss cycles 1667system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1778237950 # number of LoadLockedReq MSHR miss cycles 1668system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1778237950 # number of LoadLockedReq MSHR miss cycles 1669system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3771476218 # number of StoreCondReq MSHR miss cycles 1670system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3771476218 # number of StoreCondReq MSHR miss cycles 1671system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2255500 # number of StoreCondFailReq MSHR miss cycles 1672system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2255500 # number of StoreCondFailReq MSHR miss cycles 1673system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 63772040424 # number of demand (read+write) MSHR miss cycles 1674system.cpu1.dcache.demand_mshr_miss_latency::total 63772040424 # number of demand (read+write) MSHR miss cycles 1675system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 76950857593 # number of overall MSHR miss cycles 1676system.cpu1.dcache.overall_mshr_miss_latency::total 76950857593 # number of overall MSHR miss cycles 1677system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 517375000 # number of ReadReq MSHR uncacheable cycles 1678system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 517375000 # number of ReadReq MSHR uncacheable cycles 1679system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 587265498 # number of WriteReq MSHR uncacheable cycles 1680system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 587265498 # number of WriteReq MSHR uncacheable cycles 1681system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1104640498 # number of overall MSHR uncacheable cycles 1682system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1104640498 # number of overall MSHR uncacheable cycles 1683system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036585 # mshr miss rate for ReadReq accesses 1684system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036585 # mshr miss rate for ReadReq accesses 1685system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017778 # mshr miss rate for WriteReq accesses 1686system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017778 # mshr miss rate for WriteReq accesses 1687system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.737066 # mshr miss rate for SoftPFReq accesses 1688system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.737066 # mshr miss rate for SoftPFReq accesses 1689system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.858147 # mshr miss rate for WriteInvalidateReq accesses 1690system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.858147 # mshr miss rate for WriteInvalidateReq accesses 1691system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069518 # mshr miss rate for LoadLockedReq accesses 1692system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069518 # mshr miss rate for LoadLockedReq accesses 1693system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096605 # mshr miss rate for StoreCondReq accesses 1694system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096605 # mshr miss rate for StoreCondReq accesses 1695system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027820 # mshr miss rate for demand accesses 1696system.cpu1.dcache.demand_mshr_miss_rate::total 0.027820 # mshr miss rate for demand accesses 1697system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031677 # mshr miss rate for overall accesses 1698system.cpu1.dcache.overall_mshr_miss_rate::total 0.031677 # mshr miss rate for overall accesses 1699system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13150.908562 # average ReadReq mshr miss latency 1700system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13150.908562 # average ReadReq mshr miss latency 1701system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16125.052135 # average WriteReq mshr miss latency 1702system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16125.052135 # average WriteReq mshr miss latency 1703system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20023.667682 # average SoftPFReq mshr miss latency 1704system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20023.667682 # average SoftPFReq mshr miss latency 1705system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26013.319512 # average WriteInvalidateReq mshr miss latency 1706system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 26013.319512 # average WriteInvalidateReq mshr miss latency 1707system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12600.803211 # average LoadLockedReq mshr miss latency 1708system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12600.803211 # average LoadLockedReq mshr miss latency 1709system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19246.251604 # average StoreCondReq mshr miss latency 1710system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19246.251604 # average StoreCondReq mshr miss latency | 1641system.cpu1.dcache.writebacks::writebacks 3038485 # number of writebacks 1642system.cpu1.dcache.writebacks::total 3038485 # number of writebacks 1643system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 341138 # number of ReadReq MSHR hits 1644system.cpu1.dcache.ReadReq_mshr_hits::total 341138 # number of ReadReq MSHR hits 1645system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 817934 # number of WriteReq MSHR hits 1646system.cpu1.dcache.WriteReq_mshr_hits::total 817934 # number of WriteReq MSHR hits 1647system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 47 # number of WriteInvalidateReq MSHR hits 1648system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 47 # number of WriteInvalidateReq MSHR hits 1649system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39869 # number of LoadLockedReq MSHR hits 1650system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39869 # number of LoadLockedReq MSHR hits 1651system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 63 # number of StoreCondReq MSHR hits 1652system.cpu1.dcache.StoreCondReq_mshr_hits::total 63 # number of StoreCondReq MSHR hits 1653system.cpu1.dcache.demand_mshr_hits::cpu1.data 1159072 # number of demand (read+write) MSHR hits 1654system.cpu1.dcache.demand_mshr_hits::total 1159072 # number of demand (read+write) MSHR hits 1655system.cpu1.dcache.overall_mshr_hits::cpu1.data 1159072 # number of overall MSHR hits 1656system.cpu1.dcache.overall_mshr_hits::total 1159072 # number of overall MSHR hits 1657system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2781911 # number of ReadReq MSHR misses 1658system.cpu1.dcache.ReadReq_mshr_misses::total 2781911 # number of ReadReq MSHR misses 1659system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1183858 # number of WriteReq MSHR misses 1660system.cpu1.dcache.WriteReq_mshr_misses::total 1183858 # number of WriteReq MSHR misses 1661system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 559909 # number of SoftPFReq MSHR misses 1662system.cpu1.dcache.SoftPFReq_mshr_misses::total 559909 # number of SoftPFReq MSHR misses 1663system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 418667 # number of WriteInvalidateReq MSHR misses 1664system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 418667 # number of WriteInvalidateReq MSHR misses 1665system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 119029 # number of LoadLockedReq MSHR misses 1666system.cpu1.dcache.LoadLockedReq_mshr_misses::total 119029 # number of LoadLockedReq MSHR misses 1667system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 187786 # number of StoreCondReq MSHR misses 1668system.cpu1.dcache.StoreCondReq_mshr_misses::total 187786 # number of StoreCondReq MSHR misses 1669system.cpu1.dcache.demand_mshr_misses::cpu1.data 3965769 # number of demand (read+write) MSHR misses 1670system.cpu1.dcache.demand_mshr_misses::total 3965769 # number of demand (read+write) MSHR misses 1671system.cpu1.dcache.overall_mshr_misses::cpu1.data 4525678 # number of overall MSHR misses 1672system.cpu1.dcache.overall_mshr_misses::total 4525678 # number of overall MSHR misses 1673system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5083 # number of ReadReq MSHR uncacheable 1674system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5083 # number of ReadReq MSHR uncacheable 1675system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5087 # number of WriteReq MSHR uncacheable 1676system.cpu1.dcache.WriteReq_mshr_uncacheable::total 5087 # number of WriteReq MSHR uncacheable 1677system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10170 # number of overall MSHR uncacheable misses 1678system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10170 # number of overall MSHR uncacheable misses 1679system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 34163110205 # number of ReadReq MSHR miss cycles 1680system.cpu1.dcache.ReadReq_mshr_miss_latency::total 34163110205 # number of ReadReq MSHR miss cycles 1681system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 18897365962 # number of WriteReq MSHR miss cycles 1682system.cpu1.dcache.WriteReq_mshr_miss_latency::total 18897365962 # number of WriteReq MSHR miss cycles 1683system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10922522145 # number of SoftPFReq MSHR miss cycles 1684system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 10922522145 # number of SoftPFReq MSHR miss cycles 1685system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 10687856416 # number of WriteInvalidateReq MSHR miss cycles 1686system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 10687856416 # number of WriteInvalidateReq MSHR miss cycles 1687system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1507570159 # number of LoadLockedReq MSHR miss cycles 1688system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1507570159 # number of LoadLockedReq MSHR miss cycles 1689system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3640144702 # number of StoreCondReq MSHR miss cycles 1690system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3640144702 # number of StoreCondReq MSHR miss cycles 1691system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2571500 # number of StoreCondFailReq MSHR miss cycles 1692system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2571500 # number of StoreCondFailReq MSHR miss cycles 1693system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 53060476167 # number of demand (read+write) MSHR miss cycles 1694system.cpu1.dcache.demand_mshr_miss_latency::total 53060476167 # number of demand (read+write) MSHR miss cycles 1695system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 63982998312 # number of overall MSHR miss cycles 1696system.cpu1.dcache.overall_mshr_miss_latency::total 63982998312 # number of overall MSHR miss cycles 1697system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 518115500 # number of ReadReq MSHR uncacheable cycles 1698system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 518115500 # number of ReadReq MSHR uncacheable cycles 1699system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 583373999 # number of WriteReq MSHR uncacheable cycles 1700system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 583373999 # number of WriteReq MSHR uncacheable cycles 1701system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1101489499 # number of overall MSHR uncacheable cycles 1702system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1101489499 # number of overall MSHR uncacheable cycles 1703system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036120 # mshr miss rate for ReadReq accesses 1704system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036120 # mshr miss rate for ReadReq accesses 1705system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017767 # mshr miss rate for WriteReq accesses 1706system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017767 # mshr miss rate for WriteReq accesses 1707system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.732184 # mshr miss rate for SoftPFReq accesses 1708system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.732184 # mshr miss rate for SoftPFReq accesses 1709system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.860810 # mshr miss rate for WriteInvalidateReq accesses 1710system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.860810 # mshr miss rate for WriteInvalidateReq accesses 1711system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064579 # mshr miss rate for LoadLockedReq accesses 1712system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064579 # mshr miss rate for LoadLockedReq accesses 1713system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.101958 # mshr miss rate for StoreCondReq accesses 1714system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.101958 # mshr miss rate for StoreCondReq accesses 1715system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027607 # mshr miss rate for demand accesses 1716system.cpu1.dcache.demand_mshr_miss_rate::total 0.027607 # mshr miss rate for demand accesses 1717system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031338 # mshr miss rate for overall accesses 1718system.cpu1.dcache.overall_mshr_miss_rate::total 0.031338 # mshr miss rate for overall accesses 1719system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12280.446860 # average ReadReq mshr miss latency 1720system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12280.446860 # average ReadReq mshr miss latency 1721system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15962.527568 # average WriteReq mshr miss latency 1722system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15962.527568 # average WriteReq mshr miss latency 1723system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19507.673827 # average SoftPFReq mshr miss latency 1724system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19507.673827 # average SoftPFReq mshr miss latency 1725system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25528.299140 # average WriteInvalidateReq mshr miss latency 1726system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25528.299140 # average WriteInvalidateReq mshr miss latency 1727system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12665.570231 # average LoadLockedReq mshr miss latency 1728system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12665.570231 # average LoadLockedReq mshr miss latency 1729system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19384.537197 # average StoreCondReq mshr miss latency 1730system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19384.537197 # average StoreCondReq mshr miss latency |
| 1711system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1712system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency | 1731system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1732system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency |
| 1713system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14036.712284 # average overall mshr miss latency 1714system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14036.712284 # average overall mshr miss latency 1715system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14794.275841 # average overall mshr miss latency 1716system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14794.275841 # average overall mshr miss latency 1717system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1718system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1719system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1720system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1721system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1722system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1733system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13379.618472 # average overall mshr miss latency 1734system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13379.618472 # average overall mshr miss latency 1735system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14137.770807 # average overall mshr miss latency 1736system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14137.770807 # average overall mshr miss latency 1737system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 101931.044659 # average ReadReq mshr uncacheable latency 1738system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 101931.044659 # average ReadReq mshr uncacheable latency 1739system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 114679.378612 # average WriteReq mshr uncacheable latency 1740system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 114679.378612 # average WriteReq mshr uncacheable latency 1741system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 108307.718682 # average overall mshr uncacheable latency 1742system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 108307.718682 # average overall mshr uncacheable latency |
| 1723system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1743system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1724system.cpu1.icache.tags.replacements 9531492 # number of replacements 1725system.cpu1.icache.tags.tagsinuse 507.211334 # Cycle average of tags in use 1726system.cpu1.icache.tags.total_refs 241397065 # Total number of references to valid blocks. 1727system.cpu1.icache.tags.sampled_refs 9532004 # Sample count of references to valid blocks. 1728system.cpu1.icache.tags.avg_refs 25.324902 # Average number of references to valid blocks. 1729system.cpu1.icache.tags.warmup_cycle 8370013399000 # Cycle when the warmup percentage was hit. 1730system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.211334 # Average occupied blocks per requestor 1731system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990647 # Average percentage of cache occupancy 1732system.cpu1.icache.tags.occ_percent::total 0.990647 # Average percentage of cache occupancy | 1744system.cpu1.icache.tags.replacements 8549825 # number of replacements 1745system.cpu1.icache.tags.tagsinuse 507.203595 # Cycle average of tags in use 1746system.cpu1.icache.tags.total_refs 211942190 # Total number of references to valid blocks. 1747system.cpu1.icache.tags.sampled_refs 8550337 # Sample count of references to valid blocks. 1748system.cpu1.icache.tags.avg_refs 24.787583 # Average number of references to valid blocks. 1749system.cpu1.icache.tags.warmup_cycle 8370006207500 # Cycle when the warmup percentage was hit. 1750system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.203595 # Average occupied blocks per requestor 1751system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990632 # Average percentage of cache occupancy 1752system.cpu1.icache.tags.occ_percent::total 0.990632 # Average percentage of cache occupancy |
| 1733system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 1753system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 1734system.cpu1.icache.tags.age_task_id_blocks_1024::0 131 # Occupied blocks per task id 1735system.cpu1.icache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id 1736system.cpu1.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id | 1754system.cpu1.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id 1755system.cpu1.icache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id 1756system.cpu1.icache.tags.age_task_id_blocks_1024::2 76 # Occupied blocks per task id |
| 1737system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 1757system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 1738system.cpu1.icache.tags.tag_accesses 511390144 # Number of tag accesses 1739system.cpu1.icache.tags.data_accesses 511390144 # Number of data accesses 1740system.cpu1.icache.ReadReq_hits::cpu1.inst 241397065 # number of ReadReq hits 1741system.cpu1.icache.ReadReq_hits::total 241397065 # number of ReadReq hits 1742system.cpu1.icache.demand_hits::cpu1.inst 241397065 # number of demand (read+write) hits 1743system.cpu1.icache.demand_hits::total 241397065 # number of demand (read+write) hits 1744system.cpu1.icache.overall_hits::cpu1.inst 241397065 # number of overall hits 1745system.cpu1.icache.overall_hits::total 241397065 # number of overall hits 1746system.cpu1.icache.ReadReq_misses::cpu1.inst 9532005 # number of ReadReq misses 1747system.cpu1.icache.ReadReq_misses::total 9532005 # number of ReadReq misses 1748system.cpu1.icache.demand_misses::cpu1.inst 9532005 # number of demand (read+write) misses 1749system.cpu1.icache.demand_misses::total 9532005 # number of demand (read+write) misses 1750system.cpu1.icache.overall_misses::cpu1.inst 9532005 # number of overall misses 1751system.cpu1.icache.overall_misses::total 9532005 # number of overall misses 1752system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 94727843232 # number of ReadReq miss cycles 1753system.cpu1.icache.ReadReq_miss_latency::total 94727843232 # number of ReadReq miss cycles 1754system.cpu1.icache.demand_miss_latency::cpu1.inst 94727843232 # number of demand (read+write) miss cycles 1755system.cpu1.icache.demand_miss_latency::total 94727843232 # number of demand (read+write) miss cycles 1756system.cpu1.icache.overall_miss_latency::cpu1.inst 94727843232 # number of overall miss cycles 1757system.cpu1.icache.overall_miss_latency::total 94727843232 # number of overall miss cycles 1758system.cpu1.icache.ReadReq_accesses::cpu1.inst 250929070 # number of ReadReq accesses(hits+misses) 1759system.cpu1.icache.ReadReq_accesses::total 250929070 # number of ReadReq accesses(hits+misses) 1760system.cpu1.icache.demand_accesses::cpu1.inst 250929070 # number of demand (read+write) accesses 1761system.cpu1.icache.demand_accesses::total 250929070 # number of demand (read+write) accesses 1762system.cpu1.icache.overall_accesses::cpu1.inst 250929070 # number of overall (read+write) accesses 1763system.cpu1.icache.overall_accesses::total 250929070 # number of overall (read+write) accesses 1764system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.037987 # miss rate for ReadReq accesses 1765system.cpu1.icache.ReadReq_miss_rate::total 0.037987 # miss rate for ReadReq accesses 1766system.cpu1.icache.demand_miss_rate::cpu1.inst 0.037987 # miss rate for demand accesses 1767system.cpu1.icache.demand_miss_rate::total 0.037987 # miss rate for demand accesses 1768system.cpu1.icache.overall_miss_rate::cpu1.inst 0.037987 # miss rate for overall accesses 1769system.cpu1.icache.overall_miss_rate::total 0.037987 # miss rate for overall accesses 1770system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9937.871752 # average ReadReq miss latency 1771system.cpu1.icache.ReadReq_avg_miss_latency::total 9937.871752 # average ReadReq miss latency 1772system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9937.871752 # average overall miss latency 1773system.cpu1.icache.demand_avg_miss_latency::total 9937.871752 # average overall miss latency 1774system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9937.871752 # average overall miss latency 1775system.cpu1.icache.overall_avg_miss_latency::total 9937.871752 # average overall miss latency | 1758system.cpu1.icache.tags.tag_accesses 449535393 # Number of tag accesses 1759system.cpu1.icache.tags.data_accesses 449535393 # Number of data accesses 1760system.cpu1.icache.ReadReq_hits::cpu1.inst 211942190 # number of ReadReq hits 1761system.cpu1.icache.ReadReq_hits::total 211942190 # number of ReadReq hits 1762system.cpu1.icache.demand_hits::cpu1.inst 211942190 # number of demand (read+write) hits 1763system.cpu1.icache.demand_hits::total 211942190 # number of demand (read+write) hits 1764system.cpu1.icache.overall_hits::cpu1.inst 211942190 # number of overall hits 1765system.cpu1.icache.overall_hits::total 211942190 # number of overall hits 1766system.cpu1.icache.ReadReq_misses::cpu1.inst 8550338 # number of ReadReq misses 1767system.cpu1.icache.ReadReq_misses::total 8550338 # number of ReadReq misses 1768system.cpu1.icache.demand_misses::cpu1.inst 8550338 # number of demand (read+write) misses 1769system.cpu1.icache.demand_misses::total 8550338 # number of demand (read+write) misses 1770system.cpu1.icache.overall_misses::cpu1.inst 8550338 # number of overall misses 1771system.cpu1.icache.overall_misses::total 8550338 # number of overall misses 1772system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 84064963562 # number of ReadReq miss cycles 1773system.cpu1.icache.ReadReq_miss_latency::total 84064963562 # number of ReadReq miss cycles 1774system.cpu1.icache.demand_miss_latency::cpu1.inst 84064963562 # number of demand (read+write) miss cycles 1775system.cpu1.icache.demand_miss_latency::total 84064963562 # number of demand (read+write) miss cycles 1776system.cpu1.icache.overall_miss_latency::cpu1.inst 84064963562 # number of overall miss cycles 1777system.cpu1.icache.overall_miss_latency::total 84064963562 # number of overall miss cycles 1778system.cpu1.icache.ReadReq_accesses::cpu1.inst 220492528 # number of ReadReq accesses(hits+misses) 1779system.cpu1.icache.ReadReq_accesses::total 220492528 # number of ReadReq accesses(hits+misses) 1780system.cpu1.icache.demand_accesses::cpu1.inst 220492528 # number of demand (read+write) accesses 1781system.cpu1.icache.demand_accesses::total 220492528 # number of demand (read+write) accesses 1782system.cpu1.icache.overall_accesses::cpu1.inst 220492528 # number of overall (read+write) accesses 1783system.cpu1.icache.overall_accesses::total 220492528 # number of overall (read+write) accesses 1784system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038778 # miss rate for ReadReq accesses 1785system.cpu1.icache.ReadReq_miss_rate::total 0.038778 # miss rate for ReadReq accesses 1786system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038778 # miss rate for demand accesses 1787system.cpu1.icache.demand_miss_rate::total 0.038778 # miss rate for demand accesses 1788system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038778 # miss rate for overall accesses 1789system.cpu1.icache.overall_miss_rate::total 0.038778 # miss rate for overall accesses 1790system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9831.770810 # average ReadReq miss latency 1791system.cpu1.icache.ReadReq_avg_miss_latency::total 9831.770810 # average ReadReq miss latency 1792system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9831.770810 # average overall miss latency 1793system.cpu1.icache.demand_avg_miss_latency::total 9831.770810 # average overall miss latency 1794system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9831.770810 # average overall miss latency 1795system.cpu1.icache.overall_avg_miss_latency::total 9831.770810 # average overall miss latency |
| 1776system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1777system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1778system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1779system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1780system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1781system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1782system.cpu1.icache.fast_writes 0 # number of fast writes performed 1783system.cpu1.icache.cache_copies 0 # number of cache copies performed | 1796system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1797system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1798system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1799system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1800system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1801system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1802system.cpu1.icache.fast_writes 0 # number of fast writes performed 1803system.cpu1.icache.cache_copies 0 # number of cache copies performed |
| 1784system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9532005 # number of ReadReq MSHR misses 1785system.cpu1.icache.ReadReq_mshr_misses::total 9532005 # number of ReadReq MSHR misses 1786system.cpu1.icache.demand_mshr_misses::cpu1.inst 9532005 # number of demand (read+write) MSHR misses 1787system.cpu1.icache.demand_mshr_misses::total 9532005 # number of demand (read+write) MSHR misses 1788system.cpu1.icache.overall_mshr_misses::cpu1.inst 9532005 # number of overall MSHR misses 1789system.cpu1.icache.overall_mshr_misses::total 9532005 # number of overall MSHR misses 1790system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 85170319722 # number of ReadReq MSHR miss cycles 1791system.cpu1.icache.ReadReq_mshr_miss_latency::total 85170319722 # number of ReadReq MSHR miss cycles 1792system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 85170319722 # number of demand (read+write) MSHR miss cycles 1793system.cpu1.icache.demand_mshr_miss_latency::total 85170319722 # number of demand (read+write) MSHR miss cycles 1794system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 85170319722 # number of overall MSHR miss cycles 1795system.cpu1.icache.overall_mshr_miss_latency::total 85170319722 # number of overall MSHR miss cycles 1796system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8117000 # number of ReadReq MSHR uncacheable cycles 1797system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8117000 # number of ReadReq MSHR uncacheable cycles 1798system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8117000 # number of overall MSHR uncacheable cycles 1799system.cpu1.icache.overall_mshr_uncacheable_latency::total 8117000 # number of overall MSHR uncacheable cycles 1800system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.037987 # mshr miss rate for ReadReq accesses 1801system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.037987 # mshr miss rate for ReadReq accesses 1802system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.037987 # mshr miss rate for demand accesses 1803system.cpu1.icache.demand_mshr_miss_rate::total 0.037987 # mshr miss rate for demand accesses 1804system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.037987 # mshr miss rate for overall accesses 1805system.cpu1.icache.overall_mshr_miss_rate::total 0.037987 # mshr miss rate for overall accesses 1806system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8935.194612 # average ReadReq mshr miss latency 1807system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8935.194612 # average ReadReq mshr miss latency 1808system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8935.194612 # average overall mshr miss latency 1809system.cpu1.icache.demand_avg_mshr_miss_latency::total 8935.194612 # average overall mshr miss latency 1810system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8935.194612 # average overall mshr miss latency 1811system.cpu1.icache.overall_avg_mshr_miss_latency::total 8935.194612 # average overall mshr miss latency 1812system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1813system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1814system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1815system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1804system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8550338 # number of ReadReq MSHR misses 1805system.cpu1.icache.ReadReq_mshr_misses::total 8550338 # number of ReadReq MSHR misses 1806system.cpu1.icache.demand_mshr_misses::cpu1.inst 8550338 # number of demand (read+write) MSHR misses 1807system.cpu1.icache.demand_mshr_misses::total 8550338 # number of demand (read+write) MSHR misses 1808system.cpu1.icache.overall_mshr_misses::cpu1.inst 8550338 # number of overall MSHR misses 1809system.cpu1.icache.overall_mshr_misses::total 8550338 # number of overall MSHR misses 1810system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 90 # number of ReadReq MSHR uncacheable 1811system.cpu1.icache.ReadReq_mshr_uncacheable::total 90 # number of ReadReq MSHR uncacheable 1812system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 90 # number of overall MSHR uncacheable misses 1813system.cpu1.icache.overall_mshr_uncacheable_misses::total 90 # number of overall MSHR uncacheable misses 1814system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 75495426368 # number of ReadReq MSHR miss cycles 1815system.cpu1.icache.ReadReq_mshr_miss_latency::total 75495426368 # number of ReadReq MSHR miss cycles 1816system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 75495426368 # number of demand (read+write) MSHR miss cycles 1817system.cpu1.icache.demand_mshr_miss_latency::total 75495426368 # number of demand (read+write) MSHR miss cycles 1818system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 75495426368 # number of overall MSHR miss cycles 1819system.cpu1.icache.overall_mshr_miss_latency::total 75495426368 # number of overall MSHR miss cycles 1820system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8549000 # number of ReadReq MSHR uncacheable cycles 1821system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8549000 # number of ReadReq MSHR uncacheable cycles 1822system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8549000 # number of overall MSHR uncacheable cycles 1823system.cpu1.icache.overall_mshr_uncacheable_latency::total 8549000 # number of overall MSHR uncacheable cycles 1824system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.038778 # mshr miss rate for ReadReq accesses 1825system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.038778 # mshr miss rate for ReadReq accesses 1826system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.038778 # mshr miss rate for demand accesses 1827system.cpu1.icache.demand_mshr_miss_rate::total 0.038778 # mshr miss rate for demand accesses 1828system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.038778 # mshr miss rate for overall accesses 1829system.cpu1.icache.overall_mshr_miss_rate::total 0.038778 # mshr miss rate for overall accesses 1830system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8829.525379 # average ReadReq mshr miss latency 1831system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8829.525379 # average ReadReq mshr miss latency 1832system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8829.525379 # average overall mshr miss latency 1833system.cpu1.icache.demand_avg_mshr_miss_latency::total 8829.525379 # average overall mshr miss latency 1834system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8829.525379 # average overall mshr miss latency 1835system.cpu1.icache.overall_avg_mshr_miss_latency::total 8829.525379 # average overall mshr miss latency 1836system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 94988.888889 # average ReadReq mshr uncacheable latency 1837system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 94988.888889 # average ReadReq mshr uncacheable latency 1838system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 94988.888889 # average overall mshr uncacheable latency 1839system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 94988.888889 # average overall mshr uncacheable latency |
| 1816system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 1840system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1817system.cpu1.l2cache.prefetcher.num_hwpf_issued 7632700 # number of hwpf issued 1818system.cpu1.l2cache.prefetcher.pfIdentified 7634373 # number of prefetch candidates identified 1819system.cpu1.l2cache.prefetcher.pfBufferHit 1426 # number of redundant prefetches already in prefetch queue | 1841system.cpu1.l2cache.prefetcher.num_hwpf_issued 6602862 # number of hwpf issued 1842system.cpu1.l2cache.prefetcher.pfIdentified 6604361 # number of prefetch candidates identified 1843system.cpu1.l2cache.prefetcher.pfBufferHit 1239 # number of redundant prefetches already in prefetch queue |
| 1820system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1821system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 1844system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1845system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 1822system.cpu1.l2cache.prefetcher.pfSpanPage 974619 # number of prefetches not generated due to page crossing 1823system.cpu1.l2cache.tags.replacements 2493350 # number of replacements 1824system.cpu1.l2cache.tags.tagsinuse 13598.009718 # Cycle average of tags in use 1825system.cpu1.l2cache.tags.total_refs 15504995 # Total number of references to valid blocks. 1826system.cpu1.l2cache.tags.sampled_refs 2509448 # Sample count of references to valid blocks. 1827system.cpu1.l2cache.tags.avg_refs 6.178648 # Average number of references to valid blocks. 1828system.cpu1.l2cache.tags.warmup_cycle 9806309185500 # Cycle when the warmup percentage was hit. 1829system.cpu1.l2cache.tags.occ_blocks::writebacks 5002.427380 # Average occupied blocks per requestor 1830system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 85.119837 # Average occupied blocks per requestor 1831system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 87.520686 # Average occupied blocks per requestor 1832system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4382.194744 # Average occupied blocks per requestor 1833system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3239.455000 # Average occupied blocks per requestor 1834system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 801.292071 # Average occupied blocks per requestor 1835system.cpu1.l2cache.tags.occ_percent::writebacks 0.305324 # Average percentage of cache occupancy 1836system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.005195 # Average percentage of cache occupancy 1837system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005342 # Average percentage of cache occupancy 1838system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.267468 # Average percentage of cache occupancy 1839system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.197721 # Average percentage of cache occupancy 1840system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048907 # Average percentage of cache occupancy 1841system.cpu1.l2cache.tags.occ_percent::total 0.829957 # Average percentage of cache occupancy 1842system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1340 # Occupied blocks per task id 1843system.cpu1.l2cache.tags.occ_task_id_blocks::1023 68 # Occupied blocks per task id 1844system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14690 # Occupied blocks per task id 1845system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 24 # Occupied blocks per task id 1846system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 317 # Occupied blocks per task id 1847system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 958 # Occupied blocks per task id 1848system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 41 # Occupied blocks per task id 1849system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 38 # Occupied blocks per task id 1850system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 27 # Occupied blocks per task id 1851system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 1852system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 1853system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1230 # Occupied blocks per task id 1854system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4980 # Occupied blocks per task id 1855system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7916 # Occupied blocks per task id 1856system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 444 # Occupied blocks per task id 1857system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.081787 # Percentage of cache occupancy per task id 1858system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004150 # Percentage of cache occupancy per task id 1859system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.896606 # Percentage of cache occupancy per task id 1860system.cpu1.l2cache.tags.tag_accesses 320697996 # Number of tag accesses 1861system.cpu1.l2cache.tags.data_accesses 320697996 # Number of data accesses 1862system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 533308 # number of ReadReq hits 1863system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 157578 # number of ReadReq hits 1864system.cpu1.l2cache.ReadReq_hits::cpu1.inst 8712936 # number of ReadReq hits 1865system.cpu1.l2cache.ReadReq_hits::cpu1.data 2963890 # number of ReadReq hits 1866system.cpu1.l2cache.ReadReq_hits::total 12367712 # number of ReadReq hits 1867system.cpu1.l2cache.Writeback_hits::writebacks 3514312 # number of Writeback hits 1868system.cpu1.l2cache.Writeback_hits::total 3514312 # number of Writeback hits 1869system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 195589 # number of WriteInvalidateReq hits 1870system.cpu1.l2cache.WriteInvalidateReq_hits::total 195589 # number of WriteInvalidateReq hits 1871system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 70594 # number of UpgradeReq hits 1872system.cpu1.l2cache.UpgradeReq_hits::total 70594 # number of UpgradeReq hits 1873system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 40360 # number of SCUpgradeReq hits 1874system.cpu1.l2cache.SCUpgradeReq_hits::total 40360 # number of SCUpgradeReq hits 1875system.cpu1.l2cache.ReadExReq_hits::cpu1.data 897925 # number of ReadExReq hits 1876system.cpu1.l2cache.ReadExReq_hits::total 897925 # number of ReadExReq hits 1877system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 533308 # number of demand (read+write) hits 1878system.cpu1.l2cache.demand_hits::cpu1.itb.walker 157578 # number of demand (read+write) hits 1879system.cpu1.l2cache.demand_hits::cpu1.inst 8712936 # number of demand (read+write) hits 1880system.cpu1.l2cache.demand_hits::cpu1.data 3861815 # number of demand (read+write) hits 1881system.cpu1.l2cache.demand_hits::total 13265637 # number of demand (read+write) hits 1882system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 533308 # number of overall hits 1883system.cpu1.l2cache.overall_hits::cpu1.itb.walker 157578 # number of overall hits 1884system.cpu1.l2cache.overall_hits::cpu1.inst 8712936 # number of overall hits 1885system.cpu1.l2cache.overall_hits::cpu1.data 3861815 # number of overall hits 1886system.cpu1.l2cache.overall_hits::total 13265637 # number of overall hits 1887system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12573 # number of ReadReq misses 1888system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8955 # number of ReadReq misses 1889system.cpu1.l2cache.ReadReq_misses::cpu1.inst 819069 # number of ReadReq misses 1890system.cpu1.l2cache.ReadReq_misses::cpu1.data 1025149 # number of ReadReq misses 1891system.cpu1.l2cache.ReadReq_misses::total 1865746 # number of ReadReq misses 1892system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 260149 # number of WriteInvalidateReq misses 1893system.cpu1.l2cache.WriteInvalidateReq_misses::total 260149 # number of WriteInvalidateReq misses 1894system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 141488 # number of UpgradeReq misses 1895system.cpu1.l2cache.UpgradeReq_misses::total 141488 # number of UpgradeReq misses 1896system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 155591 # number of SCUpgradeReq misses 1897system.cpu1.l2cache.SCUpgradeReq_misses::total 155591 # number of SCUpgradeReq misses 1898system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 8 # number of SCUpgradeFailReq misses 1899system.cpu1.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses 1900system.cpu1.l2cache.ReadExReq_misses::cpu1.data 244809 # number of ReadExReq misses 1901system.cpu1.l2cache.ReadExReq_misses::total 244809 # number of ReadExReq misses 1902system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12573 # number of demand (read+write) misses 1903system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8955 # number of demand (read+write) misses 1904system.cpu1.l2cache.demand_misses::cpu1.inst 819069 # number of demand (read+write) misses 1905system.cpu1.l2cache.demand_misses::cpu1.data 1269958 # number of demand (read+write) misses 1906system.cpu1.l2cache.demand_misses::total 2110555 # number of demand (read+write) misses 1907system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12573 # number of overall misses 1908system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8955 # number of overall misses 1909system.cpu1.l2cache.overall_misses::cpu1.inst 819069 # number of overall misses 1910system.cpu1.l2cache.overall_misses::cpu1.data 1269958 # number of overall misses 1911system.cpu1.l2cache.overall_misses::total 2110555 # number of overall misses 1912system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 462714995 # number of ReadReq miss cycles 1913system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 376910753 # number of ReadReq miss cycles 1914system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 23725938333 # number of ReadReq miss cycles 1915system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 33521266479 # number of ReadReq miss cycles 1916system.cpu1.l2cache.ReadReq_miss_latency::total 58086830560 # number of ReadReq miss cycles 1917system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 226799088 # number of WriteInvalidateReq miss cycles 1918system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 226799088 # number of WriteInvalidateReq miss cycles 1919system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3089566814 # number of UpgradeReq miss cycles 1920system.cpu1.l2cache.UpgradeReq_miss_latency::total 3089566814 # number of UpgradeReq miss cycles 1921system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3237262107 # number of SCUpgradeReq miss cycles 1922system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3237262107 # number of SCUpgradeReq miss cycles 1923system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2205498 # number of SCUpgradeFailReq miss cycles 1924system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2205498 # number of SCUpgradeFailReq miss cycles 1925system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10480888835 # number of ReadExReq miss cycles 1926system.cpu1.l2cache.ReadExReq_miss_latency::total 10480888835 # number of ReadExReq miss cycles 1927system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 462714995 # number of demand (read+write) miss cycles 1928system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 376910753 # number of demand (read+write) miss cycles 1929system.cpu1.l2cache.demand_miss_latency::cpu1.inst 23725938333 # number of demand (read+write) miss cycles 1930system.cpu1.l2cache.demand_miss_latency::cpu1.data 44002155314 # number of demand (read+write) miss cycles 1931system.cpu1.l2cache.demand_miss_latency::total 68567719395 # number of demand (read+write) miss cycles 1932system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 462714995 # number of overall miss cycles 1933system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 376910753 # number of overall miss cycles 1934system.cpu1.l2cache.overall_miss_latency::cpu1.inst 23725938333 # number of overall miss cycles 1935system.cpu1.l2cache.overall_miss_latency::cpu1.data 44002155314 # number of overall miss cycles 1936system.cpu1.l2cache.overall_miss_latency::total 68567719395 # number of overall miss cycles 1937system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 545881 # number of ReadReq accesses(hits+misses) 1938system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 166533 # number of ReadReq accesses(hits+misses) 1939system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 9532005 # number of ReadReq accesses(hits+misses) 1940system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3989039 # number of ReadReq accesses(hits+misses) 1941system.cpu1.l2cache.ReadReq_accesses::total 14233458 # number of ReadReq accesses(hits+misses) 1942system.cpu1.l2cache.Writeback_accesses::writebacks 3514312 # number of Writeback accesses(hits+misses) 1943system.cpu1.l2cache.Writeback_accesses::total 3514312 # number of Writeback accesses(hits+misses) 1944system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 455738 # number of WriteInvalidateReq accesses(hits+misses) 1945system.cpu1.l2cache.WriteInvalidateReq_accesses::total 455738 # number of WriteInvalidateReq accesses(hits+misses) 1946system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 212082 # number of UpgradeReq accesses(hits+misses) 1947system.cpu1.l2cache.UpgradeReq_accesses::total 212082 # number of UpgradeReq accesses(hits+misses) 1948system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195951 # number of SCUpgradeReq accesses(hits+misses) 1949system.cpu1.l2cache.SCUpgradeReq_accesses::total 195951 # number of SCUpgradeReq accesses(hits+misses) 1950system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 8 # number of SCUpgradeFailReq accesses(hits+misses) 1951system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) 1952system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1142734 # number of ReadExReq accesses(hits+misses) 1953system.cpu1.l2cache.ReadExReq_accesses::total 1142734 # number of ReadExReq accesses(hits+misses) 1954system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 545881 # number of demand (read+write) accesses 1955system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 166533 # number of demand (read+write) accesses 1956system.cpu1.l2cache.demand_accesses::cpu1.inst 9532005 # number of demand (read+write) accesses 1957system.cpu1.l2cache.demand_accesses::cpu1.data 5131773 # number of demand (read+write) accesses 1958system.cpu1.l2cache.demand_accesses::total 15376192 # number of demand (read+write) accesses 1959system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 545881 # number of overall (read+write) accesses 1960system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 166533 # number of overall (read+write) accesses 1961system.cpu1.l2cache.overall_accesses::cpu1.inst 9532005 # number of overall (read+write) accesses 1962system.cpu1.l2cache.overall_accesses::cpu1.data 5131773 # number of overall (read+write) accesses 1963system.cpu1.l2cache.overall_accesses::total 15376192 # number of overall (read+write) accesses 1964system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023032 # miss rate for ReadReq accesses 1965system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.053773 # miss rate for ReadReq accesses 1966system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.085928 # miss rate for ReadReq accesses 1967system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.256991 # miss rate for ReadReq accesses 1968system.cpu1.l2cache.ReadReq_miss_rate::total 0.131082 # miss rate for ReadReq accesses 1969system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.570830 # miss rate for WriteInvalidateReq accesses 1970system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.570830 # miss rate for WriteInvalidateReq accesses 1971system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.667138 # miss rate for UpgradeReq accesses 1972system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.667138 # miss rate for UpgradeReq accesses 1973system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.794030 # miss rate for SCUpgradeReq accesses 1974system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.794030 # miss rate for SCUpgradeReq accesses | 1846system.cpu1.l2cache.prefetcher.pfSpanPage 840391 # number of prefetches not generated due to page crossing 1847system.cpu1.l2cache.tags.replacements 2149670 # number of replacements 1848system.cpu1.l2cache.tags.tagsinuse 13538.161783 # Cycle average of tags in use 1849system.cpu1.l2cache.tags.total_refs 13667574 # Total number of references to valid blocks. 1850system.cpu1.l2cache.tags.sampled_refs 2165890 # Sample count of references to valid blocks. 1851system.cpu1.l2cache.tags.avg_refs 6.310373 # Average number of references to valid blocks. 1852system.cpu1.l2cache.tags.warmup_cycle 9806309103500 # Cycle when the warmup percentage was hit. 1853system.cpu1.l2cache.tags.occ_blocks::writebacks 5443.099185 # Average occupied blocks per requestor 1854system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 82.941597 # Average occupied blocks per requestor 1855system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 88.885416 # Average occupied blocks per requestor 1856system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3832.023077 # Average occupied blocks per requestor 1857system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3147.321084 # Average occupied blocks per requestor 1858system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 943.891423 # Average occupied blocks per requestor 1859system.cpu1.l2cache.tags.occ_percent::writebacks 0.332220 # Average percentage of cache occupancy 1860system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.005062 # Average percentage of cache occupancy 1861system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005425 # Average percentage of cache occupancy 1862system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.233888 # Average percentage of cache occupancy 1863system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.192097 # Average percentage of cache occupancy 1864system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.057611 # Average percentage of cache occupancy 1865system.cpu1.l2cache.tags.occ_percent::total 0.826304 # Average percentage of cache occupancy 1866system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1444 # Occupied blocks per task id 1867system.cpu1.l2cache.tags.occ_task_id_blocks::1023 51 # Occupied blocks per task id 1868system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14725 # Occupied blocks per task id 1869system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 21 # Occupied blocks per task id 1870system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 436 # Occupied blocks per task id 1871system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 846 # Occupied blocks per task id 1872system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 141 # Occupied blocks per task id 1873system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 1874system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 24 # Occupied blocks per task id 1875system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 24 # Occupied blocks per task id 1876system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 1877system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 1878system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1094 # Occupied blocks per task id 1879system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5482 # Occupied blocks per task id 1880system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7066 # Occupied blocks per task id 1881system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 978 # Occupied blocks per task id 1882system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.088135 # Percentage of cache occupancy per task id 1883system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003113 # Percentage of cache occupancy per task id 1884system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.898743 # Percentage of cache occupancy per task id 1885system.cpu1.l2cache.tags.tag_accesses 283341479 # Number of tag accesses 1886system.cpu1.l2cache.tags.data_accesses 283341479 # Number of data accesses 1887system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 455761 # number of ReadReq hits 1888system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 138301 # number of ReadReq hits 1889system.cpu1.l2cache.ReadReq_hits::cpu1.inst 7823529 # number of ReadReq hits 1890system.cpu1.l2cache.ReadReq_hits::cpu1.data 2545685 # number of ReadReq hits 1891system.cpu1.l2cache.ReadReq_hits::total 10963276 # number of ReadReq hits 1892system.cpu1.l2cache.Writeback_hits::writebacks 3038484 # number of Writeback hits 1893system.cpu1.l2cache.Writeback_hits::total 3038484 # number of Writeback hits 1894system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 176317 # number of WriteInvalidateReq hits 1895system.cpu1.l2cache.WriteInvalidateReq_hits::total 176317 # number of WriteInvalidateReq hits 1896system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 59890 # number of UpgradeReq hits 1897system.cpu1.l2cache.UpgradeReq_hits::total 59890 # number of UpgradeReq hits 1898system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 34545 # number of SCUpgradeReq hits 1899system.cpu1.l2cache.SCUpgradeReq_hits::total 34545 # number of SCUpgradeReq hits 1900system.cpu1.l2cache.ReadExReq_hits::cpu1.data 755491 # number of ReadExReq hits 1901system.cpu1.l2cache.ReadExReq_hits::total 755491 # number of ReadExReq hits 1902system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 455761 # number of demand (read+write) hits 1903system.cpu1.l2cache.demand_hits::cpu1.itb.walker 138301 # number of demand (read+write) hits 1904system.cpu1.l2cache.demand_hits::cpu1.inst 7823529 # number of demand (read+write) hits 1905system.cpu1.l2cache.demand_hits::cpu1.data 3301176 # number of demand (read+write) hits 1906system.cpu1.l2cache.demand_hits::total 11718767 # number of demand (read+write) hits 1907system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 455761 # number of overall hits 1908system.cpu1.l2cache.overall_hits::cpu1.itb.walker 138301 # number of overall hits 1909system.cpu1.l2cache.overall_hits::cpu1.inst 7823529 # number of overall hits 1910system.cpu1.l2cache.overall_hits::cpu1.data 3301176 # number of overall hits 1911system.cpu1.l2cache.overall_hits::total 11718767 # number of overall hits 1912system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11008 # number of ReadReq misses 1913system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7757 # number of ReadReq misses 1914system.cpu1.l2cache.ReadReq_misses::cpu1.inst 726809 # number of ReadReq misses 1915system.cpu1.l2cache.ReadReq_misses::cpu1.data 914890 # number of ReadReq misses 1916system.cpu1.l2cache.ReadReq_misses::total 1660464 # number of ReadReq misses 1917system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 241215 # number of WriteInvalidateReq misses 1918system.cpu1.l2cache.WriteInvalidateReq_misses::total 241215 # number of WriteInvalidateReq misses 1919system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 139061 # number of UpgradeReq misses 1920system.cpu1.l2cache.UpgradeReq_misses::total 139061 # number of UpgradeReq misses 1921system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 153238 # number of SCUpgradeReq misses 1922system.cpu1.l2cache.SCUpgradeReq_misses::total 153238 # number of SCUpgradeReq misses 1923system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses 1924system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 1925system.cpu1.l2cache.ReadExReq_misses::cpu1.data 230973 # number of ReadExReq misses 1926system.cpu1.l2cache.ReadExReq_misses::total 230973 # number of ReadExReq misses 1927system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11008 # number of demand (read+write) misses 1928system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7757 # number of demand (read+write) misses 1929system.cpu1.l2cache.demand_misses::cpu1.inst 726809 # number of demand (read+write) misses 1930system.cpu1.l2cache.demand_misses::cpu1.data 1145863 # number of demand (read+write) misses 1931system.cpu1.l2cache.demand_misses::total 1891437 # number of demand (read+write) misses 1932system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11008 # number of overall misses 1933system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7757 # number of overall misses 1934system.cpu1.l2cache.overall_misses::cpu1.inst 726809 # number of overall misses 1935system.cpu1.l2cache.overall_misses::cpu1.data 1145863 # number of overall misses 1936system.cpu1.l2cache.overall_misses::total 1891437 # number of overall misses 1937system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 327528752 # number of ReadReq miss cycles 1938system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 257164513 # number of ReadReq miss cycles 1939system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 20327901458 # number of ReadReq miss cycles 1940system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 26467087148 # number of ReadReq miss cycles 1941system.cpu1.l2cache.ReadReq_miss_latency::total 47379681871 # number of ReadReq miss cycles 1942system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 239660388 # number of WriteInvalidateReq miss cycles 1943system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 239660388 # number of WriteInvalidateReq miss cycles 1944system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3007716761 # number of UpgradeReq miss cycles 1945system.cpu1.l2cache.UpgradeReq_miss_latency::total 3007716761 # number of UpgradeReq miss cycles 1946system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3151750139 # number of SCUpgradeReq miss cycles 1947system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3151750139 # number of SCUpgradeReq miss cycles 1948system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2513499 # number of SCUpgradeFailReq miss cycles 1949system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2513499 # number of SCUpgradeFailReq miss cycles 1950system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 8819162910 # number of ReadExReq miss cycles 1951system.cpu1.l2cache.ReadExReq_miss_latency::total 8819162910 # number of ReadExReq miss cycles 1952system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 327528752 # number of demand (read+write) miss cycles 1953system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 257164513 # number of demand (read+write) miss cycles 1954system.cpu1.l2cache.demand_miss_latency::cpu1.inst 20327901458 # number of demand (read+write) miss cycles 1955system.cpu1.l2cache.demand_miss_latency::cpu1.data 35286250058 # number of demand (read+write) miss cycles 1956system.cpu1.l2cache.demand_miss_latency::total 56198844781 # number of demand (read+write) miss cycles 1957system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 327528752 # number of overall miss cycles 1958system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 257164513 # number of overall miss cycles 1959system.cpu1.l2cache.overall_miss_latency::cpu1.inst 20327901458 # number of overall miss cycles 1960system.cpu1.l2cache.overall_miss_latency::cpu1.data 35286250058 # number of overall miss cycles 1961system.cpu1.l2cache.overall_miss_latency::total 56198844781 # number of overall miss cycles 1962system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 466769 # number of ReadReq accesses(hits+misses) 1963system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 146058 # number of ReadReq accesses(hits+misses) 1964system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 8550338 # number of ReadReq accesses(hits+misses) 1965system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3460575 # number of ReadReq accesses(hits+misses) 1966system.cpu1.l2cache.ReadReq_accesses::total 12623740 # number of ReadReq accesses(hits+misses) 1967system.cpu1.l2cache.Writeback_accesses::writebacks 3038484 # number of Writeback accesses(hits+misses) 1968system.cpu1.l2cache.Writeback_accesses::total 3038484 # number of Writeback accesses(hits+misses) 1969system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 417532 # number of WriteInvalidateReq accesses(hits+misses) 1970system.cpu1.l2cache.WriteInvalidateReq_accesses::total 417532 # number of WriteInvalidateReq accesses(hits+misses) 1971system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 198951 # number of UpgradeReq accesses(hits+misses) 1972system.cpu1.l2cache.UpgradeReq_accesses::total 198951 # number of UpgradeReq accesses(hits+misses) 1973system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 187783 # number of SCUpgradeReq accesses(hits+misses) 1974system.cpu1.l2cache.SCUpgradeReq_accesses::total 187783 # number of SCUpgradeReq accesses(hits+misses) 1975system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 1976system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 1977system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 986464 # number of ReadExReq accesses(hits+misses) 1978system.cpu1.l2cache.ReadExReq_accesses::total 986464 # number of ReadExReq accesses(hits+misses) 1979system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 466769 # number of demand (read+write) accesses 1980system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 146058 # number of demand (read+write) accesses 1981system.cpu1.l2cache.demand_accesses::cpu1.inst 8550338 # number of demand (read+write) accesses 1982system.cpu1.l2cache.demand_accesses::cpu1.data 4447039 # number of demand (read+write) accesses 1983system.cpu1.l2cache.demand_accesses::total 13610204 # number of demand (read+write) accesses 1984system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 466769 # number of overall (read+write) accesses 1985system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 146058 # number of overall (read+write) accesses 1986system.cpu1.l2cache.overall_accesses::cpu1.inst 8550338 # number of overall (read+write) accesses 1987system.cpu1.l2cache.overall_accesses::cpu1.data 4447039 # number of overall (read+write) accesses 1988system.cpu1.l2cache.overall_accesses::total 13610204 # number of overall (read+write) accesses 1989system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023583 # miss rate for ReadReq accesses 1990system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.053109 # miss rate for ReadReq accesses 1991system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.085004 # miss rate for ReadReq accesses 1992system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.264375 # miss rate for ReadReq accesses 1993system.cpu1.l2cache.ReadReq_miss_rate::total 0.131535 # miss rate for ReadReq accesses 1994system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.577716 # miss rate for WriteInvalidateReq accesses 1995system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.577716 # miss rate for WriteInvalidateReq accesses 1996system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.698971 # miss rate for UpgradeReq accesses 1997system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.698971 # miss rate for UpgradeReq accesses 1998system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.816038 # miss rate for SCUpgradeReq accesses 1999system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.816038 # miss rate for SCUpgradeReq accesses |
| 1975system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 1976system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses | 2000system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2001system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses |
| 1977system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.214231 # miss rate for ReadExReq accesses 1978system.cpu1.l2cache.ReadExReq_miss_rate::total 0.214231 # miss rate for ReadExReq accesses 1979system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023032 # miss rate for demand accesses 1980system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.053773 # miss rate for demand accesses 1981system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.085928 # miss rate for demand accesses 1982system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.247470 # miss rate for demand accesses 1983system.cpu1.l2cache.demand_miss_rate::total 0.137261 # miss rate for demand accesses 1984system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023032 # miss rate for overall accesses 1985system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.053773 # miss rate for overall accesses 1986system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.085928 # miss rate for overall accesses 1987system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.247470 # miss rate for overall accesses 1988system.cpu1.l2cache.overall_miss_rate::total 0.137261 # miss rate for overall accesses 1989system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 36802.274318 # average ReadReq miss latency 1990system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 42089.419654 # average ReadReq miss latency 1991system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 28966.959234 # average ReadReq miss latency 1992system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32698.921307 # average ReadReq miss latency 1993system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31133.300331 # average ReadReq miss latency 1994system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 871.804574 # average WriteInvalidateReq miss latency 1995system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 871.804574 # average WriteInvalidateReq miss latency 1996system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21836.246282 # average UpgradeReq miss latency 1997system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21836.246282 # average UpgradeReq miss latency 1998system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20806.229840 # average SCUpgradeReq miss latency 1999system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20806.229840 # average SCUpgradeReq miss latency 2000system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 275687.250000 # average SCUpgradeFailReq miss latency 2001system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 275687.250000 # average SCUpgradeFailReq miss latency 2002system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42812.514389 # average ReadExReq miss latency 2003system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42812.514389 # average ReadExReq miss latency 2004system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 36802.274318 # average overall miss latency 2005system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 42089.419654 # average overall miss latency 2006system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28966.959234 # average overall miss latency 2007system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34648.512245 # average overall miss latency 2008system.cpu1.l2cache.demand_avg_miss_latency::total 32488.004053 # average overall miss latency 2009system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 36802.274318 # average overall miss latency 2010system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 42089.419654 # average overall miss latency 2011system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28966.959234 # average overall miss latency 2012system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34648.512245 # average overall miss latency 2013system.cpu1.l2cache.overall_avg_miss_latency::total 32488.004053 # average overall miss latency | 2002system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.234142 # miss rate for ReadExReq accesses 2003system.cpu1.l2cache.ReadExReq_miss_rate::total 0.234142 # miss rate for ReadExReq accesses 2004system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023583 # miss rate for demand accesses 2005system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.053109 # miss rate for demand accesses 2006system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.085004 # miss rate for demand accesses 2007system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.257669 # miss rate for demand accesses 2008system.cpu1.l2cache.demand_miss_rate::total 0.138972 # miss rate for demand accesses 2009system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023583 # miss rate for overall accesses 2010system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.053109 # miss rate for overall accesses 2011system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.085004 # miss rate for overall accesses 2012system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.257669 # miss rate for overall accesses 2013system.cpu1.l2cache.overall_miss_rate::total 0.138972 # miss rate for overall accesses 2014system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 29753.702035 # average ReadReq miss latency 2015system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 33152.573546 # average ReadReq miss latency 2016system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 27968.698046 # average ReadReq miss latency 2017system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 28929.256138 # average ReadReq miss latency 2018system.cpu1.l2cache.ReadReq_avg_miss_latency::total 28534.001262 # average ReadReq miss latency 2019system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 993.555077 # average WriteInvalidateReq miss latency 2020system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 993.555077 # average WriteInvalidateReq miss latency 2021system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21628.758322 # average UpgradeReq miss latency 2022system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21628.758322 # average UpgradeReq miss latency 2023system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20567.679942 # average SCUpgradeReq miss latency 2024system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20567.679942 # average SCUpgradeReq miss latency 2025system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 837833 # average SCUpgradeFailReq miss latency 2026system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 837833 # average SCUpgradeFailReq miss latency 2027system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38182.657324 # average ReadExReq miss latency 2028system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38182.657324 # average ReadExReq miss latency 2029system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 29753.702035 # average overall miss latency 2030system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 33152.573546 # average overall miss latency 2031system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 27968.698046 # average overall miss latency 2032system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30794.475481 # average overall miss latency 2033system.cpu1.l2cache.demand_avg_miss_latency::total 29712.247768 # average overall miss latency 2034system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 29753.702035 # average overall miss latency 2035system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 33152.573546 # average overall miss latency 2036system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 27968.698046 # average overall miss latency 2037system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30794.475481 # average overall miss latency 2038system.cpu1.l2cache.overall_avg_miss_latency::total 29712.247768 # average overall miss latency |
| 2014system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2015system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2016system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2017system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2018system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2019system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2020system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2021system.cpu1.l2cache.cache_copies 0 # number of cache copies performed | 2039system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2040system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2041system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2042system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2043system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2044system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2045system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2046system.cpu1.l2cache.cache_copies 0 # number of cache copies performed |
| 2022system.cpu1.l2cache.writebacks::writebacks 1040490 # number of writebacks 2023system.cpu1.l2cache.writebacks::total 1040490 # number of writebacks 2024system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits | 2047system.cpu1.l2cache.writebacks::writebacks 875308 # number of writebacks 2048system.cpu1.l2cache.writebacks::total 875308 # number of writebacks |
| 2025system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits | 2049system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits |
| 2026system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits 2027system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 845 # number of ReadReq MSHR hits 2028system.cpu1.l2cache.ReadReq_mshr_hits::total 849 # number of ReadReq MSHR hits 2029system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 8 # number of WriteInvalidateReq MSHR hits 2030system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 8 # number of WriteInvalidateReq MSHR hits 2031system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 7280 # number of ReadExReq MSHR hits 2032system.cpu1.l2cache.ReadExReq_mshr_hits::total 7280 # number of ReadExReq MSHR hits 2033system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits | 2050system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits 2051system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 523 # number of ReadReq MSHR hits 2052system.cpu1.l2cache.ReadReq_mshr_hits::total 527 # number of ReadReq MSHR hits 2053system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 9 # number of WriteInvalidateReq MSHR hits 2054system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 9 # number of WriteInvalidateReq MSHR hits 2055system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 3864 # number of ReadExReq MSHR hits 2056system.cpu1.l2cache.ReadExReq_mshr_hits::total 3864 # number of ReadExReq MSHR hits |
| 2034system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits | 2057system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits |
| 2035system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits 2036system.cpu1.l2cache.demand_mshr_hits::cpu1.data 8125 # number of demand (read+write) MSHR hits 2037system.cpu1.l2cache.demand_mshr_hits::total 8129 # number of demand (read+write) MSHR hits 2038system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits | 2058system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits 2059system.cpu1.l2cache.demand_mshr_hits::cpu1.data 4387 # number of demand (read+write) MSHR hits 2060system.cpu1.l2cache.demand_mshr_hits::total 4391 # number of demand (read+write) MSHR hits |
| 2039system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits | 2061system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits |
| 2040system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits 2041system.cpu1.l2cache.overall_mshr_hits::cpu1.data 8125 # number of overall MSHR hits 2042system.cpu1.l2cache.overall_mshr_hits::total 8129 # number of overall MSHR hits 2043system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12572 # number of ReadReq MSHR misses 2044system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8954 # number of ReadReq MSHR misses 2045system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 819067 # number of ReadReq MSHR misses 2046system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 1024304 # number of ReadReq MSHR misses 2047system.cpu1.l2cache.ReadReq_mshr_misses::total 1864897 # number of ReadReq MSHR misses 2048system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 717839 # number of HardPFReq MSHR misses 2049system.cpu1.l2cache.HardPFReq_mshr_misses::total 717839 # number of HardPFReq MSHR misses 2050system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 260141 # number of WriteInvalidateReq MSHR misses 2051system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 260141 # number of WriteInvalidateReq MSHR misses 2052system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 141488 # number of UpgradeReq MSHR misses 2053system.cpu1.l2cache.UpgradeReq_mshr_misses::total 141488 # number of UpgradeReq MSHR misses 2054system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 155591 # number of SCUpgradeReq MSHR misses 2055system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 155591 # number of SCUpgradeReq MSHR misses 2056system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 8 # number of SCUpgradeFailReq MSHR misses 2057system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses 2058system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 237529 # number of ReadExReq MSHR misses 2059system.cpu1.l2cache.ReadExReq_mshr_misses::total 237529 # number of ReadExReq MSHR misses 2060system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12572 # number of demand (read+write) MSHR misses 2061system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8954 # number of demand (read+write) MSHR misses 2062system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 819067 # number of demand (read+write) MSHR misses 2063system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1261833 # number of demand (read+write) MSHR misses 2064system.cpu1.l2cache.demand_mshr_misses::total 2102426 # number of demand (read+write) MSHR misses 2065system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12572 # number of overall MSHR misses 2066system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8954 # number of overall MSHR misses 2067system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 819067 # number of overall MSHR misses 2068system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1261833 # number of overall MSHR misses 2069system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 717839 # number of overall MSHR misses 2070system.cpu1.l2cache.overall_mshr_misses::total 2820265 # number of overall MSHR misses 2071system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 380310007 # number of ReadReq MSHR miss cycles 2072system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 318025257 # number of ReadReq MSHR miss cycles 2073system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 18380027667 # number of ReadReq MSHR miss cycles 2074system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 26750668121 # number of ReadReq MSHR miss cycles 2075system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 45829031052 # number of ReadReq MSHR miss cycles 2076system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 32395588345 # number of HardPFReq MSHR miss cycles 2077system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 32395588345 # number of HardPFReq MSHR miss cycles 2078system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 8350999174 # number of WriteInvalidateReq MSHR miss cycles 2079system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 8350999174 # number of WriteInvalidateReq MSHR miss cycles 2080system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2765649497 # number of UpgradeReq MSHR miss cycles 2081system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2765649497 # number of UpgradeReq MSHR miss cycles 2082system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2300876668 # number of SCUpgradeReq MSHR miss cycles 2083system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2300876668 # number of SCUpgradeReq MSHR miss cycles 2084system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1886998 # number of SCUpgradeFailReq MSHR miss cycles 2085system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1886998 # number of SCUpgradeFailReq MSHR miss cycles 2086system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7923837459 # number of ReadExReq MSHR miss cycles 2087system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7923837459 # number of ReadExReq MSHR miss cycles 2088system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 380310007 # number of demand (read+write) MSHR miss cycles 2089system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 318025257 # number of demand (read+write) MSHR miss cycles 2090system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 18380027667 # number of demand (read+write) MSHR miss cycles 2091system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 34674505580 # number of demand (read+write) MSHR miss cycles 2092system.cpu1.l2cache.demand_mshr_miss_latency::total 53752868511 # number of demand (read+write) MSHR miss cycles 2093system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 380310007 # number of overall MSHR miss cycles 2094system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 318025257 # number of overall MSHR miss cycles 2095system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 18380027667 # number of overall MSHR miss cycles 2096system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 34674505580 # number of overall MSHR miss cycles 2097system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 32395588345 # number of overall MSHR miss cycles 2098system.cpu1.l2cache.overall_mshr_miss_latency::total 86148456856 # number of overall MSHR miss cycles 2099system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7360000 # number of ReadReq MSHR uncacheable cycles 2100system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 476808000 # number of ReadReq MSHR uncacheable cycles 2101system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 484168000 # number of ReadReq MSHR uncacheable cycles 2102system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 548574002 # number of WriteReq MSHR uncacheable cycles 2103system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 548574002 # number of WriteReq MSHR uncacheable cycles 2104system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7360000 # number of overall MSHR uncacheable cycles 2105system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1025382002 # number of overall MSHR uncacheable cycles 2106system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1032742002 # 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number of WriteReq MSHR uncacheable 2098system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 90 # number of overall MSHR uncacheable misses 2099system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10170 # number of overall MSHR uncacheable misses 2100system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10260 # number of overall MSHR uncacheable misses 2101system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 255658756 # number of ReadReq MSHR miss cycles 2102system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 206438003 # number of ReadReq MSHR miss cycles 2103system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 15587531792 # number of ReadReq MSHR miss cycles 2104system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 20464504451 # number of ReadReq MSHR miss cycles 2105system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 36514133002 # number of ReadReq MSHR miss cycles 2106system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 19899573281 # number of HardPFReq MSHR miss cycles 2107system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 19899573281 # number of HardPFReq MSHR miss cycles 2108system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 7445733077 # number of WriteInvalidateReq MSHR miss cycles 2109system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 7445733077 # number of WriteInvalidateReq MSHR miss cycles 2110system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2687293206 # number of UpgradeReq MSHR miss cycles 2111system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2687293206 # number of UpgradeReq MSHR miss cycles 2112system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2230899638 # number of SCUpgradeReq MSHR miss cycles 2113system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2230899638 # number of SCUpgradeReq MSHR miss cycles 2114system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2142999 # number of SCUpgradeFailReq MSHR miss cycles 2115system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2142999 # number of SCUpgradeFailReq MSHR miss cycles 2116system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 6831385140 # number of ReadExReq MSHR miss cycles 2117system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 6831385140 # number of ReadExReq MSHR miss cycles 2118system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 255658756 # number of demand (read+write) MSHR miss cycles 2119system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 206438003 # number of demand (read+write) MSHR miss cycles 2120system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 15587531792 # number of demand (read+write) MSHR miss cycles 2121system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 27295889591 # number of demand (read+write) MSHR miss cycles 2122system.cpu1.l2cache.demand_mshr_miss_latency::total 43345518142 # number of demand (read+write) MSHR miss cycles 2123system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 255658756 # number of overall MSHR miss cycles 2124system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 206438003 # number of overall MSHR miss cycles 2125system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 15587531792 # number of overall MSHR miss cycles 2126system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 27295889591 # number of overall MSHR miss cycles 2127system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 19899573281 # number of overall MSHR miss cycles 2128system.cpu1.l2cache.overall_mshr_miss_latency::total 63245091423 # number of overall MSHR miss cycles 2129system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7792000 # number of ReadReq MSHR uncacheable cycles 2130system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 477441500 # number of ReadReq MSHR uncacheable cycles 2131system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 485233500 # number of ReadReq MSHR uncacheable cycles 2132system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 545217001 # number of WriteReq MSHR uncacheable cycles 2133system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 545217001 # number of WriteReq MSHR uncacheable cycles 2134system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7792000 # number of overall MSHR uncacheable cycles 2135system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1022658501 # number of overall MSHR uncacheable cycles 2136system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1030450501 # number of overall MSHR uncacheable cycles 2137system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023583 # mshr miss rate for ReadReq accesses 2138system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.053102 # mshr miss rate for ReadReq accesses 2139system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.085003 # mshr miss rate for ReadReq accesses 2140system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.264224 # mshr miss rate for ReadReq accesses 2141system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.131493 # mshr miss rate for ReadReq accesses |
| 2112system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2113system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 2142system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2143system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 2114system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.570813 # mshr miss rate for WriteInvalidateReq accesses 2115system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.570813 # mshr miss rate for WriteInvalidateReq accesses 2116system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.667138 # mshr miss rate for UpgradeReq accesses 2117system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.667138 # mshr miss rate for UpgradeReq accesses 2118system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.794030 # mshr miss rate for SCUpgradeReq accesses 2119system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.794030 # mshr miss rate for SCUpgradeReq accesses | 2144system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.577695 # mshr miss rate for WriteInvalidateReq accesses 2145system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.577695 # mshr miss rate for WriteInvalidateReq accesses 2146system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.698971 # mshr miss rate for UpgradeReq accesses 2147system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.698971 # mshr miss rate for UpgradeReq accesses 2148system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.816038 # mshr miss rate for SCUpgradeReq accesses 2149system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.816038 # mshr miss rate for SCUpgradeReq accesses |
| 2120system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2121system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses | 2150system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2151system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses |
| 2122system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.207860 # mshr miss rate for ReadExReq accesses 2123system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.207860 # mshr miss rate for ReadExReq accesses 2124system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023031 # mshr miss rate for demand accesses 2125system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053767 # mshr miss rate for demand accesses 2126system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.085928 # mshr miss rate for demand accesses 2127system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245886 # mshr miss rate for demand accesses 2128system.cpu1.l2cache.demand_mshr_miss_rate::total 0.136733 # mshr miss rate for demand accesses 2129system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023031 # mshr miss rate for overall accesses 2130system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053767 # mshr miss rate for overall accesses 2131system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.085928 # mshr miss rate for overall accesses 2132system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245886 # mshr miss rate for overall accesses | 2152system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.230225 # mshr miss rate for ReadExReq accesses 2153system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.230225 # mshr miss rate for ReadExReq accesses 2154system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023583 # mshr miss rate for demand accesses 2155system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053102 # mshr miss rate for demand accesses 2156system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.085003 # mshr miss rate for demand accesses 2157system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.256682 # mshr miss rate for demand accesses 2158system.cpu1.l2cache.demand_mshr_miss_rate::total 0.138649 # mshr miss rate for demand accesses 2159system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023583 # mshr miss rate for overall accesses 2160system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053102 # mshr miss rate for overall accesses 2161system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.085003 # mshr miss rate for overall accesses 2162system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.256682 # mshr miss rate for overall accesses |
| 2133system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses | 2163system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 2134system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183418 # mshr miss rate for overall accesses 2135system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 30250.557350 # average ReadReq mshr miss latency 2136system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 35517.674447 # average ReadReq mshr miss latency 2137system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22440.200456 # average ReadReq mshr miss latency 2138system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26115.946165 # average ReadReq mshr miss latency 2139system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24574.564200 # average ReadReq mshr miss latency 2140system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45129.323351 # average HardPFReq mshr miss latency 2141system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45129.323351 # average HardPFReq mshr miss latency 2142system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32101.818529 # average WriteInvalidateReq mshr miss latency 2143system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32101.818529 # average WriteInvalidateReq mshr miss latency 2144system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19546.883813 # average UpgradeReq mshr miss latency 2145system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19546.883813 # average UpgradeReq mshr miss latency 2146system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14787.980462 # average SCUpgradeReq mshr miss latency 2147system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14787.980462 # average SCUpgradeReq mshr miss latency 2148system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 235874.750000 # average SCUpgradeFailReq mshr miss latency 2149system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 235874.750000 # average SCUpgradeFailReq mshr miss latency 2150system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33359.452778 # average ReadExReq mshr miss latency 2151system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33359.452778 # average ReadExReq mshr miss latency 2152system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 30250.557350 # average overall mshr miss latency 2153system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35517.674447 # average overall mshr miss latency 2154system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22440.200456 # average overall mshr miss latency 2155system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27479.472783 # average overall mshr miss latency 2156system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25567.068002 # average overall mshr miss latency 2157system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 30250.557350 # average overall mshr miss latency 2158system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35517.674447 # average overall mshr miss latency 2159system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22440.200456 # average overall mshr miss latency 2160system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27479.472783 # average overall mshr miss latency 2161system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45129.323351 # average overall mshr miss latency 2162system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30546.227697 # average overall mshr miss latency 2163system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2164system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2165system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2166system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 2167system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 2168system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 2169system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 2170system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 2164system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183983 # mshr miss rate for overall accesses 2165system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 23224.814317 # average ReadReq mshr miss latency 2166system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 26616.555312 # average ReadReq mshr miss latency 2167system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21446.619582 # average ReadReq mshr miss latency 2168system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 22381.061927 # average ReadReq mshr miss latency 2169system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 21997.300501 # average ReadReq mshr miss latency 2170system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 32251.883341 # average HardPFReq mshr miss latency 2171system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 32251.883341 # average HardPFReq mshr miss latency 2172system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30868.772240 # average WriteInvalidateReq mshr miss latency 2173system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 30868.772240 # average WriteInvalidateReq mshr miss latency 2174system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19324.564083 # average UpgradeReq mshr miss latency 2175system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19324.564083 # average UpgradeReq mshr miss latency 2176system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14558.396990 # average SCUpgradeReq mshr miss latency 2177system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14558.396990 # average SCUpgradeReq mshr miss latency 2178system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 714333 # average SCUpgradeFailReq mshr miss latency 2179system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 714333 # average SCUpgradeFailReq mshr miss latency 2180system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30079.764078 # average ReadExReq mshr miss latency 2181system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30079.764078 # average ReadExReq mshr miss latency 2182system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 23224.814317 # average overall mshr miss latency 2183system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26616.555312 # average overall mshr miss latency 2184system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21446.619582 # average overall mshr miss latency 2185system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23912.802013 # average overall mshr miss latency 2186system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22970.037902 # average overall mshr miss latency 2187system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 23224.814317 # average overall mshr miss latency 2188system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26616.555312 # average overall mshr miss latency 2189system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21446.619582 # average overall mshr miss latency 2190system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23912.802013 # average overall mshr miss latency 2191system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 32251.883341 # average overall mshr miss latency 2192system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25257.109948 # average overall mshr miss latency 2193system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86577.777778 # average ReadReq mshr uncacheable latency 2194system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 93929.077317 # average ReadReq mshr uncacheable latency 2195system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 93801.179200 # average ReadReq mshr uncacheable latency 2196system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 107178.494397 # average WriteReq mshr uncacheable latency 2197system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 107178.494397 # average WriteReq mshr uncacheable latency 2198system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86577.777778 # average overall mshr uncacheable latency 2199system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 100556.391445 # average overall mshr uncacheable latency 2200system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 100433.772027 # average overall mshr uncacheable latency |
| 2171system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 2201system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2172system.cpu1.toL2Bus.trans_dist::ReadReq 16743915 # Transaction distribution 2173system.cpu1.toL2Bus.trans_dist::ReadResp 14472665 # Transaction distribution 2174system.cpu1.toL2Bus.trans_dist::WriteReq 5158 # Transaction distribution 2175system.cpu1.toL2Bus.trans_dist::WriteResp 5158 # Transaction distribution 2176system.cpu1.toL2Bus.trans_dist::Writeback 3514312 # Transaction distribution 2177system.cpu1.toL2Bus.trans_dist::HardPFReq 1035959 # Transaction distribution 2178system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1137929 # Transaction distribution 2179system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 455738 # Transaction distribution 2180system.cpu1.toL2Bus.trans_dist::UpgradeReq 448749 # Transaction distribution 2181system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 344575 # Transaction distribution 2182system.cpu1.toL2Bus.trans_dist::UpgradeResp 466415 # Transaction distribution 2183system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 78 # Transaction distribution 2184system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 119 # Transaction distribution 2185system.cpu1.toL2Bus.trans_dist::ReadExReq 1299611 # Transaction distribution 2186system.cpu1.toL2Bus.trans_dist::ReadExResp 1147815 # Transaction distribution 2187system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 19064189 # Packet count per connected master and slave (bytes) 2188system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15671741 # Packet count per connected master and slave (bytes) 2189system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 370835 # Packet count per connected master and slave (bytes) 2190system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1205745 # Packet count per connected master and slave (bytes) 2191system.cpu1.toL2Bus.pkt_count::total 36312510 # Packet count per connected master and slave (bytes) 2192system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 610054016 # Cumulative packet size per connected master and slave (bytes) 2193system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 588145619 # Cumulative packet size per connected master and slave (bytes) 2194system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1332264 # Cumulative packet size per connected master and slave (bytes) 2195system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4367048 # Cumulative packet size per connected master and slave (bytes) 2196system.cpu1.toL2Bus.pkt_size::total 1203898947 # Cumulative packet size per connected master and slave (bytes) 2197system.cpu1.toL2Bus.snoops 4911557 # Total snoops (count) 2198system.cpu1.toL2Bus.snoop_fanout::samples 24519969 # Request fanout histogram 2199system.cpu1.toL2Bus.snoop_fanout::mean 3.188170 # Request fanout histogram 2200system.cpu1.toL2Bus.snoop_fanout::stdev 0.390848 # Request fanout histogram | 2202system.cpu1.toL2Bus.trans_dist::ReadReq 15242466 # Transaction distribution 2203system.cpu1.toL2Bus.trans_dist::ReadResp 12851003 # Transaction distribution 2204system.cpu1.toL2Bus.trans_dist::WriteReq 38250 # Transaction distribution 2205system.cpu1.toL2Bus.trans_dist::WriteResp 5087 # Transaction distribution 2206system.cpu1.toL2Bus.trans_dist::Writeback 3038484 # Transaction distribution 2207system.cpu1.toL2Bus.trans_dist::HardPFReq 900400 # Transaction distribution 2208system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1105427 # Transaction distribution 2209system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 417532 # Transaction distribution 2210system.cpu1.toL2Bus.trans_dist::UpgradeReq 439071 # Transaction distribution 2211system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337307 # Transaction distribution 2212system.cpu1.toL2Bus.trans_dist::UpgradeResp 446846 # Transaction distribution 2213system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 71 # Transaction distribution 2214system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution 2215system.cpu1.toL2Bus.trans_dist::ReadExReq 1140783 # Transaction distribution 2216system.cpu1.toL2Bus.trans_dist::ReadExResp 991898 # Transaction distribution 2217system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17100855 # Packet count per connected master and slave (bytes) 2218system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13710565 # Packet count per connected master and slave (bytes) 2219system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 326713 # Packet count per connected master and slave (bytes) 2220system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1037575 # Packet count per connected master and slave (bytes) 2221system.cpu1.toL2Bus.pkt_count::total 32175708 # Packet count per connected master and slave (bytes) 2222system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 547227328 # Cumulative packet size per connected master and slave (bytes) 2223system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 511521449 # Cumulative packet size per connected master and slave (bytes) 2224system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1168464 # Cumulative packet size per connected master and slave (bytes) 2225system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3734152 # Cumulative packet size per connected master and slave (bytes) 2226system.cpu1.toL2Bus.pkt_size::total 1063651393 # Cumulative packet size per connected master and slave (bytes) 2227system.cpu1.toL2Bus.snoops 4928167 # Total snoops (count) 2228system.cpu1.toL2Bus.snoop_fanout::samples 22242259 # Request fanout histogram 2229system.cpu1.toL2Bus.snoop_fanout::mean 1.242416 # Request fanout histogram 2230system.cpu1.toL2Bus.snoop_fanout::stdev 0.428544 # Request fanout histogram |
| 2201system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2202system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 2231system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2232system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 2203system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 2204system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 2205system.cpu1.toL2Bus.snoop_fanout::3 19906035 81.18% 81.18% # Request fanout histogram 2206system.cpu1.toL2Bus.snoop_fanout::4 4613934 18.82% 100.00% # Request fanout histogram | 2233system.cpu1.toL2Bus.snoop_fanout::1 16850390 75.76% 75.76% # Request fanout histogram 2234system.cpu1.toL2Bus.snoop_fanout::2 5391869 24.24% 100.00% # Request fanout histogram |
| 2207system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 2235system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 2208system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 2209system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 2210system.cpu1.toL2Bus.snoop_fanout::total 24519969 # Request fanout histogram 2211system.cpu1.toL2Bus.reqLayer0.occupancy 13930930666 # Layer occupancy (ticks) | 2236system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2237system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2238system.cpu1.toL2Bus.snoop_fanout::total 22242259 # Request fanout histogram 2239system.cpu1.toL2Bus.reqLayer0.occupancy 12259577677 # Layer occupancy (ticks) |
| 2212system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 2240system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 2213system.cpu1.toL2Bus.snoopLayer0.occupancy 160378480 # Layer occupancy (ticks) | 2241system.cpu1.toL2Bus.snoopLayer0.occupancy 163507981 # Layer occupancy (ticks) |
| 2214system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 2242system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 2215system.cpu1.toL2Bus.respLayer0.occupancy 14310919255 # Layer occupancy (ticks) | 2243system.cpu1.toL2Bus.respLayer0.occupancy 12835259097 # Layer occupancy (ticks) |
| 2216system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 2244system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2217system.cpu1.toL2Bus.respLayer1.occupancy 8198844119 # Layer occupancy (ticks) | 2245system.cpu1.toL2Bus.respLayer1.occupancy 7129308669 # Layer occupancy (ticks) |
| 2218system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 2246system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 2219system.cpu1.toL2Bus.respLayer2.occupancy 204674963 # Layer occupancy (ticks) | 2247system.cpu1.toL2Bus.respLayer2.occupancy 180853196 # Layer occupancy (ticks) |
| 2220system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 2248system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 2221system.cpu1.toL2Bus.respLayer3.occupancy 660298903 # Layer occupancy (ticks) | 2249system.cpu1.toL2Bus.respLayer3.occupancy 571040175 # Layer occupancy (ticks) |
| 2222system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 2250system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2223system.iobus.trans_dist::ReadReq 40379 # Transaction distribution 2224system.iobus.trans_dist::ReadResp 40379 # Transaction distribution 2225system.iobus.trans_dist::WriteReq 136954 # Transaction distribution 2226system.iobus.trans_dist::WriteResp 29970 # Transaction distribution | 2251system.iobus.trans_dist::ReadReq 40383 # Transaction distribution 2252system.iobus.trans_dist::ReadResp 40383 # Transaction distribution 2253system.iobus.trans_dist::WriteReq 136956 # Transaction distribution 2254system.iobus.trans_dist::WriteResp 29972 # Transaction distribution |
| 2227system.iobus.trans_dist::WriteInvalidateResp 106984 # Transaction distribution | 2255system.iobus.trans_dist::WriteInvalidateResp 106984 # Transaction distribution |
| 2228system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47756 # Packet count per connected master and slave (bytes) | 2256system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47768 # Packet count per connected master and slave (bytes) |
| 2229system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2230system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2231system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2232system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2233system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2234system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2235system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2236system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2237system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2238system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes) 2239system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2240system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2241system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2242system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) | 2257system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2258system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2259system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2260system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2261system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2262system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2263system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2264system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2265system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2266system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes) 2267system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2268system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2269system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2270system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) |
| 2243system.iobus.pkt_count_system.bridge.master::total 122846 # Packet count per connected master and slave (bytes) | 2271system.iobus.pkt_count_system.bridge.master::total 122858 # Packet count per connected master and slave (bytes) |
| 2244system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231740 # Packet count per connected master and slave (bytes) 2245system.iobus.pkt_count_system.realview.ide.dma::total 231740 # Packet count per connected master and slave (bytes) 2246system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2247system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) | 2272system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231740 # Packet count per connected master and slave (bytes) 2273system.iobus.pkt_count_system.realview.ide.dma::total 231740 # Packet count per connected master and slave (bytes) 2274system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2275system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) |
| 2248system.iobus.pkt_count::total 354666 # Packet count per connected master and slave (bytes) 2249system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47776 # Cumulative packet size per connected master and slave (bytes) | 2276system.iobus.pkt_count::total 354678 # Packet count per connected master and slave (bytes) 2277system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47788 # Cumulative packet size per connected master and slave (bytes) |
| 2250system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2251system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2252system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2253system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2254system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2255system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2256system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2257system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2258system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2259system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes) 2260system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 2261system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2262system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 2263system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) | 2278system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2279system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2280system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2281system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2282system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2283system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2284system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2285system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2286system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2287system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes) 2288system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 2289system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2290system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 2291system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) |
| 2264system.iobus.pkt_size_system.bridge.master::total 155884 # Cumulative packet size per connected master and slave (bytes) | 2292system.iobus.pkt_size_system.bridge.master::total 155896 # Cumulative packet size per connected master and slave (bytes) |
| 2265system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355312 # Cumulative packet size per connected master and slave (bytes) 2266system.iobus.pkt_size_system.realview.ide.dma::total 7355312 # Cumulative packet size per connected master and slave (bytes) 2267system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2268system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) | 2293system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355312 # Cumulative packet size per connected master and slave (bytes) 2294system.iobus.pkt_size_system.realview.ide.dma::total 7355312 # Cumulative packet size per connected master and slave (bytes) 2295system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2296system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) |
| 2269system.iobus.pkt_size::total 7513282 # Cumulative packet size per connected master and slave (bytes) 2270system.iobus.reqLayer0.occupancy 36279000 # Layer occupancy (ticks) | 2297system.iobus.pkt_size::total 7513294 # Cumulative packet size per connected master and slave (bytes) 2298system.iobus.reqLayer0.occupancy 36287000 # Layer occupancy (ticks) |
| 2271system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2272system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 2273system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2274system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 2275system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2276system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 2277system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2278system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) --- 11 unchanged lines hidden (view full) --- 2290system.iobus.reqLayer23.occupancy 22103000 # Layer occupancy (ticks) 2291system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2292system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 2293system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2294system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 2295system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2296system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 2297system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) | 2299system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2300system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 2301system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2302system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 2303system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2304system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 2305system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2306system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) --- 11 unchanged lines hidden (view full) --- 2318system.iobus.reqLayer23.occupancy 22103000 # Layer occupancy (ticks) 2319system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2320system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 2321system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2322system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 2323system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2324system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 2325system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) |
| 2298system.iobus.reqLayer27.occupancy 609062244 # Layer occupancy (ticks) | 2326system.iobus.reqLayer27.occupancy 608916622 # Layer occupancy (ticks) |
| 2299system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2300system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2301system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) | 2327system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2328system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2329system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) |
| 2302system.iobus.respLayer0.occupancy 92879000 # Layer occupancy (ticks) | 2330system.iobus.respLayer0.occupancy 92889000 # Layer occupancy (ticks) |
| 2303system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 2331system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 2304system.iobus.respLayer3.occupancy 148791282 # Layer occupancy (ticks) | 2332system.iobus.respLayer3.occupancy 148804483 # Layer occupancy (ticks) |
| 2305system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) | 2333system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 2306system.iobus.respLayer4.occupancy 171000 # Layer occupancy (ticks) | 2334system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) |
| 2307system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) | 2335system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) |
| 2308system.iocache.tags.replacements 115866 # number of replacements 2309system.iocache.tags.tagsinuse 11.306200 # Cycle average of tags in use | 2336system.iocache.tags.replacements 115850 # number of replacements 2337system.iocache.tags.tagsinuse 11.297267 # Cycle average of tags in use |
| 2310system.iocache.tags.total_refs 3 # Total number of references to valid blocks. | 2338system.iocache.tags.total_refs 3 # Total number of references to valid blocks. |
| 2311system.iocache.tags.sampled_refs 115882 # Sample count of references to valid blocks. | 2339system.iocache.tags.sampled_refs 115866 # Sample count of references to valid blocks. |
| 2312system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. | 2340system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. |
| 2313system.iocache.tags.warmup_cycle 9129676346000 # Cycle when the warmup percentage was hit. 2314system.iocache.tags.occ_blocks::realview.ethernet 7.405197 # Average occupied blocks per requestor 2315system.iocache.tags.occ_blocks::realview.ide 3.901004 # Average occupied blocks per requestor 2316system.iocache.tags.occ_percent::realview.ethernet 0.462825 # Average percentage of cache occupancy 2317system.iocache.tags.occ_percent::realview.ide 0.243813 # Average percentage of cache occupancy 2318system.iocache.tags.occ_percent::total 0.706638 # Average percentage of cache occupancy | 2341system.iocache.tags.warmup_cycle 9129662020000 # Cycle when the warmup percentage was hit. 2342system.iocache.tags.occ_blocks::realview.ethernet 3.840346 # Average occupied blocks per requestor 2343system.iocache.tags.occ_blocks::realview.ide 7.456922 # Average occupied blocks per requestor 2344system.iocache.tags.occ_percent::realview.ethernet 0.240022 # Average percentage of cache occupancy 2345system.iocache.tags.occ_percent::realview.ide 0.466058 # Average percentage of cache occupancy 2346system.iocache.tags.occ_percent::total 0.706079 # Average percentage of cache occupancy |
| 2319system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id | 2347system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id |
| 2320system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id | 2348system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id |
| 2321system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2322system.iocache.tags.tag_accesses 1043187 # Number of tag accesses 2323system.iocache.tags.data_accesses 1043187 # Number of data accesses 2324system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2325system.iocache.ReadReq_misses::realview.ide 8886 # number of ReadReq misses 2326system.iocache.ReadReq_misses::total 8923 # number of ReadReq misses 2327system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2328system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2329system.iocache.WriteInvalidateReq_misses::realview.ide 106984 # number of WriteInvalidateReq misses 2330system.iocache.WriteInvalidateReq_misses::total 106984 # number of WriteInvalidateReq misses 2331system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2332system.iocache.demand_misses::realview.ide 8886 # number of demand (read+write) misses 2333system.iocache.demand_misses::total 8926 # number of demand (read+write) misses 2334system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2335system.iocache.overall_misses::realview.ide 8886 # number of overall misses 2336system.iocache.overall_misses::total 8926 # number of overall misses | 2349system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2350system.iocache.tags.tag_accesses 1043187 # Number of tag accesses 2351system.iocache.tags.data_accesses 1043187 # Number of data accesses 2352system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2353system.iocache.ReadReq_misses::realview.ide 8886 # number of ReadReq misses 2354system.iocache.ReadReq_misses::total 8923 # number of ReadReq misses 2355system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2356system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2357system.iocache.WriteInvalidateReq_misses::realview.ide 106984 # number of WriteInvalidateReq misses 2358system.iocache.WriteInvalidateReq_misses::total 106984 # number of WriteInvalidateReq misses 2359system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2360system.iocache.demand_misses::realview.ide 8886 # number of demand (read+write) misses 2361system.iocache.demand_misses::total 8926 # number of demand (read+write) misses 2362system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2363system.iocache.overall_misses::realview.ide 8886 # number of overall misses 2364system.iocache.overall_misses::total 8926 # number of overall misses |
| 2337system.iocache.ReadReq_miss_latency::realview.ethernet 5190000 # number of ReadReq miss cycles 2338system.iocache.ReadReq_miss_latency::realview.ide 1626687073 # number of ReadReq miss cycles 2339system.iocache.ReadReq_miss_latency::total 1631877073 # number of ReadReq miss cycles | 2365system.iocache.ReadReq_miss_latency::realview.ethernet 5219500 # number of ReadReq miss cycles 2366system.iocache.ReadReq_miss_latency::realview.ide 1645546182 # number of ReadReq miss cycles 2367system.iocache.ReadReq_miss_latency::total 1650765682 # number of ReadReq miss cycles |
| 2340system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2341system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles | 2368system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2369system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles |
| 2342system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19941362889 # number of WriteInvalidateReq miss cycles 2343system.iocache.WriteInvalidateReq_miss_latency::total 19941362889 # number of WriteInvalidateReq miss cycles 2344system.iocache.demand_miss_latency::realview.ethernet 5559000 # number of demand (read+write) miss cycles 2345system.iocache.demand_miss_latency::realview.ide 1626687073 # number of demand (read+write) miss cycles 2346system.iocache.demand_miss_latency::total 1632246073 # number of demand (read+write) miss cycles 2347system.iocache.overall_miss_latency::realview.ethernet 5559000 # number of overall miss cycles 2348system.iocache.overall_miss_latency::realview.ide 1626687073 # number of overall miss cycles 2349system.iocache.overall_miss_latency::total 1632246073 # number of overall miss cycles | 2370system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19952013957 # number of WriteInvalidateReq miss cycles 2371system.iocache.WriteInvalidateReq_miss_latency::total 19952013957 # number of WriteInvalidateReq miss cycles 2372system.iocache.demand_miss_latency::realview.ethernet 5588500 # number of demand (read+write) miss cycles 2373system.iocache.demand_miss_latency::realview.ide 1645546182 # number of demand (read+write) miss cycles 2374system.iocache.demand_miss_latency::total 1651134682 # number of demand (read+write) miss cycles 2375system.iocache.overall_miss_latency::realview.ethernet 5588500 # number of overall miss cycles 2376system.iocache.overall_miss_latency::realview.ide 1645546182 # number of overall miss cycles 2377system.iocache.overall_miss_latency::total 1651134682 # number of overall miss cycles |
| 2350system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2351system.iocache.ReadReq_accesses::realview.ide 8886 # number of ReadReq accesses(hits+misses) 2352system.iocache.ReadReq_accesses::total 8923 # number of ReadReq accesses(hits+misses) 2353system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2354system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2355system.iocache.WriteInvalidateReq_accesses::realview.ide 106984 # number of WriteInvalidateReq accesses(hits+misses) 2356system.iocache.WriteInvalidateReq_accesses::total 106984 # number of WriteInvalidateReq accesses(hits+misses) 2357system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses --- 10 unchanged lines hidden (view full) --- 2368system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2369system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 2370system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2371system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2372system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2373system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2374system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2375system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 2378system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2379system.iocache.ReadReq_accesses::realview.ide 8886 # number of ReadReq accesses(hits+misses) 2380system.iocache.ReadReq_accesses::total 8923 # number of ReadReq accesses(hits+misses) 2381system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2382system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2383system.iocache.WriteInvalidateReq_accesses::realview.ide 106984 # number of WriteInvalidateReq accesses(hits+misses) 2384system.iocache.WriteInvalidateReq_accesses::total 106984 # number of WriteInvalidateReq accesses(hits+misses) 2385system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses --- 10 unchanged lines hidden (view full) --- 2396system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2397system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 2398system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2399system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2400system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2401system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2402system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2403system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 2376system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140270.270270 # average ReadReq miss latency 2377system.iocache.ReadReq_avg_miss_latency::realview.ide 183061.790795 # average ReadReq miss latency 2378system.iocache.ReadReq_avg_miss_latency::total 182884.352012 # average ReadReq miss latency | 2404system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141067.567568 # average ReadReq miss latency 2405system.iocache.ReadReq_avg_miss_latency::realview.ide 185184.130317 # average ReadReq miss latency 2406system.iocache.ReadReq_avg_miss_latency::total 185001.197131 # average ReadReq miss latency |
| 2379system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2380system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency | 2407system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2408system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency |
| 2381system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186395.749729 # average WriteInvalidateReq miss latency 2382system.iocache.WriteInvalidateReq_avg_miss_latency::total 186395.749729 # average WriteInvalidateReq miss latency 2383system.iocache.demand_avg_miss_latency::realview.ethernet 138975 # average overall miss latency 2384system.iocache.demand_avg_miss_latency::realview.ide 183061.790795 # average overall miss latency 2385system.iocache.demand_avg_miss_latency::total 182864.225073 # average overall miss latency 2386system.iocache.overall_avg_miss_latency::realview.ethernet 138975 # average overall miss latency 2387system.iocache.overall_avg_miss_latency::realview.ide 183061.790795 # average overall miss latency 2388system.iocache.overall_avg_miss_latency::total 182864.225073 # average overall miss latency 2389system.iocache.blocked_cycles::no_mshrs 111964 # number of cycles access was blocked | 2409system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186495.307308 # average WriteInvalidateReq miss latency 2410system.iocache.WriteInvalidateReq_avg_miss_latency::total 186495.307308 # average WriteInvalidateReq miss latency 2411system.iocache.demand_avg_miss_latency::realview.ethernet 139712.500000 # average overall miss latency 2412system.iocache.demand_avg_miss_latency::realview.ide 185184.130317 # average overall miss latency 2413system.iocache.demand_avg_miss_latency::total 184980.358727 # average overall miss latency 2414system.iocache.overall_avg_miss_latency::realview.ethernet 139712.500000 # average overall miss latency 2415system.iocache.overall_avg_miss_latency::realview.ide 185184.130317 # average overall miss latency 2416system.iocache.overall_avg_miss_latency::total 184980.358727 # average overall miss latency 2417system.iocache.blocked_cycles::no_mshrs 111929 # number of cycles access was blocked |
| 2390system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2418system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2391system.iocache.blocked::no_mshrs 16416 # number of cycles access was blocked | 2419system.iocache.blocked::no_mshrs 16372 # number of cycles access was blocked |
| 2392system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 2420system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 2393system.iocache.avg_blocked_cycles::no_mshrs 6.820419 # average number of cycles each access was blocked | 2421system.iocache.avg_blocked_cycles::no_mshrs 6.836611 # average number of cycles each access was blocked |
| 2394system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2395system.iocache.fast_writes 0 # number of fast writes performed 2396system.iocache.cache_copies 0 # number of cache copies performed | 2422system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2423system.iocache.fast_writes 0 # number of fast writes performed 2424system.iocache.cache_copies 0 # number of cache copies performed |
| 2397system.iocache.writebacks::writebacks 106950 # number of writebacks 2398system.iocache.writebacks::total 106950 # number of writebacks | 2425system.iocache.writebacks::writebacks 106949 # number of writebacks 2426system.iocache.writebacks::total 106949 # number of writebacks |
| 2399system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2400system.iocache.ReadReq_mshr_misses::realview.ide 8886 # number of ReadReq MSHR misses 2401system.iocache.ReadReq_mshr_misses::total 8923 # number of ReadReq MSHR misses 2402system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2403system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2404system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106984 # number of WriteInvalidateReq MSHR misses 2405system.iocache.WriteInvalidateReq_mshr_misses::total 106984 # number of WriteInvalidateReq MSHR misses 2406system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2407system.iocache.demand_mshr_misses::realview.ide 8886 # number of demand (read+write) MSHR misses 2408system.iocache.demand_mshr_misses::total 8926 # number of demand (read+write) MSHR misses 2409system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2410system.iocache.overall_mshr_misses::realview.ide 8886 # number of overall MSHR misses 2411system.iocache.overall_mshr_misses::total 8926 # number of overall MSHR misses | 2427system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2428system.iocache.ReadReq_mshr_misses::realview.ide 8886 # number of ReadReq MSHR misses 2429system.iocache.ReadReq_mshr_misses::total 8923 # number of ReadReq MSHR misses 2430system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2431system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2432system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106984 # number of WriteInvalidateReq MSHR misses 2433system.iocache.WriteInvalidateReq_mshr_misses::total 106984 # number of WriteInvalidateReq MSHR misses 2434system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2435system.iocache.demand_mshr_misses::realview.ide 8886 # number of demand (read+write) MSHR misses 2436system.iocache.demand_mshr_misses::total 8926 # number of demand (read+write) MSHR misses 2437system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2438system.iocache.overall_mshr_misses::realview.ide 8886 # number of overall MSHR misses 2439system.iocache.overall_mshr_misses::total 8926 # number of overall MSHR misses |
| 2412system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3264000 # number of ReadReq MSHR miss cycles 2413system.iocache.ReadReq_mshr_miss_latency::realview.ide 1163415573 # number of ReadReq MSHR miss cycles 2414system.iocache.ReadReq_mshr_miss_latency::total 1166679573 # number of ReadReq MSHR miss cycles | 2440system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3294500 # number of ReadReq MSHR miss cycles 2441system.iocache.ReadReq_mshr_miss_latency::realview.ide 1182279102 # number of ReadReq MSHR miss cycles 2442system.iocache.ReadReq_mshr_miss_latency::total 1185573602 # number of ReadReq MSHR miss cycles |
| 2415system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles 2416system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles | 2443system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles 2444system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles |
| 2417system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14378130953 # number of WriteInvalidateReq MSHR miss cycles 2418system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14378130953 # number of WriteInvalidateReq MSHR miss cycles 2419system.iocache.demand_mshr_miss_latency::realview.ethernet 3477000 # number of demand (read+write) MSHR miss cycles 2420system.iocache.demand_mshr_miss_latency::realview.ide 1163415573 # number of demand (read+write) MSHR miss cycles 2421system.iocache.demand_mshr_miss_latency::total 1166892573 # number of demand (read+write) MSHR miss cycles 2422system.iocache.overall_mshr_miss_latency::realview.ethernet 3477000 # number of overall MSHR miss cycles 2423system.iocache.overall_mshr_miss_latency::realview.ide 1163415573 # number of overall MSHR miss cycles 2424system.iocache.overall_mshr_miss_latency::total 1166892573 # number of overall MSHR miss cycles | 2445system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14388800003 # number of WriteInvalidateReq MSHR miss cycles 2446system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14388800003 # number of WriteInvalidateReq MSHR miss cycles 2447system.iocache.demand_mshr_miss_latency::realview.ethernet 3507500 # number of demand (read+write) MSHR miss cycles 2448system.iocache.demand_mshr_miss_latency::realview.ide 1182279102 # number of demand (read+write) MSHR miss cycles 2449system.iocache.demand_mshr_miss_latency::total 1185786602 # number of demand (read+write) MSHR miss cycles 2450system.iocache.overall_mshr_miss_latency::realview.ethernet 3507500 # number of overall MSHR miss cycles 2451system.iocache.overall_mshr_miss_latency::realview.ide 1182279102 # number of overall MSHR miss cycles 2452system.iocache.overall_mshr_miss_latency::total 1185786602 # number of overall MSHR miss cycles |
| 2425system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2426system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2427system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2428system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2429system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2430system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2431system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 2432system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2433system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2434system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2435system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2436system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2437system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 2453system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2454system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2455system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2456system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2457system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2458system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2459system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 2460system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2461system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2462system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2463system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2464system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2465system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 2438system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88216.216216 # average ReadReq mshr miss latency 2439system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130926.803174 # average ReadReq mshr miss latency 2440system.iocache.ReadReq_avg_mshr_miss_latency::total 130749.699989 # average ReadReq mshr miss latency | 2466system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 89040.540541 # average ReadReq mshr miss latency 2467system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 133049.640108 # average ReadReq mshr miss latency 2468system.iocache.ReadReq_avg_mshr_miss_latency::total 132867.152527 # average ReadReq mshr miss latency |
| 2441system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency 2442system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency | 2469system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency 2470system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency |
| 2443system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134395.152107 # average WriteInvalidateReq mshr miss latency 2444system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134395.152107 # average WriteInvalidateReq mshr miss latency 2445system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 86925 # average overall mshr miss latency 2446system.iocache.demand_avg_mshr_miss_latency::realview.ide 130926.803174 # average overall mshr miss latency 2447system.iocache.demand_avg_mshr_miss_latency::total 130729.618306 # average overall mshr miss latency 2448system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 86925 # average overall mshr miss latency 2449system.iocache.overall_avg_mshr_miss_latency::realview.ide 130926.803174 # average overall mshr miss latency 2450system.iocache.overall_avg_mshr_miss_latency::total 130729.618306 # average overall mshr miss latency | 2471system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134494.877767 # average WriteInvalidateReq mshr miss latency 2472system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134494.877767 # average WriteInvalidateReq mshr miss latency 2473system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87687.500000 # average overall mshr miss latency 2474system.iocache.demand_avg_mshr_miss_latency::realview.ide 133049.640108 # average overall mshr miss latency 2475system.iocache.demand_avg_mshr_miss_latency::total 132846.359175 # average overall mshr miss latency 2476system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87687.500000 # average overall mshr miss latency 2477system.iocache.overall_avg_mshr_miss_latency::realview.ide 133049.640108 # average overall mshr miss latency 2478system.iocache.overall_avg_mshr_miss_latency::total 132846.359175 # average overall mshr miss latency |
| 2451system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 2479system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 2452system.l2c.tags.replacements 1418934 # number of replacements 2453system.l2c.tags.tagsinuse 64475.403646 # Cycle average of tags in use 2454system.l2c.tags.total_refs 4887849 # Total number of references to valid blocks. 2455system.l2c.tags.sampled_refs 1480275 # Sample count of references to valid blocks. 2456system.l2c.tags.avg_refs 3.301987 # Average number of references to valid blocks. 2457system.l2c.tags.warmup_cycle 8811587000 # Cycle when the warmup percentage was hit. 2458system.l2c.tags.occ_blocks::writebacks 16720.464314 # Average occupied blocks per requestor 2459system.l2c.tags.occ_blocks::cpu0.dtb.walker 9.676845 # Average occupied blocks per requestor 2460system.l2c.tags.occ_blocks::cpu0.itb.walker 2.082484 # Average occupied blocks per requestor 2461system.l2c.tags.occ_blocks::cpu0.inst 3893.344537 # Average occupied blocks per requestor 2462system.l2c.tags.occ_blocks::cpu0.data 5310.090712 # Average occupied blocks per requestor 2463system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3772.998059 # Average occupied blocks per requestor 2464system.l2c.tags.occ_blocks::cpu1.dtb.walker 379.879752 # Average occupied blocks per requestor 2465system.l2c.tags.occ_blocks::cpu1.itb.walker 518.261056 # Average occupied blocks per requestor 2466system.l2c.tags.occ_blocks::cpu1.inst 4648.220337 # Average occupied blocks per requestor 2467system.l2c.tags.occ_blocks::cpu1.data 11740.962883 # Average occupied blocks per requestor 2468system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17479.422666 # Average occupied blocks per requestor 2469system.l2c.tags.occ_percent::writebacks 0.255134 # Average percentage of cache occupancy 2470system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000148 # Average percentage of cache occupancy 2471system.l2c.tags.occ_percent::cpu0.itb.walker 0.000032 # Average percentage of cache occupancy 2472system.l2c.tags.occ_percent::cpu0.inst 0.059408 # Average percentage of cache occupancy 2473system.l2c.tags.occ_percent::cpu0.data 0.081026 # Average percentage of cache occupancy 2474system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.057571 # Average percentage of cache occupancy 2475system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005797 # Average percentage of cache occupancy 2476system.l2c.tags.occ_percent::cpu1.itb.walker 0.007908 # Average percentage of cache occupancy 2477system.l2c.tags.occ_percent::cpu1.inst 0.070926 # Average percentage of cache occupancy 2478system.l2c.tags.occ_percent::cpu1.data 0.179153 # Average percentage of cache occupancy 2479system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.266715 # Average percentage of cache occupancy 2480system.l2c.tags.occ_percent::total 0.983817 # Average percentage of cache occupancy 2481system.l2c.tags.occ_task_id_blocks::1022 9966 # Occupied blocks per task id 2482system.l2c.tags.occ_task_id_blocks::1023 213 # Occupied blocks per task id 2483system.l2c.tags.occ_task_id_blocks::1024 51162 # Occupied blocks per task id 2484system.l2c.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id 2485system.l2c.tags.age_task_id_blocks_1022::1 69 # Occupied blocks per task id 2486system.l2c.tags.age_task_id_blocks_1022::2 272 # Occupied blocks per task id 2487system.l2c.tags.age_task_id_blocks_1022::3 1682 # Occupied blocks per task id 2488system.l2c.tags.age_task_id_blocks_1022::4 7941 # Occupied blocks per task id 2489system.l2c.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 2490system.l2c.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2491system.l2c.tags.age_task_id_blocks_1023::4 195 # Occupied blocks per task id 2492system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 2493system.l2c.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id 2494system.l2c.tags.age_task_id_blocks_1024::2 1978 # Occupied blocks per task id 2495system.l2c.tags.age_task_id_blocks_1024::3 11118 # Occupied blocks per task id 2496system.l2c.tags.age_task_id_blocks_1024::4 37794 # Occupied blocks per task id 2497system.l2c.tags.occ_task_id_percent::1022 0.152069 # Percentage of cache occupancy per task id 2498system.l2c.tags.occ_task_id_percent::1023 0.003250 # Percentage of cache occupancy per task id 2499system.l2c.tags.occ_task_id_percent::1024 0.780670 # Percentage of cache occupancy per task id 2500system.l2c.tags.tag_accesses 63367915 # Number of tag accesses 2501system.l2c.tags.data_accesses 63367915 # Number of data accesses 2502system.l2c.ReadReq_hits::cpu0.dtb.walker 6326 # number of ReadReq hits 2503system.l2c.ReadReq_hits::cpu0.itb.walker 4773 # number of ReadReq hits 2504system.l2c.ReadReq_hits::cpu0.inst 672724 # number of ReadReq hits 2505system.l2c.ReadReq_hits::cpu0.data 551559 # number of ReadReq hits 2506system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 298336 # number of ReadReq hits 2507system.l2c.ReadReq_hits::cpu1.dtb.walker 6350 # number of ReadReq hits 2508system.l2c.ReadReq_hits::cpu1.itb.walker 4103 # number of ReadReq hits 2509system.l2c.ReadReq_hits::cpu1.inst 758519 # number of ReadReq hits 2510system.l2c.ReadReq_hits::cpu1.data 584378 # number of ReadReq hits 2511system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 311165 # number of ReadReq hits 2512system.l2c.ReadReq_hits::total 3198233 # number of ReadReq hits 2513system.l2c.Writeback_hits::writebacks 2396374 # number of Writeback hits 2514system.l2c.Writeback_hits::total 2396374 # number of Writeback hits 2515system.l2c.WriteInvalidateReq_hits::cpu0.data 132089 # number of WriteInvalidateReq hits 2516system.l2c.WriteInvalidateReq_hits::cpu1.data 134441 # number of WriteInvalidateReq hits 2517system.l2c.WriteInvalidateReq_hits::total 266530 # number of WriteInvalidateReq hits 2518system.l2c.UpgradeReq_hits::cpu0.data 29493 # number of UpgradeReq hits 2519system.l2c.UpgradeReq_hits::cpu1.data 27736 # number of UpgradeReq hits 2520system.l2c.UpgradeReq_hits::total 57229 # number of UpgradeReq hits 2521system.l2c.SCUpgradeReq_hits::cpu0.data 5838 # number of SCUpgradeReq hits 2522system.l2c.SCUpgradeReq_hits::cpu1.data 6131 # number of SCUpgradeReq hits 2523system.l2c.SCUpgradeReq_hits::total 11969 # number of SCUpgradeReq hits 2524system.l2c.ReadExReq_hits::cpu0.data 53859 # number of ReadExReq hits 2525system.l2c.ReadExReq_hits::cpu1.data 51185 # number of ReadExReq hits 2526system.l2c.ReadExReq_hits::total 105044 # number of ReadExReq hits 2527system.l2c.demand_hits::cpu0.dtb.walker 6326 # number of demand (read+write) hits 2528system.l2c.demand_hits::cpu0.itb.walker 4773 # number of demand (read+write) hits 2529system.l2c.demand_hits::cpu0.inst 672724 # number of demand (read+write) hits 2530system.l2c.demand_hits::cpu0.data 605418 # number of demand (read+write) hits 2531system.l2c.demand_hits::cpu0.l2cache.prefetcher 298336 # number of demand (read+write) hits 2532system.l2c.demand_hits::cpu1.dtb.walker 6350 # number of demand (read+write) hits 2533system.l2c.demand_hits::cpu1.itb.walker 4103 # number of demand (read+write) hits 2534system.l2c.demand_hits::cpu1.inst 758519 # number of demand (read+write) hits 2535system.l2c.demand_hits::cpu1.data 635563 # number of demand (read+write) hits 2536system.l2c.demand_hits::cpu1.l2cache.prefetcher 311165 # number of demand (read+write) hits 2537system.l2c.demand_hits::total 3303277 # number of demand (read+write) hits 2538system.l2c.overall_hits::cpu0.dtb.walker 6326 # number of overall hits 2539system.l2c.overall_hits::cpu0.itb.walker 4773 # number of overall hits 2540system.l2c.overall_hits::cpu0.inst 672724 # number of overall hits 2541system.l2c.overall_hits::cpu0.data 605418 # number of overall hits 2542system.l2c.overall_hits::cpu0.l2cache.prefetcher 298336 # number of overall hits 2543system.l2c.overall_hits::cpu1.dtb.walker 6350 # number of overall hits 2544system.l2c.overall_hits::cpu1.itb.walker 4103 # number of overall hits 2545system.l2c.overall_hits::cpu1.inst 758519 # number of overall hits 2546system.l2c.overall_hits::cpu1.data 635563 # number of overall hits 2547system.l2c.overall_hits::cpu1.l2cache.prefetcher 311165 # number of overall hits 2548system.l2c.overall_hits::total 3303277 # number of overall hits 2549system.l2c.ReadReq_misses::cpu0.dtb.walker 1746 # number of ReadReq misses 2550system.l2c.ReadReq_misses::cpu0.itb.walker 1432 # number of ReadReq misses 2551system.l2c.ReadReq_misses::cpu0.inst 67682 # number of ReadReq misses 2552system.l2c.ReadReq_misses::cpu0.data 130428 # number of ReadReq misses 2553system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 208623 # number of ReadReq misses 2554system.l2c.ReadReq_misses::cpu1.dtb.walker 2332 # number of ReadReq misses 2555system.l2c.ReadReq_misses::cpu1.itb.walker 2285 # number of ReadReq misses 2556system.l2c.ReadReq_misses::cpu1.inst 60547 # number of ReadReq misses 2557system.l2c.ReadReq_misses::cpu1.data 132466 # number of ReadReq misses 2558system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 215131 # number of ReadReq misses 2559system.l2c.ReadReq_misses::total 822672 # number of ReadReq misses 2560system.l2c.WriteInvalidateReq_misses::cpu0.data 442954 # number of WriteInvalidateReq misses 2561system.l2c.WriteInvalidateReq_misses::cpu1.data 116624 # number of WriteInvalidateReq misses 2562system.l2c.WriteInvalidateReq_misses::total 559578 # number of WriteInvalidateReq misses 2563system.l2c.UpgradeReq_misses::cpu0.data 45697 # number of UpgradeReq misses 2564system.l2c.UpgradeReq_misses::cpu1.data 44658 # number of UpgradeReq misses 2565system.l2c.UpgradeReq_misses::total 90355 # number of UpgradeReq misses 2566system.l2c.SCUpgradeReq_misses::cpu0.data 8940 # number of SCUpgradeReq misses 2567system.l2c.SCUpgradeReq_misses::cpu1.data 8873 # number of SCUpgradeReq misses 2568system.l2c.SCUpgradeReq_misses::total 17813 # number of SCUpgradeReq misses 2569system.l2c.ReadExReq_misses::cpu0.data 77535 # number of ReadExReq misses 2570system.l2c.ReadExReq_misses::cpu1.data 55004 # number of ReadExReq misses 2571system.l2c.ReadExReq_misses::total 132539 # number of ReadExReq misses 2572system.l2c.demand_misses::cpu0.dtb.walker 1746 # number of demand (read+write) misses 2573system.l2c.demand_misses::cpu0.itb.walker 1432 # number of demand (read+write) misses 2574system.l2c.demand_misses::cpu0.inst 67682 # number of demand (read+write) misses 2575system.l2c.demand_misses::cpu0.data 207963 # number of demand (read+write) misses 2576system.l2c.demand_misses::cpu0.l2cache.prefetcher 208623 # number of demand (read+write) misses 2577system.l2c.demand_misses::cpu1.dtb.walker 2332 # number of demand (read+write) misses 2578system.l2c.demand_misses::cpu1.itb.walker 2285 # number of demand (read+write) misses 2579system.l2c.demand_misses::cpu1.inst 60547 # number of demand (read+write) misses 2580system.l2c.demand_misses::cpu1.data 187470 # number of demand (read+write) misses 2581system.l2c.demand_misses::cpu1.l2cache.prefetcher 215131 # number of demand (read+write) misses 2582system.l2c.demand_misses::total 955211 # number of demand (read+write) misses 2583system.l2c.overall_misses::cpu0.dtb.walker 1746 # number of overall misses 2584system.l2c.overall_misses::cpu0.itb.walker 1432 # number of overall misses 2585system.l2c.overall_misses::cpu0.inst 67682 # number of overall misses 2586system.l2c.overall_misses::cpu0.data 207963 # number of overall misses 2587system.l2c.overall_misses::cpu0.l2cache.prefetcher 208623 # number of overall misses 2588system.l2c.overall_misses::cpu1.dtb.walker 2332 # number of overall misses 2589system.l2c.overall_misses::cpu1.itb.walker 2285 # number of overall misses 2590system.l2c.overall_misses::cpu1.inst 60547 # number of overall misses 2591system.l2c.overall_misses::cpu1.data 187470 # number of overall misses 2592system.l2c.overall_misses::cpu1.l2cache.prefetcher 215131 # number of overall misses 2593system.l2c.overall_misses::total 955211 # number of overall misses 2594system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 161430014 # number of ReadReq miss cycles 2595system.l2c.ReadReq_miss_latency::cpu0.itb.walker 133523499 # number of ReadReq miss cycles 2596system.l2c.ReadReq_miss_latency::cpu0.inst 5728187863 # number of ReadReq miss cycles 2597system.l2c.ReadReq_miss_latency::cpu0.data 12139315223 # number of ReadReq miss cycles 2598system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 27793617273 # number of ReadReq miss cycles 2599system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 206166757 # number of ReadReq miss cycles 2600system.l2c.ReadReq_miss_latency::cpu1.itb.walker 199956257 # number of ReadReq miss cycles 2601system.l2c.ReadReq_miss_latency::cpu1.inst 5085068912 # number of ReadReq miss cycles 2602system.l2c.ReadReq_miss_latency::cpu1.data 11808697846 # number of ReadReq miss cycles 2603system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 27463393997 # number of ReadReq miss cycles 2604system.l2c.ReadReq_miss_latency::total 90719357641 # number of ReadReq miss cycles 2605system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 48375493 # number of WriteInvalidateReq miss cycles 2606system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 41411697 # number of WriteInvalidateReq miss cycles 2607system.l2c.WriteInvalidateReq_miss_latency::total 89787190 # number of WriteInvalidateReq miss cycles 2608system.l2c.UpgradeReq_miss_latency::cpu0.data 259807838 # number of UpgradeReq miss cycles 2609system.l2c.UpgradeReq_miss_latency::cpu1.data 288996819 # number of UpgradeReq miss cycles 2610system.l2c.UpgradeReq_miss_latency::total 548804657 # number of UpgradeReq miss cycles 2611system.l2c.SCUpgradeReq_miss_latency::cpu0.data 49028949 # number of SCUpgradeReq miss cycles 2612system.l2c.SCUpgradeReq_miss_latency::cpu1.data 59371116 # number of SCUpgradeReq miss cycles 2613system.l2c.SCUpgradeReq_miss_latency::total 108400065 # number of SCUpgradeReq miss cycles 2614system.l2c.ReadExReq_miss_latency::cpu0.data 6929592651 # number of ReadExReq miss cycles 2615system.l2c.ReadExReq_miss_latency::cpu1.data 4617668591 # number of ReadExReq miss cycles 2616system.l2c.ReadExReq_miss_latency::total 11547261242 # number of ReadExReq miss cycles 2617system.l2c.demand_miss_latency::cpu0.dtb.walker 161430014 # number of demand (read+write) miss cycles 2618system.l2c.demand_miss_latency::cpu0.itb.walker 133523499 # number of demand (read+write) miss cycles 2619system.l2c.demand_miss_latency::cpu0.inst 5728187863 # number of demand (read+write) miss cycles 2620system.l2c.demand_miss_latency::cpu0.data 19068907874 # number of demand (read+write) miss cycles 2621system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 27793617273 # number of demand (read+write) miss cycles 2622system.l2c.demand_miss_latency::cpu1.dtb.walker 206166757 # number of demand (read+write) miss cycles 2623system.l2c.demand_miss_latency::cpu1.itb.walker 199956257 # number of demand (read+write) miss cycles 2624system.l2c.demand_miss_latency::cpu1.inst 5085068912 # number of demand (read+write) miss cycles 2625system.l2c.demand_miss_latency::cpu1.data 16426366437 # number of demand (read+write) miss cycles 2626system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 27463393997 # number of demand (read+write) miss cycles 2627system.l2c.demand_miss_latency::total 102266618883 # number of demand (read+write) miss cycles 2628system.l2c.overall_miss_latency::cpu0.dtb.walker 161430014 # number of overall miss cycles 2629system.l2c.overall_miss_latency::cpu0.itb.walker 133523499 # number of overall miss cycles 2630system.l2c.overall_miss_latency::cpu0.inst 5728187863 # number of overall miss cycles 2631system.l2c.overall_miss_latency::cpu0.data 19068907874 # number of overall miss cycles 2632system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 27793617273 # number of overall miss cycles 2633system.l2c.overall_miss_latency::cpu1.dtb.walker 206166757 # number of overall miss cycles 2634system.l2c.overall_miss_latency::cpu1.itb.walker 199956257 # number of overall miss cycles 2635system.l2c.overall_miss_latency::cpu1.inst 5085068912 # number of overall miss cycles 2636system.l2c.overall_miss_latency::cpu1.data 16426366437 # number of overall miss cycles 2637system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 27463393997 # number of overall miss cycles 2638system.l2c.overall_miss_latency::total 102266618883 # number of overall miss cycles 2639system.l2c.ReadReq_accesses::cpu0.dtb.walker 8072 # number of ReadReq accesses(hits+misses) 2640system.l2c.ReadReq_accesses::cpu0.itb.walker 6205 # number of ReadReq accesses(hits+misses) 2641system.l2c.ReadReq_accesses::cpu0.inst 740406 # number of ReadReq accesses(hits+misses) 2642system.l2c.ReadReq_accesses::cpu0.data 681987 # number of ReadReq accesses(hits+misses) 2643system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 506959 # number of ReadReq accesses(hits+misses) 2644system.l2c.ReadReq_accesses::cpu1.dtb.walker 8682 # number of ReadReq accesses(hits+misses) 2645system.l2c.ReadReq_accesses::cpu1.itb.walker 6388 # number of ReadReq accesses(hits+misses) 2646system.l2c.ReadReq_accesses::cpu1.inst 819066 # number of ReadReq accesses(hits+misses) 2647system.l2c.ReadReq_accesses::cpu1.data 716844 # number of ReadReq accesses(hits+misses) 2648system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 526296 # number of ReadReq accesses(hits+misses) 2649system.l2c.ReadReq_accesses::total 4020905 # number of ReadReq accesses(hits+misses) 2650system.l2c.Writeback_accesses::writebacks 2396374 # number of Writeback accesses(hits+misses) 2651system.l2c.Writeback_accesses::total 2396374 # number of Writeback accesses(hits+misses) 2652system.l2c.WriteInvalidateReq_accesses::cpu0.data 575043 # number of WriteInvalidateReq accesses(hits+misses) 2653system.l2c.WriteInvalidateReq_accesses::cpu1.data 251065 # number of WriteInvalidateReq accesses(hits+misses) 2654system.l2c.WriteInvalidateReq_accesses::total 826108 # number of WriteInvalidateReq accesses(hits+misses) 2655system.l2c.UpgradeReq_accesses::cpu0.data 75190 # number of UpgradeReq accesses(hits+misses) 2656system.l2c.UpgradeReq_accesses::cpu1.data 72394 # number of UpgradeReq accesses(hits+misses) 2657system.l2c.UpgradeReq_accesses::total 147584 # number of UpgradeReq accesses(hits+misses) 2658system.l2c.SCUpgradeReq_accesses::cpu0.data 14778 # number of SCUpgradeReq accesses(hits+misses) 2659system.l2c.SCUpgradeReq_accesses::cpu1.data 15004 # number of SCUpgradeReq accesses(hits+misses) 2660system.l2c.SCUpgradeReq_accesses::total 29782 # number of SCUpgradeReq accesses(hits+misses) 2661system.l2c.ReadExReq_accesses::cpu0.data 131394 # number of ReadExReq accesses(hits+misses) 2662system.l2c.ReadExReq_accesses::cpu1.data 106189 # number of ReadExReq accesses(hits+misses) 2663system.l2c.ReadExReq_accesses::total 237583 # number of ReadExReq accesses(hits+misses) 2664system.l2c.demand_accesses::cpu0.dtb.walker 8072 # number of demand (read+write) accesses 2665system.l2c.demand_accesses::cpu0.itb.walker 6205 # number of demand (read+write) accesses 2666system.l2c.demand_accesses::cpu0.inst 740406 # number of demand (read+write) accesses 2667system.l2c.demand_accesses::cpu0.data 813381 # number of demand (read+write) accesses 2668system.l2c.demand_accesses::cpu0.l2cache.prefetcher 506959 # number of demand (read+write) accesses 2669system.l2c.demand_accesses::cpu1.dtb.walker 8682 # number of demand (read+write) accesses 2670system.l2c.demand_accesses::cpu1.itb.walker 6388 # number of demand (read+write) accesses 2671system.l2c.demand_accesses::cpu1.inst 819066 # number of demand (read+write) accesses 2672system.l2c.demand_accesses::cpu1.data 823033 # number of demand (read+write) accesses 2673system.l2c.demand_accesses::cpu1.l2cache.prefetcher 526296 # number of demand (read+write) accesses 2674system.l2c.demand_accesses::total 4258488 # number of demand (read+write) accesses 2675system.l2c.overall_accesses::cpu0.dtb.walker 8072 # number of overall (read+write) accesses 2676system.l2c.overall_accesses::cpu0.itb.walker 6205 # number of overall (read+write) accesses 2677system.l2c.overall_accesses::cpu0.inst 740406 # number of overall (read+write) accesses 2678system.l2c.overall_accesses::cpu0.data 813381 # number of overall (read+write) accesses 2679system.l2c.overall_accesses::cpu0.l2cache.prefetcher 506959 # number of overall (read+write) accesses 2680system.l2c.overall_accesses::cpu1.dtb.walker 8682 # number of overall (read+write) accesses 2681system.l2c.overall_accesses::cpu1.itb.walker 6388 # number of overall (read+write) accesses 2682system.l2c.overall_accesses::cpu1.inst 819066 # number of overall (read+write) accesses 2683system.l2c.overall_accesses::cpu1.data 823033 # number of overall (read+write) accesses 2684system.l2c.overall_accesses::cpu1.l2cache.prefetcher 526296 # number of overall (read+write) accesses 2685system.l2c.overall_accesses::total 4258488 # number of overall (read+write) accesses 2686system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.216303 # miss rate for ReadReq accesses 2687system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.230782 # miss rate for ReadReq accesses 2688system.l2c.ReadReq_miss_rate::cpu0.inst 0.091412 # miss rate for ReadReq accesses 2689system.l2c.ReadReq_miss_rate::cpu0.data 0.191247 # miss rate for ReadReq accesses 2690system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.411518 # miss rate for ReadReq accesses 2691system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.268602 # miss rate for ReadReq accesses 2692system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.357702 # miss rate for ReadReq accesses 2693system.l2c.ReadReq_miss_rate::cpu1.inst 0.073922 # miss rate for ReadReq accesses 2694system.l2c.ReadReq_miss_rate::cpu1.data 0.184791 # miss rate for ReadReq accesses 2695system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.408764 # miss rate for ReadReq accesses 2696system.l2c.ReadReq_miss_rate::total 0.204599 # miss rate for ReadReq accesses 2697system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.770297 # miss rate for WriteInvalidateReq accesses 2698system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.464517 # miss rate for WriteInvalidateReq accesses 2699system.l2c.WriteInvalidateReq_miss_rate::total 0.677367 # miss rate for WriteInvalidateReq accesses 2700system.l2c.UpgradeReq_miss_rate::cpu0.data 0.607754 # miss rate for UpgradeReq accesses 2701system.l2c.UpgradeReq_miss_rate::cpu1.data 0.616874 # miss rate for UpgradeReq accesses 2702system.l2c.UpgradeReq_miss_rate::total 0.612228 # miss rate for UpgradeReq accesses 2703system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.604953 # miss rate for SCUpgradeReq accesses 2704system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.591376 # miss rate for SCUpgradeReq accesses 2705system.l2c.SCUpgradeReq_miss_rate::total 0.598113 # miss rate for SCUpgradeReq accesses 2706system.l2c.ReadExReq_miss_rate::cpu0.data 0.590095 # miss rate for ReadExReq accesses 2707system.l2c.ReadExReq_miss_rate::cpu1.data 0.517982 # miss rate for ReadExReq accesses 2708system.l2c.ReadExReq_miss_rate::total 0.557864 # miss rate for ReadExReq accesses 2709system.l2c.demand_miss_rate::cpu0.dtb.walker 0.216303 # miss rate for demand accesses 2710system.l2c.demand_miss_rate::cpu0.itb.walker 0.230782 # miss rate for demand accesses 2711system.l2c.demand_miss_rate::cpu0.inst 0.091412 # miss rate for demand accesses 2712system.l2c.demand_miss_rate::cpu0.data 0.255677 # miss rate for demand accesses 2713system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.411518 # miss rate for demand accesses 2714system.l2c.demand_miss_rate::cpu1.dtb.walker 0.268602 # miss rate for demand accesses 2715system.l2c.demand_miss_rate::cpu1.itb.walker 0.357702 # miss rate for demand accesses 2716system.l2c.demand_miss_rate::cpu1.inst 0.073922 # miss rate for demand accesses 2717system.l2c.demand_miss_rate::cpu1.data 0.227779 # miss rate for demand accesses 2718system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.408764 # miss rate for demand accesses 2719system.l2c.demand_miss_rate::total 0.224308 # miss rate for demand accesses 2720system.l2c.overall_miss_rate::cpu0.dtb.walker 0.216303 # miss rate for overall accesses 2721system.l2c.overall_miss_rate::cpu0.itb.walker 0.230782 # miss rate for overall accesses 2722system.l2c.overall_miss_rate::cpu0.inst 0.091412 # miss rate for overall accesses 2723system.l2c.overall_miss_rate::cpu0.data 0.255677 # miss rate for overall accesses 2724system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.411518 # miss rate for overall accesses 2725system.l2c.overall_miss_rate::cpu1.dtb.walker 0.268602 # miss rate for overall accesses 2726system.l2c.overall_miss_rate::cpu1.itb.walker 0.357702 # miss rate for overall accesses 2727system.l2c.overall_miss_rate::cpu1.inst 0.073922 # miss rate for overall accesses 2728system.l2c.overall_miss_rate::cpu1.data 0.227779 # miss rate for overall accesses 2729system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.408764 # miss rate for overall accesses 2730system.l2c.overall_miss_rate::total 0.224308 # miss rate for overall accesses 2731system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 92457.052692 # average ReadReq miss latency 2732system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 93242.666899 # average ReadReq miss latency 2733system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84633.844493 # average ReadReq miss latency 2734system.l2c.ReadReq_avg_miss_latency::cpu0.data 93072.923168 # average ReadReq miss latency 2735system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 133224.128083 # average ReadReq miss latency 2736system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88407.700257 # average ReadReq miss latency 2737system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 87508.208753 # average ReadReq miss latency 2738system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83985.480899 # average ReadReq miss latency 2739system.l2c.ReadReq_avg_miss_latency::cpu1.data 89145.122869 # average ReadReq miss latency 2740system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 127658.933380 # average ReadReq miss latency 2741system.l2c.ReadReq_avg_miss_latency::total 110274.031012 # average ReadReq miss latency 2742system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 109.211099 # average WriteInvalidateReq miss latency 2743system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 355.087263 # average WriteInvalidateReq miss latency 2744system.l2c.WriteInvalidateReq_avg_miss_latency::total 160.455182 # average WriteInvalidateReq miss latency 2745system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5685.446266 # average UpgradeReq miss latency 2746system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6471.333669 # average UpgradeReq miss latency 2747system.l2c.UpgradeReq_avg_miss_latency::total 6073.871474 # average UpgradeReq miss latency 2748system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5484.222483 # average SCUpgradeReq miss latency 2749system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6691.211090 # average SCUpgradeReq miss latency 2750system.l2c.SCUpgradeReq_avg_miss_latency::total 6085.446865 # average SCUpgradeReq miss latency 2751system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89373.736390 # average ReadExReq miss latency 2752system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83951.505181 # average ReadExReq miss latency 2753system.l2c.ReadExReq_avg_miss_latency::total 87123.497552 # average ReadExReq miss latency 2754system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 92457.052692 # average overall miss latency 2755system.l2c.demand_avg_miss_latency::cpu0.itb.walker 93242.666899 # average overall miss latency 2756system.l2c.demand_avg_miss_latency::cpu0.inst 84633.844493 # average overall miss latency 2757system.l2c.demand_avg_miss_latency::cpu0.data 91693.752610 # average overall miss latency 2758system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 133224.128083 # average overall miss latency 2759system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88407.700257 # average overall miss latency 2760system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87508.208753 # average overall miss latency 2761system.l2c.demand_avg_miss_latency::cpu1.inst 83985.480899 # average overall miss latency 2762system.l2c.demand_avg_miss_latency::cpu1.data 87621.307073 # average overall miss latency 2763system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 127658.933380 # average overall miss latency 2764system.l2c.demand_avg_miss_latency::total 107061.810305 # average overall miss latency 2765system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 92457.052692 # average overall miss latency 2766system.l2c.overall_avg_miss_latency::cpu0.itb.walker 93242.666899 # average overall miss latency 2767system.l2c.overall_avg_miss_latency::cpu0.inst 84633.844493 # average overall miss latency 2768system.l2c.overall_avg_miss_latency::cpu0.data 91693.752610 # average overall miss latency 2769system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 133224.128083 # average overall miss latency 2770system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88407.700257 # average overall miss latency 2771system.l2c.overall_avg_miss_latency::cpu1.itb.walker 87508.208753 # average overall miss latency 2772system.l2c.overall_avg_miss_latency::cpu1.inst 83985.480899 # average overall miss latency 2773system.l2c.overall_avg_miss_latency::cpu1.data 87621.307073 # average overall miss latency 2774system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 127658.933380 # average overall miss latency 2775system.l2c.overall_avg_miss_latency::total 107061.810305 # average overall miss latency 2776system.l2c.blocked_cycles::no_mshrs 855 # number of cycles access was blocked | 2480system.l2c.tags.replacements 1147719 # number of replacements 2481system.l2c.tags.tagsinuse 64326.028489 # Cycle average of tags in use 2482system.l2c.tags.total_refs 4694874 # Total number of references to valid blocks. 2483system.l2c.tags.sampled_refs 1208975 # Sample count of references to valid blocks. 2484system.l2c.tags.avg_refs 3.883351 # Average number of references to valid blocks. 2485system.l2c.tags.warmup_cycle 8775850000 # Cycle when the warmup percentage was hit. 2486system.l2c.tags.occ_blocks::writebacks 21201.345204 # Average occupied blocks per requestor 2487system.l2c.tags.occ_blocks::cpu0.dtb.walker 99.174306 # Average occupied blocks per requestor 2488system.l2c.tags.occ_blocks::cpu0.itb.walker 102.969089 # Average occupied blocks per requestor 2489system.l2c.tags.occ_blocks::cpu0.inst 6287.304380 # Average occupied blocks per requestor 2490system.l2c.tags.occ_blocks::cpu0.data 9789.287555 # Average occupied blocks per requestor 2491system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7119.681672 # Average occupied blocks per requestor 2492system.l2c.tags.occ_blocks::cpu1.dtb.walker 173.781032 # Average occupied blocks per requestor 2493system.l2c.tags.occ_blocks::cpu1.itb.walker 211.002205 # Average occupied blocks per requestor 2494system.l2c.tags.occ_blocks::cpu1.inst 4753.478760 # Average occupied blocks per requestor 2495system.l2c.tags.occ_blocks::cpu1.data 6062.523137 # Average occupied blocks per requestor 2496system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8525.481150 # Average occupied blocks per requestor 2497system.l2c.tags.occ_percent::writebacks 0.323507 # Average percentage of cache occupancy 2498system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001513 # Average percentage of cache occupancy 2499system.l2c.tags.occ_percent::cpu0.itb.walker 0.001571 # Average percentage of cache occupancy 2500system.l2c.tags.occ_percent::cpu0.inst 0.095937 # Average percentage of cache occupancy 2501system.l2c.tags.occ_percent::cpu0.data 0.149373 # Average percentage of cache occupancy 2502system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.108638 # Average percentage of cache occupancy 2503system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002652 # Average percentage of cache occupancy 2504system.l2c.tags.occ_percent::cpu1.itb.walker 0.003220 # Average percentage of cache occupancy 2505system.l2c.tags.occ_percent::cpu1.inst 0.072532 # Average percentage of cache occupancy 2506system.l2c.tags.occ_percent::cpu1.data 0.092507 # Average percentage of cache occupancy 2507system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.130089 # Average percentage of cache occupancy 2508system.l2c.tags.occ_percent::total 0.981537 # Average percentage of cache occupancy 2509system.l2c.tags.occ_task_id_blocks::1022 9955 # Occupied blocks per task id 2510system.l2c.tags.occ_task_id_blocks::1023 220 # Occupied blocks per task id 2511system.l2c.tags.occ_task_id_blocks::1024 51081 # Occupied blocks per task id 2512system.l2c.tags.age_task_id_blocks_1022::0 63 # Occupied blocks per task id 2513system.l2c.tags.age_task_id_blocks_1022::1 299 # Occupied blocks per task id 2514system.l2c.tags.age_task_id_blocks_1022::2 192 # Occupied blocks per task id 2515system.l2c.tags.age_task_id_blocks_1022::3 1433 # Occupied blocks per task id 2516system.l2c.tags.age_task_id_blocks_1022::4 7968 # Occupied blocks per task id 2517system.l2c.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 2518system.l2c.tags.age_task_id_blocks_1023::4 215 # Occupied blocks per task id 2519system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 2520system.l2c.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id 2521system.l2c.tags.age_task_id_blocks_1024::2 2117 # Occupied blocks per task id 2522system.l2c.tags.age_task_id_blocks_1024::3 11769 # Occupied blocks per task id 2523system.l2c.tags.age_task_id_blocks_1024::4 36932 # Occupied blocks per task id 2524system.l2c.tags.occ_task_id_percent::1022 0.151901 # Percentage of cache occupancy per task id 2525system.l2c.tags.occ_task_id_percent::1023 0.003357 # Percentage of cache occupancy per task id 2526system.l2c.tags.occ_task_id_percent::1024 0.779434 # Percentage of cache occupancy per task id 2527system.l2c.tags.tag_accesses 59123537 # Number of tag accesses 2528system.l2c.tags.data_accesses 59123537 # Number of data accesses 2529system.l2c.ReadReq_hits::cpu0.dtb.walker 6743 # number of ReadReq hits 2530system.l2c.ReadReq_hits::cpu0.itb.walker 4986 # number of ReadReq hits 2531system.l2c.ReadReq_hits::cpu0.inst 715760 # number of ReadReq hits 2532system.l2c.ReadReq_hits::cpu0.data 559628 # number of ReadReq hits 2533system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 328609 # number of ReadReq hits 2534system.l2c.ReadReq_hits::cpu1.dtb.walker 6048 # number of ReadReq hits 2535system.l2c.ReadReq_hits::cpu1.itb.walker 4129 # number of ReadReq hits 2536system.l2c.ReadReq_hits::cpu1.inst 682361 # number of ReadReq hits 2537system.l2c.ReadReq_hits::cpu1.data 522413 # number of ReadReq hits 2538system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 303271 # number of ReadReq hits 2539system.l2c.ReadReq_hits::total 3133948 # number of ReadReq hits 2540system.l2c.Writeback_hits::writebacks 2214381 # number of Writeback hits 2541system.l2c.Writeback_hits::total 2214381 # number of Writeback hits 2542system.l2c.WriteInvalidateReq_hits::cpu0.data 145887 # number of WriteInvalidateReq hits 2543system.l2c.WriteInvalidateReq_hits::cpu1.data 132101 # number of WriteInvalidateReq hits 2544system.l2c.WriteInvalidateReq_hits::total 277988 # number of WriteInvalidateReq hits 2545system.l2c.UpgradeReq_hits::cpu0.data 29325 # number of UpgradeReq hits 2546system.l2c.UpgradeReq_hits::cpu1.data 26221 # number of UpgradeReq hits 2547system.l2c.UpgradeReq_hits::total 55546 # number of UpgradeReq hits 2548system.l2c.SCUpgradeReq_hits::cpu0.data 6410 # number of SCUpgradeReq hits 2549system.l2c.SCUpgradeReq_hits::cpu1.data 5303 # number of SCUpgradeReq hits 2550system.l2c.SCUpgradeReq_hits::total 11713 # number of SCUpgradeReq hits 2551system.l2c.ReadExReq_hits::cpu0.data 57124 # number of ReadExReq hits 2552system.l2c.ReadExReq_hits::cpu1.data 48409 # number of ReadExReq hits 2553system.l2c.ReadExReq_hits::total 105533 # number of ReadExReq hits 2554system.l2c.demand_hits::cpu0.dtb.walker 6743 # number of demand (read+write) hits 2555system.l2c.demand_hits::cpu0.itb.walker 4986 # number of demand (read+write) hits 2556system.l2c.demand_hits::cpu0.inst 715760 # number of demand (read+write) hits 2557system.l2c.demand_hits::cpu0.data 616752 # number of demand (read+write) hits 2558system.l2c.demand_hits::cpu0.l2cache.prefetcher 328609 # number of demand (read+write) hits 2559system.l2c.demand_hits::cpu1.dtb.walker 6048 # number of demand (read+write) hits 2560system.l2c.demand_hits::cpu1.itb.walker 4129 # number of demand (read+write) hits 2561system.l2c.demand_hits::cpu1.inst 682361 # number of demand (read+write) hits 2562system.l2c.demand_hits::cpu1.data 570822 # number of demand (read+write) hits 2563system.l2c.demand_hits::cpu1.l2cache.prefetcher 303271 # number of demand (read+write) hits 2564system.l2c.demand_hits::total 3239481 # number of demand (read+write) hits 2565system.l2c.overall_hits::cpu0.dtb.walker 6743 # number of overall hits 2566system.l2c.overall_hits::cpu0.itb.walker 4986 # number of overall hits 2567system.l2c.overall_hits::cpu0.inst 715760 # number of overall hits 2568system.l2c.overall_hits::cpu0.data 616752 # number of overall hits 2569system.l2c.overall_hits::cpu0.l2cache.prefetcher 328609 # number of overall hits 2570system.l2c.overall_hits::cpu1.dtb.walker 6048 # number of overall hits 2571system.l2c.overall_hits::cpu1.itb.walker 4129 # number of overall hits 2572system.l2c.overall_hits::cpu1.inst 682361 # number of overall hits 2573system.l2c.overall_hits::cpu1.data 570822 # number of overall hits 2574system.l2c.overall_hits::cpu1.l2cache.prefetcher 303271 # number of overall hits 2575system.l2c.overall_hits::total 3239481 # number of overall hits 2576system.l2c.ReadReq_misses::cpu0.dtb.walker 1023 # number of ReadReq misses 2577system.l2c.ReadReq_misses::cpu0.itb.walker 1006 # number of ReadReq misses 2578system.l2c.ReadReq_misses::cpu0.inst 70277 # number of ReadReq misses 2579system.l2c.ReadReq_misses::cpu0.data 119509 # number of ReadReq misses 2580system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 168399 # number of ReadReq misses 2581system.l2c.ReadReq_misses::cpu1.dtb.walker 1111 # number of ReadReq misses 2582system.l2c.ReadReq_misses::cpu1.itb.walker 1082 # number of ReadReq misses 2583system.l2c.ReadReq_misses::cpu1.inst 44445 # number of ReadReq misses 2584system.l2c.ReadReq_misses::cpu1.data 78155 # number of ReadReq misses 2585system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 124967 # number of ReadReq misses 2586system.l2c.ReadReq_misses::total 609974 # number of ReadReq misses 2587system.l2c.WriteInvalidateReq_misses::cpu0.data 434854 # number of WriteInvalidateReq misses 2588system.l2c.WriteInvalidateReq_misses::cpu1.data 99438 # number of WriteInvalidateReq misses 2589system.l2c.WriteInvalidateReq_misses::total 534292 # number of WriteInvalidateReq misses 2590system.l2c.UpgradeReq_misses::cpu0.data 45074 # number of UpgradeReq misses 2591system.l2c.UpgradeReq_misses::cpu1.data 42732 # number of UpgradeReq misses 2592system.l2c.UpgradeReq_misses::total 87806 # number of UpgradeReq misses 2593system.l2c.SCUpgradeReq_misses::cpu0.data 9265 # number of SCUpgradeReq misses 2594system.l2c.SCUpgradeReq_misses::cpu1.data 7405 # number of SCUpgradeReq misses 2595system.l2c.SCUpgradeReq_misses::total 16670 # number of SCUpgradeReq misses 2596system.l2c.ReadExReq_misses::cpu0.data 70615 # number of ReadExReq misses 2597system.l2c.ReadExReq_misses::cpu1.data 44107 # number of ReadExReq misses 2598system.l2c.ReadExReq_misses::total 114722 # number of ReadExReq misses 2599system.l2c.demand_misses::cpu0.dtb.walker 1023 # number of demand (read+write) misses 2600system.l2c.demand_misses::cpu0.itb.walker 1006 # number of demand (read+write) misses 2601system.l2c.demand_misses::cpu0.inst 70277 # number of demand (read+write) misses 2602system.l2c.demand_misses::cpu0.data 190124 # number of demand (read+write) misses 2603system.l2c.demand_misses::cpu0.l2cache.prefetcher 168399 # number of demand (read+write) misses 2604system.l2c.demand_misses::cpu1.dtb.walker 1111 # number of demand (read+write) misses 2605system.l2c.demand_misses::cpu1.itb.walker 1082 # number of demand (read+write) misses 2606system.l2c.demand_misses::cpu1.inst 44445 # number of demand (read+write) misses 2607system.l2c.demand_misses::cpu1.data 122262 # number of demand (read+write) misses 2608system.l2c.demand_misses::cpu1.l2cache.prefetcher 124967 # number of demand (read+write) misses 2609system.l2c.demand_misses::total 724696 # number of demand (read+write) misses 2610system.l2c.overall_misses::cpu0.dtb.walker 1023 # number of overall misses 2611system.l2c.overall_misses::cpu0.itb.walker 1006 # number of overall misses 2612system.l2c.overall_misses::cpu0.inst 70277 # number of overall misses 2613system.l2c.overall_misses::cpu0.data 190124 # number of overall misses 2614system.l2c.overall_misses::cpu0.l2cache.prefetcher 168399 # number of overall misses 2615system.l2c.overall_misses::cpu1.dtb.walker 1111 # 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number of ReadReq miss cycles 2628system.l2c.ReadReq_miss_latency::cpu1.inst 3692339104 # number of ReadReq miss cycles 2629system.l2c.ReadReq_miss_latency::cpu1.data 6847833445 # number of ReadReq miss cycles 2630system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 15053704575 # number of ReadReq miss cycles 2631system.l2c.ReadReq_miss_latency::total 64356514464 # number of ReadReq miss cycles 2632system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 50866916 # number of WriteInvalidateReq miss cycles 2633system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 43440127 # number of WriteInvalidateReq miss cycles 2634system.l2c.WriteInvalidateReq_miss_latency::total 94307043 # number of WriteInvalidateReq miss cycles 2635system.l2c.UpgradeReq_miss_latency::cpu0.data 280117177 # number of UpgradeReq miss cycles 2636system.l2c.UpgradeReq_miss_latency::cpu1.data 285028454 # number of UpgradeReq miss cycles 2637system.l2c.UpgradeReq_miss_latency::total 565145631 # number of UpgradeReq miss cycles 2638system.l2c.SCUpgradeReq_miss_latency::cpu0.data 53423811 # number of SCUpgradeReq miss cycles 2639system.l2c.SCUpgradeReq_miss_latency::cpu1.data 47784487 # number of SCUpgradeReq miss cycles 2640system.l2c.SCUpgradeReq_miss_latency::total 101208298 # number of SCUpgradeReq miss cycles 2641system.l2c.ReadExReq_miss_latency::cpu0.data 6307677426 # number of ReadExReq miss cycles 2642system.l2c.ReadExReq_miss_latency::cpu1.data 3604652546 # number of ReadExReq miss cycles 2643system.l2c.ReadExReq_miss_latency::total 9912329972 # number of ReadExReq miss cycles 2644system.l2c.demand_miss_latency::cpu0.dtb.walker 90170503 # number of demand (read+write) miss cycles 2645system.l2c.demand_miss_latency::cpu0.itb.walker 86831257 # number of demand (read+write) miss cycles 2646system.l2c.demand_miss_latency::cpu0.inst 5869737346 # number of demand (read+write) miss cycles 2647system.l2c.demand_miss_latency::cpu0.data 17069216315 # number of demand (read+write) miss cycles 2648system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 21763176095 # number of demand (read+write) miss cycles 2649system.l2c.demand_miss_latency::cpu1.dtb.walker 95166250 # number of demand (read+write) miss cycles 2650system.l2c.demand_miss_latency::cpu1.itb.walker 96017000 # number of demand (read+write) miss cycles 2651system.l2c.demand_miss_latency::cpu1.inst 3692339104 # number of demand (read+write) miss cycles 2652system.l2c.demand_miss_latency::cpu1.data 10452485991 # number of demand (read+write) miss cycles 2653system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 15053704575 # number of demand (read+write) miss cycles 2654system.l2c.demand_miss_latency::total 74268844436 # number of demand (read+write) miss cycles 2655system.l2c.overall_miss_latency::cpu0.dtb.walker 90170503 # number of overall miss cycles 2656system.l2c.overall_miss_latency::cpu0.itb.walker 86831257 # number of overall miss cycles 2657system.l2c.overall_miss_latency::cpu0.inst 5869737346 # number of overall miss cycles 2658system.l2c.overall_miss_latency::cpu0.data 17069216315 # number of overall miss cycles 2659system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 21763176095 # number of overall miss cycles 2660system.l2c.overall_miss_latency::cpu1.dtb.walker 95166250 # number of overall miss cycles 2661system.l2c.overall_miss_latency::cpu1.itb.walker 96017000 # number of overall miss cycles 2662system.l2c.overall_miss_latency::cpu1.inst 3692339104 # number of overall miss cycles 2663system.l2c.overall_miss_latency::cpu1.data 10452485991 # number of overall miss cycles 2664system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 15053704575 # number of overall miss cycles 2665system.l2c.overall_miss_latency::total 74268844436 # number of overall miss cycles 2666system.l2c.ReadReq_accesses::cpu0.dtb.walker 7766 # number of ReadReq accesses(hits+misses) 2667system.l2c.ReadReq_accesses::cpu0.itb.walker 5992 # number of ReadReq accesses(hits+misses) 2668system.l2c.ReadReq_accesses::cpu0.inst 786037 # number of ReadReq accesses(hits+misses) 2669system.l2c.ReadReq_accesses::cpu0.data 679137 # number of ReadReq accesses(hits+misses) 2670system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 497008 # number of ReadReq accesses(hits+misses) 2671system.l2c.ReadReq_accesses::cpu1.dtb.walker 7159 # number of ReadReq accesses(hits+misses) 2672system.l2c.ReadReq_accesses::cpu1.itb.walker 5211 # number of ReadReq accesses(hits+misses) 2673system.l2c.ReadReq_accesses::cpu1.inst 726806 # number of ReadReq accesses(hits+misses) 2674system.l2c.ReadReq_accesses::cpu1.data 600568 # number of ReadReq accesses(hits+misses) 2675system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 428238 # number of ReadReq accesses(hits+misses) 2676system.l2c.ReadReq_accesses::total 3743922 # number of ReadReq accesses(hits+misses) 2677system.l2c.Writeback_accesses::writebacks 2214381 # number of Writeback accesses(hits+misses) 2678system.l2c.Writeback_accesses::total 2214381 # number of Writeback accesses(hits+misses) 2679system.l2c.WriteInvalidateReq_accesses::cpu0.data 580741 # number of WriteInvalidateReq accesses(hits+misses) 2680system.l2c.WriteInvalidateReq_accesses::cpu1.data 231539 # number of WriteInvalidateReq accesses(hits+misses) 2681system.l2c.WriteInvalidateReq_accesses::total 812280 # number of WriteInvalidateReq accesses(hits+misses) 2682system.l2c.UpgradeReq_accesses::cpu0.data 74399 # number of UpgradeReq accesses(hits+misses) 2683system.l2c.UpgradeReq_accesses::cpu1.data 68953 # number of UpgradeReq accesses(hits+misses) 2684system.l2c.UpgradeReq_accesses::total 143352 # number of UpgradeReq accesses(hits+misses) 2685system.l2c.SCUpgradeReq_accesses::cpu0.data 15675 # number of SCUpgradeReq accesses(hits+misses) 2686system.l2c.SCUpgradeReq_accesses::cpu1.data 12708 # number of SCUpgradeReq accesses(hits+misses) 2687system.l2c.SCUpgradeReq_accesses::total 28383 # number of SCUpgradeReq accesses(hits+misses) 2688system.l2c.ReadExReq_accesses::cpu0.data 127739 # number of ReadExReq accesses(hits+misses) 2689system.l2c.ReadExReq_accesses::cpu1.data 92516 # number of ReadExReq accesses(hits+misses) 2690system.l2c.ReadExReq_accesses::total 220255 # number of ReadExReq accesses(hits+misses) 2691system.l2c.demand_accesses::cpu0.dtb.walker 7766 # number of demand (read+write) accesses 2692system.l2c.demand_accesses::cpu0.itb.walker 5992 # number of demand (read+write) accesses 2693system.l2c.demand_accesses::cpu0.inst 786037 # number of demand (read+write) accesses 2694system.l2c.demand_accesses::cpu0.data 806876 # number of demand (read+write) accesses 2695system.l2c.demand_accesses::cpu0.l2cache.prefetcher 497008 # number of demand (read+write) accesses 2696system.l2c.demand_accesses::cpu1.dtb.walker 7159 # number of demand (read+write) accesses 2697system.l2c.demand_accesses::cpu1.itb.walker 5211 # number of demand (read+write) accesses 2698system.l2c.demand_accesses::cpu1.inst 726806 # number of demand (read+write) accesses 2699system.l2c.demand_accesses::cpu1.data 693084 # number of demand (read+write) accesses 2700system.l2c.demand_accesses::cpu1.l2cache.prefetcher 428238 # number of demand (read+write) accesses 2701system.l2c.demand_accesses::total 3964177 # number of demand (read+write) accesses 2702system.l2c.overall_accesses::cpu0.dtb.walker 7766 # number of overall (read+write) accesses 2703system.l2c.overall_accesses::cpu0.itb.walker 5992 # number of overall (read+write) accesses 2704system.l2c.overall_accesses::cpu0.inst 786037 # number of overall (read+write) accesses 2705system.l2c.overall_accesses::cpu0.data 806876 # number of overall (read+write) accesses 2706system.l2c.overall_accesses::cpu0.l2cache.prefetcher 497008 # number of overall (read+write) accesses 2707system.l2c.overall_accesses::cpu1.dtb.walker 7159 # number of overall (read+write) accesses 2708system.l2c.overall_accesses::cpu1.itb.walker 5211 # number of overall (read+write) accesses 2709system.l2c.overall_accesses::cpu1.inst 726806 # number of overall (read+write) accesses 2710system.l2c.overall_accesses::cpu1.data 693084 # number of overall (read+write) accesses 2711system.l2c.overall_accesses::cpu1.l2cache.prefetcher 428238 # number of overall (read+write) accesses 2712system.l2c.overall_accesses::total 3964177 # number of overall (read+write) accesses 2713system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.131728 # miss rate for ReadReq accesses 2714system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.167891 # miss rate for ReadReq accesses 2715system.l2c.ReadReq_miss_rate::cpu0.inst 0.089407 # miss rate for ReadReq accesses 2716system.l2c.ReadReq_miss_rate::cpu0.data 0.175972 # miss rate for ReadReq accesses 2717system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.338826 # miss rate for ReadReq accesses 2718system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.155189 # miss rate for ReadReq accesses 2719system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.207638 # miss rate for ReadReq accesses 2720system.l2c.ReadReq_miss_rate::cpu1.inst 0.061151 # miss rate for ReadReq accesses 2721system.l2c.ReadReq_miss_rate::cpu1.data 0.130135 # miss rate for ReadReq accesses 2722system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.291817 # miss rate for ReadReq accesses 2723system.l2c.ReadReq_miss_rate::total 0.162924 # miss rate for ReadReq accesses 2724system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.748792 # miss rate for WriteInvalidateReq accesses 2725system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.429465 # miss rate for WriteInvalidateReq accesses 2726system.l2c.WriteInvalidateReq_miss_rate::total 0.657768 # miss rate for WriteInvalidateReq accesses 2727system.l2c.UpgradeReq_miss_rate::cpu0.data 0.605841 # miss rate for UpgradeReq accesses 2728system.l2c.UpgradeReq_miss_rate::cpu1.data 0.619726 # miss rate for UpgradeReq accesses 2729system.l2c.UpgradeReq_miss_rate::total 0.612520 # miss rate for UpgradeReq accesses 2730system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.591069 # miss rate for SCUpgradeReq accesses 2731system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.582704 # miss rate for SCUpgradeReq accesses 2732system.l2c.SCUpgradeReq_miss_rate::total 0.587323 # miss rate for SCUpgradeReq accesses 2733system.l2c.ReadExReq_miss_rate::cpu0.data 0.552807 # miss rate for ReadExReq accesses 2734system.l2c.ReadExReq_miss_rate::cpu1.data 0.476750 # miss rate for ReadExReq accesses 2735system.l2c.ReadExReq_miss_rate::total 0.520860 # miss rate for ReadExReq accesses 2736system.l2c.demand_miss_rate::cpu0.dtb.walker 0.131728 # miss rate for demand accesses 2737system.l2c.demand_miss_rate::cpu0.itb.walker 0.167891 # miss rate for demand accesses 2738system.l2c.demand_miss_rate::cpu0.inst 0.089407 # miss rate for demand accesses 2739system.l2c.demand_miss_rate::cpu0.data 0.235630 # miss rate for demand accesses 2740system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.338826 # miss rate for demand accesses 2741system.l2c.demand_miss_rate::cpu1.dtb.walker 0.155189 # miss rate for demand accesses 2742system.l2c.demand_miss_rate::cpu1.itb.walker 0.207638 # miss rate for demand accesses 2743system.l2c.demand_miss_rate::cpu1.inst 0.061151 # miss rate for demand accesses 2744system.l2c.demand_miss_rate::cpu1.data 0.176403 # miss rate for demand accesses 2745system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.291817 # miss rate for demand accesses 2746system.l2c.demand_miss_rate::total 0.182811 # miss rate for demand accesses 2747system.l2c.overall_miss_rate::cpu0.dtb.walker 0.131728 # miss rate for overall accesses 2748system.l2c.overall_miss_rate::cpu0.itb.walker 0.167891 # miss rate for overall accesses 2749system.l2c.overall_miss_rate::cpu0.inst 0.089407 # miss rate for overall accesses 2750system.l2c.overall_miss_rate::cpu0.data 0.235630 # miss rate for overall accesses 2751system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.338826 # miss rate for overall accesses 2752system.l2c.overall_miss_rate::cpu1.dtb.walker 0.155189 # miss rate for overall accesses 2753system.l2c.overall_miss_rate::cpu1.itb.walker 0.207638 # miss rate for overall accesses 2754system.l2c.overall_miss_rate::cpu1.inst 0.061151 # miss rate for overall accesses 2755system.l2c.overall_miss_rate::cpu1.data 0.176403 # miss rate for overall accesses 2756system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.291817 # miss rate for overall accesses 2757system.l2c.overall_miss_rate::total 0.182811 # miss rate for overall accesses 2758system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 88143.209189 # average ReadReq miss latency 2759system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 86313.376740 # average ReadReq miss latency 2760system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83522.878694 # average ReadReq miss latency 2761system.l2c.ReadReq_avg_miss_latency::cpu0.data 90047.936883 # average ReadReq miss latency 2762system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 129235.779874 # average ReadReq miss latency 2763system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 85658.190819 # average ReadReq miss latency 2764system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 88740.295749 # average ReadReq miss latency 2765system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83076.591383 # average ReadReq miss latency 2766system.l2c.ReadReq_avg_miss_latency::cpu1.data 87618.622545 # average ReadReq miss latency 2767system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 120461.438420 # average ReadReq miss latency 2768system.l2c.ReadReq_avg_miss_latency::total 105506.979747 # average ReadReq miss latency 2769system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 116.974700 # average WriteInvalidateReq miss latency 2770system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 436.856403 # average WriteInvalidateReq miss latency 2771system.l2c.WriteInvalidateReq_avg_miss_latency::total 176.508432 # average WriteInvalidateReq miss latency 2772system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6214.606580 # average UpgradeReq miss latency 2773system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6670.140738 # average UpgradeReq miss latency 2774system.l2c.UpgradeReq_avg_miss_latency::total 6436.298556 # average UpgradeReq miss latency 2775system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5766.196546 # average SCUpgradeReq miss latency 2776system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6453.002971 # average SCUpgradeReq miss latency 2777system.l2c.SCUpgradeReq_avg_miss_latency::total 6071.283623 # average SCUpgradeReq miss latency 2778system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89324.894512 # average ReadExReq miss latency 2779system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81725.180720 # average ReadExReq miss latency 2780system.l2c.ReadExReq_avg_miss_latency::total 86403.043636 # average ReadExReq miss latency 2781system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88143.209189 # average overall miss latency 2782system.l2c.demand_avg_miss_latency::cpu0.itb.walker 86313.376740 # average overall miss latency 2783system.l2c.demand_avg_miss_latency::cpu0.inst 83522.878694 # average overall miss latency 2784system.l2c.demand_avg_miss_latency::cpu0.data 89779.387742 # average overall miss latency 2785system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 129235.779874 # average overall miss latency 2786system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85658.190819 # average overall miss latency 2787system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88740.295749 # average overall miss latency 2788system.l2c.demand_avg_miss_latency::cpu1.inst 83076.591383 # average overall miss latency 2789system.l2c.demand_avg_miss_latency::cpu1.data 85492.515998 # average overall miss latency 2790system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 120461.438420 # average overall miss latency 2791system.l2c.demand_avg_miss_latency::total 102482.757509 # average overall miss latency 2792system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88143.209189 # average overall miss latency 2793system.l2c.overall_avg_miss_latency::cpu0.itb.walker 86313.376740 # average overall miss latency 2794system.l2c.overall_avg_miss_latency::cpu0.inst 83522.878694 # average overall miss latency 2795system.l2c.overall_avg_miss_latency::cpu0.data 89779.387742 # average overall miss latency 2796system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 129235.779874 # average overall miss latency 2797system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85658.190819 # average overall miss latency 2798system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88740.295749 # average overall miss latency 2799system.l2c.overall_avg_miss_latency::cpu1.inst 83076.591383 # average overall miss latency 2800system.l2c.overall_avg_miss_latency::cpu1.data 85492.515998 # average overall miss latency 2801system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 120461.438420 # average overall miss latency 2802system.l2c.overall_avg_miss_latency::total 102482.757509 # average overall miss latency 2803system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 2777system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked | 2804system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 2778system.l2c.blocked::no_mshrs 8 # number of cycles access was blocked | 2805system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked |
| 2779system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 2806system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 2780system.l2c.avg_blocked_cycles::no_mshrs 106.875000 # average number of cycles each access was blocked | 2807system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 2781system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2782system.l2c.fast_writes 0 # number of fast writes performed 2783system.l2c.cache_copies 0 # number of cache copies performed | 2808system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2809system.l2c.fast_writes 0 # number of fast writes performed 2810system.l2c.cache_copies 0 # number of cache copies performed |
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number of demand (read+write) MSHR miss cycles 2921system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 13516096621 # number of demand (read+write) MSHR miss cycles 2922system.l2c.demand_mshr_miss_latency::total 65241494660 # number of demand (read+write) MSHR miss cycles 2923system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 77296003 # number of overall MSHR miss cycles 2924system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 74149743 # number of overall MSHR miss cycles 2925system.l2c.overall_mshr_miss_latency::cpu0.inst 4978677404 # number of overall MSHR miss cycles 2926system.l2c.overall_mshr_miss_latency::cpu0.data 14688498935 # number of overall MSHR miss cycles 2927system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 19697035299 # number of overall MSHR miss cycles 2928system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 81192250 # number of overall MSHR miss cycles 2929system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 82396000 # number of overall MSHR miss cycles 2930system.l2c.overall_mshr_miss_latency::cpu1.inst 3126135146 # number of overall MSHR miss cycles 2931system.l2c.overall_mshr_miss_latency::cpu1.data 8920017259 # number of overall MSHR miss cycles 2932system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 13516096621 # number of overall MSHR miss cycles 2933system.l2c.overall_mshr_miss_latency::total 65241494660 # number of overall MSHR miss cycles |
| 2891system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3188012750 # number of ReadReq MSHR uncacheable cycles | 2934system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3188012750 # number of ReadReq MSHR uncacheable cycles |
| 2892system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5001418750 # number of ReadReq MSHR uncacheable cycles 2893system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5293500 # number of ReadReq MSHR uncacheable cycles 2894system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 377070000 # number of ReadReq MSHR uncacheable cycles 2895system.l2c.ReadReq_mshr_uncacheable_latency::total 8571795000 # number of ReadReq MSHR uncacheable cycles 2896system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4829205000 # number of WriteReq MSHR uncacheable cycles 2897system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 452800000 # number of WriteReq MSHR uncacheable cycles 2898system.l2c.WriteReq_mshr_uncacheable_latency::total 5282005000 # number of WriteReq MSHR uncacheable cycles | 2935system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5000535750 # number of ReadReq MSHR uncacheable cycles 2936system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5725000 # number of ReadReq MSHR uncacheable cycles 2937system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 377455500 # number of ReadReq MSHR uncacheable cycles 2938system.l2c.ReadReq_mshr_uncacheable_latency::total 8571729000 # number of ReadReq MSHR uncacheable cycles 2939system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4829727000 # number of WriteReq MSHR uncacheable cycles 2940system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 450782500 # number of WriteReq MSHR uncacheable cycles 2941system.l2c.WriteReq_mshr_uncacheable_latency::total 5280509500 # number of WriteReq MSHR uncacheable cycles |
| 2899system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3188012750 # number of overall MSHR uncacheable cycles | 2942system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3188012750 # number of overall MSHR uncacheable cycles |
| 2900system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9830623750 # number of overall MSHR uncacheable cycles 2901system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5293500 # number of overall MSHR uncacheable cycles 2902system.l2c.overall_mshr_uncacheable_latency::cpu1.data 829870000 # number of overall MSHR uncacheable cycles 2903system.l2c.overall_mshr_uncacheable_latency::total 13853800000 # number of overall MSHR uncacheable cycles 2904system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.216303 # mshr miss rate for ReadReq accesses 2905system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.230782 # mshr miss rate for ReadReq accesses 2906system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.091193 # mshr miss rate for ReadReq accesses 2907system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.191218 # mshr miss rate for ReadReq accesses 2908system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.411518 # mshr miss rate for ReadReq accesses 2909system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.268602 # mshr miss rate for ReadReq accesses 2910system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.357702 # mshr miss rate for ReadReq accesses 2911system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.073657 # mshr miss rate for ReadReq accesses 2912system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.184765 # mshr miss rate for ReadReq accesses 2913system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.408764 # mshr miss rate for ReadReq accesses 2914system.l2c.ReadReq_mshr_miss_rate::total 0.204495 # mshr miss rate for ReadReq accesses 2915system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.770297 # mshr miss rate for WriteInvalidateReq accesses 2916system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.464517 # mshr miss rate for WriteInvalidateReq accesses 2917system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.677367 # mshr miss rate for WriteInvalidateReq accesses 2918system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.607754 # mshr miss rate for UpgradeReq accesses 2919system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.616874 # mshr miss rate for UpgradeReq accesses 2920system.l2c.UpgradeReq_mshr_miss_rate::total 0.612228 # mshr miss rate for UpgradeReq accesses 2921system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.604953 # mshr miss rate for SCUpgradeReq accesses 2922system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.591376 # mshr miss rate for SCUpgradeReq accesses 2923system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.598113 # mshr miss rate for SCUpgradeReq accesses 2924system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.590095 # mshr miss rate for ReadExReq accesses 2925system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.517982 # mshr miss rate for ReadExReq accesses 2926system.l2c.ReadExReq_mshr_miss_rate::total 0.557864 # mshr miss rate for ReadExReq accesses 2927system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.216303 # mshr miss rate for demand accesses 2928system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.230782 # mshr miss rate for demand accesses 2929system.l2c.demand_mshr_miss_rate::cpu0.inst 0.091193 # mshr miss rate for demand accesses 2930system.l2c.demand_mshr_miss_rate::cpu0.data 0.255653 # mshr miss rate for demand accesses 2931system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.411518 # mshr miss rate for demand accesses 2932system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.268602 # mshr miss rate for demand accesses 2933system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.357702 # mshr miss rate for demand accesses 2934system.l2c.demand_mshr_miss_rate::cpu1.inst 0.073657 # mshr miss rate for demand accesses 2935system.l2c.demand_mshr_miss_rate::cpu1.data 0.227758 # mshr miss rate for demand accesses 2936system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.408764 # mshr miss rate for demand accesses 2937system.l2c.demand_mshr_miss_rate::total 0.224210 # mshr miss rate for demand accesses 2938system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.216303 # mshr miss rate for overall accesses 2939system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.230782 # mshr miss rate for overall accesses 2940system.l2c.overall_mshr_miss_rate::cpu0.inst 0.091193 # mshr miss rate for overall accesses 2941system.l2c.overall_mshr_miss_rate::cpu0.data 0.255653 # mshr miss rate for overall accesses 2942system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.411518 # mshr miss rate for overall accesses 2943system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.268602 # mshr miss rate for overall accesses 2944system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.357702 # mshr miss rate for overall accesses 2945system.l2c.overall_mshr_miss_rate::cpu1.inst 0.073657 # mshr miss rate for overall accesses 2946system.l2c.overall_mshr_miss_rate::cpu1.data 0.227758 # mshr miss rate for overall accesses 2947system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.408764 # mshr miss rate for overall accesses 2948system.l2c.overall_mshr_miss_rate::total 0.224210 # mshr miss rate for overall accesses 2949system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 79836.475372 # average ReadReq mshr miss latency 2950system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 80621.856844 # average ReadReq mshr miss latency 2951system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72130.959523 # average ReadReq mshr miss latency 2952system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 80558.829037 # average ReadReq mshr miss latency 2953system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120952.546963 # average ReadReq mshr miss latency 2954system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75810.996141 # average ReadReq mshr miss latency 2955system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 74913.235449 # average ReadReq mshr miss latency 2956system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71473.621548 # average ReadReq mshr miss latency 2957system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76617.147137 # average ReadReq mshr miss latency 2958system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115363.832721 # average ReadReq mshr miss latency 2959system.l2c.ReadReq_avg_mshr_miss_latency::total 97889.611530 # average ReadReq mshr miss latency 2960system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33579.020650 # average WriteInvalidateReq mshr miss latency 2961system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32048.054457 # average WriteInvalidateReq mshr miss latency 2962system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33259.945559 # average WriteInvalidateReq mshr miss latency 2963system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17817.885507 # average UpgradeReq mshr miss latency 2964system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17791.659815 # average UpgradeReq mshr miss latency 2965system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17804.923446 # average UpgradeReq mshr miss latency 2966system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17847.137919 # average SCUpgradeReq mshr miss latency 2967system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17802.416206 # average SCUpgradeReq mshr miss latency 2968system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17824.861169 # average SCUpgradeReq mshr miss latency 2969system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76873.835674 # average ReadExReq mshr miss latency 2970system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71448.956603 # average ReadExReq mshr miss latency 2971system.l2c.ReadExReq_avg_mshr_miss_latency::total 74622.497967 # average ReadExReq mshr miss latency 2972system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 79836.475372 # average overall mshr miss latency 2973system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80621.856844 # average overall mshr miss latency 2974system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72130.959523 # average overall mshr miss latency 2975system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79184.818080 # average overall mshr miss latency 2976system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120952.546963 # average overall mshr miss latency 2977system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75810.996141 # average overall mshr miss latency 2978system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 74913.235449 # average overall mshr miss latency 2979system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71473.621548 # average overall mshr miss latency 2980system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75100.646101 # average overall mshr miss latency 2981system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115363.832721 # average overall mshr miss latency 2982system.l2c.demand_avg_mshr_miss_latency::total 94659.804929 # average overall mshr miss latency 2983system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 79836.475372 # average overall mshr miss latency 2984system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80621.856844 # average overall mshr miss latency 2985system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72130.959523 # average overall mshr miss latency 2986system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79184.818080 # average overall mshr miss latency 2987system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 120952.546963 # average overall mshr miss latency 2988system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75810.996141 # average overall mshr miss latency 2989system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 74913.235449 # average overall mshr miss latency 2990system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71473.621548 # average overall mshr miss latency 2991system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75100.646101 # average overall mshr miss latency 2992system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 115363.832721 # average overall mshr miss latency 2993system.l2c.overall_avg_mshr_miss_latency::total 94659.804929 # average overall mshr miss latency 2994system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 2995system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 2996system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 2997system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 2998system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 2999system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 3000system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 3001system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 3002system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 3003system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 3004system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 3005system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 3006system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 2943system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9830262750 # number of overall MSHR uncacheable cycles 2944system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5725000 # number of overall MSHR uncacheable cycles 2945system.l2c.overall_mshr_uncacheable_latency::cpu1.data 828238000 # number of overall MSHR uncacheable cycles 2946system.l2c.overall_mshr_uncacheable_latency::total 13852238500 # number of overall MSHR uncacheable cycles 2947system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.131728 # mshr miss rate for ReadReq accesses 2948system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.167891 # mshr miss rate for ReadReq accesses 2949system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.089190 # mshr miss rate for ReadReq accesses 2950system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.175937 # mshr miss rate for ReadReq accesses 2951system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.338826 # mshr miss rate for ReadReq accesses 2952system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.155189 # mshr miss rate for ReadReq accesses 2953system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.207638 # mshr miss rate for ReadReq accesses 2954system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.060953 # mshr miss rate for ReadReq accesses 2955system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.130100 # mshr miss rate for ReadReq accesses 2956system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.291814 # mshr miss rate for ReadReq accesses 2957system.l2c.ReadReq_mshr_miss_rate::total 0.162828 # mshr miss rate for ReadReq accesses 2958system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.748792 # mshr miss rate for WriteInvalidateReq accesses 2959system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.429465 # mshr miss rate for WriteInvalidateReq accesses 2960system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.657768 # mshr miss rate for WriteInvalidateReq accesses 2961system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.605841 # mshr miss rate for UpgradeReq accesses 2962system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.619726 # mshr miss rate for UpgradeReq accesses 2963system.l2c.UpgradeReq_mshr_miss_rate::total 0.612520 # mshr miss rate for UpgradeReq accesses 2964system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.591069 # mshr miss rate for SCUpgradeReq accesses 2965system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.582704 # mshr miss rate for SCUpgradeReq accesses 2966system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.587323 # mshr miss rate for SCUpgradeReq accesses 2967system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.552807 # mshr miss rate for ReadExReq accesses 2968system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.476750 # mshr miss rate for ReadExReq accesses 2969system.l2c.ReadExReq_mshr_miss_rate::total 0.520860 # mshr miss rate for ReadExReq accesses 2970system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.131728 # mshr miss rate for demand accesses 2971system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.167891 # mshr miss rate for demand accesses 2972system.l2c.demand_mshr_miss_rate::cpu0.inst 0.089190 # mshr miss rate for demand accesses 2973system.l2c.demand_mshr_miss_rate::cpu0.data 0.235600 # mshr miss rate for demand accesses 2974system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.338826 # mshr miss rate for demand accesses 2975system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.155189 # mshr miss rate for demand accesses 2976system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.207638 # mshr miss rate for demand accesses 2977system.l2c.demand_mshr_miss_rate::cpu1.inst 0.060953 # mshr miss rate for demand accesses 2978system.l2c.demand_mshr_miss_rate::cpu1.data 0.176373 # mshr miss rate for demand accesses 2979system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.291814 # mshr miss rate for demand accesses 2980system.l2c.demand_mshr_miss_rate::total 0.182720 # mshr miss rate for demand accesses 2981system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.131728 # mshr miss rate for overall accesses 2982system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.167891 # mshr miss rate for overall accesses 2983system.l2c.overall_mshr_miss_rate::cpu0.inst 0.089190 # mshr miss rate for overall accesses 2984system.l2c.overall_mshr_miss_rate::cpu0.data 0.235600 # mshr miss rate for overall accesses 2985system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.338826 # mshr miss rate for overall accesses 2986system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.155189 # mshr miss rate for overall accesses 2987system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.207638 # mshr miss rate for overall accesses 2988system.l2c.overall_mshr_miss_rate::cpu1.inst 0.060953 # mshr miss rate for overall accesses 2989system.l2c.overall_mshr_miss_rate::cpu1.data 0.176373 # mshr miss rate for overall accesses 2990system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.291814 # mshr miss rate for overall accesses 2991system.l2c.overall_mshr_miss_rate::total 0.182720 # mshr miss rate for overall accesses 2992system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 75558.165200 # average ReadReq mshr miss latency 2993system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 73707.498012 # average ReadReq mshr miss latency 2994system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71015.410786 # average ReadReq mshr miss latency 2995system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 77530.939959 # average ReadReq mshr miss latency 2996system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116966.462384 # average ReadReq mshr miss latency 2997system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73080.333033 # average ReadReq mshr miss latency 2998system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76151.571165 # average ReadReq mshr miss latency 2999system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70565.791878 # average ReadReq mshr miss latency 3000system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75096.383201 # average ReadReq mshr miss latency 3001system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108158.191996 # average ReadReq mshr miss latency 3002system.l2c.ReadReq_avg_mshr_miss_latency::total 93115.223128 # average ReadReq mshr miss latency 3003system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33593.299323 # average WriteInvalidateReq mshr miss latency 3004system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31988.946630 # average WriteInvalidateReq mshr miss latency 3005system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33294.710494 # average WriteInvalidateReq mshr miss latency 3006system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17811.639681 # average UpgradeReq mshr miss latency 3007system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17792.369934 # average UpgradeReq mshr miss latency 3008system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17802.261793 # average UpgradeReq mshr miss latency 3009system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17820.316999 # average SCUpgradeReq mshr miss latency 3010system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17806.465496 # average SCUpgradeReq mshr miss latency 3011system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17814.164007 # average SCUpgradeReq mshr miss latency 3012system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76820.995171 # average ReadExReq mshr miss latency 3013system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69205.261160 # average ReadExReq mshr miss latency 3014system.l2c.ReadExReq_avg_mshr_miss_latency::total 73892.985025 # average ReadExReq mshr miss latency 3015system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75558.165200 # average overall mshr miss latency 3016system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73707.498012 # average overall mshr miss latency 3017system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71015.410786 # average overall mshr miss latency 3018system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77267.222173 # average overall mshr miss latency 3019system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116966.462384 # average overall mshr miss latency 3020system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73080.333033 # average overall mshr miss latency 3021system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76151.571165 # average overall mshr miss latency 3022system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70565.791878 # average overall mshr miss latency 3023system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72970.748431 # average overall mshr miss latency 3024system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108158.191996 # average overall mshr miss latency 3025system.l2c.demand_avg_mshr_miss_latency::total 90070.760890 # average overall mshr miss latency 3026system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75558.165200 # average overall mshr miss latency 3027system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73707.498012 # average overall mshr miss latency 3028system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71015.410786 # average overall mshr miss latency 3029system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77267.222173 # average overall mshr miss latency 3030system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116966.462384 # average overall mshr miss latency 3031system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73080.333033 # average overall mshr miss latency 3032system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76151.571165 # average overall mshr miss latency 3033system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70565.791878 # average overall mshr miss latency 3034system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72970.748431 # average overall mshr miss latency 3035system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108158.191996 # average overall mshr miss latency 3036system.l2c.overall_avg_mshr_miss_latency::total 90070.760890 # average overall mshr miss latency 3037system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60948.109240 # average ReadReq mshr uncacheable latency 3038system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 150351.356024 # average ReadReq mshr uncacheable latency 3039system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63611.111111 # average ReadReq mshr uncacheable latency 3040system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 74287.640228 # average ReadReq mshr uncacheable latency 3041system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 94467.846634 # average ReadReq mshr uncacheable latency 3042system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 145636.010011 # average WriteReq mshr uncacheable latency 3043system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 88614.605858 # average WriteReq mshr uncacheable latency 3044system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138052.535948 # average WriteReq mshr uncacheable latency 3045system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60948.109240 # average overall mshr uncacheable latency 3046system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 147997.090572 # average overall mshr uncacheable latency 3047system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63611.111111 # average overall mshr uncacheable latency 3048system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81455.350118 # average overall mshr uncacheable latency 3049system.l2c.overall_avg_mshr_uncacheable_latency::total 107392.516300 # average overall mshr uncacheable latency |
| 3007system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 3050system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate |
| 3008system.membus.trans_dist::ReadReq 921958 # Transaction distribution 3009system.membus.trans_dist::ReadResp 921958 # Transaction distribution 3010system.membus.trans_dist::WriteReq 38330 # Transaction distribution 3011system.membus.trans_dist::WriteResp 38330 # Transaction distribution 3012system.membus.trans_dist::Writeback 1184105 # Transaction distribution 3013system.membus.trans_dist::WriteInvalidateReq 663691 # Transaction distribution 3014system.membus.trans_dist::WriteInvalidateResp 663691 # Transaction distribution 3015system.membus.trans_dist::UpgradeReq 435500 # Transaction distribution 3016system.membus.trans_dist::SCUpgradeReq 292205 # Transaction distribution 3017system.membus.trans_dist::UpgradeResp 115129 # Transaction distribution 3018system.membus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution 3019system.membus.trans_dist::ReadExReq 144960 # Transaction distribution 3020system.membus.trans_dist::ReadExResp 128452 # Transaction distribution 3021system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122846 # Packet count per connected master and slave (bytes) | 3051system.membus.trans_dist::ReadReq 709274 # Transaction distribution 3052system.membus.trans_dist::ReadResp 709274 # Transaction distribution 3053system.membus.trans_dist::WriteReq 38250 # Transaction distribution 3054system.membus.trans_dist::WriteResp 38250 # Transaction distribution 3055system.membus.trans_dist::Writeback 981258 # Transaction distribution 3056system.membus.trans_dist::WriteInvalidateReq 638260 # Transaction distribution 3057system.membus.trans_dist::WriteInvalidateResp 638259 # Transaction distribution 3058system.membus.trans_dist::UpgradeReq 441618 # Transaction distribution 3059system.membus.trans_dist::SCUpgradeReq 290995 # Transaction distribution 3060system.membus.trans_dist::UpgradeResp 111840 # Transaction distribution 3061system.membus.trans_dist::SCUpgradeFailReq 38 # Transaction distribution 3062system.membus.trans_dist::ReadExReq 127489 # Transaction distribution 3063system.membus.trans_dist::ReadExResp 110378 # Transaction distribution 3064system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122858 # Packet count per connected master and slave (bytes) |
| 3022system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) | 3065system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) |
| 3023system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25278 # Packet count per connected master and slave (bytes) 3024system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5060662 # Packet count per connected master and slave (bytes) 3025system.membus.pkt_count_system.l2c.mem_side::total 5208838 # Packet count per connected master and slave (bytes) 3026system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336578 # Packet count per connected master and slave (bytes) 3027system.membus.pkt_count_system.iocache.mem_side::total 336578 # Packet count per connected master and slave (bytes) 3028system.membus.pkt_count::total 5545416 # Packet count per connected master and slave (bytes) 3029system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155884 # Cumulative packet size per connected master and slave (bytes) | 3066system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25102 # Packet count per connected master and slave (bytes) 3067system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4347669 # Packet count per connected master and slave (bytes) 3068system.membus.pkt_count_system.l2c.mem_side::total 4495681 # Packet count per connected master and slave (bytes) 3069system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336711 # Packet count per connected master and slave (bytes) 3070system.membus.pkt_count_system.iocache.mem_side::total 336711 # Packet count per connected master and slave (bytes) 3071system.membus.pkt_count::total 4832392 # Packet count per connected master and slave (bytes) 3072system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155896 # Cumulative packet size per connected master and slave (bytes) |
| 3030system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) | 3073system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) |
| 3031system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50556 # Cumulative packet size per connected master and slave (bytes) 3032system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 168740232 # Cumulative packet size per connected master and slave (bytes) 3033system.membus.pkt_size_system.l2c.mem_side::total 168947996 # Cumulative packet size per connected master and slave (bytes) 3034system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14122752 # Cumulative packet size per connected master and slave (bytes) 3035system.membus.pkt_size_system.iocache.mem_side::total 14122752 # Cumulative packet size per connected master and slave (bytes) 3036system.membus.pkt_size::total 183070748 # Cumulative packet size per connected master and slave (bytes) 3037system.membus.snoops 632037 # Total snoops (count) 3038system.membus.snoop_fanout::samples 3551920 # Request fanout histogram | 3074system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50204 # Cumulative packet size per connected master and slave (bytes) 3075system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 139364352 # Cumulative packet size per connected master and slave (bytes) 3076system.membus.pkt_size_system.l2c.mem_side::total 139571776 # Cumulative packet size per connected master and slave (bytes) 3077system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14131264 # Cumulative packet size per connected master and slave (bytes) 3078system.membus.pkt_size_system.iocache.mem_side::total 14131264 # Cumulative packet size per connected master and slave (bytes) 3079system.membus.pkt_size::total 153703040 # Cumulative packet size per connected master and slave (bytes) 3080system.membus.snoops 640714 # Total snoops (count) 3081system.membus.snoop_fanout::samples 3227461 # Request fanout histogram |
| 3039system.membus.snoop_fanout::mean 1 # Request fanout histogram 3040system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3041system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3042system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 3082system.membus.snoop_fanout::mean 1 # Request fanout histogram 3083system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3084system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3085system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 3043system.membus.snoop_fanout::1 3551920 100.00% 100.00% # Request fanout histogram | 3086system.membus.snoop_fanout::1 3227461 100.00% 100.00% # Request fanout histogram |
| 3044system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3045system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3046system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3047system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 3087system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3088system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3089system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3090system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 3048system.membus.snoop_fanout::total 3551920 # Request fanout histogram 3049system.membus.reqLayer0.occupancy 109974000 # Layer occupancy (ticks) | 3091system.membus.snoop_fanout::total 3227461 # Request fanout histogram 3092system.membus.reqLayer0.occupancy 110051499 # Layer occupancy (ticks) |
| 3050system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3051system.membus.reqLayer1.occupancy 33484 # Layer occupancy (ticks) 3052system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 3093system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3094system.membus.reqLayer1.occupancy 33484 # Layer occupancy (ticks) 3095system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 3053system.membus.reqLayer2.occupancy 21181500 # Layer occupancy (ticks) | 3096system.membus.reqLayer2.occupancy 20984500 # Layer occupancy (ticks) |
| 3054system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 3097system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 3055system.membus.reqLayer5.occupancy 10917620106 # Layer occupancy (ticks) | 3098system.membus.reqLayer5.occupancy 9462597488 # Layer occupancy (ticks) |
| 3056system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) | 3099system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) |
| 3057system.membus.respLayer2.occupancy 6186347625 # Layer occupancy (ticks) | 3100system.membus.respLayer2.occupancy 4943193797 # Layer occupancy (ticks) |
| 3058system.membus.respLayer2.utilization 0.0 # Layer utilization (%) | 3101system.membus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 3059system.membus.respLayer3.occupancy 152234718 # Layer occupancy (ticks) | 3102system.membus.respLayer3.occupancy 152223017 # Layer occupancy (ticks) |
| 3060system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3061system.realview.ethernet.txBytes 966 # Bytes Transmitted 3062system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3063system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3064system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3065system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3066system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3067system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA --- 27 unchanged lines hidden (view full) --- 3095system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3096system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3097system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3098system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3099system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3100system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3101system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3102system.realview.ethernet.droppedPackets 0 # number of packets dropped | 3103system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3104system.realview.ethernet.txBytes 966 # Bytes Transmitted 3105system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3106system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3107system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3108system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3109system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3110system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA --- 27 unchanged lines hidden (view full) --- 3138system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3139system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3140system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3141system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3142system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3143system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3144system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3145system.realview.ethernet.droppedPackets 0 # number of packets dropped |
| 3103system.toL2Bus.trans_dist::ReadReq 4966231 # Transaction distribution 3104system.toL2Bus.trans_dist::ReadResp 4959010 # Transaction distribution 3105system.toL2Bus.trans_dist::WriteReq 38330 # Transaction distribution 3106system.toL2Bus.trans_dist::WriteResp 38330 # Transaction distribution 3107system.toL2Bus.trans_dist::Writeback 2396374 # Transaction distribution 3108system.toL2Bus.trans_dist::WriteInvalidateReq 933256 # Transaction distribution 3109system.toL2Bus.trans_dist::WriteInvalidateResp 826108 # Transaction distribution 3110system.toL2Bus.trans_dist::UpgradeReq 485771 # Transaction distribution 3111system.toL2Bus.trans_dist::SCUpgradeReq 304174 # Transaction distribution 3112system.toL2Bus.trans_dist::UpgradeResp 789945 # Transaction distribution 3113system.toL2Bus.trans_dist::SCUpgradeFailReq 119 # Transaction distribution 3114system.toL2Bus.trans_dist::UpgradeFailResp 119 # Transaction distribution 3115system.toL2Bus.trans_dist::ReadExReq 295867 # Transaction distribution 3116system.toL2Bus.trans_dist::ReadExResp 295867 # Transaction distribution 3117system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7796872 # Packet count per connected master and slave (bytes) 3118system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6899953 # Packet count per connected master and slave (bytes) 3119system.toL2Bus.pkt_count::total 14696825 # Packet count per connected master and slave (bytes) 3120system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 260005833 # Cumulative packet size per connected master and slave (bytes) 3121system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 222466259 # Cumulative packet size per connected master and slave (bytes) 3122system.toL2Bus.pkt_size::total 482472092 # Cumulative packet size per connected master and slave (bytes) 3123system.toL2Bus.snoops 1634381 # Total snoops (count) 3124system.toL2Bus.snoop_fanout::samples 9291173 # Request fanout histogram 3125system.toL2Bus.snoop_fanout::mean 1.012493 # Request fanout histogram 3126system.toL2Bus.snoop_fanout::stdev 0.111071 # Request fanout histogram | 3146system.toL2Bus.trans_dist::ReadReq 4701983 # Transaction distribution 3147system.toL2Bus.trans_dist::ReadResp 4694752 # Transaction distribution 3148system.toL2Bus.trans_dist::WriteReq 38250 # Transaction distribution 3149system.toL2Bus.trans_dist::WriteResp 38250 # Transaction distribution 3150system.toL2Bus.trans_dist::Writeback 2214381 # Transaction distribution 3151system.toL2Bus.trans_dist::WriteInvalidateReq 919435 # Transaction distribution 3152system.toL2Bus.trans_dist::WriteInvalidateResp 812281 # Transaction distribution 3153system.toL2Bus.trans_dist::UpgradeReq 489803 # Transaction distribution 3154system.toL2Bus.trans_dist::SCUpgradeReq 302708 # Transaction distribution 3155system.toL2Bus.trans_dist::UpgradeResp 792511 # Transaction distribution 3156system.toL2Bus.trans_dist::SCUpgradeFailReq 125 # Transaction distribution 3157system.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution 3158system.toL2Bus.trans_dist::ReadExReq 280473 # Transaction distribution 3159system.toL2Bus.trans_dist::ReadExResp 280473 # Transaction distribution 3160system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7857713 # Packet count per connected master and slave (bytes) 3161system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6052239 # Packet count per connected master and slave (bytes) 3162system.toL2Bus.pkt_count::total 13909952 # Packet count per connected master and slave (bytes) 3163system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 261128039 # Cumulative packet size per connected master and slave (bytes) 3164system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 189974361 # Cumulative packet size per connected master and slave (bytes) 3165system.toL2Bus.pkt_size::total 451102400 # Cumulative packet size per connected master and slave (bytes) 3166system.toL2Bus.snoops 1657293 # Total snoops (count) 3167system.toL2Bus.snoop_fanout::samples 8947338 # Request fanout histogram 3168system.toL2Bus.snoop_fanout::mean 1.012974 # Request fanout histogram 3169system.toL2Bus.snoop_fanout::stdev 0.113161 # Request fanout histogram |
| 3127system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3128system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 3170system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3171system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 3129system.toL2Bus.snoop_fanout::1 9175099 98.75% 98.75% # Request fanout histogram 3130system.toL2Bus.snoop_fanout::2 116074 1.25% 100.00% # Request fanout histogram | 3172system.toL2Bus.snoop_fanout::1 8831258 98.70% 98.70% # Request fanout histogram 3173system.toL2Bus.snoop_fanout::2 116080 1.30% 100.00% # Request fanout histogram |
| 3131system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3132system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 3133system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 3174system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3175system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 3176system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 3134system.toL2Bus.snoop_fanout::total 9291173 # Request fanout histogram 3135system.toL2Bus.reqLayer0.occupancy 8184497542 # Layer occupancy (ticks) | 3177system.toL2Bus.snoop_fanout::total 8947338 # Request fanout histogram 3178system.toL2Bus.reqLayer0.occupancy 7728831785 # Layer occupancy (ticks) |
| 3136system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) | 3179system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 3137system.toL2Bus.snoopLayer0.occupancy 2554500 # Layer occupancy (ticks) | 3180system.toL2Bus.snoopLayer0.occupancy 2539500 # Layer occupancy (ticks) |
| 3138system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 3181system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 3139system.toL2Bus.respLayer0.occupancy 4445775595 # Layer occupancy (ticks) | 3182system.toL2Bus.respLayer0.occupancy 4493592227 # Layer occupancy (ticks) |
| 3140system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 3183system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 3141system.toL2Bus.respLayer1.occupancy 4394903352 # Layer occupancy (ticks) | 3184system.toL2Bus.respLayer1.occupancy 3891101888 # Layer occupancy (ticks) |
| 3142system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3143 3144---------- End Simulation Statistics ---------- | 3185system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3186 3187---------- End Simulation Statistics ---------- |