7,11c7,11
< host_inst_rate 225035 # Simulator instruction rate (inst/s)
< host_op_rate 264677 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 11911388135 # Simulator tick rate (ticks/s)
< host_mem_usage 769700 # Number of bytes of host memory used
< host_seconds 3990.80 # Real time elapsed on the host
---
> host_inst_rate 200561 # Simulator instruction rate (inst/s)
> host_op_rate 235891 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 10615931561 # Simulator tick rate (ticks/s)
> host_mem_usage 769436 # Number of bytes of host memory used
> host_seconds 4477.79 # Real time elapsed on the host
650,653c650,653
< system.cpu0.dcache.demand_hits::cpu0.data 164286110 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 164286110 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 164591140 # number of overall hits
< system.cpu0.dcache.overall_hits::total 164591140 # number of overall hits
---
> system.cpu0.dcache.demand_hits::cpu0.data 164573170 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 164573170 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 164878200 # number of overall hits
> system.cpu0.dcache.overall_hits::total 164878200 # number of overall hits
666,669c666,669
< system.cpu0.dcache.demand_misses::cpu0.data 6153573 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 6153573 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 6815315 # number of overall misses
< system.cpu0.dcache.overall_misses::total 6815315 # number of overall misses
---
> system.cpu0.dcache.demand_misses::cpu0.data 7001465 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 7001465 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 7663207 # number of overall misses
> system.cpu0.dcache.overall_misses::total 7663207 # number of overall misses
682,685c682,685
< system.cpu0.dcache.demand_miss_latency::cpu0.data 126172350500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 126172350500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 126172350500 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 126172350500 # number of overall miss cycles
---
> system.cpu0.dcache.demand_miss_latency::cpu0.data 177339794500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 177339794500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 177339794500 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 177339794500 # number of overall miss cycles
698,701c698,701
< system.cpu0.dcache.demand_accesses::cpu0.data 170439683 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 170439683 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 171406455 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 171406455 # number of overall (read+write) accesses
---
> system.cpu0.dcache.demand_accesses::cpu0.data 171574635 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 171574635 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 172541407 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 172541407 # number of overall (read+write) accesses
714,717c714,717
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036104 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.036104 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039761 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.039761 # miss rate for overall accesses
---
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.040807 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.040807 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.044414 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.044414 # miss rate for overall accesses
730,733c730,733
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20503.917074 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 20503.917074 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18513.062199 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 18513.062199 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25328.955369 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 25328.955369 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23141.720496 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 23141.720496 # average overall miss latency
740,741d739
< system.cpu0.dcache.fast_writes 0 # number of fast writes performed
< system.cpu0.dcache.cache_copies 0 # number of cache copies performed
754,757c752,755
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 1457263 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 1457263 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 1457263 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 1457263 # number of overall MSHR hits
---
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 1457353 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 1457353 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 1457353 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 1457353 # number of overall MSHR hits
770,773c768,771
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 4696310 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 4696310 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 5356480 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 5356480 # number of overall MSHR misses
---
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 5544112 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 5544112 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 6204282 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 6204282 # number of overall MSHR misses
794,797c792,795
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 87107602500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 87107602500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103687036000 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 103687036000 # number of overall MSHR miss cycles
---
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 137418972500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 137418972500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 153998406000 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 153998406000 # number of overall MSHR miss cycles
800,803c798,799
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5837295500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5837295500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11878686500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11878686500 # number of overall MSHR uncacheable cycles
---
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6041391000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6041391000 # number of overall MSHR uncacheable cycles
816,819c812,815
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027554 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.027554 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031250 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.031250 # mshr miss rate for overall accesses
---
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032313 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.032313 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.035958 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.035958 # mshr miss rate for overall accesses
834,837c830,833
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18548.094674 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18548.094674 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19357.308531 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19357.308531 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24786.471215 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24786.471215 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24821.309863 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24821.309863 # average overall mshr miss latency
840,844c836,837
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187405.146398 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187405.146398 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189452.735247 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 189452.735247 # average overall mshr uncacheable latency
< system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96353.923445 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96353.923445 # average overall mshr uncacheable latency
903,904d895
< system.cpu0.icache.fast_writes 0 # number of fast writes performed
< system.cpu0.icache.cache_copies 0 # number of cache copies performed
943d933
< system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1161,1162d1150
< system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1258,1259d1245
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5603650500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5603650500 # number of WriteReq MSHR uncacheable cycles
1261,1262c1247,1248
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11392447500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 18388602500 # number of overall MSHR uncacheable cycles
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5788797000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12784952000 # number of overall MSHR uncacheable cycles
1328,1329d1313
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179904.022730 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 179904.022730 # average WriteReq mshr uncacheable latency
1331,1333c1315,1316
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181697.727273 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 159888.378301 # average overall mshr uncacheable latency
< system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92325.311005 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 111164.795799 # average overall mshr uncacheable latency
1656,1659c1639,1642
< system.cpu1.dcache.demand_hits::cpu1.data 139703423 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 139703423 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 139904287 # number of overall hits
< system.cpu1.dcache.overall_hits::total 139904287 # number of overall hits
---
> system.cpu1.dcache.demand_hits::cpu1.data 139737373 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 139737373 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 139938237 # number of overall hits
> system.cpu1.dcache.overall_hits::total 139938237 # number of overall hits
1672,1675c1655,1658
< system.cpu1.dcache.demand_misses::cpu1.data 5471070 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 5471070 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 6120062 # number of overall misses
< system.cpu1.dcache.overall_misses::total 6120062 # number of overall misses
---
> system.cpu1.dcache.demand_misses::cpu1.data 5881027 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 5881027 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 6530019 # number of overall misses
> system.cpu1.dcache.overall_misses::total 6530019 # number of overall misses
1688,1691c1671,1674
< system.cpu1.dcache.demand_miss_latency::cpu1.data 103432662000 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 103432662000 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 103432662000 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 103432662000 # number of overall miss cycles
---
> system.cpu1.dcache.demand_miss_latency::cpu1.data 118332403000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 118332403000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 118332403000 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 118332403000 # number of overall miss cycles
1704,1707c1687,1690
< system.cpu1.dcache.demand_accesses::cpu1.data 145174493 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 145174493 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 146024349 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 146024349 # number of overall (read+write) accesses
---
> system.cpu1.dcache.demand_accesses::cpu1.data 145618400 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 145618400 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 146468256 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 146468256 # number of overall (read+write) accesses
1720,1723c1703,1706
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.037686 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.037686 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041911 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.041911 # miss rate for overall accesses
---
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040387 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.040387 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044583 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.044583 # miss rate for overall accesses
1736,1739c1719,1722
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18905.380849 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 18905.380849 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16900.590550 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 16900.590550 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20121.043995 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 20121.043995 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18121.295359 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 18121.295359 # average overall miss latency
1746,1747d1728
< system.cpu1.dcache.fast_writes 0 # number of fast writes performed
< system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1760,1763c1741,1744
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 1310532 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 1310532 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 1310532 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 1310532 # number of overall MSHR hits
---
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 1310590 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 1310590 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 1310590 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 1310590 # number of overall MSHR hits
1776,1779c1757,1760
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 4160538 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 4160538 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 4809167 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 4809167 # number of overall MSHR misses
---
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 4570437 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 4570437 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 5219066 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 5219066 # number of overall MSHR misses
1800,1803c1781,1784
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 71363385000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 71363385000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87278174000 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 87278174000 # number of overall MSHR miss cycles
---
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 85847670500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 85847670500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101762459500 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 101762459500 # number of overall MSHR miss cycles
1806,1809c1787,1788
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1094820000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1094820000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2014553500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2014553500 # number of overall MSHR uncacheable cycles
---
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 919733500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 919733500 # number of overall MSHR uncacheable cycles
1822,1825c1801,1804
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028659 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.028659 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032934 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.032934 # mshr miss rate for overall accesses
---
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031386 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.031386 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035633 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.035633 # mshr miss rate for overall accesses
1840,1843c1819,1822
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17152.441583 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17152.441583 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18148.293457 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18148.293457 # average overall mshr miss latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18783.252127 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18783.252127 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19498.212803 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19498.212803 # average overall mshr miss latency
1846,1850c1825,1826
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143282.292894 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 143282.292894 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134500.834557 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134500.834557 # average overall mshr uncacheable latency
< system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 61405.628255 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 61405.628255 # average overall mshr uncacheable latency
1909,1910d1884
< system.cpu1.icache.fast_writes 0 # number of fast writes performed
< system.cpu1.icache.cache_copies 0 # number of cache copies performed
1949d1922
< system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2165,2166d2137
< system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2259,2260d2229
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1037437000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1037437000 # number of WriteReq MSHR uncacheable cycles
2262,2263c2231,2232
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1898368500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1910642500 # number of overall MSHR uncacheable cycles
---
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 860931500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 873205500 # number of overall MSHR uncacheable cycles
2327,2328d2295
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 135772.411988 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 135772.411988 # average WriteReq mshr uncacheable latency
2330,2332c2297,2298
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126743.790893 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126776.093159 # average overall mshr uncacheable latency
< system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 57479.736948 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 57939.453255 # average overall mshr uncacheable latency
2494,2495c2460,2461
< system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8917 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 115861 # number of demand (read+write) misses
> system.iocache.demand_misses::total 115901 # number of demand (read+write) misses
2497,2498c2463,2464
< system.iocache.overall_misses::realview.ide 8877 # number of overall misses
< system.iocache.overall_misses::total 8917 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 115861 # number of overall misses
> system.iocache.overall_misses::total 115901 # number of overall misses
2507,2508c2473,2474
< system.iocache.demand_miss_latency::realview.ide 1651659585 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1657228085 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 15215599886 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 15221168386 # number of demand (read+write) miss cycles
2510,2511c2476,2477
< system.iocache.overall_miss_latency::realview.ide 1651659585 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1657228085 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 15215599886 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 15221168386 # number of overall miss cycles
2520,2521c2486,2487
< system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 115861 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 115901 # number of demand (read+write) accesses
2523,2524c2489,2490
< system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 115861 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 115901 # number of overall (read+write) accesses
2546,2547c2512,2513
< system.iocache.demand_avg_miss_latency::realview.ide 186060.559311 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 185850.407648 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 131326.329705 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 131329.051397 # average overall miss latency
2549,2550c2515,2516
< system.iocache.overall_avg_miss_latency::realview.ide 186060.559311 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 185850.407648 # average overall miss latency
---
> system.iocache.overall_avg_miss_latency::realview.ide 131326.329705 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 131329.051397 # average overall miss latency
2557,2558d2522
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
2569,2570c2533,2534
< system.iocache.demand_mshr_misses::realview.ide 8877 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8917 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 115861 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 115901 # number of demand (read+write) MSHR misses
2572,2573c2536,2537
< system.iocache.overall_mshr_misses::realview.ide 8877 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8917 # number of overall MSHR misses
---
> system.iocache.overall_mshr_misses::realview.ide 115861 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 115901 # number of overall MSHR misses
2582,2583c2546,2547
< system.iocache.demand_mshr_miss_latency::realview.ide 1207809585 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1211378085 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 9416301443 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 9419869943 # number of demand (read+write) MSHR miss cycles
2585,2586c2549,2550
< system.iocache.overall_mshr_miss_latency::realview.ide 1207809585 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1211378085 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 9416301443 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 9419869943 # number of overall MSHR miss cycles
2608,2609c2572,2573
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 136060.559311 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 135850.407648 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 81272.399194 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 81275.139498 # average overall mshr miss latency
2611,2613c2575,2576
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 136060.559311 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 135850.407648 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 81272.399194 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 81275.139498 # average overall mshr miss latency
2942,2943d2904
< system.l2c.fast_writes 0 # number of fast writes performed
< system.l2c.cache_copies 0 # number of cache copies performed
3074,3076d3034
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 5073884538 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 907395547 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 5981280085 # number of WriteReq MSHR uncacheable cycles
3078c3036
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10294572591 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5220688053 # number of overall MSHR uncacheable cycles
3080,3081c3038,3039
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1636129564 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 17838688655 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 728734017 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 11857408570 # number of overall MSHR uncacheable cycles
3179,3181d3136
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162895.997753 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 118753.507002 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154200.419836 # average WriteReq mshr uncacheable latency
3183c3138
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164187.760622 # average overall mshr uncacheable latency
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83264.562249 # average overall mshr uncacheable latency
3185,3187c3140,3141
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109250.104434 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 137138.398922 # average overall mshr uncacheable latency
< system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 48660.123998 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 91156.141469 # average overall mshr uncacheable latency
< host_inst_rate 225035 # Simulator instruction rate (inst/s)
< host_op_rate 264677 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 11911388135 # Simulator tick rate (ticks/s)
< host_mem_usage 769700 # Number of bytes of host memory used
< host_seconds 3990.80 # Real time elapsed on the host
---
> host_inst_rate 200561 # Simulator instruction rate (inst/s)
> host_op_rate 235891 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 10615931561 # Simulator tick rate (ticks/s)
> host_mem_usage 769436 # Number of bytes of host memory used
> host_seconds 4477.79 # Real time elapsed on the host
650,653c650,653
< system.cpu0.dcache.demand_hits::cpu0.data 164286110 # number of demand (read+write) hits
< system.cpu0.dcache.demand_hits::total 164286110 # number of demand (read+write) hits
< system.cpu0.dcache.overall_hits::cpu0.data 164591140 # number of overall hits
< system.cpu0.dcache.overall_hits::total 164591140 # number of overall hits
---
> system.cpu0.dcache.demand_hits::cpu0.data 164573170 # number of demand (read+write) hits
> system.cpu0.dcache.demand_hits::total 164573170 # number of demand (read+write) hits
> system.cpu0.dcache.overall_hits::cpu0.data 164878200 # number of overall hits
> system.cpu0.dcache.overall_hits::total 164878200 # number of overall hits
666,669c666,669
< system.cpu0.dcache.demand_misses::cpu0.data 6153573 # number of demand (read+write) misses
< system.cpu0.dcache.demand_misses::total 6153573 # number of demand (read+write) misses
< system.cpu0.dcache.overall_misses::cpu0.data 6815315 # number of overall misses
< system.cpu0.dcache.overall_misses::total 6815315 # number of overall misses
---
> system.cpu0.dcache.demand_misses::cpu0.data 7001465 # number of demand (read+write) misses
> system.cpu0.dcache.demand_misses::total 7001465 # number of demand (read+write) misses
> system.cpu0.dcache.overall_misses::cpu0.data 7663207 # number of overall misses
> system.cpu0.dcache.overall_misses::total 7663207 # number of overall misses
682,685c682,685
< system.cpu0.dcache.demand_miss_latency::cpu0.data 126172350500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.demand_miss_latency::total 126172350500 # number of demand (read+write) miss cycles
< system.cpu0.dcache.overall_miss_latency::cpu0.data 126172350500 # number of overall miss cycles
< system.cpu0.dcache.overall_miss_latency::total 126172350500 # number of overall miss cycles
---
> system.cpu0.dcache.demand_miss_latency::cpu0.data 177339794500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.demand_miss_latency::total 177339794500 # number of demand (read+write) miss cycles
> system.cpu0.dcache.overall_miss_latency::cpu0.data 177339794500 # number of overall miss cycles
> system.cpu0.dcache.overall_miss_latency::total 177339794500 # number of overall miss cycles
698,701c698,701
< system.cpu0.dcache.demand_accesses::cpu0.data 170439683 # number of demand (read+write) accesses
< system.cpu0.dcache.demand_accesses::total 170439683 # number of demand (read+write) accesses
< system.cpu0.dcache.overall_accesses::cpu0.data 171406455 # number of overall (read+write) accesses
< system.cpu0.dcache.overall_accesses::total 171406455 # number of overall (read+write) accesses
---
> system.cpu0.dcache.demand_accesses::cpu0.data 171574635 # number of demand (read+write) accesses
> system.cpu0.dcache.demand_accesses::total 171574635 # number of demand (read+write) accesses
> system.cpu0.dcache.overall_accesses::cpu0.data 172541407 # number of overall (read+write) accesses
> system.cpu0.dcache.overall_accesses::total 172541407 # number of overall (read+write) accesses
714,717c714,717
< system.cpu0.dcache.demand_miss_rate::cpu0.data 0.036104 # miss rate for demand accesses
< system.cpu0.dcache.demand_miss_rate::total 0.036104 # miss rate for demand accesses
< system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039761 # miss rate for overall accesses
< system.cpu0.dcache.overall_miss_rate::total 0.039761 # miss rate for overall accesses
---
> system.cpu0.dcache.demand_miss_rate::cpu0.data 0.040807 # miss rate for demand accesses
> system.cpu0.dcache.demand_miss_rate::total 0.040807 # miss rate for demand accesses
> system.cpu0.dcache.overall_miss_rate::cpu0.data 0.044414 # miss rate for overall accesses
> system.cpu0.dcache.overall_miss_rate::total 0.044414 # miss rate for overall accesses
730,733c730,733
< system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20503.917074 # average overall miss latency
< system.cpu0.dcache.demand_avg_miss_latency::total 20503.917074 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18513.062199 # average overall miss latency
< system.cpu0.dcache.overall_avg_miss_latency::total 18513.062199 # average overall miss latency
---
> system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25328.955369 # average overall miss latency
> system.cpu0.dcache.demand_avg_miss_latency::total 25328.955369 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23141.720496 # average overall miss latency
> system.cpu0.dcache.overall_avg_miss_latency::total 23141.720496 # average overall miss latency
740,741d739
< system.cpu0.dcache.fast_writes 0 # number of fast writes performed
< system.cpu0.dcache.cache_copies 0 # number of cache copies performed
754,757c752,755
< system.cpu0.dcache.demand_mshr_hits::cpu0.data 1457263 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.demand_mshr_hits::total 1457263 # number of demand (read+write) MSHR hits
< system.cpu0.dcache.overall_mshr_hits::cpu0.data 1457263 # number of overall MSHR hits
< system.cpu0.dcache.overall_mshr_hits::total 1457263 # number of overall MSHR hits
---
> system.cpu0.dcache.demand_mshr_hits::cpu0.data 1457353 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.demand_mshr_hits::total 1457353 # number of demand (read+write) MSHR hits
> system.cpu0.dcache.overall_mshr_hits::cpu0.data 1457353 # number of overall MSHR hits
> system.cpu0.dcache.overall_mshr_hits::total 1457353 # number of overall MSHR hits
770,773c768,771
< system.cpu0.dcache.demand_mshr_misses::cpu0.data 4696310 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.demand_mshr_misses::total 4696310 # number of demand (read+write) MSHR misses
< system.cpu0.dcache.overall_mshr_misses::cpu0.data 5356480 # number of overall MSHR misses
< system.cpu0.dcache.overall_mshr_misses::total 5356480 # number of overall MSHR misses
---
> system.cpu0.dcache.demand_mshr_misses::cpu0.data 5544112 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.demand_mshr_misses::total 5544112 # number of demand (read+write) MSHR misses
> system.cpu0.dcache.overall_mshr_misses::cpu0.data 6204282 # number of overall MSHR misses
> system.cpu0.dcache.overall_mshr_misses::total 6204282 # number of overall MSHR misses
794,797c792,795
< system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 87107602500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.demand_mshr_miss_latency::total 87107602500 # number of demand (read+write) MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 103687036000 # number of overall MSHR miss cycles
< system.cpu0.dcache.overall_mshr_miss_latency::total 103687036000 # number of overall MSHR miss cycles
---
> system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 137418972500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.demand_mshr_miss_latency::total 137418972500 # number of demand (read+write) MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 153998406000 # number of overall MSHR miss cycles
> system.cpu0.dcache.overall_mshr_miss_latency::total 153998406000 # number of overall MSHR miss cycles
800,803c798,799
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5837295500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5837295500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11878686500 # number of overall MSHR uncacheable cycles
< system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11878686500 # number of overall MSHR uncacheable cycles
---
> system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6041391000 # number of overall MSHR uncacheable cycles
> system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6041391000 # number of overall MSHR uncacheable cycles
816,819c812,815
< system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027554 # mshr miss rate for demand accesses
< system.cpu0.dcache.demand_mshr_miss_rate::total 0.027554 # mshr miss rate for demand accesses
< system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031250 # mshr miss rate for overall accesses
< system.cpu0.dcache.overall_mshr_miss_rate::total 0.031250 # mshr miss rate for overall accesses
---
> system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032313 # mshr miss rate for demand accesses
> system.cpu0.dcache.demand_mshr_miss_rate::total 0.032313 # mshr miss rate for demand accesses
> system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.035958 # mshr miss rate for overall accesses
> system.cpu0.dcache.overall_mshr_miss_rate::total 0.035958 # mshr miss rate for overall accesses
834,837c830,833
< system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18548.094674 # average overall mshr miss latency
< system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18548.094674 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19357.308531 # average overall mshr miss latency
< system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19357.308531 # average overall mshr miss latency
---
> system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24786.471215 # average overall mshr miss latency
> system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24786.471215 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24821.309863 # average overall mshr miss latency
> system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24821.309863 # average overall mshr miss latency
840,844c836,837
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 187405.146398 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 187405.146398 # average WriteReq mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 189452.735247 # average overall mshr uncacheable latency
< system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 189452.735247 # average overall mshr uncacheable latency
< system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 96353.923445 # average overall mshr uncacheable latency
> system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 96353.923445 # average overall mshr uncacheable latency
903,904d895
< system.cpu0.icache.fast_writes 0 # number of fast writes performed
< system.cpu0.icache.cache_copies 0 # number of cache copies performed
943d933
< system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
1161,1162d1150
< system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
1258,1259d1245
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5603650500 # number of WriteReq MSHR uncacheable cycles
< system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5603650500 # number of WriteReq MSHR uncacheable cycles
1261,1262c1247,1248
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11392447500 # number of overall MSHR uncacheable cycles
< system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 18388602500 # number of overall MSHR uncacheable cycles
---
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5788797000 # number of overall MSHR uncacheable cycles
> system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12784952000 # number of overall MSHR uncacheable cycles
1328,1329d1313
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 179904.022730 # average WriteReq mshr uncacheable latency
< system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 179904.022730 # average WriteReq mshr uncacheable latency
1331,1333c1315,1316
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 181697.727273 # average overall mshr uncacheable latency
< system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 159888.378301 # average overall mshr uncacheable latency
< system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 92325.311005 # average overall mshr uncacheable latency
> system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 111164.795799 # average overall mshr uncacheable latency
1656,1659c1639,1642
< system.cpu1.dcache.demand_hits::cpu1.data 139703423 # number of demand (read+write) hits
< system.cpu1.dcache.demand_hits::total 139703423 # number of demand (read+write) hits
< system.cpu1.dcache.overall_hits::cpu1.data 139904287 # number of overall hits
< system.cpu1.dcache.overall_hits::total 139904287 # number of overall hits
---
> system.cpu1.dcache.demand_hits::cpu1.data 139737373 # number of demand (read+write) hits
> system.cpu1.dcache.demand_hits::total 139737373 # number of demand (read+write) hits
> system.cpu1.dcache.overall_hits::cpu1.data 139938237 # number of overall hits
> system.cpu1.dcache.overall_hits::total 139938237 # number of overall hits
1672,1675c1655,1658
< system.cpu1.dcache.demand_misses::cpu1.data 5471070 # number of demand (read+write) misses
< system.cpu1.dcache.demand_misses::total 5471070 # number of demand (read+write) misses
< system.cpu1.dcache.overall_misses::cpu1.data 6120062 # number of overall misses
< system.cpu1.dcache.overall_misses::total 6120062 # number of overall misses
---
> system.cpu1.dcache.demand_misses::cpu1.data 5881027 # number of demand (read+write) misses
> system.cpu1.dcache.demand_misses::total 5881027 # number of demand (read+write) misses
> system.cpu1.dcache.overall_misses::cpu1.data 6530019 # number of overall misses
> system.cpu1.dcache.overall_misses::total 6530019 # number of overall misses
1688,1691c1671,1674
< system.cpu1.dcache.demand_miss_latency::cpu1.data 103432662000 # number of demand (read+write) miss cycles
< system.cpu1.dcache.demand_miss_latency::total 103432662000 # number of demand (read+write) miss cycles
< system.cpu1.dcache.overall_miss_latency::cpu1.data 103432662000 # number of overall miss cycles
< system.cpu1.dcache.overall_miss_latency::total 103432662000 # number of overall miss cycles
---
> system.cpu1.dcache.demand_miss_latency::cpu1.data 118332403000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.demand_miss_latency::total 118332403000 # number of demand (read+write) miss cycles
> system.cpu1.dcache.overall_miss_latency::cpu1.data 118332403000 # number of overall miss cycles
> system.cpu1.dcache.overall_miss_latency::total 118332403000 # number of overall miss cycles
1704,1707c1687,1690
< system.cpu1.dcache.demand_accesses::cpu1.data 145174493 # number of demand (read+write) accesses
< system.cpu1.dcache.demand_accesses::total 145174493 # number of demand (read+write) accesses
< system.cpu1.dcache.overall_accesses::cpu1.data 146024349 # number of overall (read+write) accesses
< system.cpu1.dcache.overall_accesses::total 146024349 # number of overall (read+write) accesses
---
> system.cpu1.dcache.demand_accesses::cpu1.data 145618400 # number of demand (read+write) accesses
> system.cpu1.dcache.demand_accesses::total 145618400 # number of demand (read+write) accesses
> system.cpu1.dcache.overall_accesses::cpu1.data 146468256 # number of overall (read+write) accesses
> system.cpu1.dcache.overall_accesses::total 146468256 # number of overall (read+write) accesses
1720,1723c1703,1706
< system.cpu1.dcache.demand_miss_rate::cpu1.data 0.037686 # miss rate for demand accesses
< system.cpu1.dcache.demand_miss_rate::total 0.037686 # miss rate for demand accesses
< system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041911 # miss rate for overall accesses
< system.cpu1.dcache.overall_miss_rate::total 0.041911 # miss rate for overall accesses
---
> system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040387 # miss rate for demand accesses
> system.cpu1.dcache.demand_miss_rate::total 0.040387 # miss rate for demand accesses
> system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044583 # miss rate for overall accesses
> system.cpu1.dcache.overall_miss_rate::total 0.044583 # miss rate for overall accesses
1736,1739c1719,1722
< system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18905.380849 # average overall miss latency
< system.cpu1.dcache.demand_avg_miss_latency::total 18905.380849 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16900.590550 # average overall miss latency
< system.cpu1.dcache.overall_avg_miss_latency::total 16900.590550 # average overall miss latency
---
> system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20121.043995 # average overall miss latency
> system.cpu1.dcache.demand_avg_miss_latency::total 20121.043995 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18121.295359 # average overall miss latency
> system.cpu1.dcache.overall_avg_miss_latency::total 18121.295359 # average overall miss latency
1746,1747d1728
< system.cpu1.dcache.fast_writes 0 # number of fast writes performed
< system.cpu1.dcache.cache_copies 0 # number of cache copies performed
1760,1763c1741,1744
< system.cpu1.dcache.demand_mshr_hits::cpu1.data 1310532 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.demand_mshr_hits::total 1310532 # number of demand (read+write) MSHR hits
< system.cpu1.dcache.overall_mshr_hits::cpu1.data 1310532 # number of overall MSHR hits
< system.cpu1.dcache.overall_mshr_hits::total 1310532 # number of overall MSHR hits
---
> system.cpu1.dcache.demand_mshr_hits::cpu1.data 1310590 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.demand_mshr_hits::total 1310590 # number of demand (read+write) MSHR hits
> system.cpu1.dcache.overall_mshr_hits::cpu1.data 1310590 # number of overall MSHR hits
> system.cpu1.dcache.overall_mshr_hits::total 1310590 # number of overall MSHR hits
1776,1779c1757,1760
< system.cpu1.dcache.demand_mshr_misses::cpu1.data 4160538 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.demand_mshr_misses::total 4160538 # number of demand (read+write) MSHR misses
< system.cpu1.dcache.overall_mshr_misses::cpu1.data 4809167 # number of overall MSHR misses
< system.cpu1.dcache.overall_mshr_misses::total 4809167 # number of overall MSHR misses
---
> system.cpu1.dcache.demand_mshr_misses::cpu1.data 4570437 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.demand_mshr_misses::total 4570437 # number of demand (read+write) MSHR misses
> system.cpu1.dcache.overall_mshr_misses::cpu1.data 5219066 # number of overall MSHR misses
> system.cpu1.dcache.overall_mshr_misses::total 5219066 # number of overall MSHR misses
1800,1803c1781,1784
< system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 71363385000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.demand_mshr_miss_latency::total 71363385000 # number of demand (read+write) MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 87278174000 # number of overall MSHR miss cycles
< system.cpu1.dcache.overall_mshr_miss_latency::total 87278174000 # number of overall MSHR miss cycles
---
> system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 85847670500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.demand_mshr_miss_latency::total 85847670500 # number of demand (read+write) MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 101762459500 # number of overall MSHR miss cycles
> system.cpu1.dcache.overall_mshr_miss_latency::total 101762459500 # number of overall MSHR miss cycles
1806,1809c1787,1788
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1094820000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1094820000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2014553500 # number of overall MSHR uncacheable cycles
< system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2014553500 # number of overall MSHR uncacheable cycles
---
> system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 919733500 # number of overall MSHR uncacheable cycles
> system.cpu1.dcache.overall_mshr_uncacheable_latency::total 919733500 # number of overall MSHR uncacheable cycles
1822,1825c1801,1804
< system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028659 # mshr miss rate for demand accesses
< system.cpu1.dcache.demand_mshr_miss_rate::total 0.028659 # mshr miss rate for demand accesses
< system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032934 # mshr miss rate for overall accesses
< system.cpu1.dcache.overall_mshr_miss_rate::total 0.032934 # mshr miss rate for overall accesses
---
> system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031386 # mshr miss rate for demand accesses
> system.cpu1.dcache.demand_mshr_miss_rate::total 0.031386 # mshr miss rate for demand accesses
> system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035633 # mshr miss rate for overall accesses
> system.cpu1.dcache.overall_mshr_miss_rate::total 0.035633 # mshr miss rate for overall accesses
1840,1843c1819,1822
< system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17152.441583 # average overall mshr miss latency
< system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17152.441583 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18148.293457 # average overall mshr miss latency
< system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18148.293457 # average overall mshr miss latency
---
> system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18783.252127 # average overall mshr miss latency
> system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18783.252127 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19498.212803 # average overall mshr miss latency
> system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19498.212803 # average overall mshr miss latency
1846,1850c1825,1826
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143282.292894 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 143282.292894 # average WriteReq mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134500.834557 # average overall mshr uncacheable latency
< system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134500.834557 # average overall mshr uncacheable latency
< system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 61405.628255 # average overall mshr uncacheable latency
> system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 61405.628255 # average overall mshr uncacheable latency
1909,1910d1884
< system.cpu1.icache.fast_writes 0 # number of fast writes performed
< system.cpu1.icache.cache_copies 0 # number of cache copies performed
1949d1922
< system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
2165,2166d2137
< system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
2259,2260d2229
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1037437000 # number of WriteReq MSHR uncacheable cycles
< system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1037437000 # number of WriteReq MSHR uncacheable cycles
2262,2263c2231,2232
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1898368500 # number of overall MSHR uncacheable cycles
< system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1910642500 # number of overall MSHR uncacheable cycles
---
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 860931500 # number of overall MSHR uncacheable cycles
> system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 873205500 # number of overall MSHR uncacheable cycles
2327,2328d2295
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 135772.411988 # average WriteReq mshr uncacheable latency
< system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 135772.411988 # average WriteReq mshr uncacheable latency
2330,2332c2297,2298
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126743.790893 # average overall mshr uncacheable latency
< system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126776.093159 # average overall mshr uncacheable latency
< system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 57479.736948 # average overall mshr uncacheable latency
> system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 57939.453255 # average overall mshr uncacheable latency
2494,2495c2460,2461
< system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses
< system.iocache.demand_misses::total 8917 # number of demand (read+write) misses
---
> system.iocache.demand_misses::realview.ide 115861 # number of demand (read+write) misses
> system.iocache.demand_misses::total 115901 # number of demand (read+write) misses
2497,2498c2463,2464
< system.iocache.overall_misses::realview.ide 8877 # number of overall misses
< system.iocache.overall_misses::total 8917 # number of overall misses
---
> system.iocache.overall_misses::realview.ide 115861 # number of overall misses
> system.iocache.overall_misses::total 115901 # number of overall misses
2507,2508c2473,2474
< system.iocache.demand_miss_latency::realview.ide 1651659585 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 1657228085 # number of demand (read+write) miss cycles
---
> system.iocache.demand_miss_latency::realview.ide 15215599886 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 15221168386 # number of demand (read+write) miss cycles
2510,2511c2476,2477
< system.iocache.overall_miss_latency::realview.ide 1651659585 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 1657228085 # number of overall miss cycles
---
> system.iocache.overall_miss_latency::realview.ide 15215599886 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 15221168386 # number of overall miss cycles
2520,2521c2486,2487
< system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses
---
> system.iocache.demand_accesses::realview.ide 115861 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 115901 # number of demand (read+write) accesses
2523,2524c2489,2490
< system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses
---
> system.iocache.overall_accesses::realview.ide 115861 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 115901 # number of overall (read+write) accesses
2546,2547c2512,2513
< system.iocache.demand_avg_miss_latency::realview.ide 186060.559311 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 185850.407648 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::realview.ide 131326.329705 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 131329.051397 # average overall miss latency
2549,2550c2515,2516
< system.iocache.overall_avg_miss_latency::realview.ide 186060.559311 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 185850.407648 # average overall miss latency
---
> system.iocache.overall_avg_miss_latency::realview.ide 131326.329705 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 131329.051397 # average overall miss latency
2557,2558d2522
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
2569,2570c2533,2534
< system.iocache.demand_mshr_misses::realview.ide 8877 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 8917 # number of demand (read+write) MSHR misses
---
> system.iocache.demand_mshr_misses::realview.ide 115861 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 115901 # number of demand (read+write) MSHR misses
2572,2573c2536,2537
< system.iocache.overall_mshr_misses::realview.ide 8877 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 8917 # number of overall MSHR misses
---
> system.iocache.overall_mshr_misses::realview.ide 115861 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 115901 # number of overall MSHR misses
2582,2583c2546,2547
< system.iocache.demand_mshr_miss_latency::realview.ide 1207809585 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 1211378085 # number of demand (read+write) MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::realview.ide 9416301443 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 9419869943 # number of demand (read+write) MSHR miss cycles
2585,2586c2549,2550
< system.iocache.overall_mshr_miss_latency::realview.ide 1207809585 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 1211378085 # number of overall MSHR miss cycles
---
> system.iocache.overall_mshr_miss_latency::realview.ide 9416301443 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 9419869943 # number of overall MSHR miss cycles
2608,2609c2572,2573
< system.iocache.demand_avg_mshr_miss_latency::realview.ide 136060.559311 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 135850.407648 # average overall mshr miss latency
---
> system.iocache.demand_avg_mshr_miss_latency::realview.ide 81272.399194 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 81275.139498 # average overall mshr miss latency
2611,2613c2575,2576
< system.iocache.overall_avg_mshr_miss_latency::realview.ide 136060.559311 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 135850.407648 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.overall_avg_mshr_miss_latency::realview.ide 81272.399194 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 81275.139498 # average overall mshr miss latency
2942,2943d2904
< system.l2c.fast_writes 0 # number of fast writes performed
< system.l2c.cache_copies 0 # number of cache copies performed
3074,3076d3034
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 5073884538 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 907395547 # number of WriteReq MSHR uncacheable cycles
< system.l2c.WriteReq_mshr_uncacheable_latency::total 5981280085 # number of WriteReq MSHR uncacheable cycles
3078c3036
< system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10294572591 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5220688053 # number of overall MSHR uncacheable cycles
3080,3081c3038,3039
< system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1636129564 # number of overall MSHR uncacheable cycles
< system.l2c.overall_mshr_uncacheable_latency::total 17838688655 # number of overall MSHR uncacheable cycles
---
> system.l2c.overall_mshr_uncacheable_latency::cpu1.data 728734017 # number of overall MSHR uncacheable cycles
> system.l2c.overall_mshr_uncacheable_latency::total 11857408570 # number of overall MSHR uncacheable cycles
3179,3181d3136
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162895.997753 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 118753.507002 # average WriteReq mshr uncacheable latency
< system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 154200.419836 # average WriteReq mshr uncacheable latency
3183c3138
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164187.760622 # average overall mshr uncacheable latency
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 83264.562249 # average overall mshr uncacheable latency
3185,3187c3140,3141
< system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109250.104434 # average overall mshr uncacheable latency
< system.l2c.overall_avg_mshr_uncacheable_latency::total 137138.398922 # average overall mshr uncacheable latency
< system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 48660.123998 # average overall mshr uncacheable latency
> system.l2c.overall_avg_mshr_uncacheable_latency::total 91156.141469 # average overall mshr uncacheable latency